TC358779XBG CMOS Digital Integrated Circuit Silicon Monolithic TC358779XBG Mobile Peripheral Devices TC358779XBG Overview The HDMI-RX to MIPI DSI-TX is a bridge device that converts HDMI(R) stream to MIPI(R) DSI while providing de-interlacing and auto-scaling features. TC358779XBG share the same 80-pin package as that of TC358749XBG. P-VFBGA80-0707-0.65-001 Weight: 77mg (Typ.) Features HDMI-RX Interface HDMI(R) 1.4b - Video Formats Support (Up to 1080P @60fps) RGB, YCbCr444: 24-bpp @60fps YCbCr422 24-bpp @60fps - Audio Supports Internal Audio PLL to track N/CTS value transmitted by the ACR packet. - 3D Support - HDCP1.3 Support (optional) - EDID Support Release A, Revision 1 (Feb 9, 2000) First 128 byte (EDID 1.3 structure) First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D) Embedded 1 K-byte SRAM (EDID_SRAM) - Maximum HDMI(R) clock speed: 165 MHz Does not support Audio Return Path and HDMI(R) Ethernet Channels DSI TX Interface MIPI DSI compliant (Version 1.1 22 November 2011) Supports up to 4 data lanes @1Gbps/lane Supports video data formats - RGB888 or RGB666 I2C Slave Interface Support for normal (100 kHz), fast mode (400 kHz) and ultra-fast mode (2 MHz) Configure all TC358779XBG internal registers Support 2 I2C Slave Addresses (7'h0F & 7'h1F) selected through boot-strap pin (INT) Audio Output Interface Any of the three audio interfaces are available: I2S, TDM or IEC60958 (pins are multiplexed) I2S Audio Interface - Up to 4 data lanes for 8-channel data - Support Master Clock mode only (c) 2014-2017 Toshiba Electronic Devices & Storage Corporation - Support 16, 18, 20 or 24-bit data (depend on HDMI(R) input stream) - Support Left or Right-justify with MSB first - Support 32 bit-wide time-slot only - Output Audio Over Sampling clock (256fs) - Support IEC 60958 & 61937 formats (depending upon HDMI(R) input stream) over I2S - Supports HBR audio stream split across 4 I2S lines if bandwidth higher than 12 MHz TDM (Time Division Multiplexed) Audio Interface - Fixed to 8 channels - Support Master Clock mode only - Support 16, 18, 20 or 24-bit PCM audio data word (depend on HDMI(R) input stream) - Support 32 bit-wide time slot only - Output Audio OverSampling clock (256fs) Digital Audio Interface - Supports 2 channels (any 2 of the total 8) (depend on HDMI(R) input stream) - Support IEC 60958 & 61937 formats (depending upon HDMI(R) input stream) Video Processing Input formats accepted: - RGB or YCbCr422 - Interlaced or Progressive - 2D or 3D Limited to 165 MHz PClk, 640x480, 720x480, 720x576, 1280x720 or 1920x1080 are expected when scalar is used Output formats supported: - RGB888 or RGB666 - Interlaced (in case of no video processing) or Progressive - 2D or 3D - Limited by 4Gbps D-PHY bandwidth, 720x480, 1280x720 or 1920x1080 are expected when scalar is invoked 1 / 18 2017-11-13 Rev. 1.1 TC358779XBG Scaling: - Hardware performs scaling automatically based on input and output frame size HDMI Rx received input frame size and Panel size programmed in registers Can be overwritten by Software if necessary - Horizontal Scaling factors supported: 3-to-2, 1-to-2, 3-to-4, 3-to-8, 9-to-4 and 9-to-16 2-to-3 and 1-to-3 - Vertical Scaling factors supported: 1-to-2, 3-to-2 and 3-to-4 2-to-1 and 3-to-1 2-to-3 and 4-to-9 4-to-5 and 8-to-15 - Special handling of 3D formats FP, SBS & T&B to avoid boundary artifacts. Color Space Conversion - RGB YCbCr - Two sets of coefficients provided - 1 set for each direction - Both color space convertors can be enabled/disabled independent of each other. InfraRed (IR) Support NEC InfraRed protocol. System Internal core has two power domains (VDDC1 and VDDC2) - VDDC1 is "always-on" power domain - VDDC2 can be shut-off during deep sleep mode Power supply inputs Core and MIPI D-PHY: 1.2 V I/O: 1.8 V - 3.3 V HDMI(R): 3.3 V VPLL: 1.2 V 2 / 18 2017-11-13 TC358779XBG Table of content REFERENCES ..................................................................................................................................................... 5 1. Overview .......................................................................................................................................................... 6 2. Features ........................................................................................................................................................... 7 3. External Pins .................................................................................................................................................. 10 3.1. Pin Summary ........................................................................................................................................... 12 3.2. Pin Layout ................................................................................................................................................ 12 4. Major Functional Blocks ................................................................................................................................. 13 5. Package ......................................................................................................................................................... 14 6. Electrical Characteristics ................................................................................................................................ 15 6.1. Absolute Maximum Ratings..................................................................................................................... 15 6.2. Recommended Operating Condition ....................................................................................................... 15 6.3. DC Electrical Specification ...................................................................................................................... 16 7. Revision History ............................................................................................................................................. 17 RESTRICTIONS ON PRODUCT USE............................................................................................................... 18 Table of Figures Figure 1.1 TC358779XBG System Overview ............................................................................................ 6 Figure 3.1 TC358779XBG 80-Pin Layout Package (Top View) .............................................................. 12 Figure 4.1 Block Diagram of TC358779XBG ........................................................................................... 13 List of Tables Table 2-1 Table 3-1 Table 3-2 Table 5-1 Table 7-1 Power Consumption................................................................................................................... 9 TC358779XBG Pin Name........................................................................................................ 10 Pin Count Summary - TC358779XBG .................................................................................... 12 Mechanical Dimension for TC358779XBG .............................................................................. 14 Revision History ....................................................................................................................... 17 3 / 18 2017-11-13 TC358779XBG HDMI is a trademark or registered trademark of HDMI Licensing, LLC in the United States and/or other countries. MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc. 4 / 18 2017-11-13 TC358779XBG REFERENCES 1. 2. 3. 4. 5. 6. 7. MIPI D-PHY, "MIPI_D-PHY_specification_v01-00-00, May 14, 2009" MIPI DSI, "MIPI Alliance Specification for Display Serial Interface (DSI) Version 1.1 Revision 22 Nov 2011" HDMI(R), "High-Definition Multimedia Interface Specification Version 1.4b March 4, 2010" I2C bus specification, version 2.1, January 2000, Philips Semiconductor IEC 60958, Digital Audio Interface, First Edition, 1999 IEC 61937, Digital audio - Interface for non-linear PCM encoded audio bit streams MIPI SlimBus, "MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus (SLIMbus) Version 1.01.01 - 14 July 2008" 5 / 18 2017-11-13 TC358779XBG 1. Overview The HDMI-RX to MIPI DSI-TX is a bridge device that converts HDMI(R) stream to MIPI(R) DSI while providing de-interlacing and auto-scaling features. System Overview block diagrams are shown below. TC358779 XBG share the same 80-pin package as that of TC358749XBG. TC358779XBG INT IR IR REFCLK RESETN STBY DDC_SCL DDC_SDA CEC HPDo SYS DDC Slave CEC HPDi HDCP eFuse Keys Sequencer Authentication Engine IPC HDCP Decryption Engine HDMID0P/N (de-Interlacer) TMDS Rx Video FiFo X YUV -> RGB IEC60958 SLIMbus Figure 1.1 I2C_SDA MicroController DSID1P/N DSID2P/N I2S Audio De-Packet HDMICP/N Scalar I2C_SCL DSID0P/N RegFile & EDID_SRAM DSI Tx RGB > YUV HDMID1P/N HDMID2P/N I2C Slave DSI Packetizer DSID3P/N DSICP/N LCDD Audio APLL I2S_BCLK / SLMB_CLK I2S_LRCLK I2S_DATA_0 / TDM / SLMB_DATA I2S_DATA_1 I2S_DATA_2 I2S_DATA_3/SPDIF TC358779XBG System Overview 6 / 18 2017-11-13 TC358779XBG 2. Features Below are the main features supported by TC358779XBG. HDMI-RX Interface HDMI(R) 1.4b - Video Formats Support (Up to 1080P @60fps) RGB, YCbCr444: 24-bpp @60fps YCbCr422 24-bpp @60fps - Audio Supports Internal Audio PLL to track N/CTS value transmitted by the ACR packet. - 3D Support - HDCP1.3 Support (optional) - EDID Support Release A, Revision 1 (Feb 9, 2000) First 128 byte (EDID 1.3 structure) First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D) Embedded 1K-byte SRAM (EDID_SRAM) - Maximum HDMI(R) clock speed: 165 MHz Does not support Audio Return Path and HDMI(R) Ethernet Channels DSI TX Interface MIPI DSI compliant (Version 1.1 22 November 2011) Supports up to 4 data lanes @1Gbps/lane Supports video data formats - RGB888 or RGB666 I2C Slave Interface Support for normal (100 kHz), fast mode (400 kHz) and ultra-fast mode (2 MHz) Configure all TC358779XBG internal registers Support 2 I2C Slave Addresses (7'h0F & 7'h1F) selected through boot-strap pin (INT) Audio Output Interface Any of the three audio interfaces are available: I2S, TDM or IEC60958 (pins are multiplexed) I2S Audio Interface - Up to 4 data lanes for 8-channel data - Support Master Clock mode only - Support 16, 18, 20 or 24-bit data (depend on HDMI(R) input stream) - Support Left or Right-justify with MSB first - Support 32 bit-wide time-slot only - Output Audio Over Sampling clock (256fs) - Support IEC 60958 & 61937 formats (depending upon HDMI(R) input stream) over I2S - Supports HBR audio stream split across 4 I2S lines if bandwidth higher than 12 MHz 7 / 18 2017-11-13 TC358779XBG TDM (Time Division Multiplexed) Audio Interface - Fixed to 8 channels - Support Master Clock mode only - Support 16, 18, 20 or 24-bit PCM audio data word (depend on HDMI(R) input stream) - Support 32 bit-wide time slot only - Output Audio OverSampling clock (256fs) Digital Audio Interface - Supports 2 channels (any 2 of the total 8) (depend on HDMI(R) input stream) - Support IEC 60958 & 61937 formats (depending upon HDMI(R) input stream) Video Processing Input formats accepted: - RGB or YCbCr422 - Interlaced or Progressive - 2D or 3D - Limited to 165 MHz PClk, 640x480, 720x480, 720x576, 1280x720 or 1920x1080 are expected when scalar is used Output formats supported: - RGB888 or RGB666 - Interlaced (in case of no video processing) or Progressive - 2D or 3D - Limited by 4Gbps D-PHY bandwidth, 720x480, 1280x720 or 1920x1080 are expected when scalar is invoked Scaling: - Hardware performs scaling automatically based on input and output frame size HDMI Rx received input frame size and Panel size programmed in registers Can be overwritten by Software if necessary - Horizontal Scaling factors supported: 3-to-2, 1-to-2, 3-to-4, 3-to-8, 9-to-4 and 9-to-16 2-to-3 and 1-to-3 - Vertical Scaling factors supported: 1-to-2, 3-to-2 and 3-to-4 2-to-1 and 3-to-1 2-to-3 and 4-to-9 4-to-5 and 8-to-15 - Special handling of 3D formats FP, SBS & T&B to avoid boundary artifacts. Color Space Conversion - RGB YCbCr - Two sets of coefficients provided - 1 set for each direction - Both color space convertors can be enabled/disabled independent of each other. 8 / 18 2017-11-13 TC358779XBG InfraRed (IR) Support NEC InfraRed protocol. System Internal core has two power domains (VDDC1 and VDDC2) - VDDC1 is "always-on" power domain - VDDC2 can be shut-off during deep sleep mode Power supply inputs Core and MIPI D-PHY: 1.2 V I/O: 1.8 V - 3.3 V HDMI(R): 3.3 V VPLL: 1.2 V Power Consumption during typical operations at room temperature Table 2-1 1080P @ 60fps 720p 1080p @ 30fps Power Consumption VDDC1 VDDC2 VDDIO1 VDDIO2 VDDMIPI AVDD33 AVDD12 AVDDPLL 1.2V 1.2V 3.3V 1.8V 1.2V 3.3V 1.2V 1.2V Current (mA) 61.13 0.80 0.89 20.50 72.80 67.82 0.01 Power (mW) 73.36 2.64 1.60 24.60 240.24 81.38 0.01 Current (mA) 170.40 0.80 0.89 20.02 72.66 56.67 1.12 Power (mW) 204.48 2.64 1.60 24.02 239.78 68.00 1.34 Total Power (mW) 423.83 541.87 Note: TC358779XBG does not perform YCbCr YUV conversion. In this document YCbCr, HDMI(R) terminology, is used to indicate video color space. 9 / 18 2017-11-13 TC358779XBG 3. External Pins Following table gives the signals of TC358779XBG and their function. Table 3-1 Group System: Reset & Clock (5) DSI TX (10) HDMI RX (8) DDC (2) CEC HPD (2) Audio (7) IR I2C (2) APLL (4) POWER (11) Ground (25) Misc Pin Name RESETN REFCLK I/O Init (O) I I - Type Sch N TC358779XBG Pin Name Function System reset input, active low Reference clock input (27/26MHz or 42MHz range) 0: Normal mode 1: Test mode Standby pin, active low Interrupt Output signal - active high (Level) I2C Slv_Addr_Sel at boot-strap MIPI-DSI clock positive MIPI-DSI clock negative MIPI-DSI Data 0 positive MIPI-DSI Data 0 negative MIPI-DSI Data 1 positive MIPI-DSI Data 1 negative MIPI-DSI Data 2 positive MIPI-DSI Data 2 negative MIPI-DSI Data 3 positive MIPI-DSI Data 3 negative HDMI Clock channel positive HDMI Clock channel negative HDMI Data 0 channel positive HDMI Data 0 channel negative HDMI Data 1 channel positive HDMI Data 1 channel negative HDMI Data 2 channel positive HDMI Data 2 channel negative DDC Slave Clock DDC Slave data CEC signal Hot Plug Detect Input Hot Plug Detect Output I2S/TDM Bit/SLIMbus Clock signal I2S Word Clock or TDM Frame Sync signal I2S (ch. 0,1)/TDM/SLIMbus data signal I2S (ch. 2,3,4,5) data signal I2S (ch. 6,7) data/SPDIF signal Audio Over Sampling Clock InfraRed signal I2C serial clock I2C serial data BIAS signal Audio PLL clock Reference Output clock Audio PLL Reference Input clock Audio PLL Low Pass Filter signal VDD for Internal Core (always ON) (1) VDD for Internal Core (can be powered down) (2) VDDIO1 IO power supply (1) VDDIO2 IO power supply (1) VDD for the MIPI DSI (1) VDD for PLL11 (1) HDMI PHY 1.2V power supply (2) HDMI PHY & APLL 3.3V power supply (2) Note 1.8V -3.3V 1.8V -3.3V TEST I - N STBY I - N INT O L N MIPI_CP MIPI_CN MIPI_D0P MIPI_D0N MIPI_D1P MIPI_D1N MIPI_D2P MIPI_D2N MIPI_D3P MIPI_D3N HDMICP HDMICN HDMID0P HDMID0N HDMID1P HDMID1N HDMID2P HDMID2N DDC_SCL DDC_SDA CEC HPDI HPDO A_SCK A_WFS A_SD[0] A_SD[2:1] A_SD[3] A_OSCK IR I2C_SCL I2C_SDA BIASDA DAOUT PCKIN PFIL VDDC1 VDDC2 VDDIO1 VDDIO2 VDD_MIPI VDD_PLL11 AVDD12 AVDD33 O O O O O O O O O O I I I I I I I I OD OD OD I O O O O O O O I OD OD O O I O - H H H H H H H H H H L L L L LL L L L H L - MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY FS-SOD FS-SOD FS-SOD N N N N N N N N Sch FS-SOD FS-SOD - VSS - - - Ground (25) - REXT(Note2) VPGM(Note3) - - - External Reference Resistor eFuse program power supply - 10 / 18 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V(Note1) 3.3V(Note1) 3.3V 3.3V (Note1) 3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.8V -3.3V 1.2V 1.2V 3.3V 1.8V - 3.3V 1.2V 1.2V 1.2V 3.3V 2017-11-13 TC358779XBG Total 80 pins Note1: These IO are 5 V tolerant. Note2: Please connect REXT to AVDD33 with a 2 k resistor ( 1%) Note3: Please tie to ground Buffer Type Abbreviation: N: Normal IO FS-SOD: Failed Safe Pseudo open-drain output, Schmitt input Sch: Schmitt input buffer MIPI-PHY: front-end analog IO for DSI HDMI-PHY: front-end analog IO for HDMI(R) 11 / 18 2017-11-13 TC358779XBG 3.1. Pin Summary Table 3-2 Pin Count Summary - TC358779XBG Group Name Pin Count SYSTEM DSI TX HDMI RX DDC CEC Audio I2C IR HPD APLL POWER GROUND TOTAL 5 11 13 2 1 7 2 1 2 4 7 25 80 3.2. Pin Layout Top View (through the die) A1 A2 A3 A4 A5 A6 A7 AVDD12 REXT VDDC2 BIASDA DAOUT PFIL VSS B1 B2 B3 B4 B5 B6 B7 B8 AVDD33 VSS VSS VSS VSS VSS PCKIN VSS C1 C2 C3 C4 C5 C6 C7 C8 HDMICP HDMICN D1 D2 D3 HDMID0P HDMID0N E1 E2 E3 HDMID1P HDMID1N F1 F2 F3 HDMID2P HDMID2N G1 G2 AVDD33 VSS H1 H2 AVDD12 CEC J1 J2 G3 H3 DDC_SCL DDC_SDA D4 D5 D6 D7 VSS VSS VSS VSS E4 E5 E6 E7 VSS VSS VSS VSS F4 F5 F6 F7 VSS VSS VSS VSS G4 G5 G6 G7 VPGM TEST VSS VSS H4 H5 H6 H7 A8 A9 A10 VDD_PLL11 MIPI_D3N MIPI_D3P D8 E8 B9 B10 MIPI_D2N MIPI_D2P C9 C10 MIPI_CN MIPI_CP D9 D10 VSS VDD_MIPI E9 E10 MIPI_D1N MIPI_D1P F8 F9 F10 MIPI_D0N MIPI_D0P G8 H8 G9 G10 VSS A_OSCK H9 H10 A_SD_0 A_WFS J3 J4 J5 J6 J7 J8 J9 J10 HPDO INT I2C_SCL IR REFCLK VSS A_SCK A_SD_1 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 VDDC1 VDDIO1 HPDI STBY I2C_SDA RESETN VDDIO2 A_SD_3 A_SD_2 VDDC2 Figure 3.1 TC358779XBG 80-Pin Layout Package (Top View) 12 / 18 2017-11-13 TC358779XBG 4. Major Functional Blocks TC358779XBG consists of the following major blocks: HDMI-RX, DSI Tx, RGB2YCbCr & YCbCr2RGB color convertors, De-Interlacer, Scalar, DDC, CEC, I2S, TDM, IEC60958, INT and I2C i/f. DDC, CEC and I2C slave controller are always enabled which are required for configuring the TC358779XBG chip and to wake up TC358779XBG chip. The following sections describe each block in detail. In addition, there is a section that describes Clock generation block. REFCLK AUDIO Audio Fifo HDMI HDMI-RX (HDCP) RGB -> YCbCr Video Processing Video Fifo IPC (deInterlacer) EDID_SRAM DDC CEC APLL PLL YCbCr -> RGB PLL DSI-TX I2S/TDM/ SPDIF/ SLIMbus BIASDA, PFIL,.... DSI TX Scalar Sequencer DDC (Slave) BM I2C (Slave) CEC_FIFO Regs INT I2C INT CEC IR SYS (CG) IR RESETN, REFCLK Figure 4.1 Block Diagram of TC358779XBG 13 / 18 2017-11-13 TC358779XBG 5. Package TC358779XBG Package (80-pin, P-VFBGA80-0707-0.65-001) Unit: mm Weight: 77mg (Typ.) Table 5-1 Mechanical Dimension for TC358779XBG Dimension Solder ball pitch Package dimension Package height Min - Typ. 0.65 mm 7.0 x 7.0 mm2 - 14 / 18 Max 1.0 mm 2017-11-13 TC358779XBG 6. Electrical Characteristics 6.1. Absolute Maximum Ratings VSS = 0 V reference Parameter Symbol Rating Unit VDDIO -0.3 to +3.9 V VDDC -0.3 to +1.8 V VDD_MIPI -0.3 to +1.8 V AVDD33 -0.3 to +3.9 V AVDD12 -0.3 to +1.8 V VIN_DSI -0.3 to VDD_MIPI+0.3 V VOUT_DSI -0.3 to VDD_MIPI+0.3 V VIN_IO -0.3 to VDDIO+0.3 V VOUT_IO -0.3 to VDDIO+0.3 V Junction temperature Tj 125 oC Storage temperature Tstg Supply voltage (1.8 V - Digital IO) Supply voltage (1.2 V - Digital Core) Supply voltage (1.2 V - MIPI DSI PHY) Supply voltage (3.3 V - HDMIRX PHY) Supply voltage (1.2 V - HDMIRX PHY) Input voltage (DSI IO) Output voltage (DSI IO) Input voltage (Digital IO) Output voltage (Digital IO) -40 to +125 oC 6.2. Recommended Operating Condition VSS = 0 V reference Parameter Symbol Min Typ. Max Unit Supply voltage (1.8/3.3 V - Digital IO) VDDIO2 1.65 1.8 3.6 V Supply voltage (3.3 V - HDMI Digital IO) VDDIO1 3.0 3.3 3.6 V VDDC AVDD33 AVDD12 VDD_MIPI 1.1 3.135 1.15 1.1 1.2 3.3 1.2 1.2 1.3 3.465 1.25 1.3 V V V V Ta -30 +25 +70 oC VSN - - 100 mVpp Supply voltage (1.2 V - Digital Core) Supply voltage (3.3 V - HDMIRX PHY) Supply voltage (1.2 V - HDMIRX PHY) Supply voltage (1.2 V - MIPI DSI PHY) Operating temperature (ambient temperature with voltage applied) Supply Noise Voltage 15 / 18 2017-11-13 TC358779XBG 6.3. DC Electrical Specification Parameter Input voltage, High level input Note1 Input voltage, Low level input Note1 Input voltage High level CMOS Schmitt Trigger Note1,2 Input voltage Low level CMOS Schmitt Trigger Note1,2 Output voltage High level Note1, Note2 Output voltage Low level Note1, Note2 Input leak current, High level (Condition: VIN = +VDDIO, VDDIO = 3.6 V) Input leak current, Low level (Condition: VIN = 0 V, VDDIO = 3.6 V) Note1: Note2: Note4: Note5: Symbol VIH VIL Min 0.7 x VDDIO 0 VIHS 0.7 x VDDIO VILS 0 VOH 0.8 x VDDIO VOL 0 IILH1 (Note4) -10 IILL1 (Note5) -10 Typ. - Max VDDIO 0.3 x VDDIO Unit V V VDDIO V 0.3 x VDDIO V VDDIO V 0.2 x VDDIO V - 10 A - 10 A - Each power source is operating within recommended operation condition. Current output value is specified to each IO buffer individually. Output voltage changes with output current value. Normal pin or Pull-up IO pin applied VDDIO supply voltage to Vin (input voltage) Normal pin applied VSS (0V) to Vin (input voltage) 16 / 18 2017-11-13 TC358779XBG 7. Revision History Table 7-1 Revision History Revision 0.75 0.821 Date 2014-04-10 2015-12-18 0.822 2016-04-01 0.823 2016-09-01 1.0 2017-10-17 1.1 2017-11-13 Description Newly released Typo Init(O) DAOUT pin in External Pins Package's weight is rounding up digits after the decimal point to form an integer. 1. Typo Correction on DSI-TX (10) on Table 3.1 2. Unified "Phy" to "PHY". Added comment to HDCP. Modified Table 3.2. Changed header, footer and the last page. Changed corporate name. Modified values in Table 2-1. 17 / 18 2017-11-13 TC358779XBG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". * TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. 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No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 18 / 18 2017-11-13