SM7745D CMOS Series
4 Pad 7 x 5mm Leadless Surface Mount Ceramic Clock Oscillator
CMOS with Enable/ Disable, 3rd Overtone Crystal Used
Low Jitter 70.00 MHz – 170.00 MHz
Standard Specifications
Overall Frequency Stability SM7745D: ± 50 PPM, SM7744D: ± 25 PPM, SM7720D: ± 20 PPM over Operating Temp. Range
Operating Temperature Range 0 to +70°C is standard, but can be extended to - 40 to +85°C for certain frequencies
Supply Voltage (Vcc) 5.0, 3.3, and 2.5 volts available, .01 µF bypass cap recommended, consult factory for 1.8 volts
Symmetry (Duty Cycle) 40/60 to 60/40% is standard, but 45/55% at 50% of Vcc is also available (see Waveform 1)
Output Load Standard load is 15 pF (typ. 1 ASIC) maximum, see Test Circuit 2 (consult factory for heavier loads)
Enable/Disable Option (E/D)
See Website for Supply Current (Icc) and Rise and Fall Times
Part Numbering Guide
Model
Frequency Stability
45 = ± 50 PPM
44 = ± 25 PPM
Frequency in MHz
Special Specifications (choose all that apply)
Y: Std Specs (5.0V ± 10%, 0 to +70 C, 40/60% Symmetry)
E: Extended Operating Temperature Range (- 40 to +85 C)
S: 45/55% Symmetry at 50% of Vcc
V: Supply Voltage of 3.3 volts ± 10%
W: Supply Voltage of 2.5 volts ± 5%
X: Supply Voltage of 1.8 volts ± 5% (Consult factory)
SM77 45 D V - 70.0M - 30 - XXX (Internal Code or blank)
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.
Mechanical: not to scale
inches (mm)
°°
Sept 2004
Solder Pads
Consult factory for higher frequencies
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 8
Pl tronics, Inc.
Packaging
Tray or
16mm tape
8mm pitch
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load
Output enabled when Pin #1 is open or at Logic “1”; Output disabled when Pin #1 is at Logic “0”.
Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.
Non-Std Output Load
Blank = 15 pF max, 30 = 30 pF max
1 pS RMS maximum, from 12 kHz to 20 MHz from carrier
Jitter
Logic Levels Logic “1” 90% of Vcc MIN; Logic “0” 10% of Vcc MAX
20 = ± 20 PPM
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
CMOS 70 - 170 MHz, 3rd OT
Page 8 - 11
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)
m
.01 F
bypass
capacitor
MAX
0.200 (5.08) 0.075 (1.9)
0.276 (7.0 ± .15)
0.197 (5.0 ± .15)
0.055
(1.4) 0.024
(0.60)
0.050 (1.27)
0.004 (0.10)
1
4
1 2
3
4
0.200 (5.08)
0.079 (2.0)
0.087 (2.2)
0.055
(1.4) 0.145
(3.68)
3
2
1 E/D
2 GND
3 OUT
4 Vcc
PIN SIGNAL
Due to part size and factory abilities, part marking may vary from lot to lot
and may contain our part number or an internal code.
m
.01 F
bypass
capacitor
MAX
0.200 (5.08) 0.075 (1.9)
0.276 (7.0 ± .15)
0.197 (5.0 ± .15)
0.055
(1.4) 0.024
(0.60)
0.050 (1.27)
0.004 (0.10)
1
4
1 2
3
4
0.200 (5.08)
0.079 (2.0)
0.087 (2.2)
0.055
(1.4) 0.145
(3.68)
3
2
1 E/D
2 GND
3 OUT
4 Vcc
PIN SIGNAL
7XYWWX
106.25M
PLE 3ESV
Marking Examples and Explanation
PLE = Pletronics
7 = Package Code
X = Frequency Stability
YWWX = Date Code
Frequency in MHz
3ESV = Applicable Specs (some internal)
PLE 7XYWW
125.0MV
