Product Folder Order Now Support & Community Tools & Software Technical Documents LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 LMR24210 42-VIN, 1-A Step-Down Voltage Regulator in DSBGA Package 1 Features 3 Description * * * * The LMR24210 synchronously rectified buck converter features all required functions to implement a highly efficient and cost effective buck regulator. It is capable of supplying 1 A to loads with an output voltage as low as 0.8 V. Dual N-channel synchronous MOSFET switches allow a low component count, thus reducing complexity and minimizing board size. 1 * * * * * * * * * * Input Voltage Range of 4.5 V to 42 V Output Voltage Range of 0.8 V to 24 V Output Current up to 1 A Integrated low RDS(ON) Synchronous MOSFETs for High Efficiency Up to 1 MHz Switching Frequency Low Shutdown IQ, 25 A Typical Programmable Soft Start No Loop Compensation Required COT With ERM Architecture Tiny Overall Solution Reduces System Cost Integrated Synchronous MOSFETs Provides High Efficiency at Low Output Voltages Stable with Low ESR Capacitors 28-Bump DSBGA Packaging Create a custom design using the LMR24010 with the WEBENCH(R) Power Designer 2 Applications * * * * Point-of-Load Conversions from 5V, 12V and 24V Rails Space Constrained Applications Industrial Distributed Power Applications Power Meters Different from most other COT regulators, the LMR24210 does not rely on output capacitor ESR for stability, and is designed to work exceptionally well with ceramic and other very low ESR output capacitors. It requires no loop compensation, results in a fast load transient response and simple circuit implementation. The operating frequency remains nearly constant with line variations due to the inverse relationship between the input voltage and the ontime. The operating frequency can be externally programmed up to 1 MHz. Protection features include VCC under-voltage lock-out, output overvoltage protection, thermal shutdown, and gate-drive undervoltage lockout. The LMR24210 is available in the small DSBGA low profile chip-scale package. Device Information(1) PART NUMBER LMR24010 PACKAGE DSBGA (28) BODY SIZE (MAX) 3.676 mm x 2.48 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space Typical Application LMR24210 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Ratings ........................... Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 14 9 Layout ................................................................... 18 9.1 Layout Considerations ............................................ 18 9.2 Layout Examples..................................................... 18 9.3 Package Considerations ......................................... 19 10 Device and Documentation Support ................. 20 10.1 10.2 10.3 10.4 10.5 10.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (April 2013) to Revision H * Editorial changes only; add WEBENCH links ........................................................................................................................ 1 Changes from Revision E (April 2013) to Revision F * 2 Page Page Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 5 Pin Configuration and Functions YPA Package 28-Bump DSGBA Top View A B C D E F G 4 VIN VIN BST SW AGND RON EN 3 SW SW SW SW AGND AGND 2 SW SW SW SW VCC AGND SS 1 PGN D VCC AGND FB PGND PGND PGND AGND Top Mark Pin Descriptions PIN NO. DESCRIPTION NAME A2, A3, B2, B3, C2, C3, D2, D3, D4 SW Switching node Internally connected to the source of the main MOSFET and the drain of the Synchronous MOSFET. Connect to the inductor. A4, B4 VIN Input supply voltage Supply pin to the device. Nominal input range is 4.5 V to 42 V. C4 BST Connection for bootstrap capacitor Connect a 33-nF capacitor from the SW pin to this pin. An internal diode charges the capacitor during the main MOSFET off-time. Analog ground Ground for all internal circuitry other than the PGND pin. E3, E4, F1, F2, F3, G3 AGND G2 SS Soft start An 8-A internal current source charges an external capacitor to provide the soft- start function. G1 FB Feedback Internally connected to the regulation and over-voltage comparators. The regulation setting is 0.8V at this pin. Connect to feedback resistors. G4 EN Enable Connect a voltage higher than 1.26V to enable the regulator. Leaving this input open circuit enables the device at internal UVLO level. F4 RON On-time control An external resistor from the VIN pin to this pin sets the main MOSFET on-time. E1, E2 VCC Start-up regulator output Nominally regulated to 6 V. Connect a capacitor of not less than 680 nF between the VCC and AGND pins for stable operation. Power ground Synchronous MOSFET source connection. Tie to a ground plane. A1, B1, C1, D1 PGND Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 3 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings See notes (1) (2) VIN, RON to AGND -0.3V to 43.5V SW to AGND -0.3V to 43.5V SW to AGND (Transient) -2V (< 100ns) VIN to SW -0.3V to 43.5V BST to SW -0.3V to 7V All Other Inputs to AGND -0.3V to 7V Storage Temperature Range -65C to +150C Junction Temperature (TJ) (1) (2) 150C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see Electrical Characteristics. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Ratings See note (1) Supply Voltage Range (VIN) 4.5V to 42V -40C to +125C Junction Temperature Range (TJ) Thermal Resistance (JA) 28-ball DSBGA (2) 50C/W For soldering specifications see SNOA549 (1) (2) 4 Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see Electrical Characteristics . JA calculations were performed in general accordance with JEDEC standards JESD51-1 to JESD51-11. Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 6.4 Electrical Characteristics Specifications with standard type are for TJ = 25C only; limits in boldface type apply over the full operating junction temperature (TJ) range. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 18V, VOUT = 3.3 V. (1) PARAMETER TEST CONDITIONS MIN TYP MAX 6.0 7.2 UNIT START-UP REGULATOR, VCC VCC VIN - VCC IVCCL VCC-UVLO VCC output voltage CCC = 680nF, no load VIN - VCC dropout voltage ICC = 20mA VCC current limit (2) VCC = 0V 5.0 350 40 65 3.55 3.75 V mV mA VCC under-voltage lockout threshold (UVLO) VIN increasing VCC-UVLO-HYS VCC UVLO hysteresis VIN decreasing - DSBGA package 150 tVCC-UVLO-D VCC UVLO filter delay IIN operating current No switching, VFB = 1V 0.7 1 mA IIN operating current, Device shutdown VEN = 0V 25 40 A 0.18 0.375 IIN IIN-SD 3.95 V mV 3 s SWITCHING CHARACTERISTICS RDS-UP-ON Main MOSFET RDS(on) RDS- DN-ON Syn. MOSFET RDS(on) VG-UVLO 0.11 0.225 Gate drive voltage UVLO VBST - VSW increasing 3.3 4 V SS pin source current VSS = 0.5V 11 Syn. MOSFET current limit threshold LMR24210 ON timer pulse width VIN = 10V, RON = 100 k 1.38 VIN = 30V, RON = 100 k 0.47 SOFT START ISS A CURRENT LIMIT ICL 1.2 1.8 2.6 A ON/OFF TIMER ton ton-MIN toff s ON timer minimum pulse width 150 ns OFF timer pulse width 260 ns ENABLE INPUT VEN VEN-HYS EN Pin input threshold VEN rising Enable threshold hysteresis VEN falling 1.13 1.18 1.23 90 V mV REGULATION AND OVERVOLTAGE COMPARATOR VFB VFB-OV IFB VSS 0.8V TJ = -40C to +125C In-regulation feedback voltage Feedback overvoltage threshold FB pin current 0.784 0.8 0.816 0.888 0.920 0.945 V V 5 nA THERMAL SHUTDOWN (1) (2) TSD Thermal shutdown temperature TJ rising 165 C TSD-HYS Thermal shutdown temperature hysteresis TJ falling 20 C Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 5 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 6.5 Typical Characteristics Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V (Figure 26) TA = 25C. Figure 1. VCC vs ICC Figure 2. VCC vs VIN SWITCHING FREQENCY (kHZ) 1000 Ron = 12.4k Ron = 12.4k Ron = 12.4k Ron = 12.4k Ron = 7.68k Ron = 7.68k Ron = 7.68k Ron = 7.68k 900 800 700 600 ; L = 3.3 ; L = 3.3 ; L = 8.2 ; L = 8.2 ; L = 3.3 ; L = 3.3 ; L = 8.2 ; L = 8.2 H, Io = 0.4A H, Io = 1A H, Io = 0.4A H, Io = 1A H, Io = 0.4A H, Io = 1A H, Io = 0.4A H, Io = 1A 500 400 300 200 100 0 0 Figure 3. Ton vs VIN 20 30 VIN(v) 40 50 Figure 4. Switching Frequency, FSW vs VIN, VOUT=0.8v, Figure 5. VFB vs Temperature 6 10 Figure 6. RDS(on) vs Temperature Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Typical Characteristics (continued) Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V (Figure 26) TA = 25C. 0.20 100 0.15 0.10 80 uVOUT(%) EFFICIENCY (%) 90 70 0.05 0.00 -0.05 60 VIN = 4.5V VIN = 9V VIN = 12v VIN = 24V VIN = 42v 50 40 0.0 VIN = 4.5V VIN = 9V VIN = 12V VIN = 24V VIN = 42V -0.10 -0.15 -0.20 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 0.0 1.0 VOUT = 3.3 V 0.2 0.4 0.6 0.8 LOAD CURRENT (A) VOUT = 3.3 V Figure 7. Efficiency vs Load Current Figure 8. VOUT Regulation vs Load Current 1.0 100 VIN = 4.5V VIN = 9V VIN = 12V VIN = 24V VIN = 42V 0.8 90 0.6 0.4 80 uVOUT(%) EFFICIENCY (%) 1.0 70 60 VIN = 4.5V VIN = 9V VIN = 12v VIN = 24V VIN = 42v 50 40 0.0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.0 1.0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 1.0 VOUT = 0.8 V Figure 9. Efficiency vs Load Current (VOUT = 0.8v) Figure 10. VOUT Regulation vs Load Current VEN VIN VO 2V/DIV 10V/Div 1V/Div VO 1V/DIV IO 200 mA/Div IO 500 mA/Div TIME (1 ms/DIV) TIME (5 ms/DIV) VOUT = 3.3 V, 1-A Loaded VOUT = 3.3 V, 1-A Loaded Figure 12. Enable Transient Figure 11. Power Up Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 7 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com Typical Characteristics (continued) Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for VOUT = 3.3 V (Figure 26) TA = 25C. 'VO 20 mV/DIV VEN 2V/DIV VSW VO 5V/DIV 2V/DIV IO 500 mA/DIV 500 mA/DIV IL TIME (0.1 ms/DIV) TIME (2 Ps/DIV) VOUT = 3.3 V, 1 A Loaded VOUT = 3.3 V, 1 A Loaded Figure 13. Shutdown Transient Figure 14. Continuous Mode Operation 'VO 20 mV/Div VSW 5V/Div VSW 5V/Div IL 500 mA/Div IL 500 mA/Div TIME (5 Ps/DIV) TIME (20 Ps/DIV) VOUT = 3.3 V, 0.5 A Loaded VOUT = 3.3 V, 0.5 A to 1 A Load Figure 15. Discontinuous Mode Operation 8 Submit Documentation Feedback Figure 16. DCM to CCM Transition Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 7 Detailed Description 7.1 Overview The LMR24210 step-down switching regulator features all required functions to implement a cost effective, efficient buck power converter capable of supplying 1 A to a load. It contains dual N-channel main and synchronous MOSFETs. The constant on-time (COT) regulation scheme requires no loop compensation, results in fast load transient response and simple circuit implementation. The regulator can function properly even with an all ceramic output capacitor network, and does not rely on the output capacitor's ESR for stability. The operating frequency remains constant with line variations due to the inverse relationship between the input voltage and the on-time. The valley current limit detection circuit, with the limit set internally at 1.8 A, inhibits the main MOSFET until the inductor current level subsides. The LMR24210 can be applied in numerous applications and can operate efficiently for inputs as high as 42 V. Protection features include output overvoltage protection, thermal shutdown, VCC undervoltage lockout and gatedrive undervoltage lockout. The LMR24210 is available in a small DSBGA chip-scale package. 7.2 Functional Block Diagram Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 9 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 7.3 Feature Description 7.3.1 COT Control Circuit Overview COT control is based on a comparator and a one-shot on-timer, with the output voltage feedback (feeding to the FB pin) compared with an internal reference of 0.8 V. If the voltage of the FB pin is below the reference, the main MOSFET is turned on for a fixed on-time determined by a programming resistor RON and the input voltage VIN, upon which the on-time varies inversely. Following the on-time, the main MOSFET remains off for a minimum of 260 ns. Then, if the voltage of the FB pin is below the reference, the main MOSFET is turned on again for another on-time period. The switching will continue to achieve regulation. The regulator will operate in the discontinuous conduction mode (DCM) at a light load, and the continuous conduction mode (CCM) with a heavy load. In the DCM, the current through the inductor starts at zero and ramps up to a peak during the on-time, and then ramps back to zero before the end of the off-time. It remains zero and the load current is supplied entirely by the output capacitor. The next on-time period starts when the voltage at the FB pin falls below the internal reference. The operating frequency in the DCM is lower and varies larger with the load current as compared with the CCM. Conversion efficiency is maintained since conduction loss and switching loss are reduced with the reduction in the load and the switching frequency respectively. The operating frequency in the DCM can be calculated approximately as follows: fSW = VOUT (VIN - 1) x L x 1.18 x 1020 x IOUT (VIN VOUT) x RON2 (1) In the CCM, the current flows through the inductor in the entire switching cycle, and never reaches zero during the off-time. The operating frequency remains relatively constant with load and line variations. The CCM operating frequency can be calculated approximately as follows: fSW = VOUT 1.3 x 10-10 x RON (2) Consider and Equation 5 when choosing the switching frequency. The output voltage is set by two external resistors RFB1 and RFB2. The regulated output voltage is VOUT = 0.8 V x (RFB1 + RFB2) / RFB2 (3) 7.3.2 Start-up Regulator (VCC) A start-up regulator is integrated within the LMR24210. The input pin VIN can be connected directly to a line voltage up to 42 V. The VCC output regulates at 6 V, and is current limited to 65 mA. Upon power up, the regulator sources current into an external capacitor CVCC, which is connected to the VCC pin. For stability, CVCC must be at least 680 nF. When the voltage on the VCC pin is higher than the undervoltage lockout (UVLO) threshold of 3.75 V, the main MOSFET is enabled and the SS pin is released to allow the soft-start capacitor CSS to charge. The minimum input voltage is determined by the dropout voltage of the regulator and the VCC UVLO falling threshold ( 3.7 V). If VIN is less than 4 V, the regulator shuts off and VCC goes to zero. 7.3.3 Regulation Comparator The feedback voltage at the FB pin is compared to a 0.8-V internal reference. In normal operation (the output voltage is regulated), an on-time period is initiated when the voltage at the FB pin falls below 0.8 V. The main MOSFET stays on for the on-time, causing the output voltage and consequently the voltage of the FB pin to rise above 0.8 V. After the on-time period, the main MOSFET stays off until the voltage of the FB pin falls below 0.8V again. Bias current at the FB pin is nominally 5 nA. 7.3.4 Zero Coil Current Detect The current of the synchronous MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM operation, which improves the efficiency at a light load. 10 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Feature Description (continued) 7.3.5 Overvoltage Comparator The voltage at the FB pin is compared to a 0.92-V internal reference. If it rises above 0.92 V, the on-time is immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage or the output load changes suddenly. Once the OVP is activated, the main MOSFET remains off until the voltage at the FB pin falls below 0.92 V. The synchronous MOSFET stays on to discharge the inductor until the inductor current reduces to zero, and then switches off. 7.3.6 On-Time Timer, Shutdown The on-time of the LMR24210 main MOSFET is determined by the resistor RON and the input voltage VIN. It is calculated as follows: 1.3 x 10 ton = -10 x RON VIN (4) The inverse relationship of ton and VIN gives a nearly constant frequency as VIN is varied. RON should be selected such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of 150 ns for ton. This limits the maximum operating frequency, which is governed by the following equation: VOUT fSW(MAX) = VIN(MAX) x 150 ns (5) The LMR24210 can be remotely shutdown by pulling the voltage of the EN pin below 1 V. In this shutdown mode, the SS pin is internally grounded, the on-timer is disabled, and bias currents are reduced. Releasing the EN pin allows normal operation to resume because the EN pin is internally pulled up. Figure 17. Shutdown Implementation 7.3.7 Current Limit Current limit detection is carried out during the off-time by monitoring the re-circulating current through the synchronous MOSFET. Referring to the Functional Block Diagram, when the main MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 1.8 A, the current limit comparator toggles, and as a result disabling the start of the next on-time period. The next switching cycle starts when the re-circulating current falls back below 1.8 A (and the voltage at the FB pin is below 0.8 V). The inductor current is monitored during the on-time of the synchronous MOSFET. As long as the inductor current exceeds 1.8 A, the main MOSFET remains inhibited to achieve current limit. The operating frequency is lower during current limit due to a longer off-time. Figure 18 illustrates an inductor current waveform. On average, the output current IOUT is the same as the inductor current IL, which is the average of the rippled inductor current. In case of current limit (the current limit portion of Figure 18), the next on-time will not initiate until the current drops below 1.8A (assume the voltage at the FB pin is lower than 0.8 V). During each on-time the current ramps up an amount equal to: (VIN - VOUT) x ton ILR = (6) L During current limit, the LMR24210 operates in a constant current mode with an average output current IOUT(CL) equal to 1.8 A + ILR / 2. Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 11 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com Feature Description (continued) Figure 18. Inductor Current - Current Limit Operation 7.3.8 N-Channel Mosfet and Driver The LMR24210 integrates an N-channel main MOSFET and an associated floating high voltage main MOSFET gate driver. The gate drive circuit works in conjunction with an external bootstrap capacitor CBST and an internal high voltage diode. CBST connecting between the BST and SW pins powers the main MOSFET gate driver during the main MOSFET on-time. During each off-time, the voltage of the SW pin falls to approximately -1 V, and CBST charges from VCC through the internal diode. The minimum off-time of 260 ns provides enough time for charging CBST in each cycle. 7.3.9 Soft Start The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. Upon turnon, after VCC reaches the undervoltage threshold, an 8-A internal current source charges up an external capacitor CSS connecting to the SS pin. The ramping voltage at the SS pin (and the non-inverting input of the regulation comparator as well) ramps up the output voltage VOUT in a controlled manner. The soft start time duration to reach steady state operation is given by the formula: tSS = VREF x CSS / 8 A = 0.8 V x CSS / 8 A (7) This equation can be rearranged as follows: CSS= tSS x 8 A / 0.8 V (8) Use of a 4.7-nF capacitor results in a 0.5-ms soft-start duration. This is a recommended value. Note that high values of CSS capacitance causes more output voltage drop when a load transient goes across the DCM-CCM boundary. If a fast load transient response is desired for steps between DCM and CCM mode the softstart capacitor value must be less than 18 nF (which corresponds to a soft-start time of 1.8 ms). An internal switch grounds the SS pin if any of the following three cases happens: (i) VCC is below the UVLO threshold; (ii) a thermal shutdown occurs; or (iii) the EN pin is grounded. Alternatively, the output voltage can be shut off by connecting the SS pin to ground using an external switch. Releasing the switch allows the SS pin to ramp up and the output voltage to return to normal. The shutdown configuration is shown in Figure 19. 12 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Feature Description (continued) Figure 19. Alternate Shutdown Implementation 7.3.10 Thermal Protection The junction temperature of the LMR24210 should not exceed the maximum limit. Thermal protection is implemented by an internal Thermal Shutdown circuit, which activates (typically) at 165C to make the controller enter a low power reset state by disabling the main MOSFET, disabling the on-timer, and grounding the SS pin. Thermal protection helps prevent catastrophic failures from accidental device overheating. When the junction temperature falls back below 145C (typical hysteresis = 20C), the SS pin is released, and normal operation resumes. 7.3.11 Thermal Derating Temperature rise increases with frequency, load current, input voltage and smaller board dimensions. On a typical board, the LMR24210 is capable of supplying 1 A below an ambient temperature of 90C under worst case operation with input voltage of 42 V. Figure 20 shows a thermal derating curve for the output current without thermal shutdown against ambient temperature up to 125C. Obtaining 1-A output current is possible at higher temperature by increasing the PCB ground plane area, adding airflow or reducing the input voltage or operating frequency. 1.2 MAXIMUM IOUT(A) 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 AMBIENT TEMPERATURE (C) 125 JA=40C/W, VOUT = 3.3 V, SW = 500 kHz. (tested on the evaluation board) Figure 20. Thermal Derating Curve Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 13 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMR24210 voltage regulator features all required functions to implement a highly efficient and cost-effective buck regulator. It is capable of supplying 1 A to loads with an output voltage as low as 0.8 V. Dual N-channel synchronous MOSFET switches allow a low component count, thus reducing complexity and minimizing board size. 8.2 Typical Application D2 VIN BOOST VIN C3 C1 L1 SW LMR12010 ON VOUT D1 EN OFF C2 R1 FB GND R2 Figure 21. Typical Application Schematic 8.2.1 Detailed Design Procedure 8.2.1.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LMR24010 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 14 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Typical Application (continued) 8.2.1.2 External Components The following guidelines can be used to select external components. RFB1 and RFB2: Choose these resistors from standard values in the range of 1 k to 10 k, satisfying the following ratio: RFB1 / RFB2 = (VOUT / 0.8 V) - 1 (9) For VOUT = 0.8 V, the FB pin can be connected to the output directly with a pre-load resistor drawing more than 20 A. This is needed because the converter operation needs a minimum inductor current ripple to maintain good regulation when no load is connected. RON:Equation 2 can be used to select RON if a desired operating frequency is selected. But the minimum value of RON is determined by the minimum on-time. It can be calculated as follows: RON t VIN(MAX) x 150 ns 1.3 x 10-10 (10) If RON calculated from Equation 2 is smaller than the minimum value determined in Equation 10, select a lower frequency to re-calculate RON by Equation 2. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged. The relationship of VIN(MAX) and RON is shown in Figure 22. On the other hand, the minimum off-time of 260 ns can limit the maximum duty ratio. Figure 22. Maximum VIN For Selected RON L: The main parameter affected by the inductor is the amplitude of inductor current ripple (ILR). Once ILR is selected, L can be determined by: L= VOUT x (VIN - VOUT) ILR x fSW x VIN where * * VIN is the maximum input voltage and fSW is determined from Equation 2. (11) If the output current IOUT is determined, by assuming that IOUT = IL, the higher and lower peak of ILR can be determined. Beware that the higher peak of ILR should not be larger than the saturation current of the inductor and current limits of the main and synchronous MOSFETs. Also, the lower peak of ILR must be positive if CCM operation is required. Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 15 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com Typical Application (continued) Figure 23. Inductor Selection for VOUT = 3.3 V Figure 24. Inductor Selection for VOUT = 0.8 V Figure 23 and Figure 24 show curves on inductor selection for various VOUT and RON. For small RON, according to Equation 10, VIN is limited. Some curves are therefore limited as shown in the figures. CVCC: The capacitor on the VCC output provides not only noise filtering and stability, but also prevents false triggering of the VCC UVLO at the main MOSFET on/off transitions. CVCC should be no smaller than 680 nF for stability, and should be a good quality, low ESR, ceramic capacitor. COUT and COUT3: COUT should generally be no smaller than 10 F. Experimentation is usually necessary to determine the minimum value for COUT, as the nature of the load may require a larger value. A load which creates significant transients requires a larger COUT than a fixed load. COUT3 is a small value ceramic capacitor located close to the LMR24210 to further suppress high frequency noise at VOUT. TI recommends a 100-nF capacitor. 16 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Typical Application (continued) CIN and CIN3: The function of CIN is to supply most of the main MOSFET current during the on-time, and limit the voltage ripple at the VIN pin, assuming that the voltage source connecting to the VIN pin has finite output impedance. If the voltage source's dynamic impedance is high (effectively a current source), CIN supplies the average input current, but not the ripple current. At the maximum load current, when the main MOSFET turns on, the current to the VIN pin suddenly increases from zero to the lower peak of the inductor's ripple current and ramps up to the higher peak value. It then drops to zero at turn-off. The average current during the on-time is the load current. For a worst case calculation, CIN must be capable of supplying this average load current during the maximum on-time. CIN is calculated from: IOUT x ton CIN = 'VIN where * * * IOUT is the load current ton is the maximum on-time VIN is the allowable ripple voltage at VIN (12) The purpose of the CIN3 is to help avoid transients and ringing due to long lead inductance at the VIN pin. A low ESR 0.1-F ceramic chip capacitor located close to the LMR24210 is recommended. CBST: A 33-nF high-quality ceramic capacitor with low ESR is recommended for CBST since it supplies a surge current to charge the main MOSFET gate driver at turnon. Low ESR also helps ensure a complete recharge during each off-time. CSS: The capacitor at the SS pin determines the soft-start time; that is, the time for the reference voltage at the regulation comparator and the output voltage to reach their final value. The time is determined from Equation 13: CSS x 0.8V tSS = 8 PA (13) CFB: If the output voltage is higher than 1.6 V, CFB is needed in the DCM to reduce the output ripple. The recommended value for CFB is 10 nF. 8.2.2 Application Curve 'VO 20 mV/Div IL 500 mA/Div TIME (200 Ps/DIV) VOUT = 3.3 V, 0.2 A to 1 A Load Figure 25. Load Transient Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 17 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 9 Layout 9.1 Layout Considerations The LMR24210 regulation, overvoltage, and current limit comparators are very fast and may respond to short duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as possible, and all external components must be as close to their associated pins of the LMR24210 as possible. Refer to the Functional Block Diagram, the loop formed by CIN, the main and synchronous MOSFET internal to the LMR24210, and the PGND pin must be as small as possible. The connection from the PGND pin to CIN must be as short and direct as possible. Add vias to connect the ground of CIN to a ground plane, located as close as possible to the capacitor. The bootstrap capacitor CBST should be connected as close to the SW and BST pins as possible, and the connecting traces should be thick. The feedback resistors and capacitor RFB1, RFB2, and CFB must be close to the FB pin. A long trace running from VOUT to RFB1 is generally acceptable since this is a low impedance node. Ground RFB2 directly to the AGND pin. Connect the output capacitor COUT to the load and tied directly to the ground plane. Connect the inductor L close to the SW pin with as short a trace as possible to reduce the potential for EMI (electromagnetic interference) generation. If it is expected that the internal dissipation of the LMR24210 produces excessive junction temperature during normal operation, making good use of the PC board's ground plane can help considerably to dissipate heat. Additionally the use of thick traces, where possible, can help conduct heat away from the LMR24210. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature. 9.2 Layout Examples Figure 26. Typical Application Schematic for VOUT = 3.3 V 18 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 LMR24210 www.ti.com SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 Layout Examples (continued) Figure 27. Typical Application Schematic for VOUT = 0.8 V 9.3 Package Considerations The die has exposed edges and can be sensitive to ambient light. For applications with direct high intensitiy ambient red, infrared, LED or natural light TI recommends shielding the device from the light source to avoid abnormal behavior. Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 19 LMR24210 SNVS738H - OCTOBER 2011 - REVISED JUNE 2019 www.ti.com 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support 10.1.1.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LMR24010 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 10.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 20 Submit Documentation Feedback Copyright (c) 2011-2019, Texas Instruments Incorporated Product Folder Links: LMR24210 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMR24210TL/NOPB ACTIVE DSBGA YPA 28 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 SJ5B LMR24210TLX/NOPB ACTIVE DSBGA YPA 28 1000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 SJ5B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMR24210TL/NOPB DSBGA YPA 28 250 178.0 12.4 LMR24210TLX/NOPB DSBGA YPA 28 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.64 3.84 0.76 8.0 12.0 Q1 2.64 3.84 0.76 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR24210TL/NOPB DSBGA YPA LMR24210TLX/NOPB DSBGA YPA 28 250 210.0 185.0 35.0 28 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPA0028 D 0.600 0.075 E TLC28XXX (Rev A) D: Max = 3.676 mm, Min =3.615 mm E: Max = 2.48 mm, Min = 2.419 mm 4215064/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. 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