1M (64K x 16) Static RAM
CY62127BV MoBL®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05155 Rev. *B Revised August 27, 2002
Features
•High Speed: 55 ns and 70 ns
•Wide voltage range: 2.7V–3.6V
•Low active power
—54 mW (max.) (15 mA)
•Low standby power (70 ns)
—54 µW (max.) (15 µA)
•Easy memory expans ion with C E and OE features
•Automatic power -do wn wh en dese lec t ed
•CMOS for optimum speed/power
•Package available in a 44-pin TSOP Type II (forward
pinout) and a 48-ball fBGA package
Functional Description[1]
The CY62127BV MoBL® MoBL® is a high-performance
CMOS static RAM organized as 64K words by 16 bits. This
device features advanced circuit design to provide ultra-low
active current. This is ideal for providing More Battery Life
(MoBL) in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
signif icantly red uces power co nsumption w hen addresses are
not toggling, or when deselected (CE HIGH or both BLE and
BHE are H IGH). The input/ou tput pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High
Enab le and Byte Lo w Enable are dis abl ed (BHE , BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Writ e Enab le (WE ) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 thro ugh A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW , the n data from me mory will app ear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array I/O0–I/O7
COLUMN DECODER
A11
A12
A13
A14
A15
2048 X 512
SENS E AMPS
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
ROW DECODER
A7
A6
A3
A0
A2
A1
A5
A4
A8
Pow er - Down
Circuit BHE
BLE
CE
A9
A10
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 2 of 11
Pin Configurations[2]
Maximum Ratings
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential.................–0.5V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[3]....................................–0.5V to VCC + 0.5V
DC Input Voltage[3].................................... −0.5V to VCC + 0.5V
Output Current into Outpu t s (LO W)..................... ........20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC
DNU
VCC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top Vi ew
TSOP II (Fo r wa rd)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
Operating Range
Range Ambient
Temperature VCC
Industrial –40°C to +85°C 2.7V to 3.6V
Product Portfolio
Product
VCC Range (V)
Speed (ns)
Power Dissipation (Industrial)
Operating, ICC
(mA) f = fmax Standby, ISB2 (µA)
VCC(min.) VCC(typ.)[4] VCC(max.) Max. Typ.[4] Max.
CY62127BV
MoBL®2.7 3.0 3.6 55 20 0.5 15
70 15
Notes:
2. NC pins are n ot connected to the die.
3. VIL(min.) = –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 3 of 11
Electri cal Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62127BV
MoBL®-55 CY62127BV
MoBL®-70
UnitMin. Typ.[4] Max. Min. Typ.[4] Max.
VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.2 2.2 V
VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC +
0.3V 2.0 VCC +
0.3V V
VIL Input LOW Voltage –0.3 0.4 –0.3 0.4 V
IIX Input Le akage Current GND < VI < VCC –1+1 –1+1 µA
IOZ Output Leakage
Current GND < VI< VCC, Output Disabled –1+1 –1+1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 3.6V
IOUT = 0 mA
CMOS Levels
20 15 mA
ISB1 Automatic CE
Power-Down
Current— TTL Inputs
Max. VCC, CE ≥ VIH
VIN ≥ VIH or VIN ≤ VIL, f = fMAX 2 2 mA
ISB2 Automatic CE
Power-Down
Current— CMOS
Inputs
Max. VCC, CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V,
f = 0
0.5 15 0.5 15 µA
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 9pF
COUT Output Capacitance 9pF
Thermal Resistance
Description Test Conditions Symbol BGA Unit
Thermal Resistance
(Junction to Ambient)[5] Still Air , soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit boar d ΘJA 55 °C/W
Thermal Resistance
(Junction to Case)[5] ΘJC 16 °C/W
AC Test Loads and Waveforms
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
V
CC
Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT VTH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise TIme
: 1 V/ns
Fall Time: 1 V/ns
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 4 of 11
Parameters 3.0V Unit
R1 1.076 K Ohms
R2 1.262 K Ohms
RTH 0.581 K Ohms
VTH 1.620 Volts
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 2.0 3.6 V
ICCDR Dat a R eten tio n Cur rent VCC= VDR = 2.0V , CE > VCC – 0.3V , VIN > VCC –
0.3V or VIN < 0.3 V 0.5 15 µA
tCDR[5] Chip Deselect to Data Retention Time 0ns
tR[6] Operation Recovery Time tRC ns
Data Retention Waveform[7]
Switching Characteristics Over the Operating Range [8]
Parameter Description 55 ns 70 ns UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[9] 5 5 ns
tHZOE OE HIGH to High Z[9, 11] 20 25 ns
tLZCE CE LOW to Low Z[9] 10 10 ns
tHZCE CE HIGH to High Z[9, 11] 20 25 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 55 70 ns
tDBE BHE / BLE LOW to Data Va lid 55 70 ns
tLZBE[10] BHE / BLE LOW to Low Z[9] 5 5 ns
tHZBE BHE / BLE HIGH to High Z[9, 11] 20 25 ns
Write Cycle[12]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
Notes:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, inpu t pu ls e le v el s o f 0 t o VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. If both byte enables are toggled together this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The i nt e rnal writ e t ime of t he me mory i s de f ine d by th e ov er l ap of W E, CE = VIL, B HE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
3.0 V
3.0 V
tCDR
VDR >2.0 V
DATA RETENTION MODE
tR
CE or
VCC
BHE.BLE
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 5 of 11
tAW Address Set-Up to W rit e End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-U p to W rit e Start 0 0 ns
tPWE WE Pulse Wid th 40 50 ns
tBW BHE / BLE Pulse Width 45 60 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[9, 11] 25 25 ns
tLZWE WE HIGH to Low Z[9] 5 5 ns
Switching Characteristics Over the Operating Range (continued)[8]
Parameter Description 55 ns 70 ns UnitMin. Max. Min. Max.
Switching Waveforms
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
Read Cycle No. 2 (OE Controlled)[14, 15]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DOE
t
LZOE
t
DBE
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 6 of 11
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE goes HIGH simult aneously wi th WE HIGH , th e outpu t remains in a h igh-i mpedance s tat e.
18. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
Write Cy cle No. 1 (WE Controlled)
BHE/BLE tBW
[12, 16, 17]
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
Write Cycle N o. 2 (CE Controlled)
BHE/BLE tBW
[12, 16, 17 ]
tSA
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 7 of 11
Switching Waveforms (continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 18
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
[17]
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
VALID
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
NOTE 18
t
BW
BHE/BLE
tSCE
t
PWE
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
X X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/OO–I/O15)Read Active (I
CC)
LHLHLData Out (I/O
O–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 8 of 11
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15) Write Active (ICC)
L L X H L Data In (I/OO–I/O7) Write Lower Byte Only Active (ICC)
L L X L H Data In (I/O8–I/O15) Write Upper Byte Only Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62127BVLL-55ZI Z44 44-lead TSOP II Industrial
70 CY62127BVLL-70ZI
CY62127BVLL-70BAI BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62127BVLL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Truth Table (continued)
CE WE OE BHE BLE Inputs/Outputs Mode Power
Package Diagrams
48-Bal l (7.00 mm x 7.00 mm x 1.2 mm) F BGA B A48A
51-85096-*E
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 9 of 11
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-A
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company
names mentioned in this document may be trademarks of their respective holders.
Package Diagrams (continued)
48-L ead VFB GA (6 x 8 x 1 mm) B V48A
51-85150-**
.
CY62127BV MoBL®
Document #: 38-05155 Rev. *B Page 11 of 11
Document Title: CY62127BV MoBL® 1M (64K x 16) Static RAM
Document Number: 38-05155
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109899 10/02/01 SZV Change from Spec number: 38-01018 to 38-05155
*A 113307 03/01/02 MGN Format standardization & update ordering information
*B 116362 09/04/02 GBI Add footnote 1 and BV Package.
