TDA4850/V1 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of September 1991

File under Integrated Circuits, IC02

1997 Jun 05

INTEGRATED CIRCUITS

TDA4850

Horizontal and vertical deflection

controller for VGA/XGA and

multi-frequency monitors

1997 Jun 05 2

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

FEATURES

•VGA operation fully implemented including

alignment-free vertical and E/W amplitude pre-settings

•4th VGA mode easy applicable (XGA, Super VGA)

•Multi-frequency operation externally selectable

•All adjustments DC-controllable

•Alignment-free oscillators

•Sync separators for video or horizontal and vertical TTL

sync levels regardless of polarity

•Horizontal oscillator with PLL1 for sync and PLL2 for

flyback

•Constant vertical and E/W amplitude in multi-frequency

operation

•DC-coupling to vertical power amplifier (TDA486X or

TDA8351)

•Internal supply voltage stabilization with excellent ripple

rejection to ensure stable geometrical adjustments.

GENERAL DESCRIPTION

The TDA4850 provides economical solutions in VGA/XGA

and multi-frequency monitors. The IC incorporates the

complete horizontal and vertical small signal processing.

VGA-dependent mode detection and settings are

performed on chip. In conjunction with TDA486X or

TDA8351 (vertical output circuits) both ICs offer an

extremely advanced system solution.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VPsupply voltage (pin 1) 9.2 12 16 V

IPsupply current −40 −mA

Vi sync AC-coupled composite video signal with negative-going sync

(peak-to-peak value; pin 9) −1−V

sync slicing level −120 −mV

DC-coupled TTL-compatible horizontal sync signal

(peak value; pin 9) 1.7 −−V

slicing level 1.2 1.4 1.6 V

DC-coupled TTL-compatible vertical sync signal

(peak value; pin 10) 1.7 −−V

slicing level 1.2 1.4 1.6 V

IoV vertical differential output current (peak-to-peak value;

pins 5 and 6) −1−mA

IoH horizontal sink output current on pin 3 −−60 mA

Tamb operating ambient temperature 0 −70 °C

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA4850 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

1997 Jun 05 3

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

BLOCK DIAGRAM

andbook, full pagewidth

MEH165

HORIZONTAL

SYNC

SEPARATOR

(TTL VIDEO SYNC)

AUTOMATIC

POLARITY

CORRECTION

17 18

RHOS CHOS

DC-coupled

(TTL level)

vertical sync

(TTL level)

mode

detector

disable

4th mode

AC-coupled

(video)

PLL1 HORIZONTAL

OSCILLATOR HORIZONTAL

OUTPUT

PLL2

horizontal

flyback

SUPPLY AND

REFERENCE

VOLTAGE

PARABOLA

ADJUSTMENT

AND OUTPUT

VERTICAL

AMPLITUDE

ADJUSTMENT

AND OUTPUT

VERTICAL

OSCILLATOR

AMPLITUDE

CONTROL

VERTICAL

SYNC

INTEGRATOR

H + V

CLAMPING AND

BLANKING

GENERATOR

VGA/MULTI-

FREQUENCY

SWITCH

VGA MODE

DETECTOR

AND OUTPUT

AUTOMATIC

POLARITY

CORRECTION

VERTICAL

SYNC

SEPARATOR

(9.2 to 16 V)

E/W drive

horizontal drive

parabola

amplitude

+VB

differential vertical output

V supply

H supply

RVOS

158

clamping/

blanking

pulse

CVOS

CVA

12 13 5 6

vertical amplitude

TDA4850

Fig.1 Block diagram.

1997 Jun 05 4

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

PINNING

SYMBOL PIN DESCRIPTION

VP1 positive supply voltage

FLB 2 horizontal ﬂyback input

HOR 3 horizontal output

GND 4 ground (0 V)

VERT1 5 vertical output 1;

negative-going sawtooth

VERT2 6 vertical output 2;

positive-going sawtooth

MODE 7 4th mode output and mode detector

disable input

CLBL 8 clamping/blanking pulse output

HVS 9 horizontal sync/video input

VS 10 vertical sync input

EW 11 E/W output (parabola to driver stage)

CVA 12 capacitor for amplitude control

RVA 13 vertical amplitude adjustment input

REW 14 E/W amplitude adjustment input

(parabola)

RVOS 15 vertical oscillator resistor

CVOS 16 vertical oscillator capacitor

PLL1 17 PLL1 phase

RHOS 18 horizontal oscillator resistor

CHOS 19 horizontal oscillator capacitor

PLL2 20 PLL2 phase Fig.2 Pin configuration.

handbook, halfpage

FLB

HOR

GND

VERT1

VERT2

MODE

CLBL

HVS

PLL2

CHOS

RHOS

PLL1

RVOS

REW

CVOS

RVA

CVA

10 11

TDA4850

MEH168

1997 Jun 05 5

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

FUNCTIONAL DESCRIPTION

Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync

signal (H only or composite sync) is input on pin 9. Video

signals are clamped with top sync on 1.28 V, and are

sliced at 1.4 V. This results in a fixed absolute slicing level

of 120 mV related to top sync.

DC-coupled TTL sync signals are also sliced at 1.4 V,

however with the clamping circuit in current limitation.

The polarity of the separated sync is detected by internal

integration of the signal, then the polarity is corrected.

The polarity information is fed to the VGA mode detector.

The corrected sync is input signal for the vertical sync

integrator and the PLL1 stage.

Vertical sync separator, polarity correction and

vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to

pin 10. They are sliced at 1.4 V. The polarity of the

separated sync is detected by internal integration, then

polarity is corrected. The polarity information is fed to the

VGA mode detector. If pin 10 is not used, it must be

connected to ground.

The separated Vi(sync) signal from pin 10, or the integrated

composite sync signal from pin 9 (TTL or video) triggers

directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode

are decoded by the polarities of the horizontal and the

vertical sync input signals. An external resistor (from VP to

pin 7) is necessary to match this function. In all three VGA

modes the correct amplitudes are activated. The presence

of the 4th mode is indicated by HIGH on pin 7. This signal

can be used externally to switch any horizontal or vertical

parameters.

VGA mode detector input

For multi-frequency operation the voltage on pin 7 must be

externally forced to a level of <50 mV. Vertical amplitude

pre-settings for VGA are then inhibited. The delay time

between vertical trigger pulse and the start of vertical

deflection changes from 575 to 300 µs (575 µs is needed

for VGA). The vertical amplitude then remains constant in

a frequency range from 50 to 110 Hz.

Clamping and blanking generator

A combined clamping and blanking pulse is available on

pin 8 (suitable for the video preamplifier TDA4880).

The lower level of 2.1 V can be the blanking signal derived

from line flyback, or the vertical blanking pulse from the

internal vertical oscillator.

Vertical blanking equals to the delay between vertical sync

and start of vertical scan. By this, an optimum blanking is

achieved for VGA/XGA as well as for multi-frequency

operation (selectable via pin 7).

The upper level of 3.9 V is the horizontal clamping pulse

with internally fixed pulse width of 1 µs. A mono flop, which

is triggered by the trailing edge of the horizontal sync

pulse, generates this pulse.

PLL1 phase detector

The phase detector is a standard one using switched

current sources. The middle of the sync is compared with

a fixed point of the oscillator sawtooth voltage. The PLL

filter is connected to pin 17.

Horizontal oscillator

This oscillator is a relaxation type oscillator. Its frequency

is determined mainly by the capacitor on pin 19.

A frequency range of one octave is achieved by the current

on pin 18. The ϕ1 control voltage from pin 17 is fed via a

buffer amplifier and an attenuator to the current reference

pin 18 to achieve a high DC loop gain. Therefore, changes

in frequency will not affect the phase relationship between

horizontal sync pulses and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector.

Line flyback signals (pin 2) are compared with a fixed point

of the oscillator sawtooth voltage. Delays in the horizontal

deflection circuit are compensated by adjusting the phase

relationship between horizontal sync and horizontal output

pulses.

A certain amount of phase adjustments is possible by

injecting a DC current from an external source into the

PLL2 filter capacitor on pin 20.

1997 Jun 05 6

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Horizontal driver

This open-collector output stage (pin 3) can directly drive

an external driver transistor. The saturation voltage is

300 mV at 20 mA. To protect the line deflection transistor,

the horizontal output stage does not conduct at VP< 6.4 V

(pin 1).

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical

amplitude after changes in sync conditions.

The free-running frequency fo is determined by the values

of RVOS and CVOS. The recommended values should be

altered marginally only to preserve the excellent linearity

and noise performance. The vertical drive currents I5 and

I6 are in relation to the value of RVOS. Therefore, the

oscillator frequency must be determined only by CVOS on

pin 16.

fo1

10.8 RVOS

×CVOS

----------------------------------------------------

To achieve a stabilized amplitude the free-running

frequency fo (without adjustment) must be lower than the

lowest occurring sync frequency. The contributions shown

in Table 1 can be assumed.

Table 1 Calculation of fo total spread

Result for 50 to 110 Hz application:

CONTRIBUTING ELEMENTS %

Minimum frequency offset between fo and

the lowest trigger frequency 10

Spread of IC ±3

Spread of R (22 kΩ)±1

Spread of C (0.1 µF) ±5

Total 19

fo50 Hz

1.19

--------------- 42 Hz==

Table 2 VGA modes

MODE HORIZONTAL/VERTICAL

SYNC POLARITY

HORIZONTAL

FREQUENCY

(kHz)

VERTICAL

FREQUENCY

(Hz)

NUMBER OF

ACTIVE LINES MODE

OUTPUT PIN 7

1+/−31.45 70 350 LOW

2−/+ 31.45 70 400 LOW

3−/−31.45 60 480 LOW

4 +/+ ﬁxed by external circuitry −−HIGH

1997 Jun 05 7

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VPsupply voltage (pin 1) −0.5 +16 V

V3,7 voltage on pins 3 and 7 −0.5 +16 V

V8voltage on pin 8 −0.5 +7 V

Vnvoltage on pins 5, 6, 9, 10, 13,

14 and 18 −0.5 +6.5 V

I2current on pin 2 −±10 mA

I3current on pin 3 −100 mA

I7current on pin 7 −20 mA

I8current on pin 8 −−10 mA

Tamb operating ambient temperature 0 70 °C

Tjjunction temperature −150 °C

Tstg storage temperature −55 +150 °C

Vesd electrostatic handling for all pins note 1 −±300 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 65 K/W

1997 Jun 05 8

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

CHARACTERISTICS

VP= 12 V; Tamb =25°C; measurements taken in Fig.6; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VPsupply voltage (pin 1) 9.2 12 16 V

IPsupply current −40 −mA

Internal reference voltage

Vref internal reference voltage 6.0 6.25 6.5 V

TC temperature coefﬁcient Tamb = 20 to 100 °C−−±90 10−6/K

PSRR power supply ripple rejection f = 1 kHz sine wave 60 75 −dB

f = 1 MHz sine wave 25 35 −dB

VPsupply voltage (pin 1) to ensure all internal

reference voltages 9.2 −16 V

Composite sync input (AC-coupled; V10 =5V)

i sync sync amplitude of video input signal (pin 9) sync on green;

RS=50Ω−300 −mV

top sync clamping level 1.1 1.32 1.5 V

slicing level above top sync level 90 120 150 mV

RSallowed source resistance for 7% duty cycle Vi sync > 200 mV −−1.5 kΩ

r9differential input resistance during sync −80 −Ω

9charging current of coupling capacitor V9> 1.5 V 1.7 2.6 3.4 µA

tint vertical sync integration time to generate

sync pulse 71013µs

Horizontal sync input (DC-coupled, TTL-compatible)

Vi sync sync input signal (peak value; pin 9) 1.7 −−V

slicing level 1.2 1.4 1.6 V

tpminimum pulse width 700 −−ns

tr, tfrise time and fall time 10 −500 ns

I9input current V9= 0.8 V −−−200 µA

V9= 5.5 V −−10 µA

Automatic horizontal polarity switch (H-sync on pin 9)

tpH

/tHhorizontal sync pulse width related to tH

(duty cycle for automatic polarity correction) −−30 %

tpdelay time for changing sync polarity 0.3 −1.8 ms

Vertical sync input (DC-coupled, TTL-compatible; V-sync on pin 10)

Vi sync sync input signal (peak value; pin 10) 1.7 −−V

slicing level 1.2 1.4 1.6 V

I10 input current 0 < V10 < 5.5 V −−±10 µA

tpV maximum vertical sync pulse width for

automatic vertical polarity switch −−300 µs

1997 Jun 05 9

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Horizontal mode detector output (VGA mode)

V7output saturation voltage LOW

(for modes 1, 2 and 3) I7=6mA −0.275 0.33 V

output voltage HIGH mode 4 −−V

7load current to force VGA mode-dependent

vertical and parabola amplitudes modes 1, 2 and 3 2 −6mA

output current mode 4 −0−mA

VGA/multi-frequency mode switch

V7input voltage LOW to force

multi-frequency mode 0−50 mV

Horizontal comparator PLL1

V17 upper control voltage limitation −5.0 −V

lower control voltage limitation −1.2 −V

I17 control current see Fig.3 −±300 −µA

Horizontal oscillator

fosc centre frequency R18 =12kΩ (pin 18);

C19 = 2.2 nF (pin 19) −31.45 −kHz

∆fosc deviation of centre frequency −−±3.0 %

TC temperature coefﬁcient −−±150 10−6/K

ϕH/tHrelative holding/catching range ±6±6.5 ±7.3 %

R18 external oscillator resistor 9 −18 kΩ

V18 voltage at reference current input (pin 18) PLL1 and PLL2 locked;

Vref = 6.25 V −3.125 −V

∆V18 control voltage −±205 −mV

Horizontal PLL2; see Fig.3

V2upper clamping level of ﬂyback input I2=6mA −5.5 −V

lower clamping level of ﬂyback input I2=−1mA −−0.75 −V

H-ﬂyback slicing level −3.0 −V

I2input current H-scan; V8< 0.9 V −0.5 −−mA

H-ﬂyback; V8> 1.8 V −−−0.2 mA

td/tHdelay between middle of sync and middle of

H-ﬂyback related to tH

−3.2 −%

V20 upper control voltage limitation −4.6 −V

lower control voltage limitation −1.6 −V

I20 control current −±200 −µA

∆t/tHPLL2 control range related to tH30 −−%

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Jun 05 10

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Horizontal output (open-collector); see Fig.3

V3output voltage LOW I3=20mA −−0.3 V

I3=60mA −−0.8 V

tp/tHtH duty cycle 42 45 48 %

VPthreshold to activate too low supply voltage

protection horizontal output off −5.3 −V

horizontal output on −5.6 −V

Horizontal clamping/blanking generator output; see Fig.3

V8output voltage LOW H and V scanning −−0.9 V

blanking output voltage internal V blanking 1.8 2.1 2.4 V

external H blanking 1.8 2.1 2.4 V

clamping output voltage H-sync on pin 9 3.5 3.9 4.3 V

I8internal sink current for all output levels H and V scanning 2.3 2.9 3.5 mA

t8clamping pulse start with end of H-sync

tclp clamping pulse width 0.8 1.0 1.2 µs

S steepness of rise and fall times −40 −ns/V

Vertical oscillator (Vref = 6.25 V)

fovertical free-running frequency R15 =22kΩ;

16 = 0.1 µF40 42 43.3 Hz

fVnominal vertical sync range no fo adjustment 50 −110 Hz

V15 voltage on pin 15 R15 =22kΩ2.8 3.0 3.2 V

tddelay between sync pulse and start of

vertical scan measured on pin 8

in VGA/XGA mode, activated by an

external resistor on pin 7 500 575 650 µs

in multi-frequency mode V7< 50 mV 240 300 360 µs

I12 control current for amplitude control −±200 −µA

12 capacitor for amplitude control −−0.33 µF

Vertical differential output; see Fig.4

Iodifferential output current between

pins 5 and 6 (peak-to-peak value) mode 3; I13 >−135 µA;

R15 =22kΩ0.9 1.0 1.1 mA

maximum offset current error Io=1mA −−±2.5 %

maximum linearity error −−±1.5 %

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Jun 05 11

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Notes to the Characteristics

1. ∆Io/∆t relative to value of mode 3.

2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment.

Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14.

Vertical amplitude adjustment (in percent of output signal)

V13 input voltage −5.0 −V

I13 adjustment current Io max (100%) −110 −120 −135 µA

Io min (typically 58%) −0−µA

∆I

/∆t VGA mode-dependent pre-settings

activated by an external resistor on pin 7 note 1; see Table 2

mode 1 116.1 116.8 117.5 %

mode 2 102.0 102.2 102.5 %

mode 3 −100 −%

mode 4 −100 −%

multi-frequency operation (VGA operation

disabled) V7<50mV −100 −%

E/W output; note 2

V11 bottom output signal during mid-scan

(pin 11) internally stabilized 1.05 1.2 1.35 V

top output signal during ﬂyback 4.1 4.35 4.6 V

TC temperature coefﬁcient of output signal −−250 10−6/K

E/W amplitude adjustment (parabola); see Fig.4

V14 input voltage (pin 14) −5.0 −V

I14 adjustment current 100% parabola −110 −120 −135 µA

typically 28% parabola −0−µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Jun 05 12

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Fig.3 Horizontal timing diagram.

handbook, full pagewidth

MEH170

4.6 V

1.6 V

PLL2 control range

(minimum 30%)

sawtooth of

horizontal

oscillator

control

current

of PLL1

clamping and

blanking pulses

on pin 8

line flyback

pulse

on pin 2

current

control

of PLL2

horizontal output

pulse with

45% duty cycle

1 µs clamping pulse

2.1 V H + V

blanking pulse

39.5%

42.5%

15% 85%

H-sync (VGA)

0.7 V

3.9 V

1997 Jun 05 13

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

Fig.4 Vertical and E/W timing diagram.

(1) In multi-frequency mode.

(2) For free-running oscillator.

handbook, full pagewidth

MHA711

,,,,,,,,,,

100 µs150 µs50 µs(1)

325 µs19.4 to 8.5 ms

(50 to 110 Hz)

1.2 V

4.5 V

3.8 V

4.0 V(2)

sawtooth

voltage

on pin 16

internal

timing

pulse

V trigger

pulse

trigger

inhibit

window

amplitude

control

pulse

vertical

blanking pulse

on pin 8

differential

output currents

E/W parabola

on pin 11

2.1 V

1.4 V

0.7 V

550 µA on pin 6

50 µA on pin 5

1997 Jun 05 14

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

INTERNAL CIRCUITRY

ook, full pagewidth

MEH258

20 Ω

80 Ω

1.4 V

TDA4850

4 V

5 V

3.1 V

7.3 V

1.2 V

1.6

all inputs

and outputs

protected in this

way except

pins 2, 9 and 10

kΩ

Vref

clamping

3.9 V 2 ×

7.3 V

7 × VBE

1.4

blanking

2.1 V

5 V 5 V

3 V

1 kΩ

2 kΩ80 Ω

2 kΩ

1.4 V

7.3 V7.3 V

1.4 V

3 mA

7.3 V

1.28 V

98 765432

3 V

11 12 13 14 15 16 17 18 19 20

HVS CLBL MODE VERT2

Vref

VERT1 GND HOR FLB VP

EW CVA

Vref

RVA REW RVOS CVOS RHOS CHOS

PLL1 PLL2

300 µA200

µA

200

µA

260 µA

300 µA

Fig.5 Internal circuit.

1997 Jun 05 15

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

TEST AND APPLICATION INFORMATION

Fig.6 Test and application circuit (measurements taken at VP= 12 V).

andbook, full pagewidth

MEH169

2.2

(2%) 2.2

E/W output vertical

amplitude parabola

amplitude

kΩ

220

kΩ

(1%)

kΩ

(1%)

220

kΩ

kΩ39

kΩ

2.7 kΩ

0.22

µF

0.1

µF

(5%)

220

pF 2.2

11 12 13 14 15 16 17 18 19 20

composite sync

horizontal TTL syncVi sync

vertical TTL sync

mode detector

disable

LOW

HIGH 9876

TDA4850

543

47 nF

47 nF vertical

differential

output

4th

mode

clamp/blank

pulses

H-output

H-flyback

VP = 9.2 to 16 V

1997 Jun 05 16

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

PACKAGE OUTLINE

UNIT A

max. 1 2 b1cD E e M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-1 92-11-17

95-05-24

min. A

max. bZ

max.

1.73

1.30 0.53

0.38 0.36

0.23 26.92

26.54 6.40

6.22 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.04.2 0.51 3.2

0.068

0.051 0.021

0.015 0.014

0.009 1.060

1.045 0.25

0.24 0.14

0.12 0.010.10 0.30 0.32

0.31 0.39

0.33 0.0780.17 0.020 0.13

SC603

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)

(1) (1)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1997 Jun 05 17

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“IC Package Databook”

(order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (Tstg max). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not

more than 2 mm above it. If the temperature of the

soldering iron bit is less than 300 °C it may remain in

contact for up to 10 seconds. If the bit temperature is

between 300 and 400 °C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

1997 Jun 05 18

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

NOTES

1997 Jun 05 19

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and multi-frequency monitors TDA4850

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

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Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Rua do Rocio 220, 5th floor, Suite 51,

04552-903 São Paulo, SÃO PAULO - SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands 547047/1200/03/pp20 Date of release: 1997 Jun 05 Document order number: 9397 750 02184