DFE-T Version 1.2 - Infineon Technologies

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Quad ISDN 4B3T Echocanceller Digital Front End

Q uad IEC DF E - T

PEB 24901 Version 1.2

PEF 24901 Version 1.2

Delta Sheet 06.96 T2490-112-L1-7600

Ed ition 06.96

This edition was realized using the software system FrameMaker



Published by Siemens AG,

HL IT

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PEB 24901

Revision History: Original version 06.96

Previous Releases: none

Page Subjects (changes since last revision)

Quad ISDN 4B3T Echocanceller Digital Front End

(Quad IEC DFE-T) PEB 24901

PEF 24901

Delta Sheet CMOS

Semico ndu cto r Grou p 4 06.96

This Delta Sheet refers to the PEB 24901 V1.1 as described in the "Preliminary

Data Sheet 2.95" and the "Errata Sheet 01.96".

The Quad IEC DFE-T V1.2 is an enhancement of the Quad IEC DFE-T V1.1. Being

compatible to the V1.1, it provides the following new features:

1. IOM-Interface clock frequencies 2048 kHz and 8192 kHz added

2. Monitor message RST corrected

3. Boundary scan functions adapted

4. Power-on reset function enhanced

5. LT Repeater mode added

6. Delay in upstream direction changed in some operation modes

1 IOM-Inte rfa ce Cloc k Frequencie s

The data clock frequency to be applied to pin DCL of the IOM interface may be 2048 kHz,

4096 kHz or 8096 kHz. Hence, either 4, 8 or 16 IOM-Channels are provided. The

selection is done with two newly defined pins and the pin SLOT being renamed to

SLOT0. Please refer to the Preliminary Data Sheet 2.95 of the PEB 24901 version 1.1 for

a complete description of all pins. The following table lists new pins and pins with new

functions only. SLOT2 is reserved for future use in order to cope with 32 IOM channels.

Pin No. Symbol Input (I)

Output (O) Description

55 SLOT 0 I IOM slot selection 0.

Least significant bit.

45 SLOT1 I IOM-slot selection 1.

Internal Pulldown.

32 SLOT 2 I IOM slot selection 2.

Most significant bit. Reserved for future use.

Connect to GND or leave open. Internal

Pulldown.

PEB 24901

PEF 24901

Semiconductor Group 5 06.96

The IOM Channel selection is:

2 Monitor Message RST

The second byte of the free running Monitor message "Report Status of ST i1, STi0" is not

corrupted to FFH anymore.

3 Boundary Scan

• The pins TDI and TMS have an internal pullup resistor.

• The content of the IDCODE-register of the boundary scan has been incremented to

0010.

• The new pins SLOT2 and SLOT1 pins are inclu ded in the in the bo undary sc an. The

table below gives the complete sequence:

SLOT2 SLOT1 SLOT0 Slots of ports

0..3 minimum DCL freq. (kHz)

0 0 0 0..3 2048

0 0 1 4..7 4096

0 1 0 8..11 8192

0 1 1 12..15

1 x x reserved for future use

Boundary Scan

Number

TDI ––>

Pin Number Pin Name Type Number of

Scan Cells

163TP1I 1

262TP2I 1

361CLS3O2

4 60 RESQ I 1

556TSPI 1

655SLOT0I 1

753LTI 1

852CLS2O2

951D3DI/O3

10 50 D2D O 2

11 49 TP3 I 1

Semico ndu cto r Grou p 6 06.96

PEB 24901

PEF 24901

12 48 D1D I/O 3

13 47 D0D I/O 3

14 46 D3C I/O 3

15 45 SLOT1 I1

16 44 D2C I/O 3

17 43 D1C I/O 3

18 42 D0C I/O 3

19 40 D3B I/O 3

20 39 D2B O 2

21 37 D1B O 2

22 35 D0B O 2

23 34 D3A O 2

24 33 D2A O 2

25 32 SLOT2 I1

26 31 D1A O 2

27 30 D0A O 2

28 29 CLS0 O 2

29 28 ST00 I 1

30 27 ST01 I 1

31 26 ST10 I 1

32 24 ST11 I 1

33 23 ST20 I 1

34 21 ST21 I 1

35 20 CLS1 O 2

36 19 ST30 I 1

37 18 ST31 I/O 3

38 17 SDX O 2

39 15 DOUT O 2

40 14 DIN I 1

41 13 FSC I/O 3

Boundary Scan

Number

TDI ––>

Pin Number Pin Name Type Number of

Scan Cells

PEB 24901

PEF 24901

Semiconductor Group 7 06.96

Note: I/O pins are bidirectional only for device test purpose. For the function of these

pins refer to section 1.2 of th e Pre liminar y Da ta Sheet 2.9 5.

4 Power-on Reset

Proper operation of the internal power-on-reset is now provided, if the supply voltage has

been below 1.0 V before applying power again.

5 LT Repeater Mode

An LT-Repeater Mode programmable via Monitor command individually for all four ports

is provided. The LT-RP Mode is enabled with the Monitor command 8150H. It is disabled

with the Monitor command 8110H. The LT-RP Mode is disabled after power-on and

reset. The state diagram of the LT-RP mode is given in fig. 1. Actication diagrams are

depicted in the Preliminary Data Sheet 2.95 section 3.4.1, pages 34ff.

6 Delay in Upstream Direction

In Upstream direction there is an additional delay of 125µs (one IOM-frame) in LT Mode

when a DCL frequency not equal to 4096 kHz is applied and in LT-RP Mode with all

possible DCL frequencies.

42 12 DCL I/O 3

43 11 PDM0 I 1

44 10 PDM1 I/O 3

45 8 PDM2 I 1

46 7 PDM3 I 1

47 5 SDR I/O 3

48 4 CL15 I 1

Boundary Scan

Number

TDI ––>

Pin Number Pin Name Type Number of

Scan Cells

Semico ndu cto r Grou p 8 06.96

PEB 24901

PEF 24901

Figure 1

State Diagram of the LT Repeater Mode

ITD09336

Deac. Acknowledge

U0, DIU DA,0U

Deactivating

DIU,0U DownPower

DID

Start Awaking

2WU , ARU

ARD

{12ms}

Awake Signal

U0, ARUSent

AWT

(TE&/AR2)

}

ms12{

(ARD

}ms7{

(/AR2&AWR)

ARU,0U

Sent/ReceivedAck.

NT-RP Synchronizing

U2A, ARU

(AR2&TE)

Synchronizing

AID

TransmissionData4U , AIU/RSYU

Sending Awake-Ack.

U2W, ARU

AWR

(TE 0)

{0.5 ms }

}ms7{

}ms12{

AR2

AWR

AWT

{7 ms }

Maintenance

U0/ , DA/HI

ANY STATE

State

ARL

{12ms}

DR TEST

(PFOFF&/ARL

| LTD| RES| SSP)

|RSYD)

ARD

(U1| U3)

U4, ARU

AIUU4,

Synchronizing