v5.4 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance * * * * * * * * * * SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy (TMR) - Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg - SEU Rate < 10-10 Errors/Bit-Day in Worst-Case Geosynchronous Orbit Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with Use of Error Detection and Correction (EDAC) IP (included) with Integrated SRAM Scrubber - Single-Bit Correction, Double-Bit Detection - Variable-Rate Background Refreshing Total Ionizing Dose Up to 300 krad (Si, Functional) Single-Event Latch-Up Immunity (SEL) to LETTH > 117 MeVcm2/mg TM1019 Test Data Available Single Event Transient (SET) - No Anomalies up to 150 MHz Specifications * * * * * * B-Flow - MIL-STD-883B E-Flow - Actel Extended Flow EV-Flow - Class V Equivalent Flow Processing Consistent with MIL-PRF 38535 * * * Prototyping Options * * * Commercial Axcelerator Devices for Functional Verification RTAX-S PROTO Devices with Same Functional and Timing Characteristics as Flight Unit in a Non-Hermetic Package Low Priced Reprogrammable ProASIC(R)3 Option for Functional Verification * RTAX-SL Low Power Option * Up to 4 Million Equivalent System Gates or 500 k Equivalent ASIC Gates Up to 20,160 SEU-Hardened Flip-Flops Up to 840 I/Os Up to 540 kbits Embedded SRAM Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883, TM3015) Features Processing Flows * * * High-Performance Embedded FIFOs 350+ MHz System Performance 500+ MHz Internal Performance 700 Mb/s LVDS Capable I/Os Offers Approximately Half the Standby Current of the Standard RTAX-S Device at Worst-Case Conditions * * Single-Chip, Nonvolatile Solution 1.5 V Core Voltage for Low Power Flexible, Multi-Standard I/Os: - 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation - Bank-Selectable I/Os - 8 Banks per Chip - Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI - JTAG Boundary Scan Testing (as per IEEE 1149.1) - Differential I/O Standards: LVPECL and LVDS - Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 - Hot-Swap Compliant with Cold-Sparing Support (Except PCI) Embedded Memory with Variable Aspect Ratio and Organizations: - Independent, Width-Configurable Read and Write Ports - Programmable Embedded FIFO Control Logic - ROM Emulation Capability Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability Table 1 * RTAX-S/SL Family Product Profile Device Capacity Equivalent System Gates ASIC Gates Modules Register (R-cells) Combinatorial (C-cells) Flip-Flops (maximum) Embedded RAM/FIFO (without EDAC) Core RAM Blocks Core RAM Bits (K = 1,024) Clocks (segmentable) Hardwired Routed I/Os I/O Banks User I/Os (maximum) I/O Registers Package CCGA/LGA CQFP May 2009 (c) 2009 Actel Corporation RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL 250,000 30,000 1,000,000 125,000 2,000,000 250,000 4,000,000 500,000 1,408 2,816 2,816 6,048 12,096 12,096 10,752 21,504 21,504 20,160 40,320 40,320 12 54 k 36 162 k 64 288 k 120 540 k 4 4 4 4 4 4 4 4 8 198 744 8 418 1,548 8 684 2,052 8 840 2,520 624 208, 352 624 352 624, 1152 256, 352 1272 352 i See the Actel website for the latest version of the datasheet. RTAX-S/SL RadTolerant FPGAs Ordering Information RTAX2000S/SL _ 1 CGS 624 B Application B = MIL-STD 883 Class B E = E-Flow (Actel Space-Level Flow) EV = Class V Equivalent Flow Processing Consistent with MIL-PRF 38535 Package Lead Count Package Type CQ = Ceramic Quad Flat Pack CG = Ceramic Column Grid Array LG = Land Grid Array S = Six Sigma Column Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard (applies to RTAX250S/SL, RTAX1000S/SL. RTAX2000S/SL) 1 = Approximately 10% Faster than Standard (applies to RTAX4000S/SL) Part Number S = SL = RTAX250S/SL = RTAX1000S/SL = RTAX2000S/SL = RTAX4000S/SL = Standard Family Low-Power Option 250,000 Equivalent System Gates 1,000,000 Equivalent System Gates 2,000,000 Equivalent System Gates 4,000,000 Equivalent System Gates Note: PROTO refers to the RTAX-S/SL Prototype Units. All CCGA PROTO units will be offered with the Six Sigma Column. Temperature Grade Offerings Package CQ208 RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL B, E, EV - - - CQ256 - - B, E, EV - CQ352 B, E, EV B, E, EV B, E, EV B, E, EV CG624/LG624 B, E, EV B, E, EV B, E, EV - CG1152/LG1152 - - B, E, EV - CG1272/LG1272 - - - B, E, EV Note: B = MIL-STD-883 Class B E = E-Flow (Actel Space-Level Flow) EV = Actel "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535) ii v5.4 RTAX-S/SL RadTolerant FPGAs Speed Grade and Temperature Grade Matrix RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL STD -1 Notes: 1. Data applies to B,E,EV flow devices. 2. Contact your Actel representative for availability. Device Resources User I/Os (Including Clock Buffers) RTAX250S/SL RTAX1000S/SL RTAX2000S/SL 115 - - - - 136 198 198 198 232 418 418 - - 684 - - - Device CQ208 CQ256 CQ352 CG624/LG624 CG1152/LG1152 CG1272/LG1272 RTAX4000S/SL - - 166 - - 840 Note: CQFP = Ceramic Quad Flat Pack and CCGA = Ceramic Column Grid Array, LGA = Land Grid Array I/Os per Package Package Device Single-Ended Differential Pair Pair Total I/Os CQ208 RTAX250S 7 41 13 115 CQ256 RTAX2000S 4 66 0 136 CQ352 RTAX250S 2 98 0 198 RTAX1000S 2 98 0 198 RTAX2000S 2 98 0 198 RTAX4000S 4 81 0 166 RTAX250S 0 124 0 248 RTAX1000S 68 170 5 418 RTAX2000S 52 178 5 418 CG1152 RTAX2000S 0 342 0 684 CG1272 RTAX4000S 0 420 0 840 CG624 v5.4 iii RTAX-S/SL RadTolerant FPGAs Actel MIL-STD-883 Class B Product Flow Table 2 * Actel MIL-STD-883 Class B Product Flow for RTAX-S/SL1, 2 Step Screen Method Requirement 1 Internal Visual 2 Serialization 3 Temperature Cycling 1010, Condition C, 10 cycles minimum 100% 4 Constant Acceleration 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 Condition A3 for LG1272, CQ352 100% 5 Particle Impact Noise Detection 2020, Condition A 100% 6 Seal (Fine & Gross Leak Test) 1014 100% 7 Pre-Burn-In Electrical Parameters In accordance specification device 100% 8 Dynamic Burn-In 1015, Condition D, 160 hours at 125C or 80 hours at 150C minimum 100% 9 Interim (Post-Burn-In) Electrical Parameters In accordance specification 100% 10 Percent Defective Allowable (PDA) Calculation 5% 11 12 Final Electrical Test 2010, Condition B 100% 100% 2 with with applicable applicable Actel Actel In accordance with applicable Actel specification, which includes a, b, and c: a. Static Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 b. Functional Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b c. Switching Tests at 25C 5005, Table 1, Subgroup 9 External Visual 2009 device All Lots device 100% 100% Notes: 1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 2. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125C final electrical test. 3. Condition A applies to RTAX4000S/SL packages only. iv v5.4 RTAX-S/SL RadTolerant FPGAs Actel Extended Flow Table 3 * Actel Extended Flow for RTAX-S/SL1, 2, 3, 4 Step Screen 1 5 Method Requirement Destructive Bond Pull 2011, Condition D Extended Sample 2 Internal Visual 2010, Condition A 100% 3 Serialization 4 Temperature Cycling 1010, Condition C, 10 cycles minimum 5 Constant Acceleration 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 Condition A5 for LG1272, CQ352 6 Particle Impact Noise Detection 2020, Condition A 100% 7 Radiographic (X-Ray) 2012, One View (Y1 Orientation) Only 100% 8 Pre-Burn-In Electrical Parameters In accordance specification 9 Dynamic Burn-In 1015, Condition D, 240 hours at 125C or 120 hours at 150C minimum 10 Interim (Post-Dynamic-Burn-In) Parameters 11 100% 100% 1015, Condition C, 72 hours at 150C or 144 hours at 125C minimum 100% 12 Interim (Post-Static-Burn-In) Electrical Parameters In accordance specification 100% 13 Percent Defective Allowable (PDA) Calculation 5% Overall, 3% Functional Parameters at 25C All Lots In accordance with applicable Actel specification, which includes a, b, and c: 100% 14 applicable a. Static Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 b. Functional Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b Actel device Static Burn-In with applicable Actel 100% Final Electrical Test with applicable device 4 Electrical In accordance specification with 100% Actel device device c. Switching Tests at 25C 5005, Table 1, Subgroup 9 15 Seal (Fine & Gross Leak Test) 1014 100% 16 External Visual 2009 100% Notes: 1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel is offering this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. 2. The Quality Conformance Inspection (QCI) for Extended Flow devices still comply to MIL-STD-833, Class B requirement. 3. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 4. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125C final electrical test. 5. Condition A applies to RTAX4000S/SL packages only. 6. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis. v5.4 v RTAX-S/SL RadTolerant FPGAs Actel "EV" Flow (Class V Flow Equivalent Processing) Table 4 * Actel "EV" Flow (Class V Equivalent Flow Processing) for RTAX-S/SL1, 2, 3 Step Screen Method Requirement 1 Destructive Bond Pull4 2011, Condition D Extended Sample 2 Internal Visual 2010, Condition A 100% 3 Serialization 100% 4 Temperature Cycling 1010, Condition C, 50 cycles minimum 100% 5 Constant Acceleration 100% 6 Particle Impact Noise Detection 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 Condition A5 for LG1272, CQ352 2020, Condition A 7 Radiographic (X-Ray) 2012, One View (Y1 Orientation) Only 100% 8 Pre-Burn-In Electrical Parameters 9 10 11 12 13 14 100% In accordance with applicable Actel device specification Dynamic Burn-In 1015, Condition D, 240 hours at 125C or 120 hours at 150C minimum Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance with applicable Actel device specification Static Burn-In 1015, Condition C, 72 hours at 150C or 144 hours at 125C minimum Interim (Post-Static-Burn-In) Electrical Parameters In accordance with applicable Actel device specification Percent Defective Allowable (PDA) Calculation 5% Overall, 3% Functional Parameters at 25C Final Electrical Test3 In accordance with applicable Actel specification, which includes a, b, and c: a. Static Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 b. Functional Tests (1) 25C (2) -55C and +125C 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b device 100% 100% 100% 100% 100% All Lots 100% 5005, Table 1, Subgroup 9 15 c. Switching Tests at 25C Seal (Fine & Gross Leak Test) 1014 100% 16 External Visual 2009 100% 17 Wafer Lot Specific Life Test (Group C) MIL-PRF-38535, Appendix B, sec. B.4.2.c All Wafer Lots Notes: 1. Actel offers "EV" flow for users requiring full compliance to MIL-PRF-38535 class V requirement. The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow devices) with the intention to be in full compliance to MIL-PRF-38535 Table IA and Appendix B requirement, but without the official class V certification from DSCC. 2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 3. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125C final electrical test. 4. Condition A applies to RTAX4000S/SL packages only. 5. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis. vi v5.4 RTAX-S/SL RadTolerant FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Low-Cost Prototyping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Detailed Specifications Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102 Package Pin Assignments 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 1152-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 1272-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 4-7 v5.4 vii RTAX-S/SL RadTolerant FPGAs General Description RTAX-S/SL offers high performance at densities of up to four million equivalent system gates for space-based applications. Based upon the Actel commercial Axcelerator(R) family, RTAX-S/SL has several system-level features such as embedded SRAM (with built-in FIFO control logic), segmentable clocks, chip-wide highway routing, and carry logic. the entire floor of the RTAX-S/SL device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element Featuring SEU-hardened flip-flops that offer the benefits of user-implemented Triple Module Redundancy (TMR) without the associated overhead, the RTAX-S/SL family is the second generation Actel product offering for space applications. The RTAX-S/SL devices are manufactured using a 0.15 m technology at a UMC facility in Taiwan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. The RTAX-S/SL family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, lowimpedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the RTAX-S family abundant routing resources. Device Architecture Actel RTAX-S/SL architecture, derived from the highlysuccessful A54SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike traditional FPGAs, Routing Switch Matrix Logic Block Sea-of-Modules Architecture Traditional FPGA Architecture Logic Modules Figure 1-1 * Sea-of-Modules Comparison v5.4 1-1 RTAX-S/SL RadTolerant FPGAs Figure 1-2 * RTAX-S/SL Family Interconnect Elements The very nature of Actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock(R) technology). Cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-101). Actel's RTAX-S/SL family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The RTAX-S/SL C-cell can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). The C-cell contains carry logic for even more efficient implementation of arithmetic functions. With its small size, the C-cell structure is extremely synthesis-friendly, simplifying the overall design as well as reducing design time. While each SEU-hardened R-cell appears as a single D-Type flip-flop to the user, each is implemented in silicon using triple redundancy to achieve a LET threshold of greater than 60 MeV-mg/cm2. Each TMR R-cell consist of three master-slave latch pairs, each with asynchronous self-correcting feedback paths. The output of each latch on the master or slave side votes with the outputs of the other two latches on that side. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents that change from feeding back and permanently latching. Care was also 1 -2 v5.4 taken in the layout to ensure that a single ion strike could not affect more than one latch (see "R-Cell" on page 2-66 for more details). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure 1-3 on page 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. Two C-cells, a single R-cell, and two Transmit (TX) and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4 on page 1-3). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-route tool, minimizing system delays while improving logic utilization. The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-side, giving a C-C-R - C-C-R pattern to the SuperCluster. This C-C-R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). The RTAX-S/SL architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. RTAX-S/SL RadTolerant FPGAs FCI A[0:1] B[0:1] D[0:3] DB CFN C-cell D E CLK Y PRE Q CLR (Positive Edge Triggered) FCO C-Cell R-Cell Figure 1-3 * RTAX-S/SL C-Cell and R-Cell C C TX TX RX RX TX TX RX RX C R B C R Figure 1-4 * RTAX-S/SL SuperCluster FCI DCOUT C-Cell C-Cell Y Y Carry Logic FCO Figure 1-5 * RTAX-S/SL Two-Bit Carry Logic v5.4 1-3 RTAX-S/SL RadTolerant FPGAs At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the RTAX1000S/SL is composed of a 3x3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the RTAX250S/SL). The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6). Table 1-1 * Number of Core Tiles per Device Device Number of Core Tiles RTAX250S/SL 4 smaller tiles RTAX1000S/SL 9 regular tiles RTAX2000S/SL 16 regular tiles RTAX4000S/SL 30 regular tiles SuperCluster C 4k RAM/ FIFO 4k RAM/ FIFO Chip Layout 4k RAM/ FIFO 4k RAM/ FIFO R TX TX RX RX RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC I/O Structure Figure 1-6 * RTAX-S/SL Device Architecture (RTAX1000S/SL shown) 1 -4 C v5.4 SC SCTile SC Core SC B TX TX RX RX C C R RTAX-S/SL RadTolerant FPGAs Embedded Memory I/O Logic As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspectratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. The RTAX-S/SL family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5 V, 1.8 V, 2.5 V, and 3.3 V. In all, RTAX-S/SL FPGAs support at least 14 different I/O standards (single-ended, differential, voltagereferenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-12 for more information). All I/O standards are available in each bank. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-6). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. By design, all user flip-flops in the RTAX-S FPGAs are immune to SEUs including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. Routing The FIFO control unit was not implemented with SEUhardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. The RTAX-S/SL hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. Actel has enhanced the SEU tolerance of the embedded SRAM within RTAX-S/SL by employing the use of two upset-mitigation techniques: * Actel has developed Error Detection and Correction (EDAC) IP for use with RTAX-S/SL. EDAC can be accomplished by the use of SmartGen-generated Error Correcting Codes (ECC) IP, which employs the use of shortened Hamming Codes * A background memory-refresher, or scrubber circuitry, which has been embedded into the EDAC IP. The embedded scrubber circuitry periodically refreshes memory in the background to ensure that no data corruption occurs while the memory is not in use. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the carry-logic FCO output of one C-cell pair to the carry-logic FCI input of the C-cell pair of the SuperCluster below. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. The use of EDAC IP combined with the embedded memory scrubber circuitry, gives the RTAX-S/SL an SEU radiation performance level of better than 10-10 errors/ bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. v5.4 1-5 RTAX-S/SL RadTolerant FPGAs I/O Module InReg OutReg EnReg I O B A N K 4k RAM/ FIFO I/O Module TX RX RX 4k RAM/ FIFO 4k RAM/ FIFO CoreTile 4k RAM/ FIFO Figure 1-7 * I/O Cluster Arrangement Figure 1-8 * RTAX-S/SL Routing Structures 1 -6 v5.4 TX B RX RX I/O Module I/O Cluster RTAX-S/SL RadTolerant FPGAs Global Resources annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, the Actel integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). Both these clocks can be segmented, allowing significantly more than eight clock domains to be implemented in the devices. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. The RTAX1000S/SL, RTAX2000S/SL, and RTAX4000S/SL devices have 12 HCLK segments per tile and 28 RCLK segments per tile. The RTAX250S/SL has 8 HCLK segments per tile and 22 RCLK segments per tile. Programming Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. Programming support is provided through Actel Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI. Factory programming is available for highvolume production needs. Design Environment The RTAX-S/SL family of FPGAs is fully supported by both Actel Libero(R) Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Actel website). Libero IDE includes Synplify(R) AE from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), and Designer software from Actel. Low-Cost Prototyping Solutions Since the enhanced radiation characteristics of radiationtolerant devices are not required during the prototyping phase of the design, Actel has developed two prototyping options for RTAX-S/SL. For early design development and functional verification, Actel offers the commercial Axcelerator devices while for final flight design verification in hardware, Actel offers the RTAX-S PROTO device that has the same form, fit, and function as the flight silicon. Prototyping with Axcelerator Units The prototyping solution using the commercial Axcelerator devices consists of two parts: Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: * A well-documented design flow that allows the customer to target an RTAX-S/SL design to the equivalent commercial Axcelerator device A set of Actel Extender circuit boards that map the commercial device package to the appropriate RTAX-S package footprint * Timer - a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route * * NetlistViewer - a design netlist schematic viewer * ChipPlanner - a graphical floorplanner viewer and editor This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Actel FPGAs. * SmartPower - allows the designer to quickly estimate the power consumption of a design Prototyping with RTAX-S PROTO Units * PinEditor - a graphical application for editing pin assignments and I/O attributes * I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format The RTAX-S PROTO units offer a prototyping solution that can be used for final timing verification of the flight design. The RTAX-S PROTO prototype units have the same timing attributes as the RTAX-S/SL flight units. Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in their part number, and "PROTO" is marked on devices to indicate that they are not intended for space flight. They With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, the Actel back- v5.4 1-7 RTAX-S/SL RadTolerant FPGAs and analyze any signal inside the FPGA without disturbing normal device operation. Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II (Figure 1-9), the Actel integrated verification and logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG port (See "Silicon Explorer II Probe Interface" on page 2-102). also are not intended for applications, which require the quality of space-flight units, such as qualification of space-flight hardware. RT-PROTO units offer no guarantee of hermeticity, and no MIL-STD-883B processing. At a minimum, users should plan on using class B level devices for all qualification activities. The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full military temperature range. The RT-PROTO units will also be offered in -1 or standard speed grades, so as to enable customers to validate the timing attributes of their space designs using actual flight silicon. In addition, Actel offers a Configurable Logic Analyzer Module (CLAM), which allows a real-time verification and debug capability to be embedded into IP programmed into Actel FPGAs. CLAM allows signals from the inside of the IP core to be routed to the exterior of the chip for verification purposes. Prototyping with ProASIC3E Reprogrammable Units Using Actel's ProASIC3E prototyping solution offers the unique advantage of reprogrammability, resulting in cost savings while providing faster functional verification of designs in prototype stage. This methodology employs a footprint compatible adaptor board and an EDIF netlist and pinout convertor for easy migration. Summary The Actel RTAX-S/SL family of FPGAs extends the successful RTSX-SU family of radiation-tolerant FPGAs, adding embedded RAM, FIFOs, and high-speed I/Os. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an RTAX-S/SL design yet still achieve high performance and efficient device utilization in an SEUhardened device. Please see the application note Prototyping for RTAX-S and RTAX-SL Devices for more details. In-System Diagnostic and Debug Capabilities The RTAX-S/SL family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe RTAX-S/SL FPGAs 16-Pin Connection TDI* TCK* Serial Connection TMS* Silicon Explorer II TDO* PRA* PRB* 22-Pin Connection CH3/PRC* CH4/PRD* Additional 14 Channels (Logic Analyzer) Note: *Refer to the "Pin Descriptions" on page 2-11 for more information. Figure 1-9 * Probe Setup 1 -8 v5.4 RTAX-S/SL RadTolerant FPGAs Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf Differences Between RTAX-S/SL and Axcelerator http://www.actel.com/documents/RTAXS_AX_Features_AN.pdf Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs http://www.actel.com/documents/EDAC_AN.pdf Prototyping for RTAX-S and RTAX-SL Devices http://www.actel.com/documents/PrototypingRTAXS_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Actel CQFP to FBGA Adapter Socket Instructions http://www.actel.com/documents/CCGA_FBGA_AN.pdf Actel CCGA to FBGA Adapter Socket Instructions http://www.actel.com/documents/CQ352-FPGA_Adapter_AN.pdf IEEE Standard 1149.1 (JTAG) in the Axcelerator Family http://www.actel.com/documents/AX_JTAG_AN.pdf User's Guides and Manuals Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User's Guide http://www.actel.com/documents/smarttime_ug.pdf Silicon Sculptor User's Guide http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf Silicon Explorer II User's Guide http://www.actel.com/documents/Silexpl_UG.pdf White Papers Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.actel.com/documents/AntifuseSecurityWP.pdf RTAX-S/SL Testing and Reliability Update http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf Miscellaneous Libero IDE flow diagram http://www.actel.com/products/software/libero/#flow v5.4 1-9 RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 * I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI Yes No Yes2 LVCMOS2.5 V No Yes No Enabled/Disabled LVCMOS1.8 V No Yes No Enabled/Disabled LVCMOS1.5 V (JESD8-11) No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled Differential, LVDS/LVPECL, Input No Yes No Enabled Disabled3 Differential, LVDS/LVPECL, Output No Yes No Disabled Enabled4 Notes: 1. Default setting for the clamp diode is set to be PCI. The LVTTL clamp diode is not enabled by default. To allow 5 V tolerance, the LVTTL clamp diode needs to be enabled using settings in Designer. Hot-insertion and cold-sparing are not supported when the clamp diode is enabled. 2. Can be implemented with an external resistor. 3. The OE input of the output buffer is automatically deasserted by Designer. 4. The OE input of the output buffer is automatically asserted by Designer. 5 V Tolerance 3.3 V PCI and 3.3 V LVTTL (with clamp diode enabled) I/O standards directly allow 5 V tolerance. For example, the 3.3V PCI I/O standard provides an internal clamp diode between the input pad and the VCCI pad so that the voltage at the input pin is clamped below the absolute maximum input voltage of 4.1 V (Table 2-2 on page 2-2). An example of the input pad voltage level is shown in EQ 2-1: Non-Actel Part Actel FPGA 5V 3.3 V 3.3 V PCI clamp diode . Rext Vinput = VCCI + Vdiode = 3.3 V + 0.7 V = 4.0 V PCI clamp diode EQ 2-1 The internal clamp diode is only enabled while the device is powered on, so the voltage at the input will not be clamped if the VCCI is powered off. An external series resistor (~100 ) is required between the input pin and the 5 V signal source to limit the current to less than 20 mA (Figure 2-1). The 100 resistor was chosen to meet the input Tr/Tf requirement (Table 2-20 on page 2-22). Figure 2-1 * Use of an External Resistor for 5 V Tolerance 5 V tolerance is not allowable for VCCI greater than 3.3 V or for input signals greater than 5.0 V. v5.4 2-1 RTAX-S/SL RadTolerant FPGAs Operating Conditions Absolute Maximum Conditions Stresses beyond those listed in Table 2-2 may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions in Table 2-3. Table 2-2 * Absolute Maximum Ratings Symbol Parameter Limits Units TJ Junction Temperature -55 to +135 C VCCA AC Core Supply Voltage1 -0.3 to 1.8 V VCCA DC Core Supply Voltage -0.3 to 1.7 V VCCI DC I/O Supply Voltage -0.3 to 3.75 V VREF DC I/O Reference Voltage -0.3 to 3.75 V VI Input Voltage -0.5 to 4.1 V VO Output Voltage -0.5 to 3.75 V TSTG Storage Temperature -60 to +150 C VCCDA2 Supply Voltage for Differential I/Os -0.3 to 3.75 V VPUMP Supply Voltage for External Pump -0.3 to 3.75 V Notes: 1. The AC transient VCCA limit is for radiation-induced transients less than 10 s duration and not intended for repetitive use. Core voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the transient does not exceed 1.8 V at any time and the total time that the transient exceeds 1.575 V does not exceed 10 s in duration. 2. VCCDA must be greater than or equal to the highest VCCI voltage Table 2-3 * RTAX-S/SL Recommended Operating Conditions Parameter Range Military Units Junction Temperature (TJ) -55 to +125 C Ambient Temperature (TA)1 -55 to +125 C 1.5 V Core Supply Voltage 1.425 to 1.575 V 1.5 V I/O Supply Voltage 1.425 to 1.575 V 1.8 V I/O Supply Voltage 1.71 to 1.89 V 2.5 V I/O Supply Voltage 2.375 to 2.625 V 3.3 V I/O Supply Voltage 3.0 to 3.6 V 2.375 to 2.625 V 3.3 V VCCDA I/O Supply Voltage (differential or voltage-referenced I/O used) 3.0 to 3.6 V 3.3 V VPUMP Supply Voltage 3.0 to 3.6 V 2.5 V VCCDA I/O Supply Voltage (no differential I/O used) 2 Notes: 1. Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 2. Please see "VCCDA Supply Voltage" on page 2-11 more detail. Overshoot/Undershoot Limits For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer than 10% of the period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the 2 -2 v5.4 period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. Note: The above specification does not apply to the PCI standard. The RTAX-S/SL PCI I/Os are compliant to the PCI standard including the PCI overshoot/undershoot specifications. RTAX-S/SL RadTolerant FPGAs Power-Up/Down Sequence VCCA, VCCI, and VCCDA can be powered up or powered down in any sequence. During power-up, all RTAX-S/SL I/Os are tristated until they reach the state defined by the design. Calculating Power Dissipation Table 2-4 * RTAX-S Standby Current Device RTAX4000S RTAX2000S RTAX1000S RTAX250S ICCDIFFA (mA) IIH, IIL, IOZ (A)1 Temperature ICCA (mA) ICCI (mA) ICCDA (mA) Typical 25C 75 15 15 3.13 1 125C 600 60 20 3.7 5 Typical 25C 50 10 7 3.13 1 125C 500 35 10 3.7 5 Typical 25C 30 10 7 3.13 1 125C 450 35 10 3.7 5 Typical 25C 20 5 5 3.13 1 125C 250 20 10 3.7 5 Notes: 1. 2. 3. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. Above values are maximum. Values in the ICCDIFFA column refer to the current (in addition to ICCDA) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins. Table 2-5 * RTAX-SL Standby Current Device RTAX4000SL RTAX2000SL RTAX1000SL RTAX250SL Temperature ICCA (mA) ICCI (mA) ICCDA (mA) ICCDIFFA (mA) IIH, IIL, IOZ (A)1 Typical 25C 40 15 15 3.13 1 125C 300 60 20 3.7 5 Typical 25C 30 10 7 3.13 1 125C 150 35 10 3.7 5 Typical 25C 20 10 7 3.13 1 125C 90 35 10 3.7 5 Typical 25C 15 5 5 3.13 1 125C 60 20 10 3.7 5 Notes: 1. 2. 3. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. Above values are maximum. Values in the ICCDIFFA column refer to the current (in addition to ICCDA) flowing per pair through differential amplifiers only when using differential pairs or voltage references pins. v5.4 2-3 RTAX-S/SL RadTolerant FPGAs Table 2-6 * Default Cload / VCCI Cload (pF) VCCI (V) Pload (W/MHz) P10 (W/MHz) PI/O (W/MHZ)* 1.5 78.8 49.5 128.3 Single-Ended without VREF LVCMOS - 15 (JESD8-11) 35 LVCMOS -18 35 1.8 113.4 73.4 186.8 LVCMOS - 25 35 2.5 218.8 148.0 366.8 LVTTL 8 mA Low Slew 35 3.3 381.2 118.7 499.9 LVTTL 12 mA Low Slew 35 3.3 381.2 138.6 519.8 LVTTL 16 mA Low Slew 35 3.3 381.2 150.8 532.0 LVTTL 24 mA Low Slew 35 3.3 381.2 169.2 550.4 LVTTL 8 mA High Slew 35 3.3 381.2 130.3 511.5 LVTTL 12 mA High Slew 35 3.3 381.2 165.9 547.1 LVTTL 16 mA High Slew 35 3.3 381.2 225.1 606.3 LVTTL 24 mA High Slew 35 3.3 381.2 267.5 648.7 PCI 10 3.3 108.9 218.5 327.4 PCI-X 10 3.3 108.9 162.9 271.8 SSTL2-I 30 2.5 - 171.2 171.2 SSTL2-II 30 2.5 - 147.8 147.8 SSTL3-I 30 3.3 - 327.2 327.2 SSTL3-II 30 3.3 - 288.4 288.4 HSTL-I 20 1.5 - 40.9 40.9 GTLP - 33 10 3.3 - 68.5 68.5 LVPECL - 33 N/A 3.3 - 260.6 260.6 LVDS - 25 N/A 2.5 - 145.8 145.8 Single-Ended with VREF Differential Note: *PI/O = P10 + Cload * Table 2-7 * VCCI2 Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices Device-Specific Value (in W/MHz) Symbol Power Component RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL P1 Core tile HCLK power component 85.8 227.5 378.0 700 P2 R-cell power component 0.6 0.6 0.6 0.6 P3 HCLK signal power dissipation 7.7 23.2 31.0 50 P4 Core tile RCLK power component 1.8 227.5 378.0 700 P5 R-cell power component 0.9 0.9 0.9 0.9 P6 RCLK signal power dissipation 8.6 25.7 34.3 55 P7 Power dissipation due to the switching activity on the R-cell 1.6 1.6 1.6 1.6 P8 Power dissipation due to the switching activity on the C-cell 1.4 1.4 1.4 1.4 P9 Power component associated with input voltage 10.0 10.0 10.0 10 P10 Power component associated with output voltage P11 Power component associated with the read operation in the RAM block 25.0 25.0 25.0 25.0 P12 Power component associated with the write operation in the RAM block 30.0 30.0 30.0 30.0 2 -4 See Table 2-4 and Table 2-5 on page 2-3 for per pin contribution. v5.4 RTAX-S/SL RadTolerant FPGAs Ptotal = Pdc + Pac Pdc = ICCA * VCCA + ICCI * VCCI + ICCDA * VCCDA + ICCDIFFA * VCCDA * Nb_da_pairs Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory Nb_da_pairs = number of differential pairs or voltage referenced pins used PHCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs s = number of R-cells clocked by this clock Fs = clock frequency PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs s = number of R-cells clocked by this clock Fs = clock frequency PR-cells = P7 * ms * Fs ms = number of R-cells switching at each Fs cycle Fs = clock frequency PC-cells = P8 * mc * Fs mc = number of C-cells switching at each Fs cycle Fs = clock frequency Pinputs = P9 * pi * Fpi pi = number of inputs Fpi = average input frequency Poutputs = (P10 + Cload * VCCI2) * po * Fpo Cload = output load (technology dependent) VCCI = output voltage (technology dependent) po = number of outputs Fpo = average output frequency Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK Nblock = number of RAM/FIFO blocks (1 block = 4k) FRCLK = read-clock frequency of the memory FWCLK = write-clock frequency of the memory v5.4 2-5 RTAX-S/SL RadTolerant FPGAs Power Estimation Example This example employs an RTAX1000S/SL shift-register design with 1,080 R-cells, one C-cell, one reset input, and one output. This design also uses a single clock (HCLK) at 100 MHz and is operated under room temperature. ms = 1,080 (in a shift register 100% of R-cells are toggling at each clock cycle) Fs s = 100 MHz = 1,080 => PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 163.8 mW and Fs = 100 MHz => PR-cells = P7 * ms * Fs = 172.8 mW mc = 1 (1 C-cell in this design) and Fs = 100 MHz => PC-cells = P8 * mc * Fs = 0.14 mW Fpi ~ 0 MHz and pi= 1 (1 reset input => this is why Fpi = 0) => Pinputs = P9 * pi * Fpi = 0 mW Fpo = 50 MHz Cload = 35 pF VCCI= 3.3 V and po = 1 => Poutputs = (P10 + Cload * VCCI2) * po * Fpo = 23.6 mW No RAM/FIFO in this shift-register => Pmemory = 0 mW Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory = 360.4 mW = ICCA * VCCA + ICCI * VCCI + ICCDA * VCCDA + ICCDIFFA * VCCDA * Nb_da_pairs = 101.1 mW Pdc Ptotal = Pdc + Pac = 360.4 mW + 101.1 mW = 461.5 mW 2 -6 v5.4 RTAX-S/SL RadTolerant FPGAs Thermal Characteristics The temperature variable in Actel Designer software refers to the junction temperature, not the ambient, case or board temperature. This is an important distinction because dynamic and static power consumption causes the chip's junction temperature to be higher than the ambient, case or board temperature. EQ 2-2, EQ 2-3, and EQ 2-4 show the relationship between thermal resistance, temperature, and power. Where: Tj - Ta ja = --------------P EQ 2-2 jc Tj - Tc = ---------------P jb Tj - Tb = ---------------P ja = Thermal resistance from junction to air jc = Thermal resistance from junction to case jb = Thermal resistance from junction to board Tj = Junction Temperature Ta = Ambient Temperature Tc = Case Temperature Tb = Board Temperature P = Power EQ 2-3 EQ 2-4 Table 2-8 * Package Thermal Characteristics Product RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL Package Type ja jc jb Units CQ208 19.9 0.8 N/A C/W CQ352 16.8 0.7 N/A C/W CG624 13.7 TBD TBD C/W CQ352 13.3 0.4 N/A C/W CG624 10.8 5.6 4.5 C/W CQ256 15.8 0.25 N/A C/W CQ352 12.3 0.2 N/A C/W CG624 9.7 4.3 3.5 C/W CG1152 9.0 2.0 2.6 C/W CQ352 12.3 0.2 N/A C/W CG1272 8.0 2.0 2.2 C/W Notes: 1. 2. 3. 4. ja are estimated at still air. jc for CQFP refers to the thermal resistance between the junction and the bottom surface of the package. jc for CG packages refers to the thermal resistance between the junction and the top surface of the package. The jb values in the table are simulated under conduction heat transfer only. v5.4 2-7 RTAX-S/SL RadTolerant FPGAs Calculation for Power Sample Case 1: Convection = 0 A sample calculation of the power dissipation allowed for an RTAX1000S/SL-CG624 in still air is shown below. Assume that the maximum junction temperature is maintained at 110C and the ambient temperature is 50C. The maximum power allowed can be estimated using the equation below. Tj = 110C Ta = 50C 110C - 50C ja = 10.8C/W = ----------------------------------P P = 5.55 W Air Solder Columns PCB Figure 2-2 * Heat Flow when Air is Present Sample Case 2: Convection = 0 A sample calculation of the power dissipation when there is no air in the environment is shown below. An RTAX1000S/ SL-CQ352 is attached to the board with a thermal adhesive between the package body. The thermal resistance of the paste is 0.58C/W. Since air is not present in the environment, most of the heat will be flowing through the bottom of the package, through the thermal paste, and to the board. Neglecting the heat flowing through the package leads, the maximum power allowed can be estimated as shown in the equations below. Tj = 110C cb = Thermal resistance of the thermal paste from case to board (i.e., = 0.58C/W) Tb = 70C jb (Total) = jc + cb 110C - 70C jc + cb = ----------------------------------P 110C - 70C 0.4C/W + 0.58C/W = ----------------------------------P 110C - 70C jb (Total) = ----------------------------------P P = 40.8 W Thermal Adhesive PCB Figure 2-3 * Heat Flow in a Vacuum The thermal resistances, shown in Table 2-8 on page 2-7, are based on the simulations done with test conditions and test boards configurations specified in JEDEC specification JESD51. 2 -8 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics RTAX-S/SL devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-9 should be applied to all timing data contained within this datasheet. Table 2-9 * Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Military, TJ = 125C, VCCA = 1.4 V) Junction Temperature VCCA -55C -40C 0C 25C 70C 85C 125C 1.4V 0.74 0.75 0.80 0.84 0.89 0.92 1.00 1.425V 0.72 0.74 0.79 0.82 0.88 0.91 0.98 1.5V 0.69 0.71 0.75 0.78 0.84 0.86 0.94 1.575V 0.66 0.68 0.72 0.75 0.80 0.83 0.90 1.6V 0.65 0.67 0.71 0.74 0.79 0.82 0.89 Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of -55C to 125C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. All timing numbers listed in this datasheet represent sample timing characteristics of RTAX-S/SL devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel's Designer software after place-androute. v5.4 2-9 RTAX-S/SL RadTolerant FPGAs Timing Model I/O Module (Nonregistered) Carry Chain Combinatorial Cell tPY = 2.45 ns Combinatorial Cell I/O LVPECL FCO tPDC = 0.70 ns I/O tCCY = 0.76 ns I/O Module (Registered) + LVPECL tDP = 1.83 ns tRD2 = 0.84 ns Buffer Module Combinatorial Cell Buffer Module tPY = 3.51 ns Y tBFPD = 0.17 ns Routed or Hardwired I/O Module (Nonregistered) tICLKQ = 0.91 ns tSUD = 0.31 ns LVTTL tDP = 1.85 ns LVTTL Output Drive Strength = 4 (24mA) High Slew Rate tPD = 0.95 ns tBFPD = 0.17 ns tRD1 = 0.66 ns tRD2 = 0.84 ns tRD3 = 1.07 ns tHCKH = 3.65 ns FMAX (external) = 350 MHz FMAX (internal) = 700 MHz Register Cell Combinatorial Cell tRD1 = 0.66 ns I/O Module (Non- registered) D Q Y Register Cell tRCO = 0.96 ns tSUD = 0.21 ns D Q I/O Module Buffer Module tOCLKQ = 0.91 ns tSUD = 0.31 ns D Q tPY = 1.26 ns GTL + 3.3V tBPFD = 0.21ns tPD = 0.95 ns + LVDS tRCO = 0.96 ns tSUD = 0.21 ns tRCKH = 3.71 ns tRCKL = 3.54 ns tRCKL = 3.54 ns FMAX (external) = 350 MHz FMAX (internal) = 700 MHz tDP = 2.00 ns Routed Clock LVTTL tDP = 1.85 ns tHCKL = 3.48 ns LVTTL tDP = 1.85 ns Hardwired or Routed Clock tRCKL = 3.55 ns Note: Timing data is for the RTAX2000S/SL, -1 speed. Figure 2-4 * Timing Model Hardwired Clock1 Routed Clock1 External Setup External Setup = (tDP + tRD2 + tSUD) - tHCKH = (tDP + tRD2 + tSUD) - tRCKH = (1.85 + 0.84 + 0.31) - 3.65 = (1.85 + 0.84 + 0.31) - 3.54 = -0.61 = -0.71 ns Clock-to-Out (Pad-to-Pad) Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tPY = tRCKH + tRCO + tRD1 + tPY = 3.65 + 0.96 + 0.66 + 3.51 = 3.71 + 0.96 + 0.66 + 3.51 = 8.78 ns = 8.84 ns 1. Calculations are examples of how to calculate related parameters and do not necessary match the path represented in the "Timing Model". 2 -1 0 v5.4 RTAX-S/SL RadTolerant FPGAs I/O Specifications User-Defined Supply Pins Pin Descriptions VREF Supply Pins GND Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF are not in fixed locations. There can be one or more VREF pins in an I/O bank. Ground Low supply voltage. VCCA Supply Voltage Global Pins Supply voltage for array (1.5 V). VCCIBx HCLKA/B/C/D Supply Voltage Supply voltage for I/Os. Bx is the I/O Bank ID - 0 to 7. See "User I/Os" on page 2-12 for more information. Unused VCCIBX I/O banks may be tied to GND or can be tied to other used VCCIBX I/O banks within the same device. VCCDA Dedicated (Hardwired) Clocks A, B, C, and D These pins are the clock input for sequential modules. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. HCLK pins may be used either as HCLK inputs or as user I/Os. If they are not being used for either purpose, Actel recommends that they are tied to ground. Supply Voltage Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. VCCDA is either 3.3 V or 2.5 V and must use 3.3 V when voltage-referenced and/or differential is used. Additionally, VCCDA must be greater than or equal to any VCCI voltages (i.e. VCCDA VCCIBx). VPUMP Supply Voltage CLKE/F/G/H Global Clocks E, F, G, and H These pins are clock inputs for clock distribution networks. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). The clock input is buffered prior to clocking the R-cells. CLK pins may be used either as CLK inputs or as user I/Os. If they are not being used for either purpose, Actel recommends that they are tied to a known state. Supply Voltage (External Pump) In low-power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches 3.3 V.2 In normal device operation, when using the internal charge pump, VPUMP can be directly tied or through a 1K resistor to GND. 2. When VPUMP = 3.3V, it shuts off the internal charge pump. v5.4 2-11 RTAX-S/SL RadTolerant FPGAs JTAG/Probe Pins Special Functions PRA/B/C/D3 NC Probes A, B, C, and D The dedicated probe pins are used to output data from any user-defined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins' probe capabilities can be permanently disabled to protect programmed design confidentiality. Refer to Table 2-102 on page 2-100 for recommendations on pin status for flight boards. No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. User I/Os4 Introduction Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II). The RTAX-S/SL family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-10 on page 2-13 contains the I/O standards supported by the RTAX-S/SL family. TDI2 Unused I/Os are configured as follows: TCK2 Test Clock Test Data Input Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal pullup resistor with approximately 10 k resistance. * Output buffer is disabled (with tristated value of Hi-Z) * Input buffer is disabled (with tristated value of Hi-Z) TDO2 * No pull-up/pull-down is programmed Test Data Output In Actel Designer Software, unused RTAX-S/SL I/Os are configured as tristate with no pull-up resistors. Serial output for JTAG boundary-scan testing. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal pull-up resistor with approximately 10 k resistance. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a programmable pull-up resistor with approximately 10 k resistance (i.e. with or without the pull-up resistor). This pin must be hardwired to ground for flight. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. All I/O standards are 3.3 V tolerant, and I/O standards, except 3.3 V PCI, are capable of hot insertion and cold sparing. 3.3 V PCI is also 5 V tolerant with the aid of an external resistor (see "5 V Tolerance" on page 2-1). Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). By design, all user flip-flops in the RTAX-S/SL FPGAs are immune to SEUs including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. I/Os are organized into banks, and there are eight banks per device - two per side (Figure 2-7 on page 2-21). Each I/O bank has a common VCCI, the supply voltage for its I/Os. 3. Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, and PRD). The series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe connector) during probing and reading back the checksum. With an internal setup we have seen 70-ohm termination resistor improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the termination resistor for their own setup. Below is a guideline on how to calculate the resistor value. The resistor value should be chosen so that the sum of it and the probe signal's driver impedance equals the effective trace impedance. Z0 = Rs + Zd Z0 = trace impedance (silicon explorer's breakout cable's resistance + PCB trace impedance), Rs = series termination, Zd = probe signal's driver impedance. The termination resistor should be placed as close as possible to the driver. Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the driver impedances needs to be calculated from RTAX-S IBIS Models (Mixed Voltage Operation). PRA, PRB, PRC, PRD, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model. Silicon explorer's breakout cable's resistance is usually close to 1 ohm. 4. Do not use an external resistor to pull the I/O above VCCI for a higher logic "1" voltage level. The desired higher logic "1" voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI. 2 -1 2 v5.4 RTAX-S/SL RadTolerant FPGAs For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a VREF. separating the VREF pin and the user I/O pad location. The differential amplifier supply voltage VCCDA should be connected to 3.3 V. When neither voltage-referenced nor differential I/Os are used, VCCDA may be connected to 2.5 V when VCCI <= 2.5 V in a given I/O bank; however, it is still recommended to connect VCCDA to 3.3 V. The location of the VREF pin should be selected according to the following rules: * The user can gain access to the various I/O standards in three ways: Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. * I/O package locations listed as no-connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF pin. * Dedicated I/O pins (GND, VCCI...) are not counted as part of the 16. * The user I/O pad immediately adjacent on either side of the VREF pin may only be used as an input. The exception is when there is a VCCI/GND pair * Instantiate specific library macros that represent the desired specific standard * Use generic I/O macros and then use Actel Designer's PinEditor to specify the desired I/O standards. (Please note that this is not applicable to differential standards.) * A combination of the first two methods Please refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library Guide for more details. Table 2-10 * I/O Standards Supported by the RTAX-S/SL Family Input/Output Supply Voltage (VCCI) Input Reference Voltage (VREF) LVTTL 3.3 N/A N/A LVCMOS 2.5 V 2.5 N/A N/A LVCMOS 1.8 V 1.8 N/A N/A LVCMOS 1.5 V (JDEC8-11) 1.5 N/A N/A 3.3 V PCI 3.3 N/A N/A GTL+ 3.3 V 3.3 1.0 1.2 I/O Standard Board Termination Voltage (VTT) V* 2.5 1.0 1.2 HSTL Class 1 1.5 0.75 0.75 GTL+ 2.5 SSTL3 Class 1 and II 3.3 1.5 1.5 SSTL2 Class1 and II 2.5 1.25 1.25 LVDS 2.5 N/A N/A LVPECL 3.3 N/A N/A Note: * 2.5 V GTL+ is not supported across the full military temperature range. v5.4 2-13 RTAX-S/SL RadTolerant FPGAs Simultaneous Switching Outputs (SSO) Actel defines SSOs as any outputs that transition in phase within a 1 ns window. The measurements made by Actel are based on the following worst-case conditions: 1. The switching outputs are adjacent to the quiet output on either side. 2. All unused I/O buffers are tristated so they do not help either ground or VCC. Table 2-12 * Compatible I/O Standards for Different VCCI Values VCCI1 Compatible Standards VREF 3.3 V LVTTL, PCI, LVPECL, GTL+ 3.3V 1.0 3.3 V SSTL 3 (Class I and II), LVTTL, PCI, LVPECL 2 2.5 V 1.5 1.0 LVCMOS 2.5V, GTL+ 2.5V, LVDS LVDS2 2.5 V LVCMOS 2.5V, SSTL 2 (Classes I and II), 3. A worst-case package was used. 1.8 V LVCMOS 1.8V N/A When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or more commonly, ground bounce. 1.5 V LVCMOS 1.5V, HSTL Class I 0.75 SSN becomes more of an issue in high pin count packages and when using high performance devices such as the RTAX-S/SL family. Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more information. I/O Banks and Compatibility Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage (VCCI), only I/Os with compatible standards can be assigned to the same bank. Table 2-11 shows the compatible I/O standards for a common VREF (for voltage-referenced standards). Similarly, Table 2-12 shows compatible standards for a common VCCI. Table 2-11 * Compatible I/O Standards for Different VREF Values VREF Compatible Standards 1.5 V SSTL 3 (Class I and II) 1.25 V SSTL 2 (Class I and II) 1.0 V GTL+ (2.5 V and 3.3 V Outputs) 0.75 V HSTL (Class I) 2 -1 4 v5.4 1.25 Notes: 1. VCCI is used for both inputs and outputs. 2. VCCI tolerance is 5%. Table 2-13 on page 2-15 summarizes the different combinations of voltages and I/O standards that can be used together in the same I/O bank. Note that two I/O standards are compatible if: * Their VCCI values are identical * Their VREF standards are identical (if applicable) For example, if LVTTL 3.3 V (VREF= 1.0V) is used, then the other available (i.e. compatible) I/O standards in the same bank are LVTTL 3.3 V PCI, GTL+, and LVPECL. Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all I/O standards used in the bank. For instance, when using LVCMOS2.5 (+/-8% VCCI tolerance) and LVDS (+/-5% VCCI tolerance) within an I/O bank, the maximum voltage tolerance of the bank will be +/-5% VCCI. RTAX-S/SL RadTolerant FPGAs I/O Standard LVTTL 3.3 V LVCMOS 2.5 V LVCMOS1.8 V LVCMOS1.5 V (JESD8-11) 3.3 V PCI GTL + (3.3 V) GTL + (2.5 V) HSTL Class I (1.5 V) SSTL2 Class I & II (2.5 V) SSTL3 Class I & II (3.3 V) LVDS (2.5 V 5%) LVPECL (3.3 V) Table 2-13 * Legal I/O Usage Matrix LVTTL 3. 3V (VREF=1.0V) - - - - - - - - LVTTL 3. 3V(VREF=1.5V) - - - - - - - - LVCMOS 2.5 V (VREF=1.0V) - - - - - - - - - LVCMOS 2.5 V (VREF=1.25V) - - - - - - - - - LVCMOS1.8 V - - - - - - - - - - - LVCMOS1.5 V (VREF=1.75 V) (JESD8-11) - - - - - - - - - - 3.3 V PCI (VREF=1.0V) - - - - - - - - 3.3 V PCI (VREF=1.5V) - - - - - - - - GTL+ (3.3 V) - - - - - - - - GTL+ (2.5 V) - - - - - - - - - - HSTL Class I - - - - - - - - - - SSTL2 Class I & II - - - - - - - - - SSTL3 Class I & II - - - - - - - - LVDS (VREF=1.0 V) - - - - - - - - - LVDS (VREF=1.25 V) - - - - - - - - - LVPECL (VREF=1.0 V) - - - - - - - - LVPECL (VREF=1.5 V) - - - - - - - - Notes: 1. Note that GTL+2.5 V is not supported across the full military temperature range. 2. A "" indicates whether standards can be used within a bank at the same time. Examples: a) LVTTL can be used with 3.3 V PCI and GTL+ (3.3 V), when VREF = 1.0 V (GTL+ requirement). b) LVTTL can be used with 3.3 V PCI and SSTL3 Class I and II, when VREF = 1.5 V (SSTL3 requirement). c) LVDS VCCI = 2.5 V 5%. v5.4 2-15 RTAX-S/SL RadTolerant FPGAs I/O Clusters Each I/O cluster incorporates two I/O modules, four RX modules and two TX modules, and a buffer module. In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg) (Figure 2-5). I/O CLUSTER Routed Input Track OEP Routed Input Track OutREg DIN YOUT Routed Input Track UOP BSR P PAD Routed Input Track EnReg DIN YOUT I/O Slew Rate Drive Strength Output Track Y InReg DCIN UIP Output Track FPGA LOGIC CORE VREF N PAD EnReg DIN YOUT Routed Input Track Routed Input Track OutREg DIN YOUT Routed Input Track OEN UON BSR Routed Input Track I/O Slew Rate Drive Strength Output Track Y InReg DCIN Output Track UIN VREF Figure 2-5 * I/O Cluster Interface Using an I/O Register To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os. Usage of each I/O register (register combining) is individually controlled and can be selected/deselected using the PinEditor tool in Actel's Designer software. I/O register combining can also be controlled at the device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given design.5 In addition, Designer software provides a global option to enable/disable the usage of registers in the I/Os. This option is design specific. The setting for each individual I/O overrides this global option. Furthermore, the Global Set Fuse option in the Designer software, when checked, causes all I/O registers to output logic HIGH at device power-up. Using the Weak Pull-Up and Pull-Down Circuits Each RTAX-S/SL I/O comes with a weak pull-up/down circuit (on the order of 10 k). I/O macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5 V, 1.8 V, and 1.5 V) standards. These macros can be instantiated if a keeper circuit for any input buffer is required. 5. Please note that register combining for multi fanout nets is not supported. 2 -1 6 v5.4 RTAX-S/SL RadTolerant FPGAs Customizing the I/O * * * Table 2-14 * Bank Wide Delay Values A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (Table 2-14). It is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the I/ O). When the input buffer drives a register within the I/O, the delay element is activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer. -1 Bit Setting The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. 4.38 5.14 23 4.60 5.41 24 4.67 5.49 25 4.90 5.76 26 5.01 5.89 27 5.23 6.15 28 5.32 6.26 29 5.55 6.52 30 5.66 6.65 31 5.88 6.92 Using the Differential I/O Standards Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Note that there are no tristated or bidirectional I/O buffers for differential standards. Table 2-14 * Bank Wide Delay Values Bit Setting Delay (ns) 22 Note: Data for RTAX2000S/SL is shown in the table above; it was measured at VCCA = 1.425 and 125C. The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values - 8mA, 12mA, 16mA, or 24mA - that can be specified in Designer.6 -1 Std. Std. Using the Voltage-Referenced I/O Standards Delay (ns) Using these I/O standards is similar to that of singleended I/O standards. Their settings can be changed in Designer. 0 0.88 1.03 1 1.10 1.29 2 1.21 1.42 3 1.44 1.69 4 1.53 1.80 5 1.75 2.06 6 1.86 2.19 7 2.09 2.46 In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very highspeed systems. 8 2.16 2.54 To implement a DDR, users must do the following: 9 2.38 2.80 10 2.49 2.93 1. Instantiate an input buffer (with the required I/O standard). 11 2.72 3.20 12 2.81 3.30 3. Connect the output from the Input buffer to the input of the DDR macro. 13 3.04 3.57 4. DDR supports all I/O standards. 14 3.15 3.70 15 3.37 3.96 5. The DDR macro in SmartGen can be used to implement DDR. 16 3.39 3.98 17 3.61 4.25 18 3.72 4.38 Macros for Specific I/O Standards 19 3.95 4.64 20 4.04 4.75 21 4.27 5.01 There are different macro types for any I/O standard or feature that determine the required VCCI and VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and 24 mA-drive Using DDR (Double Data Rate) 2. Instantiate the DDR_REG macro (Figure 2-6). 6. Bit width and I/O standard can be chosen in SmartGen. 6. These values are minimum drive strengths. v5.4 2-17 RTAX-S/SL RadTolerant FPGAs D PRE QR E QF CLK CLR Figure 2-6 * DDR Register strength. LVTTL can support high slew rate but this should only be used for critical signals. Most of the macro symbols represent variations of the six generic symbol types: * CLKBUF: Clock Buffer * HCLKBUF: Hardwired Clock Buffer * INBUF: Input Buffer * OUTBUF: Output Buffer * TRIBUFF: Tristate Buffer * BIBUF: Bidirectional Buffer Other macros include the following: * Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). * Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUFF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. * DDR_REG macro. It can be connected to any I/O standard input buffers (i.e., INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module. 2 -1 8 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-15, Table 2-16, and Table 2-17 on page 2-20 list all the available macro names differentiated by I/O standard, type, slew rate, and drive strength. Table 2-15 * Macros for Single-Ended I/O Standards Standard VCCI Macro Names LVTTL 3.3 V CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_F_8, OUTBUF_F_12, OUTBUF_F_16, OUTBUF_F_24, TRIBUFF, TRIBUFF_S_8, TRIBUFF_S_12, TRIBUFF_S_16, TRIBUFF_S_24, TRIBUFF_F_8, TRIBUFF_F_12, TRIBUFF_F_16, TRIBUFF_F_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_F_8, BIBUF_F_12, BIBUF_F_16, BIBUF_F_24, 3.3V PCI 3.3 V CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUFF_PCI, BIBUF_PCI LVCMOS25 2.5 V CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUFF_LVCMOS25, BIBUF_LVCMOS25 LVCMOS18 1.8 V CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUFF_LVCMOS18, BIBUF_LVCMOS18 LVCMOS15 (JESD8-11) 1.5 V CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUFF_LVCMOS15, BIBUF_LVCMOS15 v5.4 2-19 RTAX-S/SL RadTolerant FPGAs Table 2-16 * I/O Macros for Differential I/O Standards Standard VCCI Macro Names LVPECL 3.3 V CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL LVDS 2.5 V CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS Table 2-17 * I/O Macros for Voltage-Referenced I/O Standards Standard VCCI VREF GTL+ 3.3 V 1.0 V CLKBUF_GTP33, BIBUF_GTP33 HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUFF_GTP33, GTL+ 2.5 V 1.0 V CLKBUF_GTP25, BIBUF_GTP25 HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUFF_GTP25, SSTL2 Class I 2.5 V 1.25 V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUFF_SSTL2_I, BIBUF_SSTL2_I, INBUF_SSTL2_I, OUTBUF_SSTL2_I SSTL2 Class II 2.5 V 1.25 V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUFF_SSTL2_II, BIBUF_SSTL2_II, INBUF_SSTL2_II, OUTBUF_SSTL2_II SSTL3 Class I 3.3 V 1.5 V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUFF_SSTL3_I, BIBUF_SSTL3_I, INBUF_SSTL3_I, OUTBUF_SSTL3_I SSTL3 Class II 3.3 V 1.5 V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUFF_SSTL3_II, BIBUF_SSTL3_II, INBUF_SSTL3_II, OUTBUF_SSTL3_II HSTL Class I 1.5 V 2 -2 0 0.75 V CLKBUF_HSTL_I, TRIBUFF_HSTL_I Macro Names BIBUF_HSTL_I, v5.4 HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, RTAX-S/SL RadTolerant FPGAs User I/O Naming Conventions Due to the complex and flexible nature of the RTAX-S/SL family's user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7). GND V CCDA V PUMP V CCI 1 GND VCCA GND Corner2 I/O BANK 2 I/O BANK 1 RTAX-S/SL VCCDA GND I/O BANK 3 Corner4 I/O BANK 5 GND V CCDA V CCI 2 GND VCCA GND GND VCCDA I/O BANK 6 GND V CCDA VCCDA GND I/O BANK 0 GND V CCI 6 GND VCCA GND PRB PRA V CCI 0 GND VCCA Corner1 I/O BANK 7 V CCI 7 GND VCCA GND TDO TDI TCK TMS TRST GND V CCDA I/O BANK 4 Corner3 V CCI 3 GND VCCA GND GND V CCDA GND V CCDA V CCI 4 GND V CCA GND PRC PRD GND V CCDA V CCI 5 GND V CCA GND VCCDA GND Figure 2-7 * I/O Bank and Dedicated Pin Layout IOxxXBxFx Pair number in the bank, starting at 00, clockwise from IOB NW P - Positive Pin/ N- Negative Pin Bank I/D 0 through 7, clockwise from IOB NW Fx refers to an unimplemented feature and can be ignored Examples: IO12PB1F1 Is the positive pin of the thirteenth pair of the first I/O bank (IOB NE). IO12PB1 combined with IO12NB1 form a differential pair. For those I/Os that can be employed either as a user I/O or as a special function, the following nomenclature is used: IOxxXBxFx/special_function_name IOxxPB1Fx/CLKx This pin can be configured as a clock input or as a user I/O Figure 2-8 * General Naming Schemes v5.4 2-21 RTAX-S/SL RadTolerant FPGAs I/O Standard Electrical Specifications Table 2-18 * Input Capacitance Symbol Parameter Conditions Min. Max. Units CIN Input Capacitance VIN = 0, f =1.0 MHz 10 pF CINCLK Input Capacitance on Clock Pin VIN = 0, f =1.0 MHz 10 pF Table 2-19 * I/O Weak Pull-Up/Pull-Down Resistances1 Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(Pull up) (k)2 I/O Configuration (VCCI) R(Pull down) (k)3 Min. Max. Min. Max. 3.3 V 35 65 30 60 2.5 V 50 75 40 85 1.8 V 80 140 70 130 1.5 V 100 210 90 180 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHspec Table 2-20 * I/O Input Rise Time and Fall Time* Input Buffer Input Rise/Fall Time (Min) Input Rise/Fall Time (Max) LVTTL No Requirement 50 ns LVCMOS 2.5 V No Requirement 50 ns LVCMOS 1.8 V No Requirement 50 ns LVCMOS 1.5 V No Requirement 50 ns PCI No Requirement 50 ns PCIX No Requirement 50 ns GTL+ No Requirement 50 ns HSTL No Requirement 50 ns SSTL2 No Requirement 50 ns HSTL3 No Requirement 50 ns LVDS No Requirement 50 ns LVPECL No Requirement 50 ns Note: *Input Rise/Fall time applies to all inputs, including clock or data. Inputs have to ramp up/down linearly, in a monotonic way. Glitches or a plateau may cause double-clocking. They must be avoided. For Output Rise/Fall time, refer to IBIS Models for extraction. 2 -2 2 v5.4 RTAX-S/SL RadTolerant FPGAs IN PAD Y INBUF Input High Vtrip Vtrip ln 0V VCCA 50% 50% Y GND t DP t DP (Rising) (Falling) Figure 2-9 * Input Buffer Delays OUT Pad TRIBUF ln To AC test loads (shown below) En VCCA 50% VCCA 50% 50% ln GND 50% 50% VCCI/VTT Vtrip Vtrip Out GND VTT Vtrip VOH 10% tPY tPY (tDLH) (tDHL) VOL tENLZ 50% En GND En VOH Out VOL VCCA tENLZ Out GND/VTT tENHZ Vtrip 90% tENHZ VTT Figure 2-10 * Output Buffer Delays v5.4 2-23 RTAX-S/SL RadTolerant FPGAs I/O Module Timing Characteristics Out Q D OutReg OE D Q EnReg IN D D Q Q InReg CLK CLK (Routed or Hardwired) Figure 2-11 * Timing Model D tSUD tHD CLK tCPWHL tICLKQ tCPWLH Q tHASYN tWASYN CLR tCLR tHASYN tPRESET tWASYN PRESET tSUE tHE E Figure 2-12 * Input Register Timing Characteristics 2 -2 4 tREASYN v5.4 tREASYN RTAX-S/SL RadTolerant FPGAs D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q tHASYN tREASYN tWASYN CLR tCLR tPRESET tHASYN tREASYN tHASYN tREASYN tWASYN PRESET tSUE tHE E Figure 2-13 * Output Register Timing Characteristics D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q tHASYN tREASYN tWASYN CLR tCLR tPRESET tWASYN PRESET tSUE tHE E Figure 2-14 * Output Enable Register Timing Characteristics v5.4 2-25 RTAX-S/SL RadTolerant FPGAs 3.3 V LVTTL Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-21 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.8 2.0 3.6 0.4* 2.4 24 -24 Note: For RTAX250S/SL-CQ352 devices only, VOL limits are 500 mV across all operating temperatures. AC Loadings R=1 k Test Point for tpd Test Point for tristate 35 pF R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-15 * AC Test Loads Table 2-22 * AC Waveforms, Measuring Points, and Capacitive Load Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 3.0 1.40 N/A 35 * Measuring Point = Vtrip 2 -2 6 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-23 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVTTL I/O Module Drive Strength = 1 (8 mA) / Low Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 15.82 18.60 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 16.64 19.56 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 15.56 18.29 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 1.63 1.64 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 1.97 1.97 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 2 (12 mA) / Low Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 13.26 15.58 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 13.56 15.94 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 13.28 15.61 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 1.81 1.82 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 2.24 2.24 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns v5.4 2-27 RTAX-S/SL RadTolerant FPGAs Table 2-23 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 3 (16 mA) / Low Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 12.04 14.16 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 12.46 14.65 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 12.05 14.17 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 1.95 1.96 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 2.52 2.53 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 4 (24 mA) / Low Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 11.41 13.41 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 11.58 13.61 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 11.43 13.43 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 2.01 2.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 2.59 2.60 ns 2 -2 8 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-23 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 1 (8 mA) / High Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 4.78 5.62 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 5.06 5.95 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 4.61 5.42 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 1.98 1.99 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 2.03 2.03 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-29 RTAX-S/SL RadTolerant FPGAs Table 2-23 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVTTL I/O Module Drive Strength = 2 (12 mA) / High Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 3.87 4.55 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 4.08 4.79 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 3.34 3.93 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 1.98 1.99 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 2.31 2.31 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 3 (16 mA) / High Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 3.66 4.31 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.47 2.48 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 3.03 3.57 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 2.00 2.01 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.07 4.79 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns 2 -3 0 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-23 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. 0.37 Std. Speed Min. Max. 0.37 Units tWASYN Asynchronous pulse width ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVTTL I/O Module Drive Strength = 4 (24 mA) / High Slew Rate tDP Input buffer 1.85 2.17 ns tPY Output buffer 3.51 4.12 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.34 2.35 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 1.91 1.92 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 2.96 3.48 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.17 4.90 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-31 RTAX-S/SL RadTolerant FPGAs 2.5 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-24 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.7 1.7 3.6 0.4 2.0 12 -12 AC Loadings R=1 k Test Point for tpd Test Point for tristate 35 pF R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-16 * AC Test Loads Table 2-25 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 2.5 1.25 N/A 35 Note: *Measuring Point = Vtrip 2 -3 2 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-26 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVCMOS25 I/O Module Drive Strength = 1 (6 mA) / Low Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 21.66 25.46 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 22.81 26.81 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 20.47 24.07 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.53 4.53 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.92 4.92 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 2 (12 mA) / Low Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 18.09 21.26 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 19.05 22.39 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 17.40 20.46 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.53 4.53 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.92 4.92 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns v5.4 2-33 RTAX-S/SL RadTolerant FPGAs Table 2-26 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. 0.00 Max. Units 0.00 ns tHE Enable input hold tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 3 (16 mA) / Low Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 16.62 19.53 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 17.50 20.57 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 15.84 18.62 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.53 4.53 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.92 4.92 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 4 (24 mA) / Low Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 15.66 18.41 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 16.49 19.38 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 15.09 17.74 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.53 4.53 ns 2 -3 4 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-26 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.92 4.92 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 1 (6 mA) / High Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 6.32 7.44 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.36 3.37 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 4.26 4.27 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 6.72 7.90 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.72 9.08 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-35 RTAX-S/SL RadTolerant FPGAs Table 2-26 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVCMOS25 I/O Module Drive Strength = 2 (12 mA) / High Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 4.43 5.21 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.61 2.62 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 2.99 3.00 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 6.72 7.90 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.72 9.08 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 3 (16 mA) / High Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 3.91 4.59 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.46 2.47 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 2.64 2.64 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 6.72 7.90 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.72 9.08 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 2 -3 6 0.39 v5.4 0.39 ns RTAX-S/SL RadTolerant FPGAs Table 2-26 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS25 I/O Module Drive Strength = 4 (24 mA) / High Slew Rate tDP Input buffer 2.13 2.51 ns tPY Output buffer 3.59 4.22 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.34 2.35 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 2.43 2.43 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 6.72 7.90 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.72 9.08 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-37 RTAX-S/SL RadTolerant FPGAs 1.8 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-27 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 0.2VCCI 0.7VCCI 2.1 0.2 VCCI-0.2 8mA -8mA AC Loadings R=1 k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-17 * AC Test Loads Table 2-28 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.8 0.5VCCI N/A 35 Note: *Measuring Point = Vtrip 2 -3 8 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-29 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.7 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVCMOS18 I/O Module Drive Strength = 2 (2 mA) / Low Slew Rate tDP Input buffer 3.57 4.19 ns tPY Output buffer 33.79 39.72 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 35.58 41.83 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 26.65 31.33 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.74 4.75 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.02 5.02 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS18 I/O Module Drive Strength = 3 (6 mA) / Low Slew Rate tDP Input buffer 3.57 4.19 ns tPY Output buffer 31.06 36.51 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 32.70 38.44 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 24.32 28.59 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.74 4.75 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.02 5.02 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 v5.4 0.39 ns 2-39 RTAX-S/SL RadTolerant FPGAs Table 2-29 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.7 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS18 I/O Module Drive Strength = 4 (8 mA) / Low Slew Rate tDP Input buffer 3.57 4.19 ns tPY Output buffer 29.73 34.95 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 31.31 36.80 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 23.23 27.31 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 4.74 4.75 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.02 5.02 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS18 I/O Module Drive Strength = 2 (2 mA) / High Slew Rate tDP Input buffer 3.57 4.19 ns tPY Output buffer 6.54 7.69 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.06 3.07 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 4.41 4.41 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 7.04 8.27 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.88 9.26 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns 2 -4 0 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-29 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.7 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS18 I/O Module Drive Strength = 3 (6 mA) / High Slew Rate tDP Input buffer 3.57 4.19 ns tPY Output buffer 5.55 6.52 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 2.85 2.86 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 3.74 3.75 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 7.04 8.27 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 7.88 9.26 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-41 RTAX-S/SL RadTolerant FPGAs Table 2-29 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.7 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVCMOS18 I/O Module Drive Strength = 4 (8 mA) / High Slew Rate tDP Input buffer 4.97 5.85 ns tPY Output buffer 2.65 2.66 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.35 3.36 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 7.04 8.27 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 7.88 9.26 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 0.91 1.07 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.31 0.37 ns tSUD Data input setup 0.35 0.41 ns tSUE Enable input setup 0.00 0.00 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.39 0.39 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.37 0.37 ns tWASYN Asynchronous pulse width 0.17 0.21 ns tREASYN Asynchronous recovery time 0.00 0.00 ns tHASYN Asynchronous removal time 0.31 0.37 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 4.97 5.85 ns 2 -4 2 v5.4 RTAX-S/SL RadTolerant FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-30 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.5 0.35VCCI 0.65VCCI 1.95 0.4 VCCI-0.4 8mA -8mA AC Loadings R=1 k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz Figure 2-18 * AC Test Loads Table 2-31 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.5 0.5VCCI N/A 35 Note: *Measuring Point = Vtrip v5.4 2-43 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-32 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units LVCMOS15 I/O Module Drive Strength = 1 (2 mA) / Low Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 60.38 70.98 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 63.58 74.74 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 44.80 52.67 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.17 5.17 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 2 (4 mA) / Low Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 53.29 62.65 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 56.12 65.97 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 37.88 44.53 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.17 5.17 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns 2 -4 4 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-32 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. 0.00 Max. Units 0.00 ns tHE Enable input hold tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 3 (6 mA) / Low Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 48.90 57.49 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 51.50 60.54 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 34.84 40.95 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.17 5.17 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 8 (4 mA) / Low Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 47.21 55.49 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 49.71 58.43 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 33.18 39.01 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.17 5.17 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns v5.4 2-45 RTAX-S/SL RadTolerant FPGAs Table 2-32 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 1 (2 mA) / High Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 14.59 17.15 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 8.38 9.85 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 14.59 17.15 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 5.17 5.17 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 3.93 4.62 ns LVCMOS15 I/O Module Drive Strength = 2 (4 mA) / High Slew Rate tDP 2 -4 6 Input buffer v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-32 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tPY Output buffer 9.12 10.73 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.69 3.70 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 9.12 10.73 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 8.12 9.54 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 3 (6 mA) / High Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 7.62 8.96 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.42 3.42 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 7.62 8.96 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 5.02 5.02 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 8.12 9.54 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns v5.4 2-47 RTAX-S/SL RadTolerant FPGAs Table 2-32 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns LVCMOS15 I/O Module Drive Strength = 4 (8 mA) / High Slew Rate tDP Input buffer 3.93 4.62 ns tPY Output buffer 6.60 7.76 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 3.12 3.13 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 4.45 4.46 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 7.45 8.76 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 8.12 9.54 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 2 -4 8 v5.4 RTAX-S/SL RadTolerant FPGAs 3.3 V PCI Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5V tolerant with the aid of external components. The RTAX-S/SL 3.3 V PCI buffer is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-33 * DC Input and Output Levels VIH VIL PCI Min,V Max,V Min,V Max,V -0.5 0.3VCCI 0.5VCCI VCCI+0.5 VOL VOH IOL IOH Max,V Min,V mA mA (per PCI specification) AC Loadings Per PCI Specification except for tristate. Actel loading for tristate is in the figure below. R =1 k Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh R to V CCI for tpl R to GND for tph R = 25 Test point for data 10 pF 35 pF for tpzl/tpzh 5 pF for tphz/tplz GND Figure 2-19 * AC Test Loads Table 2-34 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) (Per PCI Spec) VREF (typ) (V) Cload (pF) N/A 10 Note: *Measuring Point = Vtrip v5.4 2-49 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-35 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units 3.3V PCI I/O Module Timing tDP Input buffer 1.72 2.02 ns tPY Output buffer 2.25 2.64 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 1.52 1.52 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 1.42 1.43 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 2.98 3.50 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 4.12 4.84 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 2 -5 0 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-36 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units 3.3V PCI-X I/O Module Timing tDP Input buffer 1.72 2.02 ns tPY Output buffer 2.30 2.71 ns tENZL Enable to Pad delay through the Output Buffer--HIGH to Z 1.52 1.52 ns tENZH Enable to Pad delay through the Output Buffer--Z to HIGH 1.56 1.57 ns tENLZ Enable to Pad delay through the Output Buffer--LOW to Z 3.10 3.65 ns tENHZ Enable to Pad delay through the Output Buffer--Z to LOW 3.64 4.28 ns tIOCLKQ Sequential clock-to-Q for the input register 0.91 1.07 ns tIOCLKY Clock-to-output Y for the IO output register and the enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-51 RTAX-S/SL RadTolerant FPGAs Voltage-Referenced I/O Standards GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer and an open drain output buffer. The VCCI pin should be connected to 2.5 V or 3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range. Table 2-37 * DC Input and Output Levels VIH VIL VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA N/A VREF-0.1 VREF+0.1 N/A 0.6* NA NA NA Note: For high temperature of 125C only, VOL limits are 700 mV, for all other temperatures 600 mV applies. AC Loadings VTT 25 Test Point 10 pF Figure 2-20 * AC Test Loads Table 2-38 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.2 VREF+0.2 VREF 1.0 10 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-39 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 3.3 V GTL+ I/O Module Timing tDP Input buffer 2.01 2.36 ns tPY Output buffer 1.26 1.49 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 2 -5 2 v5.4 0.37 ns RTAX-S/SL RadTolerant FPGAs HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The RTAX-S/SL devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer. Table 2-40 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.1 VREF+0.1 3.6 0.4 VCC-0.4 8 -8 AC Loadings VTT 50 Test Point 20 pF Figure 2-21 * AC Test Loads Table 2-41 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.5 VREF+0.5 VREF 0.75 20 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-42 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 1.4 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 1.5 V HSTL Class I I/O Module Timing tDP Input buffer 2.12 2.49 ns tPY Output buffer 5.35 6.29 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-53 RTAX-S/SL RadTolerant FPGAs SSTL2 Stub Series Terminated Logic for 2.5 V is a general-purpose 2.5 V memory bus standard (JESD8-9). The RTAX-S/SL devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-43 * DC Input and Output Levels VOL VOH IOL IOH Min,V Max,V Min,V VIH Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.57 VREF+0.57 7.6 -7.6 VIL AC Loadings VTT 50 Test Point 25 30 pF Figure 2-22 * AC Test Loads Table 2-44 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.75 VREF+0.75 VREF 1.25 30 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-45 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 2.5 V SSTL2 Class I I/O Module Timing tDP Input buffer 2.14 2.52 ns tPY Output buffer 2.61 3.07 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 2 -5 4 v5.4 RTAX-S/SL RadTolerant FPGAs Class II Table 2-46 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.8 VREF+0.8 15.2 -15.2 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-23 * AC Test Loads Table 2-47 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-0.75 VREF+0.75 VREF 1.25 30 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-48 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 2.5 V SSTL2 Class II I/O Module Timing tDP Input buffer 2.22 2.61 ns tPY Output buffer 2.61 3.07 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-55 RTAX-S/SL RadTolerant FPGAs SSTL3 Stub Series Terminated Logic for 3.3 V is a general-purpose 3.3 V memory bus standard (JESD8-8). The RTAX-S/SL devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-49 * DC Input and Output Levels VOL VOH IOL IOH Min,V Max,V Min,V VIH Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.6 VREF+0.6 8 -8 VIL AC Loadings VTT 50 Test Point 25 30 pF Figure 2-24 * AC Test Loads Table 2-50 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-1.0 VREF+1.0 VREF 1.50 30 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-51 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 3.3 V SSTL3 Class I I/O Module Timing tDP Input buffer 2.09 2.46 ns tPY Output buffer 2.55 2.99 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns 0.00 tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns 2 -5 6 v5.4 RTAX-S/SL RadTolerant FPGAs Class II Table 2-52 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min,V Max,V Min,V Max,V Max,V Min,V mA mA -0.3 VREF-0.2 VREF+0.2 3.6 VREF-0.8 VREF+0.8 16 -16 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-25 * AC Test Loads Table 2-53 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF-1.0 VREF+1.0 VREF 1.50 30 Note: *Measuring Point = Vtrip Timing Characteristics Table 2-54 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units 3.3 V SSTL3 Class II I/O Module Timing tDP Input buffer 2.17 2.55 ns tPY Output buffer 2.55 2.99 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-57 RTAX-S/SL RadTolerant FPGAs Differential Standards Physical Implementation (OutReg), and Enable Register (EnReg). However, there is no support for bidirectional I/Os or tristates with these standards. Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting in a single internal signal. To facilitate construction of the differential pair, a single I/O cluster contains the resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Actel's Designer software when the user instantiates a differential I/O macro in the design. LVDS Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register FPGA OUTBUF_LVDS P 165 ZO = 50 165 FPGA + - 100 140 N P ZO = 50 INBUF_LVDS N Figure 2-26 * LVDS Circuit The LVDS circuit consists of a differential driver connected to a terminated receiver through a constantimpedance transmission line. The receiver is a widecommon-mode-range differential amplifier. The common-mode range is from 0.2 V to 2.2 V for a differential input with 400 mV swing. To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the differential signals (Note that the driver is not a currentmode driver). This driver provides a nominal constant current of 3.5 mA. When this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is controlled by the data fed to the driver. An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV. Therefore, four external resistors are required, three for the driver and one for the receiver. Table 2-55 * DC Input and Output Levels DC Parameter VCCI 1 Description Supply voltage Min. Typ. Max. Units 2.375 2.5 2.625 V VOL Output low voltage 0.9 1.075 1.25 V VOH Output high voltage 1.25 1.425 1.6 V VI Input voltage 2.925 V VODIFF Differential output voltage VOCM Output common mode voltage VICM2 VIDIFF 0 250 350 450 mV 1.125 1.25 1.375 V Input common mode voltage 0.2 1.25 2.2 V Differential input voltage 100 350 Notes: 1. +/- 5% 2. Differential input voltage = 400 mV. 2 -5 8 v5.4 mV RTAX-S/SL RadTolerant FPGAs AC Loadings For AC test loads, see the above LVDS circuit. Table 2-56 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) Cload (pF) 1.2-0.125 1.2+0.125 1.2 N/A Note: *Measuring Point = Vtrip Timing Characteristics Table 2-57 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units LVDS I/O Module Timing tDP Input buffer 2.00 2.35 ns tPY Output buffer 2.54 2.99 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-59 RTAX-S/SL RadTolerant FPGAs LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. FPGA P OUTBUF_LVPECL 100 N + 100 187 INBUF_LVPECL - ZO = 50 100 FPGA P ZO = 50 N Figure 2-27 * LVPECL Circuit The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS, since the output voltage levels are different. Please note that the VOH levels are 200 mV below the standard LVPECL levels. Table 2-58 * DC Input and Output Levels Min. DC Parameter Typ. Max. Min. Max. Min. Max. Min. Max. Units VCCI 3 - 3.3 - 3.6 - V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.3 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential Input Voltage 0.3 - 0.3 - 0.3 - V AC Loadings For AC test loads, See the above LVPECL circuit. Table 2-59 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) Cload (pF) 1.6-0.3 1.6+0.3 1.6 N/A Note: *Measuring Point = Vtrip 2 -6 0 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-60 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units LVPECL I/O Module Timing tDP Input buffer 1.83 2.15 ns tPY Output buffer 2.45 2.88 ns tICLKQ Clock-to-Q for the I/O input register 0.91 1.07 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.91 1.07 ns tSUD Data input setup 0.31 0.37 ns tSUE Enable input setup 0.35 0.41 ns tHD Data input hold 0.00 0.00 ns tHE Enable input hold 0.00 0.00 ns tCPWHL Clock pulse width High to Low 0.39 0.39 ns tCPWLH Clock pulse width Low to High 0.39 0.39 ns tWASYN Asynchronous pulse width 0.37 0.37 ns tREASYN Asynchronous recovery time 0.17 0.21 ns tHASYN Asynchronous removal time 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.31 0.37 ns tPRESET Asynchronous Preset-to-Q 0.31 0.37 ns v5.4 2-61 RTAX-S/SL RadTolerant FPGAs Module Specifications C-Cell * Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell. * A carry input and a carry output. The carry input signal of the C-cell is the carry output from the C-cell directly to the north. * Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. * A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the east side of a SuperCluster with a signal propagation time of less than 0.1 ns. Introduction The C-cell is one of the two logic module types in the RTAX-S/SL architecture. It is the combinatorial logic resource in the RTAX-S/SL device. The RTAX-S/SL architecture implements a new Combinatorial Cell that is an extension of the C-cell implemented in the A54SX-A family. The main enhancement of the new C-cell is the addition of carry-chain logic. The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not required, it can be disabled. The C-cell features the following (Figure 2-28): * Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed clocks (CLKE/F/G/H). This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The carry-chain configuration is handled automatically for the user with the extensive Actel macro library. Refer to the Actel Antifuse Macro Library Guide for a complete listing of available RTAX-S/SL macros. CFN FCI D1 D3 B0 B1 0 1 0 1 0 1 0 1 0 1 D0 D2 DB A0 A1 FCO Figure 2-28 * C-Cell 2 -6 2 v5.4 Y RTAX-S/SL RadTolerant FPGAs Timing Model and Waveforms VCCA 50% 50% A, B, D, FCI GND VCCA 50% Y, FCO GND 50% tPD, tPDC tPD, tPDC VCCA Y, FCO 50% 50% GND tPD, tPDC tPD, tPDC Figure 2-29 * C-Cell Timing Model and Waveforms Timing Characteristics Table 2-61 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. Max. 'Std.' Speed Min. Max. Units C-Cell Propagation Delays tPD Any input to output 0.95 1.11 ns tPDC Any input to carry chain output (FCO) 0.70 0.82 ns tPDB Any input thorough DB when 1 input is used 1.49 1.75 ns tCCY Input carry chain (FCI) to Y 0.76 0.90 ns tCC Input carry chain (FCI) to carry chain output (FCO) 0.10 0.12 ns v5.4 2-63 RTAX-S/SL RadTolerant FPGAs Carry-Chain Logic The RTAX-S/SL dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-5 on page 1-3 and Figure 2-31 on page 2-65). To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e., carry out) for the two bits is generated in a Carry Look-ahead scheme to achieve minimum propagation delay from the FCI (i.e., carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-30. The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through the Actel macro library. D1 D3 B0 B1 FCI CFN D1 D3 B0 B1 CFN The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns. The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one 0 1 0 1 DCOUT 0 1 0 1 0 1 0 1 0 1 0 1 2 -6 4 v5.4 A1 A0 DB D0 D2 Y Figure 2-30 * RTAX-S/SL Two-Bit Carry Logic 0 1 FCO Y 0 1 A1 A0 DB D0 D2 0 1 RTAX-S/SL RadTolerant FPGAs FCI1 C-cell2 DCOUT C-cell1 FCI3 R-cell1 DCIN FCO2 DCOUT DCIN FCO4 FCI5 n-2 Clusters FCI(2n-1) C-cell (2n-1) C-cell2n DCOUT R-celln CDIN FCO2n Note: The carry-chain sequence can end on either C-cell. Figure 2-31 * Carry-Chain Sequencing of C-Cells Timing Characteristics Refer to the C-cell timing characteristics in Table 2-61 on page 2-63 for more information on carry-chain timing. v5.4 2-65 RTAX-S/SL RadTolerant FPGAs R-Cell Introduction * The R-cell, the sequential logic resource of the RTAX-S/SL devices, is the second logic module type in the RTAX-S/SL family architecture. The RTAX-S/SL R-cell is an enhanced version of the A54SX-A R-cell. It includes additional clock inputs for all eight global resources of the RTAX-S/SL architecture as well as global presets and clears (Figure 232). * The main features of the R-cell include the following: * Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a connection with less than 0.1 ns of routing delay. * The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using the R-cell as a 2:1 MUXed flip-flop as well. * Provision of data enable-input (S0). * Independent active low asynchronous clear (CLR). * Independent active low asynchronous preset (PSET). If both CLR and PSET are low, CLR has higher priority. Clock can be driven by any of the following (CKP selects clock polarity): - One of the four high performance hardwired fast clocks (HCLKs) - One of the four routed clocks (CLKs) - User signals Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide basis. - When the Global Set Fuse option in the Designer software is unchecked (by default), GCLR = 0 and GPSET =1 at device power-up. When the option is checked, GCLR = 1 and GPSET= 0. Both pins are pulled HIGH when the device is in user mode. * S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals. * DIN and S1 can be driven by user signals. As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Actel's extensive macro library (please see the Actel Macro Library Guide for a complete listing of available RTAX-S/SL macros). CKP DIN (user signals) DCIN SEU Enhanced D-FF HCLKA/B/C/D CLKE/F/G/H S1 Figure 2-32 * R-Cell 2 -6 6 v5.4 S0 PRE GPRE CKS CLR GCLR Internal Logic Y RTAX-S/SL RadTolerant FPGAs SEU Hardened D Flip-Flop (DFF) In order to meet the stringent SEU requirements of a LETTH greater than 37 MeV-cm2/mg, the internal design of the R-cell was modified without changing the functionality of the cell. Figure 2-33 illustrates a simplified representation of how the D flip-flop in the SuperCluster is implemented in the RTAX-S/SL architecture. The flip-flop consists of a master and a slave latch gated by opposite edges of the clock. Each latch is constructed by feeding back the output to the input stage. The potential problem in a space environment is that either of the latches can change state when hit by a particle with enough energy. the outputs of the other two latches. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch. Figure 2-35 on page 2-68 is a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip-flop. The inputs to each of the three latches are independently controllable, so the voting circuitry in the asynchronous self-correcting feedback paths can be tested exhaustively. This testing is performed on an unprogrammed array during wafer sort, final test, and post-burn-in test. This test circuitry cannot be used to test the flip-flops once the device has been programmed. To achieve the SEU requirements, the D flip-flop in the RTAX-S/SL R-cell is enhanced (Figure 2-34). Both the master and slave "latches" are actually implemented with three latches. The asynchronous self-correcting feedback paths of each of the three latches is voted with Q D CLK CLK Figure 2-33 * RTAX-S/SL R-cell Implementation of D Flip-Flop Q D CLK CLK Voter Gate CLK CLK CLK CLK CLK CLK Figure 2-34 * RTAX-S/SL R-cell Implementation of D Flip-Flop Using Voter Gate Logic v5.4 2-67 RTAX-S/SL RadTolerant FPGAs D Q Tst1 Voter Gate Tst2 Tst3 CLK Test Circuitry Figure 2-35 * RTAX-S/SL R-Cell Implementation - Test Circuitry Timing Models and Waveforms D tSUD tHD CLK tCPWHL tRCO tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tHASYN tPRESET tWASYN PRESET tSUE tHE E Figure 2-36 * R-Cell Delays 2 -6 8 v5.4 tREASYN RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-62 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units R-Cell Propagation Delays tRCO Sequential Clock to Q 0.96 1.12 ns tCLR Asynchronous Clear to Q 0.63 0.74 ns tPRESET Asynchronous Preset to Q 0.76 0.89 ns tSUD FF Data input setup 0.21 0.25 ns tSUE FF Enable input setup 0.21 0.25 ns tHD FF Data Hold 0.00 0.00 ns tHE FF Enable Hold time 0.00 0.00 ns tWASYN Asynchronous Pulse width 0.48 0.48 ns tREASYN Asynchronous Recovery time 0.00 0.00 ns tHASYN Asynchronous Removal time 0.00 0.00 ns tCPWHL Clock pulse width high to low 0.36 0.36 ns tCPWLH Clock pulse width low to high 0.36 0.36 ns Buffer Module Introduction An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to the RTAX-S/SL architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets. Timing Models and Waveforms VCCA 50% IN 50% GND IN OUT VCCA OUT GND Figure 2-37 * Buffer Module Timing Model 50% 50% tBFPD tBFPD Figure 2-38 * Buffer Module Waveform Timing Characteristics Table 2-63 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C '-1' Speed Parameter tBFPD Description Min. Any input to output Y 'Std.' Speed Max. 0.17 v5.4 Min. Max. Units 0.20 ns 2-69 RTAX-S/SL RadTolerant FPGAs Routing Specifications Routing Resources The routing structure found in RTAX-S/SL devices enables any logic module to be connected to any other logic module while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are four primary types of routing within the RTAX-S/ SL architecture: DirectConnect, CarryConnect, FastConnect and Vertical and Horizontal Routing. DirectConnect DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-39). This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. Figure 2-39 * DirectConnect and CarryConnect CarryConnect CarryConnects are used to build carry chains for arithmetic functions (Figure 2-39). The FCO output of the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster immediately below it. This pattern continues down both sides of each SuperCluster column. Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This connection has a delay of less than 0.1 ns from the FCO of one two-C-cell Cluster to the FCI of the two-C-cell Cluster immediately below it (see the "Carry-Chain Logic" on page 2-64 for more information). FastConnect For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 2-40 on page 2-71). FastConnects provide a maximum delay of 0.4 ns. The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on the Output Tracks can 2 -7 0 v5.4 then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below it. Vertical and Horizontal Routing Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-41 on page 2-71). These tracks are composed of both short-distance, segmented routing and across-chip routing tracks (segmented at core tile boundaries). The short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. These short-distance routing tracks can be used within and between SuperClusters or between modules of nonadjacent SuperClusters. They can be connected to the Output Tracks and to any logic module input (R-cell, C-cell, Buffer, and TX module). RTAX-S/SL RadTolerant FPGAs The across-chip horizontal and vertical routing provides long-distance, routing resources. These resources interface with the rest of the routing structures through the RX and TX modules (Figure 2-41 on page 2-71). The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output Tracks within the SuperCluster. The TX module is used to drive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. Figure 2-40 * FastConnect Routing Figure 2-41 * Horizontal and Vertical Tracks v5.4 2-71 RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-64 * RTAX250S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Unit Predicted Routing Delays tDC Direct connect 0.08 0.07 ns tFC Fast connect F01 0.24 0.29 ns tRD1 Fanout 1 0.66 0.77 ns tRD2 Fanout 2 0.84 0.99 ns tRD3 Fanout 3 1.07 1.25 ns tRD4 Fanout 4 1.38 1.62 ns tRD5 Fanout 5 1.45 1.7 ns tRD6 Fanout 6 2.08 2.44 ns tRD7 Fanout 7 2.26 2.66 ns tRD8 Fanout 8 2.44 2.87 ns tRD9 Fanout 9 2.87 3.37 ns tRD10 Fanout 10 3.3 3.88 ns Table 2-65 * RTAX1000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Unit Predicted Routing Delays tDC Direct connect 0.08 0.07 ns tFC Fast connect F01 0.24 0.29 ns tRD1 Fanout 1 0.66 0.77 ns tRD2 Fanout 2 0.84 0.99 ns tRD3 Fanout 3 1.07 1.25 ns tRD4 Fanout 4 1.38 1.62 ns tRD5 Fanout 5 1.45 1.7 ns tRD6 Fanout 6 2.08 2.44 ns tRD7 Fanout 7 2.26 2.66 ns tRD8 Fanout 8 2.44 2.87 ns tRD9 Fanout 9 2.87 3.37 ns tRD10 Fanout 10 3.3 3.88 ns 2 -7 2 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-66 * RTAX2000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Unit Predicted Routing Delays tDC Direct connect 0.08 0.07 ns tFC Fast connect F01 0.24 0.29 ns tRD1 Fanout 1 0.66 0.77 ns tRD2 Fanout 2 0.84 0.99 ns tRD3 Fanout 3 1.07 1.25 ns tRD4 Fanout 4 1.38 1.62 ns tRD5 Fanout 5 1.45 1.70 ns tRD6 Fanout 6 2.08 2.44 ns tRD7 Fanout 7 2.26 2.66 ns tRD8 Fanout 8 2.44 2.87 ns tRD9 Fanout 9 2.87 3.37 ns tRD10 Fanout 10 3.30 3.88 ns Table 2-67 * RTAX4000S (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) 'Std.' Speed Parameter Description Min. Max. Unit Predicted Routing Delays tDC Direct connect 0.07 ns tFC Fast connect F01 0.29 ns tRD1 Fanout 1 0.77 ns tRD2 Fanout 2 0.99 ns tRD3 Fanout 3 1.25 ns tRD4 Fanout 4 1.62 ns tRD5 Fanout 5 1.7 ns tRD6 Fanout 6 2.44 ns tRD7 Fanout 7 2.66 ns tRD8 Fanout 8 2.87 ns tRD9 Fanout 9 3.37 ns tRD10 Fanout 10 3.88 ns v5.4 2-73 RTAX-S/SL RadTolerant FPGAs Global Resources One of the most important aspects of any FPGA architecture is its global resources or clocks. The RTAX-S/ SL family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures. In addition, these global resources have been hardened to improve SEU performance. Hardwired Clocks The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip. The RTAX-S/SL architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed clock). Every RTAX-S/SL device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density. Timing Characteristics Table 2-68 * RTAX250S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHCKL Input Low to High 2.76 3.24 ns tHCKH Input High to Low 2.94 3.46 ns Table 2-69 * RTAX250S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHPWH Minimum Pulse width High 0.77 0.77 ns tHPWL Minimum Pulse width Low 0.26 0.26 ns fHMAX1 Maximum frequency 649 649 MHz Note: *fHMAX = 1000/(2*(MAX(tHPWH,tHPWL))) Table 2-70 * RTAX1000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHCKL Input Low to High 3.65 4.29 ns tHCKH Input High to Low 3.48 4.09 ns Table 2-71 * RTAX1000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHPWH Minimum Pulse width High 0.86 0.86 ns tHPWL Minimum Pulse width Low 0.31 0.31 ns fHMAX1 Maximum frequency 581 Note: *fHMAX = 1000/(2*(MAX(tHPWH,tHPWL))) 2 -7 4 v5.4 581 MHz RTAX-S/SL RadTolerant FPGAs Table 2-72 * RTAX2000S/SL (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHCKL Input Low to High 3.65 4.29 ns tHCKH Input High to Low 3.48 4.09 ns Table 2-73 * RTAX2000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tHPWH Minimum Pulse width High 0.77 0.77 ns tHPWL Minimum Pulse width Low 0.26 0.26 ns fHMAX1 Maximum frequency 649 649 MHz Note: *fHMAX = 1000/(2*(MAX(tHPWH,tHPWL))) Table 2-74 * RTAX4000S (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) 'Std.' Speed Parameter Description Min. Max. Units tHCKL Input Low to High 4.37 ns tHCKH Input High to Low 4.16 ns Max. Units Table 2-75 * RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) 'Std.' Speed Parameter Description Min. tHPWH Minimum Pulse width High TBD ns tHPWL Minimum Pulse width Low TBD ns fHMAX1 Maximum frequency TBD MHz Note: *fHMAX = 1000/(2*(MAX(tHPWH,tHPWL))) v5.4 2-75 RTAX-S/SL RadTolerant FPGAs Routed Clocks The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip. Timing Characteristics Table 2-76 * RTAX250S/SL (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRCKL Input Low to High 2.78 3.26 ns tRCKH Input High to Low 2.92 3.43 ns tRCKSW Maximum skew - 16 Loads 1.40 1.65 ns Maximum skew - 24 Loads 1.81 2.13 ns Table 2-77 * RTAX250S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRPWH Minimum Pulse width High 0.79 0.79 ns tRPWL Minimum Pulse width Low 0.27 0.27 ns fRMAX1 Maximum frequency 633 633 MHz Note: *fRMAX = 1000/(2*(MAX(tRPWH,tRPWL))) Table 2-78 * RTAX1000S/SL (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRCKL Input Low to High 3.71 4.37 ns tRCKH Input High to Low 3.54 4.16 ns tRCKSW Maximum skew - 16 Loads 1.39 1.64 ns Maximum skew - 24 Loads 1.80 2.12 ns Maximum skew - 36 Loads 1.87 2.20 ns Table 2-79 * RTAX1000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRPWH Minimum Pulse width High 1.04 1.04 ns tRPWL Minimum Pulse width Low 0.33 0.33 ns fRMAX1 Maximum frequency 481 Note: *fRMAX = 1000/(2*(MAX(tRPWH,tRPWL))) 2 -7 6 v5.4 481 MHz RTAX-S/SL RadTolerant FPGAs Table 2-80 * RTAX2000S/SL (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRCKL Input Low to High 3.71 4.37 ns tRCKH Input High to Low 3.54 4.16 ns tRCKSW Maximum skew - 16 Loads 1.39 1.64 ns Maximum skew - 24 Loads 1.80 2.12 ns Maximum skew - 36 Loads 2.12 2.49 ns Table 2-81 * RTAX2000S/SL Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) '-1' Speed Parameter Description Min. 'Std.' Speed Max. Min. Max. Units tRPWH Minimum Pulse width High 0.79 ns tRPWL Minimum Pulse width Low 0.27 ns fRMAX1 Maximum frequency 633 MHz Note: *fRMAX = 1000/(2*(MAX(tRPWH,tRPWL))) Table 2-82 * RTAX4000S (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) 'Std.' Speed Parameter Description Min. Max. Units tRCKL Input Low to High 6.41 ns tRCKH Input High to Low 6.19 ns tRCKSW Maximum skew - 16 Loads 1.65 ns Maximum skew - 24 Loads 2.11 ns Maximum skew - 36 Loads 2.16 ns Table 2-83 * RTAX4000S Worst-Case MPW (VCCA = 1.575 V, VCCI = 3.6 V, TJ = 125C) 'Std.' Speed Parameter Description Min. Max. Units tRPWH Minimum Pulse width High TBD ns tRPWL Minimum Pulse width Low TBD ns fRMAX1 Maximum frequency TBD MHz Note: *fRMAX = 1000/(2*(MAX(tRPWH,tRPWL))) v5.4 2-77 RTAX-S/SL RadTolerant FPGAs Global Resource Distribution At the root of each global resource is a ClockDistBuffer (CDB). There are two groups of four CDBs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-42). P N Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 2-43). P N P N P N CDB Cluster HCLKA HCLKB CLKE CLKF HCLKC HCLKD CLKG CLKH CDB Cluster P N P N P N P N Figure 2-42 * ClockDistBuffer Group HCLK CLK CDB Cluster ClockTileDist Cluster 4 4 CDB Cluster Figure 2-43 * Example of HCLK and CLK Distributions on the RTAX2000S/SL 2 -7 8 v5.4 RTAX-S/SL RadTolerant FPGAs The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK branches propagate vertically through the center of the core tile to CLKRowDist (RD) modules in every SuperCluster row. Together, the HCLK and CLK branches provide for a lowskew global fanout within the core tile (Figure 2-44 and Figure 2-45). Figure 2-44 * CTD, CD, and HD Module Layout Figure 2-45 * HCLK and CLK Distribution within a Core Tile v5.4 2-79 RTAX-S/SL RadTolerant FPGAs Global Resource Access Macros The HM and CM modules can select between: * The HCLK or CLK source * A local signal routed on generic routing resources This allows each core tile to have eight clocks independent of the other core tiles in the device. Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. Like the HM and CM modules, the HD and RD modules can select between: * The HCLK or CLK source from the HM or CM module, respectively * A local signal routed on generic routing resources Global resources can be driven by one of three sources: external pad(s) or an internal net. These connections can be made by using one of two types of macros: CLKBUF and CLKINT. CLKBUF and HCLKBUF CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-46). Again, an unused input can be tied to ground for power savings. P The RTAX-S/SL architecture is capable of supporting a large number of local clocks - 24 segments per HCLK driving north-south and 28 segments per CLK driving east-west per core tile. N Actel Designer software's place-and-route takes advantage of the segmented clock structure found in RTAX-S/SL devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption. Future releases of Designer will give the user greater control over these individual clock segments. Clock Network CLKBUF HCLKBUF Figure 2-46 * CLKBUF and HCLKBUF Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the Ppad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals. CLKINT and HCLKINT CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-47). Clock Network Logic CLKINT HCLKINT Figure 2-47 * CLKINT and HCLKINT 2 -8 0 v5.4 RTAX-S/SL RadTolerant FPGAs Embedded Memory The RTAX-S/SL architecture provides extensive, highspeed memory resources to the user. Each 4,608-bit block of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either RAM or FIFO. RA [K:0] RD [(N-1):0] REN To meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write operations. However, the read and write clocks are completely independent, and each may operate beyond 500 MHz. RCLK No additional core logic resources are required to cascade the address and data buses when cascading different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading. WEN WCLK The RTAX-S/SL memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A block diagram of the memory module is illustrated in Figure 2-48. RW [2:0] WD [(M-1):0] WA [J:0] PIPE WW [2:0] Figure 2-48 * RTAX-S/SL Memory Module RAM During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion. Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion (Table 2-84). Each block has independent read and write ports, which enable simultaneous read and write operations. Simultaneous read and write operations to the same address is not supported. Table 2-84 * Memory Block WxD Options Data-Word (in bits) Depth Address Bus Data Bus 1 4,096 RA/WA[11:0] RD/WD[0] 2 2,048 RA/WA[10:0] RD/WD[1:0] 4 1,024 RA/WA[9:0] RD/WD[3:0] 9 512 RA/WA[8:0] RD/WD[8:0] 18 256 RA/WA[7:0] RD/WD[17:0] 36 128 RA/WA[6:0] RD/WD[35:0] v5.4 2-81 RTAX-S/SL RadTolerant FPGAs Clocks The RCLK and the WCLK have independent source polarity selection and can be sourced by any global or local signal. 512x9, 1kx4, 2kx2, and 4kx1. The allowable RW and WW values are shown in Table 2-86. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. RAM Configurations The RTAX-S/SL architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins. The available DxW configurations are: 128x36, 256x18, Note that the RAM blocks employ little-endian byte order for read and write operations. Table 2-85 * RAM Signal Description Signal Direction Description WCLK Input Write clock (can be active on either edge). WA[J:0] Input Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. WD[M-1:0] Input Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. RCLK Input Read clock (can be active on either edge). RA[K:0] Input Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. REN Input Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. WEN Input Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. RW[2:0] Input Width of the read operation dataword. WW[2:0] Input Width of the write operation dataword. Pipe Input Sets the pipeline option to be on or off. Table 2-86 * Allowable RW and WW Values RW(2:0) WW(2:0) DxW 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101 101 128x36 11x 11x reserved 2 -8 2 v5.4 RTAX-S/SL RadTolerant FPGAs Modes of Operation Enhancing SEU Performance There are two read modes and one write mode: SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. To allow users to achieve high levels of SEU performance, Actel has developed an intellectual property (IP) core to enhance the SEU tolerance of the embedded SRAM within RTAX-S/SL. * Read Nonpipelined (synchronous - one clock edge): In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read-port active-clock edge and data appears at read-data after the RAM access time. Setting PIPE to OFF enables this mode. * This IP employs two upset-mitigation techniques: Read Pipelined (synchronous - two clock edges): The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode. * * Error Detection and Correction (EDAC) * A background memory-refresher, or scrubber The EDAC IP employs the use of shortened Hamming Codes to provide the user with single-error correction/ double-error detection (SEC/DED) capabilities. These shortened Hamming Codes provide the user with an implementation that has a reduced number of logic levels and less complexity than traditional Hamming Codes. The SmartGen-generated EDAC IP supports RAM widths of 8, 16, and 32 bits, with a variable RAM depth from 256 to 4k words. Write (synchronous - one clock edge): On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. The memory scrubber circuitry has also been embedded in the EDAC IP as an optional block. The scrubber circuitry periodically refreshes memory in the background to ensure that no corruption of its contents has taken place while the memory was not in use. The refresh rate can be set by the user. Write and read transfers are described with timing requirements beginning in "Timing Characteristics" on page 2-85. The use of EDAC IP combined with the embedded memory scrubber circuitry, gives the RTAX-S/SL an SEU radiation performance level of better than 10-10 errors/ bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. v5.4 2-83 RTAX-S/SL RadTolerant FPGAs Timing Model and Waveforms WD RD WA RA WCLK RCLK WEN REN Table 2-87 * SRAM Model tWCKH tWCKP tWCKL WCLK tWxxSU WA<11:0>, WD<35:0>, WEN<4:0> Figure 2-49 * RAM Write Timing Waveforms tRCKH tRCKP tRCKL RCLK tRxxSU tRxxHD RA<11:0>, REN<4:0> tRCK2RD1 RD <35:0> Figure 2-50 * RAM Read Timing Waveforms 2 -8 4 v5.4 tRCK2RD2 tWxxHD RTAX-S/SL RadTolerant FPGAs Timing Characteristics Table 2-88 * One RAM Block (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) -1 Speed Parameter Description Min. Max. Std. Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.45 1.70 ns tWDAHD Write Data Hold vs. WCLK 0.30 0.35 ns tWADSU Write Address Setup vs. WCLK 1.45 1.70 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 1.45 1.70 ns tWENHD Write Enable Hold vs. WCLK 0.30 0.35 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 ns tWCLKL WCLK Minimum Low Pulse Width 0.88 0.88 ns tWCKP WCLK Minimum Period 1.63 1.63 ns tRADSU Read Address Setup vs. RCLK 1.08 1.27 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 1.08 1.27 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.77 2.08 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.90 3.41 ns tRCLKH RCLK Minimum High Pulse Width 0.77 0.77 ns tRCLKL RCLK Minimum Low Pulse Width 0.93 0.93 ns tRCKP RCLK Minimum Period 1.70 1.70 ns Read Mode Note: Timing data for this single block RAM has a depth of 4,096. For all other combinations, use Actel's SmartTime tool. v5.4 2-85 RTAX-S/SL RadTolerant FPGAs Table 2-89 * Two RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.86 2.19 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 1.86 2.19 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 1.86 2.19 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 ns tWCLKL WCLK Minimum Low Pulse Width 1.76 1.76 ns tWCKP WCLK Minimum Period 2.51 2.51 ns tRADSU Read Address Setup vs. RCLK 2.28 2.68 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 2.28 2.68 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.92 2.26 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 3.03 3.56 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 1.89 1.89 ns tRCKP RCLK Minimum Period 2.62 2.62 ns Read Mode Note: Timing data for two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use Actel's SmartTime tool. 2 -8 6 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-90 * Four RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 3.17 3.73 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 3.17 3.73 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 3.17 3.73 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 ns tWCLKL WCLK Minimum Low Pulse Width 2.51 2.51 ns tWCKP WCLK Minimum Period 3.26 3.26 ns tRADSU Read Address Setup vs. RCLK 4.13 4.85 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 4.13 4.85 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.16 3.72 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 3.79 4.46 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 2.96 2.96 ns tRCKP RCLK Minimum Period 3.69 3.69 ns Read Mode Note: Timing data for four cascaded RAM blocks uses a depth of 16,384. For all other combinations, use Actel's SmartTime tool. v5.4 2-87 RTAX-S/SL RadTolerant FPGAs Table 2-91 * Eight RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 7.74 9.09 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 7.74 9.09 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 7.74 9.09 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 ns tWCLKL WCLK Minimum Low Pulse Width 5.13 5.13 ns tWCKP WCLK Minimum Period 5.88 5.88 ns tRADSU Read Address Setup vs. RCLK 9.04 10.63 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 9.04 10.63 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 4.54 5.33 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 6.60 7.76 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 5.77 5.77 ns tRCKP RCLK Minimum Period 6.50 6.50 ns Read Mode Note: Timing data for eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use Actel's SmartTime tool. 2 -8 8 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-92 * Sixteen RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 22.14 26.03 ns tWDAHD Write Data Hold vs. WCLK 0.30 0.35 ns tWADSU Write Address Setup vs. WCLK 22.14 26.03 ns tWADHD Write Address Hold vs. WCLK 0.30 0.35 ns tWENSU Write Enable Setup vs. WCLK 22.14 26.03 ns tWENHD Write Enable Hold vs. WCLK 0.30 0.35 ns tWCKH WCLK Minimum High Pulse Width 1.31 1.54 ns tWCLKL WCLK Minimum Low Pulse Width 23.34 27.44 ns tWCKP WCLK Minimum Period 46.69 54.88 ns tRADSU Read Address Setup vs. RCLK 24.27 28.53 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 24.27 28.53 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 17.02 20.01 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 18.62 21.89 ns tRCLKH RCLK Minimum High Pulse Width 1.27 1.49 ns tRCLKL RCLK Minimum Low Pulse Width 25.10 29.51 ns tRCKP RCLK Minimum Period 50.21 59.02 ns Read Mode Note: Timing data for sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use Actel's SmartTime tool. v5.4 2-89 RTAX-S/SL RadTolerant FPGAs FIFO Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one write port. This embedded FIFO controller uses no internal FPGA logic and features: * Glitch-free FIFO Flags * Gray-code address counters/pointers to prevent metastability problems * Overflow and underflow control * The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full. * The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty condition. Note: Actel recommends that the WCLK and the RCLK are in phase with each other. For more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller. Gray code counters are used to prevent metastability problems associated with flag logic. The depth of the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are synchronous with respect to the RCLK. Both ports are configurable in various size from 4kx1 to 128x36, similar to the RAM block size. Each port is fully synchronous. Read and write operations can be completely independent. Data on the appropriate WD pins are written to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output on the appropriate RD pins on every active RCLK edge as long as REN is asserted. The FIFO block may be reset to the empty state The FIFO control unit was not implemented with SEUhardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. The FIFO block offers programmable Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags as well as EMPTY and FULL flags (Figure 2-51): RD [n-1:0] WD [n-1:0] RCLK WCLK RCLK WCLK RAM REN WEN PIPE RA [J:0] WA [J:0] RW[2:0] WW[2:0] WD FREN CNT 16 E FULL = AFULL AFVAL SUB 16 > AEMPTY >= AEVAL FWEN CNT 16 E = CLR Figure 2-51 * RTAX-S/SL RAM with Embedded FIFO Controller 2 -9 0 v5.4 EMPTY WIDTH[2:0] DEPTH[3:0] RD RTAX-S/SL RadTolerant FPGAs FIFO Flag Logic The FIFO is user configurable into various depths and widths. Figure 2-52 shows the FIFO address counter details. * Bits 11 to 5 are active for all modes. * As the data word size is reduced, more leastsignificant bits are added to the address. * As the number of cascaded blocks increases, the number of significant bits in the address increases. RAM block, whereas bits 13 and 12 will be used to specify the RAM block. The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. Note that the effective number of threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-93). For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each FIFO Address Counters Mode when Active Counter Bits FIFO Address Alignment of Threshold bits Cas 16 blks CNTR [15] activate R/W EN[3] Cas 8 blks CNTR [14] activate R/W EN[2] AEVAL/AFVAL[6] Cas 4 blks CNTR [13] activate R/W EN[1] AEVAL/AFVAL[5] CNTR [12] activate R/W EN[0] Cas 2 blks by 36 R/W ADD[11:8] CNTR [11:5] always active R/W ADD[7:5] AEVAL/AFVAL[7] AEVAL/AFVAL[4] AEVAL/AFVAL[3:0] not compared [15:W] [14:W] [12:W] [13:W] 128x36 256x18 512x9 CNTR [4] activate R/W ADD[4] by 9 CNTR [3] activate R/W ADD[3] not compared by 4 CNTR [2] activate R/W ADD[2] not compared by 2 CNTR [1] activate R/W ADD[1] not compared by 1 CNTR [0] activate R/W ADD[0] not compared 4kx1 2kx2 [11:5] [11:4] by 18 1kx4 not compared [11:3] [11:2] CNTR [15:0] [11:1] [11:0] Variable Active Address Space >> REN [4:0], RAD [11:0] >> WEN [4:0], WAD [11:0] Note: Inactive counter bits are set to zero. Figure 2-52 * FIFO Address Counters Table 2-93 * FIFO Flag Logic Mode Inactive AEVAL/AFVAL bits Inactive DIFF bits (set to 0) DIFF comparison to AFVAL/AEVAL Non-cascade [7:4] [15:12] DIFF[11:8] withAE/FVAL[3:0] Cascade 2 blocks [7:5] [15:13] DIFF[12:8] withAE/FVAL[4:0] Cascade 4 blocks [7:6] [15:14] DIFF[13:8] withAE/FVAL[5:0] Cascade 8 blocks [7] [15] DIFF[14:8] withAE/FVAL[6:0] Cascade 16 blocks None None DIFF[15:8] withAE/FVAL[7:0] v5.4 2-91 RTAX-S/SL RadTolerant FPGAs Figure 2-53 illustrates flag generation. The Verilog statements for flag assignment are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-94). The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-95. For more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller. AEMPTY AEVAL [7:0], GND [7:0] (MSB....LSB) X WCLK WCNTR [15:0] Y 16 X>=Y (16-bit) DIFF [15:0] RCLK RCNTR [15:0] 16 AFULL X AFVAL [7:0], GND [7:0] (MSB....LSB) Y Figure 2-53 * ALMOST-EMPTY and ALMOST-FULL Logic Table 2-94 * Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 1 1x1 4 2 1x2 4 2 2x1 5 4 1x4 4 4 2x2 5 4 4x1 6 8 1x8 4 8 2x4 5 8 4x2 6 8 8x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 2 -9 2 v5.4 RTAX-S/SL RadTolerant FPGAs Glitch Elimination EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the write address is doublesampled by the read clock prior to comparison with the read address (part A in Figure 2-54). To prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part B in Figure 2-54). An analog filter is added to each FIFO controller to guarantee, glitch-free FIFO-flag logic. Overflow and Underflow Control The counter MSB keeps track of the difference between the read address (RA) and the write address (WA). The A B WA RCLK RA RA = EMPTY = WCLK WA FULL Figure 2-54 * Overflow and Underflow Control FIFO Configurations Clock Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO, the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable word widths, as shown in Table 2-95. As with RAM configuration, the RCLK and WCLK pins have independent polarity selection Table 2-95 * FIFO Width Configurations WIDTH(2:0) WxD The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2, 4, 8, and 16 to be specified. Table 2-84 on page 2-81 describes the FIFO depth options for various data width and memory blocks. 000 1x4k 001 2x2k Interface Figure 2-55 shows a logic block diagram of the RTAX-S/SL FIFO module. Cascading FIFO Blocks FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be taken into account when building the FIFO blocks manually. However, when using SmartGen, the user only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically configures these blocks to optimize performance. 010 4x1k 011 9x512 100 18x256 101 36x128 11x reserved DEPTH [3:0] RD [35:0] WIDTH [2:0] PIPE FREN FULL EMPTY AFULL RCLK AEVAL [7:0] AEMPTY AFVAL [7:0] WD [35:0] FWEN WCLK CLR Figure 2-55 * FIFO Block Diagram v5.4 2-93 RTAX-S/SL RadTolerant FPGAs Table 2-96 * FIFO Signal Description Signal Direction Description WCLK Input Write clock (active either edge). FWEN Input FIFO write enable. When this signal is asserted, the WD bus data is latched into the FIFO, and the internal write counters are incremented. WD[N-1:0] Input Write data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. FULL Output Active high signal indicating that the FIFO is FULL. When this signal is set, additional write requests are ignored. AFULL Output Active high signal indicating that the FIFO is AFULL. AFVAL Input 8-bit input defining the AFULL value of the FIFO. RCLK Input Read clock (active either edge). FREN Input FIFO read enable. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. EMPTY Output Empty flag indicating that the FIFO is EMPTY. When this signal is asserted, attempts to read the FIFO will be ignored. AEMPTY Output Active high signal indicating that the FIFO is AEMPTY. AEVAL Input 8-bit input defining the almost-empty value of the FIFO. PIPE Input Sets the pipe option on or off. CLR Input Active high clear input. DEPTH Input Determines the depth of the FIFO and the number of FIFOs to be cascaded. WIDTH Input Determines the width of the dataword / width of the FIFO, and the number of the FIFOs to be cascaded. 2 -9 4 v5.4 RTAX-S/SL RadTolerant FPGAs Timing Characteristics WD RD AEMPTY EMPTY AFULL FULL FWEN FREN WCLK RCLK Clr Figure 2-56 * FIFO Model tWCKP tWCKH tWCKL WCLK tWSU tWHD WD<35:0>, FWEN tCLR2HF CLR tCLR2xF tWCK2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-57 * FIFO Write Timing v5.4 2-95 RTAX-S/SL RadTolerant FPGAs tRCKH tRCKP RCLK tRSU tRCKL tRHD FREN tRCK2RD1 tRCK2RD2 RD <35:0> tCLRHF CLR tCLR2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-58 * FIFO Read Timing 2 -9 6 v5.4 tCK2xF RTAX-S/SL RadTolerant FPGAs Table 2-97 * One FIFO Block (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 15.26 17.93 ns tWHD Write Hold 0.30 0.35 ns tWCKH WCLK High 0.75 0.75 ns tWCKL WCLK Low 0.88 0.88 ns tWCKP Minimum WCLK Period 1.63 1.63 tRSU Read Setup 15.58 18.31 ns tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 0.77 0.77 ns tRCKL RCLK Low 0.93 0.93 ns tRCKP Minimum RCLK period 1.70 1.70 tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 7.94 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.77 2.08 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 3.50 4.12 ns Note: Timing data for this single cascaded FIFO block uses a depth of 4,096. For all other combinations, please use Actel's Timing software. Table 2-98 * Two FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 18.40 21.64 ns tWHD Write Hold 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 ns tWCKL WCLK Low 1.76 1.76 ns tWCKP Minimum WCLK Period 2.51 2.51 tRSU Read Setup 19.18 22.55 ns tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 ns tRCKL RCLK Low 1.89 1.89 ns tRCKP Minimum RCLK period 2.62 2.62 tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 7.94 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.92 2.26 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 3.03 3.56 ns ns Note: Timing data for two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, please use Actel's Timing software. v5.4 2-97 RTAX-S/SL RadTolerant FPGAs Table 2-99 * Four FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 19.55 22.98 ns tWHD Write Hold 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 ns tWCKL WCLK Low 2.51 2.51 ns tWCKP Minimum WCLK Period 3.26 3.26 tRSU Read Setup 20.44 24.03 tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 ns tRCKL RCLK Low 2.96 2.96 ns tRCKP Minimum RCLK period 3.69 3.69 tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 tRCK2RD1 RCLK-To-OUT (Pipelined) 3.16 3.72 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 3.79 4.46 ns ns 7.94 ns Note: Timing data for four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, please use Actel's Timing software. Table 2-100 * Eight FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 20.69 24.32 ns tWHD Write Hold 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 ns tWCKL WCLK Low 5.13 5.13 ns tWCKP Minimum WCLK Period 5.88 5.88 tRSU Read Setup 21.71 25.52 ns tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 ns tRCKL RCLK Low 5.77 5.77 ns tRCKP Minimum RCLK period 6.50 6.50 tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 7.94 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 4.54 5.33 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 6.60 7.76 ns Note: Timing data for eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, please use Actel's Timing software. 2 -9 8 v5.4 RTAX-S/SL RadTolerant FPGAs Table 2-101 * Sixteen FIFO Blocks are Cascaded (Worst-Case MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 21.85 25.69 ns tWHD Write Hold 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 ns tWCKL WCLK Low 13.40 13.40 ns tWCKP Minimum WCLK Period 14.15 14.15 tRSU Read Setup 22.97 27.00 tRHD Read Hold 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 ns tRCKL RCLK Low 14.41 14.41 ns tRCKP Minimum RCLK period 15.14 15.14 tCLR2FF Clear-to-flag (EMPTY/FULL) 2.57 3.02 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 5.88 6.91 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.85 3.35 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 6.75 tRCK2RD1 RCLK-To-OUT (Pipelined) 16.17 19.01 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 17.18 20.19 ns ns 7.94 ns Note: Timing data for sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, please use Actel's Timing software. Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: * Using the SmartGen core generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (please refer to the Actel SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User's Guide for more information). * The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. v5.4 2-99 RTAX-S/SL RadTolerant FPGAs Other Architectural Features Charge Pump Bypass TRST To reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in no DC current draw. The RTAX-S/SL family devices have a dedicated "VPUMP" pin that can be used to access an external charge pump device. In normal chip operation, when using the internal charge pump, VPUMP should be tied to GND. When the voltage level on VPUMP is set to 3.3 V, the internal charge pump is turned off, and the VPUMP voltage will be used as the charge pump voltage. Adequate voltage regulation (i.e., high drive, low output impedance, and good decoupling) should be used at VPUMP. TRST (Test-Logic Reset) is an active-low asynchronous reset signal to the TAP controller. The TRST input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the TRST state, it is recommended to connect TRST directly to ground for flight. JTAG RTAX-S/SL offers a JTAG interface that is compliant with the IEEE 1149.1 standard except for the device ID length which is 33 bits. The user can employ the JTAG interface for probing a design and executing any JTAG public instructions as defined in the Table 2-102. The JTAG pins and probes are configured as a LVTTL standard port. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note, which also applies to the RTAX-S/SL family of devices. The JTAG pins should not be left floating on flight systems. Table 2-102 * JTAG Instruction Code Instruction (IR4:IR0) Binary Code There is an optional internal pull-up resistor available for the TRST input that can be set by the user at programming. Care should be exercised when using this option in combination with an external tie-off to ground. An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST," but it only occurs at power-up or during recovery from a VCCA and/ or VCCDA voltage drop. TDO TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or "Shift_IR" state. The least significant bit of the selected register (i.e., IR or DR) is clocked out to TDO first by the falling edge of TCK. TAP Controller The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that controls the Instruction Register (IR) and the Data Registers (such as Boundary-Scan Register, IDCODE, USRCODE, BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at the rising edges of TCK. EXTEST 00000 PRELOAD / SAMPLE 00001 INTEST 00010 Instruction Register (IR) USERCODE 00011 IDCODE 00100 HIGHZ 01110 CLAMP 01111 DIAGNOSTIC 10000 The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR." When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111." If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully" flag. Reserved All others BYPASS 11111 Interface The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up resistors. 2 -1 0 0 v5.4 During flight, the following configurations for all JTAG and Probe pins are recommended (Table 2-103 on page 2-101). RTAX-S/SL RadTolerant FPGAs Table 2-103 * JTAG and Probe Pin Recommendations for Flight JTAG and Probe Pins TCK Configurations * Can be hardwired to VCCDA or ground * Can be driven to VCCDA or ground * Must not be left unterminated TDO Must be left unconnected TDI * Can be hardwired or driven to VCCDA * Can be left unconnected (equipped with internal 10 k pull-up resistor) TMS * Can be hardwired or driven to VCCDA * Can be left unconnected (equipped with internal 10 k pull-up resistor) TRST Must be hardwired to ground (equipped with optional internal 10 k pull-up resistor) PRA/B/C/D Must be left unconnected Data Registers (DRs) Probing Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data registers. Descriptions of the main registers are as follow: Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB," "PRC," and "PRD." Special Fuses 1. IDCODE: Security The IDCODE is a 33-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code, which contains the Actel identity, part number, and version number in a specific JTAG format. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note for more information. Actel antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device during power-up, thus making device cloning impossible. In addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an RTAX-S/ SL device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse FPGAs white paper). 2. USERCODE: The USERCODE is a 33-bit programmable JTAG Silicon Signature. It is a supplementary identity code for the user to program information to distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. Refer to the IEEE Standard 1149.1 (JTAG) in the Axcelerator Family application note for more information. 3. Boundary-Scan Register (BSR): Each I/O contains three BSR Cells. Each cell has a shift register bit, a latch, and two MUXes. The boundaryscan cells are used for the Output-enable (E), Output (O), and Input (I) registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan cells are then chained serially to form the BSR. The length of the BSR is the number of I/Os in the die (not the package) multiplied by three. This excludes special function pins (TRST, TCK, TMS, TDI, TDO, PRA, PRB, PRC, PRD, and VPUMP). Look for this symbol to ensure your valuable IP is secure. TM u e Figure 2-59 * FuseLock Logo 4. Bypass Register (BYR): This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to only one bit per device not being tested. It is also selected for all "reserved" or unused instructions. v5.4 2-101 RTAX-S/SL RadTolerant FPGAs To ensure maximum security in RTAX-S/SL devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note. Global Set Fuse The Global Set Fuse determines if all R-cells and I/O Registers (InReg, OutReg, and EnReg) are either cleared or preset by driving the GCLR and GPSET inputs of all R-cells and I/O Registers ("R-Cell" on page 2-66). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and GPSET= 0). A local CLR or PRESET will take precedence overt this setting. Both pins are pulled HIGH during normal device operation. For use details, see Libero IDE online help. Silicon Explorer II Probe Interface Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is operating in a prototype or a production system. The user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. Highlighted nets in Designer's ChipPlanner can be accessed using Silicon Explorer II in order to observe their real time values. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route program cycles the integrity of the design is maintained throughout the debug process. Each member of the RTAX-S/SL family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four probe signals from the RTAX-S/SL device. Each core tile can has up to two probe signals. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on page 2101 for more information). 2 -1 0 2 v5.4 Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-8). Once the design has been placed-and-routed, and the RTAX-S/SL device has been programmed, Silicon Explorer II can be connected and the Explorer software can be launched. Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. Programming Device programming is supported through the Silicon Sculptor 3, a single-site, robust and compact device programmer for the PC. Up to four Silicon Sculptor 3s can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor 3 is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Sculptor 3 programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor 3 to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor 3 also provides a self-test to test its own hardware extensively. Programming an RTAX-S/SL device using Silicon Sculptor 3 is similar to programming any other antifuse device. The procedure is as follows: 1. Load the AFM file. 2. Select the device to be programmed. 3. Begin programming. When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via our In-House Programming Center. For more details on programming the RTAX-S/SL devices, please refer to the Silicon Sculptor User's Guide. RTAX-S/SL RadTolerant FPGAs Package Pin Assignments 208 207 206 205 160 159 158 157 208-Pin CQFP Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 108 107 106 105 101 102 103 104 53 54 55 56 49 50 51 52 Figure 3-1 * 208-Pin CQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. v5.4 3-1 RTAX-S/SL RadTolerant FPGAs 208 CQFP 208 CQFP RTAX250S/SL Function Pin Number Bank 0 RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number IO43PB2F2 134 IO76PB5F5/CLKGP 77 IO02NB0F0 197 IO44NB2F2 131 IO77NB5F5/CLKHN 70 IO03NB0F0 198 IO44PB2F2 133 IO77PB5F5/CLKHP 71 IO03PB0F0 199 IO78NB5F5 66 IO12NB0F0/HCLKAN 191 IO45NB3F3 127 IO78PB5F5 67 IO12PB0F0/HCLKAP 192 IO45PB3F3 129 IO86NB5F5 62 IO13NB0F0/HCLKBN 185 IO46NB3F3 126 IO87NB5F5 60 IO13PB0F0/HCLKBP 186 IO46PB3F3 128 IO87PB5F5 61 IO48NB3F3 122 IO88NB5F5 56 Bank 1 Bank 3 IO14NB1F1/HCLKCN 180 IO48PB3F3 123 IO88PB5F5 57 IO14PB1F1/HCLKCP 181 IO50NB3F3 120 IO89NB5F5 54 IO15NB1F1/HCLKDN 174 IO50PB3F3 121 IO89PB5F5 55 IO15PB1F1/HCLKDP 175 IO55NB3F3 116 IO16NB1F1 170 IO55PB3F3 117 IO91NB6F6 47 IO16PB1F1 171 IO57NB3F3 114 IO91PB6F6 49 IO24NB1F1 165 IO57PB3F3 115 IO92NB6F6 48 IO24PB1F1 166 IO59NB3F3 110 IO92PB6F6 50 IO26NB1F1 161 IO59PB3F3 111 IO93NB6F6 42 IO26PB1F1 162 IO60NB3F3 108 IO93PB6F6 43 IO27NB1F1 159 IO60PB3F3 109 IO94PB6F6 44 IO27PB1F1 160 IO61NB3F3 106 IO96NB6F6 40 IO61PB3F3 107 IO96PB6F6 41 IO101NB6F6 35 Bank 2 3 -2 208 CQFP Bank 6 IO29NB2F2 151 IO29PB2F2 153 IO62NB4F4 100 IO101PB6F6 36 IO30NB2F2 152 IO62PB4F4 103 IO102PB6F6 37 IO30PB2F2 154 IO63NB4F4 101 IO103NB6F6 33 IO31PB2F2 148 IO63PB4F4 102 IO103PB6F6 34 IO32NB2F2 146 IO64NB4F4 96 IO105NB6F6 28 IO32PB2F2 147 IO64PB4F4 97 IO105PB6F6 30 IO34NB2F2 144 IO72NB4F4 91 IO106NB6F6 27 IO34PB2F2 145 IO72PB4F4 92 IO106PB6F6 29 IO39NB2F2 139 IO74NB4F4/CLKEN 87 IO39PB2F2 140 IO74PB4F4/CLKEP 88 IO107NB7F7 23 IO40PB2F2 141 IO75NB4F4/CLKFN 81 IO107PB7F7 25 IO41NB2F2 137 IO75PB4F4/CLKFP 82 IO108NB7F7 22 IO41PB2F2 138 IO108PB7F7 24 IO43NB2F2 132 IO110NB7F7 18 Bank 4 Bank 5 IO76NB5F5/CLKGN v5.4 76 Bank 7 RTAX-S/SL RadTolerant FPGAs 208 CQFP 208 CQFP 208 CQFP RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number IO110PB7F7 19 GND 194 VCCA 156 IO112NB7F7 16 GND 196 VCCA 168 IO112PB7F7 17 GND 201 VCCA 195 IO117NB7F7 12 GND 208 VCCDA 1 IO117PB7F7 13 NC 72 VCCDA 26 IO119NB7F7 10 NC 73 VCCDA 53 IO119PB7F7 11 NC 74 VCCDA 63 IO121PB7F7 7 NC 75 VCCDA 78 IO122NB7F7 5 NC 83 VCCDA 95 IO122PB7F7 6 NC 84 VCCDA 105 IO123NB7F7 3 NC 85 VCCDA 130 IO123PB7F7 4 NC 86 VCCDA 157 NC 176 VCCDA 167 Dedicated I/O GND 9 NC 177 VCCDA 182 GND 15 NC 178 VCCDA 202 GND 21 NC 179 VCCIB0 193 GND 32 NC 187 VCCIB0 200 GND 39 NC 188 VCCIB1 163 GND 46 NC 189 VCCIB1 172 GND 51 NC 190 VCCIB2 135 GND 59 PRA 184 VCCIB2 149 GND 65 PRB 183 VCCIB3 112 GND 69 PRC 80 VCCIB3 124 GND 90 PRD 79 VCCIB4 89 GND 94 TCK 205 VCCIB4 98 GND 99 TDI 204 VCCIB5 58 GND 104 TDO 203 VCCIB5 68 GND 113 TMS 206 VCCIB6 31 GND 119 TRST 207 VCCIB6 45 GND 125 VCCA 2 VCCIB7 8 GND 136 VCCA 14 VCCIB7 20 GND 143 VCCA 38 VPUMP 158 GND 150 VCCA 52 GND 155 VCCA 64 GND 164 VCCA 93 GND 169 VCCA 118 GND 173 VCCA 142 v5.4 3-3 RTAX-S/SL RadTolerant FPGAs 256 255 254 253 196 195 194 193 256-Pin CQFP Pin 1 1 2 3 4 192 191 190 189 Ceramic Tie Bar 256-Pin CQFP 132 131 130 129 65 66 67 68 125 126 127 128 61 62 63 64 Figure 3-2 * 256-Pin CQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -4 v5.4 RTAX-S/SL RadTolerant FPGAs 256-Pin CQFP 256-Pin CQFP RTAX2000S/SL Function Pin Number Bank 0 RTAX2000S/SL Function 256-Pin CQFP Pin Number Bank 2 RTAX2000S/SL Function Pin Number IO167PB3F15 134 IO01NB0F0 248 IO107NB2F10 184 IO01PB0F0 249 IO107PB2F10 185 IO181NB4F17 124 IO04NB0F0 246 IO110NB2F10 180 IO181PB4F17 125 IO04PB0F0 247 IO110PB2F10 181 IO182NB4F17 122 IO05NB0F0 242 IO111NB2F10 178 IO182PB4F17 123 IO05PB0F0 243 IO111PB2F10 179 IO183NB4F17 118 IO08NB0F0 240 IO112NB2F10 174 IO183PB4F17 119 IO08PB0F0 241 IO112PB2F10 175 IO184NB4F17 116 IO113NB2F10 172 IO184PB4F17 117 Bank 0 Bank 4 IO37NB0F3 234 IO113PB2F10 173 IO190NB4F17 112 IO37PB0F3 235 IO114NB2F10 168 IO190PB4F17 113 IO41NB0F3/HCLKAN 232 IO114PB2F10 169 IO192NB4F17 110 IO41PB0F3/HCLKAP 233 IO115NB2F10 166 IO192PB4F17 111 IO42NB0F3/HCLKBN 228 IO115PB2F10 167 Bank 4 IO42PB0F3/HCLKBP 229 IO117NB2F10 162 IO212NB4F19/CLKEN 104 IO117PB2F10 163 IO212PB4F19/CLKEP 105 IO213NB4F19/CLKFN 100 101 Bank 1 IO43NB1F4/HCLKCN 220 IO43PB1F4/HCLKCP 221 IO139NB3F13 158 IO213PB4F19/CLKFP IO44NB1F4/HCLKDN 216 IO139PB3F13 159 Bank 5 IO44PB1F4/HCLKDP 217 IO141NB3F13 154 IO214NB5F20/CLKGN 92 IO141PB3F13 155 IO214PB5F20/CLKGP 93 Bank 1 Bank 3 IO65NB1F6 210 IO142NB3F13 152 IO215NB5F20/CLKHN 88 IO65PB1F6 211 IO142PB3F13 153 IO215PB5F20/CLKHP 89 IO69NB1F6 208 IO145NB3F13 148 Bank 5 IO69PB1F6 209 IO145PB3F13 149 IO236NB5F22 82 IO70NB1F6 199 IO146NB3F13 146 IO236PB5F22 83 IO71NB1F6 204 IO146PB3F13 147 IO238NB5F22 80 IO71PB1F6 205 IO147NB3F13 140 IO238PB5F22 81 IO73NB1F6 202 IO147PB3F13 141 IO240NB5F22 76 IO73PB1F6 203 IO148NB3F13 142 IO240PB5F22 77 IO74NB1F6 197 IO148PB3F13 143 IO242NB5F22 74 IO74PB1F6 198 IO149NB3F13 136 IO242PB5F22 75 IO149PB3F13 137 IO243NB5F22 70 IO243PB5F22 71 Bank 2 IO87NB2F8 187 IO87PB2F8 188 IO165NB3F15 135 IO244NB5F22 68 IO89PB2F8 186 IO167NB3F15 133 IO244PB5F22 69 Bank 3 v5.4 3-5 RTAX-S/SL RadTolerant FPGAs 256-Pin CQFP RTAX2000S/SL Function 256-Pin CQFP Pin Number Bank 6 RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO320PB7F29 9 GND 171 GND 177 IO257PB6F24 60 IO258NB6F24 58 IO341NB7F31 6 GND 183 IO258PB6F24 59 IO341PB7F31 7 GND 190 GND 192 Bank 6 Bank 7 Dedicated I/O IO279NB6F26 56 GND 1 GND 193 IO279PB6F26 57 GND 5 GND 201 IO280NB6F26 52 GND 11 GND 207 IO280PB6F26 53 GND 17 GND 213 IO281NB6F26 50 GND 23 GND 219 IO281PB6F26 51 GND 29 GND 225 IO282NB6F26 46 GND 33 GND 231 IO282PB6F26 47 GND 37 GND 239 IO284NB6F26 44 GND 43 GND 245 IO284PB6F26 45 GND 49 GND 256 IO285NB6F26 40 GND 55 PRA 227 IO285PB6F26 41 GND 62 PRB 226 IO286NB6F26 38 GND 64 PRC 99 IO286PB6F26 39 GND 65 PRD 98 IO287NB6F26 34 GND 73 TCK 253 IO287PB6F26 35 GND 79 TDI 252 GND 85 TDO 250 Bank 7 9 3 -6 256-Pin CQFP IO310NB7F29 30 GND 91 TMS 254 IO310PB7F29 31 GND 97 TRST 255 IO311NB7F29 26 GND 103 VCCA 3 IO311PB7F29 27 GND 109 VCCA 4 IO312NB7F29 24 GND 115 VCCA 22 IO312PB7F29 25 GND 121 VCCA 42 IO315NB7F29 20 GND 128 VCCA 61 IO315PB7F29 21 GND 129 VCCA 63 IO316NB7F29 18 GND 132 VCCA 84 IO316PB7F29 19 GND 139 VCCA 108 IO317NB7F29 14 GND 145 VCCA 127 IO317PB7F29 15 GND 151 VCCA 131 IO318NB7F29 12 GND 157 VCCA 150 IO318PB7F29 13 GND 161 VCCA 170 IO320NB7F29 8 GND 165 VCCA 189 v5.4 RTAX-S/SL RadTolerant FPGAs 256-Pin CQFP 256-Pin CQFP RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number VCCA 191 VCCIB3 156 VCCA 212 VCCIB4 102 VCCA 238 VCCIB4 114 VCCDA 2 VCCIB4 120 VCCDA 32 VCCIB5 72 VCCDA 66 VCCIB5 78 VCCDA 67 VCCIB5 90 VCCDA 86 VCCIB6 36 VCCDA 87 VCCIB6 48 VCCDA 94 VCCIB6 54 VCCDA 95 VCCIB7 10 VCCDA 96 VCCIB7 16 VCCDA 106 VCCIB7 28 VCCDA 107 VPUMP 195 VCCDA 126 VCCDA 130 VCCDA 160 VCCDA 194 VCCDA 196 VCCDA 214 VCCDA 215 VCCDA 222 VCCDA 223 VCCDA 224 VCCDA 236 VCCDA 237 VCCDA 251 VCCIB0 230 VCCIB0 244 VCCIB1 200 VCCIB1 206 VCCIB1 218 VCCIB2 164 VCCIB2 176 VCCIB2 182 VCCIB3 138 VCCIB3 144 v5.4 3-7 RTAX-S/SL RadTolerant FPGAs 268 267 266 265 339 338 337 336 335 334 333 332 331 352 351 350 349 352-Pin CQFP Pin 1 1 2 3 4 264 263 262 261 Ceramic Tie Bar 41 42 43 44 45 46 47 48 49 223 222 221 220 219 218 217 216 215 352-Pin CQFP 173 174 175 176 127 128 129 130 131 132 133 134 135 180 179 178 177 89 90 91 92 85 86 87 88 Figure 3-3 * 352-Pin CQFP Note: The 352-pin CQFP pin assignments for RTAX250S/SL, RTAX1000S/SL and RTAX2000S/SL are compatible except for the following pins. Table 3-1 * Compatibility Table for the CQ352 Package RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX250S/SL NA 117, 148, 294, 327, 328, 91, 117, 130, 131, 148, 174, 268, 294, 307, 308, 327, 328, Not Pin Compatible RTAX1000S/SL 117, 148, 294, 327, 328, NA 91,130, 131, 174, 268, 307, 308 Not Pin Compatible RTAX2000S/SL 91, 117, 130, 131, 148, 174, 268, 294, 307, 308, 327, 328, 91,130, 131, 174, 268, 307, 308 NA Not Pin Compatible 3 -8 v5.4 RTAX-S/SL RadTolerant FPGAs Where exceptions occur, the smaller density devices have those pins designated as No Connects (NC). Customers are therefore recommended to layout their board targeting the larger density device, in order to preserve interchangeability between the two devices. Note: RTAX4000S is not pin compatible with any of the smaller density devices. For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. v5.4 3-9 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP RTAX250S/SL Function Pin Number Bank 0 352-Pin CQFP RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number IO25NB1F1 271 IO46PB3F3 220 IO00NB0F0 341 IO25PB1F1 272 IO47NB3F3 213 IO00PB0F0 342 IO27NB1F1 269 IO47PB3F3 214 IO01NB0F0 343 IO27PB1F1 270 IO48NB3F3 211 IO02NB0F0 337 IO48PB3F3 212 IO02PB0F0 338 IO29NB2F2 261 IO49NB3F3 207 IO04NB0F0 335 IO29PB2F2 262 IO49PB3F3 208 IO04PB0F0 336 IO30NB2F2 259 IO51NB3F3 205 IO06NB0F0 331 IO30PB2F2 260 IO51PB3F3 206 IO06PB0F0 332 IO31NB2F2 255 IO52NB3F3 201 IO08NB0F0 325 IO31PB2F2 256 IO52PB3F3 202 IO08PB0F0 326 IO33NB2F2 249 IO53NB3F3 199 IO10NB0F0 323 IO33PB2F2 250 IO53PB3F3 200 IO10PB0F0 324 IO34NB2F2 253 IO54NB3F3 195 IO12NB0F0/HCLKAN 319 IO34PB2F2 254 IO54PB3F3 196 IO12PB0F0/HCLKAP 320 IO35NB2F2 247 IO55NB3F3 193 IO13NB0F0/HCLKBN 313 IO35PB2F2 248 IO55PB3F3 194 IO13PB0F0/HCLKBP 314 IO36NB2F2 243 IO56NB3F3 187 IO36PB2F2 244 IO56PB3F3 188 Bank 1 Bank 2 IO14NB1F1/HCLKCN 305 IO37NB2F2 241 IO57NB3F3 189 IO14PB1F1/HCLKCP 306 IO37PB2F2 242 IO57PB3F3 190 IO15NB1F1/HCLKDN 299 IO38NB2F2 237 IO59NB3F3 183 IO15PB1F1/HCLKDP 300 IO38PB2F2 238 IO59PB3F3 184 IO16NB1F1 289 IO39NB2F2 235 IO60NB3F3 181 IO16PB1F1 290 IO39PB2F2 236 IO60PB3F3 182 IO17NB1F1 295 IO41NB2F2 231 IO61NB3F3 179 IO17PB1F1 296 IO41PB2F2 232 IO61PB3F3 180 IO18NB1F1 287 IO42NB2F2 229 IO18PB1F1 288 IO42PB2F2 230 IO62NB4F4 172 IO20NB1F1 283 IO43NB2F2 225 IO62PB4F4 173 IO20PB1F1 284 IO43PB2F2 226 IO64NB4F4 166 IO22NB1F1 277 IO44NB2F2 223 IO64PB4F4 167 IO22PB1F1 278 IO44PB2F2 224 IO65NB4F4 170 IO23NB1F1 281 IO65PB4F4 171 IO23PB1F1 282 IO45NB3F3 217 IO66NB4F4 164 IO24NB1F1 275 IO45PB3F3 218 IO66PB4F4 165 IO24PB1F1 276 IO46NB3F3 219 IO67NB4F4 160 3 -1 0 Bank 3 v5.4 Bank 4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number IO67PB4F4 161 IO90PB6F6 86 IO110PB7F7 35 IO68NB4F4 158 IO91NB6F6 84 IO111NB7F7 30 IO68PB4F4 159 IO91PB6F6 85 IO111PB7F7 31 IO70NB4F4 154 IO92NB6F6 78 IO113NB7F7 28 IO70PB4F4 155 IO92PB6F6 79 IO113PB7F7 29 IO72NB4F4 152 IO93NB6F6 82 IO114NB7F7 24 IO72PB4F4 153 IO93PB6F6 83 IO114PB7F7 25 IO73NB4F4 146 IO95NB6F6 76 IO115NB7F7 22 IO73PB4F4 147 IO95PB6F6 77 IO115PB7F7 23 IO74NB4F4/CLKEN 142 IO96NB6F6 72 IO116NB7F7 18 IO74PB4F4/CLKEP 143 IO96PB6F6 73 IO116PB7F7 19 IO75NB4F4/CLKFN 136 IO97NB6F6 70 IO117NB7F7 16 IO75PB4F4/CLKFP 137 IO97PB6F6 71 IO117PB7F7 17 IO98NB6F6 66 IO118NB7F7 12 Bank 5 IO76NB5F5/CLKGN 128 IO98PB6F6 67 IO118PB7F7 13 IO76PB5F5/CLKGP 129 IO99NB6F6 64 IO119NB7F7 10 IO77NB5F5/CLKHN 122 IO99PB6F6 65 IO119PB7F7 11 IO77PB5F5/CLKHP 123 IO100NB6F6 60 IO121NB7F7 6 IO78NB5F5 112 IO100PB6F6 61 IO121PB7F7 7 IO78PB5F5 113 IO101NB6F6 58 IO123NB7F7 4 IO79NB5F5 118 IO101PB6F6 59 IO123PB7F7 5 IO79PB5F5 119 IO103NB6F6 54 IO80NB5F5 110 IO103PB6F6 55 GND 1 IO80PB5F5 111 IO104NB6F6 52 GND 9 IO82NB5F5 106 IO104PB6F6 53 GND 15 IO82PB5F5 107 IO105NB6F6 48 GND 21 IO84NB5F5 100 IO105PB6F6 49 GND 27 IO84PB5F5 101 IO106NB6F6 46 GND 33 IO85NB5F5 104 IO106PB6F6 47 GND 39 IO85PB5F5 105 Bank 7 GND 45 IO86NB5F5 98 IO107NB7F7 40 GND 51 IO86PB5F5 99 IO107PB7F7 41 GND 57 IO87NB5F5 94 IO108NB7F7 42 GND 63 IO87PB5F5 95 IO108PB7F7 43 GND 69 IO89NB5F5 92 IO109NB7F7 36 GND 75 IO89PB5F5 93 IO109PB7F7 37 GND 81 IO110NB7F7 34 GND 88 Bank 6 v5.4 Dedicated I/O 3-11 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number GND 89 GND 334 TDI 348 GND 97 GND 340 TDO 347 GND 103 GND 345 TMS 350 GND 109 GND 352 TRST 351 GND 115 NC 91 VCCA 3 GND 121 NC 117 VCCA 14 GND 133 NC 124 VCCA 32 GND 145 NC 125 VCCA 56 GND 151 NC 126 VCCA 74 GND 157 NC 127 VCCA 87 GND 163 NC 130 VCCA 102 GND 169 NC 131 VCCA 114 GND 176 NC 138 VCCA 150 GND 177 NC 139 VCCA 162 GND 186 NC 140 VCCA 175 GND 192 NC 141 VCCA 191 GND 198 NC 148 VCCA 209 GND 204 NC 174 VCCA 233 GND 210 NC 268 VCCA 251 GND 216 NC 294 VCCA 263 GND 222 NC 301 VCCA 279 GND 228 NC 302 VCCA 291 GND 234 NC 303 VCCA 329 GND 240 NC 304 VCCA 339 GND 246 NC 307 VCCDA 2 GND 252 NC 308 VCCDA 44 GND 258 NC 315 VCCDA 90 GND 264 NC 316 VCCDA 116 GND 265 NC 317 VCCDA 132 GND 274 NC 318 VCCDA 149 GND 280 NC 327 VCCDA 178 GND 286 NC 328 VCCDA 221 GND 292 PRA 312 VCCDA 266 GND 298 PRB 311 VCCDA 293 GND 310 PRC 135 VCCDA 309 GND 322 PRD 134 VCCDA 346 GND 330 TCK 349 VCCIB0 321 3 -1 2 v5.4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number RTAX250S/SL Function Pin Number VCCIB0 333 VCCIB3 197 VCCIB6 50 VCCIB0 344 VCCIB3 203 VCCIB6 62 VCCIB1 273 VCCIB3 215 VCCIB6 68 VCCIB1 285 VCCIB4 144 VCCIB6 80 VCCIB1 297 VCCIB4 156 VCCIB7 8 VCCIB2 227 VCCIB4 168 VCCIB7 20 VCCIB2 239 VCCIB5 96 VCCIB7 26 VCCIB2 245 VCCIB5 108 VCCIB7 38 VCCIB2 257 VCCIB5 120 VPUMP 267 VCCIB3 185 v5.4 3-13 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP RTAX1000S/SL Function Pin Number Bank 0 RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO61NB1F5 271 IO97PB3F9 220 IO02NB0F0 341 IO61PB1F5 272 IO99NB3F9 213 IO02PB0F0 342 IO63NB1F5 269 IO99PB3F9 214 IO03PB0F0 343 IO63PB1F5 270 IO108NB3F10 211 IO04NB0F0 337 IO108PB3F10 212 IO04PB0F0 338 IO64NB2F6 259 IO109NB3F10 207 IO08NB0F0 331 IO64PB2F6 260 IO109PB3F10 208 IO08PB0F0 332 IO67NB2F6 261 IO111NB3F10 205 IO09NB0F0 335 IO67PB2F6 262 IO111PB3F10 206 IO09PB0F0 336 IO68NB2F6 255 IO112NB3F10 199 IO24NB0F2 325 IO68PB2F6 256 IO112PB3F10 200 IO24PB0F2 326 IO69NB2F6 253 IO113NB3F10 201 IO25NB0F2 323 IO69PB2F6 254 IO113PB3F10 202 IO25PB0F2 324 IO74NB2F7 249 IO115NB3F10 195 IO30NB0F2/HCLKAN 319 IO74PB2F7 250 IO115PB3F10 196 IO30PB0F2/HCLKAP 320 IO75NB2F7 247 IO116NB3F10 193 IO31NB0F2/HCLKBN 313 IO75PB2F7 248 IO116PB3F10 194 IO31PB0F2/HCLKBP 314 IO76NB2F7 243 IO117NB3F10 189 IO76PB2F7 244 IO117PB3F10 190 Bank 1 3 -1 4 352-Pin CQFP Bank 2 IO32NB1F3/HCLKCN 305 IO77NB2F7 241 IO124NB3F11 183 IO32PB1F3/HCLKCP 306 IO77PB2F7 242 IO124PB3F11 184 IO33NB1F3/HCLKDN 299 IO78NB2F7 237 IO125NB3F11 187 IO33PB1F3/HCLKDP 300 IO78PB2F7 238 IO125PB3F11 188 IO38NB1F3 295 IO79NB2F7 235 IO127NB3F11 181 IO38PB1F3 296 IO79PB2F7 236 IO127PB3F11 182 IO54NB1F5 287 IO82NB2F7 231 IO128NB3F11 179 IO54PB1F5 288 IO82PB2F7 232 IO128PB3F11 180 IO55NB1F5 289 IO83NB2F7 229 IO55PB1F5 290 IO83PB2F7 230 IO130NB4F12 172 IO56NB1F5 281 IO94NB2F8 225 IO130PB4F12 173 IO56PB1F5 282 IO94PB2F8 226 IO131NB4F12 170 IO57NB1F5 283 IO95NB2F8 223 IO131PB4F12 171 IO57PB1F5 284 IO95PB2F8 224 IO132NB4F12 166 IO59NB1F5 277 IO132PB4F12 167 IO59PB1F5 278 IO96NB3F9 217 IO133NB4F12 164 IO60NB1F5 275 IO96PB3F9 218 IO133PB4F12 165 IO60PB1F5 276 IO97NB3F9 219 IO134NB4F12 160 Bank 3 v5.4 Bank 4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO134PB4F12 161 IO193PB6F18 86 IO238PB7F22 37 IO136NB4F12 158 IO194NB6F18 84 IO240NB7F22 30 IO136PB4F12 159 IO194PB6F18 85 IO240PB7F22 31 IO137NB4F12 154 IO196NB6F18 78 IO241NB7F22 28 IO137PB4F12 155 IO196PB6F18 79 IO241PB7F22 29 IO138NB4F12 152 IO197NB6F18 82 IO242NB7F22 24 IO138PB4F12 153 IO197PB6F18 83 IO242PB7F22 25 IO153NB4F14 146 IO198NB6F18 76 IO244NB7F22 22 IO153PB4F14 147 IO198PB6F18 77 IO244PB7F22 23 IO159NB4F14/CLKEN 142 IO203NB6F19 72 IO245NB7F22 18 IO159PB4F14/CLKEP 143 IO203PB6F19 73 IO245PB7F22 19 IO160NB4F14/CLKFN 136 IO204NB6F19 70 IO246NB7F22 16 IO160PB4F14/CLKFP 137 IO204PB6F19 71 IO246PB7F22 17 IO205NB6F19 66 IO249NB7F23 12 Bank 5 IO161NB5F15/CLKGN 128 IO205PB6F19 67 IO249PB7F23 13 IO161PB5F15/CLKGP 129 IO206NB6F19 64 IO250NB7F23 10 IO162NB5F15/CLKHN 122 IO206PB6F19 65 IO250PB7F23 11 IO162PB5F15/CLKHP 123 IO207NB6F19 60 IO256NB7F23 4 IO167NB5F15 118 IO207PB6F19 61 IO256PB7F23 5 IO167PB5F15 119 IO208NB6F19 58 IO257NB7F23 6 IO183NB5F17 110 IO208PB6F19 59 IO257PB7F23 7 IO183PB5F17 111 IO211NB6F19 54 Dedicated I/O IO184NB5F17 112 IO211PB6F19 55 GND 1 IO184PB5F17 113 IO212NB6F19 52 GND 9 IO185NB5F17 104 IO212PB6F19 53 GND 15 IO185PB5F17 105 IO223NB6F20 48 GND 21 IO186NB5F17 106 IO223PB6F20 49 GND 27 IO186PB5F17 107 IO224NB6F20 46 GND 33 IO187NB5F17 98 IO224PB6F20 47 GND 39 IO187PB5F17 99 GND 45 IO188NB5F17 100 IO225NB7F21 40 GND 51 IO188PB5F17 101 IO225PB7F21 41 GND 57 IO190NB5F17 94 IO226NB7F21 42 GND 63 IO190PB5F17 95 IO226PB7F21 43 GND 69 IO192NB5F17 92 IO237NB7F22 34 GND 75 IO192PB5F17 93 IO237PB7F22 35 GND 81 IO238NB7F22 36 GND 88 Bank 6 Bank 7 v5.4 3-15 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number GND 89 GND 334 VCCA 14 GND 97 GND 340 VCCA 32 GND 103 GND 345 VCCA 56 GND 109 GND 352 VCCA 74 GND 115 NC 91 VCCA 87 GND 121 NC 124 VCCA 102 GND 133 NC 125 VCCA 114 GND 145 NC 126 VCCA 150 GND 151 NC 127 VCCA 162 GND 157 NC 130 VCCA 175 GND 163 NC 131 VCCA 191 GND 169 NC 138 VCCA 209 GND 176 NC 139 VCCA 233 GND 177 NC 140 VCCA 251 GND 186 NC 141 VCCA 263 GND 192 NC 174 VCCA 279 GND 198 NC 268 VCCA 291 GND 204 NC 301 VCCA 329 GND 210 NC 302 VCCA 339 GND 216 NC 303 VCCDA 2 GND 222 NC 304 VCCDA 44 GND 228 NC 307 VCCDA 90 GND 234 NC 308 VCCDA 116 GND 240 NC 315 VCCDA 117 GND 246 NC 316 VCCDA 132 GND 252 NC 317 VCCDA 148 GND 258 NC 318 VCCDA 149 GND 264 PRA 312 VCCDA 178 GND 265 PRB 311 VCCDA 221 GND 274 PRC 135 VCCDA 266 GND 280 PRD 134 VCCDA 293 GND 286 TCK 349 VCCDA 294 GND 292 TDI 348 VCCDA 309 GND 298 TDO 347 VCCDA 327 GND 310 TMS 350 VCCDA 328 GND 322 TRST 351 VCCDA 346 GND 330 VCCA 3 VCCIB0 321 3 -1 6 v5.4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number VCCIB0 333 VCCIB3 197 VCCIB6 50 VCCIB0 344 VCCIB3 203 VCCIB6 62 VCCIB1 273 VCCIB3 215 VCCIB6 68 VCCIB1 285 VCCIB4 144 VCCIB6 80 VCCIB1 297 VCCIB4 156 VCCIB7 8 VCCIB2 227 VCCIB4 168 VCCIB7 20 VCCIB2 239 VCCIB5 96 VCCIB7 26 VCCIB2 245 VCCIB5 108 VCCIB7 38 VCCIB2 257 VCCIB5 120 VPUMP 267 VCCIB3 185 v5.4 3-17 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP RTAX2000S/SL Function Pin Number Bank 0 RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO73NB1F6 269 IO132PB3F12 218 IO01NB0F0 341 IO73PB1F6 270 IO137NB3F12 213 IO01PB0F0 342 IO74NB1F6 271 IO137PB3F12 214 IO02PB0F0 343 IO74PB1F6 272 IO139NB3F13 211 IO04NB0F0 337 IO139PB3F13 212 IO04PB0F0 338 IO87NB2F8 261 IO141NB3F13 205 IO05NB0F0 335 IO87PB2F8 262 IO141PB3F13 206 IO05PB0F0 336 IO88NB2F8 255 IO142NB3F13 207 IO08NB0F0 331 IO88PB2F8 256 IO142PB3F13 208 IO08PB0F0 332 IO89NB2F8 259 IO145NB3F13 199 IO37NB0F3 325 IO89PB2F8 260 IO145PB3F13 200 IO37PB0F3 326 IO91NB2F8 253 IO146NB3F13 201 IO38NB0F3 323 IO91PB2F8 254 IO146PB3F13 202 IO38PB0F3 324 IO99NB2F9 249 IO147NB3F13 193 IO41NB0F3/HCLKAN 319 IO99PB2F9 250 IO147PB3F13 194 IO41PB0F3/HCLKAP 320 IO100NB2F9 247 IO148NB3F13 195 IO42NB0F3/HCLKBN 313 IO100PB2F9 248 IO148PB3F13 196 IO42PB0F3/HCLKBP 314 IO107NB2F10 243 IO149NB3F13 189 IO107PB2F10 244 IO149PB3F13 190 Bank 1 3 -1 8 352-Pin CQFP Bank 2 IO43NB1F4/HCLKCN 305 IO110NB2F10 241 IO161NB3F15 183 IO43PB1F4/HCLKCP 306 IO110PB2F10 242 IO161PB3F15 184 IO44NB1F4/HCLKDN 299 IO111NB2F10 237 IO163NB3F15 187 IO44PB1F4/HCLKDP 300 IO111PB2F10 238 IO163PB3F15 188 IO48NB1F4 295 IO112NB2F10 235 IO165NB3F15 181 IO48PB1F4 296 IO112PB2F10 236 IO165PB3F15 182 IO65NB1F6 283 IO113NB2F10 231 IO167NB3F15 179 IO65PB1F6 284 IO113PB2F10 232 IO167PB3F15 180 IO66NB1F6 289 IO114NB2F10 229 IO66PB1F6 290 IO114PB2F10 230 IO181NB4F17 172 IO68NB1F6 287 IO115NB2F10 225 IO181PB4F17 173 IO68PB1F6 288 IO115PB2F10 226 IO182NB4F17 170 IO69NB1F6 275 IO117NB2F10 223 IO182PB4F17 171 IO69PB1F6 276 IO117PB2F10 224 IO183NB4F17 166 IO70NB1F6 281 IO183PB4F17 167 IO70PB1F6 282 IO129NB3F12 219 IO184NB4F17 164 IO71NB1F6 277 IO129PB3F12 220 IO184PB4F17 165 IO71PB1F6 278 IO132NB3F12 217 IO185NB4F17 160 Bank 3 v5.4 Bank 4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO185PB4F17 161 IO257PB6F24 86 IO311PB7F29 37 IO190NB4F17 158 IO258NB6F24 84 IO312NB7F29 28 IO190PB4F17 159 IO258PB6F24 85 IO312PB7F29 29 IO191NB4F17 154 IO261NB6F24 82 IO315NB7F29 30 IO191PB4F17 155 IO261PB6F24 83 IO315PB7F29 31 IO192NB4F17 152 IO262NB6F24 78 IO316NB7F29 22 IO192PB4F17 153 IO262PB6F24 79 IO316PB7F29 23 IO207NB4F19 146 IO265NB6F24 76 IO317NB7F29 24 IO207PB4F19 147 IO265PB6F24 77 IO317PB7F29 25 IO212NB4F19/CLKEN 142 IO279NB6F26 72 IO318NB7F29 18 IO212PB4F19/CLKEP 143 IO279PB6F26 73 IO318PB7F29 19 IO213NB4F19/CLKFN 136 IO280NB6F26 70 IO320NB7F29 16 IO213PB4F19/CLKFP 137 IO280PB6F26 71 IO320PB7F29 17 IO281NB6F26 66 IO334NB7F31 10 Bank 5 IO214NB5F20/CLKGN 128 IO281PB6F26 67 IO334PB7F31 11 IO214PB5F20/CLKGP 129 IO282NB6F26 64 IO335NB7F31 12 IO215NB5F20/CLKHN 122 IO282PB6F26 65 IO335PB7F31 13 IO215PB5F20/CLKHP 123 IO284NB6F26 60 IO338NB7F31 6 IO217NB5F20 118 IO284PB6F26 61 IO338PB7F31 7 IO217PB5F20 119 IO285NB6F26 58 IO341NB7F31 4 IO236NB5F22 110 IO285PB6F26 59 IO341PB7F31 5 IO236PB5F22 111 IO286NB6F26 54 Dedicated I/O IO237NB5F22 112 IO286PB6F26 55 GND 1 IO237PB5F22 113 IO287NB6F26 52 GND 9 IO238NB5F22 104 IO287PB6F26 53 GND 15 IO238PB5F22 105 IO294NB6F27 48 GND 21 IO239NB5F22 106 IO294PB6F27 49 GND 27 IO239PB5F22 107 IO296NB6F27 46 GND 33 IO240NB5F22 100 IO296PB6F27 47 GND 39 IO240PB5F22 101 GND 45 IO242NB5F22 94 IO300NB7F28 42 GND 51 IO242PB5F22 95 IO300PB7F28 43 GND 57 IO243NB5F22 98 IO303NB7F28 40 GND 63 IO243PB5F22 99 IO303PB7F28 41 GND 69 IO244NB5F22 92 IO310NB7F29 34 GND 75 IO244PB5F22 93 IO310PB7F29 35 GND 81 IO311NB7F29 36 GND 88 Bank 6 Bank 7 v5.4 3-19 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number GND 89 GND 334 VCCA 150 GND 97 GND 340 VCCA 162 GND 103 GND 345 VCCA 175 GND 109 GND 352 VCCA 191 GND 115 NC 124 VCCA 209 GND 121 NC 125 VCCA 233 GND 133 NC 126 VCCA 251 GND 145 NC 127 VCCA 263 GND 151 NC 138 VCCA 279 GND 157 NC 139 VCCA 291 GND 163 NC 140 VCCA 329 GND 169 NC 141 VCCA 339 GND 176 NC 301 VCCDA 2 GND 177 NC 302 VCCDA 44 GND 186 NC 303 VCCDA 90 GND 192 NC 304 VCCDA 91 GND 198 NC 315 VCCDA 116 GND 204 NC 316 VCCDA 117 GND 210 NC 317 VCCDA 130 GND 216 NC 318 VCCDA 131 GND 222 PRA 312 VCCDA 132 GND 228 PRB 311 VCCDA 148 GND 234 PRC 135 VCCDA 149 GND 240 PRD 134 VCCDA 174 GND 246 TCK 349 VCCDA 178 GND 252 TDI 348 VCCDA 221 GND 258 TDO 347 VCCDA 266 GND 264 TMS 350 VCCDA 268 GND 265 TRST 351 VCCDA 293 GND 274 VCCA 3 VCCDA 294 GND 280 VCCA 14 VCCDA 307 GND 286 VCCA 32 VCCDA 308 GND 292 VCCA 56 VCCDA 309 GND 298 VCCA 74 VCCDA 327 GND 310 VCCA 87 VCCDA 328 GND 322 VCCA 102 VCCDA 346 GND 330 VCCA 114 VCCIB0 321 3 -2 0 v5.4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number VCCIB0 333 VCCIB3 197 VCCIB6 50 VCCIB0 344 VCCIB3 203 VCCIB6 62 VCCIB1 273 VCCIB3 215 VCCIB6 68 VCCIB1 285 VCCIB4 144 VCCIB6 80 VCCIB1 297 VCCIB4 156 VCCIB7 8 VCCIB2 227 VCCIB4 168 VCCIB7 20 VCCIB2 239 VCCIB5 96 VCCIB7 26 VCCIB2 245 VCCIB5 108 VCCIB7 38 VCCIB2 257 VCCIB5 120 VPUMP 267 VCCIB3 185 v5.4 3-21 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP RTAX4000S/SL Function Pin Number Bank 0 352-Pin CQFP RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO104PB2F12 260 IO182PB3F20 200 IO02NB0F0 341 IO106NB2F12 253 IO183NB3F20 195 IO02PB0F0 342 IO106PB2F12 254 IO183PB3F20 196 IO03PB0F0 343 IO107NB2F12 257 IO203NB3F23 189 IO05NB0F0 337 IO107PB2F12 258 IO203PB3F23 190 IO05PB0F0 338 IO111NB2F12 251 IO204NB3F23 183 IO06NB0F0 335 IO111PB2F12 252 IO204PB3F23 184 IO06PB0F0 336 IO139NB2F16 241 IO206NB3F23 187 IO07NB0F0 331 IO139PB2F16 242 IO206PB3F23 188 IO07PB0F0 332 IO140NB2F16 245 IO209NB3F23 181 IO11NB0F0 329 IO140PB2F16 246 IO209PB3F23 182 IO11PB0F0 330 IO141NB2F16 235 IO50NB0F4/HCLKAN 317 IO141PB2F16 236 IO210NB4F24 167 IO50PB0F4/HCLKAP 318 IO142NB2F16 239 IO210PB4F24 168 IO51NB0F4/HCLKBN 313 IO142PB2F16 240 IO211NB4F24 173 IO51PB0F4/HCLKBP 314 IO143NB2F16 229 IO213NB4F24 171 IO143PB2F16 230 IO213PB4F24 172 Bank 1 Bank 4 IO52NB1F6/HCLKCN 303 IO144NB2F16 233 IO214NB4F24 161 IO52PB1F6/HCLKCP 304 IO144PB2F16 234 IO214PB4F24 162 IO53NB1F6/HCLKDN 299 IO145NB2F16 223 IO215NB4F24 165 IO53PB1F6/HCLKDP 300 IO145PB2F16 224 IO215PB4F24 166 IO94NB1F10 287 IO146NB2F16 227 IO216NB4F24 155 IO94PB1F10 288 IO146PB2F16 228 IO216PB4F24 156 IO97NB1F10 281 IO217NB4F24 159 IO97PB1F10 282 IO175NB3F20 213 IO217PB4F24 160 IO98NB1F10 285 IO175PB3F20 214 IO219NB4F24 153 IO98PB1F10 286 IO176NB3F20 217 IO219PB4F24 154 IO99NB1F10 275 IO176PB3F20 218 IO260NB4F28/CLKEN 141 IO99PB1F10 276 IO177NB3F20 207 IO260PB4F28/CLKEP 142 IO100NB1F10 279 IO177PB3F20 208 IO261NB4F28/CLKFN 137 IO100PB1F10 280 IO178NB3F20 211 IO261PB4F28/CLKFP 138 IO102NB1F10 273 IO178PB3F20 212 IO102PB1F10 274 IO179NB3F20 205 IO262NB5F30/CLKGN 127 IO103NB1F10 269 IO179PB3F20 206 IO262PB5F30/CLKGP 128 IO103PB1F10 270 IO181NB3F20 201 IO263NB5F30/CLKHN 123 IO181PB3F20 202 IO263PB5F30/CLKHP 124 IO182NB3F20 199 IO304NB5F34 111 Bank 2 IO104NB2F12 3 -2 2 259 Bank 3 v5.4 Bank 5 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO304PB5F34 112 IO356PB6F40 53 GND 47 IO305NB5F34 109 GND 51 IO305PB5F34 110 IO385NB7F44 42 GND 57 IO307NB5F34 103 IO385PB7F44 43 GND 63 IO307PB5F34 104 IO386NB7F44 38 GND 69 IO308NB5F34 105 IO386PB7F44 39 GND 73 IO308PB5F34 106 IO387NB7F44 36 GND 75 IO309NB5F34 97 IO387PB7F44 37 GND 81 IO309PB5F34 98 IO388NB7F44 32 GND 86 IO310NB5F34 99 IO388PB7F44 33 GND 88 IO310PB5F34 100 IO389NB7F44 30 GND 89 IO312NB5F34 93 IO389PB7F44 31 GND 96 IO312PB5F34 94 IO391NB7F44 26 GND 102 IO313NB5F34 92 IO391PB7F44 27 GND 108 IO392NB7F44 24 GND 117 Bank 6 Bank 7 IO314PB6F36 84 IO392PB7F44 25 GND 119 IO316NB6F36 82 IO393NB7F44 20 GND 126 IO316PB6F36 83 IO393PB7F44 21 GND 132 IO317NB6F36 78 IO413NB7F47 14 GND 134 IO317PB6F36 79 IO413PB7F47 15 GND 140 IO319NB6F36 76 IO414NB7F47 8 GND 147 IO319PB6F36 77 IO414PB7F47 9 GND 149 IO349NB6F40 66 IO416NB7F47 12 GND 158 IO349PB6F40 67 IO416PB7F47 13 GND 164 IO350NB6F40 70 IO419NB7F47 6 GND 170 IO350PB6F40 71 IO419PB7F47 7 GND 176 IO351NB6F40 60 GND 177 IO351PB6F40 61 GND 1 GND 180 IO352NB6F40 64 GND 5 GND 186 IO352PB6F40 65 GND 11 GND 192 IO353NB6F40 54 GND 17 GND 194 IO353PB6F40 55 GND 19 GND 198 IO354NB6F40 58 GND 23 GND 204 IO354PB6F40 59 GND 29 GND 210 IO355NB6F40 48 GND 35 GND 216 IO355PB6F40 49 GND 41 GND 220 IO356NB6F40 52 GND 45 GND 222 Dedicated I/O v5.4 3-23 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 3 -2 4 352-Pin CQFP 352-Pin CQFP RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number GND 226 VCCA 34 VCCDA 120 GND 232 VCCA 44 VCCDA 121 GND 238 VCCA 56 VCCDA 122 GND 244 VCCA 72 VCCDA 130 GND 248 VCCA 85 VCCDA 133 GND 250 VCCA 87 VCCDA 143 GND 256 VCCA 101 VCCDA 144 GND 262 VCCA 116 VCCDA 145 GND 264 VCCA 129 VCCDA 146 GND 265 VCCA 131 VCCDA 150 GND 272 VCCA 148 VCCDA 151 GND 278 VCCA 163 VCCDA 152 GND 284 VCCA 175 VCCDA 174 GND 293 VCCA 179 VCCDA 178 GND 295 VCCA 193 VCCDA 191 GND 302 VCCA 209 VCCDA 221 GND 308 VCCA 219 VCCDA 249 GND 310 VCCA 231 VCCDA 266 GND 316 VCCA 247 VCCDA 268 GND 323 VCCA 261 VCCDA 289 GND 325 VCCA 263 VCCDA 290 GND 334 VCCA 277 VCCDA 291 GND 340 VCCA 292 VCCDA 294 GND 345 VCCA 305 VCCDA 296 GND 352 VCCA 307 VCCDA 297 PRA 312 VCCA 324 VCCDA 298 PRB 311 VCCA 339 VCCDA 306 PRC 136 VCCDA 2 VCCDA 309 PRD 135 VCCDA 16 VCCDA 319 TCK 349 VCCDA 46 VCCDA 320 TDI 348 VCCDA 74 VCCDA 321 TDO 347 VCCDA 90 VCCDA 322 TMS 350 VCCDA 91 VCCDA 326 TRST 351 VCCDA 113 VCCDA 327 VCCA 3 VCCDA 114 VCCDA 328 VCCA 4 VCCDA 115 VCCDA 346 VCCA 18 VCCDA 118 VCCIB0 315 v5.4 RTAX-S/SL RadTolerant FPGAs 352-Pin CQFP 352-Pin CQFP 352-Pin CQFP RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number VCCIB0 333 VCCIB3 197 VCCIB6 50 VCCIB0 344 VCCIB3 203 VCCIB6 62 VCCIB1 271 VCCIB3 215 VCCIB6 68 VCCIB1 283 VCCIB4 139 VCCIB6 80 VCCIB1 301 VCCIB4 157 VCCIB7 10 VCCIB2 225 VCCIB4 169 VCCIB7 22 VCCIB2 237 VCCIB5 95 VCCIB7 28 VCCIB2 243 VCCIB5 107 VCCIB7 40 VCCIB2 255 VCCIB5 125 VPUMP 267 VCCIB3 185 v5.4 3-25 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Figure 3-4 * 624-Pin CCGA/LGA (Bottom View) Note: The 624-pin CCGA pin assignments for RTAX250S/SL, RTAX1000S/SL and RTAX2000S/SL are compatible except for the following pins. Table 3-2 * Compatibility Table for the CGA/LGA 624 Package RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX250S/SL NA A12, AD11, AE17, B15, D13 A12, A14, AA20, AB13, AD11, AD4, AE12, B15, D13, F21, G10 RTAX1000S/SL A12, AD11, AE17, B15, D13 NA A14, AA20, AB13, AD4, AE12, F21, G10 RTAX2000S/SL A12, A14, AA20, AB13, AD11, AD4, AE12, B15, D13, F21, G10 A14, AA20, AB13, AD4, AE12, F21, G10 NA Where exceptions occur, the smaller density devices have those pins designated as No Connects (NC). Customers are therefore recommended to layout their board targeting the larger density device, in order to preserve interchangeability between the two devices. Note: RTAX4000S is not pin compatible with any of the smaller density devices. For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -2 6 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number Bank 0 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number IO21PB1F1 A19 IO37PB2F2 K24 IO00NB0F0 C9 IO22NB1F1 D18 IO38NB2F2 J24 IO00PB0F0 C8 IO22PB1F1 D17 IO38PB2F2 H24 IO01NB0F0 B5 IO23NB1F1 A22 IO39NB2F2 N22 IO01PB0F0 B4 IO23PB1F1 A21 IO39PB2F2 M22 IO02NB0F0 D10 IO24NB1F1 G17 IO40NB2F2 N24 IO02PB0F0 D9 IO24PB1F1 H17 IO40PB2F2 M24 IO03NB0F0 A5 IO25NB1F1 C21 IO41NB2F2 N19 IO03PB0F0 A4 IO25PB1F1 C20 IO41PB2F2 N18 IO04NB0F0 H8 IO26NB1F1 C19 IO42NB2F2 L25 IO04PB0F0 H7 IO26PB1F1 C18 IO42PB2F2 K25 IO05NB0F0 A7 IO27NB1F1 D20 IO43NB2F2 N23 IO05PB0F0 A6 IO27PB1F1 D19 IO43PB2F2 M23 IO06NB0F0 H10 IO14NB1F1/HCLKCN G15 IO44NB2F2 N25 IO06PB0F0 H9 IO14PB1F1/HCLKCP G14 IO44PB2F2 M25 IO07NB0F0 B11 IO15NB1F1/HCLKDN B14 IO07PB0F0 B10 IO15PB1F1/HCLKDP B13 IO08NB0F0 J8 IO08PB0F0 J7 IO28NB2F2 IO09NB0F0 A9 IO09PB0F0 Bank 3 IO45NB3F3 R22 IO45PB3F3 P22 J22 IO46NB3F3 R25 IO28PB2F2 H22 IO46PB3F3 P25 B9 IO29NB2F2 L18 IO47NB3F3 R23 IO12NB0F0/HCLKAN G13 IO29PB2F2 K18 IO47PB3F3 P23 IO12PB0F0/HCLKAP G12 IO30NB2F2 F23 IO48NB3F3 Y25 IO13NB0F0/HCLKBN C13 IO30PB2F2 E23 IO48PB3F3 W25 IO13PB0F0/HCLKBP C12 IO31NB2F2 J21 IO49NB3F3 U24 IO31PB2F2 J20 IO49PB3F3 U23 Bank 1 Bank 2 IO16NB1F1 D14 IO32NB2F2 E25 IO50NB3F3 T24 IO16PB1F1 C14 IO32PB2F2 D25 IO50PB3F3 R24 IO17NB1F1 A16 IO33NB2F2 M19 IO51NB3F3 Y23 IO17PB1F1 A15 IO33PB2F2 M18 IO51PB3F3 AA23 IO18NB1F1 H20 IO34NB2F2 H23 IO52NB3F3 V23 IO18PB1F1 H19 IO34PB2F2 G23 IO52PB3F3 V24 IO19NB1F1 B17 IO35NB2F2 L22 IO53NB3F3 P20 IO19PB1F1 B16 IO35PB2F2 K22 IO53PB3F3 P19 IO20NB1F1 D16 IO36NB2F2 G25 IO54NB3F3 U25 IO20PB1F1 D15 IO36PB2F2 F25 IO54PB3F3 T25 IO21NB1F1 A20 IO37NB2F2 L24 IO55NB3F3 V22 v5.4 3-27 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number IO55PB3F3 U22 IO73PB4F4 AE16 IO91NB6F6 U4 IO56NB3F3 AA24 IO74NB4F4/CLKEN W14 IO91PB6F6 V4 IO56PB3F3 Y24 IO74PB4F4/CLKEP W15 IO92NB6F6 AA1 IO57NB3F3 V20 IO75NB4F4/CLKFN AC13 IO92PB6F6 AB1 IO57PB3F3 U20 IO75PB4F4/CLKFP AD13 IO93NB6F6 W2 IO58NB3F3 AB25 IO93PB6F6 Y2 IO58PB3F3 AA25 IO78NB5F5 AE10 IO94NB6F6 V3 IO59NB3F3 Y22 IO78PB5F5 AE11 IO94PB6F6 W3 IO59PB3F3 Y21 IO79NB5F5 AD9 IO95NB6F6 R4 IO60NB3F3 W22 IO79PB5F5 AD10 IO95PB6F6 T4 IO60PB3F3 W23 IO80NB5F5 V9 IO96NB6F6 W1 IO61NB3F3 T18 IO80PB5F5 V10 IO96PB6F6 Y1 IO61PB3F3 R18 IO81NB5F5 AD7 IO97NB6F6 Y5 IO81PB5F5 AD8 IO97PB6F6 W5 Bank 4 3 -2 8 624-Pin CCGA/LGA Bank 5 IO62NB4F4 V19 IO82NB5F5 AB10 IO98NB6F6 T2 IO62PB4F4 W19 IO82PB5F5 AB11 IO98PB6F6 U2 IO63NB4F4 AE19 IO83NB5F5 AE6 IO99NB6F6 N3 IO63PB4F4 AE20 IO83PB5F5 AE7 IO99PB6F6 P3 IO64NB4F4 W18 IO84NB5F5 AB8 IO100NB6F6 T1 IO64PB4F4 V18 IO84PB5F5 AC8 IO100PB6F6 U1 IO65NB4F4 AC20 IO85NB5F5 AE4 IO101NB6F6 N4 IO65PB4F4 AC21 IO85PB5F5 AE5 IO101PB6F6 P4 IO66NB4F4 AD14 IO86NB5F5 U13 IO102NB6F6 P2 IO66PB4F4 AC14 IO86PB5F5 V13 IO102PB6F6 R2 IO67NB4F4 AD21 IO87NB5F5 AC5 IO103NB6F6 R8 IO67PB4F4 AD22 IO87PB5F5 AC6 IO103PB6F6 T8 IO68NB4F4 AD15 IO88NB5F5 Y7 IO104NB6F6 P1 IO68PB4F4 AD16 IO88PB5F5 W7 IO104PB6F6 R1 IO69NB4F4 AD19 IO89NB5F5 AB7 IO105NB6F6 M2 IO69PB4F4 AD20 IO89PB5F5 AC7 IO105PB6F6 N2 IO70NB4F4 AB14 IO76NB5F5/CLKGN W13 IO106NB6F6 M1 IO70PB4F4 AB15 IO76PB5F5/CLKGP Y13 IO106PB6F6 N1 IO71NB4F4 AD17 IO77NB5F5/CLKHN AC12 IO71PB4F4 AD18 IO77PB5F5/CLKHP AD12 IO72NB4F4 V15 IO72PB4F4 V16 IO90NB6F6 IO73NB4F4 AE15 IO90PB6F6 IO107NB7F7 H4 IO107PB7F7 J4 Y3 IO108NB7F7 K1 AA3 IO108PB7F7 L1 Bank 6 v5.4 Bank 7 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number IO109NB7F7 L3 GND V5 GND C10 IO109PB7F7 M3 GND AA10 GND C16 IO10NB0F0 D12 GND AA16 GND C23 IO10PB0F0 D11 GND AA18 GND C3 IO110NB7F7 J2 GND T21 GND D22 IO110PB7F7 J1 GND K21 GND D4 IO111NB7F7 N10 GND H21 GND E21 IO111PB7F7 N9 GND E16 GND E5 IO112NB7F7 K2 GND E10 GND H1 IO112PB7F7 L2 GND E8 GND H25 IO113NB7F7 K8 GND A18 GND K23 IO113PB7F7 L8 GND A2 GND K3 IO114NB7F7 F1 GND A24 GND L11 IO114PB7F7 G1 GND A25 GND L12 IO115NB7F7 J6 GND A8 GND L13 IO115PB7F7 J5 GND AA21 GND L14 IO116NB7F7 H3 GND AA5 GND L15 IO116PB7F7 H2 GND AB22 GND M11 IO117NB7F7 K4 GND AB4 GND M12 IO117PB7F7 L4 GND AC10 GND M13 IO118NB7F7 E2 GND AC16 GND M14 IO118PB7F7 F2 GND AC23 GND M15 IO119NB7F7 M9 GND AC3 GND N11 IO119PB7F7 M8 GND AD1 GND N12 IO11NB0F0 A11 GND AD2 GND N13 IO11PB0F0 A10 GND AD24 GND N14 IO120NB7F7 D1 GND AD25 GND N15 IO120PB7F7 E1 GND AE1 GND P11 IO121NB7F7 F3 GND AE18 GND P12 IO121PB7F7 E3 GND AE2 GND P13 IO122NB7F7 G4 GND AE24 GND P14 IO122PB7F7 G3 GND AE25 GND P15 IO123NB7F7 H5 GND AE8 GND R11 IO123PB7F7 H6 GND B1 GND R12 GND B2 GND R13 Dedicated IO GND K5 GND B24 GND R14 GND T5 GND B25 GND R15 v5.4 3-29 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 3 -3 0 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number GND T23 NC AE17 NC F17 GND T3 NC AE21 NC F18 GND V1 NC AE22 NC F19 GND V25 NC AE9 NC F20 NC A12 NC B12 NC F21 NC A14 NC B15 NC F24 NC A17 NC B18 NC F7 NC AA11 NC B19 NC F8 NC AA12 NC B20 NC F9 NC AA14 NC B21 NC G10 NC AA17 NC B22 NC G11 NC AA19 NC B6 NC G16 NC AA2 NC B7 NC G18 NC AA20 NC B8 NC G19 NC AA6 NC C11 NC G2 NC AA8 NC C17 NC G20 NC AA9 NC C7 NC G21 NC AB13 NC D13 NC G22 NC AB16 NC D2 NC G24 NC AB17 NC D24 NC G6 NC AB18 NC D7 NC G7 NC AB19 NC D8 NC G8 NC AB2 NC E11 NC G9 NC AB24 NC E12 NC H11 NC AB6 NC E14 NC H12 NC AB9 NC E15 NC H13 NC AC15 NC E17 NC H14 NC AC17 NC E18 NC H15 NC AC18 NC E24 NC H16 NC AC19 NC E7 NC H18 NC AC9 NC E9 NC J12 NC AD11 NC F10 NC J13 NC AD4 NC F11 NC J14 NC AD5 NC F12 NC J18 NC AD6 NC F14 NC J19 NC AE12 NC F15 NC J23 NC AE14 NC F16 NC J25 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number NC J3 NC R21 NC W4 NC K13 NC R3 NC W6 NC K19 NC R5 NC W8 NC K20 NC R6 NC W9 NC K6 NC R7 NC Y10 NC K7 NC T13 NC Y11 NC L19 NC T19 NC Y12 NC L20 NC T20 NC Y14 NC L21 NC T22 NC Y15 NC L23 NC T6 NC Y16 NC L5 NC T7 NC Y17 NC L6 NC U12 NC Y18 NC L7 NC U14 NC Y19 NC M17 NC U18 NC Y20 NC M20 NC U19 NC Y6 NC M21 NC U21 NC Y8 NC M4 NC U3 NC Y9 NC M5 NC U5 PRA F13 NC M6 NC U6 PRB A13 NC M7 NC U7 PRC AB12 NC N16 NC U8 PRD AE13 NC N17 NC V11 TCK F5 NC N20 NC V12 TDI C5 NC N6 NC V14 TDO F6 NC N7 NC V17 TMS D6 NC N8 NC V2 TRST E6 NC P17 NC V21 VCCA F4 NC P18 NC V6 VCCA Y4 NC P21 NC V7 VCCA AB20 NC P24 NC V8 VCCA F22 NC P5 NC W10 VCCA J17 NC P6 NC W11 VCCA J9 NC P7 NC W12 VCCA K10 NC P8 NC W16 VCCA K11 NC P9 NC W17 VCCA K15 NC R19 NC W20 VCCA K16 NC R20 NC W24 VCCA L10 v5.4 3-31 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 3 -3 2 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number RTAX250S/SL Pin Function Pin Number VCCA L16 VCCIB2 D23 VCCIB7 K9 VCCA R10 VCCIB2 E22 VCCIB7 L9 VCCA R16 VCCIB2 K17 VCCIB7 M10 VCCA T10 VCCIB2 L17 VPUMP E20 VCCA T11 VCCIB2 M16 VCCA T15 VCCIB3 AA22 VCCA T16 VCCIB3 AB23 VCCA U17 VCCIB3 AC24 VCCA U9 VCCIB3 AC25 VCCDA G5 VCCIB3 P16 VCCDA N5 VCCIB3 R17 VCCDA AA7 VCCIB3 T17 VCCDA AC11 VCCIB4 AB21 VCCDA AA13 VCCIB4 AC22 VCCDA AA15 VCCIB4 AD23 VCCDA W21 VCCIB4 AE23 VCCDA N21 VCCIB4 T14 VCCDA E19 VCCIB4 U15 VCCDA C15 VCCIB4 U16 VCCDA E13 VCCIB5 AB5 VCCDA C6 VCCIB5 AC4 VCCIB0 A3 VCCIB5 AD3 VCCIB0 B3 VCCIB5 AE3 VCCIB0 C4 VCCIB5 T12 VCCIB0 D5 VCCIB5 U10 VCCIB0 J10 VCCIB5 U11 VCCIB0 J11 VCCIB6 AA4 VCCIB0 K12 VCCIB6 AB3 VCCIB1 A23 VCCIB6 AC1 VCCIB1 B23 VCCIB6 AC2 VCCIB1 C22 VCCIB6 P10 VCCIB1 D21 VCCIB6 R9 VCCIB1 J15 VCCIB6 T9 VCCIB1 J16 VCCIB7 C1 VCCIB1 K14 VCCIB7 C2 VCCIB2 C24 VCCIB7 D3 VCCIB2 C25 VCCIB7 E4 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number Bank 0 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO23NB0F2 E11 IO42NB1F4 G21 IO00NB0F0 F8 IO23PB0F2 F11 IO42PB1F4 G20 IO00PB0F0 F7 IO24NB0F2 D7 IO43NB1F4 A16 IO02NB0F0 G7 IO24PB0F2 E7 IO43PB1F4 A15 IO02PB0F0 G6 IO25PB0F2 B12 IO44NB1F4 A20 IO04NB0F0 E9 IO26NB0F2 H11 IO44PB1F4 A19 IO04PB0F0 D8 IO26PB0F2 G11 IO45NB1F4 B17 IO06NB0F0 G9 IO27NB0F2 C11 IO45PB1F4 B16 IO06PB0F0 G8 IO27PB0F2 B8 IO46NB1F4 G17 IO07PB0F0 B6 IO28NB0F2 J13 IO46PB1F4 H17 IO08NB0F0 F10 IO28PB0F2 K13 IO47NB1F4 A17 IO08PB0F0 F9 IO29NB0F2 J8 IO48NB1F4 C19 IO09PB0F0 C7 IO29PB0F2 J7 IO48PB1F4 C18 IO10NB0F0 H8 IO30NB0F2/HCLKAN G13 IO49NB1F4 B20 IO10PB0F0 H7 IO30PB0F2/HCLKAP G12 IO49PB1F4 B19 IO11NB0F0 D10 IO31NB0F2/HCLKBN C13 IO50NB1F4 H20 IO11PB0F0 D9 IO31PB0F2/HCLKBP C12 IO50PB1F4 H19 IO12NB0F1 B5 Bank 1 IO51NB1F4 A22 IO12PB0F1 B4 IO32NB1F3/HCLKCN G15 IO51PB1F4 A21 IO13NB0F1 A7 IO32PB1F3/HCLKCP G14 IO52NB1F4 C21 IO13PB0F1 A6 IO33NB1F3/HCLKDN B14 IO52PB1F4 C20 IO14NB0F1 C9 IO33PB1F3/HCLKDP B13 IO53NB1F4 B22 IO14PB0F1 C8 IO34NB1F3 G16 IO53PB1F4 B21 IO15PB0F1 B7 IO34PB1F3 H16 IO54NB1F5 J18 IO16NB0F1 A5 IO35NB1F3 C17 IO54PB1F5 J19 IO16PB0F1 A4 IO35PB1F3 B18 IO55NB1F5 D18 IO17NB0F1 A9 IO36NB1F3 H18 IO55PB1F5 D17 IO17PB0F1 B9 IO36PB1F3 H15 IO56NB1F5 F20 IO18NB0F1 D12 IO37NB1F3 H13 IO56PB1F5 F19 IO18PB0F1 D11 IO38NB1F3 E15 IO58NB1F5 E17 IO20NB0F1 B11 IO38PB1F3 F15 IO58PB1F5 F17 IO20PB0F1 B10 IO39NB1F3 D14 IO60NB1F5 D20 IO21NB0F1 A11 IO39PB1F3 C14 IO60PB1F5 D19 IO21PB0F1 A10 IO40NB1F3 D16 IO62NB1F5 E18 IO22NB0F2 H10 IO40PB1F3 D15 IO62PB1F5 F18 IO22PB0F2 H9 IO41NB1F4 F16 IO63NB1F5 G19 v5.4 3-33 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO63PB1F5 G18 IO84NB2F7 M20 IO105NB3F9 R23 IO84PB2F7 M21 IO105PB3F9 P23 Bank 2 3 -3 4 IO64NB2F6 M17 IO86NB2F8 E25 IO106NB3F9 R19 IO64PB2F6 G22 IO86PB2F8 D25 IO106PB3F9 R20 IO65NB2F6 J21 IO87NB2F8 L24 IO107NB3F10 AB24 IO65PB2F6 J20 IO87PB2F8 K24 IO108NB3F10 R25 IO66NB2F6 L23 IO88NB2F8 G24 IO108PB3F10 P25 IO66PB2F6 K20 IO88PB2F8 F24 IO109NB3F10 U25 IO67NB2F6 F23 IO89NB2F8 J25 IO109PB3F10 T25 IO67PB2F6 E23 IO90NB2F8 G25 IO110NB3F10 U24 IO68NB2F6 L18 IO90PB2F8 F25 IO110PB3F10 U23 IO68PB2F6 K18 IO91NB2F8 L25 IO112NB3F10 T24 IO70NB2F6 E24 IO91PB2F8 K25 IO112PB3F10 R24 IO70PB2F6 D24 IO92NB2F8 J24 IO113NB3F10 Y25 IO71NB2F6 H23 IO92PB2F8 H24 IO113PB3F10 W25 IO71PB2F6 G23 IO93PB2F8 J23 IO114NB3F10 V23 IO72NB2F6 L19 IO94NB2F8 N24 IO114PB3F10 V24 IO72PB2F6 K19 IO94PB2F8 M24 IO116NB3F10 AA24 IO74NB2F7 J22 IO95NB2F8 N25 IO116PB3F10 Y24 IO74PB2F7 H22 IO95PB2F8 M25 IO117NB3F10 AB25 IO75NB2F7 N23 IO117PB3F10 AA25 IO75PB2F7 M23 IO96NB3F9 T18 IO118NB3F11 T20 IO76NB2F7 N17 IO96PB3F9 R18 IO118PB3F11 R21 IO76PB2F7 N16 IO97NB3F9 N20 IO120NB3F11 W22 IO77NB2F7 L22 IO97PB3F9 P24 IO120PB3F11 W23 IO77PB2F7 K22 IO98NB3F9 P20 IO122NB3F11 V22 IO78NB2F7 M19 IO98PB3F9 P19 IO122PB3F11 U22 IO78PB2F7 M18 IO99NB3F9 P21 IO124NB3F11 Y23 IO79NB2F7 N19 IO100NB3F9 T22 IO124PB3F11 AA23 IO79PB2F7 N18 IO100PB3F9 W24 IO126NB3F11 V21 IO80NB2F7 L21 IO101NB3F9 R22 IO126PB3F11 U21 IO80PB2F7 L20 IO101PB3F9 P22 IO128NB3F11 Y22 IO82NB2F7 P18 IO102NB3F9 U19 IO128PB3F11 Y21 IO82PB2F7 P17 IO102PB3F9 T19 IO83NB2F7 N22 IO104NB3F9 V20 IO129NB4F12 W20 IO83PB2F7 M22 IO104PB3F9 U20 IO129PB4F12 Y20 Bank 3 v5.4 Bank 4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO131NB4F12 V19 IO153NB4F14 Y15 IO173PB5F16 Y11 IO131PB4F12 W19 IO153PB4F14 Y16 IO174NB5F16 AB10 IO133NB4F12 Y18 IO155NB4F14 V15 IO174PB5F16 AB11 IO133PB4F12 Y19 IO155PB4F14 V16 IO175NB5F16 AC9 IO135NB4F12 W18 IO156NB4F14 AB14 IO175PB5F16 AE9 IO135PB4F12 V18 IO156PB4F14 AB15 IO177NB5F16 AA8 IO137NB4F12 Y17 IO157NB4F14 AE14 IO177PB5F16 Y8 IO137PB4F12 AA17 IO157PB4F14 AC18 IO178NB5F16 Y6 IO138NB4F12 AB19 IO158NB4F14 AC15 IO178PB5F16 W6 IO138PB4F12 AB18 IO158PB4F14 AC19 IO179NB5F16 Y10 IO139NB4F13 AA19 IO159NB4F14/CLKEN W14 IO179PB5F16 W10 IO139PB4F13 U18 IO159PB4F14/CLKEP W15 IO180NB5F16 Y7 IO140NB4F13 AC20 IO160NB4F14/CLKFN AC13 IO180PB5F16 W7 IO140PB4F13 AC21 IO160PB4F14/CLKFP AD13 IO181NB5F17 AD9 IO141NB4F13 AD17 Bank 5 IO181PB5F17 AD10 IO141PB4F13 AD18 IO161NB5F15/CLKGN W13 IO182NB5F17 AE10 IO142NB4F13 AD21 IO161PB5F15/CLKGP Y13 IO182PB5F17 AE11 IO142PB4F13 AD22 IO162NB5F15/CLKHN AC12 IO183NB5F17 AD7 IO143NB4F13 AB17 IO162PB5F15/CLKHP AD12 IO183PB5F17 AD8 IO143PB4F13 AC17 IO163NB5F15 V9 IO184NB5F17 AB9 IO144PB4F13 AE22 IO163PB5F15 V10 IO185NB5F17 AE6 IO145NB4F13 AE15 IO164NB5F15 V11 IO185PB5F17 AE7 IO145PB4F13 AE16 IO164PB5F15 T13 IO186NB5F17 AE4 IO146NB4F13 AD19 IO165NB5F15 U13 IO186PB5F17 AE5 IO146PB4F13 AD20 IO165PB5F15 V13 IO187NB5F17 AA9 IO147NB4F13 AD15 IO167NB5F15 W11 IO187PB5F17 Y9 IO147PB4F13 AD16 IO167PB5F15 W12 IO188NB5F17 U8 IO148PB4F13 AE21 IO168NB5F15 AB6 IO189NB5F17 AD5 IO149NB4F13 AD14 IO168PB5F15 AA6 IO189PB5F17 AD6 IO149PB4F13 AC14 IO169NB5F15 V8 IO191NB5F17 AC5 IO150NB4F13 AE19 IO169PB5F15 V7 IO191PB5F17 AC6 IO150PB4F13 AE20 IO171NB5F16 W8 IO192NB5F17 AB7 IO151NB4F13 V17 IO171PB5F16 W9 IO192PB5F17 AC7 IO151PB4F13 W17 IO172NB5F16 AB8 IO152NB4F14 AB16 IO172PB5F16 AC8 IO193NB6F18 U6 IO152PB4F14 W16 IO173NB5F16 AA11 IO193PB6F18 U5 v5.4 Bank 6 3-35 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number IO194NB6F18 Y3 IO215PB6F20 V4 IO237NB7F22 N8 IO194PB6F18 AA3 IO216NB6F20 P8 IO237PB7F22 N7 IO195NB6F18 V6 IO216PB6F20 R3 IO238NB7F22 M5 IO195PB6F18 W4 IO217NB6F20 P7 IO239NB7F22 L6 IO197NB6F18 R5 IO217PB6F20 R7 IO239PB7F22 L5 IO197PB6F18 U3 IO219NB6F20 R4 IO240NB7F22 M4 IO198NB6F18 P6 IO219PB6F20 T4 IO241NB7F22 L7 IO199NB6F18 Y5 IO220NB6F20 P2 IO241PB7F22 M7 IO199PB6F18 W5 IO220PB6F20 R2 IO242NB7F22 J3 IO200NB6F18 V3 IO221NB6F20 N4 IO243NB7F22 M9 IO200PB6F18 W3 IO221PB6F20 P4 IO243PB7F22 M8 IO201NB6F18 T7 IO223NB6F20 M2 IO244NB7F22 P9 IO201PB6F18 U7 IO223PB6F20 N2 IO244PB7F22 N6 IO202NB6F18 V2 IO224NB6F20 N3 IO245NB7F22 K8 IO203NB6F19 W2 IO224PB6F20 P3 IO245PB7F22 L8 IO203PB6F19 Y2 IO246NB7F22 F3 IO204NB6F19 AA1 IO225NB7F21 J2 IO246PB7F22 E3 IO204PB6F19 AB1 IO225PB7F21 J1 IO247NB7F23 K7 IO205NB6F19 R6 IO226PB7F21 G2 IO247PB7F23 K6 IO205PB6F19 T6 IO227NB7F21 H3 IO248NB7F23 D2 IO206NB6F19 W1 IO227PB7F21 H2 IO249NB7F23 G4 IO206PB6F19 Y1 IO229NB7F21 K2 IO249PB7F23 G3 IO207NB6F19 T2 IO229PB7F21 L2 IO251NB7F23 N10 IO207PB6F19 U2 IO230NB7F21 K1 IO251PB7F23 N9 IO208NB6F19 T1 IO230PB7F21 L1 IO253NB7F23 H4 IO208PB6F19 U1 IO231NB7F21 E2 IO253PB7F23 J4 IO209NB6F19 AA2 IO231PB7F21 F2 IO255NB7F23 J6 IO209PB6F19 AB2 IO232NB7F21 F1 IO255PB7F23 J5 IO210NB6F19 P5 IO232PB7F21 G1 IO257NB7F23 H5 IO211NB6F19 M1 IO233NB7F21 L3 IO257PB7F23 H6 IO211PB6F19 N1 IO233PB7F21 M3 Dedicated I/O IO212NB6F19 P1 IO234NB7F21 D1 GND K5 IO212PB6F19 R1 IO234PB7F21 E1 GND A18 IO213NB6F19 R8 IO235NB7F21 K4 GND A2 IO213PB6F19 T8 IO235PB7F21 L4 GND A24 IO215NB6F20 U4 IO236NB7F22 M6 GND A25 3 -3 6 Bank 7 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number GND A8 GND E8 GND V1 GND AA10 GND H1 GND V25 GND AA16 GND H21 GND V5 GND AA18 GND H25 NC A14 GND AA21 GND K21 NC AA12 GND AA5 GND K23 NC AA14 GND AB22 GND K3 NC AA20 GND AB4 GND L11 NC AB13 GND AC10 GND L12 NC AD4 GND AC16 GND L13 NC AE12 GND AC23 GND L14 NC E12 GND AC3 GND L15 NC E14 GND AD1 GND M11 NC F12 GND AD2 GND M12 NC F14 GND AD24 GND M13 NC F21 GND AD25 GND M14 NC G10 GND AE1 GND M15 NC H12 GND AE18 GND N11 NC H14 GND AE2 GND N12 NC J12 GND AE24 GND N13 NC J14 GND AE25 GND N14 NC U12 GND AE8 GND N15 NC U14 GND B1 GND P11 NC V12 GND B2 GND P12 NC V14 GND B24 GND P13 NC Y12 GND B25 GND P14 NC Y14 GND C10 GND P15 PRA F13 GND C16 GND R11 PRB A13 GND C23 GND R12 PRC AB12 GND C3 GND R13 PRD AE13 GND D22 GND R14 TCK F5 GND D4 GND R15 TDI C5 GND E10 GND T21 TDO F6 GND E16 GND T23 TMS D6 GND E21 GND T3 TRST E6 GND E5 GND T5 VCCA AB20 v5.4 3-37 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number RTAX1000S/SL Function Pin Number VCCA F22 VCCIB0 A3 VCCIB5 AC4 VCCA F4 VCCIB0 B3 VCCIB5 AD3 VCCA J17 VCCIB0 C4 VCCIB5 AE3 VCCA J9 VCCIB0 D5 VCCIB5 T12 VCCA K10 VCCIB0 J10 VCCIB5 U10 VCCA K11 VCCIB0 J11 VCCIB5 U11 VCCA K15 VCCIB0 K12 VCCIB6 AA4 VCCA K16 VCCIB1 A23 VCCIB6 AB3 VCCA L10 VCCIB1 B23 VCCIB6 AC1 VCCA L16 VCCIB1 C22 VCCIB6 AC2 VCCA R10 VCCIB1 D21 VCCIB6 P10 VCCA R16 VCCIB1 J15 VCCIB6 R9 VCCA T10 VCCIB1 J16 VCCIB6 T9 VCCA T11 VCCIB1 K14 VCCIB7 C1 VCCA T15 VCCIB2 C24 VCCIB7 C2 VCCA T16 VCCIB2 C25 VCCIB7 D3 VCCA U17 VCCIB2 D23 VCCIB7 E4 VCCA U9 VCCIB2 E22 VCCIB7 K9 VCCA Y4 VCCIB2 K17 VCCIB7 L9 VCCDA A12 VCCIB2 L17 VCCIB7 M10 VCCDA AA13 VCCIB2 M16 VPUMP E20 VCCDA AA15 VCCIB3 AA22 VCCDA AA7 VCCIB3 AB23 VCCDA AC11 VCCIB3 AC24 VCCDA AD11 VCCIB3 AC25 VCCDA AE17 VCCIB3 P16 VCCDA B15 VCCIB3 R17 VCCDA C15 VCCIB3 T17 VCCDA C6 VCCIB4 AB21 VCCDA D13 VCCIB4 AC22 VCCDA E13 VCCIB4 AD23 VCCDA E19 VCCIB4 AE23 VCCDA G5 VCCIB4 T14 VCCDA N21 VCCIB4 U15 VCCDA N5 VCCIB4 U16 VCCDA W21 VCCIB5 AB5 3 -3 8 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number Bank 0 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO30NB0F2 B11 IO57PB1F5 D15 IO00NB0F0 D7 IO30PB0F2 B10 IO58NB1F5 A22 IO00PB0F0 E7 IO31NB0F2 E11 IO58PB1F5 A21 IO01NB0F0 G7 IO31PB0F2 F11 IO59NB1F5 F16 IO01PB0F0 G6 IO33NB0F2 D12 IO61NB1F5 G17 IO02NB0F0 B5 IO33PB0F2 D11 IO61PB1F5 H17 IO02PB0F0 B4 IO34NB0F3 A11 IO62NB1F5 B17 IO04PB0F0 C7 IO34PB0F3 A10 IO62PB1F5 B16 IO05NB0F0 F8 IO37NB0F3 J13 IO63NB1F5 H18 IO05PB0F0 F7 IO37PB0F3 K13 IO65NB1F6 C17 IO06NB0F0 H8 IO38NB0F3 H11 IO66PB1F6 B18 IO06PB0F0 H7 IO38PB0F3 G11 IO67NB1F6 J18 IO11NB0F0 J8 IO40PB0F3 B12 IO67PB1F6 J19 IO11PB0F0 J7 IO41NB0F3/HCLKAN G13 IO68NB1F6 B20 IO12PB0F1 B6 IO41PB0F3/HCLKAP G12 IO68PB1F6 B19 IO13NB0F1 E9 IO42NB0F3/HCLKBN C13 IO69NB1F6 E17 IO13PB0F1 D8 IO42PB0F3/HCLKBP C12 IO69PB1F6 F17 IO15NB0F1 C9 Bank 1 IO70NB1F6 B22 IO15PB0F1 C8 IO43NB1F4/HCLKCN G15 IO70PB1F6 B21 IO16NB0F1 A5 IO43PB1F4/HCLKCP G14 IO71PB1F6 G18 IO16PB0F1 A4 IO44NB1F4/HCLKDN B14 IO73NB1F6 G19 IO17NB0F1 D10 IO44PB1F4/HCLKDP B13 IO74NB1F6 C19 IO17PB0F1 D9 IO45NB1F4 H13 IO74PB1F6 C18 IO18NB0F1 A7 IO47NB1F4 D14 IO75NB1F6 D18 IO18PB0F1 A6 IO47PB1F4 C14 IO75PB1F6 D17 IO19NB0F1 G9 IO48NB1F4 A16 IO76NB1F7 C21 IO19PB0F1 G8 IO48PB1F4 A15 IO76PB1F7 C20 IO20PB0F1 B7 IO49PB1F4 H15 IO79NB1F7 H20 IO23NB0F2 F10 IO51NB1F4 E15 IO79PB1F7 H19 IO23PB0F2 F9 IO51PB1F4 F15 IO80NB1F7 E18 IO26NB0F2 C11 IO52NB1F4 A17 IO80PB1F7 F18 IO26PB0F2 B8 IO55NB1F5 G16 IO81NB1F7 G21 IO27NB0F2 H10 IO55PB1F5 H16 IO81PB1F7 G20 IO27PB0F2 H9 IO56NB1F5 A20 IO82NB1F7 F20 IO28NB0F2 A9 IO56PB1F5 A19 IO82PB1F7 F19 IO28PB0F2 B9 IO57NB1F5 D16 IO85NB1F7 D20 v5.4 3-39 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO85PB1F7 D19 IO112NB2F10 L24 IO146NB3F13 T24 IO112PB2F10 K24 IO146PB3F13 R24 Bank 2 3 -4 0 IO86NB2F8 F23 IO113NB2F10 N17 IO147NB3F13 T20 IO86PB2F8 E23 IO115NB2F10 M20 IO147PB3F13 R20 IO87NB2F8 H23 IO115PB2F10 M21 IO148NB3F13 U25 IO87PB2F8 G23 IO117NB2F10 N19 IO148PB3F13 T25 IO88NB2F8 E24 IO117PB2F10 N18 IO149NB3F13 T22 IO88PB2F8 D24 IO118NB2F11 J25 IO153NB3F14 U19 IO89NB2F8 M17 IO121NB2F11 N24 IO153PB3F14 T19 IO89PB2F8 G22 IO121PB2F11 M24 IO154NB3F14 Y25 IO91NB2F8 J22 IO122NB2F11 L25 IO154PB3F14 W25 IO91PB2F8 H22 IO122PB2F11 K25 IO157NB3F14 V20 IO92NB2F8 L18 IO123NB2F11 N22 IO157PB3F14 U20 IO92PB2F8 K18 IO123PB2F11 M22 IO158NB3F14 AB25 IO96NB2F9 G24 IO124NB2F11 N23 IO158PB3F14 AA25 IO96PB2F9 F24 IO124PB2F11 M23 IO160PB3F14 W24 IO97NB2F9 J21 IO127NB2F11 P18 IO161NB3F15 U24 IO97PB2F9 J20 IO127PB2F11 P17 IO161PB3F15 U23 IO98PB2F9 J23 IO128NB2F11 N25 IO162NB3F15 AA24 IO99NB2F9 L19 IO128PB2F11 M25 IO162PB3F15 Y24 IO99PB2F9 K19 IO163NB3F15 V22 IO100NB2F9 E25 IO129NB3F12 N20 IO163PB3F15 U22 IO100PB2F9 D25 IO130PB3F12 P24 IO164NB3F15 V23 IO103PB2F9 K20 IO131NB3F12 P21 IO164PB3F15 V24 IO105NB2F9 M19 IO133NB3F12 P20 IO166NB3F15 AB24 IO105PB2F9 M18 IO133PB3F12 P19 IO167NB3F15 V21 IO106NB2F9 J24 IO138NB3F12 R23 IO167PB3F15 U21 IO106PB2F9 H24 IO138PB3F12 P23 IO168NB3F15 Y23 IO107NB2F10 L23 IO139NB3F13 R22 IO168PB3F15 AA23 IO107PB2F10 N16 IO139PB3F13 P22 IO169NB3F15 W22 IO109NB2F10 L22 IO141NB3F13 R19 IO169PB3F15 W23 IO109PB2F10 K22 IO142NB3F13 R25 IO170NB3F15 Y22 IO110NB2F10 G25 IO142PB3F13 P25 IO170PB3F15 Y21 IO110PB2F10 F25 IO143PB3F13 R21 IO111NB2F10 L21 IO145NB3F13 T18 IO171NB4F16 AC20 IO111PB2F10 L20 IO145PB3F13 R18 IO171PB4F16 AC21 Bank 3 v5.4 Bank 4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO172NB4F16 W20 IO206NB4F19 AB14 IO229PB5F21 AD10 IO172PB4F16 Y20 IO206PB4F19 AB15 IO230NB5F21 V11 IO173NB4F16 AD21 IO207NB4F19 AE15 IO233NB5F21 AD7 IO173PB4F16 AD22 IO207PB4F19 AE16 IO233PB5F21 AD8 IO174NB4F16 AA19 IO208PB4F19 W16 IO234NB5F21 V9 IO176NB4F16 Y18 IO209NB4F19 AE14 IO234PB5F21 V10 IO176PB4F16 Y19 IO210NB4F19 V15 IO236NB5F22 AC9 IO177NB4F16 AB19 IO210PB4F19 V16 IO238NB5F22 W8 IO177PB4F16 AB18 IO211NB4F19 AD14 IO238PB5F22 W9 IO182NB4F17 V19 IO211PB4F19 AC14 IO239NB5F22 AE4 IO182PB4F17 W19 IO212NB4F19/CLKEN W14 IO239PB5F22 AE5 IO183PB4F17 AC19 IO212PB4F19/CLKEP W15 IO240NB5F22 AB9 IO184NB4F17 AB17 IO213NB4F19/CLKFN AC13 IO242NB5F22 AA9 IO184PB4F17 AC17 IO213PB4F19/CLKFP AD13 IO242PB5F22 Y9 IO185NB4F17 AD19 Bank 5 IO243NB5F22 AD5 IO185PB4F17 AD20 IO214NB5F20/CLKGN W13 IO243PB5F22 AD6 IO187PB4F17 AC18 IO214PB5F20/CLKGP Y13 IO244NB5F22 U8 IO188NB4F17 Y17 IO215NB5F20/CLKHN AC12 IO246NB5F23 AB8 IO188PB4F17 AA17 IO215PB5F20/CLKHP AD12 IO246PB5F23 AC8 IO189PB4F17 AE22 IO216NB5F20 U13 IO247NB5F23 AB7 IO191NB4F17 W18 IO216PB5F20 V13 IO247PB5F23 AC7 IO191PB4F17 V18 IO217NB5F20 AE10 IO250NB5F23 AA8 IO192PB4F17 U18 IO217PB5F20 AE11 IO250PB5F23 Y8 IO195PB4F18 AE21 IO218NB5F20 W11 IO251NB5F23 V8 IO196NB4F18 AB16 IO218PB5F20 W12 IO251PB5F23 V7 IO197NB4F18 AD17 IO222NB5F20 AA11 IO252NB5F23 Y7 IO197PB4F18 AD18 IO222PB5F20 Y11 IO252PB5F23 W7 IO198NB4F18 V17 IO223PB5F21 AE9 IO253NB5F23 AC5 IO198PB4F18 W17 IO225NB5F21 AE6 IO253PB5F23 AC6 IO199NB4F18 AE19 IO225PB5F21 AE7 IO254NB5F23 Y6 IO199PB4F18 AE20 IO226NB5F21 Y10 IO254PB5F23 W6 IO200NB4F18 AC15 IO226PB5F21 W10 IO256NB5F23 AB6 IO201NB4F18 AD15 IO227PB5F21 T13 IO256PB5F23 AA6 IO201PB4F18 AD16 IO228NB5F21 AB10 IO202NB4F18 Y15 IO228PB5F21 AB11 IO257NB6F24 Y3 IO202PB4F18 Y16 IO229NB5F21 AD9 IO257PB6F24 AA3 v5.4 Bank 6 3-41 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO258NB6F24 V3 IO288NB6F26 P5 IO321NB7F30 J2 IO258PB6F24 W3 IO290NB6F27 P6 IO321PB7F30 J1 IO259NB6F24 AA2 IO291NB6F27 P1 IO323NB7F30 L7 IO259PB6F24 AB2 IO291PB6F27 R1 IO323PB7F30 M7 IO260NB6F24 V6 IO292NB6F27 P7 IO324NB7F30 M9 IO260PB6F24 W4 IO292PB6F27 R7 IO324PB7F30 M8 IO262NB6F24 U4 IO293NB6F27 M1 IO327NB7F30 F1 IO262PB6F24 V4 IO293PB6F27 N1 IO327PB7F30 G1 IO263NB6F24 Y5 IO294NB6F27 P8 IO328NB7F30 K7 IO263PB6F24 W5 IO296NB6F27 N3 IO328PB7F30 K6 IO268NB6F25 U6 IO296PB6F27 P3 IO329NB7F30 D1 IO268PB6F25 U5 IO298NB6F27 N4 IO329PB7F30 E1 IO269PB6F25 U3 IO298PB6F27 P4 IO331PB7F30 G2 IO272NB6F25 T2 IO299NB6F27 M2 IO332NB7F31 H3 IO272PB6F25 U2 IO299PB6F27 N2 IO332PB7F31 H2 IO273NB6F25 W2 IO333NB7F31 E2 IO273PB6F25 Y2 IO300NB7F28 P9 IO333PB7F31 F2 IO274NB6F25 R6 IO300PB7F28 N6 IO334NB7F31 H4 IO274PB6F25 T6 IO302NB7F28 M6 IO334PB7F31 J4 IO275NB6F25 T7 IO304NB7F28 N8 IO335NB7F31 H5 IO275PB6F25 U7 IO304PB7F28 N7 IO335PB7F31 H6 IO277NB6F25 V2 IO308NB7F28 M4 IO337NB7F31 D2 IO278NB6F26 R4 IO309NB7F28 L3 IO338NB7F31 J6 IO278PB6F26 T4 IO309PB7F28 M3 IO338PB7F31 J5 IO279PB6F26 R3 IO310NB7F29 N10 IO339NB7F31 F3 IO280NB6F26 R5 IO310PB7F29 N9 IO339PB7F31 E3 IO281NB6F26 AA1 IO311NB7F29 K1 IO340NB7F31 G4 IO281PB6F26 AB1 IO311PB7F29 L1 IO340PB7F31 G3 IO284NB6F26 R8 IO313NB7F29 M5 IO341NB7F31 K8 IO284PB6F26 T8 IO316NB7F29 L6 IO341PB7F31 L8 IO285NB6F26 W1 IO316PB7F29 L5 Dedicated I/O IO285PB6F26 Y1 IO317NB7F29 K2 GND K5 IO286NB6F26 P2 IO317PB7F29 L2 GND A18 IO286PB6F26 R2 IO318NB7F29 K4 GND A2 IO287NB6F26 T1 IO318PB7F29 L4 GND A24 IO287PB6F26 U1 IO320NB7F29 J3 GND A25 3 -4 2 Bank 7 v5.4 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number GND A8 GND E8 GND V1 GND AA10 GND H1 GND V25 GND AA16 GND H21 GND V5 GND AA18 GND H25 NC AA12 GND AA21 GND K21 NC AA14 GND AA5 GND K23 NC E12 GND AB22 GND K3 NC E14 GND AB4 GND L11 NC F12 GND AC10 GND L12 NC F14 GND AC16 GND L13 NC H12 GND AC23 GND L14 NC H14 GND AC3 GND L15 NC J12 GND AD1 GND M11 NC J14 GND AD2 GND M12 NC U12 GND AD24 GND M13 NC U14 GND AD25 GND M14 NC V12 GND AE1 GND M15 NC V14 GND AE18 GND N11 NC Y12 GND AE2 GND N12 NC Y14 GND AE24 GND N13 PRA F13 GND AE25 GND N14 PRB A13 GND AE8 GND N15 PRC AB12 GND B1 GND P11 PRD AE13 GND B2 GND P12 TCK F5 GND B24 GND P13 TDI C5 GND B25 GND P14 TDO F6 GND C10 GND P15 TMS D6 GND C16 GND R11 TRST E6 GND C23 GND R12 VCCA AB20 GND C3 GND R13 VCCA F22 GND D22 GND R14 VCCA F4 GND D4 GND R15 VCCA J17 GND E10 GND T21 VCCA J9 GND E16 GND T23 VCCA K10 GND E21 GND T3 VCCA K11 GND E5 GND T5 VCCA K15 v5.4 3-43 RTAX-S/SL RadTolerant FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number VCCA K16 VCCIB0 A3 VCCIB5 AC4 VCCA L10 VCCIB0 B3 VCCIB5 AD3 VCCA L16 VCCIB0 C4 VCCIB5 AE3 VCCA R10 VCCIB0 D5 VCCIB5 T12 VCCA R16 VCCIB0 J10 VCCIB5 U10 VCCA T10 VCCIB0 J11 VCCIB5 U11 VCCA T11 VCCIB0 K12 VCCIB6 AA4 VCCA T15 VCCIB1 A23 VCCIB6 AB3 VCCA T16 VCCIB1 B23 VCCIB6 AC1 VCCA U17 VCCIB1 C22 VCCIB6 AC2 VCCA U9 VCCIB1 D21 VCCIB6 P10 VCCA Y4 VCCIB1 J15 VCCIB6 R9 VCCDA A12 VCCIB1 J16 VCCIB6 T9 VCCDA A14 VCCIB1 K14 VCCIB7 C1 VCCDA AA13 VCCIB2 C24 VCCIB7 C2 VCCDA AA15 VCCIB2 C25 VCCIB7 D3 VCCDA AA20 VCCIB2 D23 VCCIB7 E4 VCCDA AA7 VCCIB2 E22 VCCIB7 K9 VCCDA AB13 VCCIB2 K17 VCCIB7 L9 VCCDA AC11 VCCIB2 L17 VCCIB7 M10 VCCDA AD11 VCCIB2 M16 VPUMP E20 VCCDA AD4 VCCIB3 AA22 VCCDA AE12 VCCIB3 AB23 VCCDA AE17 VCCIB3 AC24 VCCDA B15 VCCIB3 AC25 VCCDA C15 VCCIB3 P16 VCCDA C6 VCCIB3 R17 VCCDA D13 VCCIB3 T17 VCCDA E13 VCCIB4 AB21 VCCDA E19 VCCIB4 AC22 VCCDA F21 VCCIB4 AD23 VCCDA G10 VCCIB4 AE23 VCCDA G5 VCCIB4 T14 VCCDA N21 VCCIB4 U15 VCCDA N5 VCCIB4 U16 VCCDA W21 VCCIB5 AB5 3 -4 4 v5.4 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 3-5 * 1152-Pin CCGA/LGA (Bottom View) Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. v5.4 3-45 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number Bank 0 3 -4 6 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO18NB0F1 E11 IO36PB0F3 A16 IO00NB0F0 D6 IO18PB0F1 E10 IO37NB0F3 G16 IO00PB0F0 C6 IO19NB0F1 F13 IO37PB0F3 G15 IO01NB0F0 H10 IO19PB0F1 G13 IO38NB0F3 D16 IO01PB0F0 H9 IO20NB0F1 A10 IO38PB0F3 C16 IO02NB0F0 F8 IO20PB0F1 A9 IO39NB0F3 K16 IO02PB0F0 G8 IO21NB0F1 K14 IO39PB0F3 L16 IO03NB0F0 A6 IO21PB0F1 K13 IO40NB0F3 D17 IO03PB0F0 B6 IO22NB0F2 B11 IO40PB0F3 C17 IO04NB0F0 C7 IO22PB0F2 B10 IO41NB0F3/HCLKAN E16 IO04PB0F0 D7 IO23NB0F2 C12 IO41PB0F3/HCLKAP F16 IO05NB0F0 K10 IO23PB0F2 C11 IO42NB0F3/HCLKBN G17 IO05PB0F0 J10 IO24NB0F2 A12 IO42PB0F3/HCLKBP F17 IO06NB0F0 F9 IO24PB0F2 A11 Bank 1 IO06PB0F0 G9 IO25NB0F2 H14 IO43NB1F4/HCLKCN G19 IO07NB0F0 F10 IO25PB0F2 J14 IO43PB1F4/HCLKCP G18 IO07PB0F0 G10 IO26NB0F2 D13 IO44NB1F4/HCLKDN E19 IO08NB0F0 E9 IO26PB0F2 D12 IO44PB1F4/HCLKDP F19 IO08PB0F0 E8 IO27NB0F2 F14 IO45NB1F4 C18 IO09NB0F0 J11 IO27PB0F2 G14 IO45PB1F4 D18 IO09PB0F0 K11 IO28NB0F2 E14 IO46NB1F4 A18 IO10NB0F0 C8 IO28PB0F2 E13 IO46PB1F4 B18 IO10PB0F0 D8 IO29NB0F2 B13 IO47NB1F4 K19 IO11NB0F0 K12 IO29PB0F2 B12 IO47PB1F4 L19 IO11PB0F0 J12 IO30NB0F2 C14 IO48NB1F4 C19 IO12NB0F1 G11 IO30PB0F2 C13 IO48PB1F4 D19 IO12PB0F1 H11 IO31NB0F2 H15 IO49NB1F4 K20 IO13NB0F1 G12 IO31PB0F2 J15 IO49PB1F4 L20 IO13PB0F1 H12 IO32NB0F2 A14 IO50NB1F4 A19 IO14NB0F1 A7 IO32PB0F2 B14 IO50PB1F4 B19 IO14PB0F1 B7 IO33NB0F2 K15 IO51NB1F4 H20 IO15NB0F1 H13 IO33PB0F2 L15 IO51PB1F4 J20 IO15PB0F1 J13 IO34NB0F3 D15 IO52NB1F4 B20 IO16NB0F1 C9 IO34PB0F3 D14 IO52PB1F4 A20 IO16PB0F1 D9 IO35NB0F3 A15 IO53NB1F4 F20 IO17NB0F1 F12 IO35PB0F3 B15 IO53PB1F4 E20 IO17PB0F1 F11 IO36NB0F3 B16 IO54NB1F5 B21 v5.4 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO54PB1F5 A21 IO73NB1F6 E26 IO91NB2F8 K28 IO55NB1F5 K21 IO73PB1F6 E25 IO91PB2F8 K27 IO55PB1F5 J21 IO74NB1F6 F26 IO92NB2F8 J30 IO56NB1F5 D21 IO74PB1F6 F25 IO92PB2F8 H30 IO56PB1F5 C21 IO75NB1F6 K25 IO93NB2F8 L28 IO57NB1F5 G22 IO75PB1F6 K24 IO93PB2F8 L27 IO57PB1F5 G21 IO76NB1F7 D27 IO94NB2F8 K29 IO58NB1F5 E22 IO76PB1F7 D26 IO94PB2F8 J29 IO58PB1F5 E21 IO77NB1F7 B29 IO95NB2F8 K31 IO59NB1F5 D22 IO77PB1F7 A29 IO95PB2F8 J31 IO59PB1F5 C22 IO78NB1F7 D28 IO96NB2F9 J32 IO60NB1F5 B23 IO78PB1F7 C28 IO96PB2F9 H32 IO60PB1F5 A23 IO79NB1F7 H25 IO97NB2F9 M27 IO61NB1F5 H22 IO79PB1F7 G25 IO97PB2F9 M26 IO61PB1F5 H21 IO80NB1F7 F27 IO98NB2F9 L30 IO62NB1F5 C24 IO80PB1F7 E27 IO98PB2F9 K30 IO62PB1F5 C23 IO81NB1F7 J25 IO99NB2F9 N25 IO63NB1F5 F23 IO81PB1F7 J24 IO99PB2F9 N26 IO63PB1F5 F22 IO82NB1F7 D29 IO100NB2F9 M29 IO64NB1F6 B24 IO82PB1F7 C29 IO100PB2F9 L29 IO64PB1F6 A24 IO83NB1F7 H26 IO101NB2F9 L33 IO65NB1F6 J22 IO83PB1F7 G26 IO101PB2F9 L32 IO65PB1F6 K22 IO84NB1F7 F28 IO102NB2F9 K34 IO66NB1F6 B25 IO84PB1F7 E28 IO102PB2F9 K33 IO66PB1F6 A25 IO85NB1F7 H27 IO103NB2F9 N28 IO67NB1F6 K23 IO85PB1F7 G27 IO103PB2F9 M28 IO67PB1F6 J23 IO104NB2F9 M34 IO68NB1F6 F24 IO86NB2F8 J28 IO104PB2F9 L34 IO68PB1F6 E24 IO86PB2F8 J27 IO105NB2F9 P27 IO69NB1F6 C27 IO87NB2F8 M25 IO105PB2F9 N27 IO69PB1F6 C26 IO87PB2F8 L25 IO106NB2F9 M32 IO70NB1F6 H24 IO88NB2F8 L26 IO106PB2F9 M31 IO70PB1F6 G24 IO88PB2F8 K26 IO107NB2F10 P25 IO71NB1F6 H23 IO89NB2F8 G31 IO107PB2F10 P26 IO71PB1F6 G23 IO89PB2F8 F31 IO108NB2F10 N33 IO72NB1F6 B28 IO90NB2F8 H29 IO108PB2F10 M33 IO72PB1F6 A28 IO90PB2F8 G29 IO109NB2F10 P29 Bank 2 v5.4 3-47 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 3 -4 8 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO109PB2F10 N29 IO128NB2F11 U31 IO146NB3F13 AA29 IO110NB2F10 P30 IO128PB2F11 U32 IO146PB3F13 AA30 IO110PB2F10 N30 IO147NB3F13 AB30 IO111NB2F10 R24 IO129NB3F12 V29 IO147PB3F13 AB29 IO111PB2F10 R25 IO129PB3F12 U29 IO148NB3F13 AB32 IO112NB2F10 P31 IO130NB3F12 V31 IO148PB3F13 AA32 IO112PB2F10 N31 IO130PB3F12 V32 IO149NB3F13 AB27 IO113NB2F10 R28 IO131NB3F12 V24 IO149PB3F13 AA27 IO113PB2F10 P28 IO131PB3F12 V25 IO150NB3F14 AC31 IO114NB2F10 P32 IO132NB3F12 W28 IO150PB3F14 AB31 IO114PB2F10 N32 IO132PB3F12 V28 IO151NB3F14 AD33 IO115NB2F10 R30 IO133NB3F12 W26 IO151PB3F14 AC33 IO115PB2F10 R29 IO133PB3F12 V26 IO152NB3F14 AC28 IO116NB2F10 P34 IO134NB3F12 W33 IO152PB3F14 AB28 IO116PB2F10 P33 IO134PB3F12 V33 IO153NB3F14 AB25 IO117NB2F10 R27 IO135NB3F12 W25 IO153PB3F14 AA25 IO117PB2F10 R26 IO135PB3F12 W24 IO154NB3F14 AD32 IO118NB2F11 R34 IO136NB3F12 W31 IO154PB3F14 AC32 IO118PB2F11 R33 IO136PB3F12 W32 IO155NB3F14 AD29 IO119NB2F11 T24 IO137NB3F12 Y30 IO155PB3F14 AC29 IO119PB2F11 T25 IO137PB3F12 W30 IO156NB3F14 AE30 IO120NB2F11 T33 IO138NB3F12 Y29 IO156PB3F14 AD30 IO120PB2F11 T34 IO138PB3F12 W29 IO157NB3F14 AC26 IO121NB2F11 T27 IO139NB3F13 Y27 IO157PB3F14 AB26 IO121PB2F11 T26 IO139PB3F13 W27 IO158NB3F14 AH33 IO122NB2F11 T30 IO140NB3F13 AA33 IO158PB3F14 AG33 IO122PB2F11 T29 IO140PB3F13 Y33 IO159NB3F14 AD27 IO123NB2F11 U28 IO141NB3F13 Y25 IO159PB3F14 AC27 IO123PB2F11 T28 IO141PB3F13 Y24 IO160NB3F14 AG32 IO124NB2F11 T31 IO142NB3F13 AA31 IO160PB3F14 AF32 IO124PB2F11 T32 IO142PB3F13 Y31 IO161NB3F15 AG31 IO125NB2F11 U24 IO143NB3F13 AA28 IO161PB3F15 AF31 IO125PB2F11 U25 IO143PB3F13 Y28 IO162NB3F15 AF29 IO126NB2F11 U33 IO144NB3F13 AA34 IO162PB3F15 AE29 IO126PB2F11 U34 IO144PB3F13 Y34 IO163NB3F15 AE28 IO127NB2F11 U26 IO145NB3F13 AA26 IO163PB3F15 AD28 IO127PB2F11 U27 IO145PB3F13 Y26 IO164NB3F15 AG30 Bank 3 v5.4 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO164PB3F15 AF30 IO182PB4F17 AE24 IO201NB4F18 AM21 IO165NB3F15 AE26 IO183NB4F17 AH24 IO201PB4F18 AL21 IO165PB3F15 AD26 IO183PB4F17 AH25 IO202NB4F18 AE20 IO166NB3F15 AJ30 IO184NB4F17 AG23 IO202PB4F18 AD20 IO166PB3F15 AH30 IO184PB4F17 AG24 IO203NB4F19 AN21 IO167NB3F15 AG28 IO185NB4F17 AL25 IO203PB4F19 AP21 IO167PB3F15 AF28 IO185PB4F17 AL26 IO204NB4F19 AP20 IO168NB3F15 AF27 IO186NB4F17 AP25 IO204PB4F19 AN20 IO168PB3F15 AE27 IO186PB4F17 AP26 IO205NB4F19 AN19 IO169NB3F15 AH29 IO187NB4F17 AK24 IO205PB4F19 AP19 IO169PB3F15 AG29 IO187PB4F17 AK25 IO206NB4F19 AG20 IO170NB3F15 AD25 IO188NB4F17 AF23 IO206PB4F19 AF20 IO170PB3F15 AC25 IO188PB4F17 AE23 IO207NB4F19 AL19 IO189NB4F17 AN24 IO207PB4F19 AL20 Bank 4 IO171NB4F16 AP29 IO189PB4F17 AM24 IO208NB4F19 AG19 IO171PB4F16 AN29 IO190NB4F17 AH22 IO208PB4F19 AF19 IO172NB4F16 AH26 IO190PB4F17 AH23 IO209NB4F19 AN18 IO172PB4F16 AH27 IO191NB4F17 AJ23 IO209PB4F19 AP18 IO173NB4F16 AJ27 IO191PB4F17 AJ24 IO210NB4F19 AE19 IO173PB4F16 AJ28 IO192NB4F17 AG21 IO210PB4F19 AD19 IO174NB4F16 AL27 IO192PB4F17 AG22 IO211NB4F19 AL18 IO174PB4F16 AL28 IO193NB4F18 AP23 IO211PB4F19 AM18 IO175NB4F16 AM28 IO193PB4F18 AP24 IO212NB4F19/CLKEN AJ20 IO175PB4F16 AM29 IO194NB4F18 AN22 IO212PB4F19/CLKEP AK20 IO176NB4F16 AG25 IO194PB4F18 AN23 IO213NB4F19/CLKFN AJ18 IO176PB4F16 AG26 IO195NB4F18 AM23 IO213PB4F19/CLKFP AJ19 IO177NB4F16 AK26 IO195PB4F18 AL23 Bank 5 IO177PB4F16 AK27 IO196NB4F18 AF21 IO214NB5F20/CLKGN AJ16 IO178NB4F16 AF25 IO196PB4F18 AF22 IO214PB5F20/CLKGP AJ17 IO178PB4F16 AE25 IO197NB4F18 AL22 IO215NB5F20/CLKHN AJ15 IO179NB4F16 AP28 IO197PB4F18 AM22 IO215PB5F20/CLKHP AK15 IO179PB4F16 AN28 IO198NB4F18 AE21 IO216NB5F20 AD16 IO180NB4F16 AJ25 IO198PB4F18 AE22 IO216PB5F20 AE17 IO180PB4F16 AJ26 IO199NB4F18 AJ21 IO217NB5F20 AM17 IO181NB4F17 AM26 IO199PB4F18 AJ22 IO217PB5F20 AL17 IO181PB4F17 AM27 IO200NB4F18 AK21 IO218NB5F20 AG16 IO182NB4F17 AF24 IO200PB4F18 AK22 IO218PB5F20 AF16 v5.4 3-49 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 3 -5 0 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO219NB5F20 AM16 IO237PB5F22 AJ12 IO256NB5F23 AL6 IO219PB5F20 AL16 IO238NB5F22 AH11 IO256PB5F23 AM6 IO220NB5F20 AP16 IO238PB5F22 AH12 IO220PB5F20 AN16 IO239NB5F22 AK10 IO257NB6F24 AG6 IO221NB5F20 AN15 IO239PB5F22 AK11 IO257PB6F24 AH6 IO221PB5F20 AP15 IO240NB5F22 AE12 IO258NB6F24 AD9 IO222NB5F20 AD15 IO240PB5F22 AF12 IO258PB6F24 AE9 IO222PB5F20 AE16 IO241NB5F22 AN10 IO259NB6F24 AF7 IO223NB5F21 AL14 IO241PB5F22 AP10 IO259PB6F24 AG7 IO223PB5F21 AL15 IO242NB5F22 AG11 IO260NB6F24 AH3 IO224NB5F21 AN14 IO242PB5F22 AG12 IO260PB6F24 AH4 IO224PB5F21 AP14 IO243NB5F22 AL9 IO261NB6F24 AH5 IO225NB5F21 AK13 IO243PB5F22 AL10 IO261PB6F24 AJ5 IO225PB5F21 AK14 IO244NB5F22 AM8 IO262NB6F24 AE6 IO226NB5F21 AE15 IO244PB5F22 AM9 IO262PB6F24 AF6 IO226PB5F21 AF15 IO245NB5F23 AH10 IO263NB6F24 AF5 IO227NB5F21 AG14 IO245PB5F23 AJ10 IO263PB6F24 AG5 IO227PB5F21 AG15 IO246NB5F23 AF10 IO264NB6F24 AD8 IO228NB5F21 AJ13 IO246PB5F23 AF11 IO264PB6F24 AE8 IO228PB5F21 AJ14 IO247NB5F23 AJ9 IO265NB6F24 AF3 IO229NB5F21 AM13 IO247PB5F23 AK9 IO265PB6F24 AG3 IO229PB5F21 AM14 IO248NB5F23 AN7 IO266NB6F24 AC10 IO230NB5F21 AE14 IO248PB5F23 AP7 IO266PB6F24 AD10 IO230PB5F21 AF14 IO249NB5F23 AL7 IO267NB6F25 AD7 IO231NB5F21 AN12 IO249PB5F23 AL8 IO267PB6F25 AE7 IO231PB5F21 AP12 IO250NB5F23 AE10 IO268NB6F25 AD5 IO232NB5F21 AG13 IO250PB5F23 AE11 IO268PB6F25 AE5 IO232PB5F21 AH13 IO251NB5F23 AK8 IO269NB6F25 AE4 IO233NB5F21 AL12 IO251PB5F23 AJ8 IO269PB6F25 AF4 IO233PB5F21 AL13 IO252NB5F23 AH8 IO270NB6F25 AB9 IO234NB5F21 AE13 IO252PB5F23 AH9 IO270PB6F25 AC9 IO234PB5F21 AF13 IO253NB5F23 AN6 IO271NB6F25 AC6 IO235NB5F22 AN11 IO253PB5F23 AP6 IO271PB6F25 AD6 IO235PB5F22 AP11 IO254NB5F23 AG9 IO272NB6F25 AB8 IO236NB5F22 AM11 IO254PB5F23 AG10 IO272PB6F25 AC8 IO236PB5F22 AM12 IO255NB5F23 AJ7 IO273NB6F25 AE1 IO237NB5F22 AJ11 IO255PB5F23 AK7 IO273PB6F25 AE2 v5.4 Bank 6 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO274NB6F25 AA10 IO292PB6F27 W7 IO310PB7F29 T8 IO274PB6F25 AB10 IO293NB6F27 W4 IO311NB7F29 N3 IO275NB6F25 AB7 IO293PB6F27 Y4 IO311PB7F29 P3 IO275PB6F25 AC7 IO294NB6F27 V10 IO312NB7F29 P7 IO276NB6F25 AD1 IO294PB6F27 V11 IO312PB7F29 R7 IO276PB6F25 AD2 IO295NB6F27 Y1 IO313NB7F29 P6 IO277NB6F25 AC4 IO295PB6F27 Y2 IO313PB7F29 R6 IO277PB6F25 AC3 IO296NB6F27 W1 IO314NB7F29 M2 IO278NB6F26 AA8 IO296PB6F27 W2 IO314PB7F29 N2 IO278PB6F26 AA9 IO297NB6F27 V1 IO315NB7F29 N4 IO279NB6F26 AB5 IO297PB6F27 V2 IO315PB7F29 P4 IO279PB6F26 AB6 IO298NB6F27 V9 IO316NB7F29 R9 IO280NB6F26 Y10 IO298PB6F27 V8 IO316PB7F29 R8 IO280PB6F26 Y11 IO299NB6F27 U4 IO317NB7F29 N5 IO281NB6F26 AB3 IO299PB6F27 V4 IO317PB7F29 P5 IO281PB6F26 AB4 IO318NB7F29 R10 IO282NB6F26 Y7 IO300NB7F28 U10 IO318PB7F29 R11 IO282PB6F26 AA7 IO300PB7F28 U11 IO319NB7F29 L2 IO283NB6F26 AC2 IO301NB7F28 U2 IO319PB7F29 L1 IO283PB6F26 AC1 IO301PB7F28 U1 IO320NB7F29 N8 IO284NB6F26 Y9 IO302NB7F28 U6 IO320PB7F29 P8 IO284PB6F26 Y8 IO302PB7F28 U7 IO321NB7F30 M6 IO285NB6F26 AA5 IO303NB7F28 T3 IO321PB7F30 N6 IO285PB6F26 AA6 IO303PB7F28 U3 IO322NB7F30 P10 IO286NB6F26 W10 IO304NB7F28 U9 IO322PB7F30 P9 IO286PB6F26 W11 IO304PB7F28 U8 IO323NB7F30 L3 IO287NB6F26 AA3 IO305NB7F28 R2 IO323PB7F30 M3 IO287PB6F26 AA4 IO305PB7F28 R1 IO324NB7F30 M7 IO288NB6F26 W9 IO306NB7F28 R4 IO324PB7F30 N7 IO288PB6F26 W8 IO306PB7F28 T4 IO325NB7F30 K2 IO289NB6F27 AA1 IO307NB7F28 R5 IO325PB7F30 K1 IO289PB6F27 AA2 IO307PB7F28 T5 IO326NB7F30 G2 IO290NB6F27 W6 IO308NB7F28 T11 IO326PB7F30 H2 IO290PB6F27 Y6 IO308PB7F28 T10 IO327NB7F30 L6 IO291NB6F27 W5 IO309NB7F28 T6 IO327PB7F30 L5 IO291PB6F27 Y5 IO309PB7F28 T7 IO328NB7F30 N10 IO292NB6F27 V7 IO310NB7F29 T9 IO328PB7F30 N9 Bank 7 v5.4 3-51 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number IO329NB7F30 J4 GND AA14 GND AK5 IO329PB7F30 K4 GND AA15 GND AL1 IO330NB7F30 J5 GND AA16 GND AL11 IO330PB7F30 K5 GND AA17 GND AL2 IO331NB7F30 M10 GND AA18 GND AL24 IO331PB7F30 M9 GND AA19 GND AL3 IO332NB7F31 L8 GND AA20 GND AL31 IO332PB7F31 M8 GND AA21 GND AL32 IO333NB7F31 F2 GND AB1 GND AL33 IO333PB7F31 F1 GND AB13 GND AL34 IO334NB7F31 J6 GND AB22 GND AL4 IO334PB7F31 K6 GND AB34 GND AM1 IO335NB7F31 H4 GND AC12 GND AM10 IO335PB7F31 H3 GND AC23 GND AM15 IO336NB7F31 K7 GND AC30 GND AM2 IO336PB7F31 L7 GND AC5 GND AM20 IO337NB7F31 G4 GND AD11 GND AM25 IO337PB7F31 G3 GND AD24 GND AM3 IO338NB7F31 K9 GND AD31 GND AM31 IO338PB7F31 L9 GND AD4 GND AM32 IO339NB7F31 H6 GND AE3 GND AM33 IO339PB7F31 H5 GND AE32 GND AM34 IO340NB7F31 H7 GND AF2 GND AM4 IO340PB7F31 J7 GND AF33 GND AN1 IO341NB7F31 J8 GND AG1 GND AN2 IO341PB7F31 K8 GND AG27 GND AN26 GND AG34 GND AN3 Dedicated I/O 3 -5 2 1152-Pin CCGA/LGA GND A13 GND AG8 GND AN31 GND A2 GND AH28 GND AN32 GND A22 GND AH7 GND AN33 GND A27 GND AJ29 GND AN34 GND A3 GND AJ6 GND AN4 GND A31 GND AK12 GND AN9 GND A32 GND AK17 GND AP13 GND A33 GND AK18 GND AP2 GND A4 GND AK23 GND AP22 GND A8 GND AK30 GND AP27 v5.4 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number GND AP3 GND D4 GND P20 GND AP31 GND E12 GND P21 GND AP32 GND E17 GND R14 GND AP33 GND E18 GND R15 GND AP4 GND E23 GND R16 GND AP8 GND E30 GND R17 GND B1 GND E5 GND R18 GND B2 GND F29 GND R19 GND B26 GND F30 GND R20 GND B3 GND F6 GND R21 GND B31 GND G28 GND R3 GND B32 GND G6 GND R32 GND B33 GND G7 GND T14 GND B34 GND H1 GND T15 GND B4 GND H34 GND T16 GND B9 GND J2 GND T17 GND C1 GND J33 GND T18 GND C10 GND K3 GND T19 GND C15 GND K32 GND T20 GND C2 GND L11 GND T21 GND C20 GND L24 GND U14 GND C25 GND L31 GND U15 GND C3 GND L4 GND U16 GND C31 GND M12 GND U17 GND C32 GND M23 GND U18 GND C33 GND M30 GND U19 GND C34 GND M5 GND U20 GND C4 GND N1 GND U21 GND D1 GND N13 GND U30 GND D11 GND N22 GND U5 GND D2 GND N34 GND V14 GND D24 GND P14 GND V15 GND D3 GND P15 GND V16 GND D31 GND P16 GND V17 GND D32 GND P17 GND V18 GND D33 GND P18 GND V19 GND D34 GND P19 GND V20 v5.4 3-53 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 3 -5 4 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number GND V21 NC AG2 NC F3 GND V30 NC AG4 NC F32 GND V5 NC AH1 NC F33 GND W14 NC AH16 NC F34 GND W15 NC AH19 NC F4 GND W16 NC AH2 NC G1 GND W17 NC AH31 NC G32 GND W18 NC AH32 NC G33 GND W19 NC AH34 NC G34 GND W20 NC AJ1 NC H16 GND W21 NC AJ2 NC H19 GND Y14 NC AJ3 NC H31 GND Y15 NC AJ31 NC H33 GND Y16 NC AJ32 NC J1 GND Y17 NC AJ33 NC J16 GND Y18 NC AJ34 NC J19 GND Y19 NC AJ4 NC J3 GND Y20 NC AK16 NC J34 GND Y21 NC AK19 NC K17 GND Y3 NC AL29 NC K18 GND Y32 NC AM19 NC L17 NC A17 NC AM7 NC L18 NC A26 NC AN13 NC M1 NC AB2 NC AN17 NC M4 NC AB33 NC AN25 NC P1 NC AC34 NC AN27 NC P2 NC AD17 NC AN8 NC R31 NC AD3 NC AP17 NC T1 NC AD34 NC AP9 NC T2 NC AE18 NC B17 NC V3 NC AE31 NC B22 NC V34 NC AE33 NC B27 NC W3 NC AE34 NC B8 NC W34 NC AF1 NC D10 PRA J17 NC AF17 NC D20 PRB F18 NC AF18 NC D23 PRC AD18 NC AF34 NC D25 PRD AH18 v5.4 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number TCK J9 VCCA W13 VCCIB0 M15 TDI F7 VCCA W22 VCCIB0 M16 TDO L10 VCCA Y13 VCCIB0 M17 TMS H8 VCCA Y22 VCCIB1 A30 TRST E6 VCCDA AF26 VCCIB1 B30 VCCA AA13 VCCDA AF9 VCCIB1 C30 VCCA AA22 VCCDA AG17 VCCIB1 D30 VCCA AB14 VCCDA AG18 VCCIB1 L21 VCCA AB15 VCCDA AH14 VCCIB1 L22 VCCA AB16 VCCDA AH15 VCCIB1 L23 VCCA AB17 VCCDA AH17 VCCIB1 M18 VCCA AB18 VCCDA AH20 VCCIB1 M19 VCCA AB19 VCCDA AH21 VCCIB1 M20 VCCA AB20 VCCDA AK29 VCCIB1 M21 VCCA AB21 VCCDA AK6 VCCIB1 M22 VCCA AF8 VCCDA E15 VCCIB2 E31 VCCA AK28 VCCDA E29 VCCIB2 E32 VCCA G30 VCCDA E7 VCCIB2 E33 VCCA G5 VCCDA F15 VCCIB2 E34 VCCA N14 VCCDA F21 VCCIB2 M24 VCCA N15 VCCDA F5 VCCIB2 N23 VCCA N16 VCCDA G20 VCCIB2 N24 VCCA N17 VCCDA H17 VCCIB2 P23 VCCA N18 VCCDA H18 VCCIB2 P24 VCCA N19 VCCDA H28 VCCIB2 R23 VCCA N20 VCCDA J18 VCCIB2 T23 VCCA N21 VCCDA V27 VCCIB2 U23 VCCA P13 VCCDA V6 VCCIB3 AA23 VCCA P22 VCCIB0 A5 VCCIB3 AA24 VCCA R13 VCCIB0 B5 VCCIB3 AB23 VCCA R22 VCCIB0 C5 VCCIB3 AB24 VCCA T13 VCCIB0 D5 VCCIB3 AC24 VCCA T22 VCCIB0 L12 VCCIB3 AK31 VCCA U13 VCCIB0 L13 VCCIB3 AK32 VCCA U22 VCCIB0 L14 VCCIB3 AK33 VCCA V13 VCCIB0 M13 VCCIB3 AK34 VCCA V22 VCCIB0 M14 VCCIB3 V23 v5.4 3-55 RTAX-S/SL RadTolerant FPGAs 1152-Pin CCGA/LGA 3 -5 6 1152-Pin CCGA/LGA 1152-Pin CCGA/LGA RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number RTAX2000S/SL Function Pin Number VCCIB3 W23 VCCIB5 AC16 VCCIB6 AK4 VCCIB3 Y23 VCCIB5 AC17 VCCIB6 V12 VCCIB4 AC18 VCCIB5 AD12 VCCIB6 W12 VCCIB4 AC19 VCCIB5 AD13 VCCIB6 Y12 VCCIB4 AC20 VCCIB5 AD14 VCCIB7 E1 VCCIB4 AC21 VCCIB5 AL5 VCCIB7 E2 VCCIB4 AC22 VCCIB5 AM5 VCCIB7 E3 VCCIB4 AD21 VCCIB5 AN5 VCCIB7 E4 VCCIB4 AD22 VCCIB5 AP5 VCCIB7 M11 VCCIB4 AD23 VCCIB6 AA11 VCCIB7 N11 VCCIB4 AL30 VCCIB6 AA12 VCCIB7 N12 VCCIB4 AM30 VCCIB6 AB11 VCCIB7 P11 VCCIB4 AN30 VCCIB6 AB12 VCCIB7 P12 VCCIB4 AP30 VCCIB6 AC11 VCCIB7 R12 VCCIB5 AC13 VCCIB6 AK1 VCCIB7 T12 VCCIB5 AC14 VCCIB6 AK2 VCCIB7 U12 VCCIB5 AC15 VCCIB6 AK3 VPUMP J26 v5.4 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 3-6 * 1272-Pin CCGA/LGA (Bottom View) Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.actel.com/products/solutions/package/docs.aspx. v5.4 3-57 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number Bank 0 3 -5 8 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO18NB0F1 K13 IO36PB0F3 J15 IO00NB0F0 E9 IO18PB0F1 K12 IO37NB0F3 A11 IO00PB0F0 D9 IO19NB0F1 B4 IO37PB0F3 A10 IO01NB0F0 D8 IO19PB0F1 C4 IO38NB0F3 H15 IO01PB0F0 D7 IO20NB0F1 H13 IO38PB0F3 H14 IO02NB0F0 J10 IO20PB0F1 H12 IO39NB0F3 B16 IO02PB0F0 J9 IO21NB0F2 C13 IO39PB0F3 B15 IO03NB0F0 E7 IO21PB0F2 C12 IO40NB0F3 M16 IO03PB0F0 E8 IO22NB0F2 M14 IO40PB0F3 M17 IO04NB0F0 F9 IO22PB0F2 M13 IO41NB0F3 E16 IO04PB0F0 G9 IO23NB0F2 B10 IO41PB0F3 F16 IO05NB0F0 B7 IO23PB0F2 B9 IO42NB0F4 H17 IO05PB0F0 B6 IO24NB0F2 J14 IO42PB0F4 J17 IO06NB0F0 L13 IO24PB0F2 J13 IO43NB0F4 A14 IO06PB0F0 L12 IO25NB0F2 A8 IO43PB0F4 A15 IO07NB0F0 C7 IO25PB0F2 A9 IO44NB0F4 G16 IO07PB0F0 C6 IO26NB0F2 G13 IO44PB0F4 H16 IO08NB0F0 F10 IO26PB0F2 F13 IO45NB0F4 A17 IO08PB0F0 G10 IO27NB0F2 D14 IO45PB0F4 A16 IO09NB0F0 D10 IO27PB0F2 D13 IO46NB0F4 M18 IO09PB0F0 E10 IO28NB0F2 L16 IO46PB0F4 M19 IO10NB0F0 H11 IO28PB0F2 L15 IO47NB0F4 E18 IO10PB0F0 H10 IO29NB0F2 B13 IO47PB0F4 E17 IO11NB0F0 A5 IO29PB0F2 B12 IO48NB0F4 G18 IO11PB0F0 A4 IO30NB0F2 C10 IO48PB0F4 H18 IO12NB0F1 D6 IO30PB0F2 C9 IO49NB0F4 C18 IO12PB0F1 D5 IO31NB0F2 E15 IO49PB0F4 B18 IO13NB0F1 A7 IO31PB0F2 E14 IO50NB0F4/HCLKAN J18 IO13PB0F1 A6 IO32NB0F2 K15 IO50PB0F4/HCLKAP K18 IO14NB0F1 J12 IO32PB0F2 K16 IO51NB0F4/HCLKBN D18 IO14PB0F1 J11 IO33NB0F3 A13 IO51PB0F4/HCLKBP D17 IO15NB0F1 D12 IO33PB0F3 A12 Bank 1 IO15PB0F1 D11 IO34NB0F3 G15 IO52NB1F6/HCLKCN K19 IO16NB0F1 F12 IO34PB0F3 F15 IO52PB1F6/HCLKCP J19 IO16PB0F1 G12 IO35NB0F3 C15 IO53NB1F6/HCLKDN D20 IO17NB0F1 E12 IO35PB0F3 D15 IO53PB1F6/HCLKDP D19 IO17PB0F1 E11 IO36NB0F3 J16 IO54NB1F6 H19 v5.4 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO54PB1F6 G19 IO73NB1F8 A25 IO91PB1F9 A30 IO55NB1F6 B19 IO73PB1F8 A24 IO92NB1F9 H27 IO55PB1F6 C19 IO74NB1F8 C28 IO92PB1F9 H26 IO56NB1F6 M20 IO74PB1F8 C27 IO93NB1F9 C33 IO56PB1F6 M21 IO75NB1F8 D24 IO93PB1F9 B33 IO57NB1F6 E20 IO75PB1F8 D23 IO94NB1F10 G27 IO57PB1F6 E19 IO76NB1F8 J24 IO94PB1F10 F27 IO58NB1F6 H21 IO76PB1F8 J23 IO95NB1F10 E27 IO58PB1F6 G21 IO77NB1F8 B25 IO95PB1F10 D27 IO59NB1F6 A21 IO77PB1F8 B24 IO96NB1F10 L24 IO59PB1F6 A20 IO78NB1F8 F24 IO96PB1F10 L25 IO60NB1F7 H20 IO78PB1F8 G24 IO97NB1F10 C31 IO60PB1F7 J20 IO79NB1F8 A28 IO97PB1F10 C30 IO61NB1F7 A22 IO79PB1F8 A29 IO98NB1F10 F28 IO61PB1F7 A23 IO80NB1F8 M24 IO98PB1F10 G28 IO62NB1F7 D32 IO80PB1F8 M23 IO99NB1F10 B31 IO62PB1F7 D31 IO81NB1F8 B28 IO99PB1F10 B30 IO63NB1F7 F21 IO81PB1F8 B27 IO100NB1F10 J28 IO63PB1F7 E21 IO82NB1F9 H25 IO100PB1F10 J27 IO64NB1F7 J22 IO82PB1F9 H24 IO101NB1F10 E29 IO64PB1F7 J21 IO83NB1F9 C25 IO101PB1F10 E30 IO65NB1F7 B22 IO83PB1F9 C24 IO102NB1F10 D28 IO65PB1F7 B21 IO84NB1F9 K25 IO102PB1F10 E28 IO66NB1F7 H23 IO84PB1F9 K24 IO103NB1F10 D30 IO66PB1F7 H22 IO85NB1F9 A33 IO103PB1F10 D29 IO67NB1F7 D22 IO85PB1F9 A32 IO67PB1F7 C22 IO86NB1F9 G25 IO104NB2F12 L29 IO68NB1F7 K22 IO86PB1F9 F25 IO104PB2F12 L28 IO68PB1F7 K21 IO87NB1F9 E26 IO105NB2F12 D35 IO69NB1F7 A27 IO87PB1F9 E25 IO105PB2F12 D34 IO69PB1F7 A26 IO88NB1F9 J26 IO106NB2F12 H33 IO70NB1F7 F22 IO88PB1F9 J25 IO106PB2F12 J33 IO70PB1F7 G22 IO89NB1F9 D26 IO107NB2F12 F34 IO71NB1F7 E23 IO89PB1F9 D25 IO107PB2F12 F33 IO71PB1F7 E22 IO90NB1F9 E31 IO108NB2F12 G33 IO72NB1F8 L22 IO90PB1F9 E32 IO108PB2F12 G32 IO72PB1F8 L21 IO91NB1F9 A31 IO109NB2F12 M28 v5.4 Bank 2 3-59 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 3 -6 0 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO109PB2F12 M27 IO128NB2F14 N34 IO146PB2F16 R32 IO110NB2F12 K33 IO128PB2F14 M34 IO147NB2F16 V25 IO110PB2F12 K32 IO129NB2F14 P29 IO147PB2F16 U25 IO111NB2F12 K31 IO129PB2F14 P28 IO148NB2F17 T36 IO111PB2F12 K30 IO130NB2F15 N33 IO148PB2F17 R36 IO112NB2F13 K34 IO130PB2F15 M33 IO149NB2F17 U29 IO112PB2F13 J34 IO131NB2F15 R26 IO149PB2F17 U28 IO113NB2F13 N26 IO131PB2F15 R25 IO150NB2F17 U33 IO113PB2F13 M26 IO132NB2F15 K36 IO150PB2F17 T33 IO114NB2F13 K28 IO132PB2F15 J36 IO151NB2F17 W25 IO114PB2F13 K29 IO133NB2F15 R29 IO151PB2F17 Y25 IO115NB2F13 H32 IO133PB2F15 R28 IO152NB2F17 V36 IO115PB2F13 J32 IO134NB2F15 N35 IO152PB2F17 U36 IO116NB2F13 G35 IO134PB2F15 M35 IO153NB2F17 V31 IO116PB2F13 G34 IO135NB2F15 F35 IO153PB2F17 V30 IO117NB2F13 M29 IO135PB2F15 F36 IO154NB2F17 V32 IO117PB2F13 M30 IO136NB2F15 M36 IO154PB2F17 U32 IO118NB2F13 E33 IO136PB2F15 L36 IO155NB2F17 V27 IO118PB2F13 D33 IO137NB2F15 T26 IO155PB2F17 V28 IO119NB2F13 M32 IO137PB2F15 T25 IO156NB2F17 W34 IO119PB2F13 M31 IO138NB2F15 P33 IO156PB2F17 V34 IO120NB2F13 E36 IO138PB2F15 P32 IO120PB2F13 D36 IO139NB2F16 R31 IO157NB3F18 W29 IO121NB2F14 N28 IO139PB2F16 R30 IO157PB3F18 V29 IO121PB2F14 N27 IO140NB2F16 P36 IO158NB3F18 W35 IO122NB2F14 L33 IO140PB2F16 N36 IO158PB3F18 V35 IO122PB2F14 L32 IO141NB2F16 T28 IO159NB3F18 W30 IO123NB2F14 N30 IO141PB2F16 T27 IO159PB3F18 W31 IO123PB2F14 N29 IO142NB2F16 R35 IO160NB3F18 AA36 IO124NB2F14 K35 IO142PB2F16 R34 IO160PB3F18 Y36 IO124PB2F14 J35 IO143NB2F16 T32 IO161NB3F18 W27 IO125NB2F14 P25 IO143PB2F16 T31 IO161PB3F18 W28 IO125PB2F14 N25 IO144NB2F16 T35 IO162NB3F18 Y32 IO126NB2F14 H36 IO144PB2F16 T34 IO162PB3F18 W32 IO126PB2F14 G36 IO145NB2F16 T30 IO163NB3F18 Y28 IO127NB2F14 N32 IO145PB2F16 T29 IO163PB3F18 Y29 IO127PB2F14 N31 IO146NB2F16 R33 IO164NB3F18 AC36 v5.4 Bank 3 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO164PB3F18 AB36 IO183NB3F20 AC29 IO201PB3F22 AF28 IO165NB3F18 AA26 IO183PB3F20 AC28 IO202NB3F23 AG32 IO165PB3F18 AA25 IO184NB3F21 AE34 IO202PB3F23 AG33 IO166NB3F19 AA33 IO184PB3F21 AD34 IO203NB3F23 AG31 IO166PB3F19 Y33 IO185NB3F21 AE26 IO203PB3F23 AG30 IO167NB3F19 AA32 IO185PB3F21 AD26 IO204NB3F23 AL33 IO167PB3F19 AA31 IO186NB3F21 AE33 IO204PB3F23 AK33 IO168NB3F19 AA34 IO186PB3F21 AD33 IO205NB3F23 AK32 IO168PB3F19 AA35 IO187NB3F21 AD30 IO205PB3F23 AK31 IO169NB3F19 AA29 IO187PB3F21 AD29 IO206NB3F23 AH33 IO169PB3F19 AA30 IO188NB3F21 AH35 IO206PB3F23 AJ33 IO170NB3F19 AB32 IO188PB3F21 AG35 IO207NB3F23 AN34 IO170PB3F19 AB33 IO189NB3F21 AD32 IO207PB3F23 AN35 IO171NB3F19 AB31 IO189PB3F21 AD31 IO208NB3F23 AG29 IO171PB3F19 AB30 IO190NB3F21 AK35 IO208PB3F23 AG28 IO172NB3F19 AE36 IO190PB3F21 AK36 IO209NB3F23 AJ32 IO172PB3F19 AD36 IO191NB3F21 AE32 IO209PB3F23 AH32 IO173NB3F19 AA27 IO191PB3F21 AE31 IO173PB3F19 AA28 IO192NB3F21 AN36 IO210NB4F24 AM28 IO174NB3F19 AB34 IO192PB3F21 AM36 IO210PB4F24 AN28 IO174PB3F19 AB35 IO193NB3F22 AD27 IO211NB4F24 AN29 IO175NB3F20 AL35 IO193PB3F22 AD28 IO211PB4F24 AN30 IO175PB3F20 AL36 IO194NB3F22 AF32 IO212NB4F24 AH27 IO176NB3F20 AG36 IO194PB3F22 AF33 IO212PB4F24 AH28 IO176PB3F20 AF36 IO195NB3F22 AE30 IO213NB4F24 AM30 IO177NB3F20 AB25 IO195PB3F22 AE29 IO213PB4F24 AM29 IO177PB3F20 AB26 IO196NB3F22 AK34 IO214NB4F24 AL28 IO178NB3F20 AC32 IO196PB3F22 AL34 IO214PB4F24 AK28 IO178PB3F20 AC33 IO197NB3F22 AE28 IO215NB4F24 AR30 IO179NB3F20 AB29 IO197PB3F22 AE27 IO215PB4F24 AR31 IO179PB3F20 AB28 IO198NB3F22 AN33 IO216NB4F24 AF24 IO180NB3F20 AJ36 IO198PB3F22 AM33 IO216PB4F24 AF25 IO180PB3F20 AH36 IO199NB3F22 AH31 IO217NB4F24 AP30 IO181NB3F20 AC25 IO199PB3F22 AH30 IO217PB4F24 AP31 IO181PB3F20 AD25 IO200NB3F22 AH34 IO218NB4F24 AL27 IO182NB3F20 AE35 IO200PB3F22 AG34 IO218PB4F24 AK27 IO182PB3F20 AD35 IO201NB3F22 AF29 IO219NB4F24 AN27 v5.4 Bank 4 3-61 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 3 -6 2 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO219PB4F24 AM27 IO238NB4F26 AF21 IO256PB4F28 AE19 IO220NB4F25 AJ26 IO238PB4F26 AF22 IO257NB4F28 AM19 IO220PB4F25 AJ27 IO239NB4F26 AP24 IO257PB4F28 AM20 IO221NB4F25 AT32 IO239PB4F26 AP25 IO258NB4F28 AK19 IO221PB4F25 AT33 IO240NB4F26 AP27 IO258PB4F28 AJ19 IO222NB4F25 AN31 IO240PB4F26 AP28 IO259NB4F28 AP19 IO222PB4F25 AN32 IO241NB4F26 AN23 IO259PB4F28 AR19 IO223NB4F25 AT30 IO241PB4F26 AN24 IO260NB4F28/CLKEN AH19 IO223PB4F25 AT31 IO242NB4F27 AG21 IO260PB4F28/CLKEP AG19 IO224NB4F25 AH25 IO242PB4F27 AG22 IO261NB4F28/CLKFN AN19 IO224PB4F25 AH26 IO243NB4F27 AM22 IO261PB4F28/CLKFP AN20 IO225NB4F25 AN25 IO243PB4F27 AM23 Bank 5 IO225PB4F25 AN26 IO244NB4F27 AK22 IO262NB5F30/CLKGN AG18 IO226NB4F25 AL25 IO244PB4F27 AL22 IO262PB5F30/CLKGP AH18 IO226PB4F25 AK25 IO245NB4F27 AT24 IO263NB5F30/CLKHN AN17 IO227NB4F25 AM25 IO245PB4F27 AT25 IO263PB5F30/CLKHP AN18 IO227PB4F25 AM26 IO246NB4F27 AH21 IO264NB5F30 AJ18 IO228NB4F25 AG25 IO246PB4F27 AH22 IO264PB5F30 AK18 IO228PB4F25 AG24 IO247NB4F27 AP22 IO265NB5F30 AR18 IO229NB4F25 AR33 IO247PB4F27 AN22 IO265PB5F30 AP18 IO229PB4F25 AP33 IO248NB4F27 AJ22 IO266NB5F30 AE17 IO230NB4F25 AJ24 IO248PB4F27 AJ23 IO266PB5F30 AE16 IO230PB4F25 AJ25 IO249NB4F27 AR21 IO267NB5F30 AM17 IO231NB4F25 AT26 IO249PB4F27 AR22 IO267PB5F30 AM18 IO231PB4F25 AT27 IO250NB4F27 AE21 IO268NB5F30 AJ16 IO232NB4F26 AE23 IO250PB4F27 AE20 IO268PB5F30 AK16 IO232PB4F26 AE24 IO251NB4F27 AM21 IO269NB5F30 AT16 IO233NB4F26 AR27 IO251PB4F27 AL21 IO269PB5F30 AT17 IO233PB4F26 AR28 IO252NB4F27 AH20 IO270NB5F30 AF16 IO234NB4F26 AH23 IO252PB4F27 AJ20 IO270PB5F30 AF15 IO234PB4F26 AH24 IO253NB4F27 AT23 IO271NB5F30 AT15 IO235NB4F26 AT29 IO253PB4F27 AT22 IO271PB5F30 AT14 IO235PB4F26 AT28 IO254NB4F28 AK21 IO272NB5F31 AH17 IO236NB4F26 AK24 IO254PB4F28 AJ21 IO272PB5F31 AJ17 IO236PB4F26 AL24 IO255NB4F28 AT20 IO273NB5F31 AL16 IO237NB4F26 AR24 IO255PB4F28 AT21 IO273PB5F31 AM16 IO237PB4F26 AR25 IO256NB4F28 AE18 IO274NB5F31 AH15 v5.4 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO274PB5F31 AH16 IO293NB5F33 AP12 IO311PB5F34 AM7 IO275NB5F31 AR15 IO293PB5F33 AP13 IO312NB5F34 AG9 IO275PB5F31 AR16 IO294NB5F33 AG13 IO312PB5F34 AG8 IO276NB5F31 AJ14 IO294PB5F33 AF13 IO313NB5F34 AN7 IO276PB5F31 AJ15 IO295NB5F33 AP4 IO313PB5F34 AN8 IO277NB5F31 AN15 IO295PB5F33 AR4 IO277PB5F31 AP15 IO296NB5F33 AG12 IO314NB6F36 AF8 IO278NB5F31 AG15 IO296PB5F33 AF12 IO314PB6F36 AF9 IO278PB5F31 AG16 IO297NB5F33 AM11 IO315NB6F36 AN2 IO279NB5F31 AT10 IO297PB5F33 AM12 IO315PB6F36 AN3 IO279PB5F31 AT11 IO298NB5F33 AK12 IO316NB6F36 AH4 IO280NB5F31 AL15 IO298PB5F33 AL12 IO316PB6F36 AJ4 IO280PB5F31 AK15 IO299NB5F33 AN11 IO317NB6F36 AL3 IO281NB5F32 AM14 IO299PB5F33 AN12 IO317PB6F36 AL4 IO281PB5F32 AM15 IO300NB5F33 AN5 IO318NB6F36 AK4 IO282NB5F32 AE13 IO300PB5F33 AN6 IO318PB6F36 AK5 IO282PB5F32 AE14 IO301NB5F33 AT6 IO319NB6F36 AE10 IO283NB5F32 AT12 IO301PB5F33 AT7 IO319PB6F36 AE9 IO283PB5F32 AT13 IO302NB5F34 AH11 IO320NB6F36 AG4 IO284NB5F32 AP9 IO302PB5F34 AH12 IO320PB6F36 AG5 IO284PB5F32 AP10 IO303NB5F34 AT4 IO321NB6F36 AE11 IO285NB5F32 AN13 IO303PB5F34 AT5 IO321PB6F36 AD11 IO285PB5F32 AN14 IO304NB5F34 AJ10 IO322NB6F37 AG3 IO286NB5F32 AN9 IO304PB5F34 AJ11 IO322PB6F37 AH3 IO286PB5F32 AM9 IO305NB5F34 AM10 IO323NB6F37 AG7 IO287NB5F32 AR12 IO305PB5F34 AN10 IO323PB6F37 AG6 IO287PB5F32 AR13 IO306NB5F34 AK10 IO324NB6F37 AH7 IO288NB5F32 AL13 IO306PB5F34 AL10 IO324PB6F37 AH6 IO288PB5F32 AK13 IO307NB5F34 AP6 IO325NB6F37 AJ5 IO289NB5F32 AT9 IO307PB5F34 AP7 IO325PB6F37 AH5 IO289PB5F32 AT8 IO308NB5F34 AK9 IO326NB6F37 AK2 IO290NB5F32 AH13 IO308PB5F34 AL9 IO326PB6F37 AK3 IO290PB5F32 AH14 IO309NB5F34 AR6 IO327NB6F37 AE7 IO291NB5F32 AR9 IO309PB5F34 AR7 IO327PB6F37 AE8 IO291PB5F32 AR10 IO310NB5F34 AH9 IO328NB6F37 AM4 IO292NB5F32 AJ12 IO310PB5F34 AH10 IO328PB6F37 AN4 IO292PB5F32 AJ13 IO311NB5F34 AM8 IO329NB6F37 AD9 v5.4 Bank 6 3-63 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 3 -6 4 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO329PB6F37 AD10 IO348NB6F39 AC4 IO366PB6F41 W2 IO330NB6F37 AM1 IO348PB6F39 AC5 IO330PB6F37 AN1 IO349NB6F40 AB6 IO367NB7F42 V8 IO331NB6F38 AE5 IO349PB6F40 AB7 IO367PB7F42 W8 IO331PB6F38 AE6 IO350NB6F40 AC1 IO368NB7F42 V3 IO332NB6F38 AF4 IO350PB6F40 AD1 IO368PB7F42 W3 IO332PB6F38 AF5 IO351NB6F40 AA9 IO369NB7F42 V9 IO333NB6F38 AD8 IO351PB6F40 AA10 IO369PB7F42 V10 IO333PB6F38 AD7 IO352NB6F40 AB2 IO370NB7F42 U1 IO334NB6F38 AG2 IO352PB6F40 AB3 IO370PB7F42 V1 IO334PB6F38 AH2 IO353NB6F40 AA7 IO371NB7F42 V7 IO335NB6F38 AC12 IO353PB6F40 AA8 IO371PB7F42 V6 IO335PB6F38 AD12 IO354NB6F40 AA2 IO372NB7F42 U5 IO336NB6F38 AJ1 IO354PB6F40 AA3 IO372PB7F42 V5 IO336PB6F38 AK1 IO355NB6F40 AA5 IO373NB7F42 U9 IO337NB6F38 AC8 IO355PB6F40 AA6 IO373PB7F42 U8 IO337PB6F38 AC9 IO356NB6F40 AB4 IO374NB7F42 R1 IO338NB6F38 AD3 IO356PB6F40 AB5 IO374PB7F42 T1 IO338PB6F38 AE3 IO357NB6F40 W12 IO375NB7F42 T11 IO339NB6F38 AD5 IO357PB6F40 Y12 IO375PB7F42 T12 IO339PB6F38 AD6 IO358NB6F41 AA1 IO376NB7F43 T4 IO340NB6F39 AD4 IO358PB6F41 AB1 IO376PB7F43 U4 IO340PB6F39 AE4 IO359NB6F41 Y8 IO377NB7F43 T8 IO341NB6F39 AB8 IO359PB6F41 Y9 IO377PB7F43 T7 IO341PB6F39 AB9 IO360NB6F41 Y4 IO378NB7F43 T3 IO342NB6F39 AG1 IO360PB6F41 AA4 IO378PB7F43 T2 IO342PB6F39 AH1 IO361NB6F41 U12 IO379NB7F43 T5 IO343NB6F39 AA12 IO361PB6F41 V12 IO379PB7F43 T6 IO343PB6F39 AB12 IO362NB6F41 W1 IO380NB7F43 R5 IO344NB6F39 AD2 IO362PB6F41 Y1 IO380PB7F43 R4 IO344PB6F39 AE2 IO363NB6F41 W6 IO381NB7F43 R6 IO345NB6F39 AA11 IO363PB6F41 W7 IO381PB7F43 R7 IO345PB6F39 AB11 IO364NB6F41 W5 IO382NB7F43 N1 IO346NB6F39 AE1 IO364PB6F41 Y5 IO382PB7F43 P1 IO346PB6F39 AF1 IO365NB6F41 W10 IO383NB7F43 T10 IO347NB6F39 AL1 IO365PB6F41 W9 IO383PB7F43 T9 IO347PB6F39 AL2 IO366NB6F41 V2 IO384NB7F43 R3 v5.4 Bank 7 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number IO384PB7F43 R2 IO403NB7F46 N10 GND AA15 IO385NB7F44 R12 IO403PB7F46 N9 GND AA17 IO385PB7F44 R11 IO404NB7F46 L5 GND AA19 IO386NB7F44 L1 IO404PB7F46 L4 GND AA21 IO386PB7F44 M1 IO405NB7F46 M7 GND AA23 IO387NB7F44 G2 IO405PB7F46 M8 GND AA24 IO387PB7F44 F2 IO406NB7F46 G3 GND AB14 IO388NB7F44 P5 IO406PB7F46 F3 GND AB16 IO388PB7F44 P4 IO407NB7F46 M10 GND AB18 IO389NB7F44 R8 IO407PB7F46 M9 GND AB20 IO389PB7F44 R9 IO408NB7F46 D4 GND AB22 IO390NB7F44 J1 IO408PB7F46 D3 GND AC11 IO390PB7F44 K1 IO409NB7F46 J7 GND AC13 IO391NB7F44 N12 IO409PB7F46 J6 GND AC15 IO391PB7F44 P12 IO410NB7F46 J3 GND AC17 IO392NB7F44 M2 IO410PB7F46 K3 GND AC19 IO392PB7F44 N2 IO411NB7F46 L8 GND AC21 IO393NB7F44 P9 IO411PB7F46 L9 GND AC23 IO393PB7F44 P8 IO412NB7F47 K5 GND AC24 IO394NB7F45 M3 IO412PB7F47 K4 GND AC26 IO394PB7F45 N3 IO413NB7F47 K7 GND AC3 IO395NB7F45 M11 IO413PB7F47 K6 GND AC30 IO395PB7F45 N11 IO414NB7F47 E4 GND AC34 IO396NB7F45 M4 IO414PB7F47 F4 GND AC7 IO396PB7F45 N4 IO415NB7F47 G4 GND AD13 IO397NB7F45 N5 IO415PB7F47 G5 GND AD14 IO397PB7F45 N6 IO416NB7F47 H4 GND AD16 IO398NB7F45 J2 IO416PB7F47 J4 GND AD18 IO398PB7F45 K2 IO417NB7F47 D2 GND AD19 IO399NB7F45 N8 IO417PB7F47 D1 GND AD21 IO399PB7F45 N7 IO418NB7F47 K8 GND AD23 IO400NB7F45 G1 IO418PB7F47 K9 GND AD24 IO400PB7F45 H1 IO419NB7F47 H5 GND AE15 IO401NB7F45 M5 IO419PB7F47 J5 GND AE25 IO401PB7F45 M6 GND AF10 IO402NB7F45 E1 GND J8 GND AF11 IO402PB7F45 F1 GND AA13 GND AF14 Dedicated I/O v5.4 3-65 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 3 -6 6 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number GND AF17 GND AP35 GND L11 GND AF20 GND AP5 GND L14 GND AF23 GND AP8 GND L17 GND AF26 GND AR3 GND L20 GND AF27 GND AR34 GND L23 GND AF3 GND B3 GND L26 GND AF30 GND B34 GND L27 GND AF34 GND C11 GND L3 GND AF7 GND C14 GND L30 GND AJ29 GND C17 GND L34 GND AJ3 GND C2 GND L7 GND AJ30 GND C20 GND M15 GND AJ34 GND C23 GND M25 GND AJ7 GND C26 GND N14 GND AK11 GND C29 GND N16 GND AK14 GND C32 GND N18 GND AK17 GND C35 GND N19 GND AK20 GND C5 GND N21 GND AK23 GND C8 GND N23 GND AK26 GND E3 GND N24 GND AK29 GND E34 GND P11 GND AK6 GND F30 GND P13 GND AK8 GND F7 GND P14 GND AL18 GND G11 GND P16 GND AL31 GND G14 GND P18 GND AL7 GND G17 GND P20 GND AM3 GND G20 GND P22 GND AM34 GND G23 GND P24 GND AP11 GND G26 GND P26 GND AP14 GND G29 GND P3 GND AP17 GND G8 GND P30 GND AP2 GND H3 GND P34 GND AP20 GND H30 GND P7 GND AP23 GND H34 GND R15 GND AP26 GND H7 GND R17 GND AP29 GND J31 GND R19 GND AP32 GND L10 GND R21 v5.4 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number GND R23 GND W26 VCCA AC18 GND R27 GND W4 VCCA AC20 GND T13 GND Y11 VCCA AC22 GND T14 GND Y14 VCCA AE12 GND T16 GND Y16 VCCA AL32 GND T18 GND Y18 VCCA AL5 GND T20 GND Y20 VCCA AP3 GND T22 GND Y22 VCCA AP34 GND T24 GND Y26 VCCA AT18 GND U11 GND Y3 VCCA C3 GND U15 GND Y30 VCCA C34 GND U17 GND Y34 VCCA J30 GND U19 GND Y7 VCCA M12 GND U21 NC AJ8 VCCA P15 GND U23 NC W36 VCCA P17 GND U26 PRA F18 VCCA P19 GND U3 PRB A18 VCCA P21 GND U30 PRC AL19 VCCA P23 GND U34 PRD AT19 VCCA R14 GND U7 TCK H8 VCCA R16 GND V13 TDI F6 VCCA R18 GND V14 TDO H9 VCCA R20 GND V16 TMS F5 VCCA R22 GND V18 TRST G7 VCCA T15 GND V20 VCCA A19 VCCA T17 GND V22 VCCA AA14 VCCA T19 GND V24 VCCA AA16 VCCA T21 GND V33 VCCA AA18 VCCA T23 GND V4 VCCA AA20 VCCA U14 GND W11 VCCA AA22 VCCA U16 GND W13 VCCA AB15 VCCA U18 GND W15 VCCA AB17 VCCA U20 GND W17 VCCA AB19 VCCA U22 GND W19 VCCA AB21 VCCA V15 GND W21 VCCA AB23 VCCA V17 GND W23 VCCA AC14 VCCA V19 GND W24 VCCA AC16 VCCA V21 v5.4 3-67 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 3 -6 8 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number VCCA V23 VCCDA D16 VCCIB1 B26 VCCA W14 VCCDA D21 VCCIB1 B29 VCCA W16 VCCDA E13 VCCIB1 B32 VCCA W18 VCCDA E24 VCCIB1 F20 VCCA W20 VCCDA E5 VCCIB1 F23 VCCA W22 VCCDA E6 VCCIB1 F26 VCCA W33 VCCDA F19 VCCIB1 F29 VCCA Y15 VCCDA F31 VCCIB1 K20 VCCA Y17 VCCDA G30 VCCIB1 K23 VCCA Y19 VCCDA G31 VCCIB1 K26 VCCA Y21 VCCDA G6 VCCIB1 N20 VCCA Y23 VCCDA H28 VCCIB1 N22 VCCDA AB10 VCCDA H29 VCCIB2 E35 VCCDA AB27 VCCDA J29 VCCIB2 H31 VCCDA AE22 VCCDA L18 VCCIB2 H35 VCCDA AF18 VCCDA L19 VCCIB2 K27 VCCDA AF19 VCCDA M22 VCCIB2 L31 VCCDA AH29 VCCDA N13 VCCIB2 L35 VCCDA AH8 VCCDA R10 VCCIB2 P27 VCCDA AJ28 VCCDA V11 VCCIB2 P31 VCCDA AJ9 VCCDA V26 VCCIB2 P35 VCCDA AK30 VCCIB0 B11 VCCIB2 R24 VCCDA AK7 VCCIB0 B14 VCCIB2 U24 VCCDA AL30 VCCIB0 B17 VCCIB2 U27 VCCDA AL6 VCCIB0 B5 VCCIB2 U31 VCCDA AM13 VCCIB0 B8 VCCIB2 U35 VCCDA AM24 VCCIB0 F11 VCCIB3 AB24 VCCDA AM31 VCCIB0 F14 VCCIB3 AC27 VCCDA AM32 VCCIB0 F17 VCCIB3 AC31 VCCDA AM5 VCCIB0 F8 VCCIB3 AC35 VCCDA AM6 VCCIB0 K11 VCCIB3 AF31 VCCDA AN16 VCCIB0 K14 VCCIB3 AF35 VCCDA AN21 VCCIB0 K17 VCCIB3 AG27 VCCDA AP16 VCCIB0 N15 VCCIB3 AJ31 VCCDA AP21 VCCIB0 N17 VCCIB3 AJ35 VCCDA C16 VCCIB1 B20 VCCIB3 AM35 VCCDA C21 VCCIB1 B23 VCCIB3 Y24 v5.4 RTAX-S/SL RadTolerant FPGAs 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA 1272-Pin CCGA/LGA RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number RTAX4000S/SL Function Pin Number VCCIB3 Y27 VCCIB5 AG14 VCCIB6 AM2 VCCIB3 Y31 VCCIB5 AG17 VCCIB6 Y10 VCCIB3 Y35 VCCIB5 AL11 VCCIB6 Y13 VCCIB4 AD20 VCCIB5 AL14 VCCIB6 Y2 VCCIB4 AD22 VCCIB5 AL17 VCCIB6 Y6 VCCIB4 AG20 VCCIB5 AL8 VCCIB7 E2 VCCIB4 AG23 VCCIB5 AR11 VCCIB7 H2 VCCIB4 AG26 VCCIB5 AR14 VCCIB7 H6 VCCIB4 AL20 VCCIB5 AR17 VCCIB7 K10 VCCIB4 AL23 VCCIB5 AR5 VCCIB7 L2 VCCIB4 AL26 VCCIB5 AR8 VCCIB7 L6 VCCIB4 AL29 VCCIB6 AB13 VCCIB7 P10 VCCIB4 AR20 VCCIB6 AC10 VCCIB7 P2 VCCIB4 AR23 VCCIB6 AC2 VCCIB7 P6 VCCIB4 AR26 VCCIB6 AC6 VCCIB7 R13 VCCIB4 AR29 VCCIB6 AF2 VCCIB7 U10 VCCIB4 AR32 VCCIB6 AF6 VCCIB7 U13 VCCIB5 AD15 VCCIB6 AG10 VCCIB7 U2 VCCIB5 AD17 VCCIB6 AJ2 VCCIB7 U6 VCCIB5 AG11 VCCIB6 AJ6 VPUMP F32 v5.4 3-69 RTAX-S/SL RadTolerant FPGAs Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (v5 . 4) v5.3 (October 2008) Page RT4000S now supports the low-power grade option. In addition, this device has moved from a preliminary state to a production state. N/A RTAX250S/SL supports 624-CCGA/LGA. The following tables were updated. "RTAX-S/SL Family Product Profile","Temperature Grade Offerings","Ordering Information" N/A All DC input and output tables and timing characteristic tables were updated. N/A The "Ordering Information" section was updated. B was deleted from the Package Type and the speed grade description was updated. ii The "Temperature Grade Offerings" table note was updated. ii The "Speed Grade and Temperature Grade Matrix" table was updated. iii The "I/Os per Package" table is new. iii In Table 2 * Actel MIL-STD-883 Class B Product Flow for RTAX-S/SL1, 2, "TBD" in step 4 was changed to "Condition A". iv In Table 3 * Actel Extended Flow for RTAX-S/SL1, 2, 3, 4, "TBD" in step 4 was changed to "Condition A". v In the first paragraph of the "General Description" section, it originally said there were two million equivalent system gates but that is incorrect because there are four million equivalent system gates. 1-1 Information about segmenting clocks was added to the "Global Resources" section. 1-7 The "Prototyping with ProASIC3E Reprogrammable Units" section is new. 1-8 In Table 2-1 * I/O Features Comparison, LVTTL was updated. Note 1 was updated and note 4 is new. 2-1 In Table 2-2 * Absolute Maximum Ratings, the limit for VI was changed from 4.0 to 4.1 and VPUMP was added to the table. 2-2 The "5 V Tolerance" section was significantly updated. 2-1 RTAX4000S/SL data was updated in Table 2-4 * RTAX-S Standby Current. For RTAX2000S/SL, ICCDIFFA was changed from 2.96 to 3.13. The IIL/IIH heading was changed to IIH, IIL, or IOZ. Note 1 is new. 2-3 RTAX4000S/SL data was added to Table 2-5 * RTAX-SL Standby Current. ICCA data was updated for Typical 25C for RTAX2000S/SL, RTAX1000S/SL, and RTAX250S/SL. The IIL/IIH heading was changed to IIH, IIL, or IOZ. Note 1 is new. 2-3 Table 2-6 * Default Cload / VCCI was significantly updated. 2-4 In the "Ptotal = Pdc + Pac" section, the "Pdc" definition, Nbanks was deleted. 2-5 In the "Pmemory = 0 mW" section, the "Pdc" definition, Nbanks was deleted. 2-6 Table 2-8 * Package Thermal Characteristics was updated to include 624-pin CCGA/LGA 2-7 Table 2-9 * Temperature and Voltage Timing Derating Factors was significantly updated. 2-9 In the "Hardwired Clock" section, the Clock-to-Out (Pad-to-Pad) was updated. TRCO was changed from 0.9 to 0.96. 2-10 In the "Routed Clock1" section, the Clock-to-Out (Pad-to-Pad) was updated. TRCO was changed from 0.9 to 0.96. Footnote 1 is new. 2-10 The "VCCIBx Supply Voltage" section was updated to include information about unused banks. 2-11 The "HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C, and D" section was updated. 2-11 The "VPUMP Supply Voltage (External Pump)" section was updated. 2-11 v5.4 4-1 RTAX-S/SL RadTolerant FPGAs Previous version Changes in current version (v5 . 4) Page v5.3 (continued) The "CLKE/F/G/H Global Clocks E, F, G, and H" section was updated. 2-11 The "PRA/B/C/D Probes A, B, C, and D" section was updated. 2-12 Information about SEUs and cell buffers was added to "Introduction" section. 2-12 In Table 2-15 * Macros for Single-Ended I/O Standards, the macro names for LVTTL were changed from _H_ to _F_ 2-19 The "Customizing the I/O" section was updated. Table 2-14 * Bank Wide Delay Values is new. 2-14 The data in Table 2-19 * I/O Weak Pull-Up/Pull-Down Resistances1 was significantly updated. Notes 1, 2, and 3 were also updated. 2-22 The note was updated to include pin compatibility information for "352-Pin CQFP". 3-8 The note was updated to include pin compatibility information for "624-Pin CCGA/LGA". the RTAX250S/SL pin table is new. 3-26 The "352-Pin CQFP" table for the RTAX250S/SL device is new. 3-10 In Table 2-21 * DC Input and Output Levels, the footnote is new. 2-26 In Table 2-36 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C, the footnote is new. 2-51 Table 2-54 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C was significantly updated. 2-57 Table 2-88 * One RAM Block (Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) 2-85 to to Table 2-92 * Sixteen RAM Blocks Are Cascaded (Worst-Case Military Conditions VCCA = 1.4 V, VCCI 2-89 = 3.0 V, TJ = 125C) were updated. Table 2-96 * FIFO Signal Description to Table 2-101 * Sixteen FIFO Blocks are Cascaded (Worst-Case 2-94 to MIlitary Conditions VCCA = 1.4 V, VCCI = 3.0 V, TJ = 125C) were updated. 2-98 In the "RTAX2000S/SL Function" table, the block numbers were removed. For example "Bank 0, Block 0" was changed to "Bank 0". 3-5 v5.2 (October 2007) In Table 2-5 * RTAX-SL Standby Current, the ICCA specifications were updated for 125C. 2-3 v5.1 (August 2007) The "I/O Logic" section was updated to include information about user flip-flops being immune to SEU. 1-5 The "Low-Cost Prototyping Solutions" section was updated significantly. 1-7 Table 2-4 * RTAX-S Standby Current was updated to include IIH/IIL. 2-3 Table 2-5 * RTAX-SL Standby Current was updated to include IIH/IIL. 2-3 The CG1272 was updated in the "Package Thermal Characteristics" table. 2-7 The temperature in note 1 was changed from 175 to 125 in the "Temperature and Voltage Timing Derating Factors" table. 2-9 In the "Timing Model", the Hardwired Clock was changed to Routed or Hardwired. 2-10 v5.0 (June 2007) 4 -2 The "Ordering Information" section was updated to include the Sigma Six Column and BAE Column designation. A note was added to the "Temperature Grade Offerings" table regarding the Sigma Six Column and BAE Column. v5.4 ii RTAX-S/SL RadTolerant FPGAs Previous version Changes in current version (v5 . 4) Page v4.0 RTAX-SL information is new. N/A (May 2007) EV Flow (Class V Flow Equivalent Processing) information is new. N/A The "Ordering Information" section was updated. ii The "Actel MIL-STD-883 Class B Product Flow" table was updated. iv The "Actel Extended Flow" table was updated. v3.0 v The "Low-Cost Prototyping Solutions" section was updated to include RTAX-SL prototyping information. 1-7 Table 2-5 * RTAX-SL Standby Current is new. 2-3 In the "Sample Case 2: Convection = 0" section, cb was changed to Tj. 2-8 The Axcelerator figure listed below the "VCCDA Supply Voltage" section was incorrect and has been removed from the datasheet. 2-11 The "256-Pin CQFP" table for the RTAX2000S/SL device is new. 3-5 All information regarding the RTAX4000S device is new. N/A The "Timing Model" was updated. 2-10 September 2006 The "Specifications" section was updated. i The SEL and SET information was updated in the "Designed for Space" section. i The maximum I/O counts for the RTAX250S and RTAX1000S were updated in Table 1 * RTAX-S/SL Family Product Profile. i The "Device Resources" table was updated for CG1272/LG1272. iii The RTAX-S/SL Testing and Reliability Update white paper was added to the "White Papers" section. 1-9 The "User I/Os" section was updated with information on configuring unused I/Os. 2-12 Implementing DDR was updated in the "Using DDR (Double Data Rate)" section. 2-17 PSET was changed to PRE and D was changed to E in Figure 2-6 * DDR Register. 2-18 v3.0 The "JTAG" section was updated with JTAG pin information. 2-100 (continued) Figure 2-1 * Use of an External Resistor for 5 V Tolerance was updated. 2-1 Note 2 in Table 2-2 * Absolute Maximum Ratings was updated. 2-2 The "Calculating Power Dissipation" section was updated. 2-3 Table 2-25 * Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125C was updated. 2-30 The "Hardwired Clock" and "Routed Clock1" equations were updated. 2-10 v2.2 Table 2-4 * RTAX-S Standby Current was updated. 2-3 Table 2-6 * Default Cload / VCCI was updated. 2-4 Table 2-9 * Temperature and Voltage Timing Derating Factors was updated. 2-9 All timing characteristic tables were updated. N/A The "352-Pin CQFP" table for the RTAX4000S is new. 3-22 The "1272-Pin CCGA/LGA" table for the RTAX4000S is new. 3-58 All Timing Characteristic tables were updated. N/A Cold Sparing was added to the Hot Insertion heading in Table 2-1 * I/O Features Comparison. 2-1 The "Thermal Characteristics" section was updated. 2-7 The "Simultaneous Switching Outputs (SSO)" section was updated. 2-14 The "Timing Model" has been updated. 2-10 May 2006 v5.4 4-3 RTAX-S/SL RadTolerant FPGAs Previous version Changes in current version (v5 . 4) Page v2.2 (continued) The "Hardwired Clock" and "Routed Clock1" equations were updated. 2-10 Table 2-6 * Default Cload / VCCI was updated. 2-4 1 v2.1 Table 2-18 * I/O Weak Pull-Up/Pull-Down Resistances is new. 2-21 A note was added to Table 2-58 * DC Input and Output Levels. 2-60 The LVDS Capable I/O specification was added to "Leading-Edge Performance". i-i October 2005 Table 1 * RTAX-S/SL Family Product Profile was updated to include CQ256. i-i CQ256 was added to the"Temperature Grade Offerings" table. i-ii CQ256 is new and CQ352 for the RTAX1000S device was updated in the "Device Resources" table. i-iii The "Overshoot/Undershoot Limits" section is new. 2-2 Table 2-2 * Absolute Maximum Ratings was updated. 2-2 Table 2-3 * RTAX-S/SL Recommended Operating Conditions was updated. 2-2 The "Timing Model" has been updated. 2-10 The "Hardwired Clock" and "Routed Clock1" equations were updated. 2-10 This sentence was updated in the "CLKE/F/G/H Global Clocks E, F, G, and H" section: 2-11 When the CLK pins are unused, Actel recommends that they are tied to a known state. Figure 2-27 * LVPECL Circuit was updated. The following labels were corrected: 2-60 INBUF_LVPECL OUTBUF_LVPECL The following sentence was removed from "Global Resource Distribution": 2-78 An unused input can be tied to ground for power savings. The "RAM" section was updated. v2.0 4 -4 2-81 The "256-Pin CQFP" package figure and is new. 3-4 In Table 2-4, the ICCA column heading was changed to ICCDA and note 3 is new. 2-3 v5.4 RTAX-S/SL RadTolerant FPGAs Previous version Changes in current version (v5 . 4) Advanced v0.5 Page The "Designed for Space" section was updated. i-i Table 1 was updated to include 1152 CCGA/LGA. i-i The "Temperature Grade Offerings" table was updated to include the 1152 CCGA. i-iii The RTAX1000S and the RTAX2000S columns were updated in the "Device Resources" table. i-iii Figure 1-9 was updated and a note was added to the figure. 1-8 Table 2-4 * RTAX-S Standby Current was updated. 2-3 In Table 2-4 the LVPECL and LVDS specifications were updated. A note was also added to the table. 2-3 The "Global Resource Access Macros" section was updated. 2-80 The "JTAG" section was updated. 2-100 In the "Data Registers (DRs)" section the IDCODE and USERCODE were changed from 32 bits to 33 bits. 2-100 150C was changed to 125C in the "Thermal Characteristics" section. 2-7 Table 2-8 * Package Thermal Characteristics was updated to include the 1152 CCGA. Values in the table were updated. 2-7 A note was added to the "FIFO" section. 2-90 Table 2-7 * Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices was updated. 2-4 Table 2-17 was updated. 2-20 All Timing Characteristic tables from Table 2-22 to Table 2-84 were updated. Advanced v0.4 2-25 to 2-81 In the "Actel MIL-STD-883 Class B Product Flow" table, #3 for the 883 Method was updated. A note was also added to the table. i-iv In the "Actel Extended Flow" table, #5 for the Method column was updated. The notes were also added to the table. i-iv In the "Pin Descriptions" section, the descriptions for the "HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C, and D" and "CLKE/F/G/H Global Clocks E, F, G, and H" were updated. 2-11 A footnote was added to the "PRA/B/C/D Probes A, B, C, and D", "TCK2 Test Clock", "TDI2 Test Data Input", "TDO2 Test Data Output", and "TDO2 Test Data Output" descriptions. 2-12 The "1152-Pin CCGA/LGA" section is new. 3-45 LETTH values for SEU and SEL updated under "Designed for Space". i-i "Ordering Information" was updated/ The "Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix"tables are new and the "Device Resources" was updated. i-ii Sections "Actel MIL-STD-883 Class B Product Flow" and "Actel Extended Flow" are new. i-iv, i-v "General Description" was updated. 1-1 Table 2-7 * Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices was updated. 2-4 The"Thermal Characteristics" section was updated. 2-7 Figure 2-4 * Timing Model, the "Hardwired Clock"section and the "Routed Clock1" section were updated. 2-10 v5.4 4-5 RTAX-S/SL RadTolerant FPGAs Previous version Changes in current version (v5 . 4) Page Advanced v.04 (continued) The "Introduction" section under "User I/Os" was updated to give details regarding VREF usage. 2-12 The "Simultaneous Switching Outputs (SSO)" section under "User I/Os" was updated. 2-14 "Using DDR (Double Data Rate)" is new. 2-17 Table 2-18 was updated. 2-22 All Timing Characteristic Tables were updated. "Introduction" was updated. 2-66 The "SEU Hardened D Flip-Flop (DFF)" section was moved under "R-Cell" and updated. 2-67 The "Global Resource Distribution" section is new. 2-78 The "Enhancing SEU Performance" section is new. 2-83 Figure 2-49 and Figure 2-50 were updated. 2-84 Figure 2-57 and Figure 2-58 were updated. 2-95 The "Charge Pump Bypass" section is new. 2-100 The "TRST" section was updated. 2-100 The "Global Set Fuse" section is new. 2-102 The "208-Pin CQFP" for both the RTAX250S and RTAX1000S were added. Advanced v0.3 Advanced v0.1 4 -6 3-1 The "352-Pin CQFP" pin tables for both the RTAX1000S and RTAX2000S were updated. 3-8 The "624-Pin CCGA/LGA" pin tables for both the RTAX1000S and RTAX2000S were updated. 3-26 The "Designed for Space" section was updated. A new device, the RTAX250S, was added to the "Designed for Space", "Ordering Information", "Temperature Grade Offerings" and "Device Resources" sections. Advanced v0.2 2-25 to 2-99 i-i i to iii 2.5V GTL+ support across full military range was removed. n/a Table 1-1 * Number of Core Tiles per Device was updated. 1-4 Table 2-4 * RTAX-S Standby Current and Table 2-6 * Default Cload / VCCI were updated. 2-4 Table 2-7 * Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices was updated. 2-4 Table 2-13 * Legal I/O Usage Matrix was updated. 2-15 Table 2-17 * I/O Macros for Voltage-Referenced I/O Standards 2-20 In the "352-Pin CQFP" for the RTAX1000S, pin 80 has been changed from VCCI to VCCIB6. 3-14 In the "208 CQFP" and "352-Pin CQFP", the NC (VPP) was changed to NC for all pins. 3-2 to 3-14 The 352-Pin CQFP for the RTAX1000S is new. 3-10 Pins 14 and 32 have been changed from VCCA to VCCI for the RTAX2000S in the "352-Pin CQFP". 3-10 The "624-Pin CCGA/LGA" for the RTAX1000S is new. 3-39 v5.4 RTAX-S/SL RadTolerant FPGAs Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. International Traffic in Arms Regulations (ITAR) The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, lifesupport, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v5.4 4-7 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. 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