MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
________________________________________________________________
Maxim Integrated Products
1
OUT0
OUT1
OUT15
IN0
CAMERAS
IN1
IN15
MONITOR
MONITOR
MONITOR
MAX9675
MAX9675
16 x 16
SWITCH MATRIX
POWER-ON
RESET
SERIAL
INTERFACE
THERMAL
SHUTDOWN
DECODE LOGIC
DISABLE ALL OUTPUTS
LATCHES
256 16
16
MATRIX REGISTER
96 BITS
UPDATE REGISTER
16 BITS
ENABLE/DISABLE
AV*
AV*
AV*
AV*
*AV = +1V/V OR +2V/V
A0–A3 MODE
IN0
IN1
IN2
IN15
DIN
SCLK
UPDATE
CE
RESET
OUT0
OUT1
OUT2
OUT15
VCC
VEE
DGND
VDD
DOUT
AOUT
AGND
Typical Operating Circuit
Functional Diagram
19-4230; Rev 0; 7/08
SPI and QSPI are trademarks of Motorola, Inc.
General Description
The MAX9675 is a nonblocking 16 x 16 video cross-
point switch with buffered inputs and outputs. The
device operates on ±5V analog supplies. Digital logic is
supplied separately from an independent +2.7V to +5V
supply. The MAX9675 inputs and outputs are buffered
with all outputs able to drive a standard 75Ωreverse-
terminated video load.
The switching matrix and programmable gain are con-
trolled through an SPI™/QSPI™-compatible 3-wire seri-
al interface. The serial interface is designed to operate
in either of two modes to provide fast updates and ini-
tialization. All outputs are held in the disabled state
during power-up to avoid signal conflicts in large
switching arrays.
The programmability and high level of integration make
the MAX9675 an ideal choice for nonblocking video
switch arrays in security, surveillance, and video-
on-demand systems.
The MAX9675 is available in a 100-pin TQFP package
and specified over the extended -40°C to +85°C tem-
perature range.
Applications
Security Systems
Video Routing
Video-on-Demand Systems
Features
♦16 x16 Nonblocking Matrix with Buffered Inputs
and Outputs
♦Operates at ±5V Supply
♦Individually Programmable Output Buffer Gain
(AV= +1V/V or +2V/V)
♦High-Impedance Output Disable for Wired-OR
Connections
♦0.1dB Gain Flatness to 14MHz
♦-3dB Bandwidth 110MHz
♦-62dB Crosstalk, -110dB Isolation at 6MHz
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX9675ECQ+ -40°C to +85°C 100 TQFP
Pin Configuration appears at end of data sheet.
+Denotes a lead-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V
(VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Analog Supply Voltage (VCC - VEE) .....................................+11V
Digital Supply Voltage (VDD - DGND) ...................................+6V
Analog Supplies to Analog Ground
(VCC - AGND) and (AGND - VEE) ......................................+6V
Analog Ground to Digital Ground .........................-0.3V to +0.3V
IN_ Voltage Range .......................... (VCC + 0.3V) to (VEE - 0.3V)
OUT_ Short-Circuit Duration to AGND, VCC, or VEE......Indefinite
SCLK, CE, UPDATE, MODE, A_, DIN, DOUT,
RESET, AOUT.........................(VDD + 0.3V) to (DGND - 0.3V)
Current into Any Analog Input Pin (IN_) ...........................±50mA
Current into Any Analog Output Pin (OUT_).....................±75mA
Continuous Power Dissipation (TA= +70°C)
100-Pin TQFP (derate 22.2mW/°C above +70°C).....1777mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage
Range
VCC -
VEE
Guaranteed by PSRR test 4.5 10.5 V
Logic-Supply Voltage Range VDD to
DGND 2.7 5.5 V
(VEE + 2.5V) < VIN_ < (VCC - 2.5V),
AV = +1V/V, RL = 150Ω 1
(VEE + 2.5V) < VIN_ < (VCC - 2.5V),
AV = +1V/V, RL = 10kΩ 1
(VEE + 3.75V) < VIN_ < (VCC - 3.75V),
AV = +2V/V, RL = 150Ω 2
(VEE + 3.75V) < VIN_ < (VCC - 3.75V),
AV = +2V/V, RL = 10kΩ 2
Gain (Note 1) AV
(VEE + 1V) < VIN_ < (VCC - 1.2V),
AV = +1V/V, RL = 10kΩ 1
V/V
RL = 10kΩ 0.5 1.5
Gain Matching
(Channel to Channel)
RL = 150Ω 0.5 2
%
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V (continued)
(VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Temperature Coefficient of
Gain TCAV 10 ppm/°C
RL = 10kΩ V
E E
+ 1
V
C C
-
1.2
AV = +1V/V
RL = 150Ω V
E E
+
2.5
V
C C
-
2.5
RL = 10kΩ V
E E
+
3
V
C C
-
3.1
Input Voltage Range VIN_
AV = +2V/V
RL = 150Ω V
E E
+
3.75
V
C C
-
3.75
V
RL = 10kΩ V
E E
+
1
V
C C
-
1.2 V
Output Voltage Range VOUT_
RL = 150Ω V
E E
+
2.5
V
C C
-
2.5 V
Input Bias Current IB 4 11 µA
Input Resistance RIN_ (VEE + 1V) < VIN_ < (VCC - 1.2V) 10 MΩ
AV = +1V/V ±5 ±20
Output Offset Voltage VOFFSET AV = +2V/V ±10 ±40
mV
Output Short-Circuit Current ISC Sinking or sourcing, RL = 1Ω ±40 mA
Enabled Output Impedance ZOUT (VEE + 1V) < VIN_ < (VCC - 1.2V) 0.2 Ω
Output Leakage Current,
Disable Mode IOD (VEE + 1V) < VOUT_ < (VCC - 1.2V) 0.004 1 µA
DC Power-Supply Rejection
Ratio PSRR 4.5V < (VCC - VEE) < 10.5V 60 70 dB
Outputs enabled,
TA = +25°C 100 150
Outputs enabled 175
ICC RL = ∞
Outputs disabled 55 75
Outputs enabled,
TA = +25°C 95 150
Outputs enabled 175
IEE RL = ∞
Outputs disabled 50 75
Quiescent Supply Current
IDD 4 8
mA
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
4 _______________________________________________________________________________________
LOGIC-LEVEL CHARACTERISTICS
(VCC = +5V, VEE = -5V, VDD = +2.7V to +5.5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD = +5V 3
Input-Voltage High Level VIH VDD = +3V 2 V
VDD = +5V 0.8
Input-Voltage Low Level VIL VDD = +3V 0.6 V
Excluding RESET -1 +0.01 +1
Input Current High Level IIH VI > 2V RESET -30 -20 µA
Excluding RESET -1 +0.01 +1
Input Current Low Level IIL VI < 1V RESET -300 -235 µA
ISOURCE = 1mA, VDD = +5V 4.7 4.9
Output-Voltage High Level VOH ISOURCE = 1mA, VDD = +3V 2.7 2.9 V
ISINK = 1mA, VDD = +5V 0.1 0.3
Output-Voltage Low Level VOL ISINK = 1mA, VDD = +3V 0.1 0.3 V
VDD = +5V, VO = +4.9V 1 4
Output Current High Level IOH VDD = +3V, VO = +2.7V 1 8 mA
VDD = +5V, VO = +0.1V 1 4
Output Current Low Level IOL VDD = +3V, VO = +0.3V 1 8 mA
AC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V
(VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AV = +1V/V 110
Small-Signal -3dB
Bandwidth BWSS VOUT_ = 20mVP-P AV = +2V/V 78
MHz
AV = +1V/V 80
Medium-Signal -3dB
Bandwidth BWMS VOUT_ = 200mVP-P AV = +2V/V 75
MHz
AV = +1V/V 40
Large-Signal -3dB
Bandwidth BWLS VOUT_ = 2VP-P AV = +2V/V 50
MHz
AV = +1V/V 14
Small-Signal 0.1dB
Bandwidth BW0.1dB-SS VOUT_ = 20mVP-P AV = +2V/V 11
MHz
AV = +1V/V 14
Medium-Signal 0.1dB
Bandwidth BW0.1dB-MS VOUT_ = 200mVP-P AV = +2V/V 11
MHz
AV = +1V/V 14
Large-Signal 0.1dB
Bandwidth BW0.1dB-LS VOUT_ = 2VP-P AV = +2V/V 11
MHz
VOUT_ = 2V step, AV = +1V/V 150
Slew Rate SR VOUT_ = 2V step, AV = +2V/V 150
V/µs
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
_______________________________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V (continued)
(VCC = +5V, VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, AV= +1V/V, and TA= +25°C, unless other-
wise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AV = +1V/V 60
Settling Time tS 0.1% VOUT_ = 0 to 2V step AV = +2V/V 60
ns
AV = +1V/V 50
Switching Transient (Glitch)
(Note 3)
AV = +2V/V 45
mV
f = 100kHz 70
AC Power-Supply Rejection
Ratio
f = 1MHz 68
dB
RL = 1kΩ 0.002
Differential Gain Error
(Note 4)
RL = 150Ω 0.02
%
RL = 1kΩ 0.02
Differential Phase Error
(Note 4)
RL = 150Ω 0.12
d eg r ees
Crosstalk, All Hostile f = 6MHz -62 dB
Off-Isolation, Input to Output f = 6MHz -110 dB
Input Noise-Voltage Density en BW = 6MHz 73 µVRMS
Input Capacitance CIN 5 pF
Disabled Output
Capacitance Amplifier in disable mode 3 pF
Capacitive Load at 3dB
Output Peaking 30 pF
Output enabled 3
Output Impedance ZOUT f = 6MHz Output disabled 4k
Ω
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
6 _______________________________________________________________________________________
SWITCHING CHARACTERISTICS
(VCC = +5V, VEE = -5V, VDD = +2.7V to +5.5V, DGND = AGND = 0, VIN_ = 0 for dual supplies, RL= 150Ωto AGND, CL= 100pF, AV
= +1V/V, and TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Delay: UPDATE to Video Out tPdUdVo VIN_ = 0.5V step 200 450 ns
Delay: UPDATE to AOUT tPdUdAo
MODE = 0, time to AOUT = low after
UPDATE = low 30 200 ns
Delay: SCLK to DOUT Valid tPdDo
Logic state change in DOUT on active
SCLK edge 30 200 ns
Delay: Output Disable tPdHOe VOUT_ = 0.5V, 1kΩ pulldown to AGND 300 800 ns
Delay: Output Enable tPdLOe
Output disabled, 1kΩ pulldown to AGND,
VIN_ = 0.5V 200 800 ns
Setup: CE to SCLK tSuCe 100 ns
Setup: DIN to SCLK tSuDi 100 ns
Hold Time: SCLK to DIN tHdDi 100 ns
Minimum High Time: SCLK tMnHCk 100 ns
Minimum Low Time: SCLK tMnLCk 100 ns
Minimum Low Time: UPDATE tMnLUd 100 ns
Setup Time: UPDATE to SCLK tSuHUd
Rising edge of UPDATE to falling edge of
SCLK 100 ns
Hold Time: SCLK to UPDATE tHdHUd
Falling edge of SCLK to falling edge of
UPDATE 100 ns
Setup Time: MODE to SCLK tSuMd
Minimum time from clock edge to MODE
with valid data clocking 100 ns
Hold Time: MODE to SCLK tHdMd
Minimum time from clock edge to MODE
with valid data clocking 100 ns
Minimum Low Time: RESET tMnLRst 300 ns
Delay: RESET tPdRst 10kΩ pulldown to AGND, 0.5V step 600 ns
Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (AV) and adding output
offset voltage.
Note 2: Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, and AOUT.
Note 3: Switching transient settling time is guaranteed by the settling time (tS) specification. Switching transient is a result of updat-
ing the switch matrix.
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.
Note 5: All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
_______________________________________________________________________________________ 7
SYMBOL TYPE DESCRIPTION
Ao Signal Address Valid Flag
(AOUT)
Ce Signal Clock Enable (CE)
Ck Signal Clock (SCLK)
Di Signal Serial-Data In (DIN)
Do Signal Serial-Data Output
(DOUT)
Md Signal MODE
Oe Signal Output Enable
Rst Signal Reset Input (RESET)
Ud Signal UPDATE
Vo Signal Video Out (OUT)
H Property High- or Low-to-High
Transition
Hd Property Hold
L Property Low- or High-to-Low
Transition
Mn Property Minimum
Mx Property Maximum
Pd Property Propagation Delay
Su Property Setup
Tr Property Transition
W Property Width
Symbol Definitions
Naming Conventions
• All parameters with time units are given a "t" desig-
nation, with appropriate subscript modifiers.
• Propagation delays for clocked signals are from the
active edge of clock.
• Propagation delay for level-sensitive signals is from
input to output at the 50% point of a transition.
• Setup and hold times are measured from the 50%
point of signal transition to the 50% point of the
clocking signal transition.
• Setup time refers to any signal that must be stable
before the active clock edge, even if the signal is
not latched or clocked itself.
• Hold time refers to any signal that must be stable
during and after active clock edge, even if the sig-
nal is not latched or clocked.
• Propagation delays to unobservable internal signals
are modified to setup and hold designations
applied to observable I/O signals.
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
8 _______________________________________________________________________________________
DATA AND CONTROL TIMING
Ce: CE
Di: DIN
Do: DOUT
Ud: UPDATE
Vo: OUT_
Rst: RESET
Oe: OUTPUT ENABLE
Ao: AOUT
tSuCe tHdCe
tMnHCk
tMnLCk
tSuDi
tHdDi
tPdDo tHdUd
tMnLUd
tSuUd
Hi-Z tPdUdVo
tWTrVo
tPdUdAo tPdRstVo
tMnlRst
tPdHOeVo tPdLOeVo
Hi-Z
TIMING PARAMETER DEFINITIONS
NAME DESCRIPTION
tPdUdVo Delay: Update to Video Out
tPdUdAo Delay: UPDATE to Aout
tPdDo Delay: Clk to Data Out
Delay: Output Enable to Video Output
(High: Disable)
Delay: Output Enable to Video Output
(Low: Enable)
tSuCe Setup: Clock Enable to Clock
tSuDi Setup Time: Data In to Clock
TIMING PARAMETER DEFINITIONS
NAME DESCRIPTION
tHdDi Hold Time: Clock to Data In
tMnHCk Min High Time: Clk
tMnLCk Min Low Time: Clk
tMnLUd Min Low Time: Update
tSuHUd Setup Time: UPDATE to Clk with UPDATE High
Not Valid Setup Time: UPDATE to Clk with UPDATE Low
tHdHUd Hold Time: Clk to UPDATE with UPDATE high
Not Valid Hold Time: Clk to UPDATE with UPDATE Low
tPdDiDo Asynchronous Delay: Data In to Data Out
tMnMd Min Low Time: MODE
tMxTr Max Rise Time: Clk, Update
tMnLRst Min Low Time: Reset
tPdRstVo Delay: Reset to Video Output
Ck: SCLK
tPdHOeVo
tPdLOeVo
Figure 1. Timing Diagram
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
_______________________________________________________________________________________
9
Typical Operating Characteristics
(VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA = +25°C, unless otherwise
noted.)
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc01
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 150Ω
AV = +2V/V
AV = +1V/V
3
-7
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc02
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 150Ω
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
SMALL-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc03
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 150Ω
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc04
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 1kΩ
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc05
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 1kΩ
AV = +2V/V
AV = +1V/V
3
-7
0.1 1 10 100 1000
SMALL-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc06
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 1kΩ
AV = +1V/V
AV = +2V/V
0.3
-0.7
0.1 1 10 100 1000
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
-0.5
MAX9675 toc07
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-0.3
-0.1
0.1
0
-0.2
-0.4
-0.6
0.2
AV = +1V/V
AV = +2V/V
RL = 150Ω0.3
-0.7
0.1 1 10 100 1000
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
-0.5
MAX9675 toc08
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-0.3
-0.1
0.1
0
-0.2
-0.4
-0.6
0.2
AV = +1V/V
AV = +2V/V
RL = 1kΩ
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
(AV = +1V/V)
-5
MAX9675 toc09
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 150Ω
CL = 30pF
CL = 15pF
CL = 45pF
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA = +25°C, unless otherwise
noted.)
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
(AV = +2V/V)
-5
MAX9675 toc10
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2RL = 150Ω
CL = 30pF
CL = 15pF
CL = 45pF
0.1 101 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
(AV = +1V/V)
MAX9675 toc11
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-10
-5
5
0
10
15
CL = 45pF
CL = 15pF
CL = 30pF
7
-3
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
(AV = +2V/V)
-1
MAX9675 toc12
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
1
3
5
4
2
0
-2
6
CL = 15pF
CL = 45pF
CL = 30pF
-40
-100
0.1 10 1001 1000
MAX9675 toc13
FREQUENCY (MHz)
CROSSTALK (dB)
-90
-80
-70
-60
-50
CROSSTALK vs. FREQUENCY
AV = +1V/V
-40
-100
0.1 10 1001 1000
MAX9675 toc14
FREQUENCY (MHz)
CROSSTALK (dB)
-90
-80
-70
-60
-50
CROSSTALK vs. FREQUENCY
AV = +2V/V
-10
-100
0.1 100101
DISTORTION vs. FREQUENCY
-70
-90
-30
-50
0
-60
-80
-20
-40
MAX9675 toc15
FREQUENCY (MHz)
DISTORTION (dBc)
AV = +1V/V
2ND HARMONIC
3RD HARMONIC
-10
-100
0.1 100101
DISTORTION vs. FREQUENCY
-70
-90
-30
-50
0
-60
-80
-20
-40
MAX9675 toc16
FREQUENCY (MHz)
DISTORTION (dBc)
AV = +2V/V
2ND HARMONIC
3RD HARMONIC
0.1 101 100 1000
ENABLED OUTPUT IMPEDANCE
vs. FREQUENCY
MAX9675 toc17
FREQUENCY (MHz)
OUTPUT IMPEDANCE (Ω)
1000
-0.1
1
10
100
1M
1
100k 10M 100M1M 1G
MAX9675 toc18
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
10
100
1k
10k
100k
DISABLED OUTPUT IMPEDANCE
vs. FREQUENCY
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________
11
Typical Operating Characteristics (continued)
(VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA = +25°C, unless otherwise
noted.)
-40
-50
-60
-70
-80
-90
-100
-110
-120
100k 10M 100M1M 1G
MAX9675 toc19
FREQUENCY (Hz)
OFF-ISOLATION (dB)
OFF-ISOLATION vs. FREQUENCY
10k 1M100k 10M 100M
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX9675 toc20
FREQUENCY (Hz)
PSRR (dB)
-75
-70
-60
-65
-55
-50 1000
1
10 10k 100k 1M100 1k 10M
INPUT VOLTAGE NOISE vs. FREQUENCY
100
MAX9675 toc21
FREQUENCY (Hz)
VOLTAGE NOISE (nV/√Hz)
25ns/div
LARGE-SIGNAL PULSE RESPONSE
(AV = +1V/V)
INPUT
1V/div
OUTPUT
0.5V/div
MAX9675 toc22
25ns/div
LARGE-SIGNAL PULSE RESPONSE
(AV = +2V/V)
INPUT
0.5V/div
OUTPUT
0.5V/div
MAX9675 toc23
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE
(AV = +1V/V)
INPUT
100mV/div
OUTPUT
50mV/div
MAX9675 toc24
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE
(AV = +2V/V)
INPUT
50mV/div
OUTPUT
50mV/div
MAX9675 toc25
20ns/div
SWITCHING TIME
(AV = +1V/V)
VUPDATE
5V/div
VOUT
500mV/div
MAX9675 toc26
20ns/div
SWITCHING TIME
(AV = +2V/V)
VUPDATE
5V/div
VOUT
1V/div
MAX9675 toc27
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA = +25°C, unless otherwise
noted.)
20ns/div
SWITCHING TRANSIENT (GLITCH)
(AV = +1V/V)
VUPDATE
5V/div
VOUT
25mV/div
MAX9675 toc28
20ns/div
SWITCHING TRANSIENT (GLITCH)
(AV = +2V/V)
VUPDATE
5V/div
VOUT
25mV/div
MAX9675 toc29
0
100
50
200
150
250
300
-15 -11 -9 -7-13 -5 -3 -1 135
OFFSET VOLTAGE DISTRIBUTION
MAX9675 toc30
OFFSET VOLTAGE (mV)
-0.05
0102030405060708090100
0102030405060708090100
DIFFERENTIAL GAIN AND PHASE
(RL = 150Ω)
0
0
-0.02
0.05
0.02
0.04
0.10
0.06
0.08
0.15
IRE
DIFFERENTIAL
PHASE (°)
DIFFERENTIAL
GAIN (%)
MAX9675 toc31
0.01
0
0102030405060708090100
0102030405060708090100
DIFFERENTIAL GAIN AND PHASE
(RL = 1kΩ)
-0.004
0.02
-0.002
0
0.002
0.004
0.03
IRE
DIFFERENTIAL
GAIN (%)
MAX9675 toc32
-0.01
DIFFERENTIAL
PHASE (°)
25ns/div
LARGE-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (CL = 30pF, AV = +1V/V)
INPUT
1V/div
OUTPUT
0.5/Vdiv
MAX9675 toc33
25ns/div
LARGE-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (CL = 30pF, AV = +2V/V)
INPUT
0.5V/div
OUTPUT
0.5V/div
MAX9675 toc34
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (CL = 30pF, AV = +1V/V)
INPUT
100mV/div
OUTPUT
50mV/div
MAX9675 toc35
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (CL = 30pF, AV = +2V/V)
INPUT
50mV/div
OUTPUT
50mV/div
MAX9675 toc36
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________
13
0
20
10
40
30
60
50
70
-50 0 25-25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
MAX9675 toc39
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ICC
IEE
IDD
Typical Operating Characteristics (continued)
(VCC = +5V and VEE = -5V, VDD = +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ωto AGND, and TA = +25°C, unless otherwise
noted.)
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-50 0-25 25 50 75 100
GAIN vs. TEMPERATURE
MAX9675 toc37
TEMPERATURE (°C)
NORMALIZED GAIN (dB)
AV = +2V/V
AV = +1V/V
1p 10n 1μ100p10p 1n 100n 10μ100μ
MAX9675 toc38
10n
10μ
1μ
100n
100μ
1m
10m
100m
10
1
RESET DELAY (s)
CRESET (F)
RESET DELAY vs. RESET CAPACITANCE
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23 IN4–IN15 Buffered Analog Inputs
2, 4, 6, 8, 10, 12, 14, 16,
45, 46, 82, 83, 84, 91,
93, 95, 97
AGND Analog Ground
18, 20, 22, 24 A3–A0 Address Programming Inputs. Connect to DGND or VDD to select the address for
Individual Output Address Mode (see Table 3).
25, 47, 51, 55, 59, 63,
67, 71, 75, 81 VCC Positive Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND. Connect
a single 10µF capacitor from one VCC pin to AGND.
26, 27, 38–44, 76, 77,
85–89, 99, 100 N.C. No Connection. Not internally connected. Connect to AGND.
28 DOUT
Serial-Data Output. In Complete Matrix Mode, data is clocked through the 96-bit
Matrix Control shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
29 DGND Digital Ground
30 AOUT Address Recognition Output. AOUT drives low after successful chip address
recognition.
31 SCLK Serial-Clock Input
32 CE Clock Enable Input. Drive low to enable the serial data interface.
33 MODE Serial Interface Mode Select Input. Drive high for Complete Matrix Mode (Mode 1)
or drive low for Individual Output Address Mode (Mode 0).
34 RESET
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All
matrix settings are set to power up defaults and all analog outputs are disabled.
Additional power-on-reset delay may be set by connecting a small capacitor from
RESET to DGND.
35 UPDATE Update Input. Drive UPDATE low to transfer data from mode registers to the switch
matrix.
36 DIN Serial-Data Input. Data is clocked in on the falling edge of SCLK.
37 VDD Digital Logic Supply. Bypass VDD with a 0.1µF capacitor to DGND.
48, 50, 52, 54, 56, 58,
60, 62, 64, 66, 68, 70,
72, 74, 78, 80
OUT15–OUT0
Buffered Analog Outputs. Gain is individually programmable for AV = +1V/V or AV
= +2V/V through the serial interface. Outputs may be individually disabled (high
impedance). On power-up, or assertion of RESET, all outputs are disabled.
49, 53, 57, 61, 65, 69,
73, 79, 98 VEE Negative Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND.
Connect a single 10µF capacitor from one VEE pin to AGND.
90, 92, 94, 96 IN0–IN3 Buffered Analog Inputs
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 15
Detailed Description
The MAX9675 is a highly integrated 16 ✕16 nonblock-
ing video crosspoint switch matrix. All inputs and out-
puts are buffered, with all outputs able to drive
standard 75Ωreverse-terminated video loads.
A 3-wire interface programs the switch matrix and ini-
tializes with a single update signal. The unique serial
interface operates in one of two modes: Complete
Matrix Mode (Mode 1) or Individual Output Address
Mode (Mode 0).
In the
Functional Diagram,
the signal path of the
MAX9675 is from the inputs (IN0–IN15), through the
switching matrix, buffered by the output amplifiers, and
presented at the output terminals (OUT0–OUT15). The
other functional blocks are the serial interface and con-
trol logic. Each of the functional blocks is described in
detail below.
Analog Outputs
The MAX9675 outputs are high-speed voltage feedback
amplifiers capable of driving 150Ω(75Ωback-terminat-
ed) loads. The gain, AV= +1V/V or +2V/V, is selectable
through programming bit 4 of the serial control word.
Amplifier compensation is automatically optimized to
maximize the bandwidth for each gain selection. Each
output can be individually enabled and disabled through
bit 5 of the serial control word. When disabled, the out-
put is high impedance, presenting typically a 4kΩload,
and 3pF output capacitance, allowing multiple outputs to
be connected together in building large arrays. On
power-up (or asynchronous RESET), all outputs are ini-
tialized in the disabled state to avoid output conflicts in
large-array configurations. The programming and opera-
tion of the MAX9675 is output referred. Outputs are con-
figured individually to connect to any one of the 16
analog inputs, programmed to the desired gain (AV=
+1V/V or +2V/V), or disabled in a high-impedance state.
Analog Inputs
The MAX9675 offers 16 analog input channels. Each
input is buffered before the crosspoint switch matrix,
allowing one input to cross-connect to up to 16 outputs.
The input buffers are voltage feedback amplifiers with
high-input impedance and low-input bias current. This
allows the use of very simple input clamp circuits.
MAX9675
16 x 16
SWITCH MATRIX
POWER-ON
RESET
SERIAL
INTERFACE
THERMAL
SHUTDOWN
DECODE LOGIC
DISABLE ALL OUTPUTS
LATCHES
256 16
16
MATRIX REGISTER
96 BITS
UPDATE REGISTER
16 BITS
ENABLE/DISABLE
AV*
AV*
AV*
AV*
*AV = +1V/V OR +2V/V
A0–A3 MODE
IN0
IN1
IN2
IN15
DIN
SCLK
UPDATE
CE
RESET
OUT0
OUT1
OUT2
OUT15
VCC
VEE
DGND
VDD
DOUT
AOUT
AGND
Functional Diagram
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
16 ______________________________________________________________________________________
Switch Matrix
The MAX9675 has 256 individual T-switches making a
16 x 16 switch matrix. The switching matrix is 100%
nonblocking, which means that any input may be rout-
ed to any output. The switch matrix programming is
output referred. Each output may be connected to any
one of the 16 analog inputs. Any one input can be rout-
ed to all 16 outputs with no signal degradation.
Digital Interface
The digital interface consists of the following pins: DIN,
DOUT, SCLK, AOUT, UPDATE, CE, A3–A0, MODE, and
RESET. DIN is the serial-data input; DOUT is the serial-
data output. SCLK is the serial-data clock that clocks
data into the Data Input registers (Figure 2). Data at
DIN is loaded at each falling edge of SCLK. DOUT is
the data shifted out of the 96-bit Complete Matrix Mode
(Mode = 1). DIN passes directly to DOUT when in
Individual Output Address Mode (Mode = 0).
The falling edge of UPDATE latches the data and pro-
grams the matrix. When using Individual Output
Address Mode, the address recognition output AOUT
drives low when control word bits D13 to D10 match
the address programming inputs (A3–A0) and UPDATE
is low. Table 1 is the operation truth table.
Programming the Matrix
The MAX9675 offers two programming modes:
Individual Output Address Mode and Complete Matrix
Mode. These two distinct programming modes are
selected by toggling a single MODE pin high or low.
Both modes operate with the same physical board lay-
out. This flexibility allows initial programming of the IC
by daisy-chaining and sending one long data word
while still being able to address immediately and
update individual outputs in the matrix.
Individual Output Address Mode (MODE = 0)
Drive MODE to logic-low to select mode 0. Individual
outputs are programmed through the serial interface
CE UPDATE SCLK DIN DOUT MODE AOUT RESET OPERATION/COMMENTS
1 X X X X X X 1 No change in logic.
01↓DiDi-96 11 1
Data at DIN is clocked on the negative
edge of the SCLK into the 96-bit
Complete Matrix Mode register. DOUT
supplies original data in 96 SCLK
pulses later.
00XXX111
Data in the serial 96-bit Complete
Matrix Mode register is transferred
into parallel latches that control the
switching matrix.
01↓DiDi01 1
Data at DIN is routed to the Individual
Output Address Mode shift register.
DIN is also connected directly to
DOUT so that all devices on the serial
bus may be addressed in parallel.
00XD
iDi00 1
The 4-bit chip address A3 to A0 is
compared to D13 to D10. If equal, the
remaining 10 bits in the Individual
Output Address Mode register are
decoded, allowing reprogramming for
a single output. AOUT signals a
successful individual matrix update.
X X XXXXX 0
Asynchronous reset. All outputs are
disabled. Other logic remains
unchanged.
Table 1. Operation Truth Table
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 17
with a single 16-bit control word. The control word con-
sists of two don’t care MSBs, the chip address bits, out-
put address bits, an output enable/disable bit, an
output gain-set bit, and input address bits (Tables 2
through 6, and Figure 2).
In mode 0, data at DIN passes directly to DOUT
through the data routing gate (Figure 3). In this configu-
ration, the 16-bit control word is simultaneously sent to
all chips in an array of up to 16 addresses.
Complete Matrix Mode (MODE = 1)
Drive MODE to logic-high to select mode 1. A single
96-bit control word consisting of sixteen 6-bit control
words programs all outputs. The 96-bit control word’s
first 6-bit control word (MSBs) programs output 15, and
the last 6-bit control word (LSBs) programs output 0
(Table 7 and Figures 4 and 5). Data clocked into the
96-bit Complete Matrix Mode register is latched on the
falling edge of UPDATE, and the outputs are immedi-
ately updated.
Initialization String
The Complete Matrix Mode (Mode = 1) is convenient to
use to program the matrix at power-up. In a large
matrix consisting of many MAX9675 devices, all the
devices can be programmed by sending a single bit
stream equal to n x 96 bits, where n is the number of
MAX9675 devices on the bus. The first 96-bit data word
programs the last MAX9675 in line (see the
Matrix
Programming
section)
.
BIT NAME FUNCTION
0
(LSB) Input Address 0 LSB of input channel
select address
1 Input Address 1
2 Input Address 2
3 Input Address 3 MSB of input channel
select address
4 Gain Set
Gain Select for output
buffer, 0 = gain of +1V/V,
1 = gain of +2V/V
5 Output Enable Enable bit for output,
0 = disable, 1 = enable
6 Output Address B0 LSB of output buffer
address
7 Output Address B1
8 Output Address B2
9 Output Address B3 MSB of output buffer
address
10 IC Address A0 LSB of selected chip
address
11 IC Address A1
12 IC Address A2
13 IC Address A3 MSB of selected chip
address
14 X Don’t care
15
(MSB) X Don’t care
Table 2. 16-Bit Serial Control Word Bit
Assignments (Mode 0: Individual Output
Address Mode)
IC ADDRESS BIT ADDRESS
A3
(MSB) A2 A1
A0
(LSB)
CHIP
ADDRESS
(HEX)
CHIP
ADDRESS
(DECIMAL)
0 0 0 0 0h 0
0 0 0 1 1h 1
0 0 1 0 2h 2
0 0 1 1 3h 3
0 1 0 0 4h 4
0 1 0 1 5h 5
0 1 1 0 6h 6
0 1 1 1 7h 7
1 0 0 0 8h 8
1 0 0 1 9h 9
1 0 1 0 Ah 10
1 0 1 1 Bh 11
1 1 0 0 Ch 12
1 1 0 1 Dh 13
1 1 1 0 Eh 14
1 1 1 1 Fh 15
Table 3. Chip Address Programming for
16-Bit Control Word (Mode 0: Individual
Output Address Mode)
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
18 ______________________________________________________________________________________
IC ADDRESS = 5 OUTPUT ADDRESS = 3 OUTPUT (i) ENABLED, AV = +1V/V,
CONNECTED TO INPUT 12
EXAMPLE OF 16-BIT
SERIAL CONTROL WORD FOR OUTPUT
CONTROL IN INDIVIDUAL OUTPUT ADDRESS MODE
16-BIT INDIVIDUAL OUTPUT ADDRESS MODE:
FIRST 2 BITS ARE DON'T CARE BITS, LAST 14 BITS CLOCKED INTO DIN WHEN MODE = 0 CREATE ADDRESS WORD;
IC ADDRESS A3–A0 IS COMPARED TO DIN13–DIN10 WHEN UPDATE IS LOW; IF
EQUAL, ADDRESSED OUTPUT IS UPDATED.
DON'T CARE X
DON'T CARE X
OUTPUT ADDRESS B3
OUTPUT ADDRESS B2
OUTPUT ADDRESS B1
OUTPUT ADDRESS B0
OUTPUT ENABLED
GAIN SET = +1V/V
INPUT ADDRESS 3 (MSB) = 1
INPUT ADDRESS 0 (LSB) = 0
INPUT ADDRESS 2 = 1
INPUT ADDRESS 1 = 0
IC ADDRESS A3
IC ADDRESS A2
IC ADDRESS A1
IC ADDRESS A0
UPDATE
MODE
SCLK
DIN
tSuMd tHdMd
Figure 2. Mode 0: Individual Output Address Mode Timing and Programming Example
PIN ADDRESS
A3 A2 A1 A0
C H IP
A D DR ESS
( H EX)
C H IP
A D DR ESS
( D EC IM AL )
D GND D GND D GND D GND 0h 0
D GND D GND D GND V
D D 1h 1
D GND D GND V
D D D GND 2h 2
D GND D GND V
D D V
D D 3h 3
D GND V
D D D GND D GND 4h 4
D GND V
D D D GND V
D D 5h 5
D GND V
D D V
D D D GND 6h 6
D GND V
D D V
D D V
D D 7h 7
V
D D D GND D GND D GND 8h 8
V
D D D GND D GND V
D D 9h 9
V
D D D GND V
D D D GND Ah 10
V
D D D GND V
D D V
D D Bh 11
V
D D V
D D D GND D GND Ch 12
V
D D V
D D D GND V
D D Dh 13
V
D D V
D D V
D D D GND Eh 14
V
D D V
D D V
D D V
D D Fh 15
Table 4. Chip Address A3–A0 Pin
Programming
OUTPUT ADDRESS BIT
B3
(MSB) B2 B1 B0
(LSB)
SELECTED
OUTPUT
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Table 5. Output Selection Programming
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 19
SCLK A0–A3
CHIP ADDRESS
4
4
AS
MODE
MODE
MODE
AOUT
DOUT
B
DATA
ROUTING
GATE
16-BIT INDIVIDUAL OUTPUT ADDRESS
MODE REGISTER
96-BIT COMPLETE MATRIX MODE REGISTER
96-BIT PARALLEL LATCH
SWITCH DECODE
SWITCH MATRIX OUTPUT ENABLE
OUTPUT ADDRESS DECODE
MODE
CE
SCLK
MODE
DIN
CE 10
10
1
7
7
96
96
96
UPDATE
EN
256 16
Figure 3. Serial Interface Block Diagram
INPUT ADDRESS BIT
B3
(MSB) B2 B1 B0
(LSB)
SELECTED
INPUT
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Table 6. Input Selection Programming
BIT NAME FUNCTION
5 (MSB) Output
Enable
Enable bit for output,
0 = disable, 1 = enable
4Gain
Set
Gain Select for output buffer, 0 =
gain of +1V/V, 1 = gain of +2V/V
3Input
Address 3
MSB of input channel select
address
2Input
Address 2
1Input
Address 1
0 (LSB) Input
Address 0
LSB of input channel select
address
Table 7. 6-Bit Serial Control Word Bit
Assignments (Mode 1: Complete Matrix
Mode)
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
20 ______________________________________________________________________________________
0
0
OUT0OUT1OUT2
UPDATE 1
MODE 1
MOST-SIGNIFICANT OUTPUT BUFFER CONTROL BITS ARE SHIFTED IN FIRST, I.E., OUT15, THEN OUT14, ETC.
LAST 6 BITS SHIFTED IN PRIOR TO UPDATE NEGATIVE EDGE PROGRAM OUT0.
DIN
6-BIT CONTROL WORD
Figure 5. Mode 1: Complete Matrix Mode Programming
SCLK
tMnLCk
tSuDi tHdDi
tPdDo
tSuHUd tMnLUd
NEXT CONTROL WORD
tMnHCk
UPDATE
DOUT
EXAMPLE OF 6-BIT
SERIAL CONTROL
WORD FOR OUTPUT
CONTROL
16 x 16 CROSSPOINT = 6-BIT
CONTROL WORD
SCLK
DIN
OUTPUT (i) ENABLED, AV = +1V/V,
CONNECTED TO INPUT 14
OUTPUT ENABLED
INPUT ADDRESS 3 (MSB) = 1
INPUT ADDRESS 2 = 1
INPUT ADDRESS 1 = 1
INPUT ADDRESS 0 (LSB) = 0
GAIN SET = +1V/V
DIN
Figure 4. 6-Bit Control Word and Programming Example (Mode 1: Complete Matrix Mode Programming)
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 21
RESET
The MAX9675 features an asynchronous bidirectional
RESET with an internal 20kΩpullup resistor to VDD.
When RESET is pulled low, either by internal circuitry,
or driven externally, the analog output buffers are
latched into a high-impedance state. After RESET is
released, the output buffers remain disabled. The out-
puts may be enabled by sending a new 96-bit data
word or a 16-bit individual output address word. A reset
is initiated from any of three sources. RESET can be
driven low by external circuitry to initiate a reset, or
RESET can be pulled low by internal circuitry during
power-up (power-on reset) or thermal shutdown.
Since driving RESET low only clears the output buffer
enable bit in the matrix control latches, RESET can be
used to disable all outputs simultaneously. If no new
data has been loaded into the 96-bit complete matrix
mode register, a single UPDATE restores the previous
matrix control settings.
Power-On Reset
The power-on reset ensures all output buffers are in a
disabled state when power is initially applied. A VDD
voltage comparator generates the power-on reset.
When the voltage at VDD is less than 2.5V, the power-
on-reset comparator pulls RESET low through internal
circuitry. As the digital supply voltage ramps up cross-
ing 2.5V, the MAX9675 holds RESET low for 40ns (typ).
Connecting a small capacitor from RESET to DGND
extends the power-on-reset delay. See the RESET
Delay vs. RESET Capacitance graph in the
Typical
Operating Characteristics.
Thermal Shutdown
The MAX9675 features thermal shutdown protection
with temperature hysteresis. When the die temperature
exceeds +150°C, the MAX9675 pulls RESET low, dis-
abling the output buffers. When the die cools by 20°C,
the RESET pulldown is deasserted, and output buffers
remain disabled until the device is programmed again.
Applications Information
Building Large Video-Switching Systems
The MAX9675 can be easily used to create larger
switching matrices. The number of ICs required to
implement the matrix is a function of the number of
input channels, the number of outputs required, and
whether the array needs to be nonblocking. The most
straightforward technique for implementing nonblock-
ing matrices is to arrange the building blocks in a grid.
The inputs connect to each vertical bank of devices in
parallel with the other banks. The outputs of each build-
ing block in a vertical column connect together in a
wired-OR configuration. Figure 6 shows a 128-input,
32-output, nonblocking array using the MAX9675 16 x
16 crosspoint devices.
The wired-OR connection of the outputs shown in the
diagram is possible because the outputs of the IC
devices can be placed in a disabled or high-imped-
ance output state. This disable state of the output
buffers is designed for a maximum impedance vs. fre-
quency while maintaining a low-output capacitance.
These characteristics minimize the adverse loading
effects from the disabled outputs. Larger arrays are
constructed by extending this connection technique to
more devices.
Driving a Capacitive Load
Figure 6 shows an implementation requiring many out-
puts to be wired together. This creates a situation
where each output buffer sees not only the normal load
impedance, but also the disabled impedance of all the
other outputs. This impedance has a resistive and a
capacitive component. The resistive components
reduce the total effective load for the driving output.
Total capacitance is the sum of the capacitance of all
the disabled outputs and is a function of the size of the
matrix. Also, as the size of the matrix increases, the
length of the PCB traces increases, adding more
capacitance. The output buffers have been designed to
drive more than 30pF of capacitance while still main-
taining a good AC response. Depending on the size of
the array, the capacitance seen by the output can
exceed this amount. There are several ways to improve
the situation. The first is to use more building-block
crosspoint devices to reduce the number of outputs
that need to be wired together (Figure 7).
In Figure 7, the additional devices are placed in a sec-
ond bank to multiplex the signals. This reduces the
number of wired-OR connections. Another solution is to
put a small resistor in series with the output before the
capacitive load to limit excessive ringing and oscilla-
tions. Figure 8 shows the graph of the Optimal Isolation
Resistor vs. Capacitive Load. A lowpass filter is created
from the series resistor and parasitic capacitance to
ground. A single R-C does not affect the performance
at video frequencies, but in a very large system there
may be many R-Cs cascaded in series. The cumulative
effect is a slight rolling off of the high frequencies caus-
ing a "softening" of the picture. There are two solutions
to achieve higher performance. One way is to design
the PCB traces associated with the outputs such that
they exhibit some inductance. By routing the traces in a
repeating "S" configuration, the traces that are nearest
each other exhibit a mutual inductance increasing the
total inductance. This series inductance causes the
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
22 ______________________________________________________________________________________
amplitude response to increase or peak at higher fre-
quencies, offsetting the rolloff from the parasitic capaci-
tance. Another solution is to add a small-value inductor
to the output.
Crosstalk Signal and Board Routing Issues
Improper signal routing causes performance problems
such as crosstalk. The MAX9675 has a typical crosstalk
rejection of -62dB at 6MHz. A bad PCB layout
degrades the crosstalk rejection by 20dB or more. To
achieve the best crosstalk performance:
1) Place ground isolation between long critical sig-
nal PCB trace runs. These traces act as a shield to
potential interfering signals. Crosstalk can be
degraded by parallel traces as well as directly
above and below on adjoining PCB layers.
2) Maintain controlled-impedance traces. Design as
many of the PCB traces as possible to be 75Ωtrans-
mission lines. This lowers the impedance of the
traces, reducing a potential source of crosstalk.
More power is dissipated due to the output buffer
driving a lower impedance.
3) Minimize ground-current interaction by using a
good ground plane strategy.
In addition to crosstalk, another key issue of concern is
isolation. Isolation is the rejection of undesirable feed-
through from input to output with the output disabled.
The MAX9675 achieves a -110dB isolation at 6MHz by
selecting the pinout configuration such that the inputs
and outputs are on opposite sides of the package.
Coupling through the power supply is a function of the
quality and location of the supply bypassing. Use
appropriate low-impedance components and locate
them as close as possible to the IC. Avoid routing the
inputs near the outputs.
Power-Supply Bypassing
The MAX9675 operates from a ±5V supply. For dual-
supply operation, bypass all supply pins to ground with
0.1µF capacitors.
Figure 7. 64 x 16 Nonblocking Matrix with Reduced Capacitive
Loading
IN (0–15)
IN (16–31)
IN (32–47)
IN (48–63)
OUTPUTS (0–15) OUTPUTS (16–32)
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
IN (64–79)
IN (80–95)
IN (96–111)
IN (112–127)
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
Figure 6. 128 x 32 Nonblocking Matrix Using 16 x 16 Crosspoint Devices
IN (0–15)
IN (16–31)
IN (32–47)
IN (48–63)
OUTPUTS (0–15)
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
16
IN
16
OUT
MAX9675
MAX9675
MAX9675
MAX9675
MAX9675
16
IN
16
OUT
MAX9675
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 23
Driving a PCB Interconnect or a Cable
(AV= +1V/V or +2V/V)
The MAX9675 output buffers can be programmed to
either AV= +1V/V or +2V/V. The +1V/V configuration is
typically used when driving a short-length (less than
3cm), high-impedance “local” PCB trace. To drive a
cable or a 75Ωtransmission line trace, program the
gain of the output buffer to +2V/V and place a 75Ω
resistor in series with the output. The series termination
resistor and the 75Ωload impedance act as a voltage-
divider that divides the video signal in half. Set the gain
to +2V/V to transmit a standard 1V video signal down a
cable. The series 75Ωresistor is called the back-match,
reverse termination, or series termination. This 75Ω
resistor reduces reflections, and provides isolation,
increasing the output-capacitive-driving capability.
Matrix Programming
The MAX9675’s unique digital interface simplifies pro-
gramming multiple MAX9675 devices in an array.
Multiple devices are connected with DOUT of the first
device connecting to DIN of the second device, and so
on (Figure 9). Two distinct programming modes, indi-
vidual output address mode (MODE = 0) and complete
matrix mode (MODE = 1), are selected by toggling a
single MODE control pin high or low. Both modes oper-
ate with the same physical board layout. This allows ini-
tial programming of the IC by daisy-chaining and
sending one long data word while still being able to
address immediately and update individual locations in
the matrix.
Individual Output Address Mode (Mode 0)
In Individual Output Address Mode, the devices are
connected in a serial bus configuration, with the data
routing gate (Figure 3) connecting DIN to DOUT, mak-
ing each device a virtual node on the serial bus. A sin-
gle 16-bit control word is sent to all devices
simultaneously. Only the device with the corresponding
chip address responds to the programming word, and
updates its output. In this mode, the chip address is set
through hardware pin strapping of A3–A0. The host
then communicates with the device by sending a 16-bit
word consisting of 2 don’t care MSB bits, 4 chip
address bits, and 10 bits of data to make the word
exactly 2 bytes in length. The 10 data bits are broken
down into 4 bits to select the output to be programmed;
1 bit to set the output enable; 1 bit to set gain; and 4
bits to select the input to be connected to that output.
In this method, the matrix is programmed one output at
a time.
Complete Matrix Mode (Mode 1)
In Complete Matrix Mode, the devices are connected in
a daisy-chain fashion where n x 96 bits are sent to pro-
gram the entire matrix, and where n = the number of
MAX9675 devices connected in series. This long data
word is structured such that the first bit is the LSB of
the last device in the chain and the last data bit is the
MSB of the first device in the chain. The total length of
the data word is equal to the number of crosspoint
devices to be programmed in series times 96 bits per
crosspoint device. This programming method is most
often used at startup to initially configure the switching
matrix.
0
10
5
20
15
25
30
0 500
OPTIMAL ISOLATION RESISTANCE
vs. CAPACITIVE LOAD
CAPACITIVE LOAD (pF)
ISOLATION RESISTANCE (Ω)
200100 300 400
Figure 8. Optimal Isolation Resistor vs. Capacitive Load
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
24 ______________________________________________________________________________________
HOST
CONTROLLER
DIN
SCLK
CE
MODE
UPDATE
DOUT
CHIP ADDRESS = 0 CHIP ADDRESS = 1
VIRTUAL SERIAL BUS (MODE 0: INDIVIDUAL OUTPUT ADDRESS MODE)
CHIP ADDRESS = 2
A3
A2
A1
A0
MAX9675
DIN
SCLK
CE
MODE
UPDATE
DOUT
A3
VDD
A2
A1
A0
MAX9675
DIN
SCLK
CE
MODE
UPDATE
DOUT NEXT DEVICE
A3
A2
A1
A0
MAX9675
VDD
Figure 9. Matrix Mode Programming
Chip Information
TRANSISTOR COUNT: 24,467
PROCESS: BiCMOS
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
______________________________________________________________________________________ 25
OP VIEW
MAX9675
TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IN4
AGND
IN5
AGND
IN6
AGND
IN7
AGND
IN8
AGND
IN9
AGND
IN10
AGND
IN11
AGND
IN12
A3
IN13
A2
IN14
A1
IN15
A0
VCC
VCC
OUT2
VEE
OUT3
VCC
OUT4
VEE
OUT5
VCC
OUT6
VEE
OUT7
VCC
OUT8
VEE
OUT9
VCC
OUT10
VEE
OUT11
VCC
OUT12
VEE
OUT13
VCC
26
27
28
29
30
N.C.
N.C.
DOUT
DGND
AOUT
SCLK
CE
MODE
RESET
UPDATE
DIN
VDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AGND
AGND
VCC
OUT15
VEE
OUT14
N.C.
N.C.
VEE
AGND
IN3
AGND
IN2
AGND
IN1
AGND
IN0
N.C.
N.C.
N.C.
N.C.
N.C.
AGND
AGND
AGND
VCC
OUT0
VEE
OUT1
N.C.
N.C.
+
Pin Configuration
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
26 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
100L,TQFP.EPS
PACKAGE OUTLINE
21-0085 2
1
B
100L TQFP, 14x14x1.0mm
MAX9675
110MHz, 16 x 16 Video Crosspoint
Switch with Programmable Gain
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
27
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
PACKAGE OUTLINE,
21-0085
2
2
B
100L TQFP, 14x14x1.0mm
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
100 TQFP C100-1 21-0085