MAX105ECS+T - Maxim Integrated Products, Inc.

General Description

The MAX105 is a dual, 6-bit, analog-to-digital converter

(ADC) designed to allow fast and precise digitizing of

in-phase (I) and quadrature (Q) baseband signals. The

MAX105 converts the analog signals of both I and Q

components to digital outputs at 800Msps while achiev-

ing a signal-to-noise ratio (SNR) of typically 37dB with

an input frequency of 200MHz, and an integral nonlin-

earity (INL) and differential nonlinearity (DNL) of ±0.25

LSB. The MAX105 analog input preamplifiers feature a

400MHz, -0.5dB, and a 1.5GHz, -3dB analog input

bandwidth. Matching channel-to-channel performance

is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees

phase. Dynamic performance is 36.4dB signal-to-noise

plus distortion (SINAD) with a 200MHz analog input sig-

nal and a sampling speed of 800MHz. A fully differen-

tial comparator design and encoding circuits reduce

out-of-sequence errors, and ensure excellent

metastable performance of only one error per 1016 clock

cycles.

In addition, the MAX105 provides LVDS digital outputs

with an internal 6:12 demultiplexer that reduces the out-

put data rate to one-half the sample clock rate. Data is

output in two’s complement format. The MAX105 oper-

ates from a +5V analog supply and the LVDS output

ports operate at +3.3V. The data converter’s typical

power dissipation is 2.6W. The device is packaged in

an 80-pin, TQFP package with exposed paddle, and is

specified for the extended (-40°C to +85°C) tempera-

ture range. For a lower-speed, 400Msps version of the

MAX105, please refer to the MAX107 data sheet.

Applications

VSAT Receivers

WLANs

Test Instrumentation

Communications Systems

Features

♦Two Matched 6-Bit, 800Msps ADCs

♦Excellent Dynamic Performance

36.4dB SINAD at fIN ≈200MHz and

fCLK ≈800MHz

♦Typical INL and DNL: ±0.25LSB

♦Channel-to-Channel Phase Matching: ±0.2°

♦Channel-to-Channel Gain Matching: ±0.04dB

♦6:12 Demultiplexer reduces the Data Rates to

400MHz

♦Low Error Rate: 1016 Metastable States at

800Msps

♦LVDS Digital Outputs in Two’s Complement

Format

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

________________________________________________________________ Maxim Integrated Products 1

REF

PRIMARY

PORT

AUXILIARY

PORT

PRIMARY

PORT

AUXILIARY

PORT

I ADC

Q ADC

MAX107

Block Diagram

19-2006; Rev 0; 5/01

Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX105ECS -40°C to +85°C 80-Pin TQFP-EP

Pin Configuration appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V

OVCCI and OVCCQ to OGND...................................-0.3V to +4V

AGND to OGND ................................................... -0.3V to +0.3V

P0I± to P5I± and A0I± to A5I±

DREADY+, DREADY- to OGNDI .............-0.3V to OVCCI+0.3V

P0Q± to P5Q±, A0Q± to A5Q±

DOR+ and DOR- to OGNDQ ................-0.3V to OVCCQ+0.3V

REF to AGNDR...........................................-0.3V to AVCCR+0.3V

Differential Voltage Between INI+ and INI- ....................-2V, +2V

Differential Voltage Between INQ+ and INQ-.................-2V, +2V

Differential Voltage Between CLK+ and CLK- ...............-2V, +2V

Maximum Current Into Any Pin ...........................................50mA

Continuous Power Dissipation (TA= +70°C)

80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W

Operating Temperature Range

MAX105ECS .....................................................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead temperature (soldering, 10s) ..................................+300°C

ELECTRICAL CHARACTERISTICS

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ

= 0, fCLK = 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMIN to TMAX, unless

otherwise noted. Typical values are at TA= +25°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution RES 6 Bits

Integral Nonlinearity (Note 1) INL -1 ±0.2 1 LSB

Differential Nonlinearity

(Note 1) DNL No missing codes guaranteed -1 ±0.25 1 LSB

Offset Voltage VOS (Note 2) -1 ±0.25 1 LSB

O ffset M atchi ng Betw een AD C s OM (Note 2) -0.5 ±0.1 0.5 LSB

ANALOG INPUTS (INI+, INI-, INQ+, INQ-)

Input Open-Circuit Voltage VAOC 2.4 2.5 2.6 V

Input Open-Circuit Voltage

Matching (VINI+ - VIN-) - (VINQ+ - VINQ-)±7.5 mV

Common Mode Input Voltage

Range (Note 3) VCM Signal + Offset w.r.t. AGND 1.85 3.05 V

Full-Scale Analog Input

Voltage Range (Note 4) VFSR 0.76 0.8 0.84 Vp-p

Input Resistance RIN 1.7 2 kΩ

Input Capacitance CIN 1.5 pF

Input Resistance Temperature

Coefficient TCRIN 150 ppm/°C

Full-Power Analog Input BW FPBW-0.5dB 400 MHz

REFERENCE OUTPUT

Reference Output Resistance RREF Referenced to AGNDR 5 Ω

Reference Output Voltage √REF ISOURCE = 500µA 2.45 2.50 2.55 V

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ

= 0, fCLK = 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMIN to TMAX, unless

otherwise noted. Typical values are at TA= +25°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUTS (CLK+, CLK-)

Clock Input Resistance RCLK CLK+ and CLK- to AGND 5 kΩ

Clock Input Resistance

Temperature Coefficient TCRCLK 150 ppm/°C

Minimum Clock Input

Amplitude 500 mV

LVDS OUTPUTS (P0I± TO P5I±, P0Q± TO P5Q±, A0I± TO A5I±, A0Q± TO A5Q±, DREADY+, DREADY-, DOR+, DOR-)

Differential Output Voltage VOD 247 400 mV

C hang e i n M ag ni tud e of V



Betw een “0” and “1” S tates ∆VOD  ±25 mV

Steady-State Common Mode

Output Voltage VOC

(

)

1.125 1.375 V

Change in Magnitude of VOC

Between “0” and “1” States ∆VOC  ±25 mV

Differential Output Resistance 80 160 Ω

Short output together 2.5

Output Current Short to OGNDI = OGNDQ 25 mA

DYNAMIC SPECIFICATION

Differential 5.4 5.8

fIN = 200.018MHz at

-0.5dB FS (Note 9) Single-ended 5.75

Effective Number of Bits

(Note 8) ENOB

fIN = 400.134MHz at

-0.5dB FS Differential 5.65

Bits

Differential 35 37

fIN = 200.018MHz at

-0.5dB FS (Note 9) Single-ended 36.7

Signal-to-Noise Ratio

(Notes 10, 11) SNR

fIN = 400.134MHz at

-0.5dB FS Differential 36.5

Differential -44.5 -41

fIN = 200.018MHz at

-0.5dB FS (Note 9) Single-ended -44.5

Total Harmonic Distortion

(Note 11) THD

fIN = 400.134MHz at

-0.5dB FS Differential -41

dBc

Differential 41 45

fIN = 200.018MHz at

-0.5dB FS (Note 9) Single-ended 45

Spurious-Free Dynamic Range SFDR

fIN = 400.134MHz at

-0.5dB FS Differential 41.5

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ

= 0, fCLK = 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMIN to TMAX, unless

otherwise noted. Typical values are at TA= +25°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential 34 36.4

fIN = 200.018MHz at

-0.5dB FS (Note 9) Single-ended 36.1

Signal-to-Noise Plus Distortion

Ratio SINAD fIN = 400.134MHz at

-0.5dB FS Differential 35.2

Two-Tone Intermodulation TTIMD fIN1 = 124.1660MHz, fIN2 = 126.1260MHz

at -7dBFS -52 dBc

Crosstalk Between ADCs XTLK fINI = 200.0180MHz, fINQ = 210.0140MHz

at -0.5dB FS -70 dB

Gain Match Between ADCs GM (Note 12) -0.3 ±0.04 +0.3 dB

Phase Match Between ADCs PM (Note 12) -2 ±0.2 +2 deg

Metastable Error Rate Less than 1 in 1016 Clock

Cycles

POWER REQUIREMENTS

Analog Supply Voltage AVCC_ AVCC = AVCCI = AVCCQ = AVCCR5 ±5% V

Digital Supply Voltage OVCC_ OVCC I = OVCC Q 3.3 ±10% V

Analog Supply Current ICC ICC = AICCR + AICCI + AICCQ + AICC 250 320 mA

Output Supply Current OICC OICC = OICC I + OICC Q 400 510 mA

Analog Power Dissipation PDISS 2.6 W

C om m on- M od e Rej ecti on Rati o CMRR VIN_+ = VIN_- = ±0.1V (Note 6) 40 60 dB

Power-Supply Rejection Ratio PSRR AVCC = AVCC I = AVCC Q = AVCC R =

+4.75V to +5.25V (Note 7) 40 57 dB

TIMING CHARACTERISTICS

Maximum Sample Rate fMAX 800 Msps

Clock Pulse Width Low tPWL 0.56 ns

Clock Pulse Width High tPWH 0.56 ns

Aperture Delay tAD 100 ps

Aperture Jitter tAJ 1.5 psRMS

CLK-to-DREADY Propagation

Delay tPD1 (Note 13) 1.5 ns

DREADY-to-DATA

Propagation Delay tPD2 (Notes 5, 13) 0 120 300 ps

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

_______________________________________________________________________________________ 5

Note 1: NL and DNL is measured using a sine-histogram method.

Note 2: Input offset is the voltage required to cause a transition between codes 0 and -1.

Note 3: Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input

voltage level does not matter.

Note 4: The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting

algorithm (e.g. FFT).

Note 5: Guaranteed by design and characterization.

Note 6: Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-

mode voltage expressed in dB.

Note 7: Measured with analog power supplies tied to the same potential.

Note 8: Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.

Note 9: The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.

Note 10: Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.

The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.

Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification.

Note 12: Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input

frequency of fIN = 200.0180 MHz.

Note 13: Measured with a differential probe, 1pF capacitance.

ELECTRICAL CHARACTERISTICS (continued)

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ

= 0, fCLK = 802.816MHz, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMIN to TMAX, unless

otherwise noted. Typical values are at TA= +25°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DREADY Duty Cycle (Notes 5, 13) 47 53 %

LVDS Output Rise-Time tRDATA 20% to 80% (Notes 5, 13) 200 500 ps

LVDS Output Fall-Time tFDATA 20% to 80% (Notes 5, 13) 200 500 ps

Any differential pair <65 ps

LVDS Differential Skew tSKEW1 Any tw o LV D S outp ut si g nal s excep t D RE AD Y <100 ps

DREADY Rise-Time tRDREADY 20% to 80% (Notes 5, 13) 200 500 ps

DREADY Fall-Time tFDREADY 20% to 80% (Notes 5, 13) 200 500 ps

Primary Port Pipeline Delay tPDP 5Clock

Cycles

Auxiliary Port Pipeline Delay tPDA 6Clock

Cycles

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

6 _______________________________________________________________________________________

Typical Operating Characteristics

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,

fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=

TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C)

-100

-70

-80

-90

-50

-60

-10

-20

-30

-40

0 20 40 60 80 100 120 140

8192-POINT FFT,

DIFFERENTIAL INPUT

MAX105 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB FS)

fIN = 125.146MHz

AIN = -0.5dB FS

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

08040 120 160 200

8192-POINT FFT,

DIFFERENTIAL INPUT

MAX105 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB FS)

fIN = 124.999MHz

AIN = -0.5dB FS

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0 14070 210 280 350 420

8192-POINT FFT,

DIFFERENTIAL INPUT

MAX105 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB FS)

fIN = 400.124MHz

AIN = -0.5dB FS

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0 16080 240 320 400

TWO-TONE IMD (8192-POINT RECORD),

DIFFERENTIAL INPUT

MAX105 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB FS)

fN1 = 124.166MHz

fIN2 = 126.126MHz

AIN = -7dB FS

fIN1

fIN2

10M 1G 10G

SINAD vs. ANALOG INPUT FREQUENCY,

DIFFERENTIAL INPUT

MAX105 toc06

ANALOG INPUT FREQUENCY (Hz)

AMPLITUDE (dB)

100M

-12dB FS

-6dB FS

-1dB FS

-20

-60

10M 1G 10G

THD vs. ANALOG INPUT FREQUENCY,

DIFFERENTIAL INPUT

-50

-55

-45

-40

-35

-30

-25

MAX105 toc07

ANALOG INPUT FREQUENCY (Hz)

AMPLITUDE (dB)

100M

-12dB FS

-1dB FS

-6dB FS

10M 10G1G100M

SFDR vs. ANALOG INPUT FREQUENCY,

DIFFERENTIAL INPUT

MAX105 toc08

ANALOG INPUT FREQUENCY (Hz)

AMPLITUDE (dB)

-12dB FS

-1dB FS

-6dB FS

-4

10M 10G1G100M

FULL-POWER INPUT BANDWIDTH

SINGLE-ENDED INPUT

-2

-3

-1

MAX105 toc09

ANALOG INPUT FREQUENCY (Hz)

GAIN (dB)

10M 1G 10G

SNR vs. ANALOG INPUT FREQUENCY,

DIFFERENTIAL INPUT

MAX105 toc05

ANALOG INPUT FREQUENCY (Hz)

AMPLITUDE (dB)

100M

-1dB FS

-6dB FS

-12dB FS

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

_______________________________________________________________________________________ 7

-50

-46

-38

-42

-34

-10 -8 -7 -6 -5-9 -4 -3 -2 -1 0

THD vs. ANALOG INPUT POWER,

DIFFERENTIAL INPUT

MAX105 toc12

ANALOG INPUT POWER (dB FS)

THD (dB)

fIN = 199.8535MHz

-40 10-15 35 60 85

SNR vs. TEMPERATURE

MAX105 toc14

TEMPERATURE (°C)

SNR (dB)

fIN = 199.8535MHz

-10 -8 -7 -6 -5-9 -4 -3 -2 -1 0

SNR vs. ANALOG INPUT POWER,

DIFFERENTIAL INPUT

MAX105 toc10

ANALOG INPUT POWER (dB FS)

SNR (dB)

fIN = 199.8535MHz

-10 -8 -7 -6 -5-9 -4 -3 -2 -1 0

SINAD vs. ANALOG INPUT POWER,

DIFFERENTIAL INPUT

MAX105 toc11

ANALOG INPUT POWER (dB FS)

SINAD (dB)

fIN = 199.8535MHz

-10 -6-7-9 -8 -5 -4 -3 -2 -1 0

SFDR vs. ANALOG INPUT POWER,

DIFFERENTIAL INPUT

MAX105 toc13

ANALOG INPUT POWER (dB FS)

SFDR (dB)

fIN = 199.8535MHz

-40 10-15 35 60 85

SINAD vs. TEMPERATURE

MAX105 toc15

TEMPERATURE (°C)

SINAD (dB)

fIN = 199.8535MHz

-38

-42

-46

-50

-54

-40 10-15 35 60 85

THD vs. TEMPERATURE

MAX toc16

TEMPERATURE (°C)

THD (dB)

fIN = 199.8535MHz

-40 10-15 35 60 85

SFDR vs. TEMPERATURE

MAX105 toc17

TEMPERATURE (°C)

SFDR (dB)

fIN = 199.8535MHz

400 600500 700 800 900

SNR vs. CLOCK FREQUENCY,

DIFFERENTIAL INPUT (-1dB FS)

MAX105 toc18

CLOCK FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 202.346MHz

Typical Operating Characteristics (continued)

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,

fCLK = 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=

TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C)

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

8 _______________________________________________________________________________________

400 600500 700 800 900

SINAD vs. CLOCK FREQUENCY,

DIFFERENTIAL INPUT (-1dB FS)

MAX105 toc19

CLOCK FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 202.346MHz

-55

-52

-46

-49

-43

-40

400 600500 700 800 900

THD vs. CLOCK FREQUENCY,

DIFFERENTIAL INPUT (-1dB FS)

MAX105 toc20

CLOCK FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 202.346MHz

5.5

5.6

5.8

5.7

5.9

6.0

4.5 4.94.7 5.1 5.3 5.5

ENOB vs. ANALOG SUPPLY VOLTAGE,

DIFFERENTIAL INPUT (-1dB FS)

MAX105 toc21

ANALOG SUPPLY VOLTAGE (V)

ENOB (Bits)

fIN = 202.0761MHz

4.5 4.94.7 5.1 5.3 5.5

SFDR vs. ANALOG SUPPLY VOLTAGE,

DIFFERENTIAL INPUT (-1dB FS)

MAX105 toc22

ANALOG SUPPLY VOLTAGE (V)

SFDR (dB)

fIN = 202.0761MHz

-0.30

-0.20

-0.10

0.10

0.20

0.30

0168 243240485664

INL vs. DIGITAL OUTPUT CODE

MAX105 toc23

DIGITAL OUTPUT CODE

INL (LSB)

-0.40

-0.20

0.20

0.40

0 1632488 24405664

DNL vs. DIGITAL OUTPUT CODE

MAX105 toc24

DIGITAL OUTPUT CODE

DNL (LSB)

2.490

2.494

2.502

2.498

2.506

2.510

4.5 4.94.7 5.1 5.3 5.5

REFERENCE VOLTAGE vs. ANALOG

SUPPLY VOLTAGE

MAX toc25

ANALOG SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

200

220

260

240

280

300

4.5 4.94.7 5.1 5.3 5.5

ANALOG SUPPLY CURRENT vs.

ANALOG SUPPLY VOLTAGE

MAX105 toc26

ANALOG SUPPLY VOLTAGE (V)

ANALOG SUPPLY CURRENT (mA)

200

220

260

240

280

300

-40 10-15 35 60 85

ANALOG SUPPLY CURRENT vs.

TEMPERATURE

MAX105 toc27

TEMPERATURE (°C)

ANALOG SUPPLY CURRENT (mA)

Typical Operating Characteristics (continued)

(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,

fCLK = 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=

TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C)

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

_______________________________________________________________________________________ 9

PIN NAME FUNCTION

1, 20 T.P. Test Point. Do not connect.

2 REF Reference Output

3AV

CCRAnalog Reference Supply. Supply voltage for the internal bandgap reference. Bypass to AGNDR

with 0.01µF in parallel with 47pF for proper operation.

4 AGNDR Reference, Analog Ground. Connect to AGND for proper operation.

5, 8 AGNDI I-Channel, Analog Ground. Connect to AGND for proper operation.

6 INI- I-Channel, Differential Input. Negative terminal.

7 INI+ I Channel, Differential Input. Positive terminal.

9AV

CCII-Channel, Analog Supply. Supplies I-channel common-mode buffer, pre-amplifier and quantizer.

Bypass to AGNDI with 0.01µF in parallel with 47pF for proper operation.

10 CLK+ Sampling Clock Input

11 CLK- Complementary Sampling Clock Input

12 AVCCQQ-Channel, Analog Supply. Supplies Q-channel common-mode buffer, pre-amplifier and quantizer.

Bypass to AGNDQ with 0.01µF in parallel with 47pF for proper operation.

13, 16 AGNDQ Q-Channel, Analog Ground. Connect to AGND for proper operation.

14 INQ+ Q-Channel, Differential Input. Positive terminal.

15 INQ- Q-Channel, Differential Input. Negative terminal.

17, 18 AGND Analog Ground

19 AVCC Analog Supply. Bypass to AGND with 0.01µF in parallel with 47pF for proper operation.

21 A5Q+ Auxiliary Output Data Bit 5 (MSB), Q-Channel

22 A5Q- Complementary Auxiliary Output Data Bit 5 (MSB), Q-Channel

23 P5Q+ Primary Output Data Bit 5 (MSB), Q-Channel

24 P5Q- Complementary Primary Output Data Bit 5 (MSB), Q-Channel

25 A4Q+ Auxiliary Output Data Bit 4, Q-Channel

26 A4Q- Complementary Auxiliary Output Data Bit 4, Q-Channel

27 P4Q+ Primary Output Data Bit 4, Q-Channel

28 P4Q- Complementary Primary Output Data Bit 4, Q-Channel

29, 35 OVCCQQ-Channel Outputs, Digital Supply. Supplies Q-channel output drivers and DOR logic. Bypass to

OGND with 0.01µF in parallel with 47pF for proper operation.

30, 36 OGNDQ Q-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board

for proper operation.

Pin Description

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

10 ______________________________________________________________________________________

PIN NAME FUNCTION

31 A3Q+ Auxiliary Output Data Bit 3, Q-Channel

32 A3Q- Complementary Auxiliary Output Data Bit 3, Q-Channel

33 P3Q+ Primary Output Data Bit 3, Q-Channel

34 P3Q- Complementary Primary Output Data Bit 3, Q-Channel

37 A2Q+ Auxiliary Output Data Bit 2, Q-Channel

38 A2Q- Complementary Auxiliary Output Data Bit 2, Q-Channel

39 P2Q+ Primary Output Data Bit 2, Q-Channel

40 P2Q- Complementary Primary Output Data Bit 2, Q-Channel

41 A1Q+ Auxiliary Output Data Bit 1, Q-Channel

42 A1Q- Complementary Auxiliary Output Data Bit 1, Q-Channel

43 P1Q+ Primary Output Data Bit 1, Q-Channel

44 P1Q- Complementary Primary Output Data Bit 1, Q-Channel

45 A0Q+ Auxiliary Output Data Bit 0 (LSB), Q-Channel

46 A0Q- Complementary Auxiliary Output Data Bit 0 (LSB), Q-Channel

47 P0Q+ Primary Output Data Bit 0 (LSB), Q-Channel

48 P0Q- Complementary Primary Output Data Bit 0 (LSB), Q-Channel

49 DOR+ Complementary LVDS Out-Of-Range Bit

50 DOR- LVDS Out-of-Range Bit

51 DREADY- Complementary Data-Ready Clock

52 DREADY+ Data Ready Clock

53 P0I- Complementary Primary Output Data Bit 0 (LSB), I-Channel

54 P0I+ Primary Output Data Bit 0 (LSB), I-Channel

55 A0I- Complementary Auxiliary Output Data Bit 0 (LSB), I-Channel

56 A0I+ Auxiliary Output Data Bit 0 (LSB), I-Channel

57 P1I- Complementary Primary Output Data Bit 1, I-Channel

58 P1I+ Primary Output Data Bit 1, I-Channel

59 A1I- Complementary Auxiliary Output Data Bit 1, I-Channel

60 A1I+ Auxiliary Output Data Bit 1, I-Channel

61 P2I- Complementary Primary Output Data Bit 2, I-Channel

Pin Description (continued)

Detailed Description

The MAX105 is a dual, +5V, 6-bit, 800Msps flash ana-

log-to-digital converter (ADC), designed for high-

speed, high-bandwidth I&Q digitizing. Each ADC

(Figure 1) employs a fully differential, wide bandwidth

input stage, 6-bit quantizers and a unique encoding

scheme to limit metastable states to typically one error

per 1016 clock cycles, with no error exceeding a maxi-

mum of 1LSB. An integrated 6:12 output demultiplexer

simplifies interfacing to the part by reducing the output

data rate to one-half the sampling clock rate. The

MAX105 outputs data in LVDS two’s complement for-

mat.

When clocked at 800Msps, the MAX105 provides a typ-

ical signal-to-noise plus distortion (SINAD) of 36.4dB

with a 200MHz input tone. The analog input of the

MAX105 is designed for differential or single-ended use

with a ±400mV full-scale input range. In addition, the

MAX105 features an on-board +2.5V precision

bandgap reference, which is scaled to meet the analog

input full-scale range.

Principle of Operation

The MAX105 employs a flash or parallel architecture.

The key to this high-speed flash architecture is the use

of an innovative, high-performance comparator design.

Each quantizer and downstream logic translates the

comparator outputs into 6-bit, parallel codes in two’s

complement format and passes them on to the internal

6:12 demultiplexer. The demultiplexer enables the

ADCs to provide their output data at half the sampling

speed on primary and auxiliary ports. LVDS data is

available at speeds of up to 400MHz per output port.

Input Amplifier Circuits

As with all ADCs, if the input waveform is changing

rapidly during conversion, effective number of bits

(ENOB), signal-to-noise plus distortion (SINAD), and

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________ 11

PIN NAME FUNCTION

62 P2I+ Primary Output Data Bit 2, I-Channel

63 A2I- Complementary Auxiliary Output Data Bit 2, I-Channel

64 A2I+ Auxiliary Output Data Bit 2, I-Channel

65, 72 OVCCII-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to

OGND with 0.01µF in parallel with 47pF for proper operation.

66, 71 OGNDI I-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board

for proper operation.

67 P3I- Complementary Primary Output Data Bit 3, I-Channel

68 P3I+ Primary Output Data Bit 3, I-Channel

69 A3I- Complementary Auxiliary Output Data Bit 3, I-Channel

70 A3I+ Auxiliary Output Data Bit 3, I-Channel

73 P4I- Complementary Primary Output Data Bit 4, I-Channel

74 P4I+ Primary Output Data Bit 4, I-Channel

75 A4I- Complementary Auxiliary Output Data Bit 4, I-Channel

76 A4I+ Auxiliary Output Data Bit 4, I-Channel

77 P5I- Complementary Primary Output Data Bit 5, I-Channel

78 P5I+ Primary Output Data Bit 5, I-Channel

79 A5I- Complementary Auxiliary Output Data Bit 5, I-Channel

80 A5I+ Auxiliary Output Data Bit 5, I-Channel

Pin Description (continued)

MAX105

signal-to-noise ratio (SNR) specifications will degrade.

The MAX105’s on-board, wide-bandwidth input ampli-

fiers (I&Q) reduce this effect significantly, allowing pre-

cise digitizing of fast analog data at high conversion

rates. The input amplifiers buffer the input signal and

allow a full-scale signal input range of ±400mV

(800mVp-p).

Internal Reference

The MAX105 features an integrated, buffered +2.5V

precision bandgap reference. This reference is internal-

ly scaled to match the analog input range specification

of ±400mV. The data converter’s reference output

(REF) can source up to 500µA. REF should be buffered,

if used to supply external devices.

LVDS Digital Outputs

The MAX105 provides data in two’s complement format

to differential LVDS outputs. A simplified circuit

schematic of the LVDS output cells is shown in Figure

2. All LVDS outputs are powered from separate I-chan-

nel OVCCI and Q-channel OVCCQ (Q-channel) power

supplies, which may be operated at +3.3V ±10%. The

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

Figure 1. MAX105 Flash Converter Architecture

INI-

INI+

2kΩ

CLK+

AVCC

CLK-

P0I+/P0I-

DREADY+/DREADY-

DOR+/DOR-

P5I+/P5I-

A0I+/A0I-

A5I+/A5I-

P0Q+/P0Q-

P5Q+/P5Q-

A0Q+/A0Q-

A5Q+/A5Q-

10kΩ

CM BUFFER

REFERENCE

PRIMARY

DATA PORT

P0I-P5I

AUXILIARY

DATA PORT

A0I-A5I

PRIMARY

DATA PORT

P0Q-P5Q

AUXILIARY

DATA PORT

A0Q-A5Q

I ADC

1:2

REF

MAX105

INQ-

INQ+

2kΩ

PRE-AMP Q ADC

REF

DOR

PRE-AMP

MAX105

P0I+ - P5I+

A0I+ - A5I+

P0I- - P5I-

A0I- - A5I-

OVCCI

55Ω

Figure 2. Simplified LVDS Output Model

12 ______________________________________________________________________________________

MAX105 LVDS-outputs provide a typical ±270mV volt-

age swing around a common mode voltage of roughly

+1.2V, and must be differentially terminated at the far

end of each transmission line pair (true and comple-

mentary) with 100Ω.

Out-Of-Range Operation

A single output pair (DOR+, DOR-) is provided to flag

an out-of-range condition, if either the I or Q channel is

out-of-range, where out-of-range is above +FS or below

-FS. It features the same latency as the ADCs output

data and is demultiplexed in a similar fashion. With a

800MHz system clock, DOR+ and DOR- are clocked at

up to 400MHz.

Applications Information

Single-Ended Analog Inputs

The MAX105 is designed to work at full-speed for both

single-ended and differential analog inputs without sig-

nificant degradation in its dynamic performance. Both

input channels I (INI+, INI-) and Q (INQ+, INQ-) have

2kΩimpedance and allow for AC- and DC-coupled

input signals. In a typical DC-coupled single-ended

configuration (Table 1), the analog input signals enter

the analog input amplifier stages at the in-phase-input

pins INI+/INQ+, while the inverted phase input INI-

/INQ- pins are AC-coupled to AGNDI/AGNDQ. Single-

ended operation allows for an input amplitude of

800mVp-p, centered around VREF.

Differential Analog Inputs

To obtain +FS digital outputs with differential input drive

(Table 2), 400mV must be applied between INI+ (INQ+)

and INI- (INQ-). Midscale digital output codes occur

when there is no voltage difference between INI+

(INQ+) and INI- (INQ-). For a -FS digital output code

both in-phase (INI+, INQ+) and inverted input (INI-,

INQ-) must see -400mV.

Single-Ended to Differential

Conversion Using a Balun

An RF balun (Figure 3) provides an excellent solution to

convert a single-ended signal to a fully differential sig-

nal, required by the MAX105 for optimum performance.

At higher frequencies, the MAX105 provides better

SFDR and THD with fully differential input signals over

single-ended input signals. In differential input mode,

even-order harmonics are suppressed and each input

requires only half the signal-swing compared to single-

ended mode.

Clock Input

The MAX105 features clock inputs designed for either

single-ended or differential operation with very flexible

input drive requirements. The clock inputs (AC- or DC-

coupled) provide a 5kΩinput impedance to AVCC/2

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________ 13

IN-PHASE INPUTS

(INI+, INQ+)

INVERTED INPUTS

(INI-, INQ-)

OUT-OF-RANGE BIT

(DOR+, DOR-) OUTPUT CODE

> +400mV + VREF AC – Coupled to AGND_ 1 011111

+400mV - 0.5LSB + VREF AC – Coupled to AGND_ 0 011111

0V + VREF AC – Coupled to AGND_ 0 000000/111111

-400mV + 0.5LSB + VREF AC – Coupled to AGND_ 0 100000

< -400mV + VREF AC – Coupled to AGND_ 1 100000

Table 1. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog

Input

IN-PHASE INPUTS

(INI+, INQ+)

INVERTED INPUTS

(INI-, INQ-)

OUT-OF-RANGE BIT

(DOR+, DOR-) OUTPUT CODE

>+200mV + VREF <-200mV + VREF 1 011111

+200mV - 0.25LSB + VREF -200mV + 0.25LSB + VREF 0 011111

0V + VREF 0V + VREF 0000000/111111

-200mV + 0.25LSB + VREF +200mV - 0.25LSB + VREF 0 100000

<-200mV + VREF >+200mV + VREF 1 100000

Table 2. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input

MAX105

and are internally buffered with a preamplifier to ensure

proper operation of the converter even with small-

amplitude sine-wave sources. The MAX105 was

designed for single-ended, low-phase noise sine wave

clock signals with as little as 500mVP-P amplitude

(-2dBm).

Single-Ended Clock (Sine-Wave Drive)

Excellent performance is obtained by AC- or DC-cou-

pling a low-phase noise sine-wave source into a single

clock input (Figure 4). Essentially, the dynamic perfor-

mance of the converter is unaffected by clock-drive

power levels from -2dBm (500mVp-p clock signal ampli-

tude) to +10dBm (2VP-P clock signal amplitude). The

MAX105 dynamic performance specifications are

determined by a single-ended clock drive of -2dBm

(500mVp-p clock signal amplitude). To avoid saturation

of the input amplifier stage, limit the clock power level

to a maximum of +10dBm.

Differential Clock (Sine-Wave Drive)

The advantages of differential clock drive (Figure 5)

can be obtained by using an appropriate balun or

transformer to convert single-ended sine-wave sources

into differential drives. Refer to Single-Ended Clock

Inputs (Sine-Wave Drive) for proper input amplitude

requirements.

LVDS, ECL and PECL Clock

The innovative input architecture of the MAX105 clock

also allows these inputs to be driven by LVDS-, ECL-, or

PECL-compatible input levels, ranging from 500mVp-p

to 2Vp-p (Figure 6).

Timing Requirements

The MAX105 features a 6:12 demultiplexer, which

reduces the output data rate (including DREADY and

DOR signals) to one-half of the sample clock rate. The

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

14 ______________________________________________________________________________________

AGND

0°

180°

0°

SIGNAL SOURCE

50Ω

*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50Ω TO AGND) ON A

BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

50Ω

AGND

50Ω*

Figure 3. Single-Ended to Differential Conversion Using a Balun

AGND

FROM SIGNAL SOURCE

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

50Ω

Figure 4. Single-Ended Clock Input With AC-Coupled Input

Drive (CLK, INI, INQ)

Figure 5. Differential AC-Coupled Input Drive (CLK, INI, INQ)

AGND

50Ω TRANSMISSION LINES

TO 50Ω-TERMINATED

SIGNAL SOURCE

OR BALUM

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

50Ω

50Ω TRANSMISSION LINES

LVDS LINE DRIVER

SIGNAL

SOURCE

INPUT

CLK+,

INI+,

INQ+

CLK-,

INI-,

INQ-

100pF

100Ω

Figure 6. LVDS Input Drive (CLK, INI, INQ)

demultiplexed outputs are presented in dual 6-bit two’s

complement format with two consecutive samples in

the primary and auxiliary output ports on the rising

edge of the data ready clock. The auxiliary data port

always contains the older sample. The primary output

always contains the most recent data sample, regard-

less of the DREADY clock phase. Figure 7 shows the

timing and data alignment of the auxiliary and primary

output ports in relationship with the CLK and DREADY

signals. Data in the primary port is delayed by five

clock cycles while data in the auxiliary port is delayed

by six clock cycles.

Typical I/Q Application

Quadrature amplitude modulation (QAM) is frequently

used in digital communication systems to increase

channel capacity. A QAM signal is modulated in both

amplitude and phase. With a demodulator, this QAM

signal gets downconverted and separated in its in-

phase (I) and quadrature (Q) components. Both I&Q

channels are digitized by an ADC at the baseband

level in order to recover the transmitted information.

Figure 8 shows a typical application circuit to directly

tune L-band signals to baseband, incorporating a

direct conversion tuner (MAX2108) and the MAX105 to

digitize I&Q channels with excellent phase- and gain-

matching. A front-end L-C filter is required for anti-alias-

ing purposes.

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________ 15

Figure 7. Output Timing Relationship Between CLK and DREADY Signals and Primary/Auxiliary Output Ports

CLK+

CLK-

DREADY +

DREADY -

AUXILIARY PORT DATA

PRIMARY PORT DATA

tPWH tPWL

tPD1

tPD2

NOTE: THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK

CYCLES. BOTH PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.

CLK-

CLK+

N N+1 N+2 N+3 N+4 N+5

N N+8 N+10N+2 N+6N+4

N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13

ADC SAMPLE

MAX105 ADCs SAMPLE ON THE RISING EDGE OF CLK+

CLK

DREADY

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

DREADY-

DREADY+

N+14 N+15 N+16 N+17 N+18 N+19

N+9 N+11N+3N+1 N+7N+5

MAX105

Grounding, Bypassing,

and Board Layout

Grounding and power supply decoupling strongly influ-

ence the MAX105’s performance. At 800MHz clock fre-

quency and 6-bit resolution, unwanted digital crosstalk

may couple through the input, reference, power supply,

ground connections, and adversely influence the

dynamic performance of the ADC. In addition, the I&Q

inputs may crosstalk through poorly designed decou-

pling circuits. Therefore, closely follow the grounding

and power-supply decoupling guidelines in Figure 9.

Maxim strongly recommends using a multilayer printed

circuit board (PC board) with separate ground and

power supply planes. Since the MAX105 has separate

analog and digital ground connections (AGND, AGNDI,

AGNDQ, AGNDR, OGNDI, and OGNDQ, respectively).

The PC board should feature separate sections desig-

nated to analog (AGND) and digital (OGND), connect-

ed at only one point. Digital signals should run above

the digital ground plane and analog signals should run

above the analog ground plane. Keep digital signals far

away from the sensitive analog inputs, reference inputs,

and clock inputs. High-speed signals, including clocks,

analog inputs, and digital outputs, should be routed on

50Ωmicrostrip lines, such as those employed on the

MAX105EV kit.

The MAX105 has separate analog and digital power-

supply inputs:

•AVCC = +5V ±5%: Power supply for the analog

input section of the clock circuit.

•AVCCI = +5V ±5%: Power supply for the I-channel

common-mode buffer, pre-amp and quantizer.

•AVCCQ = +5V ±5%: Power supply for the Q-chan-

nel common-mode buffer, pre-amp and quantizer.

•AVCCR = +5V ±5%: Power supply for the on-chip

bandgap reference.

•OVCCI = +3.3V ±10%: Power supply for the I-chan-

nel output drivers and DREADY circuitry.

•OVCCQ = +3.3V ±10%: Power supply for the

Q-channel output drivers and DOR circuitry.

All supplies should be decoupled with large tantalum or

electrolytic capacitors at the point they enter the PC

board. For best performance, bypass all power sup-

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

16 ______________________________________________________________________________________

2kΩAVCC

DREADY+/DREADY-

DOR+/DOR-

10kΩ

CM BUFFER

PRE-AMP

NYQUIST

FILTER

FROM PREVIOUS STAGE

QUADRATURE

DEMODULATOR

MAX2108

CM BUFFER

REFERENCE

PRIMARY

DATA PORT

P0I-P5I

AUXILIARY

DATA PORT

A0I-A5I

PRIMARY

DATA PORT

P0Q-P5Q

AUXILIARY

DATA PORT

A0Q-A5Q

I ADC

1:2

REF

2kΩ

PRE-AMP Q ADC

REF

DOR

90°

NYQUIST

FILTER

Figure 8. Typical I/Q Application

plies to the appropriate ground with a 10µF tantalum

capacitor, to filter power supply noise, in parallel with a

0.1µF capacitor. A combination of 0.01µF in parallel

with high quality 47pF ceramic chip capacitor located

very close to the MAX105 device filters high frequency

noise. A properly designed PC board (see MAX105EV

Kit data sheet) allows the user to connect all analog

supplies and all digital supplies together thereby

requiring only two separate power sources. Decoupling

AVCC, AVCCI, AVCCQ and AVCCR with ferrite-bead

suppressors prevents further crosstalk between the

individual analog supply pins

Thermal Management

The MAX105 is designed for a thermally enhanced 80-

pin TQFP package, providing greater design flexibility,

increased thermal efficiency and a low thermal junc-

tion-case (θjc) resistance of ≈1.26°C/W. In this pack-

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________ 17

AVCCQ

AVCC

AGNDR

AGND

AGNDI

AGNDQ

AVCCQ

AVCC

AGND

AGNDQ

AGNDI

AGNDR

AVCCI

PC BOARD AVCC

PC BOARD OVCC

PC BOARD AGND FERRITE-BEAD

SUPPRESSORS

PC BOARD OGND

AVCCRAVCCR

AVCCI

OVCCQ

OGNDQ

OGNDI

OVCCI

OVCCI, OVCCQ

OVCCI

OVCCQ

OGNDQ

OGNDI

OVCCI

NOTE:

LOCATE ALL 47pF AND 10nF CAPACITORS, WHICH DECOUPLE AVCCI, AVCCQ, AVCCR, OVCCI, AND OVCCQ AS CLOSE

AS POSSIBLE TO THE CHIP. IT IS ALSO RECOMMENDED TO CONNECT ALL ANALOG GROUND CONNECTIONS TO A COMMON ANALOG

GROUND PLANE AND ALL DIGITAL GROUND CONNECTIONS TO ONE COMMON DIGITAL GROUND PLANE ON THE PC BOARD. A SIMILAR

TECHNIQUE CAN BE USED FOR ALL ANALOG AND DIGITAL POWER SUPPLIES.

AVCC = AVCCI = AVCCQ = AVCCR = +5V±5%

OVCCI = OVCCQ = +3.3V±10%

10nF 47pF

4 x 10nF

10nF 47pF

10µF10nF

10nF 47pF

10nF

47pF

MAX105

Figure 9. MAX105 Decoupling, Bypassing and Grounding

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

18 ______________________________________________________________________________________

age, the data converter die is attached to an exposed

pad (EP) leadframe using a thermally conductive

epoxy. The package is molded in a way, that this lead-

frame is exposed at the surface, facing the printed cir-

cuit board (PC board) side of the package (Figure 10).

This allows the package to be attached to the PC board

with standard infrared (IR) flow soldering techniques. A

specially created land pattern on the PC board, match-

ing the size of the EP (7.5mm x 7.5mm) does not only

guarantee proper attachment of the chip, but can also

be used for heat-sinking purposes. Designing thermal

vias* into the land area and implementing large ground

planes in the PC board design, further enhance the

thermal conductivity between board and package. To

remove heat from an 80-pin TQFP package efficiently,

an array of 6 x 6 vias (≤0.3mm diameter per via hole

and 1.2mm pitch between via holes) is required.

Note: Efficient thermal management for the MAX105 is

strongly depending on PC board and circuit design,

component placement, and installation. Therefore,

exact performance figures cannot be provided.

However, the MAX105EV kit exhibits a typical θja of

18°C/W. For more information on proper design tech-

niques and recommendations to enhance the thermal

performance of parts such as the MAX105, please refer

to Amkor Technology’s website at www.amkor.com.

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an

actual transfer function from a straight line. This straight

line is drawn between the endpoints of the transfer

function, once offset and gain errors have been nulli-

fied. The static linearity parameters for the MAX105 are

measured using the sine-histogram method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an

actual step-width and the ideal value of 1LSB. A DNL

error specification of greater than -1LSB guarantees no

missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter and Delay

Aperture uncertainties affect the dynamic performance

of high-speed converters. Aperture jitter, in particular,

directly influences SNR and limits the maximum slew

rate (dV/dt) that can be digitized without significant

error. Aperture jitter limits the SNR performance of the

ADC, according to the following relationship:

SNRdB = 20 x log10 [1 / (2 x πx fIN x tAJ[RMS])],

where fIN represents the analog input frequency and

tAJ is the RMS aperture jitter. The MAX105’s innovative

DIE

COPPER TRACE, 1oz.

TOP LAYER

GROUND PLANE (AGND)

GROUND PLANE

AGND, DGND

POWER PLANE

THERMAL LAND

COPPER PLANE, 1oz.

6 x 6 ARRAY OF THERMAL VIAS

THERMAL LAND

COPPER PLANE, 1oz.

EXPOSED PAD

EXPOXY

BONDING WIRE

80-PIN TQFP PACKAGE

WITH EXPOSED PAD

COPPER

TRACE, 1oz.

PC BOARD

MAX105

Figure 10. MAX105 Exposed Pad Package Cross-Section

*Connects the land pattern to internal or external copper planes.

clock design limits aperture jitter to typically 1.5psRMS.

Figure 11 depicts the aperture jitter (tAJ), which is the

sample-to-sample variation in the aperture delay.

Aperture delay (tAD) is the time defined between the

rising edge of the sampling clock and the instant when

an actual sample is taken (Figure 11).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the theoretical maximum SNR is the ratio of

the full-scale analog input (RMS value) to the RMS

quantization error (residual error). The ideal, theoretical

minimum analog-to-digital noise is caused by quantiza-

tion error only and results directly from the ADC’s reso-

lution (N-Bits):

SNRMAX[dB] = 6.02dB x N + 1.76dB

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter

(see Aperture Uncertainties). SNR is computed by tak-

ing the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first four harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to all spectral components minus the fundamental

and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at

a specific input frequency, amplitude, and sampling

rate relative to an ideal ADC’s quantization noise. For a

full-scale input ENOB is computed from:

ENOB = (SINAD - 1.76dB) / 6.02dB

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four

harmonics of the input signal to the fundamental itself.

This is expressed as:

where V1 is the fundamental amplitude, and V2through

V5are the amplitudes of the 2nd- through 5th-order har-

monics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS

amplitude of the fundamental to the RMS value of the

next largest spurious component, excluding DC offset.

Two-Tone Intermodulation

Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of

either input tone to the worst 3rd-order (or higher) inter-

modulation products. The individual input tone levels

are at -7dB full-scale and their envelope peaks at -1dB

full-scale.

Chip Information

TRANSISTOR COUNT: 12,286

THD x V V V V V=+++20 223242521

log ( )/ )

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

______________________________________________________________________________________ 19

CLK+

ANALOG

INPUT

SAMPLING

INSTANT

tAW

tAD

tAJ

CLK-

tAW: APERTURE WIDTH

tAJ: APERTURE JITTER

tAD: APERTURE DELAY

MAX105

Figure 11. Aperture Timing

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

20 ______________________________________________________________________________________

A5I+

A5I-

P5I+

P5I-

A4I+

A4I-

P4I+

P4I-

OVCCI

OGNDI

A3I+

60 A1I+

A1I-

P1I+

P1I-

A0I+

A0I-

P01+

P01-

DREADY+

DREADY-

DOR-

DOR+

P0Q-

P0Q+

A0Q-

A0Q+

P1Q-

P1Q+

A1Q-

A1Q+

T.P.

REF

AVCCR

AGNDR

AGNDI

INI-

INI+

AGNDI

AVCCI

CLK+

CLK-

AVCCQ

AGNDQ

INQ+

INQ-

AGNDQ

AGND

AVCC

T.P.

A3I-

P3I+

P3I-

OGNDI

OVCCI

A2I+

A2I-

P2I+

P2I-

A5Q+

A5Q-

P5Q+

P5Q-

A4Q+

A4Q-

P4Q+

P4Q-

OVCCQ

OGNDQ

A3Q+

A3Q-

P3Q+

P3Q-

OVCCQ

OGNDQ

A2Q+

A2Q-

P2Q+

P2Q-

MAX105

Pin Configuration

MAX105

Dual, 6-Bit, 800Msps ADC with On-Chip,

Wideband Input Amplifier

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21

Package Information