_______________General Description
The MAX531/MAX538/MAX539 are low-power, voltage-
output, 12-bit digital-to-analog converters (DACs) speci-
fied for single +5V power-supply operation. The MAX531
can also be operated with ±5V supplies. The
MAX538/MAX539 draw only 140µA, and the MAX531
(with internal reference) draws only 260µA. The
MAX538/MAX539 come in 8-pin DIP and SO packages,
while the MAX531 comes in 14-pin DIP and SO pack-
ages. All parts have been trimmed for offset voltage,
gain, and linearity, so no further adjustment is necessary.
The MAX538’s buffer is fixed at a gain of +1 and the
MAX539’s buffer at a gain of +2. The MAX531’s internal
op amp may be configured for a gain of +1 or +2, as
well as for unipolar or bipolar output voltages. The
MAX531 can also be used as a four-quadrant multiplier
without external resistors or op amps.
For parallel data inputs, see the MAX530 data sheet.
_______________________Applications
Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Battery-Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cellular Telephones
___________________________Features
♦Operate from Single +5V Supply
♦Buffered Voltage Output
♦Internal 2.048V Reference (MAX531)
♦140µA Supply Current (MAX538/MAX539)
♦INL = ±1/2LSB (max)
♦Guaranteed Monotonic over Temperature
♦Flexible Output Ranges:
0V to VDD (MAX531/MAX539)
VSS to VDD (MAX531)
0V to 2.6V (MAX531/MAX538)
♦8-Pin SO/DIP (MAX538/MAX539)
♦Power-On Reset
♦Serial Data Output for Daisy-Chaining
______________Ordering Information
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
________________________________________________________________
Maxim Integrated Products
1
1
2
3
4
8
7
6
5
VDD
VOUT
REFIN
AGND
DOUT
CS
SCLK
DIN
DIP/SO
TOP VIEW
MAX538
MAX539
_________________Pin Configurations
________________Functional Diagram
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
19-0172; Rev 6; 2/97
PART TEMP. RANGE PIN-PACKAGE
MAX531ACPD 0°C to +70°C 14 Plastic DIP
MAX531BCPD 0°C to +70°C 14 Plastic DIP
MAX531ACSD 0°C to +70°C 14 SO
MAX531BCSD 0°C to +70°C 14 SO
ERROR
(LSB)
±1/2
±1
±1/2
±1
DAC
DAC REGISTER
(12 BITS)
SHIFT REGISTER
(12 BITS) 4
BITS
CONTROL
LOGIC
POWER-UP
RESET
2.048V
REFERENCE
(MAX531 ONLY)
AGND
SCLK
DIN
(MAX531 ONLY)
REFOUT REFIN (MAX531 ONLY)
BIPOFF
RFB
(MAX531
ONLY)
VOUT
VDD
DGND
(MAX531
ONLY)
VSS
(MAX531
ONLY)
DOUT
(LSB) (MSB)
CLR
(MAX531
ONLY)
CS
MAX531
MAX538
MAX539
MAX531BC/D 0°C to +70°C Dice* ±1
Ordering Information continued at end of data sheet.
*Dice are specified at TA= +25°C only.
Pin Configurations continued at end of data sheet.
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output
Serial 12-Bit DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
VDD to DGND and VDD to AGND................................-0.3V, +6V
VSS to DGND and VSS to AGND .................................-6V, +0.3V
VDD to VSS.................................................................-0.3V, +12V
AGND to DGND........................................................-0.3V, +0.3V
Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V)
REFIN..................................................(VSS - 0.3V), (VDD + 0.3V)
REFOUT to AGND.........................................-0.3V, (VDD + 0.3V)
RFB .....................................................(VSS - 0.3V), (VDD + 0.3V)
BIPOFF................................................(VSS - 0.3V), (VDD + 0.3V)
VOUT (Note 1) ................................................................VSS, VDD
Continuous Current, Any Pin................................-20mA, +20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)...800mW
14-Pin SO (derate 8.33mW/°C above +70°C)..............667mW
Operating Temperature Ranges
MAX53_ _C_ _.....................................................0°C to +70°C
MAX53_ _E_ _ ..................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(VDD = +5V ±10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33µF
(MAX531), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER SYMBOL MIN TYP MAX UNITS
Unipolar Offset Error VOS 08LSB
Differential Nonlinearity DNL ±1 LSB
Relative Accuracy (Note 2) INL LSB
±1
Unipolar Offset Tempco TCVOS 3 ppm/°C
Gain Error (Note 2) GE ±1 LSB
Resolution N 12 Bits
±0.5
Gain-Error Tempco 1 ppm/°C
Power-Supply Rejection Ratio
(Note 3) PSRR 0.4 1 LSB/V
0V
DD - 2
Output Voltage Range 0V
DD - 0.4 V
Output Load Regulation 1 LSB
Short-Circuit Current ISC 12 mA
Voltage Range 0V
DD - 2 V
Input Resistance 40 kΩ
Input Capacitance 10 50 pF
AC Feedthrough -80 dB
CONDITIONS
MAX53_ _C/E
Guaranteed monotonic
4.5V ≤VDD ≤5.5V
MAX53_ _C/E
MAX531 (G = +1), MAX538
MAX531 (G = +2), MAX539
VOUT = 2V, RL= 2kΩ
Code dependent, minimum at code 555 hex
Code dependent (Note 4)
REFIN = 1kHz, 2Vp-p
Note 1: The output may be shorted to VDD, VSS,or AGND if the package power dissipation limit is not exceeded.
MAX53_AC/E
MAX53_BC/E
REFERENCE INPUT (REFIN)
VOLTAGE OUTPUT (VOUT)
STATIC PERFORMANCE
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(VDD = +5V ±10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33µF
(MAX531), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER
Input Current
SYMBOL MIN TYP MAX
IIN ±1
UNITS
Noise Voltage en
µA
400
Input Capacitance CIN
µVp-p
Power-Supply Rejection Ratio
8
PSRR 300 µV/V
Resistance RREFOUT 0.5 2
pF
Ω
Temperature Coefficient TCREFOUT 30 50 ppm/°C
Minimum Required External
Capacitor CMIN 3.3 µF
Output High
Input High
VOH
VIH 2.4
VDD - 1
V
Input Low
V
VIL 0.8 V
Output Low VOL 0.4 V
Voltage-Output Slew Rate SR 0.15 0.25 V/µs
Voltage-Output Settling Time 25 µs
Digital Feedthrough
2.024 2.048 2.072
5 nV-s
Signal-to-Noise plus Distortion SINAD 68 dB
260 400
CONDITIONS
VIN = 0V or VDD
0.1Hz to 10kHz
4.5V ≤VDD ≤5.5V
(Note 5)
MAX531AC/AE/AM/BM
ISOURCE = 2mA
ISINK = 2mA
TA= +25°C
To ±1/2LSB, VOUT = 2V
CS = VDD, DIN = 100kHz
REFIN = 1kHz, 2Vp-p (G = +1 or +2),
code = FFF hex
Power-Supply Current IDD All inputs = 0V or V DD,
output = no load 140 300 µA
CS Setup Time tCSS 20 ns
SCLK Fall to CS Fall Hold Time tCSH0 15 ns
SCLK Fall to CS Rise Hold Time tCSH1 0 ns
SCLK High Width tCH 35 ns
SCLK Low Width tCL 35 ns
DIN Setup Time tDS 45 ns
DIN Hold Time tDH 0 ns
DOUT Valid Propagation Delay tDO CL= 50pF 80 ns
CS High Pulse Width tCSW 20 ns
CLR Pulse Width tCLR 25 ns
MAX531BC/BE
MAX531
MAX538, MAX539
30
2.017 2.079
Reference Output Voltage V
2.013 2.083
VDD = 5.0V
CS Rise to SCLK Rise Setup Time tCS1 50 ns
TA= +25°C
MAX531BC
MAX531BE
Positive Supply Voltage VDD 4.5 5.5 V
REFERENCE OUTPUT (REFOUT—MAX531 only)
DIGITAL INPUTS (DIN, SCLK, CS, CLR)
DIGITAL OUTPUT (DOUT)
DYNAMIC PERFORMANCE
POWER SUPPLY
SWITCHING CHARACTERISTICS
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
4 _______________________________________________________________________________________
PARAMETER SYMBOL MIN TYP MAX UNITS
Bipolar Offset Error VOS ±8
Gain Error (Unipolar or Bipolar) GEU
LSB
Differential Nonlinearity
±1
DNL ±1 LSB
Relative Accuracy INL
LSB
LSB
±1
Gain-Error Tempco
Bipolar Offset Tempco TCVOS 3 ppm/°C
1 ppm/°C
Power-Supply Rejection Ratio
(Note 3) PSRR 0.4 1 LSB/V
Voltage Range
Resolution
VSS + 2 VDD - 2
N 12
V
Input Resistance
Bits
40 kΩ
Input Capacitance
±0.5
10 50 pF
AC Feedthrough -80 dB
CONDITIONS
BIPOFF = REFIN, MAX531_C/E
MAX531_C/E
Guaranteed monotonic
Tested at VDD = 5V,
VSS = -5V
BIPOFF = REFIN
4.5V ≤VDD ≤5.5V, -5.5V ≤VSS ≤-4.5V
Code dependent, minimum at code 555 hex
Code dependent (Note 4)
REFIN = 1kHz, 2.0Vp-p
ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only)
(VDD = +5V ±10%, VSS = -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33µF,
RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
MAX531AC/E
MAX531BC/E
2.024 2.048 2.072
MAX531AC/AE/AM/BM 30 50
Temperature Coefficient TCREFOUT MAX531BC/BE 30 ppm/°C
Resistance RREFOUT (Note 5) 0.5 2 Ω
Power-Supply Rejection Ratio PSRR 4.5V ≤VDD ≤5.5V 300 µV/V
en0.1Hz to 10kHz 400 µVp-pNoise Voltage
Minimum Required External
Capacitor CMIN 3.3 µF
Input High VIH 2.4 V
Input Low VIL 0.8 V
Input Current IIN VIN = 0V or VDD ±1 µA
Input Capacitance CIN 8 pF
Output High VOH ISOURCE = 2mA VDD - 1 V
Output Low VOL ISINK = 2mA 0.4 V
2.017 2.079
VDD = 5.0V 2.013 2.083 VReference Output Voltage TA= +25°C
MAX531BC
MAX531BE
REFERENCE INPUT (REFIN)
REFERENCE OUTPUT (REFOUT—MAX531 only)
DIGITAL INPUTS (DIN, SCLK, CS)
DIGITAL OUTPUT (DOUT)
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________
5
Note 2: In single-supply operation, INL and GE calculated from code 11 to code 4095. Tested at VDD = +5V.
Note 3: This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio.
Note 4: Guaranteed by design.
Note 5: Tested at IOUT = 100µA. The reference can typically source up to 5mA (see
Typical Operating Characteristics
).
ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only) (continued)
(VDD = +5V ±10%, VSS = -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33µF,
RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL MIN TYP MAX UNITS
Voltage-Output Slew Rate SR
dB
0.15 0.25
VDD
V/µs
4.5 5.5
ISC 12
V
mA
Positive Supply Voltage
1 LSB
Negative Supply Voltage
Voltage-Output Settling Time 25 µs
Signal-to-Noise plus Distortion
5 nV-s
VSS -5.5 0 V
Short-Circuit Current
68
Digital Feedthrough
SINAD 68
Output Load Regulation
VSS + 2 VDD - 2
Output Voltage Range VSS + 0.4 VDD - 0.4 V
CONDITIONS
VOUT = 2V, RL= 2kΩ
To ±1/2LSB, VOUT = 2V
Step 000 hex to FFF hex
REFIN = 1kHz, 2Vp-p, (G = +1)
REFIN = 1kHz, 2Vp-p, (G = +2)
MAX531 (G = +1)
MAX531 (G = +2)
CS Setup Time tCSS 20 ns
SCLK Fall to CS Fall Hold Time tCSH0 15 ns
SCLK Fall to CS Rise Hold Time tCSH1 0 ns
SCLK High Width tCH 35 ns
SCLK Low Width tCL 35 ns
DIN Setup Time tDS 45 ns
DIN Hold Time tDH 0 ns
DOUT Valid Propagation Delay tDO CL= 50pF 80 ns
CS High Pulse Width tCSW 20 ns
CLR Pulse Width tCLR 25 ns
CS Rise to SCLK Rise Setup Time tCS1 50 ns
Positive Supply Current IDD 260 400 µAAll inputs = 0V or VDD, no load
Negative Supply Current ISS -120 -200 µAAll inputs = 0V or VDD, no load
VOLTAGE OUTPUT (VOUT)
DYNAMIC PERFORMANCE
POWER SUPPLY
SWITCHING CHARACTERISTICS
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
6 _______________________________________________________________________________________
120 -60
SUPPLY CURRENT vs.
TEMPERATURE
140
MAX531-7
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
60
240
180
-20 20 80
300
-40 0 40 100
280
260
220
200
160 MAX538/MAX539
MAX531
4
-14 1 100 100k
MAX531
GAIN vs. FREQUENCY
-12
MAX531-8
FREQUENCY (Hz)
GAIN (dB)
-8
-4
0
2
-2
-6
-10
1k 10k
REFIN = 4Vp-p 80
010 1k 100k
MAX531
AMPLIFIER SIGNAL-TO-NOISE RATIO
10
MAX531-9
FREQUENCY (Hz)
SIGNAL-TO-NOISE RATIO (dB)
20
40
60
30
50
70
10k100
REFIN = 4Vp-p
2.055
2.045 -60
MAX531
REFERENCE VOLTAGE vs.
TEMPERATURE
MAX531-6
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
60
2.050
-20 20 80 100400
-40
-110
01 10 1k 100k
ANALOG FEEDTHROUGH vs.
FREQUENCY
-30
-70
MAX531-5
FREQUENCY (Hz)
ANALOG FEEDTHROUGH (dB)
100 10k 1M
-100
-90
-80
-60
-50
-40
-20
-10
CODE = 000 hex
2
8VDD-5 VDD-1
OUTPUT SOURCE CAPABILITY vs.
OUTPUT PULL-UP VOLTAGE
7
3
MAX531-4
OUTPUT PULL-UP VOLTAGE (V)
OUTPUT SOURCE CAPABILITY (mA)
VDD-2
5
6
VDD-4 VDD-3
4
VDD-0
1
0
0.25
-1.25 012
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (FIRST 12 CODES)
-1.00
MAX531-1
DIGITAL INPUT CODE (DECIMAL)
INTEGRAL NONLINEARITY (LSB)
8
-0.50
-0.75
-0.25
2610
0
4
DUAL SUPPLIES
SINGLE SUPPLY
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (ALL CODES)
0 512 1024 1536 2048 2560 3072 3584 4095
-0.25
0
0.25
INTEGRAL NONLINEARITY (LSB)
DIGITAL INPUT CODE (DECIMAL)
12
00 0.8
OUTPUT SINK CAPABILITY vs.
OUTPUT PULL-DOWN VOLTAGE
2
10
MAX531-3
OUTPUT PULL-DOWN VOLTAGE (V)
OUTPUT SINK CAPABILITY (mA)
0.6
6
4
0.2 0.4
8
1.0
14
16
__________________________________________Typical Operating Characteristics
(VDD = +5V, VREFIN = 2.048V, TA= +25°C, unless otherwise noted.)
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________ 7
____________________________Typical Operating Characteristics (continued)
(VDD = +5V, VREFIN = 2.048V, TA= +25°C, unless otherwise noted.)
20
-30 1
MAX531
GAIN AND PHASE vs. FREQUENCY
-10
10
MAX531-10
FREQUENCY (kHz)
GAIN (dB)
10 100
0
-20
800 -180
0
180
GAIN
PHASE
RFB CONNECTED TO AGND (G=2)
RFB CONNECTED TO VOUT (G=1)
PHASE (degrees)
2.0520
2.04900 5.0
MAX531 REFERENCE OUTPUT VOLTAGE
vs. REFERENCE LOAD CURRENT
2.0495
2.0515
MAX531-14
REFERENCE LOAD CURRENT (mA)
REFERENCE OUTPUT (V)
3.0
2.0505
2.0500
1.0 2.0 4.0
2.0510
0.5 1.5 2.5 3.5 4.5
VDD = ±5V, VREFIN = 2V, BIPOLAR CONFIGURATION
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
A
B
NEGATIVE SETTLING TIME (MAX531)
5µs/div
DIGITAL FEEDTHROUGH
A
B
CS = HIGH
A: DIN = 4Vp-p, 100kHz
B: VOUT, 10mV/div
2µs/div
A
B
POSITIVE SETTLING TIME (MAX531)
VDD = ±5V, VREFIN = 2V, BIPOLAR CONFIGURATION
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
5µs/div
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output
Serial 12-Bit DACs
8 _______________________________________________________________________________________
10
FUNCTION
1BIPOFF Bipolar Offset/Gain
Resistor
2 DIN Serial Data Input
3CLR Clear. Asynchronously sets
DAC register to 000 hex.
PIN
—
1
4 SCLK Serial Clock Input
5CS Chip Select, active low
6 DOUT Serial Data Output for
daisy-chaining
7 DGND Digital Ground
—
2
3
8 AGND Analog Ground
9 REFIN Reference Input
4
—
5
6
—REFOUT Reference Output,
2.048V
11 — VSS Negative Power Supply
12 7 VOUT DAC Output
13 8 VDD Positive Power Supply
14 — RFB Feedback Resistor
MAX531 MAX538
MAX539
NAME
____________________Pin Description _______________Detailed Description
General DAC Discussion
The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con-
vert 12-bit digital data to analog voltage levels (see
Functional Diagram)
. The term “inverted” describes the
ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.
An internal reset circuit forces the DAC register to reset to
000 hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000 hex. CLR operates
asynchronously and independently from the chip-select
(CS) pin.
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25µs to 0.01% of final value. The settling
time is considerably longer when the DAC code is initially
set to 000 hex, because at this code the op amp is com-
pletely debiased. Start from code 001 hex if necessary.
The output is short-circuit protected and can drive a 2kΩ
load with more than 100pF load capacitance.
tCSH0 tCSS tCH tCL tCSH1
tCSW
tDS
tDH
tDO
CS
SCLK
DIN
DOUT
tCS1
Figure 1. Timing Diagram
Internal Reference (MAX531 only)
The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current,
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.
For applications requiring very low-noise performance,
connect a 33µF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value capacitor (3.3µF min) may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor, CREFOUT, is still required for reference
stability. In applications not requiring the reference, con-
nect REFOUT to VDD or use the MAX538 or MAX539 (no
internal reference).
External Reference
An external reference in the range (VSS + 2V) to (VDD - 2V)
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
VDD - 2V. The reference voltage determines the DAC’s full-
scale output. The DAC input resistance is code dependent
and is minimum (40kΩ) at code 555 hex and virtually infi-
nite at code 000 hex. REFIN’s input capacitance is also
code dependent and has a 50pF maximum value at sever-
al codes. Because of the code-dependent nature of refer-
ence input impedances, a high-quality, low-output-imped-
ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.
If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCVOUT =
7ppm/°C (max).
Logic Interface
The MAX531/MAX538/MAX539 logic inputs are designed to
be compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital inputs
with rail-to-rail CMOS logic. With TTL logic levels, the power
requirement increases by a factor of approximately 2.
Serial Clock and Update Rate
Figure 1 shows the MAX531/MAX538/MAX539 timing. The
maximum serial clock rate is given by 1 / (tCH + tCL),
approximately 14MHz. The digital update rate is limited by
the chip-select period, which is 16 x (tCH + tCL) + tCSW.
This equals a 1.14µs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25µs, which may limit the
update rate to 40kHz for full-scale step transitions.
____________Applications Information
Refer to Figures 3a and 3b for typical operating connec-
tions.
Serial Interface
The MAX531/MAX538/MAX539 use a three-wire serial
interface that is compatible with SPI™, QSPI™
(CPOL = CPHA = 0), and Microwire™ standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the
Functional Diagram
).
Sixteen bits of serial data are clocked into the DAC MSB
first with the MSB preceded by four fill (dummy) bits. The
four dummy bits are not normally needed. They are
required only when DACs are daisy-chained. Data is
clocked in on SCLK’s rising edge while CS is low. The seri-
al input data is held in a 16-bit serial shift register. On CS’s
rising edge, the 12 least significant bits are transferred to
the DAC register and update the DAC. With CS high, data
cannot be clocked into the MAX531/MAX538/MAX539.
The MAX531/MAX538/MAX539 input data in 16-bit blocks.
The SPI and Microwire interfaces output data in 8-bit
blocks, thereby requiring two write cycles to input data to
the DAC. The QSPI interface allows variable data input
from eight to 16 bits, and can be loaded into the DAC in
one write cycle.
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________ 9
300
50
1 10 100
100
MAX531-FIG02
FREQUENCY (kHz)
REFERENCE NOISE (µVRMS)
150
200
250
00.1 1000
TOTAL
REFERENCE
NOISE
RS
REFOUT
CREFOUT
CS
TEK 7A22
CREFOUT = 3.3µF
CREFOUT = 47µF
SINGLE-POLE ROLLOFF 1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
REFERENCE NOISE (mVp-p)
Figure 2. Reference Noise vs. Frequency
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
MAX531/MAX538/MAX539
Daisy-Chaining Devices
The serial output, DOUT, allows cascading of two or
more DACs. The data at DIN appears at DOUT,
delayed by 16 clock cycles plus one clock width. For
low power, DOUT is a CMOS output that does not
require an external pull-up resistor. DOUT does not go
into a high-impedance state when CS is high. DOUT
changes on SCLK’s falling edge when CS is low. When
CS is high, DOUT remains in the state of the last data
bit.
Any number of MAX531/MAX538/MAX539 DACs can
be daisy-chained by connecting the DOUT of one
device to the DIN of the next device in the chain. For
proper timing, ensure that tCL (CS low to SCLK high) is
greater than tDO + tDS.
Unipolar Configuration
The MAX531 is configured for a gain of +1 (0V to VREFIN
unipolar output) by connecting BIPOFF and RFB to
VOUT (Figure 6). The converter operates from either sin-
gle or dual supplies in this configuration. See Table 1 for
the DAC-latch contents (input) vs. the analog VOUT
(output). In this range, 1LSB = VREFIN (2-12). The
MAX538 is internally configured for unipolar gain = +1
operation.
A gain of +2 (0V to 2VREFIN unipolar output) is set up
by connecting BIPOFF to AGND and RFB to VOUT
(Figure 7). Table 2 shows the DAC-latch contents vs.
VOUT. The MAX531 operates from either single or dual
supplies in this mode. In this range, 1LSB = (2)(VREFIN)
(2-12) = (VREFIN)(2-11). The MAX539 is internally config-
ured for unipolar gain = +2 operation.
Bipolar Configuration
A bipolar range is set up by connecting BIPOFF to
REFIN and RFB to VOUT, and operating from dual
(±5V) supplies (Figure 8). Table 3 shows the DAC-latch
contents (input) vs. VOUT (output). In this range,
1LSB = VREFIN (2-11).
Four-Quadrant Multiplication
The MAX531 can be used as a four-quadrant multiplier
by connecting BIPOFF to REFIN and RFB to VOUT,
using (1) an offset binary digital code, (2) bipolar power
supplies, using dual power supplies, and (3) a bipolar
analog input at REFIN within the range VSS + 2V to VDD
- 2V, as shown in Figure 9.
In general, a 12-bit DAC’s output is (D) (VREFIN) (G),
where “G” is the gain (+1 or +2) and “D” is the binary
representation of the digital input divided by 212 or
4096. This formula is precise for unipolar operation.
However, for bipolar, offset binary operation, the MSB is
really a polarity bit. No resolution is lost, as there are
the same number of steps. The output voltage, howev-
er, has been shifted from a range of, for example, 0V to
4.096V (G = +2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-
rant multiplier, the scale is skewed. Negative full scale
is -VREFIN, while positive full scale is +VREFIN - 1LSB.
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
10 ______________________________________________________________________________________
MAX531
CONNECT BIPOFF
TO VOUT FOR G = 1,
TO AGND FOR G = 2,
OR TO REFIN FOR
BIPOLAR GAIN
INVERTED
R-2R DAC
DIN DOUT SCLK CS CLR
2.048V
REFIN
REFOUT
AGND DGND VDD VSS
+5V
0V TO -5V
33µF0.1µF
0.1µF
2R
2R
BIPOFF
RFB
VOUT
MAX538
MAX539
INVERTED
R-2R DAC
DIN DOUTSCLK CS
REFIN
AGND
+5V
VDD
VOUT
MAX539
ONLY
0.1µF
2R
2R
Figure 3a. MAX531 Typical Operating Circuit Figure 3b. MAX538/MAX539 Typical Operating Circuit
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
______________________________________________________________________________________ 11
MAX531
MAX538
MAX539
MICROWIRE
PORT
SCLK
DIN
CS
DOUT
SK
SO
I/O
SI
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
MAX531
MAX538
MAX539
SPI
PORT
SCLK
DIN
CS
DOUT
SCK
MOSI
I/O
MISO
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
CPOL = 0, CPHA = 0
Figure 4. Microwire Connection Figure 5. SPI/QSPI Connection
Figure 6. Unipolar Configuration (0V to +2.048V Output)
33µF
REFIN
REFOUT
AGND
DGND
VDD
VSS
BIPOFF
RFB
VOUT VOUT
0V TO -5V
+5V
G = +1
MAX531
33µF
REFIN
REFOUT
AGND
DGND
VDD
VSS
BIPOFF RFB
VOUT VOUT
0V TO -5V
+5V
G = +2
MAX531
Table 1. Unipolar Binary Code Table
(0V to VREFIN Output), Gain = +1
Figure 7. Unipolar Configuration (0V to +4.096V Output)
Table 2. Unipolar Binary Code Table
(0V to 2VREFIN Output), Gain = +2
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
(VREFIN)
4095
4096
(VREFIN)
2049
4096
(VREFIN)
2048
4096
(VREFIN)
2047
4096
(VREFIN) 1
4096
OV
= +VREFIN / 2
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
+2 (VREFIN) 4095
4096
+2 (VREFIN) 2049
4096
+2 (VREFIN) 2048
4096
+2 (VREFIN) 2047
4096
+2 (VREFIN) 1
4096
OV
= +VREFIN
MAX531/MAX538/MAX539
Single-Supply Linearity
As with any amplifier, the MAX531/MAX538/MAX539’s
output buffer can be positive or negative. When the off-
set is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.
Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply opera-
tion, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX531/MAX538/MAX539,
linearity and gain error are measured from code 11 to
code 4095. The output buffer’s offset and nonlinear
behavior do not affect monotonicity, and these DACs
are guaranteed monotonic starting with code zero. In
dual-supply operation, linearity and gain error are mea-
sured from code 0 to 4095.
Power-Supply Bypassing and
Ground Management
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommend-
ed. The two ground planes should be connected
together at the low-impedance power-supply source.
DGND and AGND should be connected together at the
chip. For the MAX531 in single-supply applications,
connect VSS to AGND at the chip. The best ground
connection may be achieved by connecting the DAC’s
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC’s
DGND is connected to the system digital ground, digi-
tal noise may get through to the DAC’s analog portion.
Bypass VDD (and VSS in dual-supply mode) with a
0.1µF ceramic capacitor, connected between VDD and
AGND (and between VSS and AGND). Mount with short
leads close to the device. Ferrite beads may also be
used to further isolate the analog and digital power
supplies.
Figures 11a and 11b illustrate the grounding and
bypassing scheme described.
Saving Power
When the DAC is not being used by the system, mini-
mize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (Table 3). If there is no output load,
minimize internal loading on the reference by setting
the DAC to all 0s (on the MAX531, use CLR). Under this
condition, REFIN is high impedance and the op amp
operates at its minimum quiescent current. Due to
these low current levels, the output settling time for an
input code close to 0 typically increases to 60µs (no
more than 100µs).
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
12 ______________________________________________________________________________________
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
Table 3. Bipolar (Offset Binary) Code
Table (-VREFIN to +VREFIN Output)
33µF
REFIN
REFOUT
AGND
DGND
BIPOFF
RFB
VOUT VOUT
-5V
+5V
MAX531
INPUT OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
(+VREFIN)
2047
2048
(+VREFIN) 1
2048
(-VREFIN) 1
2048
(-VREFIN)
2047
2048
0V
(-VREFIN)
2048
2048 = -VREFIN
AC Considerations
Digital Feedthrough
High-speed serial data at any of the digital input or output
pins may couple through the DAC package and cause
internal stray capacitance to appear at the DAC output as
noise, even though CS is held high (see
Typical Operating
Characteristics
). This digital feedthrough is tested by hold-
ing CS high, transmitting 555 hex from DIN to DOUT.
Analog Feedthrough
Because of internal stray capacitance, higher frequency
analog input signals may couple to the output as shown in
the Analog Feedthrough vs. Frequency graph in the
Typical Operating Characteristics
. It is tested by holding
CS high, setting the DAC code to all 0s, and sweeping
REFIN.
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
______________________________________________________________________________________ 13
MAX531
INVERTED
R-2R DAC
DIN DOUT
SIGNAL
IN
2.048V
REFIN
VDD VSS
2R
2R
CS CLR
BIPOFF
RFB
VOUT
REFOUT
Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The
unused REFOUT is connected to VDD.
1
2
3
4
12345678
0
POSITIVE OFFSET
NEGATIVE OFFSET
DAC CODE (LSB)
OUTPUT (LSB)
Figure 10. Single-Supply Offset
8
10
9
14
13
12
11
5
6
2
3
4
7
1
8
7
6
5
1
2
3
4
0.1µF
(b) MAX538/MAX539 BYPASSING
(a) MAX531 BYPASSING
ANALOG GROUND PLANE
0.1µF
0.1µF
Figure 11. Power-Supply Bypassing
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
14 ______________________________________________________________________________________
__Or dering Information (continued)
*Dice are specified at T
A
= +25°C only.
____Pin Configurations (continued)
1
2
3
4
14
13
12
11
RFB
VDD
VOUT
VSS
SCLK
CLR
DIN
BIPOFF
DIP/SO
TOP VIEW
MAX531
5
6
7
10
9
8
REFOUT
REFIN
AGND
DGND
DOUT
CS
___________________Chip Topography
REFIN
DOUT
( ) ARE FOR MAX531 ONLY.
0.120"
(3.048mm)
0.080"
(2.032mm)
SCLK
CS
AGND
(DGND)
(REFOUT)
(VSS)
VOUT
DIN (BIPOFF)(RFB) VDD
(CLR)
TRANSISTOR COUNT: 922
SUBSTRATE CONNECTED TO VDD
±18 SO0°C to +70°CMAX539BCSA
±18 SO-40°C to +85°CMAX539BESA ±1/28 SO-40°C to +85°CMAX539AESA ±18 Plastic DIP-40°C to +85°CMAX539BEPA ±1/28 Plastic DIP-40°C to +85°CMAX539AEPA ±1Dice*0°C to +70°CMAX539BC/D
±1/28 SO0°C to +70°CMAX539ACSA ±18 Plastic DIP0°C to +70°CMAX539BCPA ±1/28 Plastic DIP0°C to +70°C
MAX539ACPA ±18 SO-40°C to +85°CMAX538BESA ±1/28 SO-40°C to +85°CMAX538AESA ±18 Plastic DIP-40°C to +85°CMAX538BEPA ±1/28 Plastic DIP-40°C to +85°CMAX538AEPA
±18 SO0°C to +70°CMAX538BCSA ±1/28 SO0°C to +70°CMAX538ACSA ±18 Plastic DIP0°C to +70°CMAX538BCPA ±1/28 Plastic DIP0°C to +70°C
MAX538ACPA ±114 SO-40°C to +85°CMAX531BESD ±1/2
±1
14 SO-40°C to +85°CMAX531AESD
±1/2
ERROR
(LSB)
±1
14 Plastic DIP-40°C to +85°CMAX531BEPD 14 Plastic DIP-40°C to +85°CMAX531AEPD
PIN-PACKAGETEMP. RANGEPART
Dice*0°C to +70°CMAX538BC/D
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
______________________________________________________________________________________ 15
________________________________________________________Package Information
PDIPN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
__________________________________________Package Information (continued)
SOICN.EPS
