MCP6V06T-E/MNY - Microchip Technology, Inc.

MCP6V06/7/8

Features

• High DC Precision:

-V

OS Drift: ±50 nV/°C (maximum)

-V

OS: ±3 µV (maximum)

-A

OL: 125 dB (minimum)

- PSRR: 125 dB (minimum)

- CMRR: 120 dB (minimum)

-E

ni: 1.7 µVP-P (typical), f = 0.1 Hz to 10 Hz

-E

ni: 0.54 µVp-p (typical), f = 0.01 Hz to 1 Hz

• Low Power and Supply Voltages:

-I

Q: 300 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.8V to 5.5V

• Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 1.3 MHz (typical)

- Unity Gain Stable

- Available in Single and Dual

- Single with Chip Select (CS): MCP6V08

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

• FilterLab® Software

• Mindi™ Circuit Designer & Simulator

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Related Parts

• MCP6V01/2/3: Spread clock, lower offset

Description

The Microchip Technology Inc. MCP6V06/7/8 family of

operational amplifiers has input offset voltage

correction for very low offset and offset drift. These

devices have a wide gain bandwidth product (1.3 MHz,

typical) and strongly reject switching noise. They are

unity gain stable, have no 1/f noise, and have good

PSRR and CMRR. These products operate with a

single supply voltage as low as 1.8V, while drawing

300 µA/amplifier (typical) of quiescent current.

The Microchip Technology Inc. MCP6V06/7/8 op amps

are offered in single (MCP6V06), single with Chip

Select (CS) (MCP6V08), and dual (MCP6V07). They

are designed in an advanced CMOS process.

Package Types (top view)

VIN+

VIN–

VSS

VDD

VOUT

5NC

NCNC

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP6V06

SOIC

MCP6V07

SOIC

VIN+

VIN–

VSS

VDD

VOUT

5NC

MCP6V08

SOIC

MCP6V06

2x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

5NC

NCNC

* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1 .

MCP6V07

4x4 DFN *

VINA+

VINA–

VSS

VOUTB

VINB–

5VINB+

VDD

VOUTA

MCP6V08

2x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

5NC

300 µA, Auto-Zeroed Op Amps

MCP6V06/7/8

Typical Application Circuit

Offset Voltage Correction for Power Driver

MCP6V06

R1R3

MCP6XXX

VDD/2

3kΩ

VIN VOUT

MCP6V06/7/8

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD –V

SS .......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (VIN+ and VIN–) †† ... VSS – 1.0V to VDD+1.0V

All other Inputs and Outputs ............ VSS – 0.3V to VDD+0.3V

Difference Input voltage ...................................... |VDD –V

SS|

Output Short Circuit Current ................................ Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................ +150°C

ESD protection on all pins (HBM, MM) ................≥ 4 kV, 300V

†Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

†† See Section 4.2.1 “Rail-to-Rail Inputs”.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT =V

DD/2, VL=V

DD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage VOS -3 — +3 µV TA = +25°C (Note 1)

Input Offset Voltage Drift with Temperature

(linear Temp. Co.)

TC1-50 — +50 nV/°C TA = -40 to +125°C

(Note 1)

Input Offset Voltage Quadratic Temp. Co. TC2— ±0.15 — nV/°C2TA = -40 to +125°C

Power Supply Rejection PSRR 125 142 — dB (Note 1)

Input Bias Current and Impedance

Input Bias Current IB—+6—pA

Input Bias Current across Temperature IB—+140— pAT

A = +85°C

IB— +1500 +5000 pA TA = +125°C

Input Offset Current IOS —-85— pA

Input Offset Current across Temperature IOS —-85— pAT

A = +85°C

IOS -1000 -190 1000 pA TA = +125°C

Common Mode Input Impedance ZCM —10

13||6 — Ω||pF

Differential Input Impedance ZDIFF —10

13||6 — Ω||pF

Common Mode

Common-Mode Input Voltage Range VCMR VSS −0.20 — VDD +0.20 V (Note 2)

Common-Mode Rejection CMRR 120 136 — dB VDD = 1.8V,

VCM = -0.2V to 2.0V

(Note 1, Note 2)

CMRR 130 147 — dB VDD = 5.5V,

VCM = -0.2V to 5.7V

(Note 1, Note 2)

Open-Loop Gain

DC Open-Loop Gain (large signal) AOL 125 147 — dB VDD =1.8V,

VOUT = 0.2V to 1.6V (Note 1)

AOL 135 158 — dB VDD =5.5V,

VOUT = 0.2V to 5.3V (Note 1)

Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these

parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).

2: Figure 2-18 shows how VCMR changed across temperature for the first three production lots.

MCP6V06/7/8

Output

Maximum Output Voltage Swing VOL, VOH VSS +15 — V

DD −15 mV G = +2, 0.5V input overdrive

Output Short Circuit Current ISC —±7—mAV

DD =1.8V

ISC —±22— mAV

DD =5.5V

Power Supply

Supply Voltage VDD 1.8 — 5.5 V

Quiescent Current per amplifier IQ200 300 400 µA IO = 0

POR Trip Voltage VPOR 1.15 — 1.65 V

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT =V

DD/2, VL=V

DD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these

parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).

2: Figure 2-18 shows how VCMR changed across temperature for the first three production lots.

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT =V

DD/2, VL=V

DD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

Amplifier AC Response

Gain Bandwidth Product GBWP — 1.3 — MHz

Slew Rate SR — 0.5 — V/µs

Phase Margin PM — 65 — ° G = +1

Amplifier Noise Response

Input Noise Voltage Eni —0.54 — µV

P-P f = 0.01 Hz to 1 Hz

Eni —1.7 —µV

P-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —82 —nV/√Hz f < 2.5 kHz

eni —52—nV/√Hz f = 100 kHz

Input Noise Current Density ini —0.6 —fA/√Hz

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC) IMD — 32 — µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 1.8V

IMD — 25 — µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 5.5V

Amplifier Step Response

Start Up Time tSTR —500 — µs V

OS within 50 µV of its final value

Offset Correction Settling Time tSTL — 300 — µs G = +1, VIN step of 2V,

VOS within 50 µV of its final value

Output Overdrive Recovery Time tODR — 100 — µs G = -100, ±0.5V input overdrive to VDD/2,

VIN 50% point to VOUT 90% point (Note 2)

Note 1: These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD

tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry.

2: tODR includes some uncertainty due to clock edge timing.

MCP6V06/7/8

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT =V

DD/2, VL=V

DD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Typ Max Units Conditions

CS Pull-Down Resistor (MCP6V08)

CS Pull-Down Resistor RPD 35—MΩ

CS Low Specifications (MCP6V08)

CS Logic Threshold, Low VIL VSS —0.3V

DD V

CS Input Current, Low ICSL —5—pA

CS = VSS

CS High Specifications (MCP6V08)

CS Logic Threshold, High VIH 0.7VDD —V

DD V

CS Input Current, High ICSH —V

DD/RPD —pA

CS = VDD

CS Input High, GND Current per

amplifier

ISS —-0.7—µA

CS = VDD, VDD = 1.8V

ISS —-2.3—µA

CS = VDD, VDD = 5.5V

Amplifier Output Leakage, CS High IO_LEAK —20—pA

CS = VDD

CS Dynamic Specifications (MCP6V08)

CS Low to Amplifier Output On

Turn-on Time

tON — 11 100 µs CS Low = VSS+0.3 V, G = +1 V/V,

VOUT = 0.9 VDD/2

CS High to Amplifier Output High-Z tOFF —10—µs

CS High = VDD – 0.3 V, G = +1 V/V,

VOUT = 0.1 VDD/2

Internal Hysteresis VHYST —0.25—V

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C (Note 1)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 8L-2x3 TDFN θJA —41—°C/W

Thermal Resistance, 8L-4x4 DFN θJA —44—°C/W(Note 2)

Thermal Resistance, 8L-SOIC θJA — 150 — °C/W

Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

MCP6V06/7/8

1.3 Timing Diagrams

FIGURE 1-1: Amplifier Start Up.

FIGURE 1-2: Offset Correction Settling

Time.

FIGURE 1-3: Output Overdrive Recovery.

FIGURE 1-4: Chip Select (MCP6V08).

1.4 Test Circuits

The circuits used for the DC and AC tests are shown in

Figure 1-5 and Figure 1-6. Lay the bypass capacitors

out as discussed in Section 4.3.8 “Supply Bypassing

and Filtering”. RN is equal to the parallel combination

of RF and RG to minimize bias current effects.

FIGURE 1-5: AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

FIGURE 1-6: AC and DC Test Circuit for

Most Inverting Gain Conditions.

The circuit in Figure 1-7 tests the op amp input’s

dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The

potentiometer balances the resistor network (VOUT

should equal VREF at DC). The op amp’s common

mode input voltage is VCM =V

IN/2. The error at the

input (VERR) appears at VOUT with a noise gain of

10 V/V.

FIGURE 1-7: Test Circuit for Dynamic

Input Behavior.

VDD

VOS

VOS +50µV

VOS –50µV

tSTR

1.8V to 5.5V

1.8V

VIN

VOS

VOS +50µV

tSTL

VIN

VOUT

VDD

VSS

tODR

VDD/2

VIL

High-Z

tON

VIH

tOFF

VOUT

-2 µA

High-Z

ISS -2 µA

300 µA

1µA

IDD

1µA

300 µA

VDD/5 MΩ

ICS VDD/5 MΩ

5pA

(typical) (typical)

(typical)

VDD

MCP6V0X

RGRF

VOUT

VIN

VDD/3

1µF

CLRL

100 nF

RISO

VDD

MCP6V0X

RGRF

VOUT

VDD/3

VIN

1µF

CLRL

100 nF

RISO

VDD

MCP6V0X

VOUT

1µF

CLRL

100 nF

RISO

20.0 kΩ24.9 Ω

20.0 kΩ50Ω

VIN

VREF

0.1%

0.1% 25 turn

20.0 kΩ

0.1%

2.49 kΩ2.49 kΩ

MCP6V06/7/8

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.1 DC Input Precision

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset V oltage Drift.

FIGURE 2-3: Input Offset Vo ltage

Quadratic Temp Co.

FIGURE 2-4: Input Offset Voltage vs.

Power Supply Voltage with VCM =V

CMR_L.

FIGURE 2-5: Input Offset Voltage vs.

Power Supply Voltage with VCM =V

CMR_H.

FIGURE 2-6: Input Offset Voltage vs.

Output Voltage.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

Input Offset Voltage (µV)

Percentage of Occurrences

80 Samples

TA = +25°C

VDD = 1.8V and 5.5V

Soldered on PCB

10%

15%

20%

25%

-50

-40

-30

-20

-10

Input Offset Voltage Drift; TC1 (nV/°C)

Percentage of Occurrences

80 Samples

VDD = 1.8V and 5.5V

Soldered on PCB

10%

15%

20%

25%

30%

-0.4

-0.2

0.0

0.2

0.4

Input Offset Voltage's Quadratic Temp Co;

TC2 (nV/°C2)

Percentage of Occurrences

80 Samples

VDD = 1.8V and 5.5V

Soldered on PCB

-4

-3

-2

-1

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5

Power Supply Voltage (V)

Input Offset Voltage (µV)

+125°C

+85°C

+25°C

-40°C

VCM = VCMR_L

Representative Part

-4

-3

-2

-1

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5

Power Supply Voltage (V)

Input Offset Voltage (µV)

+125°C

+85°C

+25°C

-40°C

VCM = VCMR_H

Representative Part

-4

-3

-2

-1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V

VDD = 5.5V

Representative Part

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-7: Input Offset Voltage vs.

Common Mode Voltage with VDD =1.8V.

FIGURE 2-8: Input Offset Voltage vs.

Common Mode Voltage with VDD =5.5V.

FIGURE 2-9: CMRR.

FIGURE 2-10: PSRR.

FIGURE 2-11: DC Open-Loop Gain.

FIGURE 2-12: CMRR and PSRR vs.

Ambient Temperature.

-4

-3

-2

-1

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V

Representative Part

-40°C

+25°C

+85°C

+125°C

-4

-3

-2

-1

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 5.5V

Representative Part

+125°C

+85°C

+25°C

-40°C

10%

15%

20%

25%

30%

35%

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

1/CMRR (µV/V)

Percentage of Occurrences

39 Samples

TA = +25°C

Soldered on PCB

VDD = 1.8V

VDD = 5.5V

10%

12%

14%

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

1/PSRR (µV/V)

Percentage of Occurrences

40 Samples

TA = +25°C

Soldered on PCB

10%

15%

20%

25%

30%

35%

40%

45%

50%

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

1/AOL (µV/V)

Percentage of Occurrences

40 Samples

TA = +25°C

Soldered on PCB

VDD = 1.8V

VDD = 5.5V

120

125

130

135

140

145

150

155

160

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CMRR, PSRR (dB)

PSRR

CMRR

VDD = 5.5V

VDD = 1.8V

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-13: DC Open-Loop Gain vs.

Ambient Temperature.

FIGURE 2-14: Input Bias and Offset

Currents vs. Common Mode Input Vo ltage with

TA=+85°C.

FIGURE 2-15: Input Bias and Offset

Currents vs. Common Mode Input Vo ltage with

TA= +125°C.

FIGURE 2-16: Input Bias and Offset

Currents vs. Ambient Temperature with

VDD = +5.5V.

FIGURE 2-17: Input Bias Current vs. Input

Voltage (below VSS).

120

125

130

135

140

145

150

155

160

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 1.8V

-150

-100

-50

100

150

200

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

TA = +85°C

DD = 5.5V

IOS

-400

-200

200

400

600

800

1000

1200

1400

1600

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

TA = +125°C

VDD = 5.5V

IOS

100

1,000

10,000

25 35 45 55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

VDD = 5.5V

-IOS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C

+25°C

-40°C

10m

100µ

10µ

1µ

100n

10n

100p

10p

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.2 Other DC Voltages and Currents

FIGURE 2-18: Input Common Mode

Voltage Headroom (Range) vs. Ambient

Temperature.

FIGURE 2-19: Output Voltage Headroom

vs. Output Current.

FIGURE 2-20: Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-21: Output Short Circuit Current

vs. Power Supply Voltage.

FIGURE 2-22: Supply Current vs. Power

Supply Voltage.

FIGURE 2-23: Power On Reset Trip

Voltage.

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Input Common Mode Voltage

Headroom (V)

Lower (VCMR – VSS)

Upper ( VDD – VCMR)

3 Lots

100

1000

0.1 1 10

Output Current Magnitude (mA)

Output Voltage Headroom

(mV)

VDD – V

VDD

= 5.5V

VOL – V

VDD

= 1.8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Output Headroom (mV)

VDD – V

VDD

= 5.5V

VOL – VSS

VDD

= 1.8V

RL = 20 k

Ω

-40

-30

-20

-10

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Output Short Circuit Current

(mA)

-40°C

+25°C

+85°C

+125°C

+85°C

+25°C

-40°C

100

150

200

250

300

350

400

450

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Supply Current (µA)

+125°C

+85°C

+25°C

-40°C

10%

15%

20%

25%

30%

1.1

1.2

1.3

1.4

1.5

1.6

1.7

POR Trip Voltage (V)

Percentage of Occurrences

93 Samples

3 Lots

TA = +25°C

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-24: Power On Reset V oltage vs.

Ambient Temperature.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

POR Trip Voltage (V)

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.3 Frequency Response

FIGURE 2-25: CMRR and PSRR vs.

Frequency.

FIGURE 2-26: Open-Loop Gain vs.

Frequency with VDD =1.8V.

FIGURE 2-27: Open-Loop Gain vs.

Frequency with VDD =5.5V.

FIGURE 2-28: Gain Bandwidth Product

and Phase Margin vs. Ambient Temperature.

FIGURE 2-29: Gain Bandwidth Product

and Phase Margin vs. Common Mode Input

Voltage.

FIGURE 2-30: Gain Bandwidth Product

and Phase Margin vs. Output Voltage.

100

110

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

CMRR, PSRR (dB)

CMRR

PSRR+

PSRR-

10 100k1k 1M10k100

-30

-20

-10

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Open-Loop Gain (dB)

-270

-240

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

| AOL |

∠AOL

1k 10k 100k 1M 10M

VDD = 1.8V

CL = 60 pF

-30

-20

-10

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Open-Loop Gain (dB)

-270

-240

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

| AOL |

∠AOL

1k 10k 100k 1M 10M

VDD = 5.5V

CL = 60 pF

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Gain Bandwidth Product

(MHz)

100

110

120

130

Phase Margin (°)

VDD

= 5.5V

GBWP

DD = 1.8V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

100

110

120

130

Phase Margin (°)

VDD

= 5.5V

VDD

= 1.8V

GBWP

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Gain Bandwidth Product

(MHz)

100

110

120

130

Phase Margin (°)

VDD

= 5.5

VDD

= 1.8V

GBWP

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-31: Closed-Loop Output

Impedance vs. Frequency with VDD =1.8V.

FIGURE 2-32: Closed-Loop Output

Impedance vs. Frequency with VDD =5.5V.

FIGURE 2-33: Channel-to-Channel

Separation vs. Frequency.

FIGURE 2-34: Maximum Output Voltage

Swing vs. Frequency.

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

VDD = 1.8V

100k 1M 10M 100M

100

10k

G = 1 V/V

G = 10 V/V

G = 100 V/V

Open-Loop Output Impedance ( Ω)

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

VDD = 5.5V

100k 1M 10M 100M

100

10k

G = 1 V/V

G = 10 V/V

G = 100 V/V

Open-Loop Output Impedance ( Ω)

100

1.E+05 1.E+06 1.E+07

Frequency (Hz)

Channel-to-Channel

Separation (dB)

VDD

= 5.5V

VDD

= 1.8V

RTI

100k 1M 10M

0.1

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

Maximum Output Voltage

Swing (V P-P)

VDD

= 5.5V

VDD

= 1.8V

1k 10k 100k 1M

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.4 Input Noise and Distortion

FIGURE 2-35: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-36: Input Noise Voltage Density

vs. Input Common Mode Voltage.

FIGURE 2-37: Inter-Modulation Distortion

vs. Frequency with VCM Disturbance (see

Figure 1-7).

FIGURE 2-38: Inter-Modulation Distortion

vs. Frequency with VDD Distur ba n ce (see

Figure 1-7).

FIGURE 2-39: Input Noise vs. Time with

1 Hz and 10 Hz Filters and VDD =1.8V.

FIGURE 2-40: Input Noise vs. Time with

1 Hz and 10 Hz Filters and VDD =5.5V.

100

1,000

10,000

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

100

1000

Input Noise Voltage;

Eni (µVP-P)

10 1k 10k

100k

eni

Eni(0 Hz to f)

Input Noise Voltage Density;

eni (nV/√Hz)

100

DD = 5.5V

DD = 1.8V

100

120

140

160

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

VDD

= 5.5

VDD

= 1.8

Input Noise Voltage Density;

eni (nV/√Hz)

100

1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

IMD Spectrum, RTI (µV PK)

GDM = 1 V/V

VCM tone = 50 mVPK, f = 1 kHz

100 1k 10k 100k

IMD tone at DC

residual

1 kHz

tone VDD = 5.5V

VDD = 1.8V

100

1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

IMD Spectrum, RTI (µV PK)

100 1k 10k 100k

GDM = 1 V/V

VDD tone = 50 mVPK, f = 1 kHz

IMD tone at DC

1 kHz

tone VDD = 5.5V

VDD = 1.8V

0 102030405060708090100

t (s)

Input Noise Voltage; e ni(t)

(0.5 µV/div)

VDD = 1.8V

NPBW = 10 Hz

NPBW = 1 Hz

0 102030405060708090100

t (s)

Input Noise Voltage; e ni(t)

(0.5 µV/div)

VDD = 5.5V

NPBW = 10 Hz

NPBW = 1 Hz

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.5 Time Response

FIGURE 2-41: Input Offset Voltage vs.

Time with Temperat ur e Ch an g e.

FIGURE 2-42: Input Offset Voltage vs.

Time at Power Up.

FIGURE 2-43: The MCP6V06/7/8 family

shows no input phase reversal with overdrive.

FIGURE 2-44: Non-inverting Small Signal

Step Response.

FIGURE 2-45: Non-inverting Large Signal

Step Response.

FIGURE 2-46: Inverting Small Signal Step

Response.

-6

-5

-4

-3

-2

-1

0 20 40 60 80 100 120 140 160 180 200

Time (s)

Input Offset Voltage (µV)

-15

-10

-5

PCB Temperature (°C)

TPCB

VOS

Temperature increased by

using heat gun for 4 seconds.

-25

-20

-15

-10

-5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0Time (200 µs/div)

Input Offset Voltage

(mV)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Power Supply Voltage

(V)

POR Trip

Point

VOS

VDD

-1

012345678910

Time (ms)

Input, Output Voltages (V)

VDD = 5.5V

G = 1

OUT

02468101214161820

Time (µs)

Output Voltage (10 mV/div)

VDD = 5.5V

G = 1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

Output Voltage (V)

VDD = 5.5V

G = 1

012345678910

Time (µs)

Output Voltage (10 mV/div)

VDD = 5.5V

G = -1

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-47: Inverting Large Signal Step

Response.

FIGURE 2-48: Slew Rate vs. Ambient

Temperature.

FIGURE 2-49: Output Overdrive Recove ry

vs. Time with G = -100 V/V.

FIGURE 2-50: Output Overdrive Recove ry

Time vs. Inverting Gain.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25 30 35 40 45 50

Time (µs)

Output Voltage (V)

DD = 5.5V

G = -1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Slew Rate (V/µs)

Falling Edge

DD = 5.5V

DD = 1.8V

Rising Edge

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

Time (50 µs/div)

Output Voltage (V)

-1

Input Voltage × G (V/V)

VDD = 5.5V

G = -100 V/V

0.5V Overdrive

VOUT G VIN

VOUT

G VIN

100

1000

1 10 100 1000

Inverting Gain Magnitude (V/V)

Overdrive Recovery Time (µs)

0.5V Output Overdrive

tODR, low

tODR, high

DD = 1.8V

DD = 5.5V

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

2.6 Chip Select Response (MCP6V08 only)

FIGURE 2-51: Chip Select Current vs.

Power Supply Voltage.

FIGURE 2-52: Power Supply Current vs.

Chip Select Voltage with VDD =1.8V.

FIGURE 2-53: Power Supply Current vs.

Chip Select Voltage with VDD =5.5V.

FIGURE 2-54: Chip Select Current vs. Chip

Select Voltage.

FIGURE 2-55: Chip Select Voltage, Output

Voltage vs. Time with VDD =1.8V.

FIGURE 2-56: Chip Select Voltage, Output

Voltage vs. Time with VDD =5.5V.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Chip Select Current (µA)

CS = VDD

100

150

200

250

300

350

400

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Chip Select Voltage (V)

Power Supply Current (µA)

VDD = 1.8V

G = 1

VIN = 0.9V

VL = 0V

Hysteresis

Op Amp

turns on

here

Op Amp

turns off

here

100

200

300

400

500

600

0.00.51.01.52.02.53.03.54.04.55.05.5

Chip Select Voltage (V)

Power Supply Current (µA)

VDD = 5.5V

G = 1

VIN = 2.75V

VL = 0V

Hysteresis

Op Amp

turns on

here

Op Amp

turns off

here

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Chip Select Voltage (V)

Chip Select Current (µA)

DD = 5.5V

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Time (5 µs/div)

Output Voltage (V)

Chip Select Voltage (V)

VDD = 1.8V

G = +1 V/V

VIN= VDD

RL = 10 kΩ tied to VDD/2

VOUT On

VOUT OffVOUT Off

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25 30 35 40 45 50

Time (5 µs/div)

Output Voltage (V)

Chip Select Voltage (V)

VDD = 5.5V

G = +1 V/V

VIN= VDD

RL = 10 kΩ tied to VDD/2

VOUT On

VOUT OffVOUT Off

MCP6V06/7/8

Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=20kΩ to VL, CL = 60 pF, and CS = GND.

FIGURE 2-57: Chip Select Relative Logic

Thresholds vs. Ambient Temperature.

FIGURE 2-58: Chip Select Hysteresis.

FIGURE 2-59: Chip Select Turn On Time

vs. Ambient Temperature.

FIGURE 2-60: Chip Select’s Pull-down

Resistor (RPD) vs. Ambient Temperature.

FIGURE 2-61: Quiescent Current in

Shutdown vs. Power Supply Voltage.

30%

35%

40%

45%

50%

55%

60%

65%

70%

-50-25 0 255075100125

Ambient Temperature (°C)

Relative Chip Select Logic

Levels; Low and High ( )

VIL/VDD

VIH/VDD

VDD = 1.8V

VDD = 5.5V

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Chip Select Hysteresis (V)

VDD = 1.8V

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Chip Select Turn On Time

(µs)

DD = 5.5V

DD = 1.8V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Pull-down Resistor (MΩ

)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Power Supply Current (µA)

CS = V

Representative Par

+125°C

+85°C

+25°C

-40°C

MCP6V06/7/8

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Outputs

The analog output pins (VOUT) are low-impedance

voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs (VIN+, VIN–, …)

are high-impedance CMOS inputs with low bias

currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 1.8V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

3.4 Chip Select (CS) Digital Input

This pin (CS) is a CMOS, Schmitt-triggered input that

places the MCP6V08 op amps into a low power mode

of operation.

3.5 Exposed Thermal Pad (EP)

There is an internal connection between the Exposed

Thermal Pad (EP) and the VSS pin; they must be con-

nected to the same potential on the Printed Circuit

Board (PCB).

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θJA).

MCP6V06 MCP6V07 MCP6V08

Symbol Description

TDFN SOIC DFN SOIC TDFN SOIC

661166V

OUT

, VOUTA Output (op amp A)

222222V

IN–, VINA– Inverting Input (op amp A)

333333V

IN+, VINA+ Non-inverting Input

(op amp A)

444444 V

SS Negative Power Supply

—— 5 5 —— V

INB+ Non-inverting Input

(op amp B)

—— 6 6 —— V

INB– Inverting Input (op amp B)

—— 7 7 —— V

OUTB Output (op amp B)

778877 V

DD Positive Power Supply

————— 8 CS

Chip Select (op amp A)

1, 5, 8 1, 5, 8 — — 1, 5, 8 1, 5 NC No Internal Connection

9 — 9 — 9 — EP Exposed Thermal Pad (EP);

must be connected to VSS

MCP6V06/7/8

NOTES:

MCP6V06/7/8

4.0 APPLICATIONS

The MCP6V06/7/8 family of auto-zeroed op amps is

manufactured using Microchip’s state of the art CMOS

process. It is designed for low cost, low power and high

precision applications. Its low supply voltage, low

quiescent current and wide bandwidth makes the

MCP6V06/7/8 ideal for battery-powered applications.

4.1 Overview of Auto-zeroing

Operation

Figure 4-1 shows a simplified diagram of the

MCP6V06/7/8 auto-zeroed op amps. This will be used

to explain how the DC voltage errors are reduced in this

architecture.

FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram.

4.1.1 BUILDING BLOCKS

The Null Amp. and Main Amp. are designed for high

gain and accuracy using a differential topology. They

have an auxiliary input (bottom left) used for correcting

the offset voltages. Both inputs are added together

internally. The capacitors at the auxiliary inputs (CFW

and CH) hold the corrected values during normal

operation.

The Output Buffer is designed to drive external loads at

the VOUT pin. It also produces a single ended output

voltage (VREF is an internal reference voltage).

All of these switches are make-before-break in order to

minimize glitch-induced errors. They are driven by two

clock phases (φ1 and φ2) that select between normal

mode and auto-zeroing mode.

The clock is derived from an internal R-C oscillator

running at a rate of fOSC1 = 650 kHz. The oscillator’s

output is divided down to the desired rate. It is also

randomized to minimize (spread) undesired clock

tones in the output.

The internal POR ensures the part starts up in a known

good state. It also provides protection against power

supply brown out events.

The Chip Select input places the op amp in a low power

state when it is high. When it goes low, it powers the op

amp at its normal level and starts operation properly.

The Digital Control circuitry takes care of all of the

housekeeping details of the switching operation. It also

takes care of Chip Select and POR events.

VIN+

VIN–Main

Output VOUT

VREF

Amp.

Buffer

Null

Amp.

Null

Input φ1

Switches

Null

Correct

φ2

Switches

Null

Output

Switches

CFW

POR

Digital

Control

Oscillator

Clock

Randomization

φ1

φ2

MCP6V06/7/8

4.1.2 AUTO-ZEROING ACTION

Figure 4-2 shows the connections between amplifiers

during the Normal Mode of operation (φ1). The hold

capacitor (CH) corrects the Null Amplifier’s input offset.

Since the Null Amplifier has very high gain, it

dominates the signal seen by the Main Amplifier. This

greatly reduces the impact of the Main Amplifier’s input

offset voltage on overall performance. Essentially, the

Null Amplifier and Main Amplifier behave as a regular

op amp with very high gain (AOL) and very low offset

voltage (VOS).

FIGURE 4-2: Normal Mode of Operation (

1); Equivalent Amplifier Diagram.

Figure 4-3 shows the connections between amplifiers

during the Auto-zeroing Mode of operation (φ2). The

signal goes directly through the Main Amplifier, and the

flywheel capacitor (CFW) maintains a constant correc-

tion on the Main Amplifier’s offset.

The Null Amplifier uses its own high open loop gain to

drive the voltage across CH to the point where its input

offset voltage is almost zero. Because the principal

input is connected to VIN+, the auto-zeroing action

corrects the offset at the current common mode input

voltage (VCM) and supply voltage (VDD). This makes

the DC CMRR and PSRR very high also.

Since these corrections happen every 50 µs, or so, we

also minimize slow errors, including offset drift with

temperature (ΔVOS/ΔTA), 1/f noise, and input offset

aging.

FIGURE 4-3: Auto-zeroing Mode of Operation (

2); Equivalent Diagram.

4.1.3 INTERMODULATION DISTORTION

(IMD)

The MCP6V06/7/8 op amps will show intermodulation

distortion (IMD), products when an AC signal is

present.

The signal and clock can be decomposed into sine

wave tones (Fourier series components). These tones

interact with the auto-zeroing circuitry’s non-linear

response to produce IMD tones at sum and difference

frequencies. IMD distortion tones are generated about

all of the square wave clock’s harmonics. See

Figure 2-37 and Figure 2-38.

VIN+

VIN–Main

Output VOUT

VREF

Amp.

Buffer

Null

Amp.

CFW

VIN+

VIN–Main

Output VOUT

VREF

Amp.

Buffer

Null

Amp.

CFW

MCP6V06/7/8

4.2 Other Functional Blocks

4.2.1 RAIL-TO-RAIL INPUTS

The input stage of the MCP6V06/7/8 op amps uses two

differential CMOS input stages in parallel. One

operates at low common mode input voltage (VCM,

which is approximately equal to VIN+ and VIN– in nor-

mal operation) and the other at high VCM. With this

topology, the input operates with VCM up to 0.2V past

either supply rail at +25°C (see Figure 2-18). The input

offset voltage (VOS) is measured at VCM =V

SS –0.2V

and VDD + 0.2V to ensure proper operation.

The transition between the input stages occurs when

VCM ≈VDD – 0.9V (see Figure 2-7 and Figure 2-8). For

the best distortion and gain linearity, with non-inverting

gains, avoid this region of operation.

4.2.1.1 Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-43 shows an input voltage

exceeding both supplies with no phase inversion.

4.2.1.2 Input Voltage and Current Limits

The ESD protection on the inputs can be depicted as

shown in Figure 4-4. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

FIGURE 4-4: Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-5 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (VIN+

and VIN–) from going too far below ground, and the

resistors R1 and R2 limit the possible current drawn out

of the input pins. Diodes D1 and D2 prevent the input

pins (VIN+ and VIN–) from going too far above VDD, and

dump any currents onto VDD. When implemented as

shown, resistors R1 and R2 also limit the current

through D1 and D2.

FIGURE 4-5: Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of the

resistor R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN–) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (VCM) is below ground (VSS); see

Figure 2-17. Applications that are high impedance may

need to limit the usable voltage range.

4.2.2 RAIL-TO-RAIL OUTPUT

The output voltage range of the MCP6V06/7/8

auto-zeroed op amps is VDD – 15 mV (minimum) and

VSS + 15 mV (maximum) when RL=20kΩ is

connected to VDD/2 and VDD = 5.5V. Refer to

Figure 2-19 and Figure 2-20 for more information.

These op amps are designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

4.2.3 CHIP SELECT (CS)

The single MCP6V08 has a Chip Select (CS) pin.

When CS is pulled high, the supply current for the

corresponding op amp drops to about 1 µA (typical),

and is pulled through the CS pin to VSS. When this

happens, the amplifier is put into a high impedance

state. By pulling CS low, the amplifier is enabled. If the

CS pin is left floating, the internal pull-down resistor

(about 5 MΩ) will keep the part on. Figure 1-4 shows

the output voltage and supply current response to a CS

pulse.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad VIN–

MCP6V0X

VDD

R1>VSS – ( minimum expected V1)

2mA

VOUT

R2>VSS – ( minimum expected V2)

2mA

MCP6V06/7/8

4.3 Application Tips

4.3.1 INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic tempera-

ture coefficients (TC1 and TC2) of input offset voltage.

The input offset voltage, at any temperature in the

specified range, can be calculated as follows:

EQUATION 4-1:

4.3.2 DC GAIN PLOTS

Figure 2-9, Figure 2-10 and Figure 2-11 are histograms

of the reciprocals (in units of µV/V) of CMRR, PSRR

and AOL, respectively. They represent the change in

input offset voltage (VOS) with a change in common

mode input voltage (VCM), power supply voltage (VDD)

and output voltage (VOUT).

The 1/AOL histogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s

input noise. The negative values shown represent

noise, not unstable behavior. We validate the op amps’

stability by making multiple measurements of VOS;

instability would manifest itself as a greater unex-

plained variability in VOS or as the railing of the output.

4.3.3 SOURCE RESISTANCES

The input bias currents have two significant

components; switching glitches that dominate at room

temperature and below, and input ESD diode leakage

currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and

equal. This minimizes the output offset caused by the

input bias currents.

The inputs should see a resistance on the order of 10Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases, it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

4.3.4 SOURCE CAPACITANCE

The capacitances seen by the two inputs should be

small and matched. The internal switches connected to

the inputs dump charges on these capacitors; an offset

can be created if the capacitances do not match.

4.3.5 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. These auto-zeroed op amps have a different

output impedance than most op amps, due to their

unique topology.

When driving a capacitive load with these op amps, a

series resistor at the output (RISO in Figure 4-6)

improves the feedback loop’s phase margin (stability)

by making the output load resistive at higher frequen-

cies. The bandwidth will be generally lower than the

bandwidth with no capacitive load.

FIGURE 4-6: Output Resistor, RISO,

Stabilizes Capacitive Loads.

Figure 4-7 gives recommended RISO values for

different capacitive loads and is independent of the

gain.

FIGURE 4-7: Recommended RISO values

for Capacitive Loads.

VOS TA

() VOS TC1ΔTTC

2ΔT2

++=

Where:

ΔT=T

A–25°C

VOS(TA) = input offset voltage at TA

VOS = input offset voltage at +25°C

TC1= linear temperature coefficient

TC2= quadratic temperature

coefficient

RISO

VOUT

MCP6V0X

100

1000

10000

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07

CL (F)

Recommended RISO (Ω)

1p 10p 100p 1n 10n 100n

100

10k

GN < 2

GN = 5

GN = 10

MCP6V06/7/8

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify RISO's value until the

response is reasonable. Bench evaluation and

simulations with the MCP6V06 SPICE macro model

(good for all of the MCP6V06/7/8 op amps) are helpful.

4.3.6 STABILIZING OUTPUT LOADS

This family of auto-zeroed op amps has an output

impedance (Figure 2-31 and Figure 2-32) that has a

double zero when the gain is low. This can cause a

large phase shift in feedback networks that have low

resistance near the part’s bandwidth. This large phase

shift can cause stability problems.

Figure 4-8 shows one circuit example that has low

resistance near the part’s bandwidth. RF and CF set a

pole at 0.16 kHz, so the noise gain (GN) is 1 V/V at the

circuit’s bandwidth (roughly 1.3 MHz). The load seen

by the op amp’s output at 1.3 MHz is RG||RL (99Ω).

This is low enough to be a real concern.

FIGURE 4-8: Output Load Issue.

To solve this problem, increase the resistive load to at

least 3 kΩ. Methods to accomplish this task include:

• Increase RG

• Remove CF (relocate the filter)

• Add a 3 kΩ resistor at the op amp’s output that is

not in the signal path; see Figure 4-9

FIGURE 4-9: One Solution To Output

Load Issue.

4.3.7 REDUCING UNDESIRED NOISE

AND SIGNALS

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimizes random analog noise

- Reduces interfering signals

• Good PCB layout techniques:

- Minimizes crosstalk

- Minimizes parasitic capacitances and induc-

tances that interact with fast switching edges

• Good power supply design:

- Isolation from other parts

- Filtering of interference on supply line(s)

4.3.8 SUPPLY BYPASSING AND

FILTERING

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

of the pin for good high-frequency performance.

These parts also need a bulk capacitor (i.e., 1 µF or

larger) within 100 mm to provide large, slow currents.

This bulk capacitor can be shared with other low noise,

analog parts.

Additional filtering of high frequency power supply

noise (e.g., switched mode power supplies) can be

achieved using resistors. The resistors need to be

small enough to prevent a large drop in VDD for the op

amp, which would cause a reduced output range and

possible load-induced power supply noise. The resis-

tors also need to be large enough to dissipate little

power when VDD is turned on and off quickly. The cir-

cuit in Figure 4-10 gives good rejection out to 1 MHz for

switched mode power supplies. Smaller resistors and

capacitors are a better choice for designs where the

power supply is reasonably quiet.

FIGURE 4-10: Additional Supply Filtering.

MCP6V0X

10.0 kΩ

100Ω

RNVOUT

VIN

10.0 kΩ

0.1 µF

MCP6V0X

10.0 kΩ

100 Ω

VOUT

VIN

10.0 kΩ

0.1 µF

3.01 kΩ

MCP6V0X

VS_ANA

143Ω143Ω

100 µF 100 µF

0.1 µF

1/4W 1/10W

to other analog parts

MCP6V06/7/8

4.3.9 PCB DESIGN FOR DC PRECISION

In order to achieve DC precision on the order of ±1 µV,

many physical errors need to be minimized. The design

of the Printed Circuit Board (PCB), the wiring, and the

thermal environment has a strong impact on the

precision achieved. A poor PCB design can easily be

more than 100 times worse than the MCP6V06/7/8 op

amps minimum and maximum specifications.

4.3.9.1 Thermo-junctions

Any time two dissimilar metals are joined together, a

temperature dependent voltage appears across the

junction (the Seebeck or thermo-junction effect). This

effect is used in thermocouples to measure tempera-

ture. The following are examples of thermo-junctions

on a PCB:

• Components (resistors, op amps, …) soldered to

a copper pad

• Wires mechanically attached to the PCB

• Jumpers

•Solder joints

•PCB vias

Typical thermo-junctions have temperature to voltage

conversion coefficients of 10 to 100 µV/°C (sometimes

higher).

There are three basic approaches to minimizing

thermo-junction effects:

• Minimize thermal gradients

• Cancel thermo-junction voltages

• Minimize difference in thermal potential between

metals

4.3.9.2 Non-inverting and Inverting Amplifier

Layout for Thermo-junctions

Figure 4-11 shows the recommended non-inverting

and inverting gain amplifier circuits on one schematic.

Usually, to minimize the input bias current related off-

set, R1 is chosen to be R2||R3.

The guard traces (with ground vias at the ends) help

minimize the thermal gradients. The resistor layout

cancels the resistor thermal voltages, assuming the

temperature gradient is constant near the resistors:

EQUATION 4-2:

FIGURE 4-11: PCB Layout and Schematic

for Single Non-inverting and Inverting Amplifiers.

Note: Changing the orientation of the resistors

will usually cause a significant decrease in

the cancellation of the thermal voltages.

VOUT ≈VPGP

M=GND

≈-VMGM,V

P=GND

Where:

GM=R

3/R2, inverting gain magnitude

GP=1+G

M, non-inverting gain

magnitude

VOS is neglected

VOUT

MCP6V06

VOUT

MCP6V06/7/8

4.3.9.3 Difference Amplifier Layout for

Thermo-junctions

Figure 4-12 shows the recommended difference ampli-

fier circuit. Usually, we choose R1=R

2 and R3=R

The guard traces (with ground vias at the ends) help

minimize the thermal gradients. The resistor layout

cancels the resistor thermal voltages, assuming the

temperature gradient is constant near the resistors:

EQUATION 4-3:

FIGURE 4-12: PCB Layout and Schematic

for Single Difference Amplifier.

4.3.9.4 Dual Non-inverting Amplifier Layout

for Thermo-junctions

The dual op amp amplifiers shown in Figure 4-16 and

Figure 4-17 produce a non-inverting difference gain

greater than 1, and a common mode gain of 1 .They

can use the layout shown in Figure 4-13. The gain set-

ting resistors (R2) between the two sides are not com-

bined so that the thermal voltages can be canceled.

The guard traces (with ground vias at the ends) help

minimize the thermal gradients. The resistor layout

cancels the resistor thermal voltages, assuming the

temperature gradient is constant near the resistors:

EQUATION 4-4:

FIGURE 4-13: PCB Layout and Schematic

for Dual Non-inverting Amplifier.

Note: Changing the orientation of the resistors

will usually cause a significant decrease in

the cancellation of the thermal voltages.

VOUT ≈VREF +(V

P–V

M)GDM

Where:

Thermal voltages are approximately equal

GDM =R

3/R1=R

4/R2, difference gain

VOS is neglected

VOUT ≈VREF +(V

P–V

M)GDM

VOUT

MCP6V06

R1R3

VREF

VOUT

R3 VREF

Note: Changing the orientation of the resistors

will usually cause a significant decrease in

the cancellation of the thermal voltages.

(VOA –V

OB)≈(VIA –V

IB)GDM

(VOA +V

OB)/2 ≈(VIA +V

IB)/2

Where:

Thermal voltages are approximately equal

GDM =1+R

3/R2, differential mode gain

GCM = 1, common mode gain

VOS is neglected

VIB

VOA VOB

VIA

VIB

VOB

½MCP6V07

VIA

VOA

½MCP6V07

MCP6V06/7/8

4.3.9.5 Other PCB Thermal Design Tips

In cases where an individual resistor needs to have its

thermo-junction voltage cancelled, it can be split into

two equal resistors as shown in Figure 4-14. To keep

the thermal gradients near the resistors as small as

possible, the layouts are symmetrical with a ring of

metal around the outside. Make R1A =R

1B =R

1/2 and

R2A =R

2B =2R

FIGURE 4-14: PCB Layout for Individual

Resistors.

Minimize temperature gradients at critical components

(resistors, op amps, heat sources, etc.):

• Minimize exposure to gradients

- Small components

- Tight spacing

- Shield from air currents

• Align with constant temperature (contour) lines

- Place on PCB center line

• Minimize magnitude of gradients

- Select parts with lower power dissipation

- Use same metal junctions on thermo-junc-

tions that need to match

- Use metal junctions with low temperature to

voltage coefficients

- Large distance from heat sources

- Ground plane underneath (large area)

- FR4 gaps (no copper for thermal insulation)

- Series resistors inserted into traces (adds

thermal and electrical resistance)

- Use heat sinks

Make the temperature gradient point in one direction:

• Add guard traces

- Constant temperature curves follow the

traces

- Connect to ground plane

• Shape any FR4 gaps

- Constant temperature curves follow the

edges

4.3.9.6 Crosstalk

DC crosstalk causes offsets that appear as a larger

input offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

Interference from the mains (usually 50 Hz or 60 Hz),

and other AC sources, can also affect the DC perfor-

mance. Non-linear distortion can convert these signals

to multiple tones, included a DC shift in voltage. When

the signal is sampled by an ADC, these AC signals can

also be aliased to DC, causing an apparent shift in

offset.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding (e.g., encapsulant)

- Use ground plane (at least a star ground)

- Place the input signal source near to the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass

capacitors) for these auto-zeroed op amps

4.3.9.7 Miscellaneous Effects

Keep the resistances seen by the input pins as small

and as near to equal as possible to minimize bias cur-

rent related offsets.

Make the (trace) capacitances seen by the input pins

small and equal. This is helpful in minimizing switching

glitch-induced offset voltages.

Bending a coax cable with a radius that is too small

causes a small voltage drop to appear on the center or

(the tribo-electric effect). Make sure the bending radius

is large enough to keep the conductors and insulation

in full contact.

Mechanical stresses can make some capacitor types

(such as ceramic) to output small voltages. Use more

appropriate capacitor types in the signal path and

minimize mechanical stresses and vibration.

Humidity can cause electro-chemical potential voltages

to appear in a circuit. Proper PCB cleaning helps, as

does the use of encapsulants.

Note: Changing the orientation of the resistors

will usually cause a significant decrease in

the cancellation of the thermal voltages.

R1B

R1A

R2B

R2A

R1B

R1A

R2B

R2A

MCP6V06/7/8

4.4 Typical Applications

4.4.1 WHEATSTONE BRIDGE

Many sensors are configured as Wheatstone bridges.

Strain gauges and pressure sensors are two common

examples. These signals can be small and the

common mode noise large. Amplifier designs with high

differential gain are desirable.

Figure 4-15 shows how to interface to a Wheatstone

bridge with a minimum of components. Because the

circuit is not symmetric, the ADC input is single ended,

and there is a minimum of filtering, the CMRR is good

enough for moderate common mode noise.

FIGURE 4-15: Simple Design.

Figure 4-16 shows a higher performance circuit for

Wheatstone bridges. This circuit is symmetric and has

high CMRR. Using a differential input to the ADC helps

with the CMRR.

FIGURE 4-16: High Performance Des ign .

4.4.2 RTD SENSOR

The ratiometric circuit in Figure 4-17 conditions a three

wire RTD. It corrects for the sensor’s wiring resistance

by subtracting the voltage across the middle RW. The

top R1 does not change the output voltage; it balances

the op amp inputs. Failure (open) of the RTD is

detected by an out-of-range voltage.

FIGURE 4-17: RTD Sensor.

The voltages at the input of the ADC can be calculated

with the following:

VDD

100R

0.01C

MCP6V06

ADC

VDD

0.2R

3kΩ

20 kΩ

1µF

200Ω

20 kΩ

1µF

ADC

VDD

½ MCP6V07

200 Ω

3kΩ

1µF

VDD

10 nF

200Ω

100 nF

10 nF

100 nF

ADC

VDD

½ MCP6V07

2.49 kΩ

10 nF

VDD

RRTD

1µF

100Ω

3kΩ

20 kΩ

100 kΩ

2.49 kΩ

2.55 kΩ

VDM GRTD VTVB

–()GWVW

VCM VTVBGRTD 1G

–+()VW

------------------------------------------------------------------------------=

GRTD 12R

3R2

⁄⋅

GWGRTD R3R1

⁄

–=

Where:

VT= Voltage at the top of RRTD

VB= Voltage at the bottom of RRTD

VW= Voltage across top and middle

RW’s

VCM = ADC’s common mode input

VDM = ADC’s differential mode input

MCP6V06/7/8

4.4.3 THERMOCOUPLE SENSOR

Figure 4-18 shows a simplified diagram of an amplifier

and temperature sensor used in a thermocouple

application. The type K thermocouple senses the

temperature at the hot junction (THJ), and produces a

voltage at V1 proportional to THJ (in °C). The amplifier’s

gain is is set so that V4/THJ is 10 mV/°C. V3 represents

the output of a temperature sensor, which produces a

voltage proportional to the temperature (in °C) at the

cold junction (TCJ), and with a 0.50V offset. V2 is set so

that V4 is 0.50V when THJ –T

CJ is 0°C.

EQUATION 4-5:

FIGURE 4-18: Thermocouple Sensor;

Simplified Circuit.

Figure 4-19 shows a more complete implementation of

this circuit. The dashed red arrow indicates a thermally

conductive connection between the thermocouple and

the MCP9700A; it needs to be very short and have low

thermal resistance.

FIGURE 4-19: Thermocouple Sensor.

The MCP9700A senses the temperature at its physical

location. It needs to be at the same temperature as the

cold junction (TCJ), and produces V3 (Figure 4-16).

The MCP1541 produces a 4.10V output, assuming

VDD is at 5.0V. This voltage, tied to a resistor ladder of

4.100(RTH) and 1.3224(RTH), would produce a Theve-

nin equivalent of 1.00V and 250(RTH). The

1.3224(RTH) resistor is combined in parallel with the

top right RTH resistor (in Figure 4-18), producing the

0.5696(RTH) resistor.

V4 should be converted to digital, then corrected for the

thermocouple’s non-linearity. The ADC can use the

MCP1541 as its voltage reference. Alternately, an

absolute reference inside a PICmicro® can be used

instead of the MCP1541.

4.4.4 OFFSET VOLTAGE CORRECTION

Figure 4-20 shows a MCP6V06 correcting the input

offset voltage of another op amp. R2 and C2 integrate

the offset error seen at the other op amp’s input; the

integration needs to be slow enough to be stable (with

the feedback provided by R1 and R3).

FIGURE 4-20: Offset Correction.

4.4.5 PRECISION COMPARATOR

Use high gain before a comparator to improve the

latter’s performance. Do not use MCP6V06/7/8 as a

comparator by itself; the VOS correction circuitry does

not operate properly without a feedback loop.

FIGURE 4-21: Precision Comparator.

V1≈THJ(40 µV/°C)

V2= (1.00V)

V3=T

CJ(10 mV/°C) + (0.50V)

V4=250V

1+(V

2–V

≈(10 mV/°C) (THJ –T

CJ) + (0.50V)

(RTH)/250

(RTH)

(RTH)/250

(RTH)

MCP6V06

Type K

40 µV/°C

(RTH)

(hot junction

(cold junction

Thermocouple

at THJ)

at TCJ)

RTH = Thevenin Equivalent Resistance

(RTH)/250

0.5696(RTH)

(RTH)/250

(RTH)

MCP6V06

Type K

(RTH)

4.100(RTH)

MCP9700A

VDD

MCP1541

VDD

3kΩ

RTH = Thevenin Equivalent Resistance (e.g., 10 kΩ)

MCP6V06

R1R3

MCP6XXX

VDD/2

3kΩ

VIN VOUT

MCP6V06

VIN

VDD/2

MCP6541

VOUT

1kΩ

MCP6V06/7/8

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP6V06/7/8 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the MCP6V06/7/8

op amps is available on the Microchip web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation over the temperature range. See

the model file for information on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the Micro-

chip web site at www.microchip.com/filterlab, the Fil-

ter-Lab design tool provides full schematic diagrams of

the filter circuit with component values. It also outputs

the filter circuit in SPICE format, which can be used

with the macro model to simulate actual filter perfor-

mance.

5.3 Mindi™ Circuit Designer &

Simulator

Microchip’s Mindi™ Circuit Designer & Simulator aids

in the design of various circuits useful for active filter,

amplifier and power management applications. It is a

free online circuit designer & simulator available from

the Microchip web site at www.microchip.com/mindi.

This interactive circuit designer & simulator enables

designers to quickly generate circuit diagrams, and

simulate circuits. Circuits developed using the Mindi

Circuit Designer & Simulator can be downloaded to a

personal computer or workstation.

5.4 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design require-

ment. Available at no cost from the Microchip website

at www.microchip.com/maps, the MAPS is an overall

selection tool for Microchip’s product portfolio that

includes Analog, Memory, MCUs and DSCs. Using this

tool, a customer can define a filter to sort features for a

parametric search of devices and export side-by-side

technical comparison reports. Helpful links are also

provided for Data sheets, Purchase and Sampling of

Microchip parts.

5.5 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog Demon-

stration and Evaluation Boards that are designed to

help customers achieve faster time to market. For a

complete listing of these boards and their correspond-

ing user’s guides and technical information, visit the

Microchip web site at www.microchip.com/analog

tools.

Some boards that are especially useful are:

• MCP6V01 Thermocouple Auto-Zeroed Reference

Design

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP

Evaluation Board

• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP

Evaluation Board

5.6 Application Notes

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

ADN003: “Select the Right Operational Amplifier for

your Filtering Circuits”, DS21821

AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

AN723: “Operational Amplifier AC Specifications and

Applications”, DS00723

AN884: “Driving Capacitive Loads With Op Amps”,

DS00884

AN990: “Analog Sensor Conditioning Circuits – An

Overview”, DS00990

These application notes and others are listed in the

design guide:

“Signal Chain Design Guide”, DS21825

MCP6V06/7/8

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

MCP6VO6E

SN 0823

256

XXXXXX

8-Lead DFN (4x4) (MCP6V07)

XXXXXX

YYWW

NNN

Example

6V07

E/MD^^

0823

256

8-Lead TDFN (2x3) (MCP6V06, MCP6V08) Example:

XXX

YWW

AAC

838

Device Code

MCP6V06 AAC

MCP6V08 AAD

Note: Applies to 8-Lead

2x3 TDFN

MCP6V06/7/8

/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0'±[[PP%RG\>')1@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV

 3DFNDJHLVVDZVLQJXODWHG

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $   

6WDQGRII $   

&RQWDFW7KLFNQHVV $ 5()

2YHUDOO/HQJWK ' %6&

([SRVHG3DG:LGWK (   

2YHUDOO:LGWK ( %6&

([SRVHG3DG/HQJWK '   

&RQWDFW:LGWK E   

&RQWDFW/HQJWK /   

&RQWDFWWR([SRVHG3DG .  ± ±

NOTE 1

NOTE 2

NOTE 1

EXPOSED

PAD

TOP VIEW BOTTOM VIEW

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &&

MCP6V06/7/8

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 6LJQLILFDQW&KDUDFWHULVWLF

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± ±

6WDQGRII



$  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

&KDPIHURSWLRQDO K  ± 

)RRW/HQJWK /  ± 

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

0ROG'UDIW$QJOH7RS  ± 

0ROG'UDIW$QJOH%RWWRP  ± 

NOTE 1

12 3

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6V06/7/8

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP6V06/7/8

/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH01±[[PP%RG\>7')1@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP6V06/7/8

/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH01±[[PP%RG\>7')1@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP6V06/7/8

NOTES:

MCP6V06/7/8

APPENDIX A: REVISION HISTORY

Revision B (December 2008)

The following is the list of modifications:

1. Added the 8-lead, 2x3 TDFN package for the

MCP6V01 and MCP6V03 devices.

2. Added 8-lead, 2x3 TDFN package information to

Thermal Characteristic table.

3. Added information on the Exposed Thermal Pad

(EP) for the 8-lead, 2x3 TDFN and 8-lead, 4x4

DFN packages.

4. Added Section 4.3.6 “Stabilizing Output

Loads”.

5. Other minor typographical corrections.

Revision A (June 2008)

• Original Release of this Document.

MCP6V06/7/8

APPENDIX B: OFFSET RELATED

TEST SCREENS

Input offset voltage related specifications in the DC

spec table (Table 1-1) are based on bench measure-

ments (see Section 2.1 “DC Input Precision”). These

measurements are much more accurate because:

• More compact circuit

• Soldered parts on the PCB

• More time spent averaging (reduces noise)

• Better temperature control

- Reduced temperature gradients

- Greater accuracy

We use production screens to ensure the quality of our

outgoing products. These screens are set at wider lim-

its to eliminate any fliers; see Ta b l e B - 1 .

TABLE B-1: OFFSET RELATED TEST SCREENS

Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT =V

DD/2, VL=V

DD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).

Parameters Sym Min Max Units Conditions

Input Offset

Input Offset Voltage VOS -10 +10 µV TA = +25°C (Note 1, Note 2)

Input Offset Voltage Drift with Temperature

(linear Temp. Co.)

TC1——nV/°CT

A = -40 to +125°C (Note 3)

Power Supply Rejection PSRR 115 — dB (Note 1)

Common Mode

Common Mode Rejection CMRR 106 — dB VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1)

CMRR 116 — dB VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1)

Open-Loop Gain

DC Open-Loop Gain (large signal) AOL 114 — dB VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1)

AOL 122 — dB VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)

Note 1: Due to thermal junctions and other errors in the production environment, these specifications are only screened in

production.

2: VOS is also sample screened at +125°C.

3: TC1 is not measured in production.

MCP6V06/7/8

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6V06 Single Op Amp

MCP6V06T Single Op Amp

(Tape and Reel for 2x3 TDFN and SOIC)

MCP6V07 Dual Op Amp

MCP6V07T Dual Op Amp

(Tape and Reel for 4×4 DFN and SOIC)

MCP6V08 Single Op Amp with Chip Select

MCP6V08T Single Op Amp with Chip Select

(Tape and Reel for SOIC)

Temperature Range: E = -40°C to +125°C

Package: MD = Plastic Dual Flat, No-Lead (4×4x0.9 mm), 8-lead

(MCP6V07 only)

MNY * = Plastic Dual Flat, No-Lead (2×3x0.75 mm), 8-lead

(MCP6V06, MCP6V08)

SN = Plastic SOIC (150mil Body), 8-lead

* Y = nickel palladium gold manufacturing designator. Only

available on the TDFN package.

PART NO. –X /XXX

PackageTemperature

Range

Device

Examples:

a) MCP6V06T-E/SN: Extended temperature,

8LD SOIC package.

b) MCP6V06-E/MNY: Extended temperature,

8LD 2x3 TDFN package.

a) MCP6V07-E/MD: Extended temperature,

8LD 4x4 DFN package..

b) MCP6V07T-E/SN: Tape and Reel,

Extended temperature,

8LD SOIC package.

a) MCP6V08-E/SN: Extended temperature,

8LD SOIC package.

b) MCP6V08-E/MNY:Extended temperature,

8LD 2x3 TDFN package.

MCP6V06/7/8

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for th e design

and manufacture of development systems is ISO 9001:2000 certified.

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