PD - 95407A IRF1302SPbF IRF1302LPbF Benefits l l l l l l l Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free HEXFET(R) Power MOSFET D VDSS = 20V RDS(on) = 4.0m G ID = 174A S Description This Stripe Planar design of HEXFET(R) Power MOSFET utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. D2Pak IRF1302SPbF TO-262 IRF1302LPbF Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. Units 174 120 700 200 1.4 20 350 See Fig.12a, 12b, 15, 16 TBD -55 to + 175 A W W/C V mJ A mJ V/ns C 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA www.irf.com Junction-to-Case Junction-to-Ambient (PCB mount) Typ. Max. Units --- --- 0.75 40 C/W 1 07/07/10 IRF1302S/LPbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) RDS(on) VGS(th) gfs Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 20 --- --- 2.0 59 --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.021 3.3 --- --- --- --- --- --- 79 18 31 28 130 47 16 IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance --- 4.5 LS Internal Source Inductance --- 7.5 Ciss Coss Crss Coss Coss Coss eff. Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance --- --- --- --- --- --- 3600 2370 520 5710 2370 3540 V(BR)DSS V(BR)DSS/TJ IGSS Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 4.0 m VGS = 10V, ID = 104A 4.0 V VDS = 10V, ID = 250A --- S VDS = 15V, ID = 104A 20 VDS = 20V, VGS = 0V A 250 VDS = 16V, VGS = 0V, TJ = 150C 200 VGS = 20V nA -200 VGS = -20V 120 ID = 104A 27 nC VDS = 16V 46 VGS = 10V --- VDD = 11V --- ID = 104A ns --- RG = 4.5 --- VGS = 10V D Between lead, --- 6mm (0.25in.) nH G from package --- and center of die contact S --- VGS = 0V --- pF VDS = 25V --- = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 16V, = 1.0MHz --- VGS = 0V, VDS = 0V to 16V Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton 2 Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol --- --- 174 showing the A G integral reverse --- --- 700 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 104A, VGS = 0V --- 66 100 ns TJ = 25C, IF = 104A --- 130 200 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRF1302S/LPbF 10000 10000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 1000 TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 10 4.5V 20s PULSE WIDTH Tj = 25C 1000 100 4.5V 10 20s PULSE WIDTH Tj = 175C 1 1 0.1 1 10 0.1 100 1 Fig 1. Typical Output Characteristics T J = 175C 100.00 T J = 25C VDS = 15V 20s PULSE WIDTH 5.0 6.0 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 7.0 I D = 174A 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current () 2.0 4.0 100 Fig 2. Typical Output Characteristics 1000.00 10.00 10 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) 1.0 0.5 V GS = 10V 0.0 -60 -40 -20 0 20 40 60 80 TJ , Junction Temperature 100 120 140 160 180 ( C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF1302S/LPbF 100000 12 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd VGS , Gate-to-Source Voltage (V) C, Capacitance(pF) Ciss Coss 1000 Crss 7 5 2 100 0 1 10 0 100 20 10000 ID , Drain-to-Source Current (A) 1000 I SD , Reverse Drain Current (A) 60 TJ = 175 C OPERATION IN THIS AREA LIMITED BY R DS(on) 100sec 100 TJ = 25 C V GS = 0 V 0.1 0.2 0.7 100 1000 10 1 80 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100 40 QG, Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 1.2 1.7 V SD,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 VDS = 16V 10 Coss = Cds + Cgd 10000 I D = 104A 2.2 1msec 10 10msec Tc = 25C Tj = 175C Single Pulse 1 1 10 100 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF1302S/LPbF 175 VGS 131 ID , Drain Current (A) RD VDS LIMITED BY PACKAGE D.U.T. RG + -VDD 10V 88 Pulse Width 1 s Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit 44 VDS 90% 0 25 50 75 100 125 TC , Case Temperature 150 175 ( C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms (Z thJC ) 1 D = 0.50 Thermal Response 0.20 0.1 0.10 P DM 0.05 0.02 t1 SINGLE PULSE (THERMAL RESPONSE) t2 0.01 Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t 2 J = P DM x Z thJC +TC 0.1 1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRF1302S/LPbF 700 15V ID 43A 74A TOP + V - DD IAS 20V 0.01 tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp A EAS , Single Pulse Avalanche Energy (mJ) D.U.T RG 560 DRIVER L VDS BOTTOM 420 280 140 0 25 50 75 100 125 Starting Tj, Junction Temperature I AS 104A 150 175 ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms QG QGS QGD 4.0 VG Charge Fig 13a. Basic Gate Charge Waveform Current Regulator Same Type as D.U.T. 50K 12V .2F .3F D.U.T. + V - DS VGS(th) Gate threshold Voltage (V) 10 V 3.0 ID = 250A 2.0 1.0 -75 -50 -25 VGS 0 25 50 75 100 125 150 175 T J , Temperature ( C ) 3mA IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6 Fig 14. Threshold Voltage Vs. Temperature www.irf.com IRF1302S/LPbF 1000 Duty Cycle = Single Pulse Avalanche Current (A) 0.01 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 100 0.05 0.10 10 1 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 410 TOP Single Pulse BOTTOM 10% Duty Cycle ID = 104A EAR , Avalanche Energy (mJ) 360 310 260 210 160 110 60 10 25 50 75 100 125 Starting T J , Junction Temperature (C) Fig 16. Maximum Avalanche Energy Vs. Temperature www.irf.com 150 Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav 7 IRF1302S/LPbF Peak Diode Recovery dv/dt Test Circuit + D.U.T* Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + RG * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test V GS * + - V DD Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode [VDD] Forward Drop Inductor Curent Ripple 5% [ISD] *** VGS = 5.0V for Logic Level and 3V Drive Devices 8 Fig 17. For N-channel HEXFET(R) power MOSFETs www.irf.com IRF1302S/LPbF D2Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D2Pak (TO-263AB) Part Marking Information T HIS IS AN IRF 530S WIT H LOT CODE 8024 AS SEMBLED ON WW 02, 2000 IN T HE ASSE MBLY LINE "L" INT ERNAT IONAL RECT IF IE R LOGO ASSE MBLY LOT CODE PART NUMBER F 530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L OR INTERNAT IONAL RECTIF IER LOGO ASSEMBLY LOT CODE PART NUMBER F 530S DAT E CODE P = DESIGNAT ES LEAD - F REE PRODUCT (OPT IONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SIT E CODE Notes: 1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9 IRF1302S/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 ASS EMBLED ON WW 19, 1997 IN THE AS SEMBLY LINE "C" INTERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C OR INT ERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S ITE CODE Notes: 1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ 10 www.irf.com IRF1302S/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 11.60 (.457) 11.40 (.449) 1.65 (.065) 0.368 (.0145) 0.342 (.0135) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 1.75 (.069) 1.25 (.049) 10.90 (.429) 10.70 (.421) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. Notes: 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Starting TJ = 25C, L = 0.063mH RG = 25, IAS = 104A. (See Figure 12). ISD 104A, di/dt 100A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/2010 www.irf.com 11