PIC16F1513-E/SP - Microchip Technology

 2012 Microchip Technology Inc. Preliminary DS41624A

PIC16(L)F1512/1513

Data Sheet

28-Pin Flash Microcontrollers

with XLP Technology

DS41624A-page 2 Preliminary  2012 Microchip Technology Inc.

Information contained in this publication regarding device

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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

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FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

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chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

ISBN: 9781620761014

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

 2012 Microchip Technology Inc. Preliminary DS41624A-page 3

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Up to 7 Kbytes Linear Program Memory

Addressing

• Up to 256 Bytes Linear Data Memory Addressing

• Operating Speed:

- DC – 20 MHz clock input @ 2.5V

- DC – 16 MHz clock input @ 1.8V

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequency range from

16 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• External Oscillator Block with:

- Four crystal/resonator modes up to 20 MHz

- Three external clock modes up to 20 MHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Oscillator Start-up Timer (OST)

Analog Features:

• Analog-to-Digital Converter (ADC):

- 10-bit resolution

- Up to 17 channels

- Special Event Triggers

- Conversion available during Sleep

- Hardware Capacitive Voltage Divider (CVD)

- Double sample conversions

- Two result registers

- Inverted acquisition

- 7-bit pre-charge timer

- 7-bit acquisition timer

- Two guard ring output drives

- Adjustable sample and hold capacitor array

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

• Integrated Temperature Indicator

Extreme Low-Power Management

PIC16LF1512/3 with nanoWatt XLP:

• Sleep mode: 20 nA @ 1.8V, typical

• Watchdog Timer: 300 nA @ 1.8V, typical

• Secondary Oscillator: 600 nA @ 32 kHz, 1.8V,

typical

• Operating Current: 30 A/MHz @ 1.8V, typical

Special Microcontroller Features:

• Operating Voltage Range:

- 2.3V-5.5V (PIC16F1512/3)

- 1.8V-3.6V (PIC16LF1512/3)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Low-Power Brown-out Reset

(LPBOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via

Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Programmable Code Protection

• Low-Power Sleep mode

• 128 Bytes High-Endurance Flash:

- 100,000 write Flash endurance (minimum)

Peripheral Highlights:

• Up to 25 I/O Pins (1 input-only pin):

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable interrupt-on-change

(IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Low-power 32 kHz secondary oscillator driver

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

• Two Capture/Compare (CCP) modules:

• Master Synchronous Serial Port (MSSP) with SPI

and I2CTM with:

- 7-bit address masking

- SMBus/PMBusTM compatibility

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module:

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

- Auto-wake-up on start

PIC16(L)F1512/3

28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1512/3

DS41624A-page 4 Preliminary  2012 Microchip Technology Inc.

PIC16(L)F151X/152X Family Types

FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1512/3

Device

Data Sheet Index

Program Memory

Flash (words)

Data SRAM

(bytes)

I/O’s(2)

ADC

Timers

(8/16-bit)

EUSART

MSSP (I2C™/SPI)

CCP

Debug(1)

XLP

10-bit (ch)

Advanced Control

PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 2 I Y

PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 2 I Y

PIC16(L)F1516 (2) 8192 512 25 17 N2/1 1 1 2 I Y

PIC16(L)F1517 (2) 8192 512 36 28 N2/1 1 1 2 I Y

PIC16(L)F1518 (2) 16384 1024 25 17 N2/1 1 1 2 I Y

PIC16(L)F1519 (2) 16384 1024 36 28 N2/1 1 1 2 I Y

PIC16(L)F1526 (3) 8192 768 54 30 N6/3 2 2 10 I Y

PIC16(L)F1527 (3) 16384 1536 54 30 N6/3 2 2 10 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: Future Product PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit microcontrollers.

2: DS41452 PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs.

3: DS41458 PIC16(L)F1526/27 Data Sheet, 64-Pin Flash, 8-bit MCUs.

28-Pin SPDIP, SOIC, SSOP

PIC16F1512/3

PIC16LF1512/3

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6/ICSPCLK/ICDCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

14 15

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7/ICSPDAT/ICDDAT

 2012 Microchip Technology Inc. Preliminary DS41624A-page 5

PIC16(L)F1512/3

FIGURE 2: 28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1512/3

RC0

RB7/ICSPDAT/ICDDAT

RB6/ICSPCLK/ICDCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

RE3/MCLR/VPP

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC1

RC2

RC3

PIC16F1512/3

PIC16LF1512/3

28-Pin UQFN

PIC16(L)F1512/3

DS41624A-page 6 Preliminary  2012 Microchip Technology Inc.

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3)

I/O

28-Pin SPDIP, SOIC, SSOP

28-Pin UQFN

A/D

Timers

CCP

EUSART

MSSP

Interrupt

Pull-up

Basic

RA0 227 AN0 — — — SS(2) — — —

RA1328AN1 — ——— —— —

RA2 4 1 AN2 — — — — — — —

RA3 5 2 AN3/VREF+ — ——— —— —

RA4 6 3 — T0CKI — — — — — —

RA5 7 4 AN4 — — — SS(1) —— VCAP

RA6 10 7 — — — — — — — OSC2/CLKOUT

RA7 9 6 — — — — — — — OSC1/CLKIN

RB0 21 18 AN12 — — — — INT/IOC Y —

RB1 22 19 AN10 — — — — IOC Y —

RB2 23 20 AN8 — — — — IOC Y —

RB3 24 21 AN9 — CCP2(2) ——IOCY —

RB4 25 22 AN11

ADOUT

— — — — IOC Y —

RB5 26 23 AN13 T1G — — — IOC Y —

RB6 27 24 ADGRDA — — — — IOC YICSPCLK/ICDCLK

RB7 28 25 ADGRDB — — — — IOC Y ICSPDAT/ICDDAT

RC0 11 8 — SOSCO/T1CKI — — — — — —

RC1 12 9 — SOSCI CCP2(1) —— —— —

RC2 13 10 AN14 —CCP1 — — — — —

RC3 14 11 AN15 — — — SCK/SCL — — —

RC4 15 12 AN16 — — — SDI/SDA — — —

RC5 16 13 AN17 — — — SDO — — —

RC6 17 14 AN18 — — TX/CK — — — —

RC7 18 15 AN19 — — RX/DT — — — —

RE3 1 26 — — — — — — Y MCLR/VPP

VDD 20 17 — — — — — — — —

VSS 8,19 5,16 — — — — — — — —

NC — — — — — — — — — —

Note 1: Peripheral pin location selected using APFCON register. Default location.

2: Peripheral pin location selected using APFCON register. Alternate location.

 2012 Microchip Technology Inc. Preliminary DS41624A-page 7

PIC16(L)F1512/3

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 13

3.0 Memory Organization ................................................................................................................................................................. 15

4.0 Device Configuration.................................................................................................................................................................. 37

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 43

6.0 Resets ........................................................................................................................................................................................ 59

7.0 Interrupts .................................................................................................................................................................................... 67

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 79

9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 83

10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 85

11.0 Flash Program Memory Control ................................................................................................................................................. 89

12.0 I/O Ports ................................................................................................................................................................................... 105

13.0 Interrupt-On-Change ................................................................................................................................................................ 121

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 125

15.0 Temperature Indicator Module ................................................................................................................................................. 127

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129

17.0 Timer0 Module ......................................................................................................................................................................... 163

18.0 Timer1 Module with Gate Control............................................................................................................................................. 167

19.0 Timer2 Module ......................................................................................................................................................................... 179

20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 183

21.0 Capture/Compare/PWM Modules ............................................................................................................................................ 235

22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 245

23.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 275

24.0 Instruction Set Summary.......................................................................................................................................................... 279

25.0 Electrical Specifications............................................................................................................................................................ 293

26.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 321

27.0 Development Support............................................................................................................................................................... 323

28.0 Packaging Information.............................................................................................................................................................. 327

The Microchip Web Site..................................................................................................................................................................... 345

Customer Change Notification Service .............................................................................................................................................. 345

Customer Support .............................................................................................................................................................................. 345

Reader Response .............................................................................................................................................................................. 346

Product Identification System ............................................................................................................................................................ 347

PIC16(L)F1512/3

DS41624A-page 8 Preliminary  2012 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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welcome your feedback.

Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer Notification System

 2012 Microchip Technology Inc. Preliminary DS41624A-page 9

PIC16(L)F1512/3

1.0 DEVICE OVERVIEW

The PIC16(L)F1512/3 are described within this data

sheet. They are available in 28-pin packages. Figure 1-1

shows a block diagram of the PIC16(L)F1512/3 devices.

Table 1-2 shows the pinout descriptions.

Reference Tab l e 1 - 1 for peripherals available per

device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1512

PIC16(L)F1513

Analog-to-Digital Converter (ADC) ●●

Fixed Voltage Reference (FVR) ●●

Temperature Indicator ●●

Capture/Compare/PWM Modules

CCP1 ●●

CCP2 ●●

EUSARTs

EUSART ●●

Master Synchronous Serial Ports

MSSP ●●

Timers

Timer0 ●●

Timer1 ●●

Timer2 ●●

PIC16(L)F1512/3

DS41624A-page 10 Preliminary  2012 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM

PORTB

Timer2MSSP

Timer0

CCP2

ADC

10-Bit

CCP1

Note 1: See applicable chapters for more information on peripherals.

2: See Ta b le 1 - 1 for peripherals available on specific devices.

CPU

Program

Flash Memory

PORTA

RAM

Timing

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Timer1

OSC1/CLKIN

OSC2/CLKOUT

FVR

PORTC

PORTE

Tem p.

Indicator

EUSART

 2012 Microchip Technology Inc. Preliminary DS41624A-page 11

PIC16(L)F1512/3

TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION

Name Function Input

Type

Output

Type Description

RA0/AN0/SS(2) RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

SS ST — Slave Select input.

RA1/AN1 RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

RA2/AN2 RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

RA3/AN3/VREF+ RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

VREF+ AN — A/D Positive Voltage Reference input.

RA4/T0CKI RA4 TTL CMOS General purpose I/O.

T0CKI ST — Timer0 clock input.

RA5/AN4/SS(1)/VCAP RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

SS ST — Slave Select input.

VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1512/3 only).

RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN ST — External clock input (EC mode).

RB0/AN12/INT RB0 TTL CMOS General purpose I/O with IOC and WPU.

AN12 AN — A/D Channel 12 input.

INT ST — External interrupt.

RB1/AN10 RB1 TTL CMOS General purpose I/O with IOC and WPU.

AN10 AN — A/D Channel 10 input.

RB2/AN8 RB2 TTL CMOS General purpose I/O with IOC and WPU.

AN8 AN — A/D Channel 8 input.

RB3/AN9/CCP2(2) RB3 TTL CMOS General purpose I/O with IOC and WPU.

AN9 AN — A/D Channel 9 input.

CCP2 ST CMOS Capture/Compare/PWM 2.

RB4/AN11/ADOUT RB4 TTL CMOS General purpose I/O with IOC and WPU.

AN11 AN — A/D Channel 11 input.

ADOUT CMOS — A/D with CVD output.

RB5/AN13/T1G RB5 TTL CMOS General purpose I/O with IOC and WPU.

AN13 AN — A/D Channel 13 input.

T1G ST — Timer1 Gate input.

RB6/ICSPCLK/ADGRDA RB6 TTL CMOS General purpose I/O with IOC and WPU.

ICSPCLK ST CMOS In-Circuit Data I/O.

ADGRDA — CMOS Guard Ring output A.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.

2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.

PIC16(L)F1512/3

DS41624A-page 12 Preliminary  2012 Microchip Technology Inc.

RB7/ICSPDAT/ADGRDB RB7 TTL CMOS General purpose I/O with IOC and WPU.

ICSPDAT ST CMOS ICSP™ Data I/O.

ADGRDB — CMOS Guard Ring output B.

RC0/SOSCO/T1CKI RC0 ST CMOS General purpose I/O.

SOSCO — XTAL Secondary oscillator connection.

T1CKI ST — Timer1 clock input.

RC1/SOSCI/CCP2(1) RC1 ST CMOS General purpose I/O.

SOSCI — XTAL Secondary oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM 2.

RC2/AN14/CCP1 RC2 ST CMOS General purpose I/O.

AN14 AN — A/D Channel 14 input.

CCP1 ST CMOS Capture/Compare/PWM 1.

RC3/AN15/SCK/SCL RC3 ST CMOS General purpose I/O.

AN15 AN — A/D Channel 15 input.

SCK ST CMOS SPI clock.

SCL I2C™ OD I2C™ clock.

RC4/AN16/SDI/SDA RC4 ST CMOS General purpose I/O.

AN16 AN — A/D Channel 16 input.

SDI ST — SPI data input.

SDA I2C™ OD I2C™ data input/output.

RC5/AN17/SDO RC5 ST CMOS General purpose I/O.

AN17 AN — A/D Channel 17 input.

SDO — CMOS SPI data output.

RC6/AN18/TX/CK RC6 ST CMOS General purpose I/O.

AN18 AN — A/D Channel 18 input.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC7/AN19/RX/DT RC7 ST CMOS General purpose I/O.

AN19 AN — A/D Channel 19 input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

RE3/MCLR/VPP RE3 ST — General purpose input with WPU.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.

2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.

 2012 Microchip Technology Inc. Preliminary DS41624A-page 13

PIC16(L)F1512/3

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”,

for more information.

2.2 16-Level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register and, if enabled, will cause a soft-

ware Reset. See Section 3.4 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 24.0 “Instruction Set Summary” for more

details.

PIC16(L)F1512/3

DS41624A-page 14 Preliminary  2012 Microchip Technology Inc.

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VDD

Brown-out

Reset

VSS

Internal

Oscillator

Block

Configuration

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

15 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

 2012 Microchip Technology Inc. Preliminary DS41624A-page 15

PIC16(L)F1512/3

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for these devices. Accessing a location

above these boundaries will cause a wrap-around within

the implemented memory space. The Reset vector is at

0000h and the interrupt vector is at 0004h (see

Figure 3-1 and Figure 3-2).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16F1512

PIC16LF1512 2,048 07FFh

PIC16F1513

PIC16LF1513 4,096 0FFFh

PIC16(L)F1512/3

DS41624A-page 16 Preliminary  2012 Microchip Technology Inc.

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1512 PARTS

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1513 PARTS

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory Page 0

07FFh

Wraps to Page 0

0800h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 0 7FFFh

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

 2012 Microchip Technology Inc. Preliminary DS41624A-page 17

PIC16(L)F1512/3

3.1.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIW instruction will place the

lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

CALL constants

;… THE CONSTANT IS IN W

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

PIC16(L)F1512/3

DS41624A-page 18 Preliminary  2012 Microchip Technology Inc.

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

Data memory uses a 12-bit address. The upper 7 bits

of the address define the Bank address and the lower

5 bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Ta bl e 3- 2 . For detailed

information, see Table 3-8.

TABLE 3-2: CORE REGISTERS

Addresses BANKx

x00h or x80h INDF0

x01h or x81h INDF1

x02h or x82h PCL

x03h or x83h STATUS

x04h or x84h FSR0L

x05h or x85h FSR0H

x06h or x86h FSR1L

x07h or x87h FSR1H

x08h or x88h BSR

x09h or x89h WREG

x0Ah or x8Ah PCLATH

x0Bh or x8Bh INTCON

 2012 Microchip Technology Inc. Preliminary DS41624A-page 19

PIC16(L)F1512/3

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 24.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand.

PIC16(L)F1512/3

DS41624A-page 20 Preliminary  2012 Microchip Technology Inc.

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the

appropriate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1512/3 are as shown

in Table 3-4 through Tabl e 3 -7 .

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

 2012 Microchip Technology Inc. Preliminary DS41624A-page 21

PIC16(L)F1512/3

TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: PIC16F1512 only.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Tab l e 3- 2)

080h

Core Registers

(Tab l e 3- 2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch —

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh —28Eh—30Eh—38Eh—

00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h PORTE 090h TRISE 110h —190h— 210h WPUE 290h — 310h — 390h —

011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h —

012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h —

013h —093h—113h— 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h —

014h —094h—114h— 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP

015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN

016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF

017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h —

018h T1CON 098h —118h—198h—218h— 298h CCPR2L 318h — 398h —

019h T1GCON 099h OSCCON 119h — 199h RCREG 219h — 299h CCPR2H 319h — 399h —

01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah —39Ah—

01Bh PR2 09Bh ADRES0L 11Bh — 19Bh SPBRGL 21Bh —29Bh—31Bh—39Bh—

01Ch T2CON 09Ch ADRES0H 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —

01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh —

01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh—

01Fh —09Fh—11Fh— 19Fh BAUDCON 21Fh —29Fh—31Fh—39Fh—

020h

General

Purpose

80 Bytes

0A0h General Purpose

32 Bytes

120h

Unimplemented

Read as ‘0’

1A0h

Unimplemented

Read as ‘0’

220h

Unimplemented

Read as ‘0’

2A0h

Unimplemented

Read as ‘0’

320h

Unimplemented

Read as ‘0’

3A0h

Unimplemented

Read as ‘0’

0BFh

0C0h Unimplemented

Read as ‘0’

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h

Common RAM

0F0h Common RAM

(Accesses

70h – 7Fh)

170h Common RAM

(Accesses

70h – 7Fh)

1F0h Common RAM

(Accesses

70h – 7Fh)

270h Common RAM

(Accesses

70h – 7Fh)

2F0h Common RAM

(Accesses

70h – 7Fh)

370h Common RAM

(Accesses

70h – 7Fh)

3F0h Common RAM

(Accesses

70h – 7Fh)

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

PIC16(L)F1512/3

DS41624A-page 22 Preliminary  2012 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1513 MEMORY MAP (BANKS 0-7)

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: PIC16F1513 only.