Philips Semiconductors Power Diodes Thermal Considerations Thermal resistance Circuit performance and long term reliability are affected by the temperature of the chip. Normally, both are improved by keeping the chip temperature (junction temperature) low. Heat radiates from the package `1' to ambient. Heat conducts via leads `2', and solder joints `3' to the substrate `4'. Electrical power dissipated in any semiconductor device is a source of heat. This increases the temperature of the chip with regard to some reference point, normally an ambient temperature of o 25 C in still air. The size of the increase in temperature depends on the amount of power dissipated in the device and the net thermal resistance between the heat source and the reference point. This can be expressed with the following formula: Rth j -a = Rth j -tp + Rth tp -a The thermal resistance for surface mounted devices therefore, can be expressed as: see Fig:2) where: Rth j-a is the thermal resistance from junction to ambient Rth j-tp is the thermal resistance from junction to tie point Rth tp-a is the thermal resistance from the tie-point to ambient. j = Ptot x Rth j-a where: j is the increase in junction temperature. Ptot is the total power generated in the device Rth j-a is the thermal resistance from junction to ambient. Surface mounted devices Heat transfer can occur by radiation, conduction and convection. Surface mounted devices lose most of their heat by conduction when mounted on a substrate. Referring to Fig:1, heat conducts from its source (the junction) via the package leads and soldered connections to the substrate. Some heat radiates from the package into the surrounding air, where it is dispersed by convection or by forced cooling air. heat that radiates from the substrate is dispersed in the same way. junction Rth j-tp tie point Rth j-a Rth tp-a ambient Figure 2: Representation of thermal resistance for a surface mounted device. 1 2 2 3 3 4 Figure 1: Heat losses The Rth j-tp value is essentially independent of external mounting method and cooling air, but is sensitive to the materials used in the package construction, the chip bonding method and the chip area, all of which are fixed. The Rth tp-a value depends on the shape and material of the tracks and substrate. For all package types typical values are given in Table:1 for mounting on (FR4) printed-circuit board with small pad area. The maximum power handling capability (Ptot given by: max) is Philips Semiconductors Power Diodes Ptot max (T = j max - Tamb Thermal Considerations ) Rth j -a where: Tj max is the maximum junction temperature Tamb is the ambient temperature Calculating this maximum power handling capability we have to take into account the maximum junction temperature of the particular device, the maximum o temperature of the solder joints (110 C for long time reliability) and the ambient temperature. Dependent on the ratio of the component parts of the thermal resistance, it is possible that the junction temperature or the temperature of the solder joints (Ttp) will be the limiting factor. This can be shown in the following examples for SOT23 and SOD87 packages mounted on FR4 printed circuit board. o o Tamb = 25 C; Tj = Tj max; Ttp < 110 C Leaded devices Figure:3 illustrates the various components of thermal resistance for an axial leaded diode mounted with symmetrical, equal length leads. The thermal resistance from junction to ambient (Rthj-a) comprises the following thermal resistances: Rth j-p is the thermal resistance from junction package. Rth p-tp is the thermal resistance from package to point Rth tp-a is the thermal resistance from tie-point ambient. Rth p-a is the thermal resistance from package ambient. max = (T j max - Tamb ) to to Rth j-p Rth j -a (150 C - 25 C) = 0.25 W = o tie junction EXAMPLE FOR THE SOT23 PACKAGE Ptot to o package 500 K / W Rth p-tp Rth j-a Ttp = Tamb + Ptot max xRth tp -a tie-point = 25o C + 0.25Wx150 K / W = 62.5o C Rth p-a Rth tp-a o This is below 110 C so Tjmax is the limiting factor EXAMPLE FOR THE SOD87 PACKAGE Ptot max (T = j max - Tamb ) o 150 K / W Ttp = Tamb + Ptot max xRth tp - a = 25o C + 1Wx120 K / W = 145o C o This is above 110 C so the Ptot will be limited by Ttp, therefore: Ptot max = = ( Ttp max - Tamb ) Rth tp - a (110 C - 25 C) = 0.71 W o Figure 3: Representation of thermal resistance for a leaded device. Rth j -a (175 C - 25 C) = 1 W = o ambient o 120 K / W The Ptot values given in Table:1 are based on: The values of the thermal components depend on the package type, the lead length and the mounting method used. Using the model in Fig:3 and referring to Table:2, values for the thermal resistance from junction to ambient can be calculated using the formula: R j - a = Rth j - p + ( Rth p -a Rth p -tp + Rth tp -a ) Rth p - a + Rth p -tp + Rth tp -a The maximum power handling capability (Ptot given by: Ptot max = (T j max - Tamb Rth j -a ) max) is Philips Semiconductors Power Diodes Thermal Considerations where: Tj max is the maximum junction temperature Tamb is the ambient temperature. Table 1 Thermal resistance values and maximum power handling capability of surface mounted packages. Calculating the maximum power handling capability we have to take into account the maximum junction temperature of the particular device, the maximum o temperature of the solder joints (110 C for long time reliability) and the ambient temperature. Dependent on the ratio of the component parts of the thermal resistance it is possible that the junction temperature or the temperature of the solder joints (Ttp) will be the limiting factor. This can be shown in the following examples for a SOD57 devices mounted on a FR4 printed circuit board, as shown in Fig:4. EXAMPLE FOR SOD57 DEVICE R j - a = 14 K / W + 429 K / W (38 K./W + 70 K / W ) 429 K / W + 38 K / W + 70 K / W = 100K / W and: Ptot (T = max j max - Tamb PACKAGE Rth j-a Rth j-tp Rth tp-a Ptot (K/W) (K/W) (K/W) max (W) SOD87 150 30 120 0.71 SOD106 (A) 150 25 125 0.68 SOT23 500 330 170 0.25 SOT89 125 15 100 0.85 SOT223 85 15 70 1.21 SOT323 (SC70-3) 625 300 325 0.20 SOT363 (SC70-6) 415 200 215 0.30 SOT457 300 150 150 0.42 SO8 (SOT96-1) 155 35 115 0.74 SO20 (SOT163-1) 100 30 70 1.21 SSOP16 (SOT338-1) 145 75 70 0.86 SSOP24 (SOT340-1) 105 35 70 1.19 Note: All thermal resistance values are typical. ) 50 Rth j -a (175 C - 60 C) = 115 = . W o o 100 K / W Ttp = Tamb + 50 Rth p -a x Rth tp -a Rth p - a + Rth p - tp + Rth tp - a x Ptot using values in Table:2: Ttp = Tamb + 429 K / W x 70 K / W x Ptot 429 K / W + 38 K / W + 70 K / W 7 2 is simplified to: Ttp = Tamb + 56 K / W x Ptot o 25 o using Ttp = 110 C and Tamb = 60 C the equation becomes: Ptot = Ptot = (T tp - Tamb 3 ) 56 K / W 110o C - 60o C ( 56 K / W ) = 0.89W Figure 4: Leaded device mounted on printed circuit board 50 x 50 mm. o This is lower than Ptot max = 1.15 W (for Tj max = 175 C) o so in this particular case Ttp = 110 C is limiting the Ptot.max. Philips Semiconductors Power Diodes Thermal Considerations Table 2: Thermal resistance values for leaded packages THERMAL RESISTANCE Rth j-p (junction to package) Rth p-tp (package to tie-point) Rth p-a (package to ambient) Rth tp-a (tie-point to ambient) Notes: 1. 2. 3. 4. CONDITIONS lead length = 5 mm lead length = 10 mm lead length = 15 mm lead length = 20 mm lead length = 25 mm lead length = 5 mm lead length = 10 mm lead length = 15 mm lead length = 20 mm lead length = 25 mm notes: 1 and 2 notes: 1 and 3 notes: 1 and 4 SOD57 SOD88A 14 SOD61 SOD81 60 SOD64 SOD83A 10 19 38 57 76 95 586 429 338 279 237 70 55 45 48 96 144 192 240 1261 843 633 507 423 70 55 45 7 14 21 28 35 417 293 225 183 154 70 55 45 19 38 57 76 95 787 527 396 317 264 70 55 45 28 Device mounted on a 1.5 m thick epoxy-glass printed circuit board with a copper thickness > 40m. Mounted as in Fig:4. 2 Mounted with copper laminate per lead of 1 cm 2 Mounted with copper laminate per lead of 2.25 cm Philips Semiconductors Power Diodes Thermal Considerations Further thermal resistance data for surface mounted power packages. The results tabulated below are the results of a laboratory investigation into the effect of pcb pad area and power dissipation on thermal resistance. The results were obtained with the test samples positioned vertically in still air. As the power dissipation is increased, the thermal resistance decreases slightly. This is because, as the power dissipation increases, the resulting higher junction temperature causes increased losses due to radiation and natural convection. Table 3: SOT223 PACKAGE (Rth Junction to Ambient) HEATSINK PCB PAD AREA (mm2) 20 49 81 144 256 484 900 POWER DISSIPATION (W) 0.5W 110 99 91 88 78 73 68 1W 110 98 90 87 79 74 69 1.5W 90 86 78 73 69 Table 4: SOT428 PACKAGE (Rth Junction to Ambient) HEATSINK PCB PAD AREA (mm2) 20 49 81 144 256 484 900 POWER DISSIPATION (W) 0.5W 90 77 71 64 58 54 46 1W 85 75 69 62 56 50 45 1.5W 73 66 60 54 48 43 Table 5: SOT404 PACKAGE (Rth Junction to Ambient) HEATSINK PCB PAD AREA (mm2) 103.5 192 300 475 825 1200 POWER DISSIPATION (W) 1W 60 52 47 41 39 36 2W 55 47 43 39 36 34 3W 41 37 34 32 2W 72 65 59 53 47 43 2.5W 58 52 46 42 3W 45 41