VCC6 LVPECL, LVDS Crystal Oscillator Data Sheet VCC6 Description Vectron's VCC6 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off either a 2.5 or 3.3 volt supply, hermetically sealed 5x7 ceramic package. Features * * * * * * * Applications Ultra Low Jitter Performance, Fundamental or 3rd OT Crystal Design Output Frequencies to 275.000MHz 0.3 ps typical RMS jitter, 12k-20MHz Differential Output Enable/Disable -10/70C, -40/85C or -55/125C Operation Hermetically Sealed 5x7 Ceramic Package * Product is compliant to RoHS directive and fully compatible with lead free assembly * * * * * * * * * * Ethernet, GbE, Synchronous Ethernet Fiber Channel Enterprise Servers Telecom Clock source for A/D's, D/A's Driving FPGA's Test and Measurement PON Medical COTS Block Diagram VDD Complementary Output Output Crystal Oscillator E/D or NC E/D or NC Page1 Gnd Performance Specifications Table 1. Electrical Performance, LVPECL Option Parameter Symbol Min Typical Maximum Units 3.3 2.5 3.465 2.625 V V 50 98 mA 275.000 MHz Supply Voltage1 VDD Current (No Load) IDD 3.135 2.375 Frequency Nominal Frequency2 fN 25 2,3 Stability (Ordering Option) 20, 25, 50, 100 ppm Outputs Output Logic Levels4, -10/70C Output Logic High Output Logic Low VOH VOL VDD-1.025 VDD-1.810 VDD-0.880 VDD-1.620 V V Output Logic Levels4, -40/85C Output Logic High Output Logic Low VOH VOL VDD-1.085 VDD-1.830 VDD-0.880 VDD-1.555 V V Output Rise and Fall Time4 tR/tF 600 ps Load 50 ohms into VDD-1.3V 5 Duty Cycle 45 Jitter (12 kHz - 20 MHz BW)155.52MHz6 J Period Jitter7 RMS P/P Random Jitter Deterministic Jitter J Output Enabled8 Output Disabled VIH VIL Disable Time tD 50 55 % 0.3 0.7 ps 2.3 20 2.4 0 ps ps ps ps Enable/Disable 0.7*VDD Enable/Disable Leakage Current Enable Pull-Up Resistor Output Enabled Output Disabled 200 ns 200 uA 33 1 Start-Up Time tSU Operating Temp. (Ordering Option) TOP V V 0.3*VDD KOhm MOhm 10 ms -10/70 or -40/85 C 1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Figure 1 defines the test circuit and Figure 2 defines these parameters. 5. Duty Cycle is defined as the On/Time Period. 6. Measured using an Agilent E5052, 155.520MHz. Please see "Typical Phase Noise and Jitter Report for the VCC6 series". 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. tR VDD -1.3V 1 tF VOH 6 50% NC 2 5 3 4 VOL NC 50 On Time 50 -1.3V Period Figure 1. Figure 2. Page2 Performance Specifications Table 2. Electrical Performance, LVDS Option Parameter Symbol Min Typical Maximum Units 3.3 2.5 3.465 2.625 V V 60 mA Supply 1 Voltage VDD Current (No Load) IDD 3.135 2.375 Frequency 2 Nominal Frequency fN 80 Stability2,3, (Ordering Option) 275.000 MHz 20, 25, 50, 100 ppm Outputs 4 Output Logic Levels Output Logic High Output Logic Low VOH VOL Differential Output Amplitude 1.43 1.10 1.6 0.9 V V 247 330 454 mV 50 mV 1.125 1.25 1.375 V 50 mV 10 uA 600 ps Differential Output Error Offset Voltage Offset Voltage Error Output Leakage Current Output Rise and Fall Time4 tR/tF Load 100 ohms differential 5 Duty Cycle 45 Jitter (12 kHz - 20 MHz BW)155.52MHz6 J Period Jitter7 RMS P/P Random Jitter Deterministic Jitter J Output Enabled8 Output Disabled VIH VIL Disable Time tD 50 55 % 0.3 0.7 ps 2.5 22 2.6 0 ps ps ps ps Enable/Disable V V 0.7*VDD 0.3*VDD Enable/Disable Leakage Current Enable Pull-Up Resistor Output Enabled Output Disabled 200 ns 200 uA 33 1 Start-Up Time tSU Operating Temp. (Ordering Option) TOP KOhm MOhm 10 ms -10/70 or -40/85 C 1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Figure 2 defines these parameters and Figure 3 defines the test circuit. 5. Duty Cycle is defined as the On/Time Period. 6. Measured using an Agilent E5052, 155.520MHz. Please see "Typical Phase Noise and Jitter Report for the VCC6 series". 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. Out 50 50 Out 0.01 uF 6 5 4 1 2 3 DC Figure 3. Page3 Package and Pinout Table 3. Pinout Pin # Symbol Function 1 E/D or NC Enable Disable or No Connection 2 E/D or NC Enable Disable or No Connection 3 GND Electrical and Lid Ground 4 fO Output Frequency 5 CfO Complementary Output Frequency 6 VDD Supply Voltage 6 7.00.15 5 The Enable/Disable function is set at the factory on either pin 1 or pin 2 and is an ordering option. Outputs will be Enabled if the Enable/Disable is left open. 4 VCC6-XXX 1.96 XXXMXX 5.00.15 YYWW C 1 2 3 1.78 3.66 1.6 max 1.397 1 6 2 Bottom View 5 1.27 3 2.54 3.57 5.08 4 Dimensions are in mm 2.54 5.08 Figure 4. Package Outline Drawing Figure 5. Pad Layout LVPECL Application Diagrams 140 140 Figure 6. Standard PECL Output Configuration Figure 7. Single Resistor Termination Scheme Resistor values are typically 140 ohms for 3.3V operation and 84 ohms for 2.5V operation. Figure 8. Pull-Up Pull Down Termination Resistor values are typically for 3.3V operation For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms The VCC6 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 6. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 7, and a pull-up/pull-down scheme as shown in Figure 8. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. Page4 LVDS Application Diagrams VCC LVDS Driver LVDS Driver LVDS Receiver 100 100 Receiver OUT+ OUT- Figure 9. Standard LVDS Output Configuration Figure 10. LVDS to LVDS Connection, Internal 100ohm Figure 11. LVDS to LVDS Connection Some LVDS structures have an internal 100 ohm resistor External 100ohm and AC blocking caps on the input and do not need additional components. Some input structures may not have an internal 100 ohm resistor on the input and will need an external 100ohm resistor for impedance matching. Also, the input may have an internal DC bias which may not be compatible with LVDS levels, AC blocking capacitors can be used. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Environmental and IR Compliance Table 4. Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002 Mechanical Vibration MIL-STD-883 Method 2007 Temperature Cycle MIL-STD-883 Method 1010 Solderability MIL-STD-883 Method 2003 Fine and Gross Leak MIL-STD-883 Method 1014 Resistance to Solvents MIL-STD-883 Method 2015 Moisture Sensitivity Level MSL1 Contact Pads Gold over Nickel S IR Compliance Table 5. Reflow Profile Parameter Symbol Value PreHeat Time ts 200 sec Max Ramp Up RUP 3C/sec Max 150 sec Max Time above 217C tL Time to Peak Temperature tAMB-P Time at 260C tP Time at 240C tP2 60 sec Max Ramp down RDN 6C/sec Max 260 Temperature (DegC) Suggested IR Profile Devices are built using lead free epoxy and can be subjected to standard lead free IR reflow conditions shown in Table 5. Contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220C. RUP 217 200 tS tAMB-P 25 Time (sec) Page5 tP RDN 150 480 sec Max Reliability 30 sec Max tL S Maximum Ratings, Tape & Reel Absolute Maximum Ratings and Handling Precautions Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Although ESD protection circuitry has been designed into the VCC6, proper precautions should be taken when handling and mounting. VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes. Table 6. Maximum Ratings Parameter Symbol Rating Unit Storage Temperature TSTORE -55/125 C Supply Voltage -0.5 to 5.0 V Enable/Disable Voltage -0.5 to VDD+0.5 V ESD, Human Body Model 1500 V ESD, Charged Device Model 1000 V Table 7. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 16 7.5 1.5 4 8 180 2 13 21 55 17 21 250 Table 8. Standard Frequencies (MHz) 19.4400 25.0000 27.1200 30.7200 33.0000 33.3330 35.0000 35.5000 38.8800 40.0000 40.6800 43.7500 48.0000 50.0000 53.1250 71.5000 74.1758 74.2500 75.0000 56.0000 61.440 62.2080 62.5000 66.0000 68.0000 70.0000 75.4000 77.7600 78.1250 80.0000 81.2500 83.3330 84.0000 86.0000 87.5000 90.0000 95.0000 99.1440 100.0000 105.0000 106.2500 110.0000 112.0000 112.5000 114.2850 120.0000 122.8800 124.4160 125.0000 125.0093 128.0000 130.0000 130.5882 132.8125 133.0000 135.0000 136.0000 156.2500 156.253906 140.0000 142.5408 143.0000 148.7500 150.0000 153.6000 153.8500 155.5200 156.1734 156.261718 156.2740 156.2930 159.3750 160.0000 161.1300 161.1328 162.3250 164.3555 165.0000 172.6423 166.0000 166.5600 166.6286 166.6667 167.3300 167.3317 167.328125 167.4100 168.2009 168.6997 173.3700 173.3708 173.4380 175.000 176.0950 176.8382 177.3437 178.018970 178.1250 178.5000 195.3125 200.0000 210.0000 212.4840 212.5000 218.7500 180.0000 187.0177 187.5000 190.0000 192.4560 225.0000 250.0000 260.0000 266.0000 275.0000 Page6 Ordering Information VCC6 - X X X - XXMXXXXXX * Frequency in MHz Product XO, 5x7 Package Output and Voltage Q: +3.3 Vdc 5%, LVPECL R: +2.5 Vdc 5%, LVPECL L: +3.3 Vdc 5%, LVDS V: +2.5 Vdc 5%, LVDS Enable/Disable A: E/D is on Pin 2 C: E/D is on Pin 1 *Note: not all combination of options are available. Other specifications may be available upon request. Stability/Temp Range A: 100 ppm over -10/70C B: 50 ppm over -10/70C C: 100 ppm over -40/85C D: 50 ppm over -40/85C E: 25 ppm over -10/70C F: 25 ppm over -40/85C G: 20 ppm over -10/70C, excludes aging P: 100 ppm over -55/125C 20ppm Options VCC6-107-frequency VCC6-109-frequency VCC6-110-frequency VCC6-111-frequency VCC6-119-frequency VCC6-120-frequency VCC6-121-frequency VCC6-122-frequency LVPECL LVDS LVPECL LVDS LVPECL LVPECL LVDS LVDS +3.3V +3.3V +2.5V +2.5V +3.3V +2.5V +3.3V +2.5V 20ppm over -10/70C, includes 10 years aging, E/D on Pin1 20ppm over -10/70C, includes 10 years aging, E/D on Pin1 20ppm over -10/70C, includes 10 years aging, E/D on Pin1 20ppm over -10/70C, includes 10 years aging, E/D on Pin1 20ppm over -40/85C, includes 10 years aging, E/D on Pin1 20ppm over -40/85C, includes 10 years aging, E/D on Pin1 20ppm over -40/85C, includes 10 years aging, E/D on Pin1 20ppm over -40/85C, includes 10 years aging, E/D on Pin1 * Add _SNPBDIP for tin lead solder dip Example: VCC6-QAD-125M000000_SNPBDIP Page7 Revision History Revision Date Approved Feb 12, 2014 TG Description Updated Vectron Logo, Hudson & Asia Contact Address Aug 04, 2014 VN Frequency range Limited to 275MHz. Removed Optional 7.5x5.08mm package. Aug 10, 2018 FB Update logo and contact information Page8