1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. This new energy ef ficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•Robust High Voltage Termination
•Avalanche Energy Specified
•Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
•Diode is Characterized for Use in Bridge Circuits
•IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–to–Source V oltage VDSS 500 Vdc
Drain–to–Gate V oltage (RGS = 1.0 M
W
)VDGR 500 Vdc
Gate–to–Source Voltage – Continuous
Gate–to–Source V oltage – Non–repetitive (tp ≤ 10 ms) VGS
VGSM ±20
±40 Vdc
Vpk
Drain Current — Continuous @ TC = 25°C
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp ≤ 10
m
s)
ID
ID
IDM
8.0
5.0
32
Adc
Apk
Total Power Dissipation @ TC = 25 °C
Derate above 25°CPD125
1.0 Watts
W/°C
Operating and Storage Temperature Range TJ, Tstg –55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy – STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25
W
)EAS 510 mJ
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient R
q
JC
R
q
JA 1.0
62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 sec. TL260 °C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 2
Order this document
by MTP8N50E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM
D
S
G
CASE 221A–06, Style 5
TO-220AB
Motorola, Inc. 1996
MTP8N50E
2Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coef ficient (Positive)
V(BR)DSS 500
——
500 —
—Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS —
——
—250
1000
m
Adc
Gate–Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coef ficient (Negative)
VGS(th) 2.0
—2.8
6.3 4.0
—Vdc
mV/°C
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 4.0 Adc) RDS(on) —0.6 0.8 Ohms
Drain–to–Source On–V oltage (VGS = 10 Vdc)
(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125°C)
VDS(on) —
—5.0
—7.2
6.4
Vdc
Forward T ransconductance
(VDS = 15 Vdc, ID = 4.0 Adc) gFS 4.0 — — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V 25 Vdc V 0 Vdc
Ciss —1450 1680 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
)
Coss —190 246
T ransfer Capacitance
f
=
1
.
0
MHz)
Crss —45.4 144
SWITCHING CHARACTERISTICS (2)
T urn–On Delay Time
(R C1 9 1
W
)
td(on) —15 50 ns
Rise T ime
(Rgo +C17n=91
W
)
tr— 33 72
T urn–Off Delay Time
(R
go +
C17n
=
9
.
1
W
)
td(off) —40 150
Fall T ime tf— 32 60
Gate Charge
(see Figure 8)
(V 400 Vd I 8 0 Ad
QT— 40 64 nC
(see Figure 8) (VDS = 400 Vdc, ID = 8.0 Adc, Q1— 8.0 —
(DS ,D,
VGS = 10 Vdc) Q2—17 —
Q3— 17.3 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage VSD Vdc
(IS = 8.0 Adc, VGS = 0 Vdc) — 1.2 2.0
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C) — 1.1 —
Reverse Recovery Time
(I 8 0 Ad V 0 Vd
trr — 320 — ns
(IS = 8.0 Adc, VGS = 0 Vdc, ta—179 —
(S,GS ,
dIS/dt = 100 A/
m
s) tb— 141 —
Reverse Recovery Stored Charge QRR —3.0 —
m
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die) LD— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad) LS— 7.5 —
(1) Pulse Test: Pulse Width ≤ 300
m
s, Duty Cycle ≤ 2.0%.
(2) Switching characteristics are independent of operating junction temperature.
MTP8N50E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
100
°
C
25
°
C
TJ = –55
°
C
VDS, DRAIN–TO–SOURCE VOLTAGE (VOL TS)
Figure 1. On–Region Characteristics
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–to–Source Leakage Current
versus Voltage
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
16
12
8.0
4.0
108.06.04.02.00
16
12
8.0
4.0
2.0 2.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
0.8
0.6
0.4
0.2
014106.02.00
0.60
0 4.0 8.0 12 16
2.5
1.5
0.5
0150100500–50
TJ = 25
°
C7 V
6 V
5 V
ID, DRAIN CURRENT (AMPS)
VGS = 10 V
0
4.0 8.0 12 16 2.0 6.0 10 14
0 100 300 500200 400
0
2.0
1.0
100,000
1,000
10
1.0
10,000
100
1412
8 V
ID, DRAIN CURRENT (AMPS)
0.55
0.70
0.65
0.75
0.85
0.80
TJ = 25
°
C
VGS = 10 V
15 V
1.6
1.2
1.0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
VGS = 10 V
TJ = 100
°
C
25
°
C
–55
°
C
1257525–25
VGS = 10 V
ID = 8 A
VGS = 0 V TJ = 125
°
C
25
°
C
100
°
C
VDS
≥
10 V
3.0 3.5
14
10
6.0
2.0
1.4
0.90
MTP8N50E
4Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
GATE–TO–SOURCE OR DRAIN–T O–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
DRAIN–T O–SOURCE VOLTAGE (VOLTS)
Figure 8. High Voltage Capacitance Variation
Qg, TOTAL GA TE CHARGE (nC)
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
RG, GATE RESISTANCE (OHMS)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage versus
Current
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
IS, SOURCE CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
V
C, CAPACITANCE (pF)
t, TIME (ns)
4000
3000
2000
1000
20105.00–5.0–10
10,000
1,000
100
10 100 1000
8.0
6.0
4.0
2.0
03224168.00
1000
100
10 1.0 10 100
6.0
2.0
00.90.80.70.60.5
C, CAPACITANCE (pF)
10
40
0.1 1.0 10 100 1000
0
8.0
4.0
100
10
0.1
0.01
1.0
15 25
12
10
, GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
1.31.21.11.0
TJ = 25
°
C
VGS = 0 V
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
VGS = 20 V
SINGLE PULSE
TC = 25
°
C
100
m
s
dc
10 ms
1 ms
10
m
s
TJ = 25
°
C
ID = 8 A
VDD = 250 V
VGS = 10 V
td(off)
tr
td(on)
VGS = 0 V TJ = 25
°
C
Ciss
Coss
Crss
VDS = 0 V VGS = 0 V
Ciss
Ciss
Crss
Crss
Coss
TJ = 25
°
C
VGS VDS
400
300
200
100
0
VDS, DRAIN–T O–SOURCE VOLTAGE (VOLTS)
TJ = 25
°
C
ID = 8 A
VDS
VGS
Q2Q1
QT
Q3 tf
MTP8N50E
5
Motorola TMOS Power MOSFET Transistor Device Data
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
E
TJ, STAR TING JUNCTION TEMPERATURE (
°
C) 15025
600
0
100
200
50 100
75 125
300
400
500 ID = 8 A
, SINGLE PULSE DRAIN–TO–SOURCE
AS AV ALANCHE ENERGY (mJ)
Figure 14. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESIST ANCE
t, TIME (seconds)
1.0
0.01
D = 0.5
0.05
0.01SINGLE PULSE
0.00001
0.02
0.1
0.0001 0.001 0.01 1.0 10
0.1
0.2
0.1
MTP8N50E
6Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 221A–06
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.570 0.620 14.48 15.75
B0.380 0.405 9.66 10.28
C0.160 0.190 4.07 4.82
D0.025 0.035 0.64 0.88
F0.142 0.147 3.61 3.73
G0.095 0.105 2.42 2.66
H0.110 0.155 2.80 3.93
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.15 1.52
N0.190 0.210 4.83 5.33
Q0.100 0.120 2.54 3.04
R0.080 0.110 2.04 2.79
S0.045 0.055 1.15 1.39
T0.235 0.255 5.97 6.47
U0.000 0.050 0.00 1.27
V0.045 ––– 1.15 –––
Z––– 0.080 ––– 2.04
B
Q
H
Z
L
V
G
N
A
K
F
123
4
D
SEATING
PLANE
–T–
C
S
T
U
R
J
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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Opportunity/Af firmative Action Employer.
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MTP8N50E/D
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