July 1996
NDS331N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
_______________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter NDS331N Units
VDSS Drain-Source Voltage 20 V
VGSS Gate-Source Voltage - Continuous 8V
IDMaximum Drain Current - Continuous (Note 1a) 1.3 A
- Pulsed 10
PDMaximum Power Dissipation (Note 1a)0.5 W
(Note 1b) 0.46
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1a) 250 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
NDS331N Rev.E
1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V
RDS(ON) = 0.16 Ω @ VGS= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very
small outline surface mount package.
D
S
G
© 1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS= 0 V 1µA
TJ =125°C 10 µA
IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA0.5 0.7 1V
TJ =125°C 0.3 0.53 0.8
RDS(ON) Static Drain-Source On-Resistance VGS = 2.7 V, ID = 1.3 A0.15 0.21 Ω
TJ =125°C 0.24 0.4
VGS = 4.5 V, ID = 1.5 A0.11 0.16
ID(ON) On-State Drain Current VGS = 2.7 V, VDS = 5 V 3A
VGS = 4.5 V, VDS = 5 V 4
gFS Forward Transconductance VDS = 5 V, ID = 1.3 A, 3.5 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 10 V, VGS = 0 V,
f = 1.0 MHz 162 pF
Coss Output Capacitance 85 pF
Crss Reverse Transfer Capacitance 28 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)Turn - On Delay Time VDD = 5 V, ID = 1 A,
VGS = 5 V, RGen = 6 Ω5 20 ns
trTurn - On Rise Time 25 40 ns
tD(off) Turn - Off Delay Time 10 20 ns
tfTurn - Off Fall Time 5 20 ns
QgTotal Gate Charge VDS = 5 V, ID = 1.3 A,
VGS = 4.5 V 3.5 5nC
Qgs Gate-Source Charge 0.3 nC
Qgd Gate-Drain Charge 1nC
NDS331N Rev.E
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current 0.42 A
ISM Maximum Pulsed Drain-Source Diode Forward Current 10 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note 2)0.8 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD(t)=TJ−TA
RθJA
(t)=TJ−TA
RθJC
+RθCA
(t)=ID
2(t)×RDS(ON)TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS331N Rev.E
1a 1b
NDS331N Rev.E
Figure 1. On-Region Characteristics.
0 1 2 3
0
1
2
3
4
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
3.0 2.7
V =4.5V
GS
DS
D
2.5
1.5
2.0
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
00.5 11.5 22.5 3
0.5
0.75
1
1.25
1.5
1.75
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125°C
J
25°C
D
V = 2.7 V
GS
-55°C
R , NORMALIZED
DS(on)
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
-50 -25 025 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 2.7V
GS
I = 1.3A
D
R , NORMALIZED
DS(ON)
Figure 3. On-Resistance Variation
with Temperature.
00.5 11.5 22.5 3
0
1
2
3
4
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 5.0V
DS
GS
D
T = -55°C
J
Figure 5. Transfer Characteristics.
-50 -25 025 50 75 100 125 150
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = 250µA
D
V = V
DS GS
V , NORMALIZED
th
Figure 6. Gate Threshold Variation
with Temperature.
00.5 11.5 22.5 3
0.5
0.75
1
1.25
1.5
1.75
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 2.0V
GS
D
R , NORMALIZED
DS(on)
3.5 4.5
2.7 3.0
2.5
Typical Electrical Characteristics
NDS331N Rev.E
Typical Electrical Characteristics (continued)
-50 -25 0 25 50 75 100 125 150
0.92
0.96
1
1.04
1.08
1.12
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250µA
D
BV , NORMALIZED
DSS
J
Figure 7. Breakdown Voltage Variation with
Temperature.
0.1 0.2 0.5 1 2 5 10 20
10
20
50
100
200
400
600
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 9. Capacitance Characteristics.
00.2 0.4 0.6 0.8 11.2
0.0001
0.001
0.01
0.1
1
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
J
25°C
-55°C
V = 0V
GS
SD
S
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
0 1 2 3 4 5
0
1
2
3
4
5
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 1.3A
D10V
15V
V = 5V
DS
Figure 10. Gate Charge Characteristics.
G
D
S
VDD
RL
V
V
IN
OUT
VGS DUT
RGEN
Figure 11. Switching Test Circuit.Figure 12. Switching Waveforms.
10%
50%
90%
10%
90%
90%
50%
VIN
VOUT
on off
d(off) f
r
d(on)
t t
ttt
t
INVERTED
10%
PULSE WIDTH
NDS331N Rev.E
Typical Electrical Characteristics (continued)
01234
0
2
4
6
8
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55°C
J
25°C
D
FS
V = 5.0V
DS
125°C
Figure 13. Transconductance Variation with Drain
Current and Temperature.
00.1 0.2 0.3 0.4
0
0.2
0.4
0.6
0.8
1
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
Ao
Figue 15. SuperSOTTM _ 3 Maximum
Steady-State Power Dissipation. versus Copper
Mounting Pad Area.
0.1 0.2 0.5 1 2 5 10 20 30
0.01
0.03
0.1
0.3
1
3
10
20
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
DC
1s
10ms
100ms
10s
RDS(ON) LIMIT
V = 2.7V
SINGLE PULSE
R =See Note1b
T = 25°C
GS
A
θJA
100us
Figure 14. Maximum Safe Operating Area.
00.1 0.2 0.3 0.4
1
1.2
1.4
1.6
1.8
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1b
1a
D
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = 2.7V
Ao
GS
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad. Area
Figure 17. Transient Thermal Response Curve.
Note : Thermal characterization performed using the conditions described in note 1b. Transient thermal
response will change depending on the circuit board design.
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
Duty Cycle, D = t /t
12
R (t) = r(t) * R
R = See Note 1b
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
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