LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with
Programmable Power-On Reset Delay; Low Noise Version Available (LP2988)
Check for Samples: LP2987,LP2988
1FEATURES DESCRIPTION
The LP2987/8 are fixed-output 200 mA precision LDO
2• Ultra Low Dropout Voltage voltage regulators with power-ON reset delay which
• Power-ON Reset Delay Requires Only One can be implemented using a single external capacitor.
Component The LP2988 is specifically designed for noise-critical
• Bypass Pin for Reduced Output Noise applications. A single external capacitor connected to
(LP2988) the Bypass pin reduces regulator output noise.
• Specified Continuous Output Current 200 mA Using an optimized VIP (Vertically Integrated PNP)
• Specified Peak Output Current > 250 mA process, these regulators deliver superior
• SOIC-8 and VSSOP-8 Surface Mount Packages performance:
• <2 μA Quiescent Current when Shutdown Dropout Voltage: 180 mV @ 200 mA load, and 1
• Low Ground Pin Current at All Loads mV @ 1 mA load (typical).
• 0.5% Output Voltage Accuracy (“A” Grade) Ground Pin Current: 1 mA @ 200 mA load, and 200
μA @ 10 mA load (typical).
• Wide Supply Voltage Range (16V Max)
• Overtemperature/overcurrent Protection Sleep Mode: The LP2987/8 draws less than 2 μA
quiescent current when shutdown pin is held low.
•−40°C to +125°C Junction Temperature Range Error Flag/Reset: The error flag goes low when the
APPLICATIONS output drops approximately 5% below nominal. This
pin also provides a power-ON reset signal if a
• Cellular Phone capacitor is connected to the DELAY pin.
• Palmtop/Laptop Computer Precision Output: Standard product versions of the
• Camcorder, Personal Stereo, Camera LP2987 and LP2988 are available with output
voltages of 5.0V, 3.8V, 3.3V, 3.2V, 3.0V, or 2.8V, with
specified accuracy of 0.5% (“A” grade) and 1%
(standard grade) at room temperature.
Block Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
8
7
6
5
BYPASS
DELAY
GROUND
INPUT
SENSE
OUTPUT
SHUTDOWN
ERROR
1
2
3
45
6
7
8
N/C
DELAY
INPUT
SENSE
OUTPUT
SHUTDOWN
ERROR
GROUND
GROUND
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
Connection Diagram (LP2987)
Figure 1. Top View
SOIC-8/VSSOP-8 Package
Surface Mount Packages
See Package Drawing Number D0008A/DGK0008A
Figure 2. Top View
8-Lead WSON Surface Mount Package
See Package Drawing Number NGN0008A
Connection Diagram (LP2988)
Figure 3. Top View
SOIC-8/VSSOP-8 Package
Surface Mount Packages
See Package Drawing Number D0008A/DGK0008A
Figure 4. Top View
8-Lead WSON Surface Mount Package
See Package Drawing Number NGN0008A
2Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
using: The value of θJ−Afor the SOIC-8 (D) package is 160°C/W, and the VSSOP-8 (DGK) package is 200°C/W.
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Storage Temperature Range −65°C to +150°C
Operating Junction
Temperature Range −40°C to +125°C
Lead Temperature
(Soldering, 5 seconds) 260°C
ESD Rating (3) 2 kV
Power Dissipation (4) Internally Limited
Input Supply Voltage
(Survival) −0.3V to +16V
Input Supply Voltage
(Operating) 2.1V to +16V
Shutdown Pin −0.3V to +16V
Sense Pin −0.3V to +6V
Output Voltage
(Survival) (5) −0.3V to +16V
IOUT (Survival) Short Circuit Protected
Input-Output Voltage
(Survival) (6) −0.3V to +16V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The ESD rating of the Bypass pin is 500V (LP2988 only). The ESD rating of the VIN pin is 1kV and the Delay pin is ESD rated at 1.5kV.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
The value θJ−Afor the WSON (NGN) package is specifically dependent on PCB trace area, trace material, and the number of layers and
thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187
(literature number SNOA401). Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2987/8 output must be diode-clamped
to ground.
(6) The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output
above the input will turn on this diode and may induce a latch-up mode which can damage the part (see APPLICATION HINTS).
ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL= 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
LM2987/8AI-X.X (1) LM2987/8I-X.X (1)
Symbol Parameter Conditions Typical Units
Min Max Min Max
ΔVOOutput Voltage Tolerance −0.5 0.5 −1.0 1.0
0.1 mA < IL< 200 mA −0.8 0.8 −1.6 1.6 %VNOM
−1.8 1.8 −2.8 2.8
ΔVO/ΔVIN Output Voltage Line VO(NOM) + 1V ≤VIN ≤16V 0.014 0.014
0.007 %/V
Regulation 0.032 0.032
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL= 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
LM2987/8AI-X.X (1) LM2987/8I-X.X (1)
Symbol Parameter Conditions Typical Units
Min Max Min Max
VIN–VODropout Voltage IL= 100 µA 2.0 2.0
1
(2) 3.5 3.5
IL= 75 mA 120 120
90 mV
170 170
IL= 200 mA 230 230
180 350 350
IGND Ground Pin Current IL= 100 µA 120 120
100 150 150 µA
IL= 75 mA 800 800
500 1400 1400
IL= 200 mA 2.1 2.1
1 mA
3.7 3.7
VS/D < 0.3V 0.05 1.5 1.5 µA
IO(PK) Peak Output Current VOUT ≥VO(NOM) −5% 400 250 250 mA
IO(MAX) Short Circuit Current RL= 0 (Steady State) (3) 400
enLP2987 Output Noise BW = 300 Hz to
Voltage (RMS) 50 kHz, VOUT = 3.3V 100
COUT = 10 µF µV(RMS)
LP2988 Output Noise BW = 300 Hz to 50 kHz,
Voltage (RMS) VOUT = 3.3V 20
COUT = 10 µF
CBYPASS = .01 µF
ΔVOUT/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF 65 dB
CBYP = 0 (LP2988)
ΔVOUT/ΔT Output Voltage (4) 20 ppm/°C
Temperature Coefficient
IDELAY Delay Pin Current Source 1.6 2.8 1.6 2.8
2.2 µA
1.4 3.0 1.4 3.0
SHUTDOWN INPUT
VS/D S/D Input Voltage VH= O/P ON 1.4 1.6 1.6 V
(5) VL= O/P OFF 0.55 0.18 0.18
IS/D S/D Input Current VS/D = 0 0 −1−1µA
VS/D = 5V 5 15 15
(2) Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a
1V differential.
(3) See TYPICAL PERFORMANCE CHARACTERISTICS curves.
(4) Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.
(5) To prevent mis-operation, the Shutdown input must be driven by a signal that swings above VHand below VLwith a slew rate not less
than 40 mV/µs (see APPLICATION HINTS).
4Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL= 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
LM2987/8AI-X.X (1) LM2987/8I-X.X (1)
Symbol Parameter Conditions Typical Units
Min Max Min Max
ERROR COMPARATOR
IOH Output “HIGH” Leakage VOH = 16V 1 1
0.01 µA
2 2
VOL Output “LOW” Voltage VIN = VO(NOM) −0.5V, 220 220
150 mV
IO(COMP) = 300 µA 350 350
VTHR Upper Threshold Voltage −5.5 −3.5 −5.5 −3.5
−4.6
(MAX) −7.7 −2.5 −7.7 −2.5
VTHR Lower Threshold Voltage −8.9 −4.9 −8.9 −4.9 %VOUT
−6.6
(MIN) −13.0 −3.3 −13.0 −3.3
HYST Hysteresis 2.0
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
VOUT Dropout Voltage
vs vs
Temperature Temperature
Figure 5. Figure 6.
Dropout Voltage
vs
Load Current Dropout Characteristics
Figure 7. Figure 8.
Ground Pin Current vs Ground Pin Current vs
Temperature and Load Load Current
Figure 9. Figure 10.
6Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Input Current Input Current
vs vs
VIN VIN
Figure 11. Figure 12.
Load Transient Response Load Transient Response
Figure 13. Figure 14.
Line Transient Response Line Transient Response
Figure 15. Figure 16.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Turn-On Waveform Turn-On Waveform
Figure 17. Figure 18.
Short Circuit Current Short Circuit Current
Figure 19. Figure 20.
Short Circuit Current Instantaneous Short Circuit Current
vs Output Voltage vs Temperature
Figure 21. Figure 22.
8Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Shutdown Pin Current vs
DC Load Regulation Shutdown Pin Voltage
Figure 23. Figure 24.
Shutdown Voltage Input to Output Leakage
vs Temperature vs Temperature
Figure 25. Figure 26.
Delay Pin Current
vs Delay Pin Current vs
VIN Delay Pin Voltage
Figure 27. Figure 28.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Delay Sink Current
Delay Sink Current vs
vs Temperature Temperature
Figure 29. Figure 30.
Output Impedance Output Impedance
vs vs
Frequency Frequency
Figure 31. Figure 32.
Ripple Rejection (LP2987) Ripple Rejection (LP2988)
Figure 33. Figure 34.
10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Output Noise Density (LP2987) Output Noise Voltage (LP2988)
Figure 35. Figure 36.
Output Noise Density (LP2988) Output Noise Density (LP2988)
Figure 37. Figure 38.
Turn-On Time (LP2988) Turn-On Time (LP2988)
Figure 39. Figure 40.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL= 1 mA.
Turn-On Time (LP2988)
Figure 41.
12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
BASIC APPLICATION CIRCUITS
Figure 42.
*Capacitance value shown is minimum required to assure stability, but may be increased without limit. Larger output
capacitor provides improved dynamic response.
**Shutdown must be actively terminated (see APPLICATION HINTS). Tie to INPUT (pin 4) if not used.
Figure 43.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
APPLICATION HINTS
WSON Package Devices
The LP2987/LP2988 is offered in the 8 lead WSON surface mount package to allow for increased power
dissipation compared to the SOIC-8 and the VSSOP-8. For details on thermal performance as well as mounting
and soldering specifications, refer to Application Note AN-1187 (literature number SNOA401).
EXTERNAL CAPACITORS
As with any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
INPUT CAPACITOR: An input capacitor (≥2.2 µF) is required between the LP2987/8 input and ground (amount
of capacitance may be increased without limit).
This capacitor must be located a distance of not more than 0.5” from the input pin and returned to a clean analog
ground. Any good quality ceramic or tantalum may be used for this capacitor.
OUTPUT CAPACITOR: The output capacitor must meet the requirement for minimum amount of capacitance
and also have an appropriate E.S.R. (equivalent series resistance) value.
Curves are provided which show the allowable ESR range as a function of load current for 3V and 5V outputs.
Figure 44. ESR Curves For 5V Output Figure 45. ESR Curves For 3V Output
IMPORTANT: The output capacitor must maintain its ESR in the stable region over the full operating
temperature range of the application to assure stability.
The minimum required amount of output capacitance is 4.7 µF. Output capacitor size can be increased without
limit.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range. A good Tantalum capacitor will show very little variation with
temperature, but a ceramic may not be as good (see next section).
The output capacitor should be located not more than 0.5” from the output pin and returned to a clean analog
ground.
14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
CAPACITOR CHARACTERISTICS
TANTALUM: A solid tantalum capacitor is the best choice for the output capacitor on the LM2987/8. Available
from many sources, their typical ESR is very close to the ideal value required on the output of many LDO
regulators.
Tantalums also have good temperature stability: a 4.7 µF was tested and showed only a 10% decline in
capacitance as the temperature was decreased from +125°C to −40°C. The ESR increased only about 2:1 over
the same range of temperature.
However, it should be noted that the increasing ESR at lower temperatures present in all tantalums can cause
oscillations when marginal quality capacitors are used (where the ESR of the capacitor is near the upper limit of
the stability range at room temperature).
CERAMIC: The ESR of ceramic capacitor can be low enough to cause an LDO regulator to oscillate: a 2.2 µF
ceramic was measured and found to have an ESR of 15 mΩ.
If a ceramic capacitor is to be used on the LP2987/8 output, a 1Ωresistor should be placed in series with the
capacitor to provide a minimum ESR for the regulator.
A disadvantage of ceramic capacitors is that their capacitance varies a lot with temperature: Large ceramic
capacitors are typically manufactured with the Z5U temperature characteristic, which results in the capacitance
dropping by 50% as the temperature goes from 25°C to 80°C.
This means you have to buy a capacitor with twice the minimum COUT to assure stable operation up to 80°C.
ALUMINUM: The large physical size of aluminum electrolytics makes them unsuitable for most applications.
Their ESR characteristics are also not well suited to the requirements of LDO regulators. The ESR of a typical
aluminum electrolytic is higher than a tantalum, and it also varies greatly with temperature.
A typical aluminum electrolytic can exhibit an ESR increase of 50X when going from 20°C to −40°C. Also, some
aluminum electrolytics can not be used below −25°C because the electrolyte will freeze.
POWER-ON RESET DELAY
A power-on reset function can be easily implemented using the LP2987/8 by adding a single external capacitor to
the Delay pin. The Error output provides the power-on reset signal when input power is applied to the regulator.
The reset signal stays low for a pre-set time period after power is applied to the regulator, and then goes high
(see Timing Diagram below).
Figure 46. Timing Diagram for Power-Up
The external capacitor cDLY sets the delay time (TDELAY). The value of capacitor required for a given time delay
may be calculated using the formula:
CDLY = TDELAY/(5.59 X 105)
To simplify design, a plot is provided below which shows values of CDLY versus delay time.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
Figure 47. Plot of CDLY vs TDELAY
DETAILS OF ERR/RESET CIRCUIT OPERATION: (Refer to LP2987/8 Equivalent Circuit).
Figure 48. LP2987/8 Equivalent Circuit
The output of comparator U2 is the ERR/RESET flag. Since it is an open-collector output, it requires the use of a
pull-up resistor (RP). The 1.23V reference is tied to the inverting input of U2, which means that its output is
controlled by the voltage applied to the non-inverting input.
The output of U1 (also an open-collector) will force the non-inverting input of U2 to go low whenever the
LP2987/8 regulated output drops about 5% below nominal.
U1's inverting input is also held at 1.23V. The other input samples the regulated output through a resistive divider
(RAand RB). When the regulated output is at nominal voltage, the voltage at the divider tap point will be 1.23V. If
this voltage drops about 60 mV below 1.23V, the output of U1 will go low forcing the output of U2 low (which is
the ERROR state).
16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
Power-ON reset delay occurs when a capacitor (shown as CDLY) is connected to the Delay pin. At turn-ON, this
capacitor is initially fully discharged (which means the voltage at the Delay pin is 0V). The output of U1 keeps
CDLY fully discharged (by sinking the 2.2 µA from the current source) until the regulator output voltage comes up
to within about 5% of nominal. At this point, U1's output stops sinking current and the 2.2 µA starts charging up
CDLY.
When the voltage across CDLY reaches 1.23V, the output of U2 will go high (note that D1 limits the maximum
voltage to about 2V).
SELECTING CDLY: The maximum recommended value for this capacitor is 1 µF. The capacitor must not have
excessively high leakage current, since it is being charged from a 2.2 µA current source.
Aluminum electrolytics can not be used, but good-quality tantalum, ceremic, mica, or film types will work.
SHUTDOWN INPUT OPERATION
The LP2987/8 is shut off by driving the Shutdown input low, and turned on by pulling it high. If this feature is not
to be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds listed as VHand VL, respectively (see Electrical
Characteristics).
It is also important that the turn-on (and turn-off) voltage signals applied to the Shutdown input have a slew rate
which is not less than 40 mV/µs.
CAUTION
The regulator output state can not be ensured if a slow-moving AC (or DC) signal is
applied that is in the range between VHand VL.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the LP2987/8 has an inherent diode connected between
the regulator output and input.
During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.
However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator
output.
In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin),
which can damage the part.
In any application where the output may be pulled above the input, an external Schottky diode must be
connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2987/8 to
0.3V (see Absolute Maximum Ratings).
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LP2987 LP2988
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
BYPASS CAPACITOR (LP2988)
The capacitor connected to the Bypass pin must have very low leakage. The current flowing out of the Bypass
pin comes from the Bandgap reference, which is used to set the output voltage. Since the Bandgap circuit has
only a few microamps flowing in it, loading effects due to leakage current will cause a change in the regulated
output voltage.
Curves are provided which show the effect of loading the Bypass pin on the regulated output voltage.
Care must be taken to ensure that the capacitor selected for bypass will not have significant leakage current over
the operating temperature range of the application.
A high quality ceramic capacitor which uses either NPO or COG type dielectiric material will typically have very
low leakage. Small surface-mount polypropolene or polycarbonate film capacitors also have extremely low
leakage, but are slightly larger in size than ceramics.
18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LP2987 LP2988
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP2987AILD-3.0/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L007A
LP2987AILD-5.0/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L009A
LP2987AILDX-5.0/NOPB ACTIVE WSON NGN 8 4500 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L009A
LP2987AIMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L44A
LP2987AIMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987A
IM5.0
LP2987ILD-3.3/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L008A
B
LP2987IM-3.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987I
M3.0
LP2987IM-3.3/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987I
M3.3
LP2987IM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987I
M5.0
LP2987IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L43B
LP2987IMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L44B
LP2987IMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L43B
LP2987IMX-3.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987I
M3.0
LP2987IMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2987I
M5.0
LP2988AIM-5.0 NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2988A
IM5.0
LP2988AIM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2988A
IM5.0
LP2988AIMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L49A
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP2988AIMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L50A
LP2988AIMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L51A
LP2988AIMX-3.3/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2988A
IM3.3
LP2988ILD-3.8/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L083A B
LP2988IM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2988I
M5.0
LP2988IMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L49B
LP2988IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L50B
LP2988IMM-5.0 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L51B
LP2988IMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L51B
LP2988IMMX-3.0/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L49B
LP2988IMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L50B
LP2988IMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2988I
M5.0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 3
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP2987AILD-3.0/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LP2987AILD-5.0/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LP2987AILDX-5.0/NOPB WSON NGN 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LP2987AIMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2987AIMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2987ILD-3.3/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LP2987IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2987IMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2987IMMX-3.3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2987IMX-3.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2987IMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2988AIMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988AIMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988AIMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988AIMX-3.3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LP2988ILD-3.8/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LP2988IMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP2988IMM-5.0 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988IMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988IMMX-3.0/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988IMMX-3.3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2988IMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2987AILD-3.0/NOPB WSON NGN 8 1000 210.0 185.0 35.0
LP2987AILD-5.0/NOPB WSON NGN 8 1000 210.0 185.0 35.0
LP2987AILDX-5.0/NOPB WSON NGN 8 4500 367.0 367.0 35.0
LP2987AIMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2987AIMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2987ILD-3.3/NOPB WSON NGN 8 1000 210.0 185.0 35.0
LP2987IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2987IMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2987IMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LP2987IMX-3.0/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2987IMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2988AIMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2988AIMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988AIMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988AIMX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0
LP2988ILD-3.8/NOPB WSON NGN 8 1000 210.0 185.0 35.0
LP2988IMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988IMM-5.0 VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988IMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LP2988IMMX-3.0/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LP2988IMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LP2988IMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
2X
2.4
0.8 MAX
(0.25)
(0.25) (0.2)
(0.15)
0.05
0.00
8X 0.6
0.4
3 0.05
2.2 0.05
6X 0.8
A4.1
3.9 B
4.1
3.9
(0.2) TYP
WSON - 0.8 mm max heightNGN0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214794/A 11/2019
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED SYMM
SYMM
9
DETAIL A
SEE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
PIN 1 ID DETAIL A
PIN 1 ID
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(3)
(3.3)
6X (0.8)
(2.2)
( 0.2) VIA
TYP (0.85)
(1.25)
8X (0.5)
(R0.05) TYP
WSON - 0.8 mm max heightNGN0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214794/A 11/2019
SYMM
1
45
8
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
0.59
4X (1.31)
8X (0.3)
8X (0.5)
4X (0.98)
(3.3)
(0.755)
6X (0.8)
WSON - 0.8 mm max heightNGN0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214794/A 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
METAL
TYP
SYMM 9
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
