MX29LV040CT2I-70G - Macronix International Co., Ltd.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

4M-BIT [512K x 8] CMOS SINGLE VOLTAGE

3V ONLY EQUAL SECTOR FLASH MEMORY

FEATURES

• Extendedsingle-supplyvoltagerange2.7Vto3.6V

• 524,288x8only

• Singlepowersupplyoperation

 -3.0Vonlyoperationforread,eraseandprogramoperation

• Fully compatible with MX29LV040 device

• Fastaccesstime:55Q/70/90ns

• Lowpowerconsumption

 -30mAmaximumactivecurrent

 -0.2uAtypicalstandbycurrent

• Commandregisterarchitecture

 -8equalsectorof64K-Byteeach

 -ByteProgramming(9ustypical)

 -SectorErase(Sectorstructure64K-Bytex8)

• AutoErase(chip&sector)andAutoProgram

 -AutomaticallyeraseanycombinationofsectorswithEraseSuspendcapability

 -Automaticallyprogramandverifydataatspeciedaddress

• Erasesuspend/EraseResume

 -Suspendssectoreraseoperationtoreaddatafrom,orprogramdatato,anysectorthatisnotbeingerased,

thenresumestheerase

• StatusReply

 -Data#Polling&Togglebitfordetectionofprogramanderaseoperationcompletion

• Sectorprotection

 -Hardwaremethodtodisableanycombinationofsectorsfromprogramoreraseoperations

 -Anycombinationofsectorscanbeerasedwitherasesuspend/resumefunction

• CFI(CommonFlashInterface)compliant

 -Flashdeviceparametersstoredonthedeviceandprovidethehostsystemtoaccess

• 100,000minimumerase/programcycles

• Latch-upprotectedto100mAfrom-1VtoVCC+1V

• Packagetype:

 -32-pinPLCC

 -32-pinTSOP(8mmx20mm,8mmx14mm)

- All devices are RoHS Compliant

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

PIN CONFIGURATIONS

32 PLCC

32 TSOP (Standard Type) (8mm x 20mm)

PIN DESCRIPTION

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

GND

MX29LV040C

14 17 20

32 30 A14

A13

A11

OE#

A10

CE#

GND

A12

A15

A16

A18

VCC

WE#

A17

MX29LV040C

SYMBOL PIN NAME

A0~A18 AddressInput

Q0~Q7 DataInput/Output

CE# ChipEnableInput

WE# WriteEnableInput

OE# OutputEnableInput

GND GroundPin

VCC +3.0Vsinglepowersupply

32 TSOP (8mm x 14mm)

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

GND

MX29LV040C

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q7

A0-A18

CE#

OE#

WE#

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Table 1. SECTOR (GROUP) STRUCTURE

Note:Allsectorsare64Kbytesinsize.

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000h-0FFFFh

SA1 0 0 110000h-1FFFFh

SA2 0 10 20000h-2FFFFh

SA3 0 1 1 30000h-3FFFFh

SA4 10 0 40000h-4FFFFh

SA5 10150000h-5FFFFh

SA6 110 60000h-6FFFFh

SA7 111 70000h-7FFFFh

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Table 2-1. BUS OPERATION

Table 2-2. BUS OPERATION

Notes:

1.Sectorunprotectedcode:00h.Sectorprotectedcode:01h.

2.AM:MSBofaddress.

3.Sectoraddresses:A18~A16.

4.Vhvis11.5Vto12.5V.

5.Xmeansdon'tcare.

Operation CE# OE# WE# Address Q7~Q0

ReadMode L L H AIN DOUT

Write L H L AIN DIN

StandbyMode Vcc±0.3V X X X High-Z

OutputDisable L H H X High-Z

Operation CE# OE# WE# A0 A1 A6 A9 Q7~Q0

ReadSiliconID

ManufacturesCode L L H L L X Vhv C2H

ReadSiliconID

DeviceCode L L H H L X Vhv 4FH

SectorProtect L Vhv L X X L Vhv X

ChipUnprotected L Vhv L X X H Vhv X

SectorProtectVerify L L H X H X Vhv Code(1)

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

WRITE COMMANDS/COMMAND SEQUENCES

Towriteacommandtothedevice,systemmustdriveWE#andCE#toVil,andOE#toVih.Inacommandcycle,

alladdress arelatched atthe laterfalling edgeof CE#and WE#,and alldata arelatched atthe earlierrising

edgeofCE#andWE#.

Figure1illustratestheACtimingwaveformofawritecommand,andTable3denesallthevalidcommandsets

ofthedevice.Systemisnotallowedtowriteinvalidcommandsnotdenedinthisdatasheet.Writinganinvalid

commandwillbringthedevicetoanundenedstate.

REQUIREMENTS FOR READING ARRAY DATA

Readarrayactionistoreadthedatastoredinthearray.Whilethememorydeviceisinpowereduporhasbeen

reset,itwillautomaticallyenterthestatusofreadarray.Ifthemicroprocessorwantstoreadthedatastoredinthe

array,ithastodriveCE#(deviceenablecontrolpin)andOE#(Outputcontrolpin)asVil,andinputtheaddress

ofthedatatobereadintoaddresspinatthesametime.Afteraperiodofreadcycle(TceorTaa),thedatabeing

readoutwillbedisplayedonoutputpinformicroprocessortoaccess.IfCE#orOE#isVih,theoutputwillbein

tri-state,andtherewillbenodatadisplayedonoutputpinatall.

Afterthememorydevicecompletesembeddedoperation(automaticEraseorProgram),itwillautomaticallyre-

turntothestatusofreadarray,andthedevicecanreadthedatainanyaddressinthearray.Intheprocessof

erasing,ifthedevicereceivestheErasesuspendcommand,eraseoperationwillbestoppedtemporarilyaftera

periodoftimenomorethanTready1andthedevicewillreturntothestatusofreadarray.Atthistime,thedevice

canreadthedatastoredinanyaddressexceptthesectorbeingerasedinthearray.Inthestatusoferasesus-

pend,ifuserwantstoreadthedatainthesectorsbeingerased,thedevicewilloutputstatusdataontotheout-

put.Similarly,ifprogramcommandisissuedaftererasesuspend,afterprogramoperationiscompleted,system

canstillreadarraydatainanyaddressexceptthesectorstobeerased.



Thedeviceneedstoissueresetcommandtoenablereadarrayoperationagaininordertoarbitrarilyreadthe

datainthearrayinthefollowingtwosituations:

1.Inprogramoreraseoperation,theprogrammingorerasingfailurecausesQ5togohigh.

2.ThedeviceisinautoselectmodeorCFImode.

Inthe twosituations above,if resetcommand isnot issued,the deviceis notin readarray modeand system

mustissueresetcommandbeforereadingarraydata.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

SECTOR PROTECT OPERATION

Whenasectorisprotected,programoreraseoperationwillbedisabledonthatprotectedsector.MX29LV040C

providesamethodsforsectorprotection.

ThemethodisassertingVhvonA9andOE#pins,withA6andCE#atVil.Theprotectionoperationbeginsatthe

fallingedgeofWE#andterminatesattherisingedge.ContactMacronixfordetails.

CHIP UNPROTECT OPERATION

MX29LV040Cprovidesonemethodsforchipunprotect.Thechipunprotectoperationunprotectsallsectorswith-

inthedevice.Itisrecommendedtoprotectallsectorsbeforeactivatingchipunprotectmode.Allsectorgroups

areunprotectedwhenshippedfromthefactory.

ThemethodisassertingVhvonA9andOE#pins,withA6atVihandCE#atVil(seeTable2).Theunprotectop-

erationbeginsatthefallingedgeofWE#andterminatesattherisingedge.ContactMacronixfordetails.

AUTOMATIC SELECT OPERATION

WhenthedeviceisinReadarraymode,erase-suspendedreadarraymodeorCFImode,usercanissueread

siliconIDcommandtoenterreadsiliconIDmode.AfterenteringreadsiliconIDmode,usercanqueryseveral

siliconIDscontinuouslyanddoesnotneedtoissuereadsiliconIDmodeagain.WhenA0isLow,devicewillout-

putMacronixManufactureIDC2.WhenA0ishigh,devicewilloutputDeviceID.InreadsiliconIDmode,issuing

resetcommandwillresetdevicebacktoreadarraymodeorerase-suspendedreadarraymode.

AnotherwaytoenterreadsiliconIDistoapplyhighvoltageonA9pinwithCE#,OE#,A6andA1atVil.While

thehighvoltageofA9pinisdischarged,devicewillautomaticallyleavereadsiliconIDmodeandgobacktoread

arraymodeorerase-suspendedreadarraymode.WhenA0isLow,devicewilloutputMacronixManufactureID

C2.WhenA0ishigh,devicewilloutputDeviceID.

VERIFY SECTOR PROTECT STATUS OPERATION

MX29LV040CprovideshardwaresectorprotectionagainstProgramandEraseoperationforprotectedsectors.

ThesectorprotectstatuscanbereadthroughSectorProtectVerifycommand.ThismethodrequiresVhvonA9

pin,VihonWE#andA1pins,VilonCE#,OE#,A6andA0pins,andsectoraddressonA16toA18pins.Ifthe

readoutdatais01H,thedesignatedsectorisprotected.Oppositely,ifthereadoutdatais00H,thedesignated

sectorisnotprotected.

DATA PROTECTION

Toavoidaccidentalerasureorprogrammingofthedevice,thedeviceisautomaticallyresettoreadarraymode

duringpowerup.Besides,onlyaftersuccessfulcompletionofthespeciedcommandsetswillthedevicebegin

itseraseorprogramoperation.

Otherfeaturestoprotectthedatafromaccidentalalternationaredescribedasfollowed.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

LOW VCC WRITE INHIBIT

ThedevicerefusestoacceptanywritecommandwhenVccislessthan1.4V.Thispreventsdatafromspuriously

altered.ThedeviceautomaticallyresetsitselfwhenVccislowerthan1.4VandwritecyclesareignoreduntilVcc

isgreaterthan1.4V.SystemmustprovidepropersignalsoncontrolpinsafterVccislargerthan1.4Vtoavoid

unintentionalprogramoreraseoperation

WRITE PULSE "GLITCH" PROTECTION

CE#,WE#,OE#pulsesshorterthan5nsaretreatedasglitchesandwill notberegardedasaneffectivewrite

cycle.

LOGICAL INHIBIT

AvalidwritecyclerequiresbothCE#andWE#atVilwithOE#atVih.WritecycleisignoredwheneitherCE#at

Vih,WE#aVih,orOE#atVil.

POWER-UP SEQUENCE

Uponpowerup,MX29LV040Cisplacedinreadarraymode.Furthermore,programoreraseoperationwillbegin

onlyaftersuccessfulcompletionofspeciedcommandsequences.

POWER-UP WRITE INHIBIT

WhenWE#,CE#isheldatVilandOE#isheldatVihduringpowerup,thedeviceignorestherstcommandon

therisingedgeofWE#.

POWER SUPPLY DECOUPLING

A0.1uFcapacitorshouldbeconnectedbetweentheVccandGNDtoreducethenoiseeffect.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

TABLE 3. MX29LV040C COMMAND DEFINITIONS

Notes:

1.Itisnotallowedtoadoptanyothercodewhichisnotintheabovecommanddenitiontable.

Command Read

Mode

Reset

Mode

AutomaticSelect

Program Chip

Erase

Sector

Erase CFIRead Erase

Suspend

Erase

Resume

Silicon

Device

Sector

Protect

Verify

1stBus

Cyc

Addr Addr XXX 555 555 555 555 555 555 AA XXX XXX

Data Data F0 AA AA AA AA AA AA 98 B0 30

2ndBus

Cyc

Addr 2AA 2AA 2AA 2AA 2AA 2AA

Data 55 55 55 55 55 55

3rdBus

Cyc

Addr 555 555 555 555 555 555

Data 90 90 90 A0 80 80

4thBus

Cyc

Addr X00 X01 (Sector)

X02 Addr 555 555

Data C2 4F 00/01 Data AA AA

5thBus

Cyc

Addr 2AA 2AA

Data 55 55

6thBus

Cyc

Addr 555 Sector

Data 10 30

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

RESET

Inthefollowingsituations,executingresetcommandwillresetdevicebacktoreadarraymode:

• Amongerasecommandsequence(beforethefullcommandsetiscompleted)

• Sectorerasetime-outperiod

• Erasefail(whileQ5ishigh)

• Amongprogramcommandsequence(beforethefullcommandsetiscompleted,erase-suspended program

included)

• Programfail(whileQ5ishigh,anderase-suspendedprogramfailisincluded)

• ReadsiliconIDmode

• Sectorprotectverify

• CFImode

Whiledeviceisatthestatusofprogramfailorerasefail(Q5ishigh),usermustissueresetcommandtoreset

devicebacktoreadarraymode.WhilethedeviceisinreadsiliconIDmode,sectorprotectverifyorCFImode,

usermustissueresetcommandtoresetdevicebacktoreadarraymode.

Whenthedeviceisintheprogressofprogramming(notprogramfail)orerasing(noterasefail),devicewillig-

noreresetcommand.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

AUTOMATIC PROGRAMMING

TheMX29LV040CcanprovidetheuserprogramfunctionbytheformofByte-Mode.Aslongastheusersenter

therightcycledenedintheTable.3(including2unlockcyclesandA0H),anydatauserinputswillautomatically

beprogrammedintothearray.

Once the program function is executed, the internal write state controller will automatically execute the algo-

rithms and timings necessary for program and verication, which includes generating suitable program pulse,

verifyingwhetherthethresholdvoltageoftheprogrammedcellishighenoughandrepeatingtheprogrampulse

ifanyofthecellsdoesnotpassverication.Meanwhile,theinternalcontrolwillprohibittheprogrammingtocells

thatpassvericationwhiletheothercellsfailinvericationinordertoavoidover-programming.Withtheinternal

writestatecontroller,thedevicerequirestheusertowritetheprogramcommandanddataonly.

Programmingwillonlychangethebitstatusfrom"1"to"0".Thatistosay,itisimpossibletoconvertthebitstatus

from"0"to"1"byprogramming.Meanwhile,theinternalwritevericationonlydetectstheerrorsofthe"1"thatis

notsuccessfullyprogrammedto"0".

Anycommandwrittentothedeviceduringprogrammingwillbeignoredexcepthardwarereset,whichwilltermi-

natetheprogramoperationafteraperiodoftimenomorethanTready1.Whentheembeddedprogramalgorithm

iscompleteortheprogramoperationisterminatedbyhardwarereset,thedevicewillreturntothereadingarray

datamode.

ThetypicalchipprogramtimeatroomtemperatureoftheMX29LV040Cislessthan4.5seconds.

Whentheembeddedprogramoperationisongoing,usercanconrmiftheembeddedoperationisnishedor

notbythefollowingmethods:

*1:Thestatus"inprogress"meansbothprogrammodeanderase-suspendedprogrammode.

*2:Whenanattemptismadetoprogramaprotectedsector,Q7willoutputitscomplementdataorQ6continues

totoggleforabout1usorlessandthedevicereturnstoreadarraystatewithoutprogramingthedatainthepro-

tectedsector.

Status Q7 Q6 Q5

Inprogress*1 Q7# Toggling 0

Finished Q7 Stoptoggling 0

Exceedtimelimit Q7# Toggling 1

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

SECTOR ERASE

SectorEraseistoeraseallthedatainasectorwith"1"and"0"asall"1".Itrequiressixcommandcyclestois-

sue.Thersttwocyclesare"unlockcycles",thethirdoneisacongurationcycle,thefourthandftharealso

"unlockcycles"andthesixthcycleisthesectorerasecommand.Afterthesectorerasecommandsequenceis

issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector ad-

dressandsectorerasecommandcanbewrittenmultiply.Onceuserentersanothersectorerasecommand,the

time-outperiodof50usisrecounted.Ifuserentersanycommandotherthansectoreraseorerasesuspenddur-

ingtime-outperiod,theerasecommandwouldbeabortedandthedeviceisresettoreadarraycondition.The

numberofsectorscouldbefromonesectortoallsectors.Aftertime-outperiodpassingby,additionalerasecom-

mandisnotacceptedanderaseembeddedoperationbegins.

Duringsectorerasing,allcommandswillnotbeacceptedexcepthardwareresetanderasesuspendanduser

cancheckthestatusaschiperase.

Whentheembeddederaseoperationisongoing,usercanconrmiftheembeddedoperationisnishedornot

bythefollowingmethods:

CHIP ERASE

ChipEraseistoeraseallthedatawith"1"and"0"asall"1".Itneeds6cyclestowritetheactionin,andtherst

twocyclesare"unlock"cycles,thethirdoneisacongurationcycle,thefourthandftharealso"unlock"cycles,

andthesixthcycleisthechiperaseoperation.

Duringchiperasing,allthecommandswillnotbeacceptedexcepthardwareresetortheworkingvoltageistoo

lowthatchiperasewillbeinterrupted.AfterChipErase,thechipwillreturntothestateofReadArray.

Whentheembeddedchiperaseoperationisongoing,usercanconrmiftheembeddedoperationisnishedor

notbythefollowingmethods:

*1:ThestatusQ3isthetime-outperiodindicator.WhenQ3=0,thedeviceisintime-outperiodandisacceptible

toanothersectoraddresstobeerased.WhenQ3=1,thedeviceisineraseoperationandonlyerasesuspendis

valid.

*2:Whenanattemptismadetoeraseaprotectedsector,Q7willoutputitscomplementdataorQ6continues

totogglefor100usorlessandthedevicereturnedtoreadarraystatuswithouterasingthedataintheprotected

sector.

Status Q7 Q6 Q5 Q2

Inprogress 0 Toggling 0 Toggling

Finished 1Stoptoggling 0 1

Exceedtimelimit 0 Toggling 1Toggling

Status Q7 Q6 Q5 Q3 Q2

Time-outperiod 0 Toggling 0 0 Toggling

Inprogress 0 Toggling 0 1Toggling

Finished 1Stoptoggling 0 1 1

Exceedtimelimit 0 Toggling 1 1 Toggling

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

When the device has suspended erasing, user can execute the command sets except sector erase and chip

erase,suchasreadsiliconID,sectorprotectverify,program,CFIqueryanderaseresume.

SECTOR ERASE RESUME

Sectoreraseresumecommandisvalidonlywhenthedeviceisinerasesuspendstate.Aftereraseresume,user

canissueanothererasesuspendcommand,butthereshouldbea400uSintervalbetweeneraseresumeand

thenexterasesuspend.Ifuserissueinnitesuspend-resumeloop,orsuspend-resumeexceeds1024times,the

timeforerasingwillincrease.

SECTOR ERASE SUSPEND

Duringsectorerasure,sectorerasesuspendistheonlyvalidcommand.Ifuserissueerasesuspendcommand

inthetime-outperiodofsectorerasure,devicetime-outperiodwillbeoverimmediatelyandthedevicewillgo

backtoerase-suspendedreadarraymode.Ifuserissueerasesuspendcommandduringthesectoreraseisbe-

ingoperated,devicewillsuspendtheongoingeraseoperation,andaftertheTready1(<=20us)suspendnishes

andthedevicewillentererase-suspendedreadarraymode.Usercanjudgeifthedevicehasnishederasesus-

pendthroughQ6,Q7,andRY/BY#.

Afterdevicehasenterederase-suspendedreadarraymode,usercanreadothersectorsnotaterasesuspend

bythespeedofTaa;whilereadingthesectorinerase-suspendmode,devicewilloutputitsstatus.Usercanuse

Q6andQ2tojudgethesectoriserasingortheeraseissuspended.

Status Q7 Q6 Q5 Q3 Q2

Erasesuspendreadinerasesuspendedsector 1Notoggle 0 N/A Toggle

Erasesuspendreadinnon-erasesuspendedsector Data Data Data Data Data

Erasesuspendprograminnon-erasesuspendedsector Q7# Toggle 0 N/A N/A

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Table 4-1. CFI mode: Identication Data Values

(Allvaluesinthesetablesareinhexadecimal)

QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE

MX29LV040CfeaturesCFImode.Hostsystemcanretrievetheoperatingcharacteristics,structureandvendor-

specied information such as identifying information, memory size, byte conguration, operating voltages and

timinginformationofthisdevicebyCFImode.IfthesystemwritestheCFIQuerycommand"98h",toaddress

"55h"/"AAh",thedevicewillentertheCFIQueryMode,anytimethedeviceisreadytoreadarraydata.Thesys-

temcanreadCFIinformationattheaddressesgiveninTable4.

OnceuserentersCFIquerymode,usercannotissueanyothercommandsexceptresetcommand.Thereset

commandisrequiredtoexitCFImodeandgobacktothemodebeforeenteringCFI.Thesystemcanwritethe

CFIQuerycommandonlywhenthedeviceisinreadmode,erasesuspend,standbymodeorautomaticselect

mode.

Table 4-2. CFI Mode: System Interface Data Values

Description Address (h)

(Byte Mode) Data (h)

Vccsupplyminimumprogram/erasevoltage 1B 0027

Vccsupplymaximumprogram/erasevoltage 1C 0036

VPPsupplyminimumprogram/erasevoltage 1D 0000

VPPsupplymaximumprogram/erasevoltage 1E 0000

Typicaltimeoutpersingleword/bytewrite,2nus 1F 0004

Typicaltimeoutformaximum-sizebufferwrite,2nus 20 0000

Typicaltimeoutperindividualblockerase,2nms 21 000A

Typicaltimeoutforfullchiperase,2nms 22 0000

Maximumtimeoutforword/bytewrite,2ntimestypical 23 0005

Maximumtimeoutforbufferwrite,2ntimestypical 24 0000

Maximumtimeoutperindividualblockerase,2ntimestypical 25 0004

Maximumtimeoutforchiperase,2ntimestypical 26 0000

Description Address (h)

(Byte Mode) Data (h)

Query-uniqueASCIIstring"QRY"

10 0051

11 0052

12 0059

PrimaryvendorcommandsetandcontrolinterfaceIDcode 13 0002

14 0000

Addressforprimaryalgorithmextendedquerytable 15 0040

16 0000

AlternatevendorcommandsetandcontrolinterfaceIDcode(none) 17 0000

18 0000

Addressforalternatealgorithmextendedquerytable(none) 19 0000

1A 0000

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Table 4-3. CFI Mode: Device Geometry Data Values

Description Address (h)

(Byte Mode) Data (h)

Devicesize=2ninnumberofbytes 27 0013

Flashdeviceinterfacedescription(02=asynchronousx8/x16) 28 0000

29 0000

Maximumnumberofbytesinbufferwrite=2n(notsupport) 2A 0000

2B 0000

Numberoferaseregionswithindevice 2C 0001

IndexforEraseBankArea1

2D 0007

2E 0000

2F 0000

30 0001

IndexforEraseBankArea2

31 0000

32 0000

33 0000

34 0000

IndexforEraseBankArea3

35 0000

36 0000

37 0000

38 0000

IndexforEraseBankArea4

39 0000

3A 0000

3B 0000

3C 0000

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Table 4-4. CFI Mode: Primary Vendor-Specic Extended Query Data Values

Description Address (h)

(Byte Mode) Data (h)

Query-Primaryextendedtable,uniqueASCIIstring,PRI

40 0050

41 0052

42 0049

Majorversionnumber,ASCII 43 0031

Minorversionnumber,ASCII 44 0030

Unlockrecognizesaddress(0=recognize,1=don'trecognize) 45 0001

Erasesuspend(2=tobothreadandprogram) 46 0002

Sectorprotect(N=#ofsectors/group) 47 0001

Temporarysectorunprotect(1=supported) 48 0001

Sectorprotect/Chipunprotectscheme 49 0004

SimultaneousR/Woperation(0=notsupported) 4A 0000

Burstmode(0=notsupported) 4B 0000

Pagemode(0=notsupported) 4C 0000

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

ABSOLUTE MAXIMUM STRESS RATINGS

OPERATING TEMPERATURE AND VOLTAGE

Commercial (C) Grade SurroundingTemperature(TA) 0°Cto+70°C

Industrial (I) Grade SurroundingTemperature(TA) -40°Cto+85°C

VCC Supply Voltages VCCrange +2.7Vto3.6V

SurroundingTemperaturewithBias -65°Cto+125°C

StorageTemperature -65°Cto+150°C

VoltageRange

VCC -0.5Vto+4.0V

A9andOE# -0.5Vto+12.5V

Theotherpins -0.5VtoVcc+0.5V

OutputShortCircuitCurrent(lessthanonesecond) 200mA

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

DC CHARACTERISTICS

Symbol Description Min. Typ. Max. Remark

Iilk InputLeak  ± 1.0uA

Iilk9 A9Leak 35uA A9=12.5V

Iolk OutputLeak ± 1.0uA

Icr1 ReadCurrent(5MHz) 7mA 12mA CE#=Vil,OE#=Vih

Icr2 ReadCurrent(1MHz) 2mA 4mA CE#=Vil,OE#=Vih

Icw WriteCurrent 15mA 30mA CE#=Vil,OE#=Vih,

WE#=Vil

Isb StandbyCurrent 0.2uA 5uA Vcc=Vccmax,

otherpindisable

Isbs SleepModeCurrent 0.2uA 5uA

Vil InputLowVoltage -0.5V  0.8V

Vih InputHighVoltage 0.7xVcc  Vcc+0.3V

Vhv VeryHighVoltageforhardware

Protect/Unprotect/AutoSelect 11.5V 12.5V

Vol OutputLowVoltage 0.45V Iol=4.0mA

Voh1 OuputHighVoltage 0.85xVcc Ioh1=-2mA

Voh2 OuputHighVoltage Vcc-0.4V Ioh2=-100uA

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

SWITCHING TEST CIRCUITS

TestCondition

OutputLoad:1TTLgate

OutputLoadCapacitance,CL:30pF(70ns)/100pF(90ns)

Rise/FallTimes:5ns

In/Outreferencelevels:1.5V

SWITCHING TEST WAVEFORMS

1.5V 1.5V

Test Points

3.0V

0.0V

OUTPUT

INPUT

R1=6.2Kohm

R2=2.7Kohm

TESTED DEVICE

DIODES=IN3064

OR EQUIVALENT

Vcc

0.1uF

+3.3V

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

AC CHARACTERISTICS

Symbol Description Min. Typ. Max. Unit

Taa Validdataoutputafteraddress 55/70/90 ns

Tce ValiddataoutputafterCE#low 55/70/90 ns

Toe ValiddataoutputafterOE#low 30/30/35 ns

Tdf DataoutputoatingafterOE#highorCE#high 25/25/30 ns

Toh Outputholdtimefromtheearliestrisingedgeofaddress,

CE#,OE# 0  ns

Trc Readperiodtime 55/70/90 ns

Twc Writeperiodtime 70/90 ns

Tcwc Commandwriteperiodtime 70/90 ns

Tas Addresssetuptime 0 ns

Tah Addressholdtime 45 ns

Tds Datasetuptime 35/45 ns

Tdh Dataholdtime 0 ns

Tvcs Vccsetuptime 50 us

Tcs ChipenableSetuptime 0 ns

Tch Chipenableholdtime 0 ns

Toes Outputenablesetuptime 0 ns

Toeh Outputenableholdtime Read 0 ns

Toggle&Data#Polling 10 ns

Tws WE#setuptime 0 ns

Twh WE#holdtime 0 ns

Tcep CE#pulsewidth 35 ns

Tceph CE#pulsewidthhigh 30 ns

Twp WE#pulsewidth 35 ns

Twph WE#pulsewidthhigh 30 ns

Tghwl Readrecovertimebeforewrite 0  ns

Tghel Readrecovertimebeforewrite 0  ns

Twhwh1 Programoperation 9 us

Twhwh2 Sectoreraseoperation 0.7 sec

Tbal Sectoraddholdtime 50 us

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 1. COMMAND WRITE OPERATION

Addresses

CE#

OE#

WE#

DIN

Tds

Tah

Data

Tdh

Tce Tch

Tcwc

Twph

Twp

Toes

Tas

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

VA: Valid Address

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

READ OPERATION

Figure 2. READ TIMING WAVEFORMS

Addresses

CE#

OE#

Taa

WE#

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Voh

Vol

HIGH Z HIGH Z

DATA Valid

Toe

Toeh Tdf

Tce

Trc

Outputs

Toh

ADD Valid

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

ERASE/PROGRAM OPERATION

Figure 3. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Twc

Address

OE#

CE#

55h 10h

2AAh 555h

Progress Complete

VA VA

Tas Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh2

Read Status

Last 2 Erase Command Cycle

Tcs Twph

WE#

Data

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO Data=FFh ?

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Data# Polling Algorithm or

Toggle Bit Algorithm

Auto Chip Erase Completed

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 5. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Twc

Address

OE#

CE#

55h

Sector

Address 1

Sector

Address 0

2AAh

30h

Progress Complete

VA VA

30h

Sector

Address n

Tas

Tah

Tbal

Tghwl

Tch

Twp

Tds Tdh

Twhwh2

Read Status

Last 2 Erase Command Cycle

Tcs Twph

WE#

Data

30h

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data Address 555H

Write Data 80H Address 555H

Write Data 30H Sector Address

Write Data Address 2AAH

Data# Polling Algorithm or

Toggle Bit Algorithm

Auto Sector Erase Completed

Last Sector

to Erase

YES

Data=FFh

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 7. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

ERASE SUSPEND

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

ERASE RESUME

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 8. AUTOMATIC PROGRAM TIMING WAVEFORMS

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh1

Last 2 Read Status CycleLast 2 Program Command Cycle

Tcs Twph

WE#

Data

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 9. CE# CONTROLLED WRITE TIMING WAVEFORM

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tcep

Tds Tdh

Twhwh1 or Twhwh2

Tceph

WE#

Data

TwhTws

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 10. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Read Again Data:

Program Data?

YES

Auto Program Completed

Data# Polling Algorithm or

Toggle Bit Algorithm

next address

Last Byte to be

Programed

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

SECTOR PROTECT/CHIP UNPROTECT

Figure 11. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM

150us: Sector Protect

15ms: Chip Unprotect

1us

Data

SA, A6

A1, A0

CE#

WE#

OE#

VA VA VA

Status

VA: valid address

40h60h60h

Verification

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 12. SILICON ID READ TIMING WAVEFORM

Taa

Tce

Taa

Toe

Toh Toh

Tdf

DATA OUT

C2H 4FH

Vhv

Vih

Vil

ADD

CE#

OE#

WE#

DATA OUT

DATA

Q7~Q0

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

WRITE OPERATION STATUS

Figure 13. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

Tdf

Tce

Tch

Toe

Toeh

Toh

CE#

OE#

WE#

Q6~Q0 Status Data Status Data

ComplementComplement True Valid Data

Taa

Trc

Address VAVA

High Z

Valid DataTrue

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 14. DATA# POLLING ALGORITHM

Read Q7~Q0 at valid address

(Note 1)

Read Q7~Q0 at valid address

Start

Q7 = Data# ?

Q5 = 1 ?

Q7 = Data# ?

(Note 2)

FAIL Pass

Yes

Notes:

1.Forprogramming,validaddressmeansprogramaddress.

Forerasing,validaddressmeanserasesectorsaddress.

2. Q7shouldberecheckedevenQ5="1"becauseQ7maychangesimultaneouslywithQ5.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 15. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

Tdf

Tce

Tch

Toe

Toeh

Taa

Trc

Toh

Address

CE#

OE#

WE#

Q6/Q2

Valid Status

(first read)

Valid Status

(second read) (stops toggling)

Valid Data

VA VA

VA : Valid Address

Valid Data

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

Figure 16. TOGGLE BIT ALGORITHM

Notes:

1.Readtogglebittwicetodeterminewhetherornotitistoggling.

2.RechecktogglebitbecauseitmaystoptogglingasQ5changesto"1".

Read Q7-Q0 Twice

Q5 = 1?

Read Q7~Q0 Twice

PGM/ERS fail

Write Reset CMD PGM/ERS Complete

Q6 Toggle ?

(Note 1)

YES

Start

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

ACtimingillustratedinFigureAisrecommendedforthesupplyvoltagesandthecontrolsignalsatdevicepower-

up.Ifthetiminginthegureisignored,thedevicemaynotoperatecorrectly.

Figure A. AC Timing at Device Power-Up

Vcc

ADDRESS

CE#

WE#

OE#

DATA

Tvr

Taa

Tr or Tf Tr or Tf

Tce

Vcc(min)

GND

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Voh

High Z

Vol

Valid

Ouput

Valid

Address

Tvcs

Toe

Tf Tr

Symbol Parameter Min. Max. Unit

Tvr VccRiseTime 20 500000 us/V

Tr InputSignalRiseTime  20 us/V

Tf InputSignalFallTime  20 us/V

Note:Nottested100%.

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

PIN CAPACITANCE

Parameter Limits Units

Min. Typ. Max.

ChipEraseTime 4 32 sec

SectorEraseTime 0.7 8 sec

Erase/ProgramCycles 100,000 Cycles

ChipProgrammingTime 4.5 13.5 sec

ByteProgrammingTime 9 300 us

Min. Max.

InputVoltagedifferencewithGNDonA9,OE#pins -1.0V 12.5V

InputVoltagedifferencewithGNDonallI/Opins -1.0V Vcc+1.0V

Inputcurrentpulse -100mA +100mA

AllpinsincludedexceptVcc.Testconditions:Vcc=3.0V,onepinpertesting

Parameter Symbol Parameter Description Test Set Max. Unit

CIN2 ControlPinCapacitance VIN=0 12 pF

COUT OutputCapacitance VOUT=0 12 pF

CIN InputCapacitance VIN=0 8 pF

DATA RETENTION

Parameter Condition Min. Max. Unit

Dataretention 55˚C 20 years

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(ns)

OPERATING

CURRENT MAX.

(mA)

STANDBY

CURRENT MAX.

(uA)

PACKAGE Remark

MX29LV040CTC-55Q 55 30 5 32PinTSOP

(8x20mm) 

MX29LV040CTC-70G 70 30 5 32PinTSOP

(8x20mm) 

MX29LV040CTC-90G 90 30 5 32PinTSOP

(8x20mm) 

MX29LV040CQC-55Q 55 30 5 32PinPLCC 

MX29LV040CQC-70G 70 30 5 32PinPLCC 

MX29LV040CQC-90G 90 30 5 32PinPLCC 

MX29LV040CTI-55Q 55 30 5 32PinTSOP

(8x20mm) 

MX29LV040CTI-70G 70 30 5 32PinTSOP

(8x20mm) 

MX29LV040CTI-90G 90 30 5 32PinTSOP

(8x20mm) 

MX29LV040CQI-55Q 55 30 5 32PinPLCC 

MX29LV040CQI-70G 70 30 5 32PinPLCC 

MX29LV040CQI-90G 90 30 5 32PinPLCC 

MX29LV040CT2I-70G 70 30 5 32PinTSOP

(8x14mm) 

MX29LV040CT2I-90G 90 30 5 32PinTSOP

(8x14mm) 

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

PART NAME DESCRIPTION

MX 29 LV 70C T C G

OPTION:

G: RoHS compliant package

Q: Restricted VCC (3.0V~3.6V) with RoHS compliant package

SPEED:

55: 55ns

70: 70ns

90: 90ns

TEMPERATURE RANGE:

C: Commercial (0°C to 70°C)

I: Industrial (-40°C to 85°C)

PACKAGE:

Q: PLCC

T: TSOP (8mm x 20mm)

T2: TSOP (8mm x 14mm)

REVISION:

DENSITY & MODE:

040: 4M, x8 Equal Sector

TYPE:

L, LV: 3V

DEVICE:

29:Flash

040

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

PACKAGE INFORMATION

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

P/N:PM1149 REV. 2.6, APR. 11, 2012

MX29LV040C

REVISION HISTORY

Revision No. Description Page Date

1.0 1.Removed"Preliminary" P1 JUN/30/2005

 2.Added"RecommendedOperatingConditions" P43

1.1 1.Modied"Lowpowerconsumption--activecurrent"from20mA(Max.)P1 AUG/30/2005

 to30mA(Max.)

 2.AddeddescriptionaboutPb-freedevicesareRoHSCompliant P1

1.2 1.ModiedEraseResumefromdelay10mstodelay400us P12,32 JAN/17/2006

1.3 1.Modiedtable15.CFImode P45,46 APR/24/2006

 2.AddedVLKOdescription P15,18

1.4 1.ModiedCFImode P45,46 JUL/11/2006

1.5 1.Datasheetformatchanged All AUG/15/2006

1.6 1.Datamodication All AUG/16/2006

1.7 1.Datamodication All AUG/17/2006

1.8 1.Addedstatement P44 NOV/06/2006

1.9 1.Revisedstatement P14 DEC/28/2007

2.0 1.Addednote1intotable3.CommandDenitions P9 JAN/17/2008

2.1 1.ModiedFigure9.CE#ControlledWriteTimingWaveform P29 FEB/21/2008

2.2 1.RevisedTwc,Tcwc,TdsACtimingspec P20 JUL/31/2008

2.3 1.Added32-TSOP(8mmx14mm)packageinformation P1,2,39 MAR/25/2009

  P40,43

2.4 1.Addeddataretentiontable P38 AUG/21/2009

 2.Modiedthesectorerasetimemaxfrom15sto8s P38

 3.DeletedLeadEPN P39,40

2.5 1.ModieddescriptionforRoHScompliance P1,40 DEC/15/2011

 2.Addednote P37

2.6 1.ModiedPartNameDescription P40 APR/11/2012

2.ModiedFigure9.CE#ControlledWriteTimingWaveform P29



MX29LV040C

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specications without notice.

Exceptfor customizedproductswhich hasbeen expressly identiedin theapplicableagreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

householdapplicationsonly,andnotforuseinanyapplicationswhichmay,directlyorindirectly,causedeath,

personalinjury,orseverepropertydamages.IntheeventMacronixproductsareusedincontradictedtotheir

targetusageabove,thebuyershalltakeanyandallactionstoensuresaidMacronix'sproductqualiedforits

actualuseinaccordancewiththeapplicablelawsandregulations;andMacronixaswellasit’ssuppliersand/or

distributorsshallbereleasedfromanyandallliabilityarisentherefrom.

tradenamethereof,suchasMacronix,MXIC,MXICLogo,MXLogo,IntegratedSolutionsProvider,NBit,

Nbit, NBiit, Macronix NBit, eLiteFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO,

MacronixvEE, Macronix MAP, RichAudio, RichBook,RichTV,andFitCAM.Thenamesandbrandsof

other companies are for identication purposes only and may be claimed as the property of the respective

companies.

Forthecontactandorderinformation,pleasevisitMacronix’sWebsiteat:http://www.macronix.com