LP55271
LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I2C
Programmability, Connectivity Test and Audio Synchronization
Literature Number: SNVS460
LP55271
Tiny LED Driver for Camera Flash and 4 LEDs with I
2
C
Programmability, Connectivity Test and Audio
Synchronization
General Description
The LP55271 is a lighting management unit for handheld
devices with I
2
C compatible control interface. The LP55271
has a step-up DC/DC converter with high current output and
it drives display and keypad backlights and powers the cam-
era flash LED. In addition the DC/DC converter has the
output current to power for example an audio amplifier si-
multaneously. The chip has four 8-bit programmable high
efficiency constant current LED drivers and a FLASH LED
driver. Built-in audio synchronization feature allows the user
to synchronize one of the LEDs to audio input.
The LP55271 has an integrated 370 mA flash driver with a
safety stop feature and 46 mA torch mode. An external
enable pin is provided for the synchronizing the flash with the
camera action. An external software independent test inter-
face provides a fast way to find a broken path or short on
LED circuits. Very small microSMD package together with
minimum number of external components is a best fit for
handheld devices.
Features
nHigh current boost DC-DC converter (up to 1A output
current)
nProgrammable boost output voltage
n370 mA flash LED constant current driver with low
tolerance and a safety circuit
nSynchronization pin for the flash timing
nTwo single-ended audio inputs with gain control
nFour constant current 15 mA LED drivers with 8-bit
programmable brightness control
nAudio synchronization feature
nI
2
C compatible control interface
nBuilt-in LED connectivity test to maximize manufacturing
yield
nSmall microSMD-30 package (2.5 mm x 3.0 mm x 0.6
mm)
Applications
nCamera FLASH, funlight and backlight driving in battery
powered devices
Typical Application
20202401
September 2006
LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I
2
C Programmability, Connectivity
Test and Audio Synchronization
© 2006 National Semiconductor Corporation DS202024 www.national.com
Connection Diagrams and Package Mark Information
CONNECTION DIAGRAMS
microSMD-30 package, 2.466 x 2.974 x 0.60 mm body size, 0.5 mm pitch NS Package Number TLA3011A
20202402
Top View 20202403
Bottom View
PACKAGE MARK
20202404
Top View
XY — Date Code
TT — Die Traceability
D55B — Product Identification
ORDERING INFORMATION
Order Number Package Marking Supplied As Spec/Flow
LP55271TL D55B TNR 250 NoPB
LP55271TLX D55B TNR 3000 NoPB
LP55271
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Connection Diagrams and Package Mark Information (Continued)
Pin Descriptions
Pin Name Type Description
D3 VDD1 P Supply Voltage
A1 VDD2 P Supply Voltage
F5 SW1 A Boost Converter Switch
E5 SW2 A Boost Converter Switch
D5 FB A Boost Converter Feedback
B5 LED1 O LED1 Driver Output
A5 LED2 O LED2 Driver Output
B4 LED3 O LED3 Driver Output
A4 LED4 O LED4 Driver Output
F2 FLASH O Flash LED Driver Output
F3 GNDC G Ground for Core Circuitry
D2 RT A Oscillator Frequency Setting
C1 VREF A Reference Voltage
B1 VDDA P Internal LDO
F4 GND_SW1 G Boost Converter Ground
E4 GND_SW2 G Boost Converter Ground
C5 GND_LED G LEDs 1 to 4 Driver Ground Connection
F1 GND_FLASH G Flash Driver Ground Connection
A2 IFLASH A Resistor for Flash Current Setting
D1 GNDA G Analog Ground Connection
C3 GND G Ground
E1 VDD_IO P Supply Voltage for Digital Interface
A3 NRST DI Low Active Reset
B3 SCL DI I
2
C Compatible Interface Clock Signal
E2 SDA OD I
2
C Compatible Interface Data Signal
E3 FLASH_SYNC DI FLASH LED Control
D4 T2 DO Test Pin (Result)
C4 T1 DI Test Pin (Clock)
C2 ASE1 AI Audio Input
B2 ASE2 AI Audio Input
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin
I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin
LP55271
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage on power pins (V
DD1,2
) -0.3V to +6.0V
Voltage on analog pins -0.3V to V
DD1,2
+0.3V
with 6.0V max
Voltage on input/output pins -0.3V to V
DD1,2
+0.3V
with 6.0V max
V(all other pins): Voltage to GND -0.3V to 6.0V
I(V
REF
)10µA
I(FLASH) 500 mA
Continuous Power Dissipation
(Note 3)
Internally Limited
Junction Temperature (T
J-MAX
) 125oC
Storage Temperature Range -65oC to +150oC
Maximum Lead Temperature
(Reflow soldering, 3 times)
(Note 4)
260oC
ESD Rating (Note 5)
Human Body Model 2 kV
Operating Ratings (Note 1),(Note 2)
Voltage on power pins (V
DD1,2
) 3.0 to 5.5V
Voltage on ASE1, ASE2 0V to 1.6V
V
DD_IO
1.65V to V
DD1
Junction Temperature (T
J
) Range -30oC to +125oC
Ambient Temperature (T
A
) Range
(Note 6)
-30oCto+85
oC
Thermal Properties
Junction-to-Ambient Thermal
Resistance (θ
JA
),
TLA3011A Package (Note 7)
60 - 100oC/W
Electrical Characteristics (Notes 2, 8)
Limits in standard typeface are for T
J
=25
oC. Limits in boldface type apply over the operating ambient temperature range
(-30oC<T
A
<+85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: V
IN
= 3.6V, C
IN
=
10 µF, C
OUT1
= 10 µF, C
OUT2
= 10 µF, C
VDD_IO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF, C
VDD2
= 100
nF, L
1
= 4.7 µH. (Note 9)
Symbol Parameter Condition Min Typ Max Units
I
SHUT DOWN
Current of V
DD1
+V
DD2
pins +
Leakage Current of SW1, SW2,
LED1 to 4 and FLASH
Voltage on V
DD_IO
= 0V, NRST = L,
NSTBY(bit) = L
15µA
I
DD
Active Mode Supply Current
(V
DD1
+V
DD2
current)
NRST = H, NSTBY(bit) = H, no load,
EN_BOOST(bit) = L, SCL, SDA = H
350 µA
I
DD
No load supply current
(V
DD1
+V
DD2
current)
NSTBY(bit) = H, EN_BOOST(bit) = H,
SCL, SDA, NRST = H,
AUTOLOAD_EN(bit) = L
850 µA
I
VDDIO
V
DD_IO
Standby Supply current NSTBY(bit) = L 1µA
V
DDA
I
VDDA
=1mA -4% 2,8V +4% V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 160oC (typ.) and disengages at TJ=
140oC (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale
Package.
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125oC), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX =T
J-MAX-OP –(θJA xP
D-MAX).
Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
LP55271
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LP55271 Block Diagram
20202405
LP55271
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Modes of Operation
20202406
RESET: In the reset mode all the internal registers are reset to the default values. Reset is entered always if input
NRST is LOW or internal Power On Reset (POR) is active. Power on reset will activate during the chip
startup or when the supply voltage V
DD2
falls below 1.5V. Once V
DD2
rises above 1.5V, POR will inactivate
and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR by default.
STANDBY: The standby mode is entered if the register bit NSTBY is LOW and reset is not active. This is the low power
consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the
control bits are effective immediately after start up.
STARTUP: When NSTBY bit is written high, the internal startup sequence powers up all the needed internal blocks
(V
REF
, Oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the
internal state-machine. If the chip temperature rises too high, the thermal shutdown (TSD) disables the chip
operation and startup mode is entered until no thermal shutdown event is present.
BOOST STARTUP: Soft-start for boost output is generated in the boost startup mode. The boost output is raised in a low current
PWM mode during the 10 ms delay generated by the state-machine. The boost startup is entered from
internal startup sequence if EN_BOOST is HIGH or from normal mode when EN_BOOST is written HIGH.
NORMAL: During normal mode the user controls the chip using the Control Registers. The registers can be written in
any sequence and any number of bits can be altered in a register in one write.
LP55271
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Magnetic Boost DC/DC Converter
The LP55271 boost DC/DC converter generates a 4.00 –
5.40V output voltage to drive the LEDs from a single Li-Ion
battery (3.0V to 4.5V). The output voltage is controlled with a
4-bit register in 8 steps. The converter is a magnetic switch-
ing PWM mode DC/DC converter with a current limit. The
converter has 2.0 MHz / 1.0 MHz selectable switching fre-
quency operation, when the timing resistor RT is 82 kΩ.
The LP55271 boost converter uses pulse-skipping elimina-
tion method to stabilize the noise spectrum. Even with light
load or no load a minimum length current pulse is fed to the
inductor. An internal active load is used to remove the ex-
cess charge from the output capacitor when needed.
The topology of the magnetic boost converter is called CPM
control, current programmed mode, where the inductor cur-
rent is measured and controlled with the feedback. The
output voltage control changes the resistor divider in the
feedback loop.
The following figure shows the boost topology with the pro-
tection circuitry. Four different protection schemes are imple-
mented:
1. Over voltage protection, limits the maximum output volt-
age.
— Keeps the output below breakdown voltage.
— Prevents boost operation if battery voltage is much
higher than desired output.
2. Over current protection, limits the maximum inductor
current.
— Voltage over switching NMOS is monitored; too high
voltages turn the switch off.
3. Feedback (FB) protection for no connection.
4. Duty cycle limiting, done with digital control.
20202477
Boost Converter Topology
LP55271
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Magnetic Boost DC/DC Converter (Continued)
MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for T
J
=25
oC. Limits in boldface type apply over the operating ambient temperature
range (-30oC<T
A
<+85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: V
IN
=
3.6V, C
IN
=10µF,C
OUT1
=10µF,C
OUT2
=10µF,C
VDDIO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF,
C
VDD2
= 100 nF, L
1
= 4.7 µH. (Note 9)
Symbol Parameter Conditions Min Typ Max Units
I
LOAD
Load Current
(Note 10)
3.2V ≤V
IN
≤4.5V
V
OUT
= 5.0V
670 mA
V
OUT
Output Voltage Accuracy
(FB pin)
3.2V ≤V
IN
≤4.5V
V
OUT
(target value) = 5.0V,
active load off
−5 +5 %
Output Voltage
(FB Pin)
3.0V ≤V
IN
≤(5.0V+V
SCHOTTKY
)
active load off
5.0 V
V
IN
>(5.0V + V
SCHOTTKY
)V
IN
-V
SCHOTTKY
RDS
ON
Switch ON Resistance V
IN
= 3.6V, I
SW
= 1.0A 0.20 0.4 Ω
f
PWF
PWM Mode Switching
Frequency
RT=82kΩ
FREQ_SEL (bit) = 1
FREQ_SEL (bit) = 0
2.0
1.0
MHz
Frequency Accuracy 3.2V ≤V
DD1,2
≤5.0V
RT=82kΩ
−6
-9
±3+6
+9
%
t
PULSE
Switch Pulse Minimum
Width
no load 25 ns
t
STARTUP
Startup Time 10 ms
I
CL_OUT
SW1 + SW2 current limit 1.7 A
Note 10: Specified currents are the worst case currents. If input voltage is larger or output voltage is smaller, current can be increased according to graph "Boost
Maximum Output Current".
BOOST STANDBY MODE
User can set the boost converter to STANDBY mode by
writing the register bit EN_BOOST low when there is no load
to avoid idle current consumption. When EN_BOOST is
written high, the converter starts in low current PWM (Pulse
Width Modulation) mode for 10 ms and then goes to normal
PWM mode.
BOOST CONTROL REGISTERS
User can control the boost output voltage and the switching
frequency according to the following tables.
Boost Output Voltage
[3:0] Register
Boost Output Voltage (V)
(Typical)
0000 4.00
0001 4.20
0011 4.40
0111 4.60 default
1000 4.80
1001 5.00
1011 5.20
1111 5.40
FREQ_SEL Bit
Boost Switching
Frequency
(Typical)
0 1.0 MHz default
1 2.0 MHz
LP55271
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Boost Converter Typical Performance Characteristics
T
J
=25
oC. Unless otherwise noted, typical performance characteristics apply to the LP55271 Block Diagram with: V
IN
= 3.6V,
V
OUT
= 5.0V, C
IN
=10µF,C
OUT1
=10µF,C
OUT2
=10µF, C
VDD_IO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF,
C
VDD2
= 100 nF, L1 = 4.7 µH (Note 9).
Boost Converter Efficiency Boost Typical Waveforms at 100 mA Load
20202479 20202480
Battery Current vs Voltage Boost Frequency vs RT Resistor
20202481 20202482
Boost Line Regulation 3.0V - 3.6V Boost Startup to 5.4V with no Load
20202483 20202484
LP55271
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Boost Converter Typical Performance Characteristics (Continued)
Boost Load Transient Response, 50 mA to 100 mA Boost Maximum Output Current
20202485 20202498
LP55271
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Flash Driver
LP55271 has an internal constant current driver that is ca-
pable for sinking low (46 mA) and high (370 mA) current
mainly targeted for torch and flash LED in camera phone
applications. 370 mA flash driver can be hardware or soft-
ware enabled. Flash safety function prevents hardware dam-
ages due to possible overheating when the flash has been
stuck on because of a hardware, software or user error.
Flash safety counter starts counting when the flash is acti-
vated and disables the flash automatically when the pre-
defined 1.0s or 2.0s time limit is reached. Flash is activated
with FLASH_SYNC bit or FLASH_SYNC pin, as defined in
the table below. Safety time limit is defined by SAFETY-
_TIME bit. (Time limit is 2.0s if SAFETY_TIME bit is low and
1.0s if the bit is high.)
Flash driver currents — both torch and flash — are set with
external resistor R
F
. The flash current is 480/R
F
amperes
and the torch current is 60/R
F
amperes. User should not use
lower resistance value than 1200Ω.
Flash LED Control (X = don’t care)
EN_TORCH bit EN_FLASH bit FLASH_SYNC bit or pin SAFETY_TIME bit Flash LED Action
0 0 X X Off
1 0 X X Torch
X 1 Change from LOW to HIGH to
engage; from HIGH to LOW to
disengage
0 for 2.0 seconds;
1 for 1.0 second
Flash
Flash Programming Example
Address Data Function
00H 8FH Sets safety time to 1.0s. In this example LED1 to LED4 are enabled.
00H 9FH Enables torch.
00H FFH Activates FLASH. EN_FLASH bit and FLASH_SYNC bit are written simultaneously because EN_FLASH
disables torch.
00H BFH Disables FLASH. If FLASH is disabled by safety time, FLASH_SYNC bit needs to be written to 0 before
next FLASH.
FLASH DRIVER ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for T
J
=25
oC. Limits in boldface type apply over the operating ambient temperature range (-30oC
<T
A
<+85 oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: V
IN
= 3.6V, C
IN
=10µF,C
OUT1
=10µF,C
OUT2
=10µF,C
VDDIO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF, C
VDD2
= 100 nF, L
1
= 4.7 µH, R
F
= 1300Ω
Symbol Parameter Condition Min Typ Max Units
I
FLASH
Flash Mode Sink Current
(Note 8)
3.0V ≤V
IN
≤5.5V,
V
FLASH
= 1.0V -7.5
370
+7.5
mA
%
I
TORCH
Torch Mode Sink Current
(Note 8)
3.0V ≤V
IN
≤5.5V 46 mA
I
LEAKAGE
Flash Driver Leakage Current V
FB
= 5.0V 0.1 µA
t
FLASH
Flash Turn-On Time
(Note 11)
20 µs
V
SAT
Saturation Voltage 3.0V ≤V
IN
≤5.5V,
Current Decreased to 95% of
the Maximum Sink Current
550 mV
t
SAFETY
Safety Time Accuracy -9 +9 %
Note 11: Flash turn-on time is measured from the moment the flash is activated until the flash current crosses 90% of its target value.
LP55271
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Constant Current Sink Outputs LED1, LED2, LED3, LED4
LP55271 has four independent backlight/keypad LED driv-
ers. All the drivers are regulated constant current sinks. LED
currents are controlled by 8-bit current mode DACs. Every
driver can be controlled in two ways:
1. Brightness control with constant current drivers
2. Direct ON/OFF control. The current is pre-set by 8-bit
current mode DAC.
In addition, LED1 driver can be synchronized to audio input
signal amplitude.
By using brightness control user can set brightness of every
single LED by using 8-bit brightness control registers. If
analog audio is available on system the user can use audio
synchronization for synchronizing LED1 to the music. Direct
ON/OFF control is mainly for switching LEDs on and off.
LED Control Register (00 hex) has control bits for direct
on/off control of all the LEDs. Note that the LEDs have to be
turned on in order to control them with audio synchronization
(LED1 only) or brightness control.
The brightness is programmed as described in the following.
I
LED
= n x (15 mA / 255)
where:
n = LED[7:0] (8-bit)
step = 15 mA / 255 ≈0.05882 mA
For example if 13.2 mA is required for driver current:
n = 13.2 mA / (15 mA / 255) ≈224
224 = 1110 0000, E0 hex
LED1 to LED4 Brightness Control
LED1[7:0], LED2[7:0], LED3[7:0] and LED4[7:0] Registers Driver Current, mA (typical)
0000 0000 0
0000 0001 0.059
0000 0010 0.118
••
1110 0000 13.176
••
1111 1110 14.941
1111 1111 15
LED1 TO LED4 DRIVERS ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for T
J
=25
oC. Limits in boldface type apply over the operating ambient temperature range (-30oC
<T
A
<+85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: V
IN
= 3.6V, C
IN
=10µF,C
OUT1
=10µF,C
OUT2
=10µF,C
VDDIO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF, C
VDD2
= 100 nF, L
1
= 4.7 µH. (Note
9)
Symbol Parameter Condition Min Typ Max Units
I
MAX
Maximum Sink Current 15 mA
I
LEAKAGE
Leakage Current V
FB
= 5.0V 0.03 µA
I
LED
Current Tolerance I
SINK
= 13.2 mA (target value)
-7
13.2
+7
mA
%
I
MATCH
Sink Current Matching
Between LED 1 to 4
I
SINK
= 13.2 mA 1 %
V
SAT
Saturation Voltage 3.0V ≤V
IN
≤5.5V,
Current Decreased to 95% of the
Maximum Sink Current
150 230 mV
Note: Sink current matching is the maximum difference from the average.
LP55271
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Audio Synchronization
The LED1 output can be synchronized to incoming audio
signal with Audio Synchronization feature. Audio Synchroni-
zation synchronizes LED1 based on input signal’s peak am-
plitude. Programmable gain and automatic gain control func-
tion are also available for adjustment of input signal
amplitude to light response. Control of LED1 brightness
refreshing frequency is done with four different frequency
configurations. The digitized input signal has a DC compo-
nent that is removed by a digital DC-remover. The DC-
remover is a high-pass filter where corner frequency is user
selectable by using DC_FREQ bit. LP55271 has 2-channel
audio (stereo) input for audio synchronization, as shown in
the figure below. The inputs accept signals in the range of 0V
to 1.6V peak-to-peak and these signals are mixed into a
single wave so that they can be filtered simultaneously.
LP55271 audio synchronization is mainly done digitally and
it consists following signal path blocks (see figure below).
•Input buffer
•AD converter
•Automatic Gain Control (AGC) and manually program-
mable gain
•Peak detector
Automatic Gain Control (AGC) adjusts the input signal to
suitable range automatically. User can disable AGC and the
gain can be set manually with programmable gain. Audio
synchronization is based on peak detection method.
20202416
Audio Synchronization Input Electrical Parameters
Symbol Parameter Conditions Min Typ Max Units
Z
IN
Input Impedance of
ASE1, ASE2
10 15 kΩ
A
IN
ASE1, ASE2 Audio
Input Level Range
(peak-to-peak)
Min input level needs maximum gain;
Max input level for minimum gain.
0 1600 mV
CONTROL OF AUDIO SYNCHRONIZATION
The following table describes the controls required for audio synchronization. LED1 brightness control through serial interface is
not available when audio synchronization is enabled.
Audio Synchronization Control
EN_SYNC Audio synchronization enabled. Set EN_SYNC=1toenable audio synchronization or 0 to disable.
EN_AGC Automatic gain control. Set EN_AGC=1toenable automatic control or 0 to disable.
When EN_AGC is disabled, the audio input signal gain value is defined by GAIN_SEL.
GAIN_SEL[2:0] Input signal gain control. Gain has a range from 0 dB to -46 dB.
SPEED_CTRL[1:0] Control for refreshing frequency. Sets the typical refreshing rate for the LED1 output.
THRESHOLD[3:0] Control for the audio input threshold. Sets the typical threshold for the audio inputs signals.
May be needed if there is noise on the audio lines.
DC_FREQ Control for the high-pass filter corner frequency.
0=80Hz
1 = 510 Hz
LP55271
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Audio Synchronization (Continued)
Audio Input Threshold Setting
Threshold[3:0] Threshold Level, mV (typical)
0000 Disabled
0001 0.2
0010 0.4
**
**
1110 2.5
1111 2.7
Typical Gain Values vs. Audio Input Amplitude
Audio Input Amplitude mV
P-P
Gain Value dB
0to10 0
0to20 -6
0to40 -12
1to85 -18
3 to 170 -24
5 to 400 -31
10 to 800 -37
20 to 1600 -46
Input Signal Gain Control
GAIN_SEL[2:0] Gain dB
000 0
001 -6
010 -12
011 -18
100 -24
101 -31
110 -37
111 -46
Refreshing Frequency
SPEED_CTRL[1:0] Refreshing Rate Hz
00 FASTEST
01 15
10 7.6
11 3.8
Logic Interface Characteristics
Limits in standard typeface are for T
J
=25
oC. Limits in boldface type apply over the operating ambient temperature range
(-30oC<T
A
<+85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: V
IN
= 3.6V, C
IN
=
10 µF, C
OUT1
= 10 µF, C
OUT2
= 10 µF, C
VDDIO
= 100 nF, C
VREF
= 100 nF, C
VDDA
= 4.7 µF, C
VDD1
= 100 nF, C
VDD2
= 100
nF, L
1
= 4.7 µH (Note 9)
Symbol Parameter Condition Min Typical Max Unit
Logic Inputs SCL and FLASH_SYNC
V
IL
Input Low Level V
DD_IO
= 1.65V to V
DD1,2
0.2xV
DD_IO
V
V
IH
Input High Level 0.8xV
DD_IO
V
I
I
Input Current -1.0 1.0 µA
f
SCL
SCL Pin Clock Frequency 400 kHz
Logic Input NRST
V
IL
Input Low Level V
DD_IO
= 1.65V to V
DD1,2
0.5 V
V
IH
Input High Level 1.2 V
I
I
Input Current -1.0 1.0 µA
t
NRST
Reset Pulse Width 10 µs
Logic Input/Output SDA
V
OL
Output Low Level I
OUT
=3mA 0.3 0.5 V
I
L
Output leakage current V
OUT
= 2.8V 1.0 µA
LP55271
www.national.com 14
I
2
C Compatible Interface
I
2
C SIGNALS
The SCL pin is used for the I
2
C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I
2
C specification. The values
of the pull-up resistors are determined by the capacitance of
the bus (typ. ~1.8 kΩ). Signal timing specifications are
shown in table I
2
C Timing Parameters.
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20202449
I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I
2
C master always
generates START and STOP bits. The I
2
C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I
2
C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20202450
I
2
C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9
th
clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP55271
address is 4C hex. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects
the register to which the data will be written. The third byte
contains data to write to the selected register.
When a READ function is to be accomplished, a WRITE
function must precede the READ function, as shown in the
I
2
C Read Cycle waveform.
20202451
I
2
C Chip Address 4C hex for LP55271
LP55271
www.national.com15
I
2
C Compatible Interface (Continued)
20202417
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 4C hex for LP55271.
I
2
C Write Cycle
20202418
I
2
C Read Cycle
20202454
I
2
C Timing Diagram
I
2
C TIMING PARAMETERS (V
DD1,2
= 3.0 to 4.5V, V
DDIO
= 1.65V to V
DD1,2
)
Symbol Parameter Limit Units
Min Max
1 Hold Time (repeated) START Condition 0.6 µs
2 Clock Low Time 1.3 µs
3 Clock High Time 600 ns
4 Setup Time for a Repeated START Condition 600 ns
5 Data Hold Time (Output direction, delay generated by LP55271) 300 900 ns
5 Data Hold Time (Input direction) 0 900 ns
6 Data Setup Time 100 ns
7 Rise Time of SDA and SCL 20+0.1C
b
300 ns
8 Fall Time of SDA and SCL 15+0.1C
b
300 ns
9 Set-up Time for STOP condition 600 ns
LP55271
www.national.com 16
I
2
C Compatible Interface (Continued)
10 Bus Free Time between a STOP and a START Condition 1.3 µs
C
b
Capacitive Load for Each Bus Line 10 200 pF
NOTE: Data guaranteed by design
Test Interface
The test bus can be controlled externally or internally. For
the external control, the LP55271 pins V
DD1,2
only need to
be powered. External control is independent on status of
NRST and V
DDIO
pins. T1 is an input and it has an internal 6
kΩpull-down resistor. T2 is an output line for the test result
with an internal 200 kΩpull-down resistor. When T1 is low,
T2 is always pulled down; when T1 is high, T2 is indicating
the result of the test.
20202419
High Level Schematic Representation of the Test Interface
The device is capable of detecting a defective unit in three
cases:
•Production test 1: The LP55271 is assembled on a
printed wiring board (PWB), but there is no LEDs con-
nected on current sink outputs. An external 4.2V test
voltage is supplied on the V
DD1
and V
DD2
pins, from
which follows that the reset operating mode is entered
with POR. Test pin T1 is pulled high. The chip will send an
acknowledge “1” onto the T2 pin if the chip is in working
order; otherwise T2 stays low (0). Refer to Test Interface
Timing Diagram.
•Production test 2: The LP55271 is assembled on a
PWB with the external components shown in LP55271
Block Diagram. 4.2V voltage is connected to V
DD1
,V
DD2
and FB pins (see the figure above), from which follows
that the reset operating mode is entered with POR. Test
pin T1 is pulled high. The chip will send an acknowledge
“1” onto the T2 pin if the chip is in working order; other-
wise T2 stays low (0). If the ACK is “1”, a repetitive test
pattern “0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and
if the LED corresponding the pattern (see Test Interface
Timing Diagram) is connected properly T2 gives “1”, oth-
erwise T2 stays low. The last “1” disengages the test.
•Field test: Build-in self-test through the I
2
C compatible
control interface. The LP55271 is enabled (NSTBY(bit) =
1, EN_BOOST(bit) = 1) and external test pins T1 and T2
are disconnected. The result can be read through the I
2
C
compatible control interface. LED test is enabled by writ-
ing to address 0Ch hex data 01h. Result can be read
from the same address during the next I
2
C cycle. Note:
I
2
C compatible interface clock signal controls the timing
of the test procedure. For that reason the clock signal
frequency should be 50 kHz or less during the build-in
self-test.
LP55271
www.national.com17
Test Interface (Continued)
20202420
Test Interface Timing Diagram
Test Interface Timing Parameters
Symbol Condition Parameter
Limit
UnitsMin Max
1V
DD1,2
= 4.2V Setup Time after V
DD1,2
= 4.2V 1 ms
2 Clock High Time 200 µs
3 Clock Low Time 200 µs
4 Test Result Settling Time 10 µs
5 Data Hold Time 0 10 ns
NOTE: Data guaranteed by design
Test Interface Characteristics
Limits in standard typeface are for T
J
=25
oC.
Symbol Parameter Condition Min Typ Max Units
Logic Input T1
V
IL
Input Low Level V
DD1,2
= 4.2V 0.5 V
V
IH
Input High Level 1.2 V
Logic Output T2
V
OL
Output Low Level V
DD1,2
= 4.2V, I
OUT
=3mA
(pull-up current)
0.3 0.5 V
V
OH
Output High Level V
DD1,2
= 4.2V, I
OUT
=-3mA
(pull-down current)
V
DD1,2
- 0,5 3.9 V
Internal Current Sink
I
SINK
Sink Current V
DD1,2
= 4.2V 500 µA
Connectivity Test Pass Range
V
PASS1
Voltage Over the Internal
Current Sink; Low Level
Production test cases
V
DD1,2
= 4.2V
V
OUT
= 3.9V to 4.2V
-50
0.10
+50
V
%
V
PASS2
Voltage Over the Internal
Current Sink; High Level -10
2.90
+10
V
%
V
PASS3
Voltage Over the Internal
Current Sink; Low Level
Field test cases
V
DD1,2
= 3.0V to 4.2V
V
OUT
= 5.0V ±5%
-30
0.40
+30
V
%
V
PASS4
Voltage Over the Internal
Current Sink; High Level -10
3.95
+10
V
%
NOTE: Data guaranteed by design
LP55271
www.national.com 18
Recommended External
Components
OUTPUT CAPACITOR, C
OUT1
,C
OUT2
The output capacitors C
OUT1
,C
OUT2
directly affect the mag-
nitude of the output ripple voltage. In general, the higher the
value of C
OUT
, the lower the output ripple magnitude. Multi-
layer ceramic capacitors with low ESR are the best choice.
At the lighter loads, the low ESR ceramics offer a much
lower V
OUT
ripple that the higher ESR tantalums of the same
value. At the higher loads, the ceramics offer a slightly lower
V
OUT
ripple magnitude than the tantalums of the same value.
However, the dv/dt of the V
OUT
ripple with the ceramics is
much lower that the tantalums under all load conditions.
Capacitor voltage rating must be sufficient, 10V is recom-
mended
Some ceramic capacitors, especially those in small
packages, exhibit a strong capacitance reduction with
the increased applied voltage. The capacitance value
can fall to below half of the nominal capacitance. Too
low output capacitance can make the boost converter
unstable.
INPUT CAPACITOR, C
IN
The input capacitor C
IN
directly affects the magnitude of the
input ripple voltage and to a lesser degree the V
OUT
ripple. A
higher value C
IN
will give a lower V
IN
ripple. Capacitor volt-
age rating must be sufficient, 10V or greater is recom-
mended.
OUTPUT DIODE, D
1
The output diode for a boost converter must be chosen
correctly depending on the output voltage and the output
current. The diode must be rated for a reverse voltage
greater than the output voltage used. The average current
rating must be greater than the maximum load current ex-
pected, and the peak current rating must be greater than the
peak inductor current (~1.7A at maximum load). A Schottky
diode should be used for the output diode. Schottky diodes
with a low forward voltage drop (V
F
) and fast switching
speeds are ideal for increasing efficiency in portable appli-
cations. Do not use ordinary rectifier diodes, since slow
switching speeds and long recovery times cause the effi-
ciency and the load regulation to suffer. In Schottky barrier
diodes reverse leakage current increases quickly with the
junction temperature. Therefore, reverse power dissipation
and the possibility of thermal runaway has to be considered
when operating under high temperature conditions. Ex-
amples of suitable diodes are Diodes Incorporated type
DFLS220L, ON Semiconductor type MBRA210LT3 and Phil-
ips type PMEG1020.
INDUCTOR, L
1
The LP55271 high switching frequency enables the use of
the small surface mount inductor. A 4.7 µH shielded inductor
is suggested for 2 MHz switching frequency. The inductor
should have a saturation current rating higher than the peak
current it will experience during circuit operation (~1.7A at
maximum load). Less than 300 mΩESR is suggested for
high efficiency. Open core inductors cause flux linkage with
circuit components and interfere with the normal operation of
the circuit. This should be avoided. For high efficiency,
choose an inductor with a high frequency core material such
as ferrite to reduce the core losses. To minimize radiated
noise, use a toroid, pot core or shielded core inductor. The
inductor should be connected to the SW1 and SW2 pins as
close to the I
C
as possible. Example of a suitable inductor is
TDK type VLCF5020T-4R7N1R7-1.
Table List of Recommended External Components
Symbol Symbol Explanation Value Unit Type
C
VDD1
V
DD1
Bypass Capacitor 100 nF Ceramic, X5R
C
VDD2
V
DD2
Bypass Capacitor 100 nF Ceramic, X5R
C
OUT1,2
Output Capacitors from FB to GND 2 x 10 µF ±10% µF Ceramic, X5R, 10V
C
IN
Input Capacitor from Battery Voltage to GND 10 ±10% µF Ceramic, X5R, 10V
C
VDDIO
V
DD_IO
Bypass Capacitor 100 nF Ceramic, X5R
C
VDDA
V
DDA
Bypass Capacitor 4.7 µF Ceramic, X5R, 6.3V
C
1,2
Audio Input Capacitors 47 nF Ceramic, X5R
R
T
Oscillator Frequency Bias Resistor 82 kΩ1%
R
F
Flash Current Set Resistor for 370 mA Sink
Current
1300 Ω1%
C
VREF
Reference Voltage Capacitor, between V
REF
and GND
100 nF Ceramic, X5R
L
1
Boost Converter Inductor 4.7 µH Shielded, low ESR,
I
SAT
~1.7A
D
1
Rectifying Diode, V
F
@maxload 0.35 V Schottky diode
Flash LED User defined
LED1 to LED4
LP55271
www.national.com19
LP55271 Control Registers and Default Values
ADDR
(HEX)
REGISTER D7 D6 D5 D4 D3 D2 D1 D0
00 LED Control Register safety_time flash_sync en_flash en_torch en_led1 en_led2 en_led3 en_led4
00000000
01 LED1 led1[7] led1[6] led1[5] led1[4] led1[3] led1[2] led1[1] led1[0]
00000000
02 LED2 led2[7] led2[6] led2[5] led2[4] led2[3] led2[2] led2[1] led2[0]
00000000
03 LED3 led3[7] led3[6] led3[5] led3[4] led3[3] led3[2] led3[1] led3[0]
00000000
04 LED4 led4[7] led4[6] led4[5] led4[4] led4[3] led4[2] led4[1] led4[0]
00000000
0B ENABLES nstby en_boost en_autoload freq_sel
00 10
0C LED Test Control led1_ok led2_ok led3_ok led4_ok flashled_ok en_test
r/o r/o r/o r/o r/o 0
0D Boost Output boost[3] boost[2] boost[1] boost[0]
0111
2A Audio Sync Control1 gain_sel[2] gain_sel[1] gain_sel[0] dc_freq en_agc en_sync speed_ctrl[1] speed_ctrl[2]
00000000
2B Audio Sync Control2 threshold[3] threshold[2] threshold[1] threshold[0]
0011
r/o = Read Only
LP55271
www.national.com 20
Physical Dimensions inches (millimeters) unless otherwise noted
The dimension for X1, X2 and X3 are as given:
•X1 = 2.466 mm ±0.03 mm
•X2 = 2.974 mm ±0.03 mm
•X3 = 0.60 mm ±0.075 mm
microSMD-30
NS Package Number TLA3011A
See National Semiconductor Application Note 1112 Micro SMD Wafer Level Chip Scale Package for PCB design and assembly
instructions.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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www.national.com
LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I
2
C Programmability, Connectivity
Test and Audio Synchronization
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