ICs for Communications
Digital Answering Machine with Full Duplex Speakerphone
SAM EC
PSB 4860 Version 2.1
Data Sheet 10.97 DS 1
Edition 10.97
This edition was real ized using the software system FrameMaker .
Published by Siemens AG,
HL TS
© Siem ens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are conc erne d, liability is only assumed for components, not for
applica tio ns , proc es s es and c irc uit s i mp lem ented within com ponents or ass em blies.
The inform at ion describe s the t yp e of co m ponent and shall not be c ons idered as assured characte ris tics .
Terms of delivery and rig ht s to ch ange design reserv ed.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Repres ent at iv es w orldw ide (see address list).
Due to technical requirem ents components may cont ain dangerous substances. For inf ormation on the t y pes in
question please con ta ct yo ur nearest Sieme ns Offic e, Sem ic onductor G roup.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the rec ycling operators k now n t o y ou. W e ca n als o help you – get in touch w it h yo ur nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical com ponents1 of the Semiconduct or Group of Siemens AG, may only be used in life -s upport devices or
systems2 with the express written approval of the Sem ic onductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system .
2 Life suppo rt dev ic es or sys te m s are int ended (a) to be implanted in the human body, or (b) to support and/or
maintain and s us t ain human life. If th ey fail, it is rea so nable to assume th at the healt h of th e us er may be en-
dangered.
PSB 4860
Revision History: Current Version: 10.97
Previous Version: Preliminary Data Sheet 09.97
Page
(in previou s
Version)
Page
(in new
Version)
Subjects (major changes since last revision)
Index added
PSB 4860
Table of Contents Page
Semiconductor Group 3 10.97
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6.1 Analog Featurephone with Digital Answering Machine . . . . . . . . . . . . . . .19
1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal . . . . . .21
1.6.3 DECT Basestation with Integrated Digital Answering Machine . . . . . . . . .22
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.1.1 Full Duplex Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.1.2 Echo Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.1.3 Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.1.4 Line Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.1.5 DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.1.6 CNG Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
2.1.7 Alert Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.1.8 CPT Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.1.9 Caller ID Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.1.10 DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.1.11 Speech Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.1.12 Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.1.13 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.1.14 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.1.15 Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.1.16 Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.1.17 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.2.1 File Definition and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.2.2 User Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.2.3 High Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . .67
2.2.4 Low Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . . .75
2.2.5 Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
2.2.6 Special Notes on File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
2.3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.3.1 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.3.2 SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.3.3 Reset and Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.3.4 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
2.3.5 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PSB 4860
Table of Contents Page
Semiconductor Group 4 10.97
2.3.6 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.7 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.8 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.9 Clock Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.3.10 Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.4.1 IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.4.2 SSDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
2.4.3 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
2.4.4 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.4.5 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
2.4.6 Auxiliary Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.2 Hardware Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.3 Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
3.3.1 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
3.3.2 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
4.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
)
IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI® , ARCOFI®-BA,
ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, IS AC®-P, ISAC®-P TE, IDEC®,
SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Siem ens AG.
DigiTape™, MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, ASM™, ASP™ are tra dem arks of Siemens AG.
PSB 4860
List of Figures Page
Semiconductor Group 5 10.97
General
Figure 1: Pin Configuration of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2: Logic Symbol of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3: Block Diagram of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4: Analog Full Duplex Speakerphone with Digital Answering Machine . . . . 20
Figure 5: Featurephone with Answering Machine for ISDN Terminal . . . . . . . . . . . 21
Figure 6: DECT Basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Units
Figure 7: Functional Units - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8: Functional Units - Recording a Phone Conversation . . . . . . . . . . . . . . . . 25
Figure 9: Functional Units - Simultaneous Internal and External Call . . . . . . . . . . . 26
Figure 10: Speakerphone - Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11: Speakerphone - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12: Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13: Echo Cancellation Unit - Typical Room Impulse Response . . . . . . . . . . . 29
Figure 14: Echo Suppression Unit - States of Operation. . . . . . . . . . . . . . . . . . . . . . 30
Figure 15: Echo Suppression Unit - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16: Speech Detector - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17: Speech Comparator - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18: Speech Comparator - Interdependence of Parameters . . . . . . . . . . . . . . 36
Figure 19: Echo Suppression Unit - Automatic Gain Control. . . . . . . . . . . . . . . . . . . 39
Figure 20: Line Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . 42
Figure 21: DTMF Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22: CNG Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23: Alert Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24: CPT Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25: CPT Detector - Cooked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26: Caller ID Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27: DTMF Generator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 28: Speech Coder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 29: Speech Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30: Analog Front End Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . 55
Figure 31: Digital Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 32: Universal Attenuator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 33: Automatic Gain Control Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . 59
Figure 34: Equalizer - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Memory Management
Figure 35: Memory Management - Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 36: Memory Management - Directory Structure . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 37: Audio File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 38: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PSB 4860
List of Figures Page
Semiconductor Group 6 10.97
Figure 39: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Miscellaneous
Figure 40: Operation Modes - State Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Interfaces
Figure 41: IOM®-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 42: IOM®-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 43: IOM®-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 44: IOM®-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 45: SSDI Interface - Transmitter Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 46: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 47: SSDI Interface - Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 48: Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . 92
Figure 49: Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 50: Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 51: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 52: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 53: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 54: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 55: Configuration Register Write Access or Register Read Command . . . . . 96
Figure 56: ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . 99
Figure 57: ARAM/DRAM Interface - Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . 100
Figure 58: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 101
Figure 59: ARAM/DRAM Interface - Refresh Cycle Timing. . . . . . . . . . . . . . . . . . . 101
Figure 60: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 61: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 62: Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 103
Figure 63: Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . 104
Figure 64: Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . 105
Figure 65: Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 66: Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 67: Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 68: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 108
Electrical Characteristics
Figure 69: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Timing Diagrams
Figure 70: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 71: SSDI/IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 232
Figure 72: SSDI/IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 232
Figure 73: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
PSB 4860
List of Figures Page
Semiconductor Group 7 10.97
Figure 74: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 75: Analog Front End Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 76: Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 77: Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 78: Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 79: Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 80: Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . 241
Figure 81: Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . 242
Figure 82: Memory Interface - Samsung Data Write. . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 83: Memory Interface - Samsung Data Read. . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 84: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 85: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
PSB 4860
List of Tables Page
Semiconductor Group 8 10.97
General
Table 1: Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Units
Table 2: Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 3: Echo Cancellation Unit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 4: Speech Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 5: Speech Comparator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 6: Attenuation Control Unit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7: SPS Output Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 8: Automatic Gain Control Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 9: Fixed Gain Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 10: Speakerphone Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 11: Line Echo Cancellation Unit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 12: DTMF Detector Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 13: DTMF Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 14: DTMF Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 15: CNG Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 16: CNG Detector Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 17: Alert Tone Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 18: Alert Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 19: CPT Detector Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 20: CPT Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 21: Caller ID Decoder Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 22: Caller ID Decoder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 23: Caller ID Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 24: DTMF Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 25: Speech Coder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 26: Speech Coder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 27: Speech Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 28: Analog Front End Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 29: Digital Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 30: Universal Attenuator Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 31: Automatic Gain Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 32: Equalizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Memory Management - General
Table 33: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 34: Memory Management Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 35: Memory Management Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Memory Management - Commands
Table 36: Initialize Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
PSB 4860
Semiconductor Group 9 10.97
Table 37: Initialize Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 38: Activate Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 39: Activate Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 40: Activate Memory Result Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 41: Open File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 42: Open Next Free File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 43: Open Next Free File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 44: Seek Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 45: Cut File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 46: Compress File Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 47: Memory Status Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 48: Memory Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 49: Garbage Collection Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 50: Access File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 51: Access File Descriptor Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 52: Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 53: Read Data Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 54: Write Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 55: Set Address Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 56: DMA Read Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 57: DMA Read Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 58: DMA Write Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 59: Block Erase Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 60: Execution Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Miscellaneous
Table 61: Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 62: SPS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 63: Power Down Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 64: Interrupt Source Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 65: Hardware Configuration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 66: Frame Synchronization Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 67: Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 68: File Command Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 69: Module Weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Interfaces
Table 70: SSDI vs. IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 71: IOM®-2 Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 72: SSDI Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 73: Control of ALS Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 74: Analog Front End Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 75: Analog Front End Interface Clock Cycles. . . . . . . . . . . . . . . . . . . . . . . . . .93
PSB 4860
Semiconductor Group 10 10.97
Table 76: Command Words for Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 77: Address Field W for Configuration Register Write . . . . . . . . . . . . . . . . . . .97
Table 78: Address Field R for Configuration Register Read . . . . . . . . . . . . . . . . . . .97
Table 79: Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 80: Address Line Usage (ARAM/DRAM Mode) . . . . . . . . . . . . . . . . . . . . . . .100
Table 81: Refresh Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 82: Address Line Usage (Samsung Mode). . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table 83: Flash Memory Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 84: Static Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 85: Multiplex Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 86: Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Electrical Characteristics
Table 87: Status Register Update Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Semiconductor Group 11 10.97
PSB 4860
Overview
1Overview
General
General
Combined with an anal og front end th e PSB 4860 provide s a s olution for embe dded o r
stand alone answering machine applications. Together with a standard microc ontroller
for analog telephones the se two chi ps form the co re of a featurep hone with fu ll duplex
speakerphone and answering machine capabilities.
The chip features recording by DigiTape™, a family of high performance algorithms.
Messages recorded with DigiTape™ can be played back with variable speed without
pitch alteration. Messages recorded with a higher bitrate can be converted into
messages with a lower bitrate arbitrarily. Current members of DigiTape (TM) span the
range from 3.3 kbit/s to 10.3 kbit/s.
Furthermore the PSB 4860, V2.1 has a full duplex speakerphone, a caller ID decoder,
DTMF recognition and generation and call progress tone detection. The frequency
response o f c heap m icrophon es or lou dspeak ers can be correct ed by a programma ble
equalizer.
Messages and u ser da ta can be stored i n AR AM/DRAM or flas h memory wh ich c an be
directly connected to the PSB 4860. The PSB 4860 also supports a voice prompt
EPROM for fixed announcements.
The PSB 4860 provides an IOM®-2 compa tible interface with two channels f or speech
data.
Alternatively to the IOM®-2 compat ible in terface the PSB 4 860 su pport s a si mple se rial
data interface (SSDI) with separate strobe sign als for each direction (linear PCM data,
one channel).
A separate interface is used for a glueless connection to the PSB 4851.
The chip is programmed by a simple four wire serial control interface and can inform the
microcontroller of new events by an interrupt signal. For data retention the PSB 4860
supports a power down mode where only the real time clock and the memory refresh (in
case of ARAM/DRAM) are operational.
The PSB 4860 supports interface pins to +5 V levels.
P-MQFP-80
Semiconductor Group 12 10.97
Digital Answering Machine with Full Duplex
Speakerphone
SAM EC
PSB 4860
Version 2.1 CMOS
Type Package
PSB 4860 P-MQFP-80
1.1 Features
Digital Functions
• High performance recording by DigiTape™
• Selectable compression rate (3.3 kbit/s, 10.3 kbit/s)
• Variable playback speed
• Support for ARAM or Flash Memory
• Optional voice prompt EPROM
• Full duplex speakerphone
• DTMF generation and detection
• Call progress tone detection
• Caller ID recognition
• Direct memory access
• Re al time clock
• Equalizer
• Automatic gain control
• Automa tic timestamp
• Auxil iary paral lel port
• Ultra low power refresh mode
General Features
• SSDI/IOM®-2 compatible interface
• Serial control interface for programming
PSB 4860
Overview
Semiconductor Group 13 10.97
1.2 Pin Configuration
(top view)
Figure 1 Pin Configuration of PSB 4860
110 20
21
30
40
4160 50
61
70
80
VDDA
XTAL1
XTAL2
OSC1
OSC2
VSSA
SCLK
SDR
VDD
AFEDD
AFEDU
VDD
VSS
VDD
VSS
AFEFS
AFECLK
FSC
DU/DX
DD/DR
DXST
DRST
VDD
VSS
DCL
W/FWE
FRDY
VPRD/FCLE
RAS/FOE
CAS1/FCS
SPS0
SPS1
VDD
VSS
MD1
MD2
MA3
MA2
MA1
MA0
MD7
MD6
MD5
MD4
MD3
VDD
VSS
VDD
VSS
VSS
VSS
RO
VDD
MA4
MA5
MA6
VDD
MA8
VSS
MA15
VSS
MA7
MA9
MA10
VDD
MA12
MA13
MA14
VSS
MA11
VDDP
RST
CLK
VSS
MD0
VDDP
INT
SDX
CS
CAS0/ALE
SAM EC
PSB 4860
PSB 4860
Overview
Semiconductor Group 14 10.97
1.3 Pin Definitions and Functions
Table 1 Pin Definitions and Functions
Pin No.
P-MQFP-80 Symbol Dir. Reset Function
41, 80
V
DDP -- Power supply (5V %)
Power supply for the interface.
7, 15, 21,
29, 39, 49,
58, 61, 67,
73
V
DD -- Power supply (3.0 V - 3.6 V)
Power supply for logic.
1
V
DDA -- Power supply (3.0 V - 3.6 V)
Power supply for clock generator.
4
V
SSA -- Power supply (0 V)
Ground for clock generator.
9, 16, 22,
30, 40, 48,
57, 59, 60,
78, 66, 72
V
SS -- Power supply (0 V)
Ground for logic and interface.
17 AFEFS O L Analog Frontend Frame Sync:
8 kHz frame synchronization signal for the
analog front end.
18 AFECLK O L Analog Frontend Clock:
Clock signal for the analog front end.
19 AFEDD O L Analog Frontend Data Downstream:
Data output to the analog frontend.
20 AFEDU I - Analog Frontend Data Upstream:
Data input from the analog frontend.
79 RST I - Reset:
Active high reset signal.
23 FSC I - Data Frame Synchronization:
8 kHz frame synchronization signal (IOM®-2 and
SSDI mode).
24 DCL I - Data Clock:
Data Clock of the serial data interface.
10±
PSB 4860
Overview
Semiconductor Group 15 10.97
26 DD/DR I/OD
I
-IOM®-2 Compatible Mode:
Receive data from IOM®-2 controlling device.
SSDI Mode:
Receive data of the strobed serial data interface.
25 DU/DX I/OD
O/
OD
-IOM®-2 Compatible Mode:
Transmit data to IOM®-2 controlling device.
SSDI Mode:
Transmit data of the strobed serial data
interface.
27 DXST O L DX Strobe:
Strobe for DX in SSDI interface mode.
28 DRST I - DR Strobe:
Strobe for DR in SSDI interface mode.
14 CS I- Chip Select:
Select signal of the serial control interface (SCI).
11 SCLK I - Serial Clock:
Clock signal of the serial control interface (SCI).
13 SDR I - Serial Data Receive:
Data input of the serial control interface (SCI).
12 SDX O/
OD HSerial Data Transmit:
Data Output of the serial control interface (SCI).
10 INT O/
OD HInterrupt
New status available.
Table 1 Pin Definitions and Functions
PSB 4860
Overview
Semiconductor Group 16 10.97
52
53
54
55
62
63
64
65
68
69
70
71
74
75
76
77
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L1)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Memory Address 0-15:
Multiplexed address outputs for ARAM, DRAM
access.
Non-multiplexed address outputs for voice
prompt EPROM.
Auxiliary Parallel Port:
General purpo se I/O .
42
43
44
45
46
47
50
51
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
Memo ry Data 0- 7:
Memory (ARAM, DRAM, Flash Memory,
EPROM) data bus.
35
36
CAS0/
ALE
CAS1/
FCS
O
O
H2) ARAM, DRAM:
Column address strobe for memory bank 0 or 1.
Flash Memory :
Address Latch Enable for address lines A16-A23.
Chip select signal for Flash Memory
34 RAS/
FOE OH
2)ARAM, DRAM:
Row address strobe for both memory banks.
Flash Memory :
Output enable signal for Flash Memory.
33 VPRD/
FCLE OH
2)ARAM, DRAM:
Read signal for voice prompt EPROM.
Flash Memory :
Command latch enable for Flash Memory.
Table 1 Pin Definitions and Functions
PSB 4860
Overview
Semiconductor Group 17 10.97
1) These lines are driv en low with 125 µA un til the m ode (address lines or auxiliary port) is def ined.
2) These lines are driv en high with 70 µA during reset.
32 W/FWE OH
2)ARAM, D RAM:
Write signal for all memory banks.
Flash Memory:
Write signal for Flash Memory.
31 FRDY I - Flash Memory Ready
Input for Ready/Busy signal of Flash Memory
5
6OSC1
OSC2
I
O-
ZAuxiliary Oscillator:
Oscillator loop for 32.768 kHz crystal.
8CLKI-Alternative AFECLK Source
13,824 MHz
2
3XTAL1
XTAL2
I
O-
ZOscillator:
XTAL1: External clock or input of oscillator loop.
XTAL2: output of oscillator loop for crystal.
37
38 SPS0
SPS1
O
OL
LMultipurpose Outputs:
General purpose, speakerphone, address lines
or status
56 RO O - Reserved Output
Must be left open.
Table 1 Pin Definitions and Functions
PSB 4860
Overview
Semiconductor Group 18 10.97
1.4 Logic Symbol
1
Figure 2 Logic Symbol of PSB 4860
DU/DX
DD/DR
DCL
FSC
SDX
SDR
SCLK
CS
IOM®-2
SCI
AFECLK
AFEFS
AFEDU
AFEDD
PSB
MA0-MA15 MD0-MD7CAS0/
ALE CAS1/
FCS FOE
RAS/ VPRD/
FCLE
W/
FWE
Memory
V
DDA
V
DD
V
SS
OSC2
OSC1XTAL1XTAL2
RST
SSDI4851
INT
FRDY
DXST
DRST
CLK
PSB 4860
PSB 4860
Overview
Semiconductor Group 19 10.97
1.5 Functional Block Diagram
Figure 3 Block Diagram of PSB 4860
1.6 System Integration
The PSB 4860 com bin ed with an a nalo g fron t end (PSB 4851 ) can be us ed i n a v ariet y
of applications. This combination offers outstanding features like full duplex
speakerphone and emergency operation. Some applications are given in the following
sections.
1.6.1 Analog Featurephone with Digital Answering Machine
Figure 4 shows an example of an analog telephone system. The telephone can operate
during power failure by line powering. In this case only the handset and ringer circuit are
active. All other parts of the chipset are shut down leaving enough power for the external
microcontroller to perform basic tasks like keyboard monitoring.
DU/DX
DD/DR
DCL
FSC
SDX
SDR
SCLK
CS
AFECLK
AFEFS
AFEDU
AFEDD
MA0-MA15 MD0-MD7CAS0/
ALE CAS1/
FCS FOE
RAS/VPRD/
FCLE
W/
FWE
OSC2
OSC1XTAL1XTAL2
RST
DSP
Memory Inte r face
Reset and Timing Unit
Data
Interface
Control
Interface
Analog
Front End
Interface INT
FRDY
DXST
DRST
PSB 4860
Overview
Semiconductor Group 20 10.97
For answering machine operation the voice data is stored in ARAM or Flash Memory
devices. In addition, voice prompts can be played back from an optional voice prompt
EPROM. If flash memory is used the functionality of the voice prompt EPROM can be
realized by the flash memory devices. The microcontroller can use the memory attached
to the PSB 4860/PSB 4851 to store and retrieve binary data.
Figure 4 Analog Full Duplex Speakerphone with Digital Answering Machine
Voice Pr om p t
ARAM
Flash Memory
EPROM
Microcontroller
077-3445
line
tip/
ring
PSB 4860
PSB 4851
PSB 4860
Overview
Semiconductor Group 21 10.97
1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal
Figure 5 shows an ISDN featurephone that takes full advantage of two simultaneous
connecti ons. In this a pplication o ne channel o f the PSB 4851 interfa ces to the ha ndset
and speakerphone while the other provides an interface for an external analog device
(e.g. FAX machine).
Figure 5 Featurephone with Answering Machine for ISDN Terminal
In additio n, the two ch ann els of the PSB 485 1 ca n be use d for h oldi ng two c on nec tion s
simultaneously. One connection can be switched to the handset and the other to the
speakerphone box. Local three party conferences are also possible.
Flash Memory
PSB 4860
PSB 4851
Microcontroller
077-3445
IOM®-2
SCI
PSB 2186
ISAC®-S TE S0-BUS
Power Controlle r
PSB 2120/1
SLIC
POTS
PSB 4860
Overview
Semiconductor Group 22 10.97
1.6.3 DECT Basestation with Integrated Digital Answering Machine
Figure 6 shows a DECT basestation based on the PSB 4860/PSB 485 1 chipse t. In this
application it is possible to service both an external call and an internal call at the same
time. For programming the serial control interface (SCI) is used while voice data is
transferred via the strobed serial data interface (SSDI/IOM®-2).
Figure 6 DECT Basestation
Flash Memory
Microcontroller
077-3445
Antenna
SSDI/IOM®-2
SCI
Burstmode
Controller
DECT
HF
line
tip/
ring
PSB 4860
PSB 4851
PSB 4860
Functional Description
Semiconductor Group 23 10.97
2 Functional Description
Functional Units
Functional Units
The PSB 4860 contains several functional units that can be combined with almost no
restrictions to perform a given task. Figure 7 gives an overview of the important
functional units.
Figure 7 Functional Units - Overview
DTMF
Generator
DTMF
Detector
Speech
Coder
Speaker-
phone
CID
Decoder
Speech
Decoder
CPT
Detector
line
line
micro-
loud-
SSDI/IOM®-2 IOM®-2
S
1
S
3
S
5
S
7
S
11
S
12
S
10
S
9
S
13
S
4
S
2
S
8
S
6
signal summati on: signal sources:
S1,...,S18
in
out
speaker
phone
I1
I2
I3
line side
acoustic side
Memory
SCI
I1I1
I1
I2
I3
I1
I2
I3
Cha nnel 2Channel 1
I3I4
I1I2
I1I2I3I1I2I3
I1I2
I1
Alert Tone
Detector
CNG
Detector
I1I1
Universal
Attenuator
I1
S
14
Line Echo
Canceller
I1I2
S
15
AGC
I1I2
S
17
Equalizer
I1
S
18
S
16
PSB 4860
Functional Description
Semiconductor Group 24 10.97
Each unit has one or more signal inputs (denoted by I). Most units have at least one
signal output (denoted by S). Any input I can be connected to any signal output S. In
addition to the signals shown in figure 7 there is also the signal S0 (silence), which is
useful at signal summation points. Table 2 lists the available signals within the PSB 4860
according to their reference points.
Table 2 Signal Summary
Signal Description
S0Silence
S1Analog line input (channel 1 of PSB 4851 interface)
S2Analog line outp ut (channel 1 of PSB 4851 interface)
S3Microphone input (channel 2 of PSB 4851 interface)
S4Loudspeaker/Handset output (channel 2 of PSB 4851 interface)
S5Serial interface input, channel 1
S6Serial interface output, channel 1
S7Serial interface input, channel 2
S8Serial interface output, channel 2
S9DTMF generator output
S10 DTMF generator auxiliary output
S11 Speakerphone output (acoustic side)
S12 Speakerphone output (line side)
S13 Speech decoder output
S14 Universal attenuator output
S15 Line echo canceller output
S16 Automatic gain control output (after gain stage)
S17 Automatic gain control output (before gain stage)
S18 Equalizer output
PSB 4860
Functional Description
Semiconductor Group 25 10.97
The following figures show the connections for two typical states during operation. Units
that are not needed are not shown. Inputs that are not needed are connected to S0 which
provides silence (denoted by 0). In figure 8 a hands-free phone conversation is currently
in progress. The speech coder is used to record the signals of both parties. The alert tone
detector is used to det ect an ale rting ton e o f an off-hook c all er id req ues t w hil e t he C ID
decoder decodes the actual data transmitted in this case.
Figure 8 Functional Units - Recording a Phone Conversation
Alert Tone
Detector
Speech
coder
Speaker-
phone
CID
decoder
Line Echo
Canceller
line
line
micro-
loud-
in
out
speaker
phone
line side
acoustic side
Memory
SCI
0
0
0
0
0
0
AGC
PSB 4860
Functional Description
Semiconductor Group 26 10.97
In figure 9 a phone conversation using the speakerphone is in progress. One party is
using the base station of a DECT system while the other party is using a mobile handset.
At the same time an external call is serviced by the answering machine. In the current
state a message (recorded or outgoing) is being played back. In this case the DTMF
detector is used to detect sign als for remote access while the CPT detector is used to
determine the end of the external call.
Figure 9 Functional Units - Simultaneous Internal and External Call
Speaker-
phone
Speech
decoder
line
line
micro-
loud-
SSDI/IOM®-2
in
out
speaker
phone
line side
acoustic side
Memory
SCI
0
0
0
Channel 1
0
0
00
0
DTMF
Detector
CPT
decoder
Line Echo
Canceller
Equalizer
PSB 4860
Functional Description
Semiconductor Group 27 10.97
2.1 Functional Units
In this section the functional units of the PSB 4860 are described in detail. The functional
units can be individually enabled or disabled.
2.1.1 Full Duplex Speakerphone
The speakerphone unit (figure 10) is attached to four signals (microphone, loudspeaker,
line out and line in). The two input signals (microphone, line in) are preceded by a signal
summation point.
Figure 10 Speakerphone - Signal Connections
Internally, this unit can be divided into an echo cancellation unit and an echo suppression
unit (figure 11). The echo cancellation unit provides the attenuation Gc while the echo
suppression unit provides the attenuation Gs. The total attenuation ATT of the
speakerphone is therefore ATT=GC+Gs.
Figure 11 Speakerphone - Block Diagram
The echo suppression unit can be enabled without the echo cancellation unit. If the echo
cancellation unit is disabled, the echo suppression unit still provides speakerphone
functionality, albeit only half duplex. As the echo cancellation must be disabled during
recording or playback of speech data, this option allows for speakerphone operation
Speakerphone
S
11
S
12
a
c
o
u
s
t
i
c
s
i
d
e
l
i
n
e
s
i
d
e
I
2
I
1
I
3
I
4
microphone
loudspeaker
line out
line in
Echo
Cancellation
line outmicrophone
loudspeaker line in
Echo
Suppression
GcGS
PSB 4860
Functional Description
Semiconductor Group 28 10.97
even if recording or playback is going on. The echo suppression unit is also used to
provide additional attenuation if the echo cancellation unit cannot provide all of the
required attenuation itself.
2.1.2 Echo Cancellation
A simplified block diagram of the echo cancellation unit is shown in figure 12.
Figure 12 Echo Cancellation Unit - Block Diagram
The echo cancellation unit consists of an finite impulse response filter (FIR) that models
the expected acoustic echo, an NLMS based adaption unit and a control unit. The
expected echo is subtracted from the actual input signal from the microphone. If the
model is exact a nd the e cho does not exc eed the length of the filt er then th e echo c an
be completely cancelled. However, even if this ideal state can be achieved for one given
moment the acoustic echo usually changes over time. Therefore the NLMS unit
continuously adapts the coefficients of the FIR filter. This adaption process is steered by
the control unit. As an example, the adaption is inhibited as long as double talk is
detected by the co ntrol un it. Furtherm ore t he cont rol unit informs the ech o supp ress ion
unit about the achieved echo return loss.
Table 3 shows the registers associated with the echo cancellation unit.
Table 3 Echo Cancellation Unit Registers
Register # of Bits Name Comment
SAELEN 9 LEN Length of FIR filter
SAEATT 15 ATT Attenuation reduction during double-talk
SAEGS 3 GS Global scale (all blocks)
microphone
loudspeaker
-
FIR
Filter
NLMSControl
line out
line in
PSB 4860
Functional Description
Semiconductor Group 29 10.97
The length of the FIR filter can be varied from 127 to 511 taps (15.875ms to 63.875ms).
The taps are grouped into blocks. Each block contains 64 taps.
The performance of the FIR filter can be enhanced by prescaling some or call of the
coefficients of the FIR filter. A coefficient is prescaled by multiplying it by a constant. The
advantage of prescaling is an enhanced precision and consequently an enhanced echo
cancellation. The disadvantage is a reduced echo cancellation performance if the signal
exceeds the maximal coefficient value. More precisely, if a coefficient at tap Ti is scaled
by a factor Ci then the level of the echo (room impulse response) must not exceed Max/
Ci (Max: Maximum PCM value). As an example figure shows a typical room impulse
response.
Figure 13 Echo Cancellation Unit - Typical Room Impulse Response
First of all, the echo never exceeds 0.5 of the maximum value. Furthermore the echo
never exceeds 0.25 of the maximum value after time t0.25. Therefore all coefficients can
be scaled by a factor of 2 and al l coefficien ts for taps corres ponding to times af ter t0.25
can be scaled a factor of 4.
The echo cancellation unit provides three parameters for scaling coefficients. The first
parameter (GS) determines a scale for all coefficients. The second parameter (FB)
determines the first block for which an additional scale (PS) takes effect.
This feature can be used for different default settings like large or small rooms.
SAEPS1 3 AS Partial scale (for blocks >= SAEPS2:FB)
SAEPS2 3 FB First block affected by partial scale
Table 3 Echo Cancellation Unit Registers
t
A
0.5
0.25
t0.25
PSB 4860
Functional Description
Semiconductor Group 30 10.97
2.1.3 Echo Suppression
The echo suppression unit can be in one of three states:
• tran smit state
• receive state
• idle stat e
In transmit state the microphone signal drives the line output while the line input is
attenuated. In receive state the louds peaker signal is driven by the line input while the
microphone signal is attenuated. In idle state both signal paths are active with evenly
distributed attenuation.
Figure 14 Echo Suppression Uni t - States of Operation
line out
line in
microphone
loudspeaker
idle state
line out
line in
microphone
loudspeaker
receive state
line out
line in
microphone
loudspeaker
transmit state
PSB 4860
Functional Description
Semiconductor Group 31 10.97
Figure15 shows the signal flow graph of the echo suppression unit in more detail.
Figure 15 Echo Suppression Unit - Signal Flow Graph
State switching is controlled by the speech comparators (SCAS, SCLS) and the speech
detectors (SDX, SDR). The amplifiers (AGCX, AGCR, LGAX, LGAR) are used to
achieve proper signal levels for each state. All blocks are programmable. Thus the
telephone set can be optimized and adjusted to the particular geometrical and acoustical
enviro nme nt. The following s ecti ons dis cus s each block of the echo sup pression uni t in
detail.
SCLSSCAS
SDX
SDR
AGCR
AGCX
Attenuation
Control
line outmicrophone
loudspeaker
LGAX
LGAR line in
GHX
GHR
PSB 4860
Functional Description
Semiconductor Group 32 10.97
2.1.3.1 Speech Detector
For each signal source a speech detector (SDX, SDR) is available. The speech
detectors are identi cal but ca n be programm ed indiv idually . Figure 16 s hows th e sig nal
flow graph of a speech detector.
Figure 16 Speech Detector - Signal Flow Graph
The first three units (LIM, LP1, PD) are used for preprocessing the signal while the actual
speech detection is performed by the background noise monitor.
Background Noise Monitor
The tasks of the noise monitor are to differentiate voice signals from background noise,
even if it exceeds the voice level, and to recognize voice signals without any delay.
Therefore the Background Noise Monitor consists of the Low-Pass Filter 2 (LP2) and the
offset in two separate branches. Basically it works on the burst-characteristic of the
speech: voice signals consist of short peaks with high power (bursts). In contrast,
background noise can be regarded approximately stationary from its average power.
Low-Pass Filter 2 provides different time constants for noise (non-detected speech) and
speech. It determines the average of the noise reference level. In case of background
noise the level at the output of LP2 is approximately the level of the input. As in the other
branch an additional offset OFF is added to the signal, the comparator signals noise. At
speech bursts the digital signals arriving at the comparator via the offset branch change
faster than those via the LP2-branch. If the difference exceeds the offset OFF, the
LIM LP1 PD
LP2
OFF
LP1 PDS
PDN
LP2S
LP2N
LP2L
Background Noise Monitor
Signal Preprocessing
-
LIM
PSB 4860
Functional Description
Semiconductor Group 33 10.97
comparator si gnals speech. Therefore th e output of the background noise monitor is a
digital signal indicating speech (1) or noise (0).
A small fade constant (LP2N) enables fast settling of LP2 to the average noise level after
the end of speech re cognition. How eve r, a to o s mal l time c ons tant for LP2N can cause
rapid charging to such a high level that after recognizing speech the danger of an
unwanted switching back to noise exists. It is recommended to choose a large rising
constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is not
recommend ed to choos e an infinite L P2S because t hen appro aching the noi se level is
disab led . Du ring conti nuou s sp eech or tones the LP2 will be charge d unt il the limitatio n
LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This
limitation permits transmission of continuous tones and “music on hold”.
The offset stage represents the estimated difference between the speech signal and
averaged noise.
Signal Preprocessing
As described in the preceding chapter, the background noise monitor is able to
disc ri min ate b etw een speech and noi se. I n very sho rt spee ch p aus es e.g . between two
words, however, it changes immediately to non-speech, which is equal to noise.
Therefore a peak detection is required in front of the Noise Monitor.
The main task of the Peak Detector (PD) is to bridge the very short speech pauses during
a monolog so that this time constant has to be long. Furthermore, the speech bursts are
stored so that a sure speech detection is guaranteed. But if no speech is recognized the
noise low-pass LP2 mu st be charged faster to the averag e noise lev el. In addition, th e
noise edges are to be smoothed. Therefore two time constants are necessary. As the
peak detector is very sensitive to spikes, the low-pass LP1 filters the incoming signal
containing noise in a way that main spikes are eliminated. Due to the programmable time
constant it is possible to refuse high-energy sibilants and noise edges.
To compress the speech signals in their amplitudes and to ease the detection of speech,
the si gnals have t o be compand ed logari thmical ly. Here by, the spee ch detect or should
not be i nfluenced by the s ystem noise w hich is always present but shoul d discriminate
between speech and background noise. The limitation of the logarithmic amplifier can be
programmed via the parameter LIM. LIM is related to the maximum PCM level. A signal
exceeding the limitation defined by LIM is getting amplified logarithmically, while very
smooth s yst em noi se bel ow is ne glecte d. It sh oul d be th e leve l o f the m ini mum sy stem
noise which is always existing; in the transmit path the noise generated by the telephone
circuitry itself and in receive direction the level of the first bit which is stable without any
speech signal at the receive path. Table 6 shows the parameters for the speech detector.
PSB 4860
Functional Description
Semiconductor Group 34 10.97
The input signal of the speech detector can be connected to either the input signal of the
echo suppression unit (as shown for SDX) or the output of the associated AGC (as
shown for SDR).
Table 4 Speech Detector Parameters
Parameter # of bytes Range Comment
LIM 1 0 to 95 dB Limitation of log. amplifier
OFF 1 0 to 95 dB Level offset up to detected noise
PDS 1 1 to 2000 ms Peak decrement PD1 (speech)
PDN 1 1 to 2000 ms Peak decrement PD1 (noise)
LP1 1 1 to 2000 ms Time constant LP1
LP2S 1 2 to 250 s Time constant LP2 (speech)
LP2N 1 1 to 2000 ms Time constant LP2 (noise)
LP2L 1 0 to 95 dB Maximum value of LP2
PSB 4860
Functional Description
Semiconductor Group 35 10.97
2.1.3.2 Speech Comparators (SC)
The echo su ppres si on un it has tw o ide ntical s pee ch c omp arato rs (SCAS, SC LS). Eac h
comparator can be programmed individually to accommodate the different system
characteris tics of the acoustic inte rface and the line interface . As SCAS and SCLS are
identical, the following description holds for both SCAS and SCLS.
The SC has two input signals SX and SR, which map to microphone/loudspeaker for
SCAS and line in/line out for SCLS.
In principle, the SC works according to the following equation:
Therefore, SCAS controls the switching to transmit state and SCLS controls the
switching to receive state. Switching is done only if SX exceeds SR by at least the
expected acoustic level enhancement V which is divided into two parts: G and GD. A
block diagram of the SC is shown in figure 17.
Figure 17 Speech Comparator - Block Diagram
At both inputs, logarithmic amplifiers compress the signal range. Hence after the
required signal processing for controlling the acoustic echo, pure logarithmic levels on
both paths are compared.
The main task of the comparator is to control the echo. The internal coupling due to the
direct sound and mechanical resonances are covered by G. The external coupling,
mainly caused by the acoustic feedback, is controlled by GD/PD.
if SX > SR + V then switch state
GGDS
GDN PDS
PDN
SX
SR
Log. Amp. Base Gain Gain Reserve Peak Decrement
Log. Amp.
PDS
PDN
Peak Decrement
PSB 4860
Functional Description
Semiconductor Group 36 10.97
The base g ain (G) corre sponds to the termin al couplin gs of the compl ete telepho ne: G
is the measured or calculated level enhancement between both receive and transmit
inputs of the SC.
To control the acoustic feedback two parameters are necessary: GD represents the
actual reserve on the measured G. Together with the Peak Decrement (PD) it simulates
the echo behavior at the acoustic side: After speech has ended there is a short time
during which hard couplings through the mechanics and resonances and the direct echo
are present. Till the end of that time (∆t) the level enhancement V must be at least equal
to G to prevent clipping caused by these internal couplings. Then, only the acoustic
feedback is present. This coupling, however, is reduced by air attenuation. For this in
general the longer the delay, the smaller the echo being valid. This echo behavior is
featured by the decrement PD.
Figure 18 Speech Comparator - Interdependence of Parameters
According to figure 18, a compromise between the reserv e GD and th e decrement PD
has to be made: a smaller reserve (GD) above the level enhancement G requires a
longer time to decrease (PD). It is easy to overshout the other side but the
intercommunication is harder because after the end of the speech, the level of the
estimated echo has to be exceeded. In contrary, with a higher reserve (GD*) it is harder
to overshout continuous speech or tones, but it enables a faster intercommunication
because of a stronger decrement (PD*).
t
dB
∆t
GD*
GD PD*
PD
RX-Speech
RX-noise
G
G
PSB 4860
Functional Description
Semiconductor Group 37 10.97
Two pairs of coefficients, GDS/PDS when speech is detected, and GDN/PDN in case of
noise, offer a different echo handling for speech and non-speech.
With speech, even if very strong resonances are present, the performance will not be
worsened by the high GDS needed. Only when speech is detected, a high reserve
prevents clipping. A time period ET [ms] after speech end, the parameters of the
comparator are switched to the “noise” values. If both sets of the parameters are equal,
ET has no function.
2.1.3.3 Attenuation Control
The attenuation control unit controls the attenuation stages GHX and GHR and performs
state switching. The programmable attenuation ATT is completely switched to GHX
(GHR) in receive state (transmit state). In idle state both GHX and GHR attenuate by
ATT/2.
In a ddition, a ttenuati on is a lso influ enced by the auto matic gain co ntrol st ages (AGCX ,
AGCR).
State switching depends on the signals of one speech comparator and the
corresponding speech detector. While each state is associated with the programmed
attenuation, the time is takes to reach the steady-state attenuat ion after a state switch
can be programmed (TSW).
If the current state is eit her transmit or receive and n o speech on e ither side has been
detected for time TW then idle state is entered. To smoothen the transition, the
attenuation is incremented (decremented) by DS until the evenly di stribution ATT/2 for
both GHX and GHR is reached.
Table 6 shows the parameters for the attenuation unit. Note that TSW is dependent on
the current attenuation by the formula .
Table 5 Speech Comparator Parameters
Parameter # of bytes Range Comment
G 1 – 48 to + 48 dB Base Gain
GDS 1 0 to 48 dB Gain Reserve (Speech)
PDS 1 0.025 to 6 dB/ms Peak Decrement (Speech)
GDN 1 0 to 48 dB Gain Reserve (Noise)
PDN 1 0.025 to 6 dB/ms Peak Decrement (Noise)
ET 1 0 to 992 ms Time to Switch from speech to noise
parameters
Tsw SW ATT×=
PSB 4860
Functional Description
Semiconductor Group 38 10.97
Note: In addition, attenuation is also influenced by the Automatic Gain Control stages
(AGCX, AGCR) in order to keep the total loop attenuation constant.
2.1.3.4 Echo Suppression Status Output
The PSB 4860 can report the current state of the echo suppression unit to ease
optimization of the parameter set of the echo suppression unit. In this case the SPS0 and
SPS1 pins are set according to table 7.
Furthermore the controller can read the current value of the SPS pins by reading register
SPSCTL.
2.1.3.5 Loudhearing
The speakerphone unit can also be used for controlled loudhearing. If enabled in
loudhearing mode, the loudspeaker amplif ier of the PSB 4851 (ALS) is used instead of
GHR (figure 15) when appropriate to avoid oscillation. In order to enable this feature, the
PSB 4851 must be programmed to allow ALS override. The ALS field within the AFE
control register AFECTL defines the value sent to the PSB 4851 if attenuation is
necessary (see specification of the PSB 4851).
2.1.3.6 Automatic Gai n Control
The echo suppression unit has two identical automatic gain control units (AGCX,
AGCR).
Table 6 Attenuation Control Unit Parameters
Parameter # of bytes Range Comment
TW 1 16 ms to 4 s TW to return to idle state
ATT 1 0 to 95 dB Attenuation for GHX and GHR
DS 1 0.6 to 680 ms/dB Decay Speed (to idle state)
SW 1 0.0052 to 10 ms/dB Decay Rate (used for TSW)
Table 7 SPS Output Encoding
SPS0SPS1Echo Suppression Unit State
0 0 no echo suppression operation
0 1 receive
10transmit
1 1 idle
PSB 4860
Functional Description
Semiconductor Group 39 10.97
Operation of the AGC depends on a threshold level defined by the parameter COM
(value relative to the maximum PCM-value). The regulation speed is controlled by
SPEEDH for signal amplitudes above the threshold and SPEEDL for amplitudes below.
Usually SPEEDH will be chosen to be at least 10 times faster than SPEEDL. The bold
line in Figure 19 depicts the steady-state output level of the AGC as a function of the
input level.
Figure 19 Echo Suppression Unit - Automatic Gain Control
For reasons of physiological acceptance the AGC gain is automatically reduced in case
of con tinuous backg round noi se (e.g. by ventil ators). The reduc tion is programme d via
the NOlS parameter. When the noise level exceeds the threshold determined by NOIS,
the amplification will be reduced by the same amount the noise level is above the
threshold. The current gain/attenuation of the AGC can be read at any time (AG_CUR).
An additional low pass with time constant LP is provided to avoid an immediate response
of the AGC to very short signal bursts.
If SDX detects noise, AGCX is not working. In this case the last gain setting is used.
Regulation starts with this value as soon as SDX detects speech.
Likewise, if SDR detects noise, AGCR is not working. In this case the last gain setting is
used. Regulation starts with this value as soon as SDR detects speech. When the AGC
has been disabled the initial gain used immediately after enabling the AGC can be
programmed. Table 8 shows the pa rameters of the AGC.
COM
AG_ATT
AG_GAIN
AGC input leve l
AGC
output
level
max. PCM
-10 dB
-20 dB
-10 dB-20 dB
Example:
COM
AG_GAIN
AG_ATT
=
=
=
-30 dB
15 dB
20 dB
PSB 4860
Functional Description
Semiconductor Group 40 10.97
Note: There are two sets of parameters, one for AGCX and one for AGCR.
Note: By setting AG_GAIN to 0 dB a limitation function can be realized with the AGC.
2.1.3.7 Fixed Gain
Each signal path features an additional amplifier (LGAX, LGAR) that can be set to a fixed
gain. These amplifiers should be used for the basic amplification in order to avoid
saturation in the preceding stages. Table 9 shows the only parameter of this stage.
2.1.3.8 Mode Control
Table 10 shows the registers used to determine the signal sources and the mode.
Table 8 Automatic Gain Control Parameters
Parameter # of Bytes Range Comment
AG_INIT 1 -95 dB to 95dB Initial AGC gain/attenuation
COM 1 0 to – 95 dB Compare level rel. to max. PCM-value
AG_ATT 1 0 to -95 dB Attenuation range
AG_GAIN 1 0 to 95 dB Gain range
AG_CUR 1 -95 dB to 95 dB Current gain/attenuation
SPEEDL 1 0.25 to 62.5 dB/s Change rate for lower levels
SPEEDH 1 0.25 to 62.5 dB/s Change rate for higher levels
NOIS 1 0 to – 95 dB Threshold for AGC-reduction
by background noise
LP 1 0.025 to 16 ms AGC low pass time constant
Table 9 Fixed Gain Parameters
Parameter # of Bytes Range Comment
LGA 1 -12 dB to 12 dB always active
Table 10 Speakerphone Control Registers
Register # of Bits Name Comment
SCTL 1 ENS Echo suppression unit enable
SCTL 1 ENC Echo cancellat ion unit enable
SCTL 1 MD Speakerphone or loudhearing mode
SCTL 1 AGX AGCX enable
PSB 4860
Functional Description
Semiconductor Group 41 10.97
SCTL 1 AGR AGCR enable
SCTL 1 SDX SDX input tap
SCTL 1 SDR SDR input tap
AFECTL 4 ALS ALS value for loudhearing
SSRC1 5 I1 Input signal 1 (microphone)
SSRC1 5 I2 Input signal 2 (microphone)
SSRC2 5 I3 Input signal 3 (line in)
SSRC2 5 I4 Input signal 4 (line in)
Table 10 Speakerphone Control Registers
PSB 4860
Functional Description
Semiconductor Group 42 10.97
2.1.4 Line Echo Canceller
The PSB 4860 contains an adaptive line echo cancellation unit for the cancellation of
near en d echoes. The unit has tw o modes: normal and exte nded. In normal mod e, the
maximum echo length is 4 ms. This mode is always available. In extended mode, the
maximum echo length is 24 ms. Extended mode cannot be used while the speech
encoder, the echo cancellation unit or slow playback is active.
The line echo cancellation unit is especially useful in front of the various detectors
(DTMF, CPT, etc.). A block diagram is shown in figure 20.
Figure 20 Line Echo Cancellation Unit - Block Diagram
The line echo canceller provides only one outgoing signal (S15) as the other outgoing
signal would be identical with the input signal I1.
Input I2 is usually connec ted to the l ine input while inp ut I1 is connected to the outgoing
signal.
In normal mode the adaption process can be controlled by three parameters: MIN, ATT
and MGN. Adaption takes only place if both of the following conditions hold:
1.
2.
With the firs t con diti on ada ption to sma ll signal s can be avoid ed. The s econd condit ion
avoids adaption during double talk. The parameter ATT represents the echo loss
provided by external circuitry. The adaption stops if the power of the received signal (I2)
exceeds the power of the expected signal (I1-ATT) by more than the margin MGN.
+
-Σ
Adaptive
Filter
I2S15
I1
I1 MIN>
I1 I2–ATTMGN+–0>
PSB 4860
Functional Description
Semiconductor Group 43 10.97
Table 11 shows the registers associated with the line echo canceller.
Table 11 Line Echo Cancellation Unit Registers
Register # of Bits Name Comment Relevant
Mode
LECCTL 1 EN Line echo canceller enable both
LECCTL 1 MD Line echo canceller mode
LECCTL 5 I2 Input signal selection for I2both
LECCTL 5 I1 Input signal selection for I1both
LECLEV 15 MIN Minimal power for signal I1 normal
LECATT 15 ATT Externally provided attenuation (I1 to I2) normal
LECMGN 15 MGN Margin for double talk detection normal
PSB 4860
Functional Description
Semiconductor Group 44 10.97
2.1.5 DTMF Detector
Figure 21 shows a block diagram of the DTMF detector. Th e re sul ts of the dete cto r are
available in the status register and a dedicated result register that can be read via the
serial control interface (SCI) by the external controller. All sixteen standard DTMF tones
are recognized.
Figure 21 DTMF Detector - Block Diagram
Table 12 to 14 show the associated registers.
As soon as a v ali d DTM F t one is reco gni zed , t he status word and the D TM F t one c ode
are updated (table 13).
DTV is set when a DTMF tone is recognized and reset when no DTMF tone is recognized
or the detector is disabled. The code for the DTMF tone is placed into the register
DDCTL. The registers DDTW and DDLEV hold parameters for detection (table 14).
Table 12 DTMF Detector Control Register
Register # of Bits Name Comment
DDCTL 1 EN DTMF detector enable
DDCTL 5 I1 Input signal selection
Table 13 DTMF Detector Results
Register # of Bits Name Comment
STATUS 1 DTV DTMF code valid
DDCTL 5 DTC DTMF tone code
Table 14 DTMF Detector Parameters
Register # of Bits Name Comment
DDTW 15 TWIST Twist for DTMF recognition
DDLEV 6 MIN Minimum signal level to detect DTMF tones
DTMF SCI
I1Recognition
PSB 4860
Functional Description
Semiconductor Group 45 10.97
2.1.6 CNG Detector
The calli ng tone (C NG) detector c an detect the standard ca lling tone s of fax mach ines
or modems. This helps to distinguish voice messages from data transfers. The result of
the detector is available in the status register that can be read via the serial control
interface (SC I) by the exte rnal con troller. The C NG detector c onsists o f two band-pas s
filters with fixed center frequency of 1100 Hz and 1300 Hz.
Figure 22 CNG Detector - Block Diagram
Table 15 shows the available parameters.
Both the programmed minimum time and the minimum signal level must be exceeded
for a valid CNG tone. Furthermore the input signal resolution can be reduced by the RES
parameter. This can be useful in a noisy environment at low signal levels although the
accuracy of the detection d ecreases. As soo n as a valid tone is recognized, t he status
word of the PSB 4860 is updated. The status bits are defined as follows:
Table 15 CNG Detector Registers
Register # of Bits Name Comment
CNGCTL 1 EN CNG detector enable
CNGCTL 5 I1 Input signal selection
CNGLEV 16 MIN Minimum signal level
CNGBT 16 TIME Minimum time of signal burst
CNGRES 16 RES Input signal resolution
Table 16 CNG Detector Result
Register # of Bit s Name Comment
STATUS 1 CNG Fax/Modem calling tone detected
CNG Detector
SCI
I1
1100 Hz 1300 Hz
PSB 4860
Functional Description
Semiconductor Group 46 10.97
2.1.7 Alert Tone Detector
The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for
caller id protocols. The results of the detector are available in the status register and the
dedi cated regis ter ATDCT L0 that can be r ead via the se rial co ntrol int erface (SCI) by the
external controller.
Figure 23 Alert Tone Detector - Block Diagram
As soon as a valid alert tone is recognized, the status word of the PSB 4860 and the code
for the detected combination of alert tones are updated (table 18).
Table 17 Alert Tone Detector Registers
Register # of Bits Name Comment
ATDCTL0 1 EN Alert Tone Detector Enable
ATDCTL0 5 I1 Input signal selection
ATDCTL1 1 MD Detection of dual tones or single tones
ATDCTL1 1 DEV Maximum deviation (0.5% or 1.1%)
ATDCTL1 8 MIN Minimum signal level to detect alert tones
Table 18 Alert Tone Detector Results
Register # of Bits Name Comment
STATUS 1 ATV Alert tone detected
ATDCTL0 2 ATC Alert tone code
Alert Tone SCI
I1 Detector
PSB 4860
Functional Description
Semiconductor Group 47 10.97
2.1.8 CPT Detector
The selected signal is monitored continuously for a call progress tone. The CPT detector
consists of a band-pass and an optional timing checker (figure 24).
Figure 24 CPT Detector - Block Diagram
The CPT detector can be used in two modes: raw and cooked. In raw mode, the
occurrence of a signal within the frequency range, time and energy limits is directly
reported. The timing checker is bypassed and therefore the PSB 4860 does not interpret
the length or interval of the signal.
In cook ed mod e, the number and durati on of sig nal bu rsts are interpreted by th e t imin g
checker. A signal burst followed by a gap is called a cycle. Cooked mode requires a
minimum of two cycles. The CPT flag is set with the first burst after the programmed
number of cycles has been detected. The CPT flag remains set until the unit is disabled,
even if the conditions are not met anymore. In this mode the CPT is modelled as a
sequence of identical bursts separated by gaps with identical length. The PSB 4860 can
be programmed to accept a range for both the burst and the gap. It is also possible to
specify a maximum aberration of two consecutive bursts and gaps. Figure 25 sh ows the
parameters for a single cycle (burst and gap).
Figure 25 CPT Detector - Cooked Mode
The status bit is defined as follows:
Timing
Band-pass
SCI (Statu s)I1
300-640 Hz
Checker
tBmax
tBmin
tGmin
tGmax
PSB 4860
Functional Description
Semiconductor Group 48 10.97
CPT is not affected by reading the status word. It is automatically reset when the unit is
disabled. Table 20 shows the control register for the CPT detector.
If any c ondition is viol ated durin g a seq uence of cycles t he timing checke r is rese t and
restarts with the next valid burst.
Note: In cooked mode CPT is set with the first burst after the programmed number of
cycles has been detected.
Note: The number of cycles must be set to zero in raw mode.
Table 19 CPT Detector Result
Register # of Bits Name Comment
STATUS 1 CPT CP tone currently detected [340 Hz; 640 Hz]
Table 20 CPT Detector Registers
Register # of Bits Name Comment
CPTCTL 1 EN Unit enable
CPTCTL 1 MD Mode (cooked, raw)
CPTCTL 5 I1 Input signal selection
CPTMN 8 MINB Minimum time of a signal burst (tBmin)
CPTMN 8 MING Minimum time of a signal gap (tGmin)
CPTMX 8 MAXB Maximum time of a signal burst (tBmax)
CPTMX 8 MAXG Maximum time of a signal gap (tGmax)
CPTDT 8 DIFB Maximum diffe renc e betw een con sec uti ve burst s
CPTDT 8 DIFG Maximum diffe renc e betw een con sec uti ve gaps
CPTTR 3 NUM Number of cycles (cooked mode), 0 (raw mode)
CPTTR 8 MIN Minimum signal level to detect tones
CPTTR 4 SN Minimal signal-to-noise ratio
PSB 4860
Functional Description
Semiconductor Group 49 10.97
2.1.9 Caller ID Decoder
The calle r ID decoder i s basically a 1200 baud modem (FSK, demodulati on only). Th e
bit stream is formatted by a subsequent UART and the data is available in a data register
along with status information (figure 26).
Figure 26 Caller ID Decoder - Block Diagram
The FSK demodulator supports two modes according to table 21. The appropriate mode
is detected automatically.
The CID decoder does not interpret the data received. Each byte received is placed into
the CIDCTL register (table 23). The status byte of the PSB 4860 is updated (table 22).
CIA and CD are cleared when the unit is disabled. In addition, CIA is cleared when
CIDCTL0 is read.
Table 21 Caller ID Decoder Modes
Mode Mark
(Hz) Space
(Hz) Comment
1 1200 2200 Bellcore
2 1300 2100 V.23
Table 22 Caller ID Decoder Status
Register # of Bit s Name Comment
STATUS 1 CIA CID byte received
STATUS 1 CD Carrier Detected
Table 23 Caller ID Decoder Registers
Register # of Bits Name Comment
CIDCTL0 1 EN Unit enable
CIDCTL0 5 I1 Input signal selection
CIDCTL0 8 DATA Last CID data byte received
UART
FSK demod. SCI (Statu s, D ata)
I1 (Bellcore , V.23)
PSB 4860
Functional Description
Semiconductor Group 50 10.97
When the CID unit is enabled, it first waits for a channel seizure signal consisting of a
series of alternating space and mark signals. The number of spaces and marks that have
to be received without errors before the PSB 4860 reports a carrier detect by setting
status bit CD can be programmed.
Channel seizure must be followed by at least 16 continuous mark signals. The first space
signal detected is then regarded as the start bit of the first message byte.
The interpretation of the data, including message type, length and checksum is
completely left to the controller. The CID unit should be disabled as soon as the complete
information has been received as it cannot detect the end of the transmission by itself.
Note: Some caller ID mechanism may require additional external components for DC
decoupling. These tasks must be handled by the controller.
Note: The controller is responsible for selecting and storing parts of the CID as needed.
CIDCTL1 5 NMSS Number of mark/space sequences necessary for
successful detection of carrier detect
CIDCTL1 6 NMB Number of mark bits necessary before space of first
byte after carrier detect
CIDCTL1 5 MIN Minimum signal level for CID detection
Table 23 Caller ID Decoder Registers
Register # of Bits Name Comment
PSB 4860
Functional Description
Semiconductor Group 51 10.97
2.1.10 DTMF Generator
The DTMF generator can generate single or dual tones with programmable frequency
and gai n. This un it is pr imari ly used to generate the co mmon D TMF ton es but ca n also
be used for signalling or other user defined tones. A block diagram is shown in figure 27.
Figure 27 DTMF Generator - Block Diagram
Both generators and amplifiers are identical. There are two modes for programming the
generators, cooked mode and raw mode. In cooked mode, the standard DTMF
frequencies are generated by programming a single 4 bit code. In raw mode, the
frequency of each generator/amplifier can be programmed individually by a separate
register. The unit has two outputs which provide the same signal but with individually
programmable attenuation. Table 24 shows the parameters of this unit.
Note: DGF1 and DGF2 are undefined when cooked mode is used and must not be
written.
Table 24 DTMF Generator Registers
Register # of Bit s Name Comment
DGCTL 1 EN Enable for generators
DGCTL 1 MD Mode (cooked/raw)
DGCTL 4 DTC DTMF code (cooked mode)
DGF1 1 5 FRQ1 Frequency of generato r 1
DGF2 1 5 FRQ2 Frequency of generato r 2
DGL 7 LEV1 Level of signal for generator 1
DGL 7 LEV2 Level of signal for generator 2
DGATT 8 ATT1 Attenuation of S9
DGATT 8 ATT2 Attenuation of S10
f1
f2
generator
generator
gain1
gain2 att2
S9
S10
att1
PSB 4860
Functional Description
Semiconductor Group 52 10.97
2.1.11 Speech Coder
The speech coder (figure 28) has two input signals I1 and I2. The first signal (I1) is fed to
the coder w hile the second signal (I2 ) is used as a reference signal fo r voice co ntrolled
recording. The signal I1 can be coded by either a High Quality coder or a Long Play
coder.
Figure 28 Speech Coder - Block Diagram
In High Qua lity the output da ta stream runs at a fixed rate of 10300 bit/s and provides
excellent s peech qual ity. In Long Pla y mode, the ou tput data stream is further reduc ed
to an average of 3300 bit/s while still maintaining good quality.
Data is written starting at the current file pointer and the file pointer is advanced as
needed. In ca se of any m emory e rror (e.g. memory full ) a fil e error is i ndicated a nd the
coder is disabled. The controller must subsequently close the file.
The coder can be switched on the fly. However, it may take up to 60 ms until the switch
is executed. The controller must therefore wait for at least this time until issuing another
command that relies on the mode switch. No audio data is lost during switching.
The signal I2 is first filtered by a low pass LP1 with programmable time constant and then
compared to a reference level MIN. If the filtered signal exceeds MIN, then the status bit
SD (table 25) is set immediately. If the filtered signal has been smaller than MIN for a
programmable time TIME then the status bit SD is reset.
The coder can be enabled in permanent mode or in voice recognition mode. In
permanent mode, the coder starts immediately and compresses all input data
continuously. The current state of the status bit SD does not affect the coder.
In voice recognition mode, the coder is automatically started on the first transition of the
status bit from 0 to 1. Once the coder has started it remains active until disabled.
Table 25 Speech Coder Status
Register # of Bits Name Comment
STATUS 1 SD Speech detected
HQ
10300 bit/s
LP
3300 bit/s
I2
I1
Memory
MIN
LP
PSB 4860
Functional Description
Semiconductor Group 53 10.97
The operation of the speech coder is defined according to table 26.
Note: The peak data rate in LP mode is 4800 bit/s.
Note: Both HQ and LP mode will not produce identical bit streams after a coding/
decodi ng cyc le.
Table 26 Speech Coder Registers
Register # of Bit s Name Comment
SCCTL 1 EN Enable speech coder
SCCTL 1 HQ High quality mode
SCCTL 1 VC Voice controlled recording
SCCTL 5 I1 Input signal 1 selection
SCCTL 5 I2 Input signal 2 selection
SCCT2 8 MIN Minimal signal level for speech detection
SCCT2 8 TIME Minimum time for reset of SD
SCCT3 8 LP Time constant for low-pass
PSB 4860
Functional Description
Semiconductor Group 54 10.97
2.1.12 Speech Decoder
The speech decoder (figure 29) decompresses the data previously coded by the speech
coder unit and delivers a standard 128 kbit/s data stream.
Figure 29 Speech Decoder - Block Diagram
The decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent
of the selected quality. The decoder requests input data as needed at a variable rate.
Table 27 shows the signal and mode selection for the speech decoder.
Data reading starts at the location of the current fil e pointer. The fi le pointer is updated
during speech decoding. If the end of the file is reached, the decoder is automatically
disabled. The PSB 4860 automatically resets SDCTL:EN at this point.
Table 27 Speech Decoder Registers
Register # of Bits Name Comment
SDCTL 1 EN Enable speech decoder
SDCTL 2 SPEED Selection of playback speed
HQ
10300 bit/s
LP
3300 bit/s
S13
Memory
PSB 4860
Functional Description
Semiconductor Group 55 10.97
2.1.13 Analog Front End Interface
There are two identical interfaces at the analog side (to PSB 4851) as shown in figure 30.
Figure 30 Analog Front End Interface - Block Diagram
For each si gnal a n ampl ifier is pr ovided for le vel a djustme nt. The in coming signa ls ca n
be passed through an optional high-pass (HP). This high-pass (fg=20 Hz) is useful for
blocking DC offs ets and sh ould be enable d by de faul t. Furth ermore , up to thre e sig nals
can be mixed in order to generate the outgoing signals (S2,S4). Table 28 shows the
associated regis ters .
Table 28 Analog Front End Interface Registers
Register # of Bit s Name Comment
IFG1 16 IG1 Gain for IG1
IFG2 16 IG2 Gain for IG2
IFS1 1 HP High-pass for S1
IFS1 5 I1 Input signal 1 for IG2
IFS1 5 I2 Input signal 2 for IG2
IFS1 5 I3 Input signal 3 for IG2
IFG3 16 IG3 Gain for IG3
IFG4 16 IG4 Gain for IG4
IFS2 1 HP High-pass for S3
IFS2 5 I1 Input signal 1 for IG4
IFS2 5 I2 Input signal 2 for IG4
IFS2 5 I3 Input signal 3 for IG4
Channel 2
S
1
Channel 1
S
2
I1
I2
I3
line out
line in IG1
IG2
S
3
S
4
I1
I2
I3
loudspeaker
microphone
IG4
HP IG3 HP
PSB 4860
Functional Description
Semiconductor Group 56 10.97
2.1.14 Digital Interface
There are two almost identical i nterfaces at the di gital side as shown in figure 31. The
only difference between these two interfaces is that only channel 1 supports the SSDI
mode.
Figure 31 Digital Interface - Block Diagram
Each out going s ignal c an b e the s um of tw o sign als w ith no a tten uation a nd one sig nal
with programmable attenuation (ATT). The attenuator can be used for artificial echo if
there is none externally provided (e.g. ISDN application). Each input can be passed
through an optional high-pass (HP). The associated registers are shown in table 29.
Table 29 Digital Interface Registers
Register # of Bits Name Comment
IFS3 5 I1 Input signal 1 for S6
IFS3 5 I2 Input signal 2 for S6
IFS3 5 I3 Input signal 3 for S6
IFS3 1 HP High-pass for S5
IFS4 5 I1 Input signal 1 for S8
IFS4 5 I2 Input signal 2 for S8
IFS4 5 I3 Input signal 3 for S8
IFS4 1 HP High-pass for S7
Channel 2 (IOM®-2 Interface)Channel 1 (SSDI/IOM®-2 Interface)
S
7
S
8
I1
I2
I3
ATT2
HP
S
5
S
6
I1
I2
I3
ATT1
HP
PSB 4860
Functional Description
Semiconductor Group 57 10.97
IFG5 8 ATT1 Attenuation for input signal I3 (Channel 1)
IFG5 8 ATT2 Attenuation for input signal I3 (Channel 2)
Table 29 Digital Interface Registers
Register # of Bit s Name Comment
PSB 4860
Functional Description
Semiconductor Group 58 10.97
2.1.15 Universal Attenuator
The PSB 4860 contains an universal attenuator that can be connected to any signal (e.g.
for sidetone gain in ISDN applications).
Figure 32 Universal Attenuator - Block Diagram
Table 30 shows the associated register.
Table 30 Universal Attenuator Registers
Register # of Bits Name Comment
UA 8 ATT Attenuation for UA
UA 5 I1 Input signal for UA
S14
UA
I1
PSB 4860
Functional Description
Semiconductor Group 59 10.97
2.1.16 Automatic Gain Control Unit
In addition to the unive rsal attenuator with programmable but fixed gai n the PSB 4860
contains an amplifier with automatic gain control (AGC). The AGC is preceeded by a
signal summation point for two input signals. One of the input signals can be attenuated.
Figure 33 Automatic Gain Control Unit - Block Diagram
Furthermore the signal after the summation point is available. Besides providing a
general sig nal summatio n (S16 not used) this sign al is especi ally usef ul if the AGC un it
provides the input signal for the speech coder. In this case S17 can be used as a
reference signal for voice controlled recording.
The operation of the AGC is similar to AGCX (ACCR) of the speakerphone. The
differences are as follows:
• No NOIS parameter
• Separate enable/disable control
• Slightly different coefficient format
Furthermore the AGC contains a comparator that starts and stops the gain regulation.
The signal after the summation point (S17) is filtered by a peak detector with time
constant DEC for decay. Then the signal is compared to a programmable limit LIM.
Regulation takes only place when the filtered signal exceeds the limit.
Table 31 shows the associated registers.
Table 31 Automatic Gain Control Registers
Register # of Bit s Name Comment
AGCCTL 1 EN Enable
AGCCTL 5 I1 Input signal 1 for AGC
AGCCTL 5 I2 Input signal 2 for AGC
AGCATT 15 ATT Attenuation for I2
AGC1 8 AG_INIT Initial AGC gain/attenuation
AGC1 8 COM Compare level rel. to max. PCM-value
S16
AGC
I1
ATT
I2S17
PSB 4860
Functional Description
Semiconductor Group 60 10.97
AGC2 8 SPEEDL Change rate for lower levels
AGC2 8 SPEEDH Change rate for higher level
AGC3 8 AG _ATT Atte nuat ion range
AGC3 7 AG _GAI N Gain range
AGC4 7 DEC Peak detector time constant
AGC4 8 LIM Comparator minimal signal level
AGC5 7 LP AGC low pass time constant
Table 31 Automatic Gain Control Registe rs
Register # of Bits Name Comment
PSB 4860
Functional Description
Semiconductor Group 61 10.97
2.1.17 Equalizer
The PSB 4860 also provides an equalizer that can be inserted into any signal path. The
main application for t he e qua liz er is the ada ption to the frequ enc y c hara cte ri sti cs of th e
microphone, transducer or loudspeaker.
The equalizer consists of an IIR filter followed by an FIR filter as shown in figure 34.
Figure 34 Equalizer - Block Diagram
The coefficients A1-A9, B2-B9 and C1 belong to the IIR filter, the coefficients D1-D17 and
C2 belong to the FIR filter. Table 32 shows the registers associated with the equalizer.
Table 32 Equalizer Registers
Register # of Bit s Name Comment
FCFCTL 1 EN Enable
FCFCTL 5 I Input signal for equalizer
FCFCTL 6 ADR Filter coefficient address
FCFCOF 16 Filter coefficient data
z-1 z-1 z-1
A1 A2 A9
z-1
z-1
z-1
C1
B2B9
z-1 z-1 z-1
D1 D2 D17
C2
S18
I
FIR
IIR
PSB 4860
Functional Description
Semiconductor Group 62 10.97
Due to the multit ude of coefficie nts the use s an indirec t address ing sche me for reading
or writing an individual coefficient. The address of the coefficient is given by ADR and
the actual value is read or written to register FCFCOF.
In order to ease programming the PSB 4860 automatically increments the address ADR
after each access to FCFCOF.
Note: Any access to an out-of-range address automatically resets FCFCTL:ADR.
PSB 4860
Functional Description
Semiconductor Group 63 10.97
2.2 Memory Management
Memory Management
Memory Management - General
This section describes the memory management provided by the PSB 4860. As figure
35 shows, three units can access the external memory. During recording, the speech
coder can write compressed speech data into the external memory. For playback, the
speech decoder reads compressed speech data from external memory. In addition, the
microcontroller can directly access the memory by the SCI interface.
Figure 35 Memory Management - Data Flow
The memory is organ ize d as a f ile sy stem. For e ach me mory spa ce (R/W-memo ry an d
voice prompt memory) the PSB 4860 maintains a directory with 255 file descriptors
(figure 36).
Figure 36 Memory Management - Directory Structure
The directories must be created after each power failure for volatile R/W-memory. All file
descriptors are cleared (all words zero). For non-volatile memory, the directories have to
Speech Decoder
Speech Co der
MemorySCI
length (0- 65535)
user data (1 6 bits)
file descriptor 1
file descriptor 255
file descriptor n
file descriptor (R/W)directory
RTC1 (16 bits)
RTC2 (16 bits)
PSB 4860
Functional Description
Semiconductor Group 64 10.97
be created only once. If the directories already exist, the memory has just to be activated
after a reset. The file descriptors are not changed in this case.
All commands that access the other fields or involve a write access must not be used in
voice prompt memory space.
2.2.1 File Definition and Access
A file is a linear sequence of units and can be accessed in two modes: binary and audio.
In binary mode, a unit is a word. In audio mode, a unit is a variable number of words
representing 30 ms of uncompressed speech. A file can contain at most 65535 units.
Figure 37 show s an audio file containi ng 100 aud io units. The len gth of the message is
therefore 3 s.
Figure 37 Audio File Organization - Example
Figure 38 shows a binary file of 11 words containing a phonebook (with only two entries).
Figure 38 Binary File Organization - Example
There is one special file in the voice prompt directory (referenced by file number 255)
which is intended for a large number of phrases and hence has a different
organization.This file exists only in the directory for the voice prompt memory. It consists
of up to 2048 phrases of arbitrary individual length. The actual number of units within an
individual phrase is determined during creation and cannot be altered afterwards.
Phrases can be combined in any sequence without intermediate noise or gaps.
Hi Jack, this is Tom. Please call me back tomorrow.
099
3 s
544F 4D20 3535 3534 3330 004A 4143 4B20 5555 5538 3131
TO
0101
M 555430 JACK 555811
PSB 4860
Functional Description
Semiconductor Group 65 10.97
Figure 39 shows a phrase file containing a total of five phrases.
Figure 39 Phrase File Organization - Example
Before an access to a file can take place, the file must be opened with the following
information:
1. memory space
2. file number
3. access mode
These param eters rema in effect ive unti l the next ope n comma nd is giv en or, in c ase of
the file pointer, until a file access. All other files are closed and cannot be accessed. The
file with file number 0 is not a physical file. Opening this file closes all physical files.
The PSB 4860 provides four registers for file access and two bits within the STATUS
register. Table 33 shows these registers.
The status register contains two flags (table 34) to indicate if currently a file command is
under execu tion and if the las t file com man d termi nate d without error. A new com man d
must not be written to FCMD while the last one is still running (STATUS:BSY=1). The
only command that can be aborted is Compress File.
Table 33 Memory Management Registers
Register # of Bit s Comment
FCMD 16 Command to execute
FCTL 16 Access mode and file number
FDATA 16 Data transfer and additional parameters
FPTR 16 (11) File pointer (phrase selector)
STATUS 16 Busy and Error indication
Table 34 Memory Management Status
Register # of Bit s Name Comment
STATUS 1 BSY File command or decoder/encoder still running
STATUS 1 ERR File command completed/aborted with error
one two you have messages le ft friday
01 4
PSB 4860
Functional Description
Semiconductor Group 66 10.97
Writing to FCMD also resets the error bit in the status register.
Table 35 shows th e parameters de fining the acces s mode and the acc ess location. All
parameters can only be written when no file command is currently running. They become
effective aft er the completion of an open command. If another unit (e.g. spee ch coder)
accesses the fil e, the file pointer is upda ted automaticall y. Therefore the controll er can
monitor the progress of recording or playing by reading the file pointer.
Commands are written to the FCMD register. The busy bit in the STATUS register is set
within 125µs. The command may start execution after a delay, however (see section
2.2.5). Some commands require additional parameters which are written prior to the
command into the specified registers. Data transfer is done by the register FDATA (both
reading and writing).
2.2.2 User Data Word
The user data wo rd consis ts of 12 bits that can be read or written by the user, two bits
(R) that are reserved for future use and two read-only bits (D,M) which indicate the status
of a file.
If D is set, the file is marked for deletion and should not be used any more. This bit is
maintained by the PSB 4860 for housekeeping.
Table 35 Memory Management Parameters
Register # of Bits Name Comment
FCTL 1 MS Memory space (R/W or voice prompt)
FCTL 1 MD Access mode (audio or binary)
FCTL 1 TS Write timestamp (file open only)
FCTL 8 FNO File number (active file)
FPTR 16 File pointer or phrase selector
15 0
D M R R User Definable
PSB 4860
Functional Description
Semiconductor Group 67 10.97
2.2.3 High Level Memory Management Commands
This section describes each of the high level memory management commands in detail.
These commands are sufficient for normal operation of an answering machine. In
addition, th ere are four low level c ommand s (sectio n 2.2.4). These comma nds are onl y
required for special tasks like in-system reprogramming of the voice prompt area.
Memory Management - Commands
2.2.3.1 Initialize
This command creates a directory, sets the external memory configuration and delivers
the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory
space is scanned for a valid directory. The PSB 4860 can either create an empty
directory from scratch or leave the first n files of an existing directory untouched while
deleting the remaining files (ARAM/DRAM only). This option is useful if due to an
unexpected event (e.g. power loss during recording) some data is corrupted. In that case
vital system information can still be recovered if it has been stored in the first files.
Possible Errors:
• no R/W memory f ound
• more than 59 bad blocks (flash and ARAM)
• voice prompt directory requested, but not detected
Note: This command must be given only once for flash devices.
Table 36 Initialize Memory Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Initialize command code
FCMD 1 IN Confirmation for Initialization
FCTL 8 FNO 0: delete no file
1: delete all files
n: delete starting with file n
CCTL 2 MT Type of R/W memory (DRAM, Flash)
CCTL 1 MQ Quality of R/W memory (Audio, Normal)
CCTL 1 MV Scan for voice prompt directory
Table 37 Initialize Memory Results
Register # of Bit s Name Comment
FDATA 16 Number of usable 1kByte blocks in R/W memory
PSB 4860
Functional Description
Semiconductor Group 68 10.97
2.2.3.2 Activate
This command activates an existing directory, sets the external memory configuration
and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt
memory space is scanned for a valid directory. Upon activation the PSB 4860 checks (in
case of ARAM/DRAM only) the consistency of the directory in R/W memory space. It
returns the first file that contains corrupted data (if any). If corrupted data is detected an
initialization should be performed with the same file number as an input parameter.
Possible error conditions:
• no memory connected
• no directory found
• device ID wrong (flash only)
• corrupted files found (see FCTL:FNO)
• directory corrupted
This command can have three types of result as shown in table 40.
Table 38 Activate Memory Parameters
Register # of Bits Name Comment
FCMD 5 CMD Activate command code
CCTL 2 MT Type of R/W memory (DRAM, Flash)
CCTL 1 MQ Quality of R/W memory (Audio, Normal)
CCTL 1 MV Voice prompt directory available
Table 39 Activate Memory Results
Register # of Bits Name Comment
FDATA 16 Number of usable 1 kByte blocks in R/W memory
FCTL 8 FNO n: number of first corrupted file
Table 40 Activate Memory Result Interpretation
Result STATUS:
ERR FCTL:
FNO Comment
no error 0 0 Command successful, memory activated.
soft error 1 n The first n-1 files are O.K. The memory is activated.
hard error 1 1 The memory is not activated due to a hard error.
PSB 4860
Functional Description
Semiconductor Group 69 10.97
2.2.3.3 Open File
A specific file is opened for subsequent accesses with the specified access mode.
Opening a new file automatically closes the currently open file and clears the file pointer.
Opening file number 0 can be used to close all physical files. If the TS flag is set, the
current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor
in order to provide a timestamp.
Possible error conditions:
• selected file marked for deletion, but not yet deleted by garbage collection
• memory space invalid
• new file selected, but memory full
• <fno> exceeds number of prompts (in voice prompt space only)
• wrong access mode selected for existing file
Note: In case of flash memory existing ones in the entries RTC1/RTC2 of the file
descriptor cannot be altered. Therefore TS should be set only once during the
lifetime of a file.
2.2.3.4 Open Next Free File
The next free file is opened for subsequent write accesses with the specified access
mode. The search starts at the specified file number. If the TS flag is set, the current
content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in
order to provide a timestamp. If a free file has been found, the file is opened and the file
number is returned in FCTL:FNO. Otherwise an error is reported.
Table 41 Open File Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Open command code
FCTL 1 MS Memory space (R/W, voice prompt)
FCTL 1 MD Acce ss mod e (audio or binary )
FCTL 1 TS Write timestamp
FCTL 8 FNO File num ber <fno>
Table 42 Open Next Free File Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Open Next Free File command code
FCTL 1 MD Acce ss mod e (audio or binary )
PSB 4860
Functional Description
Semiconductor Group 70 10.97
:
Possible error conditions:
• no unused file found
• memory full
Note: In case of flash memory existing ones cannot be altered. Therefore TS should be
set only once during the lifetime of a file.
Note: R/W-memory must be selected. Otherwise the result is unpredictable.
2.2.3.5 Seek
The file p ointer of the curren tly open ed file i s set to the spe cified p osition . If t he current
file is the phrase file the PSB 4860 starts the speech decoder immediately after the seek
is finished. This is done by simply enabling the decoder. All other settings of the decoder
remain unaffected. The BSY bit is first set during the file command. It is then reset for a
short period until the speech decoder is enabled internally. It is then set again while the
decoder is running and finally reset when the phrase is finished.
Possible error conditions:
• file pointer out of range
• phras e numbe r out of range
FCTL 1 TS Write timestamp
FCTL 8 FNO Starting point (>0)
Table 43 Open Next Free File Results
Register # of Bits Name Comment
FCTL 8 FNO File number
Table 44 Seek Parameters
Register # of Bits Name Comment
FCMD 5 CMD Seek command code
FPTR 16 (11) File pointer (phrase selector)
Table 42 Open Next Free File Parameters
Register # of Bits Name Comment
PSB 4860
Functional Description
Semiconductor Group 71 10.97
2.2.3.6 Cut File
All uni ts starting wit h the unit a ddressed by the file po inter are removed from the f ile. If
all units are deleted the file is marked for deletion (see user data word). However, the
associated file descriptor and memory space are released only after a subsequent
garbage collection.
Possible error conditions:
• file pointer out of range
• voice prompt memory selected
2.2.3.7 Compress File
An audio file tha t has been recorded in H Q mode ca n be recode d using LP mod e. This
reduces t he file si ze to approxim ately one thi rd of the ori ginal s ize. Th e spee ch qua lity,
howe ver, is somewhat lo wer compared to a si gnal that has been record ed in LP mode
in th e first plac e. This c ommand ca n be aborte d at an y time an d resumed l ater without
loss of info rmation. Prior to this comman d all files must be cl osed. Table 46 shows th e
parameters for this command.
.
Possible error conditions:
• <fno> invalid
• another file currently open
• bin ary file sel ected
Table 45 Cut File Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Cut command code
FPTR 16 Position of first unit to delete
Table 46 Compress File Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Compress command code
FCTL 8 FNO File num ber <fno>
PSB 4860
Functional Description
Semiconductor Group 72 10.97
2.2.3.8 Memory Status
This command returns the number of available 1 kB blocks in R/W memory space.
Possible error conditions:
• file open
2.2.3.9 Garbage Collection
This command initiates a garbage collection. Until a garbage collection files that are
marked for de letion stil l occupy the associ ated file d escriptor and memory sp ace. After
the garbage collection these file descriptors and the associated memory space are
available again. This command can optionally remap the directory. In this mode the
remaining file descriptors are remapped to form a contiguous block starting with file
number 1. The original order is preserved. This command requires that all files are
closed, i. e. file 0 is o pened. Inde pendently of th e selected di rectory only th e read/write
directory is used.
Possible error conditions:
• file open
2.2.3.10 Access File Descriptor
By this command the length, user data word and RTC1/RTC2 of a file descriptor can be
read. The user data word can also be written. The file or the other entries of the file
descriptor are not affected by this command.
Table 47 Memory Status Parameters
Register # of Bits Name Comment
FCMD 5 CMD Memory status code
Table 48 Memory Status Results
Register # of Bits Name Comment
FDATA 16 FREE Number of free blocks
Table 49 Garbage Collection Parameters
Register # of Bits Name Comment
FCMD 5 CMD Garbage Collection Command Code
FCMD 1 RD Remap Directory
PSB 4860
Functional Description
Semiconductor Group 73 10.97
Possible error conditions:
• none
Note: In case of flash memory bits already set to 1 cannot be altered.
Note: Do not use this command with the phrase file (fno = 255).
2.2.3.11 Read Data
This command can be used in binary access mode only. A single word is read at the
position given by the file pointer. The file pointer can be set by the Seek command. The
file pointer is advanced by one word automatically.
Possible error conditions:
• file pointer out of range
• phrase file selected
• aud io file sel ecte d
Table 50 Access File Descriptor Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Read Access or Write Access command code
FDATA 16 User data (write access only)
Table 51 Access File Descriptor Results
Register # of Bit s Name Comment
FDATA 16 Content of selected entry (read access only)
Table 52 Read Data Parameters
Register # of Bit s Name Comment
FCMD 5 CMD Read Data Command Code
Table 53 Read Data Re sults
Register # of Bit s Name Comment
FDATA 16 Data word
PSB 4860
Functional Description
Semiconductor Group 74 10.97
2.2.3.12 Write Data
This commands can be used in binary access mode only. A single word is written at the
position of the file pointer. The file pointer is advanced by one word automatically. Note,
that for FLASH memory only zero es c an be overw ritte n by ones . This restric tio n occ urs
only if an already used value within an existing file is to be overwritten.
Possible error conditions:
• file pointer out of range (for existing files only)
• voice prompt memory selected
• memory full
• audio file selected
Table 54 Write Data Parameters
Register # of Bits Name Comment
FCMD 5 CMD Access Mode Command Code (including mode)
FDATA 16 D ata wo rd
PSB 4860
Functional Description
Semiconductor Group 75 10.97
2.2.4 Low Level Memory Management Commands
These commands allow the direct access of any location (single word) of the external
memory. Additionally it is possible to erase any block in case of a flash device. These
commands should not be used during normal operation as they may interfere with the
file system. No file must be open when one of these commands is given.
The primary use of these commands is the in-system programming of a flash device with
voice prompts. Please refer to the appropriate Application Notes.
2.2.4.1 Set Address
This comma nd sets the 24 bi t address poin ter APTR. Only the addres s bits A8-A23 are
set, the address bits A0-A7 are automatical ly cle ared.
Possible error conditions:
• file open
2.2.4.2 DMA Read
This command reads a single word addressed by APTR. After the read access APTR is
automatically incremented by one. Table 56 shows the parameters for this command.
Possible error conditions:
• file open
Table 55 Se t Addre ss Para meters
Register # of Bit s Name Comment
FCMD 5 CMD Set Address command code
FDATA 16 ADR Address bits A8-A23 of address pointer APTR
Table 56 DMA Read Para meters
Register # of Bit s Name Comment
FCMD 5 CMD DMA Read command code
Table 57 DMA Read Resu lts
Register # of Bit s Name Comment
FDATA 16 DATA Data read from address APTR.
PSB 4860
Functional Description
Semiconductor Group 76 10.97
2.2.4.3 DMA Write
This comma nd writes a singl e word to the lo cation add ressed by APTR . After the w rite
access APTR is autom aticall y increm ented b y one. Tabl e 58 shows the param eters fo r
this command.
Possible error conditions:
• file open
Note: If flash memory is connected the actual write is only performed when the last word
within a pa ge i s w ritte n. U nti l th en t he data is merel y bu ffere d in the flas h d evi ce.
Please check the flash memory data sheets on page size.
2.2.4.4 Block Erase
This command erases the physical block which includes the address given by APTR.
The actual amount of memory erased by this command depends on the block size of the
flash device. Table 59 shows the parameters for this command.
Possible error conditions:
• file open
• ARAM/DRAM configured
Table 58 DMA Write Parameters
Register # of Bits Name Comment
FCMD 5 CMD DMA Write command code
FDATA 16 DATA Data to be written to APTR
Table 59 Block Erase Parameters
Register # of Bits Name Comment
FCMD 5 C MD Block Era se com man d code
PSB 4860
Functional Description
Semiconductor Group 77 10.97
2.2.5 Execution Time
The execution time of the file commands is determined by four factors:
1. Internal state of the PSB 4860
2. Memory conf igu ration
3. Memory stat e
4. Individual characteristics of the memory devices
Therefore there is no genera l formula for an exact c alculation of the execution time for
file commands. For ARAM/DRAM items three and four are not significant as the memory
access timing is always fixed and no additional delay is incurred for erasing memory
blocks. However, the amount of memory has significant impact on the initialization in
case of ARAM and flash.
For flash devices the particular location of a write access in combination with the internal
organization of the memory device may result in a block erase and subsequent write
accesse s in order to copy data . In this case the indiv idual erase and write timin g of the
attached devices also prolongs the execution time.
The first factor, the internal state of the PSB 4860, can influence all file commands
regardless of the memory type attached. In general the PSB 4860 may delay any file
command by up to 30 ms. However, it is possible to skip this delay if the following
conditions hold:
1. The command is not
initialize/activate
2. Neither the DTMF detector nor the speech coder nor the speech decoder are running
If neither condition is violated then the PSB 4860 can be forced to start command
execution immediately. This is done by setting the EIE bit in the FCMD register along
with the command code.
Table 60 gives an indication of the execution time for two typical memory configurations.
Table 60 Ex ecution Times
Command ARAM (4 MBit) KM29LV040
Initialize 40 s1) <11 s
Activate < 10 ms 3 s
Open File /Open Next Free File <10 ms <26 ms
Seek (within 4 MBit File) <0.5 s <0.5 s
Seek (within phrase file) <1 ms <1 ms
Cut File <5 ms <5 ms
Compress File #units * 30 ms #units * 30 ms
Access File Descriptor <10 ms <10 ms
PSB 4860
Functional Description
Semiconductor Group 78 10.97
2.2.6 Special Notes on File Commands
1. No MMU commands must be inserted between opening a file and writing data to it,
either by writing data to a binary file or by enabling the coder for audio files.
Therefore reading or writing the file descriptor is only allowed after all data writing has
happened.
2. If an audio file has been opened for replay, a Write File Descriptor Command must be
followed by a Seek command before the decoder can be enabled.
1) less than 20 m s for D R AM
Memory Status <10 ms <10 ms
Read/Write Data <10 ms <10 ms
Garbage Collection <20 ms 3 s
Table 60 Execution Times
Command ARAM (4 MBit) KM29LV040
PSB 4860
Functional Description
Semiconductor Group 79 10.97
2.3 Miscellaneous
Miscellaneous
Miscellaneous
2.3.1 Real Time Clock
The PSB 4860 supplies a real time clock which maintains time with a resolution of a
second and a range of up to a year. There are two registers which contain the current
time and date (table 61).
The real time clock maintains time during normal mode and power down mode only if the
auxiliary oscillator OSC is running and the RTC is enabled.
Note: Writing out-o f-range values to RTC1 and RTC2 resu lts in undefined ope ration of
the RTC
2.3.2 SPS Control Register
The two SPS outputs (SPS0, SPS1) can be used as either general purpose outputs,
speakerphone status outputs, extended address outputs for Voice Prompt EPROM or as
status register outputs. Table 62 shows the associated register.
When used as status register outputs, the status register bit at position POS appears at
SPS0 and the bit at position POS+1 appears at SPS1. This mode of operation can be
used for debugging purposes or direct polling of status register bits.
2.3.3 Reset and Power Down Mode
The PSB 4860 can be in either reset mode, pow er down mode or acti ve mode. During
reset the PSB 4860 clears the hardwa re configurat ion registers and st ops both in ternal
Table 61 Real Time Clock Registers
Register # of Bit s Name Comment
RTC1 6 SEC Seconds e lapsed
RTC1 6 MIN Minutes elapsed
RTC2 5 HR H ours elapsed
RTC2 11 DAY Days elapsed
Table 62 SPS Registers
SPSCTL 1 SP0 Output Value of SPS0
SPSCTL 1 SP1 Output Value of SPS1
SPSCTL 3 MODE Mode of Operation
SPSCTL 4 POS Position for status register window
PSB 4860
Functional Description
Semiconductor Group 80 10.97
and external activity. The address lines MA0-MA15 provide a weak low until they are
actually used as address lines (strong outputs) or auxiliary port pins (I/O). In reset mode
the hardware co nfiguration reg isters can be rea d and written. Wit h the first acces s to a
read/write register the PSB 4860 enters active mode. In this mode the main oscillator is
running and normal operation tak es pl ace . By s etti ng the powe r do wn bi t (PD ) t he PSB
4860 can be brought to power down mode.
In power down mode the main oscillator is stopped and, depending on
HWCONFI G2: PPM), the mem ory c ontro l lines are rele ase d (weak high). Dependin g on
the configuration (ARAM/DRAM, APP) the PSB 4860 may still generate external activity
(e.g. refresh cycles). The PSB 4860 enters active mode again upon an access to a read/
write register. Figure 40 shows a state chart of the modes of the PSB 4860.
Figure 40 Operation Modes - State Chart
2.3.4 Interrupt
The PSB 4860 can generate an interrupt to inform the host of an update of the STATUS
register according to table 64. An interrupt mask register (INTM) can be used to disable
or enable the interrupting capability of each bit of the STATUS register except ABT
individually.
Table 63 Power Down Bit
Register # of Bits Name Comment
CCTL 1 PD power down mode
Reset
Active
Mode Power Down
Mode
Mode
CCTL.PD=1
R/W reg. access
RST=1RST=1
R/W reg. ac c es s
PSB 4860
Functional Description
Semiconductor Group 81 10.97
An interrupt is internally generated if any combination of these events occurs and the
interrupt is not masked. The interrupt is cleared when the host reads the STATUS
register. If a new event occurs while the host reads the status register, the status register
is updated
after
the current access is terminated and a new interrupt is generated
immediately after the access has ended.
Note: If the inte rnal in terrupt oc curs after the con troll er h as already se lec ted the de vic e
but not yet read the STATUS word, then the STATUS word is updated and the
internal interrupt is cleared. Therefore the controller should always evaluate the
STATUS word when read.
2.3.5 Abort
If the PSB 4860 cannot continue the current operations in progress (e.g. due to a
transient lo ss of power) it stops operation and initializes all read/write registers to their
reset state. After that it sets the ABT bit of the STATUS register and generates an
interrupt. The PSB 4860 discards all comman ds wi th the excepti on of a write command
to the revision register while ABT is set. Only after the write command to the revision
register (with any value) the ABT bit is reset and a reinitialization can take place.
Table 64 Interrupt Source Summary
STATUS
(old) STATUS
(new) Set by Reset by
RDY=0 RDY=1 Command completed Command issued
CIA=0 CIA=1 New Caller ID byte available CIDCTL0 read
CD=0 CD=1 Carrier detected Carrier lost
CD=1 CD=0 Carrier lost Carrier detected
CPT=0 CPT=1 Call progress tone detected CPT lost
CPT=1 CPT=0 Call progress tone lost CPT detected
CNG=0 CNG=1 Fax calling tone detected CNG lost
DTV=0 DTV=1 DTMF tone detected DTMF tone lost
DTV=1 DTV=0 DTMF tone lost DTMF tone detected
ATV=0 ATV=1 Alert tone detected Alert tone lost
ATV=1 ATV=0 Alert tone lost Alert tone detected
BSY=1 BSY=0 File command completed New command issued
SD=0 SD=1 Speech activity detected Speech activity lost
SD=1 SD=0 Speech activity lost Speech activity detected
PSB 4860
Functional Description
Semiconductor Group 82 10.97
2.3.6 Revisi on Register
The PSB 4860 contains a revision register. This register is read only and does not
influence ope ration in any way. A write to the revis ion register clears the ABT bit of the
STATUS register but does not alter the content of the revision register.
2.3.7 Hardware Configuration
The PSB 4860 can be adapted to various external hardware configurations by four
special registers: HWCONFIG0 to HWCONFIG3. These registers are usually only
written once during initialization and must not be changed while the PSB 4860 is in active
mode. It is mandatory that the programmed configuration reflects the external hardware
for proper operation. Special care must be taken to avoid I/O conflicts or excess current
by enabling inputs without an external driving source. Table 65 can be used as a
checklist.
2.3.8 Frame Synchronization
The PSB 4860 locks itsel f to eith er an ex ternally suppli ed clo ck or fram e syn c signa l or
generates the frame sync signal itself. This internal reference frame sync signal is called
master frame sync (MFSC). In addition, the PSB 4860 can derive the AFECLK and
AFEFSC from either the main oscillator or an auxiliary clock input. Table 66 shows how
AFECLK and MFSC are derived by the PSB 4860. The bits ACS and MFS are contained
in the hardware configuration registers.
Table 65 Hardware Configuration Checklist
Register Name Value Check
HWCONFIG0 PFRDY 1 FRDY must not float
HWCONFIG0 OSC 1 OSC1/2 must be connected to a crystal
HWCONFIG0 ACS 1 CLK must not float (tie low if no clock present)
HWCONFIG1 MFS 1 FSC must not float (tie low if no clock present)
HWCONFIG1 ACT 1 FSC must not float (tie low if no clock present)
Table 66 Frame Synchronization Selection
ACS MFS AFECLK MFSC Application
0 0 XTAL AFEFSC Analog featurephone
0 1 - FSC ISDN stand-alone
1 0 CLK AFEFSC DECT
1 1 CLK FSC unused
PSB 4860
Functional Description
Semiconductor Group 83 10.97
2.3.9 Clock Tracking
The PSB 4860 can a djust AFECLK and AFEFSC dynamica lly to a sli ghtly varying FSC
if AFECLK and AFEFSC are derived from the main oscillator (XTAL). This mode requires
that both AFEFSC and FSC are nominally running at the same frequency (8 kHz).
This feature is especially useful when the FSC signal is not derived from the same clock
source as AFECLK (ISDN application).
2.3.10 Dependencies of Modules
There are some restrictions concerning the modules that can be enabled at the same
time (table 67). A chec ked cell in dicates that the two module s (defined by the row an d
the column of the cell) must not be enabled at the same time.
There are three classes of file commands denoted by the letters B, O and I. Table 68
shows the definition of these classes:
Examples:
• The line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder
is running at slow speed.
• If the DTMF detec tor is running, no ne of the backg round file comm ands (B) must be
executed. In addition, no file command must be executed with immediate execution
1) if Speech Decoder is running at slow speed
Table 67 Dependencies of Modules
Speech
Encoder Speech
Decoder Line EC
(24 ms) Acoustic
EC DTMF
Detector File
Command
Speech Enc. XXX B,O,I
Speech Dec. X X1) XB,O,I
Line EC (24 ms) X X1) XB,O
Acoustic EC X X X X B,O
DTMF Det. XB,I
File Cmd. B,O,I B,O,I B,O B,O B,I
Table 68 File Command Classes
Class Description
B Background commands (Activate, Recompress, Garbage Collection, Initialize)
O Open Commands (Open, Open Next Free File)
I Any command executed with EIE=1 (i.e. immediate execution)
PSB 4860
Functional Description
Semiconductor Group 84 10.97
enabled (I). However, files my be opened and other commands (like read or write)
may be executed without immediate execution enabled.
Furthermore it may be necessary to restrict the length of the FIR filter of the echo
cancellation unit if several other units are operating at the same time. The sum of all
weigh ts (table 69) of the simu ltaneously enabled modules must not exceed 100 at any
given time.
Example:
• For an analog phone echo cancellation, DTMF tone generation, caller ID reception,
and line echo cancellation are necessary. The system uses the PSB 4851 and the
equalizer to linearize the loudspeaker. In this case the sum of all weights without echo
cancellation is 35.6. Therefore 255 taps can be used for a total of 98.1.
• In an ISDN phone echo cancellation, channel 1 of the digital interface, the analog
interfa ce with clo ck tracking and the equal izer shall be enable d at the sam e time. In
1) The alert tone detector would add another 2.6, but can be disabled after the alert tone has been detected.
Therefore it can be left out of the ca lcu lat ion.
Table 69 Module Weights
Module Weight Comment Example 1 Example 2
Equalizer 2.8 X X
CPT Detector 5.6
Caller I D De coder1) 4.2 X
CNG Detector 2.6
DTMF Generator 2.2 X
Echo Cancellation 52.1 127 taps (16 ms)
Echo Cancellation 62.5 255 taps (32 ms) X
Echo Cancellation 72.9 383 taps (48 ms)
Echo Cancellation 83.3 511 taps (64 ms) X
Line Echo Cancellation 12.7 X
Universal Attenuator 0.2
Digital Interface 1.7 channel 1 or SSDI X
Digital Interface 1.7 channel 2
Analog Interface 2.5 X X
Clock Tracking 0.6 X
Miscellaneous 8.0 always active X X
PSB 4860
Functional Description
Semiconductor Group 85 10.97
this application the sum of all weights without echo cancellation is 15.6. Therefore 511
taps can be used for a total of 98.9.
PSB 4860
Functional Description
Semiconductor Group 86 10.97
2.4 Interfaces
Interfaces
Interfaces
This section describes the interfaces of the PSB 4860. The PSB 4860 supports both an
IOM®-2 interface with si ngle and do uble clock mode and a strobe d serial data interface
(SSDI). However, these two interfaces cannot be used simultaneously as they share
some pins. Both interfaces are for data transfer only and cannot be used for
programming the PSB 4860. Table 70 lists the features of the two alternative interfaces.
2.4.1 IOM®-2 Interface
The data s tream is partiti oned into pac kets called frames. Each f rame is divid ed into a
fixed number of timeslots. Each timeslot is used to transfer 8 bits. Figure 41 shows a
commonly used terminal mode (three channels ch0, ch1 and ch2 with four timeslots
each). The first timeslot (in fi gure 41: B1 ) i s de noted by number 0, the second one (B2)
by 1 and so on.
Figure 41 IOM®-2 Interface - Frame Structure
The signal FSC is used to indicate the start of a frame. Figure 42 shows as an example
two valid FSC-signals (FSC, FSC*) which both indicate the same clock cycle as the first
clock cycle of a new frame (T1).
Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However,
programming is not supported via the monitor channels.
Table 70 SSDI vs. IOM®-2 Interface
IOM®-2 SSDI
Signals 4 6
Channels (bidirectional) 2 1
Code linear PCM, A-law, µ-law linear PCM
Synchronization within frame by timeslot
(programmable) by signal
(DXST, DRST)
B1 M0B2
FSC
DD/DU
ch0ch1ch2
125 µs
CI0 IC1 M1IC2 CI1
PSB 4860
Functional Description
Semiconductor Group 87 10.97
Figure 42 IOM®-2 Interface - Fra me Start
The PSB 4860 supports both single clock mode and double clock mode. In single clock
mode, the bit rate is equal to the clock rate. Bits are shifted out with the rising edge of
DCL and s ampled at the fal ling edge . In dou ble cloc k mode, the clock runs at twice the
bit rate. Therefore for each bit there are two clock cycles. Bits are shifted out with the
rising edge of the first clock cycle and sampled with the falling edge of the second clock
cycl e. Figure 43 shows the ti ming for si ngl e c l oc k mod e a nd figure 44 sho ws th e t iming
for dou ble clo ck mod e.
Figure 43 IOM®-2 Interface - Single Clock Mode
DCL
FSC
FSC*
T1T2
DCL
T1T2
DD/DR
DU/DX bit 0 bit 1 bit 2
bit 0 bit 1 bit 2
PSB 4860
Functional Description
Semiconductor Group 88 10.97
Figure 44 IOM®-2 Interface - Double Clock Mode
The PSB 4860 supports up to two channels simultaneously for data transfer. Both the
coding (PC M or linear) an d the data dire ction (DD/ DU assignme nt for transmit/ receive)
can be programmed individually for each channel. Table 71 shows the registers used for
configuration of the IOM®-2 interface.
In A-law or µ-law mode, only 8 bits are transferred and therefore only one timeslot is
needed for a channel. In linear mode, 16 bits are needed for a single channel. In this
mode, two c ons ecutive t ime slo ts are use d for data transfer. Bits 8 to 1 5 a r e trans ferred
Table 71 IOM®-2 Interface Registers
Register # of Bits Name Comment
SDCONF 1 EN Interface enable
SDCONF 1 DCL Selection of clock mode
SDCONF 6 NTS Number of timeslots within frame
SDCHN1 1 EN Channel 1 enable
SDCHN1 6 TS First timeslot (channel 1)
SDCHN1 1 DD Data Direction (channel 1)
SDCHN1 1 PCM 8 bit code or 16 bit linear PCM (channel 1)
SDCHN1 1 PCD 8 bit code (A-law or µ-law, channel 1)
SDCHN2 1 EN Channel 2 enable
SDCHN2 6 TS First timeslot (channel 2)
SDCHN2 1 DD Data Direction (channel 2)
SDCHN2 1 PCM 8 bit code or 16 bit linear PCM (channel 2)
SDCHN2 1 PCD 8 bit code (A-law or µ-law, channel 2)
DCL
T1
DD/DR
DU/DX bit 0 bit 1 bit 2
bit 0 bit 1
T2T3T4T5
PSB 4860
Functional Description
Semiconductor Group 89 10.97
within the first timeslot and bits 0 to 7 are transferred within the next timeslot. The first
timeslot must have an even number. The most significant bit is always transmitted first.
PSB 4860
Functional Description
Semiconductor Group 90 10.97
2.4.2 SSDI Interface
The SSDI interface is intended for seamless connection to low-cost burst mode
controll ers (e .g. PM B 272 51) a nd s up ports a s ing le c han nel in each direction. The d ata
stream is partitioned into frames. Within each frame one 16 bit value can be sent and
received b y the PSB 4860 . The start of a frame i s indicate d by the ri sing edge of FSC.
Data is always sampled at the falling edge of DCL and shifted out with the rising edge of
DCL.
The SSDI transmitter and receiver are operating independently of each other except that
both use the same FSC and DCL signal.
2.4.2.1 SSDI Interface - Transmitter
The PSB 4860 indicates outgoing data (on signal DX) by activating DXST for 16 clocks.
The signal DXST is activated with the same rising edge of DCL that is used to send the
first bit (Bit 15) of the data. DXST is deactivated with the first rising edge of DCL after the
last bit has been transferred. The PSB 4860 drives the signal DX only when DXST is
activa ted. Figu re 45 shows the timing for the transmitter.
Figure 45 SSDI Interface - Transmitter Timing
2.4.2.2 SSDI Interface - Receiver
Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly
16 DCL cloc ks. As there may be more th an on e DRST pul ses wi thin a sing le fram e the
PSB 4860 can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In
order to detect the first pulse properly, DRST must not be active at the rising edge of
FSC. In figure 46 the PSB 4860 is listening to the third DRST pulse (n=3).
FSC
125 µs
DXST
DCL
DU/DX bit 15 bit 14 bit 1 bit 0
PSB 4860
Functional Description
Semiconductor Group 91 10.97
Figure 46 SSDI Interface - Active Pulse Selection
Figure 47 shows the timing for the SSDI receiver.
Figure 47 SSDI Interface - Receiver Timing
Table 72 shows the registers used for configuration of the SSDI interface.
Table 72 SSDI Interface Register
Register # of Bits Name Commen t
SDCHN1 4 NAS Number of active DRST strobe
FSC
DRST
active puls e (n=3)
FSC
125 µs
DRST
DCL
DD/DR bit 15 b it 14 bit 1 bit 0
PSB 4860
Functional Description
Semiconductor Group 92 10.97
2.4.3 Analog Front End Interface
The PSB 4860 uses a four wire interface similar to the IOM®-2 interface to exchange
information with the analog front end (PSB 4851). The main difference is that all
timeslots and the channel assignments are fixed as shown in figure 48.
.
Figure 48 Analog Front End Interface - Frame Structure
Voice data is transferred in 16 bit linear coding in two bidirectional channels C1 and C2.
An auxiliary channel C3 is used to transfer the current setting of the loudspeaker
amplifier ALS to the PSB 4860. The remaining bits are fixed to zero. In the other direction
C3 transfers an override value for ALS from the PSB 4860 to the PSB 4851. An additional
override bit OV determines if the currently transmitted value should override the
AOAR:LSC1) setting. The AOAR:LSC setting is not affe cted by C3:ALS override . Table
73 shows the source control of the gain for the ALS amplifier.
Furthermore the AFE interface can be enabled or disabled according to table 74.
1) See specif ic at ion of PSB 4851, aut om at ic ally s et by the PSB 4860 in loudhearing mode.
Table 73 Control of ALS Amplifier
AOPR:OVRE C3:OV Gain of ALS amplifier
0 - AOAR:LSC
1 0 AOAR:LSC
11C
3
:ALS
Table 74 Analog Front End Interface Register
Register # of Bits Name Comment
AFECTL 1 EN Interface enable
Channel C1Channel C3
Channel C2
AFEFS
AFEDD
125 µs
ALS
AFEDU unused
000OV
16 bit 16 bit 8 bit
PSB 4860
Functional Description
Semiconductor Group 93 10.97
Figure 49 Analog Front End Interface - Frame Start
Figure 49 shows the synchronization of a frame by AFEFS. The first clock of a new frame
(T1) is indicated by AFEFS switching from low to high before the falling edge of T1.
AFEFS may remain high during subsequent cycles up to T32.
Figure 50 Analog Front End Interface - Data Transfer
The dat a is shi fted out with th e rising e dge of AFEC LK and s ampled at the fal ling edg e
of AFECLK (figure 50). If AOPR:OVRE is not set, the channel C3 is not used by the PSB
4851. All values (C1, C2, C3:ALS) are transferred MSB first. The data clock (AFECLK)
rate is fixed at 6.912 MHz. Table 75 shows the clock cycles used for the three channels.
Table 75Analog Front End Interface Clock Cycles
Clock Cycles AFEDD (driven by PSB 4860) AFEDU (driven by PSB 4851)
T1-T16 C1 data C1 data
T17-T32 C2 data C2 data
T33-T40 C3 data C3 data
T41-T864 0 tristate
AFECLK
AFEFS
T1T2
AFECLK
T1T2
AFEDD
AFEDU bit 0 bit 1 bit 2
bit 0 bit 1 bit 2
PSB 4860
Functional Description
Semiconductor Group 94 10.97
2.4.4 Serial Control Interface
The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is
transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled by the PSB 4860 at the rising edge
of SCLK and shifted out at the falling edge of SCLK. Each access must be terminated by
a rising edge of CS. The accesses to the PSB 4860 can be divided into three classes:
1. Configuration Read/Write
2. Status/Data Read
3. Register Read/Write
If the PSB 4860 is in power down mode, a read access to the status register does not
deliver vali d data with th e exception of the R DY bit. After the statu s has been read the
access can be either terminated or extended to read data from the PSB 4860. A register
read/writ e access can only be pe rformed when the PSB 4 860 is ready. The RDY bit in
the status register provides this information.
Any access to the PSB 4860 starts with the transfer of 16 bits to the PSB 4860 over line
SDR. This first word specifies the access class, access type (read or write) and, if
necessary, the register accessed. If a configuration register is written, the first word also
includes the data and the access is terminated. Likewise, if a register read is issued, the
access i s terminated a fter the first word. All other a ccesses contin ue by the tra nsfer of
the status register from the PSB 4860 over line SDX. If a register (excluding
configur ation) is to b e written, the next 16 bits containing the data are tra nsferred over
line SDR and the access is terminated. Figures 51 to 54 show the t iming diagrams for
the different access classes and types to the PSB 4860.
Figure 51 Status Register Read Access
CS
SCLK
SDR c15 c14 c1c0
s15 s14 s1s0
SDX
c15,..,c0:
s15,..,s0:command word for sta tu s regis t er read :
status registe r :
INT
PSB 4860
Functional Description
Semiconductor Group 95 10.97
Figure 52 Data Read Access
Figure 53 Register Write Access
CS
SCLK
SDR c15 c14 c1c0
s15 s14 s1s0
SDX
c15,..,c0:
s15,..,s0:command word for dat a read:
status regis te r:
d15 d14 d1d0
d15,..,d0: data to be read:
CS
SCLK
SDR c15 c14 c1c0
s15 s14 s1s0
SDX
c15,..,c0:
s15,..,s0:command word for regis t er w rit e:
status regis te r:
d15 d14 d1d0
d15,..,d0: data to be written :
PSB 4860
Functional Description
Semiconductor Group 96 10.97
Figure 54 Configuration Register Read Access
Configuration registers at even adresses use bit positions d7-d0 while configuration
registers at odd adresses use bit positions d15-d8.
Figure 55 Configuration Register Write Access or Register Read Command
The internal interrupt signal is cleared when the first bit of the status register is put on
SDX. Ho wever, external ly the sign al INT i s deactivated as long as CS stays low. If the
internal interrupt signal is not cleared or another event causing an interrupt occurs while
the microcontroller is already reading the status belonging to the first event then INT
goes low again immediately after CS is removed. The timing is shown in figure 51. Table
76 shows the formats of the different command words. All other command words are
reserved.
CS
SCLK
SDR c15 c14 c1c0
SDX
c15,..,c0:
s15,..,s0:command word for conf iguration regis t er read:
status registe r :
d15,..,d0: d at a to be read :
s15 s14 s1s0d15 d14 d1d0
CS
SCLK
SDR c15 c14 c1c0
c15,..,c0: command word for configuration register write:
or register read:
PSB 4860
Functional Description
Semiconductor Group 97 10.97
In case of a configuration register write, W determines which configuration register is to
be written (table 77):
In case of a configuration register read, R determines which pair of configuration
registers is to be read (table 78):
Note: Reading any register except the status register or a hardware configuration
register requires at least two accesses. The first access is a register read
command (fig ure 55). With this a ccess the registe r address is transferre d to the.
After that access data read accesses (figure 52) must be executed. The first data
read access with STATUS:RDY=1 delivers the value of the register.
Table 76 Command Words for Register Access
1514131211109876543210
Read Status Register or
Data Read Access 0011000000000000
Read Register 0101 REG
Write Register 0100 REG
Read Conf iguration Re g. 011100R000000000
Write Configuration Reg . 011000 W DATA
Table 77 Address Field W for Configuration Register Write
9 8 Register
0 0 HWCONFIG 0
0 1 HWCONFIG 1
1 0 HWCONFIG 2
1 1 HWCONFIG 3
Table 78 Address Field R for Configuration Register Read
9 Regi ste r pai r
0 HWCONFIG 0 / HWCONFIG 1
1 HWCONFIG 2 / HWCONFIG 3
PSB 4860
Functional Description
Semiconductor Group 98 10.97
2.4.5 Memory Interface
The PSB 4860 supports eithe r Flash Memory or ARAM/DRAM as externa l memory for
storing messages. If ARAM/DRAM is used, an EPROM can be added optionally to
support read-only messages (e.g. voice prompts). Table 79 summarizes the different
configur atio ns sup porte d.
If ARAM/DRAM is used, the total amount of memory must be a power of two and all
devices must be of the same type. The pin FRDY must be tied high.
For flash devices, the PSB 4860 supports in-circuit programming of voice prompts by
releasing th e contro l lines during rese t and (op tionall y) power do wn. Ins tea d of ac tively
driving the lines FCS, FOE, FWE, FCLE and ALE these lines are pulled high by a weak
pullup during reset and (optionally) power down.
Table 79 Supported Memory Configurations
Mbit Type Bank 0 (D0-D3) Bank 1 (D4-D7) Comment
1 ARAM/DRAM 256kx4 -
2 ARAM/DRAM 256kx4 256kx4
4 ARAM/DRAM 1Mx4 -
4 ARAM/DRAM 512kx8
8 ARAM/DRAM 1Mx4 1Mx4
16 ARAM/DRAM 4Mx4 - 2k or 4k refresh
16 ARAM/DRAM 2Mx8 2k refresh
32 ARAM/DRAM 4Mx4 4Mx4 2k or 4k refresh
32 ARAM/DRAM 2x2Mx8 2k refresh
64 ARAM/DRAM 16Mx4 - 4k or 8k refresh
64 ARAM/DRAM 8Mx8 4k or 8k refresh
128 ARAM/DRAM 16Mx4 16Mx4 4k or 8k refresh
4-128 FLASH 512kx8 devices KM29N040
16-128 FLASH 2Mx8 devices KM29N16000
PSB 4860
Functional Description
Semiconductor Group 99 10.97
2.4.5.1 ARAM/DRAM Interface
The PSB 4860 supports up to two banks of memory which may be 4 bit or 8 bit wide
(Figure 56). If both banks are used they must be populated identically.
Figure 56 ARAM/DRAM Interface - Connection Diagram
MA0-MA15
MD0-MD3
RAS
CAS0
W
A0-A12
D0-D3
RAS
CAS
W
OE
MA0-MA15
MD0-MD3
RAS
CAS0
W
A0-A12
D0-D7
RAS
CAS
W
OE
single 4 bit bank single 8 bit bank
MA0-MA15
MD0-MD7
RAS
CAS0
W
A0-A12
D0-D3
RAS
CAS
W
OE
A0-A12
D0-D3
RAS
CAS
W
OE
MD4-MD7
CAS1
two 4 bit banks
MA0-MA15
MD0-MD7
RAS
CAS0
W
A0-A12
D0-D7
RAS
CAS
W
OE
A0-A12
D0-D7
RAS
CAS
W
OE
CAS1
two 8 bit banks
PSB 4860 PSB 4860
PSB 4860 PSB 4860
PSB 4860
Functional Description
Semiconductor Group 100 10.97
The PSB 4860 also supports different internal organizations of ARAM/DRAM chips.
Table 80 shows the necessary connections on the address bus.
The timing of the ARAM/DRAM interface is shown in figures 57 to 59. The timing is
derived form the internal memory clock MCLK* which runs at a quarter of the system
clock.
Figure 57 ARAM/DRAM Interface - Read Cycle Timing
1) see chip control register CCTL
Table 80 Address Line Usage (ARAM/DRAM Mode)
ARAM/DRAM CS91) MA0-MA8MA9MA10 MA11 MA12 MA13
256k x4 1 A0-A8
512k x8 1 A0-A8A9
1M x4 0 A0-A8A9
4M x4 (2k refresh) 0 A0-A8A9A10
4M x4 (4k refresh) 0 A0-A8A9A10 A11
2M x8 0 A0-A8A9A10
16M x4 (4k refresh) 0 A0-A8A9A10 A11
16M x4 (8k refresh) 0 A0-A8A9A10 A11 A12
8M x8 (4k refresh) 0 A0-A8A9A10 A11
8M x8 (8k refresh) 0 A0-A8A9A10 A11 A12
MCLK*
MA0-MA13
MD0-MD7
CAS0,CAS1
RAS
row addr. col. addr.
PSB 4860
Functional Description
Semiconductor Group 101 10.97
Figure 58 ARAM/DRAM Interface - Write Cycle Timing
Figure 59 ARAM/DRAM Interface - Refre sh Cycle Timing
The PSB 4860 ensures that RAS remains inactive for at least one MCLK*-cycle between
successive accesses.
The frequency at which refresh cycles are performed is shown in table 81.
1) as programmed by HWCONFIG2:RSEL
Table 81 Refresh Frequency Selection
Refresh frequency Comment
64 kHz Memory access (e.g. recording) in progress
8, 16, 32 or 64 kHz1) No memory access in progress or power-down
MCLK*
MA0-MA13
MD0-MD7
CAS0,CAS1
RAS
row addr. col. addr.
W
data out
MCLK*
CAS0,CAS1
RAS
PSB 4860
Functional Description
Semiconductor Group 102 10.97
2.4.5.2 EPROM Interface
The PSB 4860 supports an EPROM in parallel with ARAM/DRAM. This interface is
always 8 Bits wide and sup ports a maximum of 256 kB. Figure 60 shows a conn ection
diagram and figure 61 the timing. This interface supports read cycles only.
Figure 60 EPROM Interface - Connection Diagram
Figure 61 EPROM Interface - Read Cycle Timing
Note: In order to access more than 64 kB the pins SPS
0
and SPS
1
can be programmed
to provide the address lines A
16
and A
17
. In this mode A
16
and A
17
remain stable
during the whole read cycle. See the register SPSCTL for programming
information.
MA0-MA15
MD0-MD7
VPRD
A0-A15
D0-D7
CE
OE
PSB 4860
A16
A17
SPS1
SPS0
VPRD
MD0-MD7
MCLK*
MA0-MA15
PSB 4860
Functional Description
Semiconductor Group 103 10.97
2.4.5.3 Flash Memory Interface
The PSB 4860 h as specia l support fo r the KM29N040 a nd KM29N16000 or equivalent
devices. No external components are required for up to four KM29N040. Figure 62
shows the conn ection diagram for a single dev ice .
Figure 62 Flash Memory Interface - Connection Diagram
Table 82 shows the signals output during a device access on the MA-lines. The address
bits can used by an external dec oder. Up to fou r KM29N040 are supported di rectly by
the decoded select signals FCS0-FCS3.
Table 82 Address Line Usage (Samsung Mode)
MA11 MA10 MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0
FCS3FCS2FCS1FCS0A23 A22 A21 A20 A19 A18 A17 A16
D0-D7
CE
RE
WE
CLE
MD0-MD7
FCS
FOE
FWR
FCLE
ALE ALE
+5V
R/B
FRDY
WP
PSB 4860
PSB 4860
Functional Description
Semiconductor Group 104 10.97
Figure 63 shows an application with three KM29N040 devices.
Figure 63 Flash Memory Interface - Multiple Devices
An access to the Flash Memory can consist of several partial access cycles where only
the timing of the partial ac cess cy cles is defined but not the ti me betwe en two adjac ent
partial access cycles. The PSB 4860 performs three types of partial access cycles:
1. Command write
2. Address write
3. Data read/write
Table 83 shows the supported accesses and the corresponding partial access cycles.
Table 83 Flash Memory Command Summary
Access Command
write Address
write 1 Address
write 2 Address
write 3 # of Data
read/write Command
write
RESET FF - - - - -
STATUS READ 70 - - - 1 -
BLOCK ERASE 60 A8-A15 A16-A23 --D0
READ 00 A0-A7A8-A15 A16-A23 1-32 -
WRITE 80 A0-A7 A8-A15 A16-A23 1-32 10
D0-D7CE RE WE CLE
MD0-MD7
FOE
FWR
FRDY
ALE
ALE
+5V
R/B
FCLE
WP
D0-D7CE RE WE CLE ALER/B
WP
MA8
MA9
MA10
D0-D7CE RE WE CLE ALER/B
WP
PSB 4860
PSB 4860
Functional Description
Semiconductor Group 105 10.97
The timing for the partial access cycles is shown in figures 64 to 65. Note that both FCS
and MA0-MA15 remain stable between the first and the last partial access of a device
access.
Figure 64 Flash Memory Interface - Command Write
Figure 65 Flash Memory Interface - Address Write
As there i s no acc es s tha t sta rts or s top s w ith a n add ress wri te c ycl e (fig ure 65) FCS is
already low at the start of this cycle and also remains low.
MCLK*
MA0-MA11
MD0-MD7
FWR
FCS
FCLE
data out
MCLK*
MD0-MD7
FWR
ALE
data out
address latch cycle
t0t1t2t3
PSB 4860
Functional Description
Semiconductor Group 106 10.97
Figure 66 Flash Memory Interface - Data Write
As there is no access that starts or stops with a data write cycle (figure 66) FCS is
already low at the start of this cycle and also remains low.
Figure 67 Flash Memory Interface - Data Read
If the device access ends with a read cycle, the FCS-signals go inactive after t3 of the
last read cycle. The data is latched at the rising edge of FOE.
MCLK*
MD0-MD7
FWR
data out
write cycle
t0t1t2t3
MCLK*
MD0-MD7
FOE
data in
read cycle
t0t1t2t3
PSB 4860
Functional Description
Semiconductor Group 107 10.97
2.4.6 Auxiliary Parallel Port
The PSB 4860 provid es an auxi liary paral lel po rt if the m emory inte rf ace is in Sam sun g
mode and only one device is used. In this case the lines MA0 to M A15 are not needed for
the memory interface a nd can there fore be used for an auxil iary paralle l port. This p ort
has two modes: static mode and multiplex mode.
2.4.6.1 Static Mode
In st atic m ode al l pins o f the aux iliary parallel p ort inte rf ace ha ve id enti cal fu nctiona lity .
Any pin can be configu red as an out put or an input. Pins configu red as outp uts provid e
a static signal as programmed by the controller. Pins configured as inputs are monitoring
the si gnal continuou sly without lat ching. The c ontroller always reads the cu rrent value.
Table 84 shows the registers used for static mode.
2.4.6.2 Multiplex Mode
In multiplex mode, the PSB 4860 uses MA12-MA15 to distinguish four timeslots. Each
timeslot has a duration o f a pprox ima tely 2 ms . Th e time slots are sep arate d b y a g ap of
approxima tely 125 µs in which none of the signals at MA12-MA15 are active. The PSB
4860 multiplexes three more output registers to MA0-MA11 in timeslots 0, 1 and 2. In
timeslot 3 the direction of the pins can be programmed. For input pins, the signal is
latched at the falling edge of MA15. Table 85 shows the registers used for multiplex
mode.
This mode is useful for scanning keys or controlling seven segment LED displays.
Table 84 Static Mode Registers
Register # of bits Comment
DOUT3 16 Output signals (for pins configured as outputs)
DIN 16 Input signals (for pins configured as inputs)
DDIR 16 Pin direction
Table 85 Multiplex Mode Registers
Register # of bits Comment
DOUT0 12 Output signals on MA0-MA11 while MA15=1
DOUT1 12 Output signals on MA0-MA11 while MA14=1
DOUT2 12 Output signals on MA0-MA11 while MA13=1
DOUT3 12 Output signals (for pins configured as outputs) while MA12=1
DIN 12 Input signals (for pins configured as inputs) at falling edge of MA12
DDIR 12 Pin direction during MA12=1
PSB 4860
Functional Description
Semiconductor Group 108 10.97
Figure 68 shows the timing diagram for multiplex mode.
Figure 68 Auxiliary Parallel Port - Multiplex Mode
Note: In either mode the voltage at any pin (MA
0
to MA
15
) must not exceed V
DD.
2 ms
MA15
MA14
MA13
MA12
MA0-MA11 DOUT0 DOUT2DOUT1 DOUT0DIN/DOUT3
PSB 4860
Detailed Register Description
Semiconductor Group 109 10.97
3 Detailed Register Description
The PSB 4860 has a single status register (read only) and an array of data registers
(read/write). Th e purpose of the status regis ter is to inform the externa l microcontroller
of important status changes of the PSB 48 60 and to provi de a handshake mechanism
for data register reading or writing. If the PSB 4860 generates an interrupt, the status
register contains the reason of the interrupt.
3.1 Status Register
RDY Ready
0: The last command (if any) is still in progress.
1: The last command has been executed.
ABT Abort
0: No exception during operation
1: Some exception other than reset caused the PSB 4860 to abort any
operation currently in progress. The external microcontroller should
reinitialize the PSB 4860 to ensure proper operation. The ABT bit is
cleared by writing any value to register REV. No other command is
accepted by the PSB 4860 while ABT is set.
CIA Caller ID Available
0: No new data for caller ID
1: New caller ID byte available
CD Carrier Detect
0: No carrier detected
1: Carrier detected
1) undefined
15 0
RDY ABT 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV -1) -1) -1)
PSB 4860
Detailed Register Description
Semiconductor Group 110 10.97
CPT Call Progress Tone
0: Currently no call progress tone detected or pause detected (raw mode)
1: Currently a call progr ess is detected
CNG Fax Calling Tone
0: Currently no fax calling tone detected
1: Currently a fax calling tone is detected
SD Speech De tected
0: No speech detected
1: Speech signal at input of coder
ERR Error (File Command)
0: No error
1: Last file command resulted in an error
BSY Busy (File Command)
0: File system idle
1: File system still busy (also set d uring encoding /decodin g)
DTV DTMF Tone Valid
0: No new DTMF code available
1: New DTMF code available in DDCTL
ATV Ale rt Tone Valid
0: No new alert tone code available
1: New alert tone code available in ADCTL0
PSB 4860
Detailed Register Description
Semiconductor Group 111 10.97
3.2 Hardware Configuration Registers
HWCONFIG 0 - Hardware Configuration Register 0
PPSDX Push/Pull for SDX
0: The SDX pin has open-drain characteristic
1: The SDX pin has push/pull characteristic
PPINT Push/Pull for INT
0: The INT pin has open-drain characteristic
1: The INT pin has push/pull characteristic
PFRDY Pullup for FRDY
0: The internal pullup resistor of pin FRDY is enabled
1: The internal pullup resistor of FRDY is disabled
PPSDI Push/Pull for SDI interface
0: The DU and DD pins have open-drain characteristic
1: The DU and DD pins have push/pull characteristic
OSC Enable Auxiliary Oscillator
0: The auxiliary oscillator (OSC1, OS C2) is disabled
1: The auxiliary oscillator (OSC1, OS C2) is enabled
RTC Enable Real Time Clock
0: The real time clock is disabled
1: The real time clock (RTC) is enabled.
ACS AFE Clock Source
0: AFECLK is derived from the main oscillator
1: AFECLK is derived from the CLK input
PD Power Down (read only)
0: The PSB 4860 is in active mode
1: The PSB 4860 is in power down mode
7 0
PD ACS RTC OSC PPSDI PFRDY PPINT PPSDX
PSB 4860
Detailed Register Description
Semiconductor Group 112 10.97
HWCONFIG 1 - Hardware Configuration Register 1
APP Auxiliary Parallel Port
ACT AFE Clock Tracking
0: AFECLK tracking disabled
1: AFECLK tracking enabled
ADS AFE Double Speed
0: 8 kHz AFEFSC
1: 16 kHz AFEFSC
MFS Master Frame Sync Selection
0: AFEFSC
1: FSC
XTAL XTAL Frequency
SSDI SSDI Interface Selection
0: IOM®-2 Interface
1: SSDI Interface
1) The factor p is needed to calculate the clock frequency at AFECL K.
7 0
APP ACT ADS MFS XTAL SSDI
7 6 Description
0 0 normal (A RA M /DR AM, Intel type flash, v oic e prompt EPROM )
0 1 APP static m ode
1 0 APP multiplex mode
1 1 reserved
2 1 Factor p1) Description
0 0 reserved reserved
0 1 4.5 31.104 MHz
1 0 reserved reserved
1 1 reserved reserved
PSB 4860
Detailed Register Description
Semiconductor Group 113 10.97
HWCONFIG 2 - Hardware Configuration Register 2
PPM Push/Pull for Memory Interface (reset, power down)
0: The signals for the memory interface have push/pull characteristic
1: The signals for the memory interface have pullup/pulldown characteristic
ESDX Edge Select for DX
0: DX is transmitted with the rising edge of DCL
1: DX is transmitted with the falling edge of DCL
ESDR Edge Selec t for DR
0: DR is latched with the falling edge of DCL
1: DR is latched with the rising edge of DCL
CSEL Codec Selection for AFE interface
0: Interface to PSB 4851
1: Interface to AK 4510
CHS Channel Select (AK 4510 only)
RSEL Refresh Select
7 0
PPM ESDX ESDR CSEL CHS RSEL
3 2 Description
0 0 left cha nnel of AK 4510
0 1 right channel of AK4510
1 0 left and right channel
1 1 reserved
1 0 Description
0 0 64 kHz re fre sh fre quency
0 1 32 kHz re fre sh fre quency
1 0 16 kHz re fre sh fre quency
1 1 8 kHz refres h f requency
PSB 4860
Detailed Register Description
Semiconductor Group 114 10.97
HWCONFIG 3 - Hardware Configuration Register 3
7 0
00000000
PSB 4860
Detailed Register Description
Semiconductor Group 115 10.97
3.3 Read/Write Registers
The following sections contains all read/write registers of the PSB 4860. The register
addresses are given as hexadecimal values. Registers marked with an R are affected by
reset or a wak e up after p ower down . All other reg isters ret ain their p revious value. No
access must be made to addresses other than those associated with a read/write
register.
3.3.1 Register Table
Address. Name Long Name Page
00h REV Revision.............................................................................. 119
01h R CCTL Chip Control ....................................................................... 120
02h R INTM Interrupt Mask Register...................................................... 121
03h R AFEC TL Analog Front End Interface Control.................................... 122
04h R IFS1 Interface Select 1 ............................................................... 123
05h R IFG1 Interface Gain 1.................................................................. 124
06h R IFG2 Interface Gain 2.................................................................. 125
07h R IFS2 Interface Select 2 ............................................................... 126
08h R IFG3 Interface Gain 3.................................................................. 127
09h R IFG4 Interface Gain 4.................................................................. 128
0AhR SDCON F Serial Data Interface Configuration.................................... 129
0BhR SDCHN 1 Serial Data Interface Channel 1......................................... 130
0ChR IFS3 Interface Select 3 ............................................................... 132
0DhR SDCHN2 Serial Data Interface Channel 2......................................... 133
0EhR IFS4 Interface Select 4 ............................................................... 134
0FhR IFG5 Interface Gain 5.................................................................. 135
10h R UA Universal Attenuator........................................................... 136
11h R DGCTL DTMF Generator Control.................................................... 137
12h DGF1 DTMF Generator Frequency 1........................................... 138
13h DGF2 DTMF Generator Frequency 2........................................... 139
14h DGL DTMF Generator Level....................................................... 140
15h DGATT DTMF Generator Attenuation............................................. 141
16h R CNGCTL Call ing Tone Control .................... ....... .................... ...... ...... 142
17h CNGBT CNG Burst Time................................................................. 143
18h CNGLEV CNG Minimal Signal Level ................................................. 144
19h CNGRES CNG Signal Resolution ...................................................... 145
1AhR ATDCTL0 Alert Tone Detection 0........................................................ 146
1Bh ATDCTL1 Alert Tone Detection 1........................................................ 147
1ChR CIDCTL0 Caller ID Control 0.............................................................. 148
1Dh CIDCTL1 Caller ID Control 1.............................................................. 149
20h R CPTCTL Call Progress Tone Control................................................ 150
21h CPTTR Call Progress Tone Thresholds.......................................... 151
22h CPTMN CPT Minimum Times.......................................................... 152
PSB 4860
Detailed Register Description
Semiconductor Group 116 10.97
23h CPTMX CPT Maximum Times......................................................... 153
24h CPTDT CPT Delta Times................................................................ 154
25h R LECCTL Line Echo Cancellation Control.......................................... 155
26h LECLEV Minimal Signal Level for Line Echo Cancellation ............... 156
27h LECATT Externally Provid ed Attenu atio n................................... ...... 157
28h LECMGN Margin for Double Talk Detection....................................... 158
29h R DDCTL DTMF Detector Control...................................................... 159
2Ah DDTW DTMF Detector Signal Twist .............................................. 160
2Bh DDLEV DTMF Detector Minimum Signal Level............................... 161
2EhR FCFCTL Equalizer Control................................................................ 162
2Fh FCFCOF Equalizer Coefficient Data.................................................. 164
30h R SCCTL Speech Coder Control........................................................ 165
31h SCCT2 Speech Coder Control 2..................................................... 166
32h SCCT3 Speech Coder Control 3..................................................... 167
34h R SDCTL Speech Decoder Control.................................................... 168
38h R AGCCTL AGC Control....................................................................... 169
39h R AGCATT Automatic Gain Control Attenuation................................... 170
3Ah AGC1 Automatic Gain Control 1................................................... 171
3Bh AGC2 Automatic Gain Control 2................................................... 172
3Ch AGC3 Automatic Gain Control 3................................................... 173
3Dh AGC4 Automatic Gain Control 4................................................... 174
3Eh AGC5 Automatic Gain Control 5................................................... 175
40h R FCTL File Control......................................................................... 176
41h R FCMD File Command.................................................................... 177
42h R FDATA File Data............................................................................. 179
43h R FPTR File Pointer......................................................................... 180
47h R SPSCTL SPS Control........................................................................ 181
48h R RTC1 Real Time Clock 1.............................................................. 182
49h R RTC2 Real Time Clock 2.............................................................. 183
4AhR DOUT0 Data Out (Timeslot 0)......................................................... 184
4BhR DOUT1 Data Out (Timeslot 1)......................................................... 185
4ChR DOUT2 Data Out (Timeslot 2)......................................................... 186
4DhR DOUT3 Data Out (Timeslot 3 or Static Mode)................................. 187
4Eh DIN Data In (Timeslot 3 or Static Mode).................................... 188
4FhR DDIR Data Direction (Timeslot 3 or Static Mode) ........................ 189
60h R SCTL Speakerphone Control ....................................................... 190
62h R SSRC1 Speakerphone Source 1..................................................... 191
63h R SSRC2 Speakerphone Source 2..................................................... 192
64h SSDX1 Speech Detector (Transmit) 1............................................ 193
65h SSDX2 Speech Detector (Transmit) 2............................................ 194
66h SSDX3 Speech Detector (Transmit) 3............................................ 195
67h SSDX4 Speech Detector (Transmit) 4............................................ 196
68h SSDR1 Speech Detector (Receive) 1............................................. 197
PSB 4860
Detailed Register Description
Semiconductor Group 117 10.97
69h SSDR2 Speech Detector (Receive) 2............................................. 198
6Ah SSDR3 Speech Detector (Receive) 3............................................. 199
6Bh SSDR4 Speech Detector (Receive) 4............................................. 200
6Ch SSCAS1 Speech Comparator (Acoustic Side) 1............................... 201
6Dh SSCAS2 Speech Comparator (Acoustic Side) 2............................... 202
6Eh SSCAS3 Speech Comparator (Acoustic Side) 3............................... 203
6Fh SSCLS1 Speech Comparator (Line Side) 1...................................... 204
70h SSCLS2 Speech Comparator (Line Side) 2...................................... 205
71h SSCLS3 Speech Comparator (Line Side) 3...................................... 206
72h SATT1 Attenuation Unit 1............................................................... 207
73h SATT2 Attenuation Unit 2............................................................... 208
74h SAGX1 Automatic Gain Control (Transmit) 1.................................. 209
75h SAGX2 Automatic Gain Control (Transmit) 2.................................. 210
76h SAGX3 Automatic Gain Control (Transmit) 3.................................. 211
77h SAGX4 Automatic Gain Control (Transmit) 4.................................. 212
78h SAGX5 Automatic Gain Control (Transmit) 5.................................. 213
79h SAGR1 Automatic Gain Control (Receive) 1................................... 214
7Ah SAGR2 Automatic Gain Control (Receive) 2................................... 215
7Bh SAGR3 Automatic Gain Control (Receive) 3................................... 216
7Ch SAGR4 Automatic Gain Control (Receive) 4................................... 217
7Dh SAGR5 Automatic Gain Control (Receive) 5................................... 218
7Eh SLGA Line Gain............................................................................ 219
80h SAELEN Acoustic Echo Cancellation Length.................................... 220
81h SAEATT Acoustic Echo Cancellation Double Talk Attenuation ........ 221
82h SAEGS Acoustic Echo Cancellation Global Scale .......................... 222
83h SAEPS1 Acoustic Echo Cancellation Partial Scale........................... 223
84h SAEPS2 Acoustic Echo Cancellation First Block.............................. 224
Note: Registers CCTL, FCTL, FCMD, FDATA, FPTR, RTC1, RTC2, DOUT0, DOUT1,
DOUT2, DOUT3 and DDIR are only affected by reset, not by wakeup. For register
SPSCTL see the register description for the exact behaviour.
3.3.2 Register Naming Conventions
Several registers cont ain one or more fi elds for inpu t signal se lectio n. All fields labelled
I1 (I2, I3) are five bits wide and use the same coding as shown in table 86.
Table 86 Signal Encoding
4 3 2 1 0 Signal Description
00000S
0Silence
00001S
1Analog line input (channel 1 of PSB 4851 interface)
PSB 4860
Detailed Register Description
Semiconductor Group 118 10.97
00010S
2Analog line output (channel 1 of PSB 4851 interface)
00011S
3Microphone input (channel 2 of PSB 4851 interface)
00100S
4Loudspeaker/Handset output (channel 2 of PSB
4851 interface)
00101S
5Serial interface input, channel 1
00110S
6Serial interface output, channel 1
00111S
7Serial interface input, channel 2
01000S
8Serial interface output, channel 2
01001S
9DTMF generator output
01010S
10 DTMF generator auxiliary output
01011S
11 Speakerphone output (acoustic side)
01100S
12 Speakerphone output (line side)
01101S
13 Speech decoder output
01110S
14 Universal attenuator output
01111S
15 Line echo canceller output
10000S
16 AGC unit output (after AGC)
10001S
17 AGC unit output (before AGC)
10010S
18 Equalizer output
10011 reserved
1 0 1 - - reserved
1 1 - - - reserved
Table 86 Signal Encoding
4 3 2 1 0 Signal Description
PSB 4860
Detailed Register Description
Semiconductor Group 119 10.97
00hREV Revision
The revision register can only be read. For the PSB 4860, V2.1, all bits except bit 12 are
zero.
Note: A write access to the revision register does not alter its content. It does, however,
reset the ABT bit of the STATUS register.
15 0
0001000000000000
PSB 4860
Detailed Register Description
Semiconductor Group 120 10.97
01hRCCTL Chip Control
MV Voice Prompt Directory
0: not available
1: available (within EPROM or Flash)
PD Power Down
0: PSB 4860 is in active mode
1: enter power-down mode
MQ Memory Quality
0: ARAM
1: DRAM
MT Memory Type
CS9 CAS selection
0: other memory
1: 256kx4 or 512kx8 memory
SAS Split Address Space
0: other ARAM/DRAM
1: two 2Mx8 devices
15 0
0000MV00PD000MQ MT CS9SAS
Reset Value
0000000000000000
3 2 Description
0 0 ARAM/DRAM
1 1 Samsung flash memory
PSB 4860
Detailed Register Description
Semiconductor Group 121 10.97
02hRINTM Interrupt Mask Register
If a bit of this register is reset (set to 0), the corresponding bit of the status register does
not generate an interrupt.
If a bit is s et (set to 1), an ex ternal interrup t can be gene rated by th e corresp onding bit
of the status register.
15 0
RDY 1 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV 0 0 0
Reset Value
0100000000000000
PSB 4860
Detailed Register Description
Semiconductor Group 122 10.97
03hRAFECTL Analog Front End Interface Control
ALS Loudspeaker Amplification
This value is tran sferre d on ch ann el C3 of the AFE inte rface. If the PSB 48 51 is used it
represents the amplification of the loudspeaker amplifier.
EN Interface Enable
0: AFE interface disabled
1: AFE interface enabled
15 0
0000 ALS 0000000EN
Reset Value
0000 0 00000000
PSB 4860
Detailed Register Description
Semiconductor Group 123 10.97
04hRIFS1 Interface Select 1
The signal selection fields I1, I2 and I3 of IFS1 determine the outgoing signal of channel
1 of the analog interface. For the PSB 4851 this is usually the line out signal.
The HP bit enables a high-pass for the incoming signal of channel 1 of the analog
interface. For the PSB 4851 this is usually the line in signal.
HP High-Pass for S1
0: Disabled
1: Enabled
I1 Input signal 1 for IG2
I2 Input signal 2 for IG2
I3 Input signal 3 for IG2
Note: As all sources are always active, unused sources must be set to 0 (S
0
).
15 0
HP I1 I2 I3
Reset Value
00 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 124 10.97
05hRIFG1 Interface Gain 1
IFG1 is associated with the incoming signal of channel 1 of the analog interface. For the
PSB 4851 this is usually the line in signal.
IG1
In order to obtain a gain
G
the parameter IG1 can be calculated by the following formula:
15 0
0IG1
Reset Value
0 8192 (0 dB)
IG1 32768 G 12.04 dB–()20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 125 10.97
06hRIFG2 Interface Gain 2
IFG2 is associated with the outgoing signal of channel 1 of the analog interface. For the
PSB 4851 this is usually the line out signal.
IG2 Gain of Amplifier IG2
In order to obtain a gain
G
the parameter IG2 can be calculated by the following formula:
15 0
0IG2
Reset Value
0 8192 (0 dB )
IG2 32768 G 12.04 dB–()20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 126 10.97
07hRIFS2 Interface Select 2
The signal selection fields I1, I2 and I3 of IFS2 determine the outgoing signal of channel
2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal.
The HP bit enables a high-pass for the incoming signal of channel 2 of the analog
interface. For the PSB 4851 this is usually the microphone signal.
HP High-Pass for S3
0: Disabled
1: Enabled
I1 Input signal 1 for IG4
I2 Input signal 2 for IG4
I3 Input signal 3 for IG4
Note: As all sources are always active, unused sources must be set to 0 (S
0
).
15 0
HP I1 I2 I3
Reset Value
00 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 127 10.97
08hRIFG3 Interface Gain 3
IFG3 is associated with the incoming signal of channel 2 of the analog interface. For the
PSB 4851 this is usually the microphone signal.
IG3 Gain of Amplifier IG3
In order to obtain a gain
G
the parameter IG3 can be calculated by the following formula:
15 0
0IG3
Reset Value
0 8192 (0 dB)
IG3 32768 G 12.04 dB–()20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 128 10.97
09hRIFG4 Interface Gain 4
IFG4 is associated with the outgoing signal of channel 2 of the analog interface. For the
PSB 4851 this is usually the loudspeaker signal.
IG4 Gain of Amplifier IG4
In order to obtain a gain
G
the parameter IG4 can be calculated by the following formula:
15 0
0IG4
Reset Value
0 8192 (0 dB)
IG4 32768 G 12.04 dB–()20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 129 10.97
0AhRSDCONF Serial Data Interface Configuration
NTS Number of Timeslots
DCL Double Clock Mode
0: Single Clock Mode
1: Double Clock Mode
EN Enable Interface
0: Interface is disabled (both channels)
1: Interface is enabled (depending on separate channel enable bits)
15 0
00 NTS 00000DCL0EN
Reset Value
00 0 00000000
13 12 11 10 9 8 Description
0000001
0000012
... ... ... ... ... ... ...
11111164
PSB 4860
Detailed Register Description
Semiconductor Group 130 10.97
0BhRSDCHN1 Serial Data Interface Channel 1
NAS Number of active DRST strobe (SSDI interface mode)
PCD PCM Code
0: A-law
1: µ-law
EN Enable Interface
0: Interface is disabled
1: Interface is enabled if SDCONF:EN=1
PCM PCM Mode
0: 16 Bit Linear Coding (two timeslots)
1: 8 Bit PCM Coding (one timeslot)
DD Data Direction
0: DD: Data Downstream, DU: Data Upstream
1: DD: Data Upstream, DU: Data Downstream
TS Timeslot for Channel 1
15 0
NAS 0 0 PCD EN PCM DD TS
Reset Value
0 000000 0
15 14 13 12 Description
00001
... ... ... ... ...
111116
543210Description
0000000
... ... ... ... ... ... ...
11111163
PSB 4860
Detailed Register Description
Semiconductor Group 131 10.97
Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used.
Only even timeslots are allowed in this case.
PSB 4860
Detailed Register Description
Semiconductor Group 132 10.97
0ChRIFS3 Interface Select 3
The signal selection fields I1, I2 and I3 of IFS3 determine the outgoing signal of channel
1 of the IOM/SSDI-interface.
The HP bit enables a high-pass for the incoming signal of channel 1 of the analog IOM/
SSDI-interface.
HP High-Pass for S6
0: Disabled
1: Enabled
I1 Input signal 1 for S5
I2 Input signal 2 for S5
I3 Input signal 3 for S5
Note: As all sources are always active, unused sources must be set to 0 (S
0
).
15 0
HP I1 I2 I3
Reset Value
00 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 133 10.97
0DhRSDCHN2 Serial Data Interface Channel 2
PCD PCM Code
0: A-law
1: µ-law
EN Enable Interface
0: Interface is disabled
1: Interface is enabled if SDCONF:EN=1
PCM PCM Mode
0: 16 Bit Linear Coding (two timeslots)
1: 8 Bit PCM Coding (one timeslot)
DD Data Direction
0: DD: Data Downstream, DU: Data Upstream
1: DD: Data Upstream, DD: Data Downstream
TS Timeslot for Channel 2
Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used.
Only even timeslots are allowed in this case.
15 0
000000PCDENPCMDD TS
Reset Value
0000000000 0
5 4 3 2 1 0 Description
0000000
0000011
... ... ... ... ... ... ...
11111163
PSB 4860
Detailed Register Description
Semiconductor Group 134 10.97
0EhRIFS4 Interface Select 4
The signal selection fields I1, I2 and I3 of IFS4 determine the outgoing signal of channel
2 of the IO M/SSDI-in terface. The HP bit ena bles a high-p ass fo r the incoming si gnal of
channel 2.
HP High-Pass for S7
0: Disabled
1: Enabled
I1 Input signal 1 for S8
I2 Input signal 2 for S8
I3 Input signal 3 for S8
As all sources are always active, unused sources must be set to 0 (S
0
).
15 0
HP I1 I2 I3
Reset Value
00 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 135 10.97
0FhRIFG5 Interface Gain 5
ATT1 Attenuation for I3 (Channel 1)
In order to obtain an attenuation
A
the parameter ATT1 can be calculated by the
following formula:
ATT2 Attenuation for I3 (Channel 2)
In order to obtain an attenuation
A
the parameter ATT2 can be calculated by the
following formula:
15 0
ATT1 ATT2
Reset Value
255 (0 dB ) 255 (0 d B)
ATT1 256 A20dB⁄
×10=
ATT2 256 A20dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 136 10.97
10hRUA Universal Attenuator
ATT Attenuation for UA
For a given attenuation
A
[dB] the parameter ATT can be calculated by the following
formula:
I1 Input Selection for UA
15 0
ATT 000 I1
Reset Value
0 (-100 dB ) 0 0 0 0
ATT 256 A20dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 137 10.97
11hRDGCTL DTMF Generator Control
EN Generator Enable
0: Disabled
1: Enabled
MD Mode
0: raw
1: cooked
DTC Dial Tone Code (cooked mode)
15 0
ENMD0000000000 DTC
Reset Value
000000000000 0
3 2 1 0 Digit Frequency
0 0 0 0 1 697/1209
0 0 0 1 2 697/1336
0 0 1 0 3 697/1477
0 0 1 1 A 697/1633
0 1 0 0 4 770/1209
0 1 0 1 5 770/1336
0 1 1 0 6 770/1477
0 1 1 1 B 770/1633
1 0 0 0 7 852/1209
1 0 0 1 8 852/1336
1 0 1 0 9 852/1477
1 0 1 1 C 852/1633
1 1 0 0 * 941/1209
1 1 0 1 0 941/1336
1 1 1 0 # 941/1477
1 1 1 1 D 941/1633
PSB 4860
Detailed Register Description
Semiconductor Group 138 10.97
12hDGF1 DTMF Generator Frequency 1
FRQ Frequency of Generator 1
The parameter FRQ for a given frequency
f
[Hz] can be calculated by the following
formula:
15 0
0 FRQ
FRQ 32768 f
4000Hz
-------------------
×=
PSB 4860
Detailed Register Description
Semiconductor Group 139 10.97
13hDGF2 DTMF Generator Frequency 2
FRQ Frequency of Generator 2
he parameter FRQ for a given frequency
f
[Hz] can be calculated by the following
formula:
15 0
0FRQ
FRQ 32768 f
4000Hz
-------------------
×=
PSB 4860
Detailed Register Description
Semiconductor Group 140 10.97
14hDGL DTMF Generator Level
LEV2 Signal Level of Generator 2
In order to obtain a s ignal leve l
L
(relati ve to the PC M maximum value) for g enerator 2
the value of LEV2 can be calculated according to the following formula:
LEV1 Signal Level of Generator 1
In order to obtain a s ignal leve l
L
(relati ve to the PC M maximum value) for g enerator 1
the value of LEV1 can be calculated according to the following formula:
15 0
0 LEV2 0 LEV1
LEV2 128 L20dB⁄
×10=
LEV1 128 L20dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 141 10.97
15hDGATT DTMF Generator Attenuation
ATT2 Attenuation of Signal S10
In order to obtain attenuation
A
the parameter ATT2 can be calculated by the formula:
ATT1 Attenuation of Signal S9
In order to obtain attenuation
A
the parameter ATT1 can be calculated by the formula:
15 0
ATT2 ATT1
ATT2 128 1024 A20dB⁄
×10+A181dB,>;
128 A20dB⁄
×10 A 18 1 dB,<;
=
ATT1 128 1024 A20dB⁄
×10+A181dB,>;
128 A20dB⁄
×10 A 18 1 dB,<;
=
PSB 4860
Detailed Register Description
Semiconductor Group 142 10.97
16hRCNGCTL Calling Tone Control
EN Enable
0: CNG unit disabled
1: CNG unit enabled
I1 Input Selection for Calling Tone Detector
15 0
EN0000000000 I1
Reset Value
00000000000 0
PSB 4860
Detailed Register Description
Semiconductor Group 143 10.97
17hCNGBT CNG Burst Time
TIME Minimum Time for Calling Tone
In order to obtain the parameter TIME for a minimum time
t
the f ol lowi ng f orm ula can be
used:
15 0
0 TIME
TIME t 0.125 ms⁄=
PSB 4860
Detailed Register Description
Semiconductor Group 144 10.97
18hCNGLEV CNG Minimal Signal Level
MIN Minimum Signal Level for Calling Tone
In order to obtain the pa ramet er MIN for a mini mum signa l level
L
the following form ula
can be used:
15 0
00 MIN
MIN 16384 L20dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 145 10.97
19hCNGRES CNG Signal Resolution
RES Signal Resolution
The parameter RES depends on the noise level
L
as follows:
15 0
1111 RES
RES 4096–L20dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 146 10.97
1AhRATDCTL0 Alert Tone Detection 0
EN Enable alert tone detection
0: The alert tone detection is disabled
1: The alert tone detection is enabled
I1 Input signal selection
ATC Alert Tone Code
1) undefined
15 0
EN00 I1 000000 ATC
Reset Value
000 0 000000 -
1)
1 0 Description
0 0 no tone
0 1 2130
1 0 2750
1 1 2130/2750
PSB 4860
Detailed Register Description
Semiconductor Group 147 10.97
1BhATDCTL1 Alert Tone Detection 1
MD Alert tone detection mode
0: Only dual tones will be detected
1: Either dual or single tones will be detected
DEV Maximum frequency deviation for alert tone
0: 0.5%
1: 1.1%
MIN Minimum level of alert tone signal
For a minimum signal level
min
the parameter MIN is given by the following formula:
15 0
MD00DEV0000 MIN
MIN 2560 min 20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 148 10.97
1ChRCIDCTL0 Caller ID Control 0
EN CID Enable
0: Disabled
1: Enabled
I1 Input signal selection
DATA Last received data byte
15 0
EN 0 0 I1 DATA
Reset Value
000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 149 10.97
1DhCIDCTL1 Caller ID Control 1
NMB Minimum Number of Mark Bits
NMSS Minimum Number of Mark/Space Sequences
MIN Minimum Signal Level for CID Decoder
For a minimum signal level
min
the parameter MIN is given by the following formula:
15 0
NMB NMSS MIN
15 14 13 12 11 10 Description
0000000
000 110
... ... ... ... ... ... ...
111111630
9 8 7 6 5 Description
000001
0000111
... ... ... ... ...
11111311
MIN 640 min 20 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 150 10.97
20hRCPTCTL Call Progress Tone Control
EN CPT Detector Enable
0: Disabled
1: Enabled
MD CPT Mode
0: raw
1: cooked
I1 Input signal selection
15 0
ENMD000000000 I1
Reset Value
00000000000 0
PSB 4860
Detailed Register Description
Semiconductor Group 151 10.97
21hCPTTR Call Progress Tone Thresholds
NUM Number of Cycles
SN Minimal Signal-to-Noise Ratio
MIN Minimum Signal Level for CPT Detector
15 0
NUM 0 SN MIN
15 14 13 cooked mode raw mode
0 0 0 reserved 0
0 0 1 2 reserved
... ... ... ... reserved
1 1 1 8 reserved
11 10 9 8 Description
11119dB
100012dB
010015dB
001018dB
000022dB
Value Description
89h-40 dB
85h-42 dB
80h-44 dB
9Ah-46 dB
95h-48 dB
90h-50 dB
PSB 4860
Detailed Register Description
Semiconductor Group 152 10.97
22hCPTMN CPT Minimum Times
MINB Minimum Time for CPT Burst
The paramet er MINB for a min imal burst time
TBmin
can be ca lcu lated by the foll ow ing
formula:
MING Minimum Time for CPT Gap
The parameter MING for a minimal burst time
TGmin
can be calculated by the following
formula:
15 0
MINB MING
MINB TBmin 32 ms–
4
--------------------------------------=
MING TGmin 32 ms–
4
--------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 153 10.97
23hCPTMX CPT Maximum Times
MAXB Maximum Time for CPT Burst
The parameter MAXB for a maximal burst time of
TBmax
can be calculated by the
following formula:
MAXG Maximum Time for CPT Gap
The parameter MAXG for a maximal burst time of
TGmax
can be calculated by the
following formula:
15 0
MAXB MAXG
MAXB TBmax TBmin–
8
-----------------------------------------=
MAXG TGmax TGmin–
8
------------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 154 10.97
24hCPTDT CPT Delta Times
DIFB Maximum Time Difference between consecutive Bursts
The parameter DIFB for a maximal difference of
t
ms of two burst durations can be
calculated by the following formula:
DIFG Maximum Time Difference between consecutive Gaps
The parameter DIFG for a maximal difference of
t
ms of two gap durations can be
calculated by the following formula:
15 0
DIFB DIFG
DIFB t
2ms
-----------=
DIFG t
2ms
-----------=
PSB 4860
Detailed Register Description
Semiconductor Group 155 10.97
25hRLECCTL Line Echo Cancellation Control
EN Enable
0: Disabled
1: Enabled
MD Mode
0: Normal
1: Extended
I1 Input signal selection for I1
I2 Input signal selection for I2
15 0
ENMD0000 I1 I2
Reset Value
000000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 156 10.97
26hLECLEV Minimal Signal Level for Line Echo Cancellation
MIN
The pa ramet er MIN for a mi nimal signa l l evel
L
(d B) can be c alculat ed by th e foll owing
formula:
15 0
0MIN
MIN 512 96.3 L+()×
5log2×
----------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 157 10.97
27hLECATT Externally Provided Attenuation
ATT
The parame ter ATT for an extern ally provided attenuation
A
(dB)
can be calculated by
the following formula:
15 0
0ATT
ATT 512 A×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 158 10.97
28hLECMGN Margin for Double Talk Detection
MGN
The parameter MGN for a margin of
L
(dB) can be calculated by the following formula:
15 0
0MGN
MGN 512 L×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 159 10.97
29hRDDCTL DTMF Detector Control
EN Enable DTMF tone detection
0: The DTMF detection is disabled
1: The DTMF detection is enabled
I1 Input signal selection
DTC DTMF Tone Code
1) undefined
15 0
EN00 I1 000 DTC
Reset Value
0000000-
1)
4 3 2 1 0 Frequency Digit
1 0 0 0 0 941 / 1633 D
1 0 0 0 1 697 / 1209 1
1 0 0 1 0 697 / 1336 2
1 0 0 1 1 697 / 1477 3
1 0 1 0 0 770 / 1209 4
1 0 1 0 1 770 / 1336 5
1 0 1 1 0 770 / 1477 6
1 0 1 1 1 852 / 1209 7
1 1 0 0 0 852 / 1336 8
1 1 0 0 1 852 / 1477 9
1 1 0 1 0 941 / 1336 0
1 1 0 1 1 941 / 1209 *
1 1 1 0 0 941 / 1477 #
1 1 1 0 1 697 / 1633 A
1 1 1 1 0 770 / 1633 B
1 1 1 1 1 852 / 1633 C
PSB 4860
Detailed Register Description
Semiconductor Group 160 10.97
2AhDDTW DTMF Detector Signal Twist
TWIST Signal twist for DTMF tone
In order to obtain a minimal signal twist
T
the parameter TWIST can be calculated by the
following formula:
Note: TWIST must be in the range [4096,20480]
15 0
0TWIST
TWIST 32768 0.5 dB T–()10 dB⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 161 10.97
2BhDDLEV DTMF Detector Minimum Sign al Level
MIN Minimum Signal Level
Note: Values outside the given range are reserved and must not be used.
15 0
1111111111 MIN
5 4 3 2 1 0 Description
001110 -50dB
001111 -49dB
... ... ... ... ... ... ...
100001 -31dB
100010 -30dB
PSB 4860
Detailed Register Description
Semiconductor Group 162 10.97
2EhRFCFCTL Equalizer Control
EN Enable equalizer
0: The equalizer is disabled
1: The equalizer is enabled
ADR Coefficient address
15 0
EN0 ADR 000 I
Reset Value
00 0 000 0
13 12 11 10 9 8 Coefficient
000000 A1
000001 A2
000010 A3
000011 A4
000100 A5
000101 A6
000110 A7
000111 A8
001000 A9
001001 B2
001010 B3
001011 B4
001100 B5
001101 B6
001 110 B7
001111 B8
010000 B9
010001 C1
010010 D1
010011 D2
010100 D3
010101 D4
01 0110 D5
PSB 4860
Detailed Register Description
Semiconductor Group 163 10.97
I1 Input signal selection
010111 D6
011000 D7
011001 D8
011010 D9
011011 D10
011100 D11
011101 D12
01 1 110 D13
011111 D14
100000 D15
100001 D16
100010 D17
100011 C2
13 12 11 10 9 8 Coefficient
PSB 4860
Detailed Register Description
Semiconductor Group 164 10.97
2FhFCFCOF Equalizer Coefficient Data
V Coefficient value
For the coefficient A1-A9, B2-B9 and D1-D17 the following formula can be used to
calculate V for a coefficient
c
:
For the coefficients C1 and C2 the following formula can be used to calculate V for a
coefficient
c
:
15 0
V
V 32768 c×=; -1c1<≤
V128c×= ; 1 c 256<≤
PSB 4860
Detailed Register Description
Semiconductor Group 165 10.97
30hRSCCTL Speech Coder Control
EN Enable
0: Disabled
1: Enabled
HQ High Quality Mode
0: Long Play Mode
1: High Quality Mode
VC Voice Controlled Start of Recording
0: Disabled
1: Enabled
I1 Input signal selection (first input)
I2 Input signal selection (second input)
15 0
EN HQ VC 0 0 0 I1 I2
Reset Value
000000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 166 10.97
31hSCCT2 Speech Coder Control 2
TIME
The parameter TIME for a time
t
([ms]) can be calculated by the following formula:
MIN
The parameter MIN for a signal level
L
([dB]) can be calculated by the following formula:
15 0
TIME MIN
TIME t
32
------=
MIN 16384
L
20
------
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 167 10.97
32hSCCT3 Speech Coder Control 3
LP
The parameter LP for a time constant of
t
([ms]) can be calculated by the following
formula:
15 0
0 LP 00000000
LP 256
t
---------=
PSB 4860
Detailed Register Description
Semiconductor Group 168 10.97
34hRSDCTL Speech Decoder Control
EN Enable
0: Disabled
1: Enabled
SPEED Playback Speed
15 0
EN000000000000 SPEED
Reset Value
00000000000000 0
1 0 Description
0 0 normal speed
0 1 0.5 times norm al speed
1 0 1.5 times norm al speed
1 1 2.0 times norm al speed
PSB 4860
Detailed Register Description
Semiconductor Group 169 10.97
38hRAGCCTL AGC Control
EN Enable
0: Disabled
1: Enabled
I1 Input signal selection for I1
I2 Input signal selection for I2
15 0
EN00000 I1 I2
Reset Value
000000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 170 10.97
39hRAGCATT Automatic Gain Control Attenuation
ATT
The parameter ATT for an attenuation
A
([dB]) can be calculated by the following
formula:
15 0
ATT
Reset Value
0 (-100 dB )
ATT 32768
A
20
------
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 171 10.97
3AhAGC1 Automatic Gain Control 1
COM
The parameter COM for a signal level
L
([dB]) can be calculated by the following formula:
AG_INIT
In order to obtain an initial gain
G
([db]) the parameter AG_INIT can be calculated by the
following formula:
15 0
COM AG_INIT
COM 128 10+ L6622,+
20
------------------------- L -42,14 dB<;
10L4214,+
20
------------------------- L -42,14 dB>;
=
AG_INIT 128 10+ G1806,+
20
------------------------- G 6 02 dB,<;
10G602,–
20
---------------------- G 6 02 dB,>;
=
PSB 4860
Detailed Register Description
Semiconductor Group 172 10.97
3BhAGC2 Automatic Gain Control 2
SPEEDL
The parameter SPEEDL for a multiplication factor
M
is given by the following formula:
SPEEDH
The parameter SPEEDH for a multiplication factor
M
is given by the following formula:
15 0
SPEEDL SPEEDH
SPEEDL M
8192
------------=
SPEEDH M
256
---------=
PSB 4860
Detailed Register Description
Semiconductor Group 173 10.97
3ChAGC3 Automatic Gain Control 3
MIN
The parameter MIN for a gain
G
([dB]) can be calculated by the following formula:
MAX
The parameter MAX for an attenuation
A
([dB]) can be calculated by the following
formula:
15 0
MIN MAX
MIN 128 10+ G1806,+
20
------------------------- G 6 02 dB,<;
10G602,–
20
---------------------- G 6 02 dB,>;
=
MAX 10A4214,+
20
-------------------------
=
PSB 4860
Detailed Register Description
Semiconductor Group 174 10.97
3DhAGC4 Automatic Gain Control 4
DEC
The parameter DEC for a time constant
t
([1/ms]) is given by the following formula:
LIM
The parameter LIM for a signal level
L
([dB]) can be calculated by the following formula:
15 0
DEC LIM
DEC 256
t
---------=
LIM 128 10+ L903,+
20
---------------------- L 66,22 dB<;
10L6622,+
20
------------------------- L 66,22 dB>;
=
PSB 4860
Detailed Register Description
Semiconductor Group 175 10.97
3EhAGC5 Automatic Gain Control 5
LP
The parameter LP for a time constant
t
([1/ms]) is given by the following formula:
15 0
000000001 LP
LP 16
t
------=
PSB 4860
Detailed Register Description
Semiconductor Group 176 10.97
40hRFCTL File Control
MD Mode
0: Audio Mode
1: Binary Mode
MS Memory Space
0: R/W Memory
1: Voice Prompt Directory
TS Time Stamp
0: no update of RTC1/RTC2 entry of file descriptor
1: RTC1/RTC2 entries are updated by content of RTC1/RTC2 registers.
FNO File Number
15 0
0MDMSTS0000 FNO
Reset Value
00000000 0
PSB 4860
Detailed Register Description
Semiconductor Group 177 10.97
41hRFCMD File Command
IN Initialize
0: no
1: yes (if CMD=1111)
RD Remap Dir ectory
0: no
1: yes
ABT Abort Command
0: no
1: abort recompress
EIE Enable Immediate Execution
0: disabled (default, always possible)
1: enabled (restricted to certain commands and operating modes)
CMD File Command
15 0
0INRD00000ABTEIE0 CMD
Reset Value
00000000000 0
4 3 2 1 0 Description
0 0 0 0 0 Open File
00001Activate
0 0 0 1 0 Seek
0001 1Cut File
0 0 1 0 0 Read Data
00101Write Data
0 0 1 1 0 Me mory Status
0 0 1 1 1 Re c ompress file
0 1 0 0 0 Re ad F ile D es c ript or - User
0 1 0 0 1 Write File Descrip t or - User
PSB 4860
Detailed Register Description
Semiconductor Group 178 10.97
0 1 0 1 0 Rea d Fi le D es criptor - RTC1
0 1 0 1 1 Rea d Fi le D es criptor - RTC2
0 1 1 0 0 Rea d Fi le D es criptor - LEN
0 1 1 0 1 Garbage Collec tio n
0 1 1 1 0 Open Next Free File
0 1 1 1 1 Initialize
10000DMA Read
1 0 0 0 1 DMA Write
1 0 0 1 0 Eras e Block
1 0 0 1 1 Set A ddress
1 0 1 - - reserved
1 1 0 - - reserved
1 1 1 - - reserved
4 3 2 1 0 Description
PSB 4860
Detailed Register Description
Semiconductor Group 179 10.97
42hRFDATA File Data
The FDATA register contains the following information after a memory status command:
FREE Free Blocks
Number of blocks (1 kByte) currently usable for recording.
15 0
FREE
Reset Value
0
PSB 4860
Detailed Register Description
Semiconductor Group 180 10.97
43hRFPTR File Pointer
15 0
File Pointer
0 0 0 0 0 Phrase select or
Reset Value
0
PSB 4860
Detailed Register Description
Semiconductor Group 181 10.97
47hRSPSCTL SPS Control
POS Position of Status Register Window
MODE Mode of SPS Interface
SP1 Direct Control for SPS1
0: SPS1 set to 0
1: SPS1 set to 1
SP0 Direct Control for SPS0
0: SPS0 set to 0
1: SPS0 set to 1
Note: If mode 1 has been select ed prior to pow er-do wn, both mode 1 and the value s of
SP1 and SP0 are retained during power-down and wake-up. Other modes are
reset to 0 during power down.
1) undefined
15 0
POS 0 0 0 0 0 0 0 MODE SP1 SP0
Reset Value
0 0000000 0 -
1) -1)
15 14 13 12 SPS0SPS1
0 0 0 0 Bit 0 Bit 1
0 0 0 1 Bit 1 Bit 2
... ... ... ... ... ...
1 1 1 0 Bit 14 Bit 15
4 3 2 Description
0 0 0 D is abled (SPS0 and SPS1 zero)
0 0 1 Output of SP1 an d SP0
1 0 0 Output of speakerphone state
1 0 1 Ex panded addres s out put
1 1 0 Output of STATUS register
PSB 4860
Detailed Register Description
Semiconductor Group 182 10.97
48hRRTC1 Real Time Clock 1
MIN Minutes
Number of minutes elapsed in the current hour (0-59).
SEC Seconds
Number of seconds elapsed in the current minute (0-59).
15 0
0000 MIN SEC
Reset Value
0000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 183 10.97
49hRRTC2 Real Time Clock 2
DAY Days
Number of days elapsed since last reset (0-2047).
HR Hours
Number of hours elapsed in the current day (0-23).
15 0
DAY HR
Reset Value
00
PSB 4860
Detailed Register Description
Semiconductor Group 184 10.97
4AhRDOUT0 Data Out (Timeslot 0)
DATA Output Data
Output data for pins MA0-MA11 while MA12=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
15 0
0000 DATA
Reset Value
0000 0
PSB 4860
Detailed Register Description
Semiconductor Group 185 10.97
4BhRDOUT1 Data Out (Timeslot 1)
DATA Output Data
Output data for pins MA0-MA11 while MA13=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
15 0
0000 DATA
Reset Value
0000 0
PSB 4860
Detailed Register Description
Semiconductor Group 186 10.97
4ChRDOUT2 Data Out (Timeslot 2)
DATA Output Data
Output data for pins MA0-MA11 while MA14=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
15 0
0000 DATA
Reset Value
0000 0
PSB 4860
Detailed Register Description
Semiconductor Group 187 10.97
4DhRDOUT3 Data Out (Timeslot 3 or Static Mode)
DATA Output Data
Output data for pins MA0-MA11 while MA15=1 (only if HWCONFIG1:APP=10).
Output data for pins MA0-MA15 (only if HWCONFIG1:APP=01)
Note: This register cannot be read.
15 0
DATA
Reset Value
0
PSB 4860
Detailed Register Description
Semiconductor Group 188 10.97
4EhDIN Data In (Timeslot 3 or Static Mode)
DATA Input Data
Input data for pins MA0-MA11 at falling edge of MA12 (only if HWCONFIG1:APP=10).
Input data for pins MA0-MA15 (only if HWCONFIG1:APP=01)
15 0
DATA
PSB 4860
Detailed Register Description
Semiconductor Group 189 10.97
4FhRDDIR Data Direction (Timeslot 3 or Static Mode)
DIR Port Direction
Port direction during MA12=1 or in static mode.
0: input
1: output
Note: This register cannot be read.
15 0
DIR
Reset Value
0 (all inputs)
PSB 4860
Detailed Register Description
Semiconductor Group 190 10.97
60h RSCTL Speakerphone Control
ENS Enable Echo Suppression
0: The echo suppression unit is disabled
1: The echo suppression unit is enabled
ENC Enable Echo Cancellation
0: The echo cancellation unit is disabled
1: The echo cancellation unit is enabled
MD Mode
0: Speakerphone mode
1: Loudhearing mode
SDR Signal Source of SDR
0: after AGCR
1: before AGCR
SDX Signal Source of SDX
0: after AGCX
1: before AGCX
AGR AGCR Enable
0: AGCR disabled
1: AGCR enabled
AGX A GCX Enable
0: AGCX dis abled
1: AGCX enabled
15 0
ENSENC000000MDSDRSDX00AGRAGX0
Reset Value
0000000000000000
PSB 4860
Detailed Register Description
Semiconductor Group 191 10.97
62hRSSRC1 Speakerphone Source 1
I1 Input Signal Selection (Acoustic Source 1)
I2 Input Signal Selection (Acoustic Source 2)
15 0
000000 I1 I2
Reset Value
000000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 192 10.97
63hRSSRC2 Speakerphone Source 2
I3 Input Signal Selection (Line Source 1)
I4 Input Signal Selection (Line Source 2)
15 0
000000 I3 I4
Reset Value
000000 0 0
PSB 4860
Detailed Register Description
Semiconductor Group 193 10.97
64hSSDX1 Speech Detector (Transmit) 1
LP2L
The parameter LP2L for a saturation level
L
(dB) can be calculated by the following
formula:
LIM
The parameter LIM for a minimum signal level
L
(dB, relative to PCM max. value) can be
calculated by the following formula:
15 0
0 LP2L 0 LIM
LP2L 2L×
5log2×
-------------------=
LIM 296.3L+()×
5log2×
----------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 194 10.97
65hSSDX2 Speech Detector (Transmit) 2
LP1
The parameter LP1 for a time
t
(ms) can be calculated by t he follo wing formula:
OFF
The parameter OFF for a level offset of
O
(dB) can be calculated by the following
formula:
15 0
LP1 0 OFF
LP1 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
OFF 2O×
5 log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 195 10.97
66hSSDX3 Speech Detector (Transmit) 3
PDN
The parameter PDN for a time
t
(ms) can be calculated by the following formula:
LP2N
The parameter LP2N for a time
t
(ms) can be calculated by the following formula:
15 0
PDN LP2N
PDN 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
LP2N 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
PSB 4860
Detailed Register Description
Semiconductor Group 196 10.97
67hSSDX4 Speech Detector (Transmit) 4
PDS
The parameter PDS for a time
t
(ms) can be calc ula t ed by the follo wing formula:
LP2S
The parameter LP2S for a time
t
(ms) can be calculated by the following formula:
15 0
PDS 0 LP2S
PDS 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
LP2S 262144
t
------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 197 10.97
68hSSDR1 Speech Detector (Receive) 1
LP2L
The parameter LP2L for a saturation level
L
(dB) can be calculated by the following
formula:
LIM
The parameter LIM for a minimum signal level
L
(dB, relative to PCM max. value) can be
calculated by the following formula:
15 0
0 LP2L 0 LIM
LP2L 2L×
5log2×
-------------------=
LIM 296.3L+()×
5log2×
----------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 198 10.97
69hSSDR2 Speech Detector (Receive) 2
LP1
The parameter LP1 for a time
t
(ms) can be calculated by t he follo wing formula:
OFF
The parameter OFF for a level offset of
O
(dB) can be calculated by the following
formula:
15 0
LP1 0 OFF
LP1 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
OFF 2O×
5 log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 199 10.97
6AhSSDR3 Speech Detector (Receive) 3
PDN
The parameter PDN for a time
t
(ms) can be calculated by the following formula:
LP2N
The parameter LP2N for a time
t
(ms) can be calculated by the following formula:
15 0
PDN LP2N
PDN 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
LP2N 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
PSB 4860
Detailed Register Description
Semiconductor Group 200 10.97
6BhSSDR4 Speech Detector (Receive) 4
PDS
The parameter PDS for a time
t
(ms) can be calc ula t ed by the follo wing formula:
LP2S
The parameter LP2S for a time
t
(ms) can be calculated by the following formula:
15 0
PDS 0 LP2S
PDS 64 t⁄0.5 t 64<<;
128 2048 t⁄+ 16.2 t 2048<<;
=
LP2S 262144
t
------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 201 10.97
6ChSSCAS1 Speech Comparator (Acoustic Side) 1
G
The parameter G for a gain
A
(dB) can be calculated by the following formula:
Note: The parameter G is interpreted in two’s complement.
ET
The parameter ET for a time t (ms) can be calculated by the following formula:
15 0
GET
G
2A×
5log2×
-------------------=
ET t
4
---=
PSB 4860
Detailed Register Description
Semiconductor Group 202 10.97
6DhSSCAS2 Speech Comparator (Acoustic Side) 2
GDN
The parameter GDN for a gain
G
(dB) can be calculated by the following formula:
PDN
The parameter PDN for a decay rate
R
(ms/dB) can be calculated by the following
formula:
15 0
0GDN PDN
GDN 4G×
5log2×
-------------------=
PDN 64 R×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 203 10.97
6EhSSCAS3 Speech Comparator (Acoustic Side) 3
GDS
The parameter GDS for a gain
G
(dB) can be calculated by the following formula:
PDS
The parameter PDS for a decay rate
R
(ms/dB) can be calculated by the following
formula:
15 0
0 GDS PDS
GDS 4G×
5log2×
-------------------=
PDS 64 R×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 204 10.97
6FhSSCLS1 Speech Comparator (Line Side) 1
G
The parameter G for a gain
A
(dB) can be calculated by the following formula:
Note: The parameter G is interpreted in two’s complement.
ET
The parameter ET for a time t (ms) can be calculated by the following formula:
15 0
GET
G
2A×
5log2×
-------------------=
ET t
4
---=
PSB 4860
Detailed Register Description
Semiconductor Group 205 10.97
70hSSCLS2 Speech Comparator (Line Side) 2
GDN
The parameter GDN for a gain
G
(dB) can be calculated by the following formula:
PDN
The parameter PDN for a decay rate
R
(ms/dB) can be calculated by the following
formula:
15 0
0 GDN PDN
GDN 4G×
5log2×
-------------------=
PDN 64 R×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 206 10.97
71hSSCLS3 Speech Comparator (Line Side) 3
GDS
The parameter GDS for a gain
G
(dB) can be calculated by the following formula:
PDS
The parameter PDS for a decay rate
R
(ms/dB) can be calculated by the following
formula:
15 0
0GDS PDS
GDS 4G×
5log2×
-------------------=
PDS 64 R×
5 log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 207 10.97
72hSATT1 Attenuation Unit 1
ATT
The parameter ATT for an attenuation
A
(dB) can be calculated by the following formula:
SW
The parameter SW for a switching rate
R
(ms/dB) can be calculated by the following
formula:
15 0
0ATT SW
ATT 2A×
5log2×
-------------------=
SW 128 1
5log2×SW×
-----------------------------------+ 0.0053 SW 0.66<<;
16
5log2×SW×
----------------------------------- 0.66 SW 0.63<<;
=
PSB 4860
Detailed Register Description
Semiconductor Group 208 10.97
73hSATT2 Attenuation Unit 2
TW
The parameter TW for a time
t
(ms) can be calculated by the following formula:
DS
The parameter DS for a decay rate
R
(ms/dB) can be calculated by the following formula:
15 0
TW DS
TW t
16
------=
DS 5log2×R1–×
4
---------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 209 10.97
74hSAGX1 Automatic Gain Control (Transmit) 1
AG_INIT
The parameter AG_INIT for a gain
G
(dB) can be calculated by the following formula:
This parameter is interpreted in two’s complement.
COM
The threshold COM for a level
L
(dB) can be calculated by the following formula:
15 0
AG_INIT 0 COM
AG_INIT 2–G×
5 log2×
-------------------=
COM 296.3L+()×
5log2×
----------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 210 10.97
75hSAGX2 Automatic Gain Control (Transmit) 2
AG_ATT
The parameter AG_ATT for a gain
G
(dB) can be calculated by the following formula:
SPEEDH
The parameter SPEEDH for the regulation speed
R
(ms/dB) can be calculated by the
following formula:
The variable D denotes the aberration (dB).
15 0
0 AG_ATT SPEEDH
AG_ATT 2–G×
5log2×
-------------------=
SPEEDH 4096
DR×
--------------=
PSB 4860
Detailed Register Description
Semiconductor Group 211 10.97
76hSAGX3 Automatic Gain Control (Transmit) 3
AG_GAIN
The parameter AG_GAIN for a gain
G
(dB) can be calculated by the following formula:
SPEEDL
The parameter COM for a gain
G
(dB) can be calculated by the following formula:
The variable D denotes the aberration (dB).
15 0
AG_GAIN SPEEDL
AG_GAIN 2–G×
5log2×
-------------------=
COM 296.3G+()×
5log2×
-----------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 212 10.97
77hSAGX4 Automatic Gain Control (Transmit) 4
NOIS
The parameter NOIS for a threshold level
L
(dB) can be calculated by the following
formula:
LPA
The parameter LPA for a low pass time constant
T
(mS) can be calculated by the
following formula:
15 0
0 NOIS 0 LPA
COM 296.3L+()×
5log2×
----------------------------------=
LPA 16
T
------=
PSB 4860
Detailed Register Description
Semiconductor Group 213 10.97
78hSAGX5 Automatic Gain Control (Transmit) 5
AG_CUR
The current gain
G
of the AGC can be derived from the parameter Parameter AG_CUR
by the following formula:
AG_CUR is interpreted in two’s complement.
15 0
AG_CUR 00000000
G
5– log2 AG_CUR×× 2
-----------------------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 214 10.97
79hSAGR1 Automatic Gain Control (Receive) 1
AG_INIT
The parameter AG_INIT for a gain
G
(dB) can be calculated by the following formula:
This parameter is interpreted in two’s complement.
COM
The parameter COM for a threshold
L
(dB) can be calculated by the following formula:
15 0
AG_INIT 0 COM
AG_INIT 2–G×
5log2×
-------------------=
COM 296.3L+()×
5log2×
----------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 215 10.97
7AhSAGR2 Automatic Gain Control (Receive) 2
AG_ATT
The parameter AG_ATT for a gain
G
(dB) can be calculated by the following formula:
SPEEDH
The parameter SPEEDH for the regulation speed
R
(ms/dB) can be calculated by the
following formula:
The variable D denotes the aberration (dB).
15 0
0 AG_ATT SPEEDH
AG_ATT 2–G×
5log2×
-------------------=
SPEEDH 4096
DR×
--------------=
PSB 4860
Detailed Register Description
Semiconductor Group 216 10.97
7BhSAGR3 Automatic Gain Control (Receive) 3
AG_GAIN
The parameter AG_GAIN for a gain
G
(dB) can be calculated by the following formula:
SPEEDL
The parameter SPEEDL for the regulation speed
R
(ms/dB) can be calculated by the
following formula:
The variable D denotes the aberration (dB).
15 0
AG_GAIN SPEEDL
AG_GAIN 2–G×
5log2×
-------------------=
SPEEDL 4096
DR×
--------------=
PSB 4860
Detailed Register Description
Semiconductor Group 217 10.97
7ChSAGR4 Automatic Gain Control (Receive) 4
NOIS
The parameter NOIS for a threshold level
L
(dB) can be calculated by the following
formula:
LPA
The parameter LPA for a low pass time constant
T
(mS) can be calculated by the
following formula:
15 0
0 NOIS 0 LPA
COM 296.3L+()×
5log2×
----------------------------------=
LPA 16
T
------=
PSB 4860
Detailed Register Description
Semiconductor Group 218 10.97
7DhSAGR5 Automatic Gain Control (Receive) 5
AG_CUR
The current gain
G
of the AGC can be derived from the parameter Parameter AG_CUR
by the following formula:
AG_CUR is interpreted in two’s co mplement.
15 0
AG_CUR 00000000
G
5– log2 AG_CUR×× 2
-----------------------------------------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 219 10.97
7EhSLGA Line Gain
LGAR
The parameter LGAR for a gain
G
(dB) is given by the following formula:
LGAX
The parameter LGAX for a gain
G
(dB) is given by the following formula:
15 0
0 LGAR 0 LGAX
LGAR 128 G12–()20⁄
×10=
LGAX 128 G12–()20⁄
×10=
PSB 4860
Detailed Register Description
Semiconductor Group 220 10.97
80hSAELEN Acoustic Echo Cancellation Length
LEN
LEN denotes the number of FIR-taps used.
15 0
0000000 LEN
PSB 4860
Detailed Register Description
Semiconductor Group 221 10.97
81hSAEATT Acoustic Echo Cancellation Double Talk Attenuation
ATT
The parameter ATT for an attenuation
A
(dB) is given by the following formula:
15 0
0ATT
ATT 512 A×
5log2×
-------------------=
PSB 4860
Detailed Register Description
Semiconductor Group 222 10.97
82hSAEGS Acoustic Echo Cancellation Global Scale
GS
All coefficients of the FIR filter are scaled by a factor C. This factor is given by the
following equation:
15 0
0000000000000 GS
C2
GS
=
PSB 4860
Detailed Register Description
Semiconductor Group 223 10.97
83hSAEPS1 Acoustic Echo Cancellation Partial Scale
PS
The additional scaling coefficient AC is given by the following formula:
15 0
0000000000000 PS
AC 2PS
=
PSB 4860
Detailed Register Description
Semiconductor Group 224 10.97
84hSAEPS2 Acoustic Echo Cancellation First Block
FB
The parameter FB denotes the first block that is affected by the partial scaling coefficient.
If the partial coefficient is one, FB is disregarded.
15 0
0000000000000 FB
PSB 4860
Electrical Characteristics
Semiconductor Group 225 10.97
4 Electrical Characteristics
Electrical Characteristics
Electrical Characteristics
4.1 Absolute Maximum Ratings
ESD integrity (according MIL-Std. 883D, method 3015.7): 2 kV
Exception: The pins INT, SDX, DU/DX, DD/DR, SPS0, SPS1 and MD0-MD7 are not
protected against voltage stress >1 kV.
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
4.2 DC Characteristics
Parameter Symbol Limit Values Unit
Ambient temperature under bias TA-20 to 85 °C
Storage temperature TSTG – 65 to125 °C
Supply Voltage VDD -0.5 to 4.2 V
Supply Voltage VDDA -0.5 to 4.2 V
Supply Voltage VDDP -0.5 to 6 V
Voltage of pin with respect to ground:
XTAL1, XTAL2
VS0 to VDDA V
Voltage on any pin with respect to ground VSIf VDDP < 3 V:
– 0.4 to VDD + 0.5
If VDDP > 3 V:
– 0.4 to VDDP + 0.5
V
VDD/VDDA = 3.3 V ± 0.3 V; VDDP = 5 V ± 10%; VSS/VSSA = 0 V; TA = 0 to 70 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Input leakage current IIL – 1.0 1.0 µA0V≤V
IN ≤VDD
H-input level (except MA0-MA15,
XTAL1,OSC1)VIH1 2.0 VDDP +
0.3 V
H-input level (OSC1)VIH2 0.8
VDD
VDDA +
0.3 V
H-input level (MA0-MA15, MCTL1))VIH3 2.0 VDD V
L-input level (except pins
XTAL1,OSC1)VIL1 – 0.3 0.8 V
PSB 4860
Electrical Characteristics
Semiconductor Group 226 10.97
1) MCTL signals are (W/FWE, VPRD/FCLE, RAS/FOE, CAS0/ALE, CAS1/FCS)
L-input level (OSC1)VIL2 – 0.3 0.2
VDDA
V
H-output level (except DU/DX,
DD/DR, MA0-MA15, SPS0, SPS1,
MD0-MD7)
VOH1 VDD –
0.45 VIO = 2 mA
H-output level (SPS0, SPS1, MD0-
MD7, SDX, INT) VOH2 VDD –
0.6 VIO = 2 mA
H-output level (MA0-MA15)VOH3 VDD –
0.45 VIO = 5 mA
H-output level (DU/DX, DD/DR) VOH4 VDD –
0.6 VIO = 7 mA
L-output level (except DU/DX,
DD/DR, MA0-MA15)VOL1 0.45 V IO = – 2 mA
L-output level (MA0-MA15)
(address mode or APP output) VOL2 0.45 V IO = – 5 mA
L-output current (MA0-MA15)
(after reset) ILO 50 150 240 µARST=1
H-output current (MCTL1))IHO 25 65 120 µARST=1
L-output level (pins DU/DX, DD/
DR) VOL3 0.45 V IO = – 7 mA
Internal pullup current (FRDY)ILI 350 750 1300 µA
Input capacitance CI10 pF
Output capacitance CO15 pF
VDD supply current
(power down, no refresh, no RTC) IDDS1 10 50 µA
VDD supply current
(power down, refresh, RTC) IDDS2 20 70 µA
VDD supply current
operating IDDO 55 70 mA VDD = 3.3 V
VDDP supply current IDDP 110 µA
V
DD/VDDA = 3.3 V ± 0.3 V; VDDP = 5 V ± 10%; VSS/VSSA = 0 V; TA = 0 to 70 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
PSB 4860
Electrical Characteristics
Semiconductor Group 227 10.97
4.3 AC Characteristics
Digital inputs are dri ven to 2.4 V for a logical “1” a nd to 0.45 V f or a logical “0”. Timing
measurements are made at 2.0 V for a logical “1” and 0.8 V for a logical “0”. The AC-
testing input/output waveforms are shown below.
Figure 69 Input/Output Waveforms for AC-Tests
PSB 4860
Electrical Characteristics
Semiconductor Group 228 10.97
DTMF Detector
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Frequency deviation accept -1.5 1.5 %
Frequency deviation reject 3.5 -3.5 %
Acceptance level -45 0 dB rel. to max. PCM
Rejection level -50 dB rel. to max. PCM
Twist deviation accept +/-2 +/-8 dB programmable
Noise Tolerance 12 dB
Signal duration accept 40 ms
Signal duration reject 23 ms
Gap duration accept 18 ms
CPT Detector
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Frequency acceptance range 300 640 Hz
Frequency rejection range 800 200 Hz
Acceptance level -45 0 dB rel. to max. PCM
Rejection level -50 dB rel. to max. PCM
Signal duration accept 50 ms programmable
Signal duration reject 10 ms
Caller ID Decoder
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Frequency deviation accept -2 2 %
Acceptance level -45 0 dB rel. to max. PCM
Transmission rate 1188 1200 1212 baud
Noise Tolerance -12 dB
PSB 4860
Electrical Characteristics
Semiconductor Group 229 10.97
Alert Tone Detector
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Frequency deviation accept -0.5 0.5 % ATDCTL1:DEV=0
Frequency deviation accept -1.1 1.1 % ATDCTL1:DEV=1
Frequency deviation reject 3.5 -3.5 %
Acceptance level -40 0 dB rel. to max. PCM
Rejection level -5 dB rel. to acceptance level
Twist deviation accept +/-7 dB
Noise Tolerance 20 dB
Signal duration accept 75 ms
Gap duration accept 40 ms
CNG Detector
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Frequency deviation accept -40 40 Hz
Frequency deviation reject -50 50 Hz
Acceptance level -45 0 dB SNR >10 dB
Acceptance level -50 0 dB SNR >15 dB
Rejection level -3 dB dB rel. to CNGLEV:MIN
Signal duration reject -1 % rel. to CNGBT:TIME
PSB 4860
Electrical Characteristics
Semiconductor Group 230 10.97
Status Register Update Time
The individual bits of the STATUS register may change due to an event (like a
recognized DTMF tone) or a command. The timing can be divided into four classes
With these definitions the timing of the individual bits in the STATUS register can be
given as shown in table:
1) one FSC period
1) up to 30 m s if co mmand is either SDCT L: EN=1 or SCCTL: EN =1
Timing Diagrams
Table 87 Status Register Update Timing
Class Timing Comment
Min. Max.
I 0 0 Immediately after command has been issued
A 0 125 µs1) Command has been accepted
D125µS 250 µs Deactivation time after command has been issued
E - - Associated event has happened
Bit RDY ABT CIA CD CPT CNG SD ERR BSY DTV ATV
0->1 AEEEEEEEA
1) EE
1->0 I A A,D E,D E,D D E,D A E E,D E,D
PSB 4860
Electrical Characteristics
Semiconductor Group 231 10.97
Figure 70 Oscillator Circuits
Recommended Values
Oscillator Circuits Value Unit
Min Typ Max
Load CL140 pF
Static cap aci tanc e X 15pF
Motional capacitance X117 fF
Resonance resistor X160 Ω
Load CL230 pF
Static Ca pac itan ce X21.7 pF
Motional capacitance X23.5 fF
Resonance resistor X218 40 kΩ
Frequen cy dev iati on 100 ppm
XTAL1
XTAL2
CL1
CL1
X1
OSC1
OSC2
CL2
CL2
X2
PSB 4860
Electrical Characteristics
Semiconductor Group 232 10.97
Figure 71 SSDI/IOM®-2 Interface - Bit Synchronization Timing
Figure 72 SSDI/IOM®-2 Interface - Frame Synchronization Timing
Parameter
SSDI/IOM®-2 Interface Symbol Limit values Unit
Min Max
DCL period t1 90 ns
DCL high t2 35 ns
DCL low t335 ns
Input data setup t4 20 ns
DD/DR
DCL
DU/DX
DU/DX
first bit last bit
bit n bit n+1
t
4
t
6
t
7
t
8
t
5
t
2
t
1
t
3
FSC
DCL
t
9
t
10
t
9
t
10
PSB 4860
Electrical Characteristics
Semiconductor Group 233 10.97
Input data hold t520 ns
Output data from high impedance to active
(FSC high or other than first timeslot) t6 30 ns
Output data from active to high impedance t7 30 ns
Output data delay from clock t830 ns
FSC setup t940 ns
FSC hold t10 40 ns
FSC jitter (deviation per frame) -200 200 ns
Parameter
SSDI/IOM®-2 Interface Symbol Limit values Unit
Min Max
PSB 4860
Electrical Characteristics
Semiconductor Group 234 10.97
Figure 73 SSDI Interface - Strobe Timing
Parameter
SSDI Interface Symbol Limi t value s Unit
Min Max
DXST delay t120 ns
DRST inactive setup t220 ns
DRST inactive hold t320 ns
DRST active setup t420 ns
DRST active hold t520 ns
FSC setup t68 DCL cycles
FSC hold t740 ns
DRST
DCL
t
4
t
5
t
2
t
3
FSC
t
6
t
7
DXST
t
1
PSB 4860
Electrical Characteristics
Semiconductor Group 235 10.97
Figure 74 Serial Control Interface
Parameter
SCI Interface Symbol Limit values Unit
Min Max
SCLK cycle time t1500 ns
SCLK high time t2 100 ns
SCLK low time t3 100 ns
CS setup time t4 40 ns
CS hold time t510 ns
SDR setup time t6 40 ns
SDR hold time t7 40 ns
SDX data out delay t8 80 ns
CS high to SDX tristate t940 ns
SCLK to SDX active t10 80 ns
SCLK to SDX tristate t11 40 ns
CS to INT delay t12 80 ns
CS
SCLK
SDR
SDX
INT
t
4
t
2
t
3
t
1
t
12
t
10
t
11
t
9
t
5
t
6
t
7
t
8
PSB 4860
Electrical Characteristics
Semiconductor Group 236 10.97
Figure 75 Analog Front End Interface
Parameter
AFE Interface Symbol Limit values Unit
Min Max
AFECLK period t1 125 165 ns
AFECLK high t2 21/f
XTAL
AFECLK low t321/f
XTAL
AFEDU setup t4 20 ns
AFEDU hold t520 ns
AFEDD output delay t630 ns
AFEFS output delay t730 ns
AFEDU
AFECLK
AFEDD bit n bit n+1
t
4
t
6
t
5
t
2
t
1
t
3
AFEFS
t
7
t
7
PSB 4860
Electrical Characteristics
Semiconductor Group 237 10.97
Figure 76 Memory Interface - DRAM Read Access
Parameter
Memory Interface - DRAM Read Access Symbol Limit values Unit
Min Max
row address setup time t1 50 ns
row address hold time t2 50 ns
column address setup time t350 ns
RAS precharge time t4 110 ns
RAS to CAS delay t5110 2000 ns
CAS pulse width t6 110 2000 ns
Data input setup time t7 40 ns
Data input hold time t80ns
MA0-MA13
MD0-MD7
CAS0,CAS1
RAS
row addr. col. addr.
t
1
t
2
t
3
t
6
t
7
t
8
t
5
t
4
PSB 4860
Electrical Characteristics
Semiconductor Group 238 10.97
Figure 77 Memory Interface - DRAM Write Access
Parameter
Memory Interface - DRAM Write Access Symbol Limit values Unit
Min Max
row address setup time t1 50 ns
row address hold time t2 50 ns
column address setup time t350 ns
RAS precharge time t4 110 ns
RAS to CAS delay t5110 2000 ns
CAS pulse width t6 110 2000 ns
Data output setup time t7100 ns
Data output hold time t850 ns
RAS to W delay t950 ns
W to CAS setup t10 50 ns
MA0-MA13
MD0-MD7
CAS0,CAS1
RAS
row ad dr. col. addr.
t
1
t
2
t
3
t
6
t
7
t
8
t
5
t
4
W
t
9
t
10
PSB 4860
Electrical Characteristics
Semiconductor Group 239 10.97
Figure 78 Memory Interface - DRAM Refresh Cycle
Note: The frequency of the DRAM refresh cycle depends on the selected mode. In active
mode or normal refresh mode (during power down) the minimal frequency is 64
kHz. In battery backup mode, the refresh frequency is 8 kHz.
Parameter
Memory Interface - DRAM Refresh Cycle Symbol Limit values Unit
Min Max
RAS precharge time t1 100 ns
RAS low time t2 200 5000 ns
CAS setup t3100 ns
CAS hold t4 100 ns
CAS0,CAS1
RAS
t
3
t
1
t
2
t
4
PSB 4860
Electrical Characteristics
Semiconductor Group 240 10.97
Figure 79 Memory Interface - EPROM Read
Parameter
Memory Interface - EPROM Read Symbol Limit values Unit
Min Max
Address setup before VPRD t1 110 ns
VPRD low time t2 500 ns
Data setup time t340 ns
Data hold time t4 0ns
MA0-MA15
MD0-MD7
VPRD
linear address
t
1
t
2
t
3
t
4
PSB 4860
Electrical Characteristics
Semiconductor Group 241 10.97
Figure 80 Memory Interface - Samsung Command Write
Note: FCS stays low if other cycles follow for the same access.
Parameter
Memory Interface - Samsung Command
Write
Symbol Limit values Unit
Min Max
Address setup before FCS, FCLE t1 100 ns
FCS low time, FCLE high time t2 400 ns
FWR hold after FCLE rising t3100 ns
FWR low time t4 200 ns
FWR setup before FCLE falling t5100 ns
Data setup time t6200 ns
Data hold time t750 ns
MA0-MA11
MD0-MD7
FCS(FCS0-FCS3)
A16-A23 and FCS0-FCS3
t
1
t
2
FWR
FCLE
t
3
t
4
t
5
t
6
t
7
PSB 4860
Electrical Characteristics
Semiconductor Group 242 10.97
Figure 81 Memory Interface - Samsung Address Write
Parameter
Memory Interface - Samsung Address
Write
Symbol Limit values Unit
Min Max
ALE high time t1 400 ns
FWR hold after ALE rising t2100 ns
FWR low time t3 200 ns
FWR setup before ALE falling t4100 ns
Data setup time t5200 ns
Data hold time t650 ns
MD0-MD7
t
1
FWR
ALE
t
2
t
3
t
4
t
5
t
6
PSB 4860
Electrical Characteristics
Semiconductor Group 243 10.97
Figure 82 Memory Interface - Samsung Data Write
Parameter
Memory Interface - Samsung Data Write Symbol Limit values Unit
Min Max
FWR low time t1 200 ns
Data setup time t2200 ns
Data hold time t350 ns
MD0-MD7
FWR
t
1
t
2
t
3
PSB 4860
Electrical Characteristics
Semiconductor Group 244 10.97
Figure 83 Memory Interface - Samsung Data Read
Parameter
Memory Interface - Samsung Data Read Symbol Limit values Unit
Min Max
FOE low t ime t1 200 ns
Data setup time t240 ns
Data hold time t30ns
MD0-MD7
FOE
t
1
t
2
t
3
PSB 4860
Electrical Characteristics
Semiconductor Group 245 10.97
Figure 84 Auxiliary Parallel Port - Multiplex Mode
Parameter
Auxiliary Port Interface - Multiplex Mode Symbol Limit values Unit
Min Typ Max
Active time (MA0-MA15)t1 2ms
Gap time (MA0-MA15)t2125 µs
Data setup time t350 ns
Data hold time t40ns
MA0-MA11
MA12
t
3
t
4
t
1
t
2
MA13
PSB 4860
Electrical Characteristics
Semiconductor Group 246 10.97
Figure 85 Reset Timing
Parameter
Reset Timing Symbol Limit values Unit
Min Max
V
DD/
V
DDP/
V
DDA rise time 5%-95% t1 20 ms
Supply voltages stable to RST high t2 0ns
Supply voltages stable to RST low t30.1 ms
RST high time t41000 ns
RST
t
3
V
DD/
V
DDP
t
1
t
2
t
4
PSB 4860
Package Outlines
Semiconductor Group 247 10.97
5 Package Outlines
Plastic Package, P-MQFP-80 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group 248 10.97
PSB 4860
Index
A
Abort
Clearing Event 82, 119
Functional Description 81
Status Bit 109
Alert Tone Detector
Electrical Characteristics 229
Functional Description 46
Registers 146–147
Status Bit 110
Analog Front End Interface
Electrical Characteristics 236
Functional Description 55
Registers 122–128
Timing 92
ARAM
see Memory Interfa ce
Automatic Gain Control
Functional Description 59
Registers 169–175
Auxiliary Parallel Port
Electrical Characteristics 245
Mode Bits 112
Multiplex Mode 107
Registers 184–189
Static Mode 107
C
Caller I D De coder
Electrical Characteristics 228
Functional Description 49
Registers 148–149
Status Bits 109
CNG Detector
Electrical Characteristics 229
Functional Description 45
Registers 142–145
Status Bit 110
CPT Detector
Electrical Character istics 228
Functional Description 47
Registers 150–154
Status Bit 110
D
Digital Interface
Functional Description 56
Mode Bits 112
Registers 129–135
DRAM
see Memory Interface
DTMF Detector
Electrical Character istics 228
Functional Description 44
Registers 159–161
Status Bit 110
DTMF Generator
Functional Description 51
Registers 137–141
E
EPROM
see Memory Interface
Equalizer
Functional Description 61
Registers 162–164
Execution Time s
File Commands 77
F
File
Commands
Access File Descriptor 72
Compress 71
Create Next New 69
Delete 71
Semiconductor Group 249 10.97
PSB 4860
Index
Execution Times 77
New File 69
Open 69
Read Binary Data 73
Registers 176–180
Restrictions 78
Seek 70
Status Bits 110
Tailcut 71
Write Binary Data 74
Type
Audio 64
Binary 64
Phrase 65
User Data Word 66
Flash Memory
see Memory Interfa ce
G
Group Listening 38
H
Hardware Configuration
Functional Description 82
Registers 111
I
Interrupt
Functional Description 80
Pin Configuration 111
Register 121
IOM®-2 Interface
Electrical Characteristics 232–233
Functional Description 86
see also: Digital Interface
L
Line Echo Canceller
Functional Description 42
Registers 155–158
Loudhearing 38
M
Memory Interface
ARAM/DRAM
Connection Diagram 99
Electrical Characteristics 237–239
Refresh 101, 113
Timing 100
EPROM
Connection Diagram 102
Electrical Characteristics 240
Timing 102
Flash
Connection Diagram 103
Electrical Characteristics 241–244
In-Circuit Programming 98, 113
Multiple Devices 104
Timing 105
Register 120
Supported Devices 98
Memory Management
Activation 68
Directories 63
ExecutionTimes 77
Files 64
Garbage Collection 72
Initialization 67
Memory Status 72
Overview 63
Status 65
O
Oscillator
Electrical Character istics 231
Mode Bits 112
P
Power Down
Functional Description 79
Semiconductor Group 250 10.97
PSB 4860
Index
Status Bit 111
R
Real Time Clock
Configuration Bits 111
Functional Description 79
Oscill ator 231
Registers 182–183
Recompression 71
Reset
Electrical Characteristics 246
Functional Description 79
Register Values 115
Restrictions
File Commands 78
Modules 83
Revision
Functional Description 82
Register 119
S
Serial Control Interface
Command Opcodes 97
Electrical Characteristics 235
Functional Description 94
Signals
Encoding 117
Reference Table 117
Speakerphone
Functional Description
Automatic Gain Control 38
Control 37
Echo Cancellation 28
Echo Suppression 30
Overview 27
Speech Comparator 35
Speech Detector 32
Registers 190–223
Speech Coder
Functional Description 52
Registers 165–167
Speech Decoder
Functional Description 54
Register 168
SPS Outputs
Functional Description 38, 79
Register 181
SSDI Interface
Electrical Characteristics 232–234
Functional Description 90
see also: Digital Interface
Sta tus Register
Definition 109
Update Timing 230
U
Universal Attenuator
Functional Description 58
Register 136
