CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply
D
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – E Tube CD74AC74E CD74AC74E
55°Cto125°C
SOIC M
Tube CD74AC74M
AC74M
–
55°C
to
125°C
SOIC
–
M
Tape and reel CD74AC74M96
AC74M
CDIP – F Tube CD54AC74F3A CD54AC74F3A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
‡H‡
H H ↑HHL
H H ↑LLH
H H L X Q0Q0
‡This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
CD54AC74 ...F PACKAGE
CD74AC74 ...E OR M PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
TA = 25°C–55°C to
125°C–40°C to
85°CUNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
VCC = 1.5 V 1.2 1.2 1.2
VIH High-level input voltage VCC = 3 V 2.1 2.1 2.1 V
VCC = 5.5 V 3.85 3.85 3.85
VCC = 1.5 V 0.3 0.3 0.3
VIL Low-level input voltage VCC = 3 V 0.9 0.9 0.9 V
VCC = 5.5 V 1.65 1.65 1.65
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
IOH High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA
IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA
∆t/∆v
In
p
ut transition rise or fall rate
VCC = 1.5 V to 3 V 50 50 50
ns/V
∆t/∆v
Input
transition
rise
or
fall
rate
VCC = 3.6 V to 5.5 V 20 20 20
ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
TA = 25°C–55°C to
125°C–40°C to
85°CUNIT
CC
MIN MAX MIN MAX MIN MAX
1.5 V 1.4 1.4 1.4
IOH = –50 µA3 V 2.9 2.9 2.9
4.5 V 4.4 4.4 4.4
VOH VI = VIH or VIL IOH = –4 mA 3 V 2.58 2.4 2.48 V
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA†5.5 V 3.85
IOH = –75 mA†5.5 V 3.85
1.5 V 0.1 0.1 0.1
IOL = 50 µA3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
VOL VI = VIH or VIL IOL = 12 mA 3 V 0.36 0.5 0.44 V
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA†5.5 V 1.65
IOL = 75 mA†5.5 V 1.65
IIVI = VCC or GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
Ci10 10 10 pF
†T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless
otherwise noted)
–55°C to
125°C–40°C to
85°CUNIT
MIN MAX MIN MAX
fclock Clock frequency 9 10 MHz
t
Pulse duration
PRE or CLR low 50 44
ns
t
w
Pulse
duration
CLK 56 49
ns
t
Setup time
Data 44 39 ns
t
su
S
e
t
up
ti
me PRE or CLR inactive ns
thHold time Data after CLK↑0 0 ns
trec Recovery time, before CLK↑CLR↑or PRE↑34 30 ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
–55°C to
125°C–40°C to
85°CUNIT
MIN MAX MIN MAX
fclock Clock frequency 79 90 MHz
t
Pulse duration
PRE or CLR low 5.6 4.9
ns
t
w
Pulse
duration
CLK 6.3 5.5
ns
t
Setup time
Data 4.9 4.3 ns
t
su
S
e
t
up
ti
me PRE or CLR inactive ns
thHold time Data after CLK↑0 0 ns
trec Recovery time, before CLK↑CLR↑or PRE↑4.7 4.1 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
–55°C to
125°C–40°C to
85°CUNIT
MIN MAX MIN MAX
fclock Clock frequency 110 125 MHz
t
Pulse duration
PRE or CLR low 4 3.5
ns
t
w
Pulse
duration
CLK 4.5 3.9
ns
t
Setup time
Data 3.5 3.1 ns
t
su
S
e
t
up
ti
me PRE or CLR inactive ns
thHold time Data after CLK↑0 0 ns
trec Recovery time, before CLK↑CLR↑or PRE↑2.7 2.4 ns
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C–40°C to
85°CUNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
fmax 9 10 MHz
tPLH
CLK
QQ
125 114
ns
tPHL
CLK
Q
or
Q
125 114
ns
tPLH
PRE or CLR
QorQ
132 120
ns
tPHL
PRE
or
CLR
Q
or
Q
144 131
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C–40°C to
85°CUNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
fmax 79 90 MHz
tPLH
CLK
QQ
3.5 14 3.6 12.7
ns
tPHL
CLK
Q
or
Q
3.5 14 3.6 12.7
ns
tPLH
PRE or CLR
QorQ
3.7 14.7 3.8 13.4
ns
tPHL
PRE
or
CLR
Q
or
Q
4 16.1 4.1 14.6
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C–40°C to
85°CUNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
fmax 110 125 MHz
tPLH
CLK
QQ
2.5 10 2.6 9.1
ns
tPHL
CLK
Q
or
Q
2.5 10 2.6 9.1
ns
tPLH
PRE or CLR
QorQ
2.6 10.5 2.7 9.5
ns
tPHL
PRE
or
CLR
Q
or
Q
2.9 11.5 3 10.4
ns
operating characteristics, TA = 25°C
PARAMETER TYP UNIT
Cpd Power dissipation capacitance 55 pF
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
R1 = 500 Ω†Open
GND
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
Output
Control
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC 20% VCC
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
80% VCC
VCC
R2 = 500 Ω†
†When VCC = 1.5 V, R1 = R2 = 1 kΩ
VOLTAGE WAVEFORMS
RECOVER Y TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54AC74F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD74AC74E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC74EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC74M ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC74M96 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC74M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC74M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC74ME4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC74MG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC74M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC74M96 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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