MCP33151D/41D-XX 1 Msps/500 kSPS, 14/12-Bit Differential Input SAR ADC Features Typical Applications * Sample Rate (Throughput): - MCP33151D/41D-10: 1 Msps - MCP33151D/41D-05: 500 kSPS * 14/12-Bit Resolution with No Missing Codes * No Latency Output * Wide Operating Voltage Range: - Analog supply voltage (AVDD): 1.8V - Digital input/output interface voltage (DVIO): 1.7-5.5V - External reference voltage (VREF): AVDD - 5.1V * Differential Input Operation - Input full-scale range: -VREF to +VREF * Ultra Low Current Consumption (typical): - During input acquisition (standby): ~1.5 A - During conversion: MCP33151D/41D-10: ~0.66 mA MCP33151D/41D-05: ~0.33 mA * SPI-Compatible Serial Communication: - SCLK clock rate: up to 100 MHz - 3-wire with optional BUSY indicator * ADC Self-Calibration for Offset, Gain, and Linearity Errors: - During power-up (automatic) - On-Demand via user's command during normal operation * Built In Data Accumulator - Integrate up to 1024 consecutive converted samples - Increase ENOB up to 18.5 bits by automatically averaging conversion results * AEC-Q100 Qualified: - Temperature grade 1: -40C to +125C * Package Options: MSOP-10 and TDFN-10 * * * * * * * High-Precision Data Acquisition Medical Instruments Test Equipment Electric Vehicle Battery Management Systems Motor Control Applications Switch-Mode Power Supply Applications Battery-Powered Equipment System Design Supports The MCP331x1D-XX Evaluation Kit demonstrates the performance of the MCP331x1D-XX SAR ADC family devices. The evaluation kit includes: (a) MCP331x1D Evaluation Board, (b) PIC32MZ EF Curiosity Board for data collection, and (c) SAR ADC Utility PC GUI. Contact Microchip Technology Inc. for the evaluation tools and the PIC32 firmware example codes. Package Types MSOP-10 TDFN-10 * * Includes Exposed Thermal Pad (see Table 4-1). MCP331x1D-XX Device Offering (Note 1) Part Number Resolution Sample Rate MCP33151D-10 14-bit 1 Msps Differential MCP33141D-10 12-bit 1 Msps MCP33151D-05 14-bit 500 kSPS MCP33141D-05 12-bit 500 kSPS Note 1: Input Range Input Type (Differential) Performance (Typical) SNR (dBFS) SFDR (dB) 5.1V 83.8 Differential 5.1V Differential 5.1V Differential 5.1V THD (dB) INL (LSB) DNL (LSB) 107.3 -104.7 0.27 0.11 73.8 100.0 -101.5 0.07 0.05 83.7 103.8 -100.9 0.27 0.11 73.8 99.8 -98.9 0.05 0.07 SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V. 2019 Microchip Technology Inc. DS20006219A-page 1 MCP33151D/41D-XX Application Diagram AVDD to 5.1V 1.8V 1.8V to 5.5V VREF AVDD DVIO 15 AIN+ 0V to VREF SDI 2.2nF MCP331x1D-XX 15 2.2nF Description The MCP33151D/41D-10 and MCP33151D/41D-05 are fully-differential, 14-bit and 12-bit, single-channel, 1 Msps and 500 kSPS ADC family devices, respectively, featuring low power consumption and high performance, using a successive approximation register (SAR) architecture. The device operates with an external voltage reference (VREF) from AVDD to 5.1V, which supports a wide range of input full-scale range from -VREF to +VREF. The reference voltage setting is independent of the analog supply voltage (AVDD). The conversion output is available through an easy-to-use simple SPIcompatible 3-wire interface. The device requires a 1.8V analog supply voltage (AVDD) and a 1.7V to 5.5V digital I/O interface supply voltage (DVIO). The wide digital I/O interface supply (DVIO) range (1.7-5.5V) allows the device to interface with most host devices (Master) available in the current industry such as the PIC32 microcontrollers, without using external voltage level shifters. Once all supply voltages are connected, the device will power-up and perform an automatic calibration to minimize offset, gain and linearity errors. The automatic calibration takes place approximately 40 ms following power-up, and it is necessary to ensure that all power supplies are fully settled and stable after this time. See Section 4.3 "Power-Up Sequence and Auto-Calibration" for more details. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage did not fully settle during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration and restore optimum performance. Host Device SCLK AIN- 0V to VREF CNVST SDO (PIC32MZ) GND During Standby, most of the internal analog circuitry is shutdown in order to reduce current consumption. Typically, the device consumes approximately 1.5 A during Standby. A new conversion is started on the rising edge of CNVST. When the conversion is complete and the host lowers CNVST, the output data is presented on SDO, and the device enters Standby to begin acquiring the next input sample. The user can clock out the ADC output data using the SPI-compatible serial clock during Standby. The ADC system clock is generated by the internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK). This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed. The device is AEC-Q100 qualified for automotive applications and operates over the extended temperature range of -40C to +125C. The available package options are Pb-free small 3 mm x 3 mm TDFN-10 and MSOP-10. When the initial power-up sequence is completed, the device enters a low-current input acquisition mode (also referred to as `Standby mode'), where sampling capacitors are connected to the input pins. DS20006219A-page 2 2019 Microchip Technology Inc. MCP33151D/41D-XX 1.0 KEY ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings External Analog Supply Voltage (AVDD) ...................................................................................................... -0.3V to 2.0V External Digital Supply Voltage (DVIO)......................................................................................................... -0.3V to 5.8V External Reference Voltage (VREF).............................................................................................................. -0.3V to 5.8V Analog Inputs w.r.t GND ................................................................................................................. -0.3V to VREF + 0.3V Current at Input Pins ..............................................................................................................................................2 mA Current at Output and Supply Pins .................................................................................................................... 250 mA Storage Temperature ..............................................................................................................................-65C to +150C Maximum Junction Temperature (TJ) ................................................................................................................... +150C ESD Protection on All Pins ...................................................................................................... 4 kV HBM, 2 kV CDM Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.2 Electrical Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF, +25C is applied for typical values. MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V Digital Input/Output Interface Voltage Range DVIO 1.7 -- 5.5 IDDAN -- -- -- 660 330 1.5 900 600 -- A A A fS = 1 Msps (MCP331x1D-10) fS = 500 kSPS (MCP331x1D-05) During Input Acquisition (tACQ) IIO_STBY -- -- -- -- -- 400 343 200 171 120 -- -- -- -- -- A A A A nA fS = 1 Msps (MCP33151D-10) fS = 1 Msps (MCP33141D-10) fS = 500 kSPS (MCP33151D-05) fS = 500 kSPS (MCP33141D-05) During Input Acquisition (tACQ) VREF AVDD -- 5.1 V Power Supply Requirements Analog Supply Current at AVDD Pin: During Conversion During Standby IDDAN_STBY Average Digital Supply Current at DVIO Pin: During Data Transfer During Standby IIO_DATA Note 3 Note 3 External Reference Voltage Input Reference Voltage (Note 2, Note 3) Note 1: 2: 3: 4: 5: 6: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. Differential Input Full-Scale Range (FSR) = 2 x VREF. PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result. ENOB = (SINAD - 1.76)/6.02. 2019 Microchip Technology Inc. DS20006219A-page 3 MCP33151D/41D-XX TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF, +25C is applied for typical values. MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Reference Load Current at VREF Pin: During Conversion During Standby Sym. Min. Typ. Max. Units IREF -- -- -- 220 110 40 290 180 -- A A nA fS = 1 Msps (MCP331x1D-10) fS = 500 kSPS (MCP331x1D-05) During Input Acquisition (tACQ) IREF_STBY Conditions Total Power Consumption (Including AVDD, DVIO, VREF pins) MCP331x1D-10 -- -- -- -- 3.6 1.8 0.4 3.3 -- -- -- -- mW mW mW W Averaged power for tACQ + tCNV 1.8 0.4 3.3 -- -- -- mW mW W Averaged power for tACQ + tCNV PDISS_STBY -- -- -- Input Voltage Range (Note 2) VIN+ -0.1 -- VREF + 0.1 V VIN- -0.1 -- VREF + 0.1 Input Full-Scale Voltage Range FSR -VREF -- +VREF Input Common-mode Voltage Range VCM 0 VREF/2 VREF Input Sampling Capacitance CS -- 10 -- pF at 1 Msps at 500 kSPS at 100 kSPS During Standby PDISS_TOTAL PDISS_STBY Input acquisition (tACQ) MCP331x1D-05 at 500 kSPS at 100 kSPS During Standby PDISS_TOTAL Input acquisition (tACQ) Analog Inputs -3dB Input Bandwidth BW-3dB Differential Input (Note 2, Note 4) Note 2 Note 1 -- 45 -- MHz -- 2.5 -- ns Time delay between CNVST rising edge and when input is sampled ILEAK_AN_INPUT -- 2.2 200 nA During Standby fS -- -- 1 Msps MCP331x1D-10 -- -- 500 kSPS MCP331x1D-05 14 -- -- Aperture Delay (Note 1) Leakage Current at Analog Input Pin VPP Differential Input: VIN = VIN+ - VIN- Note 1 System Performance Sample Rate (Throughput Rate) Resolution (No Missing Codes) bits MCP33151D-XX 12 -- -- bits MCP33141D-XX Integral Nonlinearity INL -1.5 0.27 +1.5 LSB MCP33151D-XX -- 0.07 -- LSB MCP33141D-XX Differential Nonlinearity DNL -0.8 0.11 +0.8 LSB MCP33151D-XX -0.3 0.05 +0.3 LSB MCP33141D-XX Note 1: 2: 3: 4: 5: 6: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. Differential Input Full-Scale Range (FSR) = 2 x VREF. PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result. ENOB = (SINAD - 1.76)/6.02. DS20006219A-page 4 2019 Microchip Technology Inc. MCP33151D/41D-XX TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF, +25C is applied for typical values. MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Offset Error Offset Error Drift with Temperature Gain Error GER Gain Error Drift with Temperature Min. Typ. Max. Units -1.62 0.4 1.62 mV MCP33151D-XX -1.33 0.4 1.33 mV MCP33141D-XX -- 0.1 -- V/C -- 1 -- LSB MCP33151D-XX -- 0.2 -- LSB MCP33141D-XX -- 8 -- V/C Input Common-mode Rejection Ratio CMRR -- 84 -- dB Power Supply Rejection Ratio PSRR -- 75 -- dB Conditions Note 5 Dynamic Performance Signal-to-Noise Ratio SNR MCP33151D-10 and MCP33151D-05: 14-bit ADC dBFS VREF = 5V, fIN = 1 kHz -- 83.9 -- -- 79.2 -- VREF = 1.8V, fIN = 1 kHz 82.6 83.7 -- VREF = 5V, fIN = 10 kHz -- 78.8 -- VREF = 1.8V, fIN = 10 kHz -- 73.8 MCP33141D-10 and MCP33141D-05: 12-bit ADC Signal-to-Noise Distortion Ratio (Note 6) -- -- 73.1 -- dBFS VREF = 5V, fIN = 1 kHz VREF = 1.8V, fIN = 1 kHz 73.4 73.8 -- VREF = 5V, fIN = 10 kHz -- 73.0 -- VREF = 1.8V, fIN = 10 kHz MCP33151D-10 and MCP33151D-05: 14-bit ADC SINAD -- 83.9 -- -- 79.2 -- dBFS VREF = 5V, fIN = 1 kHz VREF = 1.8V, fIN = 1 kHz -- 83.6 -- VREF = 5V, fIN = 10 kHz -- 77.8 -- VREF = 1.8V, fIN = 10 kHz -- 73.8 MCP33141D-10 and MCP33141D-05: 12-bit ADC Note 1: 2: 3: 4: 5: 6: -- 73.1 -- dBFS VREF = 5V, fIN = 1 kHz VREF = 1.8V, fIN = 1 kHz -- 73.8 -- VREF = 5V, fIN = 10 kHz -- 73.0 -- VREF = 1.8V, fIN = 10 kHz -- This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. Differential Input Full-Scale Range (FSR) = 2 x VREF. PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result. ENOB = (SINAD - 1.76)/6.02. 2019 Microchip Technology Inc. DS20006219A-page 5 MCP33151D/41D-XX TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF, +25C is applied for typical values. MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Spurious Free Dynamic Range SFDR Min. Typ. Max. Units Conditions MCP33151D-10 and MCP33151D-05: 14-bit ADC -- 110.5 -- -- 107.2 -- dBc VREF = 5V, fIN = 1 kHz VREF = 1.8V, fIN = 1 kHz -- 105.9 -- VREF = 5V, fIN = 10 kHz -- 96.3 -- VREF = 1.8V, fIN = 10 kHz -- 99.8 MCP33141D-10 and MCP33141D-05: 12-bit ADC Total Harmonic Distortion (first five harmonics) -- dBc VREF = 5V, fIN = 1 kHz -- 99.4 -- VREF = 1.8V, fIN = 1 kHz -- 99.9 -- VREF = 5V, fIN = 10 kHz -- 95.2 -- VREF = 1.8V, fIN = 10 kHz THD MCP33151D-10 and MCP33151D-05: 14-bit ADC -- -105.0 -- -- -105.2 -- dBc VREF = 5V, fIN = 1 kHz VREF = 1.8V, fIN = 1 kHz -- 103.2 -- VREF = 5V, fIN = 10 kHz -- 95.2 -- VREF = 1.8V, fIN = 10 kHz -- -100.7 MCP33141D-10 and MCP33141D-05: 12-bit ADC -- dBc VREF = 5V, fIN = 1 kHz -- -100.3 -- VREF = 1.8V, fIN = 1 kHz -- -100.4 -- VREF = 5V, fIN = 10 kHz -- -94.2 -- VREF = 1.8V, fIN = 10 kHz tCAL -- 400 550 ReCalNSCLK -- 1024 -- System Self-Calibration Self-Calibration Time Number of SCLK Clocks for Recalibrate Command ms Note 2 clocks Includes clocks for data bits Serial Interface Timing Information: See Serial Interface Timing Specifications Digital Inputs/Outputs High-level Input Voltage VIH 0.7 x D VIO -- DVIO + 0.3 V DVIO < 2.3V 0.9 x D VIO Low-level Input Voltage VIL -0.3 -- -0.3 Hysteresis of Schmitt Trigger Inputs Note 1: 2: 3: 4: 5: 6: VHYST -- DVIO 2.3V 0.3 x DVIO V DVIO 2.3V V All digital inputs 0.2 x DVIO 0.2 x DVIO -- DVIO < 2.3V This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. Differential Input Full-Scale Range (FSR) = 2 x VREF. PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result. ENOB = (SINAD - 1.76)/6.02. DS20006219A-page 6 2019 Microchip Technology Inc. MCP33151D/41D-XX TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF, +25C is applied for typical values. MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Low-level Output Voltage VOL -- -- 0.2 x DVIO V IOL = 500 A (source) High-level Output Voltage VOH 0.8 x D VIO -- -- V IOH = -500 A (sink) Input Leakage Current ILI -- -- 1 A CNVST/SDI/SCLK = GND or DVIO Output Leakage Current ILO -- -- 1 A Output is high-Z, SDO = GND or DVIO CINT -- 7 -- pF TA = +25C Internal Capacitance (all digital inputs and outputs) Note 1: 2: 3: 4: 5: 6: Conditions This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. Differential Input Full-Scale Range (FSR) = 2 x VREF. PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result. ENOB = (SINAD - 1.76)/6.02. TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, GND = 0V, Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1 Msps, +25C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram. Parameters Sym. Min. Typ. Max. Units Serial Clock Frequency fSCLK -- -- 100 MHz SCLK Period tSCLK 10 -- -- ns 12 -- -- DVIO 2.3V, fSCLK = 83.3 MHz (Max.) 16 -- -- DVIO 1.7V, fSCLK = 62.5 MHz (Max.) 3 -- -- SCLK Low Time tSCLK_L SCLK High Time tSCLK_H Output Valid from SCLK Low Quiet Time tDO tQUIET Conditions See tSCLK specification DVIO 3.3V, fSCLK = 100 MHz (Max.) ns DVIO 2.3V ns DVIO 2.3V ns DVIO 3.3V DVIO 1.7V 4.5 -- -- 3 -- -- 4.5 -- -- -- -- 10 -- -- 12 DVIO 2.3V -- -- 16 DVIO 1.7V 10 -- -- DVIO 1.7V ns 3-wire Operation: Note 1: 2: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. 2019 Microchip Technology Inc. DS20006219A-page 7 MCP33151D/41D-XX TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +125C, AVDD = 1.8V, DVIO = 3.3V, GND = 0V, Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1 Msps, +25C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram. Parameters SDI Valid Setup Time Sym. Min. Typ. Max. Units ns Conditions tSU_SDIH_CNV 5 -- -- -- -- SDI High to CNVST Rising Edge -- 10 DVIO 2.3V tCNVH 10 Output Enable Time tEN -- -- -- 15 DVIO 1.7V Output Disable Time tDIS -- -- 15 Note 2 CNVST Pulse Width Time MCP331x1D-10 Sample Rate fS -- -- 1 Msps Input Acquisition Time tACQ 250 490 -- ns Data Conversion Time tCNV -- 510 750 ns Time Between Conversions tCYC 1 -- -- s Throughput Rate tCYC = tACQ + tCNV, fS = 1 Msps MCP331x1D-05 fS -- -- 500 kSPS Input Acquisition Time Sample Rate tACQ 600 800 -- ns Data Conversion Time tCNV -- 1200 1400 ns Time Between Conversions tCYC 2 -- -- s Note 1: 2: Throughput Rate tCYC = tACQ + tCNV, fS = 500 kSPS This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. TCYC = 1/fs SDI = 1 tSU_SDIH_CNV tCNVH tEN (late CNV) (Note 1) CNV (CS) tSCLK 1 tDO SC>K "High" (with pull-up) SDO Hi-Z (with no pull-up) D13 3 4 tSCLK_L D12 D11 5 12 13 tSCLK_H D10 D9 14 tDIS D2 D1 D0 tEN (early CNV) (Note 2) ADC State Converting Phase (tCNV ) Note 2 tQUIET 1: tEN when CNVST is lowered after tCNV (MAX). 2: tEN when CNVST is lowered before tCNV (MAX). Input Acquisition (tACQ) FIGURE 1-1: Interface Timing Diagram (14-bit device). CNVST is Used as Chip Select. See Section 6.0 "Digital Serial Interface" for More Details. DS20006219A-page 8 2019 Microchip Technology Inc. MCP33151D/41D-XX TABLE 1-3: TEMPERATURE CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Conditions Operating Temperature Range TA -40 -- +125 C Note 1 Storage Temperature Range TA -65 -- +150 C Note 1 Thermal Resistance, MSOP-10 JA -- 202 -- C/W Thermal Resistance, TDFN-10 JA -- 68 -- C/W Temperature Ranges Thermal Package Resistance Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC. 2019 Microchip Technology Inc. DS20006219A-page 9 MCP33151D/41D-XX NOTES: DS20006219A-page 10 2019 Microchip Technology Inc. MCP33151D/41D-XX 2.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33151D-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 0.25 0.5 VREF = 5V VREF = 5V 0.1 DNL (LSB) INL (LSB) 0.25 0 0 -0.1 -.25 -0.5 0 4,096 8,192 12,288 -0.25 16,384 Code FIGURE 2-1: VREF = 5V. 0 4,096 8,192 12,288 INL vs. Output Code: FIGURE 2-4: VREF = 5V. 0.5 DNL vs. Output Code: 0.25 VREF = 1.8V VREF = 1.8V 0.10 DNL (LSB) INL (LSB) 0.25 0 0 -0.10 -0.25 -0.5 0 4,096 8,192 12,288 16,384 -0.25 0 4,096 8,192 Code FIGURE 2-2: VREF = 1.8V. 12,288 16,384 Code INL vs. Output Code: FIGURE 2-5: VREF = 1.8V. 1.5 DNL vs. Output Code: 0.5 Max DNL (LSB) 1 0.3 Max INL (LSB) DNL (LSB) 0.5 INL (LSB) 16,384 Code 0 0.1 -0.1 -0.5 Min INL (LSB) -0.3 -1 -1.5 1.5 Min DNL (LSB) 2 2.5 3 3.5 4 4.5 5 5.5 -0.5 1.5 2 Reference Voltage (V) FIGURE 2-3: INL vs. Reference Voltage. 2019 Microchip Technology Inc. 2.5 3 3.5 4 4.5 5 5.5 Reference Voltage (V) FIGURE 2-6: DNL vs. Reference Voltage. DS20006219A-page 11 MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 1 0.3 0.2 Max INL (LSB) 0 DNL (LSB) INL (LSB) 0.5 VREF = 5V Max DNL (LSB) 0.1 0 VREF = 5V -0.1 Min INL (LSB) Min DNL (LSB) -0.5 -0.2 -1 -40 -20 0 20 40 60 80 100 120 -0.3 -40 140 -20 0 Temperature (C) FIGURE 2-7: -20 fs = 1 Msps -60 -80 -100 -120 -140 -160 80 100 120 140 DNL vs. Temperature. VREF = 1.8V -20 SNR = 83.8 dBFS SINAD = 83.8 dBFS SFDR = 109.2 dBc THD = -104.9 dBc Offset = -1 LSB Resolution = 14-bit -40 60 MCP33151D-10 0 Amplitude (dBFS) Amplitude (dBFS) FIGURE 2-10: MCP33151D-10 VREF = 5V 40 Temperature (C) INL vs. Temperature. 0 20 fs = 1 Msps SNR = 79.1 dBFS SINAD = 79.0 dBFS SFDR = 105.6 dBc THD = -102.6 dBc Offset = -2 LSB Resolution = 14-bit -40 -60 -80 -100 -120 -140 0 100 200 300 400 -160 500 0 100 200 300 400 500 Frequency (kHz) Frequency (kHz) FIGURE 2-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. FIGURE 2-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V. MCP33151D-05 0 VREF = 5V fs = 0.5 Msps -60 -80 -100 -120 -140 -160 VREF = 1.8V -20 SNR = 83.8 dBFS SINAD = 83.7 dBFS SFDR = 106.9 dBc THD = -102.4 dBc Offset = -1 LSB Resolution = 14-bit -40 Amplitude (dBFS) Amplitude (dBFS) -20 MCP33151D-05 0 fs = 0.5 Msps SNR = 79.0 dBFS SINAD = 78.9 dBFS SFDR = 101.8 dBc THD = -98.8 dBc Offset = -2 LSB Resolution = 14-bit -40 -60 -80 -100 -120 -140 0 50 100 150 200 250 -160 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) FIGURE 2-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. FIGURE 2-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V. DS20006219A-page 12 2019 Microchip Technology Inc. MCP33151D/41D-XX Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. -95 14 82.5 110 80 13 75 1.5 2 2.5 3 3.5 4 4.5 5 THD (dB) SFDR(dB) -105 SNR (dB) SINAD(dB) ENOB 77.5 105 THD(dB) -100 100 12.5 12 5.5 -110 2 3 Reference Voltage (V) FIGURE 2-16: Voltage. 84.1 5 95 THD/SFDR vs. Reference 79.8 SNR (dB) 84 SNR (dB) 79.6 SINAD(dB) SINAD(dB) SNR/SINAD (dB) SNR/SINAD (dB) 4 Reference Voltage (V) FIGURE 2-13: SNR/SINAD/ENOB vs. Reference Voltage. 83.9 83.8 79.4 79.2 79 78.8 VREF = 5V 83.7 78.6 83.6 -50 0 50 100 VREF = 1.8V 78.4 -50 150 0 50 100 FIGURE 2-17: SNR/SINAD vs. Temperature: VREF = 1.8V. FIGURE 2-14: SNR/SINAD vs. Temperature: VREF = 5V. -105 114 THD(dB) SFDR(dB) -93 103 -94 102 THD(dB) SFDR(dB) -107 110 VREF = 5V 0 20 40 60 80 108 100 120 140 Temperature (C) FIGURE 2-15: THD/SFDR vs. Temperature: VREF = 5V. 2019 Microchip Technology Inc. THD(dB) THD(dB) 112 SFDR(dB) -95 -106 -20 150 Temperature (C) Temperature (C) -108 -40 SFDR(dB) 13.5 ENOB SNR/SINAD (dB) 85 -96 101 100 -97 VREF = 1.8V 99 -98 98 -99 97 -100 -40 -20 0 20 40 60 80 SFDR(dB) Note: 96 100 120 140 Temperature (C) FIGURE 2-18: THD/SFDR vs. Temperature: VREF = 1.8V. DS20006219A-page 13 MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 85 79 SNR (dB) SINAD(dB) 83 82 81 78 77.5 77 76.5 VREF = 5V 1 76 10 100 200 VREF = 1.8V 1 10 110 -75 THD (dB) SFDR (dB) 105 -80 100 -85 95 -90 90 -95 85 -100 80 110 -90 105 -95 100 -100 95 -105 90 -110 85 VREF = 5V 1 10 100 80 200 THD (dB) THD (dB) -70 115 THD (dB) SFDR (dB) SFDR (dB) -80 -115 -105 -110 75 VREF = 1.8V 1 10 100 Input Frequency (kHz) FIGURE 2-23: THD/SFDR vs. Input Frequency: VREF = 1.8V. 85 80 SNR (dB) SINAD(dB) SNR (dB) SINAD(dB) 84.5 SNR/SINAD (dB) SNR/SINAD (dB) 70 200 Input Frequency (kHz) FIGURE 2-20: THD/SFDR vs. Input Frequency: VREF = 5V. 84 83.5 83 -30 200 FIGURE 2-22: SNR/SINAD vs.Input Frequency: VREF = 1.8V. FIGURE 2-19: SNR/SINAD vs.Input Frequency: VREF = 5V. -85 100 Input Frequency (kHz) Input Frequency (kHz) SFDR (dB) 80 SNR (dB) SINAD(dB) 78.5 SNR/SINAD (dB) SNR/SINAD (dB) 84 79.5 79 78.5 VREF = 5V -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 2-21: SNR/SINAD vs. Input Amplitude: VREF = 5V. DS20006219A-page 14 78 -30 VREF = 1.8V -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 2-24: SNR/SINAD vs. Input Amplitude: VREF = 1.8V. 2019 Microchip Technology Inc. MCP33151D/41D-XX Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. -95 115 -99 107 -105 -100 106 -101 105 -102 104 105 VREF = 5V -25 -20 -15 -10 -5 0 100 -103 -30 VREF = 1.8V -25 Amplitude (dBFS) -15 -10 80 84.2 13.6 83.4 13.2 82.6 SNR (dB) SINAD(dB) ENOB 81.8 12.8 SNR/SINAD (dB) 14 100 12.4 79.2 13.4 78.4 12.8 77.6 SNR (dB) SINAD(dB) ENOB 76.8 250 500 12 1000 76 25 -90 50 100 112 11 1000 114 -98 104 -102 100 -106 THD(dB) SFDR(dB) 96 THD(dB) 108 -94 110 -98 106 -102 102 -106 98 VREF = 5V VREF = 1.8V 250 500 92 1000 -110 25 50 Sample Rate (kSPS) THD/SFDR vs Sample Rate: 2019 Microchip Technology Inc. 500 -90 SFDR(dB) THD(dB) -94 FIGURE 2-27: VREF = 5V. 250 FIGURE 2-29: SNR/SINAD/ENOB vs. Sample Rate: VREF = 1.8V. THD(dB) SFDR(dB) 100 11.6 Sample Rate (kSPS) FIGURE 2-26: SNR/SINAD/ENOB vs. Sample Rate: VREF = 5V. 50 12.2 VREF = 1.8V Sample Rate (kSPS) -110 25 103 14 VREF = 5V 50 0 FIGURE 2-28: THD/SFDR vs. Input Amplitude: VREF = 1.8V. ENOB 85 81 25 -5 Amplitude (dBFS) FIGURE 2-25: THD/SFDR vs. Input Amplitude: VREF = 5V. SNR/SINAD (dB) -20 ENOB -110 -30 THD(dB) 110 THD(dB) -100 SFDR(dB) THD (dB) SFDR(dB) SFDR(dB) THD (dB) SFDR(dB) SFDR(dB) Note: 100 250 500 94 1000 Sample Rate (kSPS) FIGURE 2-30: VREF = 1.8V. THD/SFDR vs Sample Rate: DS20006219A-page 15 MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 10 10 5 86 VREF = 5V 841918 84 82 CMRR (dB) Occurrences 8 6 4 80 78 76 184932 74 21725 -2 -1 0 1 2 3 10 -2 10 1.2 500 0.8 250 0 0.0 -250 -0.4 -500 -0.8 -750 -1000 -40 -1.2 VREF = 5V -20 0 20 40 60 80 100 120 -1.6 140 1 10 2 10 3 3.9 OFFSET ERROR GAIN ERROR 650 3.0 450 2.0 250 1.1 50 0.2 -150 -0.7 VREF = 1.8V -350 -40 -20 0 20 40 60 80 100 -1.6 140 120 Temperature (C) FIGURE 2-32: Offset and Gain Error vs. Temperature: VREF = 5V. MCP33151D-10 FIGURE 2-35: Offset and Gain Error vs. Temperature: VREF = 1.8V. MCP33151D-05 5 0.5 3 0.4 2.4 0.8 4 n tio 0.7 0.6 0.5 er ow lP ta To 3.5 n Co 3 ) (AV DD 0.4 p sum = V 1.8 2.5 2 I DDAN V) 0.3 I IO_DATA 0.2 (DV IO I REF (V REF 0.1 = 3.3 1.5 1 = 5V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 FIGURE 2-33: Power Consumption vs. Sample Rate, MCP33151D-10: CLOAD_SDO = 20 pF. ) .8V 0.3 (AV DD =1 I DDAN Tota I IO_DATA 0.1 (DV IO I REF (V REF = 0 0.1 1.8 on mpti nsu Co wer l Po 0.2 0.5 Sample Rate (Msps) DS20006219A-page 16 Current (mA) 4.5 Total Power (mW) 0.9 Current (mA) 10 CMRR vs. Input Frequency: Temperature (C) 1 0 850 0.4 OFFSET ERROR GAIN ERROR FIGURE 2-34: VREF = 5V. OFFSET/GAIN ERROR (uV) 1.6 750 OFFSET/GAIN ERROR (LSB) OFFSET/GAIN ERROR (uV) Shorted Input Histogram: 1000 10 Frequency (kHz) Output Code FIGURE 2-31: VREF = 5V. -1 0.2 0.3 0.4 1.2 ) = 3.3V 0.6 Total Power (mW) 0 -3 VREF = 5V 72 -3 10 1 OFFSET/GAIN ERROR (LSB) 2 5V) 0 0.5 Sample Rate (Msps) FIGURE 2-36: Power Consumption vs. Sample Rate, MCP33151D-05: CLOAD_SDO = 20 pF. 2019 Microchip Technology Inc. MCP33151D/41D-XX Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. MCP33151D-10 1 5 4 ion Total Power Consumpt 0.7 0.6 3.5 I DDAN (AV DD = 1.8V) 0.5 3 IIO_DATA (DVIO = 3.3V) 0.4 0.3 I REF (V REF = 5V) 2.5 2 1.5 0.2 1 0.1 0.5 0 -40 -25 -10 5 0 20 35 50 65 80 95 110 125 ion 1.8 IIO_DATA (DVIO = 3.3V) 0.2 1.2 IREF (VREF = 5V) 0.1 0.6 0 20 35 50 65 80 95 110 125 FIGURE 2-39: Power Consumption vs. Temperature, MCP33151D-05: CLOAD_SDO = 20 pF. 5 12 10 Total Power Consumption 6 IIO_STBY (DVIO = 3.3V) 1 4 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 8 Total Power ( W) Current ( A) Total Power Consumpt 14 IDDAN_STBY (AVDD = 1.8V) 6 2 0.3 2.4 16 7 3 I DDAN (AV DD Temperature (C) FIGURE 2-37: Power Consumption vs. Temperature, MCP33151D-10: CLOAD_SDO = 20 pF. 8 = 1.8V) 0.4 0 -40 -25 -10 5 Temperature (C) 4 3 Total Power (mW) Current (mA) 0.8 MCP33151D-05 4.5 Current (mA) 0.9 0.5 Total Power (mW) Note: 2 0 20 35 50 65 80 95 110 125 Temperature (C) FIGURE 2-38: Power Consumption vs. Temperature during Shutdown (Standby). 2019 Microchip Technology Inc. DS20006219A-page 17 MCP33151D/41D-XX NOTES: DS20006219A-page 18 2019 Microchip Technology Inc. MCP33151D/41D-XX 3.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33141D-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 0.2 0.2 VREF = 5V VREF = 5V 0.1 DNL (LSB) INL (LSB) 0.1 0 -0.1 -0.1 -0.2 0 -0.2 0 1,024 2,048 3,072 4,096 0 1,024 2,048 FIGURE 3-1: VREF = 5V. 3,072 INL vs. Output Code: FIGURE 3-4: VREF = 5V. 0.2 DNL vs. Output Code: 0.2 VREF = 1.8V VREF = 1.8V 0.1 DNL (LSB) INL (LSB) 0.1 0 -0.1 -0.2 0 -0.1 0 1,024 2,048 3,072 -0.2 4,096 0 1,024 2,048 Code FIGURE 3-2: VREF = 1.8V. 3,072 4,096 Code INL vs. Output Code: FIGURE 3-5: VREF = 1.8V. 0.5 DNL vs. Output Code: 0.3 0.25 0.15 Max INL (LSB) Max DNL (LSB) DNL (LSB) INL (LSB) 4,096 Code Code 0 0 Min DNL (LSB) -0.25 -0.5 1.5 -0.15 Min INL (LSB) 2 2.5 3 3.5 4 4.5 5 5.5 -0.3 1.5 2 Reference Voltage (V) FIGURE 3-3: INL vs. Reference Voltage. 2019 Microchip Technology Inc. 2.5 3 3.5 4 4.5 5 5.5 Reference Voltage (V) FIGURE 3-6: DNL vs. Reference Voltage. DS20006219A-page 19 MCP33151D/41D-XX Note: Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 0.5 0.5 VREF = 5V VREF = 5V 0.25 Max INL (LSB) Max DNL (LSB) DNL (LSB) INL (LSB) 0.25 0 0 Min INL (LSB) Min DNL (LSB) -0.25 -0.25 -0.5 -40 -20 0 20 40 60 80 100 120 -0.5 -40 140 -20 0 Temperature (C) FIGURE 3-7: -80 -100 -120 100 120 140 fs = 1 Msps -20 Amplitude (dBFS) -60 80 DNL vs. Temperature. VREF = 1.8V SNR = 73.9 dBFS SINAD = 73.9 dBFS SFDR = 100.6 dBc THD = -98.7 dBc Offset = 0 LSB Resolution = 12-bit -40 60 MCP33141D-10 0 fs = 1 Msps -20 Amplitude (dBFS) FIGURE 3-10: MCP33141D-10 VREF = 5V 40 Temperature (C) INL vs. Temperature. 0 20 SNR = 73.0 dBFS SINAD = 73.0 dBFS SFDR = 101.0 dBc THD = -100.0 dBc Offset = -1 LSB Resolution = 12-bit -40 -60 -80 -100 0 100 200 300 400 -120 500 0 100 200 300 400 500 Frequency (kHz) Frequency (kHz) FIGURE 3-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. FIGURE 3-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V. MCP33141D-05 0 VREF = 5V -40 -60 -80 -100 -120 fs = 0.5 Msps -20 SNR = 73.8 dBFS SINAD = 73.8 dBFS SFDR = 99.6 dBc THD = -99.9 dBc Offset = -1 LSB Resolution = 12-bit Amplitude (dBFS) Amplitude (dBFS) VREF = 1.8V fs = 0.5 Msps -20 MCP33141D-05 0 SNR = 73.0 dBFS SINAD = 73.0 dBFS SFDR = 100.7 dBc THD = -94.9 dBc Offset = -1 LSB Resolution = 12-bit -40 -60 -80 -100 0 50 100 150 200 250 -120 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) FIGURE 3-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. FIGURE 3-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V. DS20006219A-page 20 2019 Microchip Technology Inc. MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 12.5 12 THD(dB) 73 ENOB SNR/SINAD (dB) 74 72 11.5 SNR (dB) SINAD(dB) ENOB 71 1.5 2 2.5 3 3.5 4 4.5 5 11 5.5 -96 100.5 -97 100 -98 99.5 -99 THD (dB) SFDR(dB) -100 98 -102 97.5 -103 2 3 4 5 97 Reference Voltage (V) FIGURE 3-16: Voltage. FIGURE 3-13: SNR/SINAD/ENOB vs. Reference Voltage. 73.86 THD/SFDR vs. Reference 73.2 SNR (dB) SINAD(dB) SNR (dB) 73.15 SINAD(dB) SNR/SINAD (dB) 73.84 SNR/SINAD (dB) 98.5 -101 Reference Voltage (V) 73.82 73.8 73.78 99 SFDR(dB) Note: VREF = 5V 73.1 73.05 73 72.95 VREF = 1.8V 72.9 73.76 -50 0 50 100 72.85 -50 150 0 50 100 150 Temperature (C) Temperature (C) FIGURE 3-17: SNR/SINAD vs. Temperature: VREF = 1.8V. FIGURE 3-14: SNR/SINAD vs. Temperature: VREF = 5V. -98.2 99 -92 99 -93 98 98 97.5 -98.8 THD(dB) THD(dB) -98.6 SFDR(dB) 98.5 -98.4 -94 THD(dB) SFDR(dB) 97 -95 VREF = 1.8V 96 -96 SFDR(dB) THD(dB) SFDR(dB) 95 VREF = 5V -99 -40 -20 0 20 40 60 80 97 100 120 140 Temperature (C) FIGURE 3-15: THD/SFDR vs. Temperature: VREF = 5V. 2019 Microchip Technology Inc. -97 -40 -20 0 20 40 60 80 94 100 120 140 Temperature (C) FIGURE 3-18: THD/SFDR vs. Temperature: VREF = 5V. DS20006219A-page 21 MCP33151D/41D-XX Note: Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 73 72.6 SNR/SINAD (dB) 72.9 SNR/SINAD (dB) 72.4 SNR (dB) SINAD(dB) 72.8 72.7 SNR (dB) SINAD(dB) 72.2 72 71.8 71.6 71.4 72.6 71.2 1 71 10 100 200 VREF = 1.8V 1 10 -80 105 -75 100 -90 95 -95 90 -100 85 10 100 80 200 THD (dB) -85 VREF = 5V 105 THD (dB) SFDR (dB) SFDR (dB) THD (dB) THD (dB) SFDR (dB) 1 -80 100 -85 95 -90 90 -95 85 -100 -105 80 VREF = 1.8V 1 10 Input Frequency (kHz) 100 Input Frequency (kHz) 75 74 SNR (dB) SINAD(dB) SNR (dB) SINAD(dB) 74.5 SNR/SINAD (dB) SNR/SINAD (dB) 75 200 FIGURE 3-23: THD/SFDR vs. Input Frequency: VREF = 1.8V. FIGURE 3-20: THD/SFDR vs. Input Frequency: VREF = 5V. 74 73.5 73 -30 200 FIGURE 3-22: SNR/SINAD vs. Input Frequency: VREF = 1.8V. FIGURE 3-19: SNR/SINAD vs. Input Frequency: VREF = 5V. -105 100 Input Frequency (kHz) Input Frequency (kHz) SFDR (dB) 72.5 VREF = 5V 73.5 73 72.5 VREF = 5V -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 3-21: SNR/SINAD vs. Input Amplitude: VREF = 5V. DS20006219A-page 22 72 -30 VREF = 1.8V -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 3-24: SNR/SINAD vs. Input Amplitude: VREF = 1.8V. 2019 Microchip Technology Inc. MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. -90 105 -90 105 -100 95 -95 100 -100 95 THD(dB) 100 THD(dB) -95 VREF = 1.8V VREF = 5V -25 -20 -15 -10 -5 0 90 -105 -30 -25 Input Amplitude (dBFS) -10 73.4 12.6 72.8 12.2 SNR (dB) SINAD(dB) ENOB 50 100 250 11.8 11.4 12.4 71.8 11.8 71.2 SNR (dB) SINAD(dB) ENOB 70.6 500 11 1000 70 25 50 100 110 -86 -96 102 -100 98 -104 94 THD(dB) 106 SFDR(dB) THD(dB) 500 10 1000 109 THD(dB) SFDR(dB) -92 -90 105 -94 101 -98 97 -102 93 VREF = 1.8V VREF = 5V 250 500 90 1000 Sample Rate (kSPS) THD/SFDR vs. Sample 2019 Microchip Technology Inc. 250 FIGURE 3-29: SNR/SINAD/ENOB vs. Sample Rate: VREF = 1.8V. THD(dB) SFDR(dB) FIGURE 3-27: Rate: VREF = 5V. 10.6 Sample Rate (kSPS) -88 100 11.2 VREF = 1.8V FIGURE 3-26: SNR/SINAD/ENOB vs. Sample Rate: VREF = 5V. 50 90 72.4 Sample Rate (kSPS) -108 25 0 13 VREF = 5V 71 25 -5 73 SNR/SINAD (dB) 13 ENOB SNR/SINAD (dB) 74 71.6 -15 FIGURE 3-28: THD/SFDR vs. Input Amplitude: VREF = 1.8V. FIGURE 3-25: THD/SFDR vs. Input Amplitude: VREF = 5V. 72.2 -20 Input Amplitude (dBFS) ENOB -105 -30 SFDR(dB) THD (dB) SFDR(dB) SFDR(dB) THD (dB) SFDR(dB) SFDR(dB) Note: -106 25 50 100 250 500 89 1000 Sample Rate (kSPS) FIGURE 3-30: THD/SFDR vs. Sample Rate: VREF = 1.8V. DS20006219A-page 23 MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. 105 86 84 82 CMRR (dB) Occurrences VREF = 5V 779082 8 6 4 80 78 76 269494 2 74 0 -3 -2 -1 0 1 2 VREF = 5V 72 -3 10 3 10 -2 10 Output Code Shorted Input Histogram: OFFSET ERROR GAIN ERROR 1000 500 0.6 1000 0.4 800 0.2 0 0.0 -500 -0.2 -1000 -0.4 -1500 -0.6 -2000 -2500 -40 -0.8 VREF = 5V -20 0 20 40 60 80 100 -1.0 140 120 FIGURE 3-34: VREF = 5V. OFFSET/GAIN ERROR (uV) OFFSET/GAIN ERROR (uV) 1500 OFFSET/GAIN ERROR (LSB) FIGURE 3-31: VREF = 5V. 10 0 10 1 10 2 10 3 CMRR vs. Input Frequency: 1.1 OFFSET ERROR GAIN ERROR 0.9 600 0.7 400 0.5 200 0.2 0 0.0 -200 -0.2 -400 -0.5 -600 -0.7 -800 -1000 -40 -0.9 VREF = 1.8V -20 0 20 Temperature (C) 40 60 80 100 -1.1 140 120 Temperature (C) FIGURE 3-32: Offset and Gain Error vs. Temperature: VREF = 5V. FIGURE 3-35: Offset and Gain Error vs. Temperature: VREF = 1.8V. MCP33141D-10 MCP33141D-05 1 5 0.5 3 0.4 2.4 0.8 4 n tio mp 0.7 0.6 tal To 0.5 3.5 o rC we Po u ns 3 ) (AV DD 0.4 I DDAN 0.3 I REF (V REF 0.2 = V 1.8 2.5 2 = 5V) 1.5 1 3V) I IO_DATA 0.1 (DV IO = 3. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 (AV DD I DDAN 0.2 FIGURE 3-33: Power Consumption vs. Sample Rate, MCP33141D-10: CLOAD_SDO = 20 pF. =1 1.8 tion mp r owe al P Tot 0.1 0 0.1 ) .8V 0.3 su Con I REF (V REF 1.2 = 5V) V) V = 3.3 I IO_DATA (D IO 0.5 Sample Rate (Msps) DS20006219A-page 24 Current (mA) 4.5 Total Power (mW) 0.9 Current (mA) -1 Frequency (kHz) OFFSET/GAIN ERROR (LSB) 10 0.2 0.3 0.4 0.6 Total Power (mW) Note: 0 0.5 Sample Rate (Msps) FIGURE 3-36: Power Consumption vs. Sample Rate, MCP33141D-05: CLOAD_SDO = 20 pF. 2019 Microchip Technology Inc. MCP33151D/41D-XX Note: Unless otherwise specified, all parameters apply for TA = +25C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz. MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz. MCP33141D-10 1 3.5 8V) V DD = 1. I DDAN (A 3 2.5 0.4 2 I 0.3 0.2 REF (V REF = 5V) IIO_DATA (DVIO = 3.3V) 0.1 1.5 1 0 20 35 50 65 80 95 110 125 Total Power Consumpt 1.8 0.2 IREF (VREF = 5V) 1.2 ion I IO_DATA (DV IO = 3.3V) 0.1 0.6 8 0 20 35 50 65 80 95 110 125 Temperature (C) FIGURE 3-37: Power Consumption vs. Temperature, MCP33141D-10: CLOAD_SDO = 20 pF. FIGURE 3-39: Power Consumption vs. Temperature, MCP33141D-05: CLOAD_SDO = 20 pF. 16 14 IDDAN_STBY (AVDD = 1.8V) 6 5 12 10 Total Power Consumption 6 IIO_STBY (DVIO = 3.3V) 1 4 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 8 Total Power ( W) 7 Current ( A) 0.3 0 -40 -25 -10 5 Temperature (C) 2 2.4 8V) V DD = 1. I DDAN (A 0.5 0 -40 -25 -10 5 3 0.4 Current (mA) Current (mA) 4 ion Total Power Consumpt 0.5 4 3 4.5 0.7 0.6 0.5 Total Power (mW) 0.9 0.8 MCP33141D-05 5 Total Power (mW) Note: 2 0 20 35 50 65 80 95 110 125 Temperature (C) FIGURE 3-38: Power Consumption vs. Temperature during Shutdown (Standby). 2019 Microchip Technology Inc. DS20006219A-page 25 MCP33151D/41D-XX NOTES: DS20006219A-page 26 2019 Microchip Technology Inc. MCP33151D/41D-XX 4.0 PIN DESCRIPTIONS MSOP-10 TDFN-10 * * Includes Exposed Thermal Pad (see Table 4-1). FIGURE 4-1: Pin Configurations. TABLE 4-1: PIN FUNCTION TABLE Pin Number Pin Name Description MSOP-10 TDFN-10 1 1 VREF Reference voltage input (AVDD - 5.1V). This pin should be decoupled with a 10 F tantalum capacitor. 2 2 AVDD DC supply voltage input for analog section (1.8V). This pin should be decoupled with a 1 F ceramic capacitor. 3 3 AIN+ Differential positive analog input. 4 4 AIN- Differential negative analog input. 5 5 GND Power supply ground reference. This pin is a common ground for both the analog power supply (AVDD) and digital I/O supply (DVIO). 6 6 CNVST Conversion-start control and active-low SPI chip-select digital input. A new conversion is started on the rising edge of CNVST. When the conversion is complete, output data is available at SDO by lowering CNVST. 7 7 SDO SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK clock, with MSB first. 8 8 SCLK SPI-compatible serial data clock digital input. The ADC output is synchronously shifted out by this clock. 9 9 SDI SPI-compatible serial data digital input. Tie to DVIO for normal operation. 10 10 DVIO DC supply voltage for digital input/output interface (1.7V - 5.5V). This pin should be decoupled with a 0.1 F ceramic capacitor. -- 11 EP 2019 Microchip Technology Inc. Exposed Thermal Pad. Not internally bonded (NC). DS20006219A-page 27 MCP33151D/41D-XX 4.1 Supply Voltages (AVDD, DVIO) 4.3 The device has two power supply pins: (a) 1.8V analog power supply (AVDD), and (b) 1.7V to 5.5V digital input/output interface power supply (DVIO). Since DVIO has a very wide voltage range, some I/O interface signal parameters have slightly different timing specifications depending on the DVIO value. See Serial Interface Timing Specifications for details. Note: 4.2 Proper decoupling capacitors (1 F to AVDD, 0.1 F to DVIO) should be mounted as close as possible to the respective pins. Reference Voltage (VREF) The device requires a single-ended external reference voltage (VREF). The external input reference range is from AVDD to 5.1V. This reference voltage sets the differential input full-scale range from -VREF to +VREF. The reference pin needs a tantalum decoupling capacitor (10 F, 10V rating). Additional multiple ceramic capacitors can be added in parallel to decouple high-frequency noise. 4.2.1 Power-Up Sequence and Auto-Calibration The device will perform an automatic calibration on power-up approximately 40 ms after all three power rails (AVDD, DVIO, and VREF) are powered by their respective voltage supplies. The calibration process will take approximately 400 ms to complete before the device will be ready for acquisition. To avoid potential auto-calibration issues, all supplies must be fully stabilized < 40 ms from the moment power is initially supplied. All digital activity must be avoided prior to and during device calibration. At higher operating temperatures (>85C) it may be necessary to provide additional time for the device to complete calibration (up to 550ms at 125C). Therefore it is advisable to wait at least 450-500 ms following power-on before initiating any other activity. Otherwise, it may be necessary to send a manual recalibration command to ensure proper operation. See Figure 4-2 for example power-on operation timing, and refer to Section 6.2 "Recalibrate Command" for more details regarding initiating manual recalibration. Once the device finishes calibration it will automatically enter Acquisition (ACQ) mode. VOLTAGE REFERENCE SELECTION The performance of the voltage reference has a large impact on the accuracy of high-precision data acquisition systems. The voltage reference should have high accuracy, low-noise, and low-temperature drift. A 0.1% output accuracy of the reference directly corresponds to 0.1% absolute accuracy of the ADC output. The RMS output noise voltage of the reference must be less than 1/2 LSB of the ADC. Wait (tWAIT = ~40 ms) ADC State WAIT Device Calibration (tCAL = ~00ms) ACQUISITION MODE CALIBRATION AVDD VREF DVIO FIGURE 4-2: Note: Power-Up Sequence and Auto-Calibration Timing Diagram. Unlike manual recalibration, there will be no activity on SDO to indicate completion of auto-calibration. Refer to Section 6.2 "Recalibrate Command" for more details. DS20006219A-page 28 2019 Microchip Technology Inc. MCP33151D/41D-XX 5.0 DEVICE OVERVIEW When the MCP33151D/41D-XX is first powered-up, it automatically performs a self-calibration and enters a low-current input acquisition mode (Standby). The external reference voltage (VREF), ranging from AVDD to 5.1V, sets the differential input full-scale range (FSR) from -VREF to +VREF. VREF SW1 AIN+ + RSON C S+ SW2+ (350) (10 pF) CPIN D2 ILEAKAGE The differential input signal needs an appropriate input common-mode voltage from 0V to VREF, depending on the input signal condition. VREF/2 is typically used for a symmetric differential input. During input acquisition (Standby), the internal input sampling capacitors are connected to the input signal, while most of the internal analog circuits are shutdown to save power. During this input acquisition time (tACQ), the device consumes a typical current of 1.5 A. Sample VIN+ VT = 0.6V D1 (~1 nA) VREF Sample VIN- VT = 0.6V D1 SW1- AINCPIN RSON C S- SW2- (350) (10 pF) D2 ILEAKAGE (~1 nA) The user can operate the device with an easy-to-use, SPI-compatible, 3-wire interface. The device initiates data conversion on the rising edge of the conversion-start control (CNVST). The data conversion time (tCNV) is set by the internal clock. Once the conversion is complete and the host lowers CNVST, the output data is available on SDO and the device automatically starts the next input acquisition. During this input acquisition time (tACQ), the user can clock out the output data by providing the SPI-compatible serial clock (SCLK). The device provides conversion data with no missing codes. This ADC device family has a large input full-scale range, high precision, high throughput with no output latency, and is an ideal choice for various ADC applications. 5.1 Analog Inputs Figure 5-1 shows a simplified equivalent circuit of the differential input architecture with a switched capacitor input stage. The input sampling capacitors (CS+ and CS-) are about 10 pF each. The back-to-back diodes (D1 - D2) at each input are ESD protection diodes. Note that these ESD diodes are tied to VREF, so that each input signal can swing from 0V to +VREF and from -VREF to +VREF differentially. During input acquisition (Standby), the sampling switches are closed and each input sees the sampling capacitor ( 10 pF) in series with the on-resistance of the sampling switch, RSON ( 350). Where: CS +, CS - = RSON = On-resistance of the sampling switch 350 CPIN = Package pin + ESD capacitor 2 pF. input sample and hold capacitor 10 pF, FIGURE 5-1: Simplified Equivalent Analog Input Circuit. 5.1.1 ABSOLUTE MAXIMUM INPUT VOLTAGE RANGE The input voltage at each input pin (AIN+ and AIN-) must meet the following absolute maximum input voltage limits: * (VIN+, VIN-) < VREF + 0.1V * (VIN+, VIN-) > GND - 0.1V Note: The ESD diodes at the analog input pins are biased from VREF. Any input voltage outside the absolute maximum range can turn on the input ESD protection diodes and results in input leakage current which may cause conversion errors and permanent damage to the device. Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. For high-precision data conversion applications, the input voltage needs to be fully settled within 1/2 LSB during the input acquisition period (tACQ). The settling time is directly related to the source impedance: A lower impedance source results in faster input settling time. Although the device can be driven directly with a low impedance source, using a low-noise input driver, such as the MCP6D11, is highly recommended. 2019 Microchip Technology Inc. DS20006219A-page 29 MCP33151D/41D-XX 5.1.2 INPUT VOLTAGE RANGE The differential input (VIN) and common-mode voltage (VCM) at the input pins are defined by Equation 5-1: EQUATION 5-1: DIFFERENTIAL INPUT V IN = V IN + -V IN - V ++V IN IN VCM = --------------------------2 Where: VIN+ = the input at the AIN+ pin, VIN- = the input at the AIN- pin. The input signal swings around an input common-mode voltage (VCM), typically centered at VREF/2 for the best performance. The absolute value of the differential input (VIN) needs to be less than the reference voltage. The device will output saturated output codes if the absolute value of the input (VIN) is greater than the reference voltage. Note: Saturation output codes: 01111111111111 for VIN > VREF 10000000000000 for VIN < -VREF The differential input full-scale voltage range (FSR) is given by the external reference voltage (VREF) setting (see Equation 5-2). EQUATION 5-2: FSR AND INPUT RANGE Input Full-Scale Range (FSR) = 2V REF Input Range: - V REF V IN VREF - 1 LSB 5.2 Analog Input Conditioning Circuits The MCP33151D/41D-XX supports various input types, such as: fully-differential inputs, arbitrary waveform inputs and single-ended inputs. 5.2.1 FULLY-DIFFERENTIAL INPUT SIGNALS The MCP33151D/41D-XX provides the best linearity performance with fully-differential inputs. Figure 5-2 shows an example of a fully-differential input conditioning circuit with a differential input driver followed by an RC anti-aliasing filter. Figure 5-3 shows its transfer function. The front-end differential driver provides a low output impedance, which provides fast settling of the analog inputs during the acquisition phase and provides isolation between the signal source and the ADC. The RC low-pass anti-aliasing filter band-limits the output noise of the input driver and attenuates the kick-back noise spikes from the ADC during conversion. Figure 5-2 is the reference circuit that is used to collect most of the linearity performance data shown in Section 1.0 "Key Electrical Characteristics". The differential input driver shown in Figure 5-2 can be replaced with a low noise dual-channel op-amp. See Section 5.3 "ADC Input Driver Selection" for the driver selection. 5.2.2 ARBITRARY WAVEFORM INPUT SIGNALS The MCP33151D/41D-XX can convert input signals with arbitrary waveforms at the inputs AIN+ and AIN-. These inputs can be symmetric, non-symmetric or independent with respect to each other. In the arbitrary input configuration, each ADC analog input is connected to a single ended source ranging from 0V to VREF. In this case, the ADC converts the voltage difference between the two input signals. Figure 5-4 shows the configuration example for the arbitrary input signals. 5.2.3 SINGLE-ENDED INPUT SIGNALS Although the MCP33151D/41D-10 is a fully-differential input device, it can also convert single-ended input signals. The most commonly recommended single-ended configurations are: * pseudo-differential bipolar configuration, and * pseudo-differential unipolar configuration. 5.2.3.1 Pseudo-Differential Bipolar Configuration In the pseudo-differential bipolar configuration, one of the ADC analog inputs (typically AIN-) is driven with a fixed DC voltage (typically VREF/2), while the other (AIN+) is connected to a single-ended signal in the range 0V to VREF. In this case, the ADC converts the voltage difference between the single-ended signal and the DC voltage. Figure 5-5 shows the configuration example and Figure 5-6 shows its transfer function. The differential input (VIN) between the two differential ADC analog input pins (AIN+, AIN-) swings from -VREF to +VREF centered at the input common-mode voltage (VOCM). DS20006219A-page 30 2019 Microchip Technology Inc. MCP33151D/41D-XX 5.2.3.2 Pseudo-Differential Unipolar Configuration In the pseudo-differential unipolar input configuration, one of the ADC analog inputs (typically AIN-) is connected to ground, while the other (AIN+) is connected to a single ended signal in the range 0V to VREF. In this case, the ADC converts the voltage difference between the single ended signal and ground. Figure 5-7 shows the configuration example and Figure 5-8 shows its transfer function. VDC Voltage Reference VREF (MCP1501) CR (Note 2) Differential Inputs VREF 1.8V 1.8V to 5.5V AVDD DVIO 10 F RF RG VREF VREF/2 0V R1 VREF AIN+ 0V SDI C1 VREF/2 MCP331x1D-XX VOCM CNVST R1 VREF AIN0V RG RF Input Driver (Note 1) Note fc = SDO VREF VREF/2 0V C1 (PIC32MZ) GND 1 2R1C1 1: Contact Microchip Technology Inc. for availability of MCP6D11 differential driver application circuits. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 5-2: Host Device SCLK Input Conditional Circuit for Fully-Differential Input. Digital Output Code (Two's Complement) 2n/2 - 1 -VREF +VREF - 1 LSB 0 VIN Differential Input Voltage - 2n/2 Available VIN range FIGURE 5-3: Transfer Function for Figure 5-2. 2019 Microchip Technology Inc. DS20006219A-page 31 MCP33151D/41D-XX Voltage Reference VREF (MCP1501) CR (Note 2) VDC 1.8V 1.8V to 5.5V AVDD DVIO 10 F Arbitrary Waveform Differential Input VREF R1 VREF AIN+ SDI C1 0V MCP331x1D-XX CNVST R1 Low Noise Input Buffer (Note 1) Note SDO C1 0V fc = (PIC32MZ) GND 1 2R1C1 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 5-4: Host Device SCLK AIN- VREF Input Configuration for Arbitrary Waveform Input Signals. VDC Voltage Reference VREF (MCP1501) CR (Note 2) 1.8V 1.8V to 5.5V AVDD DVIO 10 F Low Noise Input Buffer (Note 1) Single-Ended Input VREF VREF/2 0V R1 VREF AIN+ VREF SDI C1 0V MCP331x1D-XX R1 C1 Host Device SCLK AINVREF/2 CNVST (PIC32MZ) SDO GND 1 F fc = Note 1 2R1C1 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 5-5: Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal. Digital Output Code (Two's Complement) 2n/2 - 1 2n/4 -VREF -VREF/2 0 +VREF/2 +VREF - 1 LSB VIN Analog Input Voltage - 2n/4 Available VIN range - 2n/2 FIGURE 5-6: DS20006219A-page 32 Transfer Function for Figure 5-5. 2019 Microchip Technology Inc. MCP33151D/41D-XX VDC Voltage Reference VREF (MCP1501) CR (Note 2) 1.8V 1.8V to 5.5V AVDD DVIO 10 F Low Noise Input Buffer (Note 1) Single-Ended Input VREF VREF/2 0V R1 VREF AIN+ VREF VREF/2 0V SDI C1 MCP331x1D-XX R1 GND 1 2R1C1 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 5-7: (PIC32MZ) SDO C1 Note Host Device SCLK AIN- fc = CNVST Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal. Digital Output Code (Two's Complement) 2n/2 - 1 2n/4 -VREF -VREF/2 0 +VREF/2 +VREF VIN Analog Input Voltage Available VIN range - 2n/4 - 2n/2 FIGURE 5-8: Transfer Function for Figure 5-7. 2019 Microchip Technology Inc. DS20006219A-page 33 MCP33151D/41D-XX 5.3 ADC Input Driver Selection The noise and distortion of the ADC input driver can degrade the dynamic performance (SNR, SFDR, and THD) of the overall ADC application system. Therefore, the ADC input driver needs better performance specifications than the ADC itself. The data sheet of the driver typically shows the output noise voltage and harmonic distortion parameters. Figure 5-9 shows a simplified system noise presentation block diagram for the front-end driver and ADC. When the ADC is operating with a full-scale input range, the ADC input-referred RMS noise is approximated as shown in Equation 5-5: EQUATION 5-5: ADC INPUT-REFERRED NOISE VN_ADC Input-Referred Noise (V) FSR = ---------- 10 2 2 SNR - ---------20 SNR Front-End Driver VN_ADC V REF - --------20 = ------------ 10 2 Input-Referred Noise SNR R -+ -+ ADC C Simplified System Noise * Unity Gain Bandwidth: An input driver with higher bandwidth usually results in better overall linearity performance. Typically, the driver should have the unity gain bandwidth greater than 5 times the -3 dB cutoff frequency of the anti-aliasing filter: EQUATION 5-3: BANDWIDTH REQUIREMENT FOR ADC INPUT DRIVER BW Input Driver 5 f B Where: * Noise Contribution from the Front-End Driver: The noise from the input driver can degrade the ADC's SNR performance. Therefore, the selected input driver should have the lowest possible broadband noise density and 1/f noise. When an anti-aliasing filter is used after the input driver, the output noise density of the input driver is integrated over the -3 dB bandwidth of the filter. Equation 5-6 shows the RMS output noise voltage calculation using the RC filter's bandwidth and noise density (eN) of the input driver. GN in Equation 5-6 is the noise gain of the driver amplifier and becomes 1 for a unity gain buffer driver. (Hz) 5 -------------- , for a single-pole RC filter. 2 RC fB = -3 dB bandwidth of RC anti-aliasing filter, as shown in Figure 5-9. * Distortion: The nonlinearity characteristics of the input driver cause distortions in the ADC output. Therefore, the input driver should have less distortion than the ADC itself. The recommended total harmonic distortion (THD) of the driver is at least 10 dB less than that of the ADC: EQUATION 5-4: , for single-ended input. Where FSR is the input full-scale range of the ADC. VN_RMS_Driver Noise FIGURE 5-9: Representation. V REF - --------20 = ------------ 10 2 2 , for differential input; RECOMMENDED THD FOR ADC INPUT DRIVER THD Input Driver THD ADC - 10 * ADC Input-Referred Noise: (dB) EQUATION 5-6: NOISE FROM FRONT-END DRIVER AMPLIFIER eN VN_RMS_Driver_Noise = G N ------- fB 2 V Where eN is the broadband noise density (V/Hz) of the front-end driver amplifier and is typically given in its data sheet. In Equation 5-6, 1/f noise (eNFlicker) is ignored assuming it is very small compared to the broadband noise (eN). For high precision ADC applications, the noise contribution from the front-end input driver amplifier is typically constrained to be less than about 20% (or 1/5 times) of the ADC input-referred noise as shown in Equation 5-7: EQUATION 5-7: RECOMMENDED ADC INPUT DRIVER NOISE 1 V N_RMS_Driver_Noise --- V N_ADC_Input-Referred_Noise 5 DS20006219A-page 34 2019 Microchip Technology Inc. MCP33151D/41D-XX Using Equation 5-5 to Equation 5-7, the recommended noise voltage density (eN) limit of the ADC input driver is expressed in Equation 5-8: EQUATION 5-8: TABLE 5-2: NOISE DENSITY FOR ADC INPUT DRIVER ADC (Note 1) eN 1 G N ------- f B --- V N_ADC_Input_Referred_Noise 5 2 (a) eN for differential input ADC: 1 1 e N ----------- ------------V REF 10 5G N f B VREF SNR - ---------20 V --------- Hz NOISE VOLTAGE DENSITY (eN) OF INPUT DRIVER FOR MCP33141D-XX SNR - ---------20 1.8V B 3V 72 319.7 V Using Equation 5-8, the recommended maximum noise voltage density limit for unity gain input driver for differential input ADC can be estimated. Table 5-1 and Table 5-2 show a few example results with GN = 1. These tables may be used as a reference when selecting the ADC input driver amplifier. TABLE 5-1: NOISE VOLTAGE DENSITY (EN) OF INPUT DRIVER FOR MCP33151D-XX ADC (Note 1) VREF 1.8V 3V 5V RC Filter 73.6 443.2 V V --------- Hz- 5V ADC Input Driver Amplifier (GN = 1) ADC Noise SNR fB Input-Referred Voltage (dBFS) (Note 2) Noise Density (eN) (a) eN for single-ended input ADC: 1 1 e N -------------- ------------VREF 10 10G N f RC Filter 73.8 Note 1: 2: 721.9 V 3 MHz 29.5 nV/Hz 4 MHz 25.5 nV/Hz 5 MHz 22.8 nV/Hz 3 MHz 40.8 nV/Hz 4 MHz 35.4 nV/Hz 5 MHz 31.6 nV/Hz 3 MHz 66.5 nV/Hz 4 MHz 57.6 nV/Hz 5 MHz 51.5 nV/Hz See Equation 5-5 for the ADC input-referred noise calculation for differential input. fB is -3dB bandwidth of the RC anti-aliasing filter. ADC Input Driver Amplifier (GN = 1) ADC Noise SNR fB Input-Referred Voltage (dBFS) (Note 2) Noise Density (eN) 78.8 81.8 83.7 Note 1: 2: 146 V 172 V 231 V 3 MHz 13.5 nV/Hz 4 MHz 11.7 nV/Hz 5 MHz 10.4 nV/Hz 3 MHz 15.9 nV/Hz 4 MHz 13.8 nV/Hz 5 MHz 12.3 nV/Hz 3 MHz 21.3 nV/Hz 4 MHz 18.4 nV/Hz 5 MHz 16.5 nV/Hz See Equation 5-5 for the ADC input-referred noise calculation for differential input. fB is -3dB bandwidth of the RC anti-aliasing filter. 2019 Microchip Technology Inc. DS20006219A-page 35 MCP33151D/41D-XX 5.4 Device Operation 5.4.2 The start of the conversion is controlled by CNVST. On the rising edge of CNVST, the sampled charge is locked (sample switches are opened) and the ADC performs the conversion. Once a conversion is started, it will not stop until the current conversion is complete. The data conversion time (tCNV) is not user controllable. After the conversion is complete and the host lowers CNVST, the output data is presented on SDO. When the MCP33151D/41D-XX is first powered-up, it self-calibrates internal systems and automatically enters Input Acquisition mode. The device operates in two phases: (a) Input Acquisition (Standby) and (b) Data Conversion. Figure 5-10 shows the ADC's operating sequence. 5.4.1 DATA CONVERSION PHASE INPUT ACQUISITION PHASE (STANDBY) Any noise injection during the conversion phase may affect the accuracy of the conversion. To reduce external environment noise, minimize I/O events and running clocks during the conversion time. During the input acquisition phase (tACQ), also called Standby, the two input sampling capacitors, CS+ and CS-, are connected to the AIN+ and AIN- pins, respectively. The input voltage is sampled until a rising edge on CNVST is detected. The input voltage should be fully settled within 1/2 LSB during tACQ. The output data is clocked out MSB first. While the output data is being transferred, the device enters the next input acquisition phase. The acquisition time (tACQ) is user-controllable. The system designer can increase the acquisition time (tACQ) as much as needed to reduce sampling rate for additional power savings. Note: Transferring output data during the acquisition phase can disturb the next input sample. It is highly recommended to allow at least tQUIET (10 ns, typical) between the last edge on the SPI interface and the rising edge on CNVST. See Figure 1-1 for tQUIET. tCYC = 1/fS Input Acquisition (Standby) Operating Condition IDDAN Data Conversion tACQ MCP331x1D-10: 490 ns (typical) MCP331x1D-05: 800 ns (typical) tCNV MCP331x1D-10: 510 ns (typical) MCP331x1D-05: 1200 ns (typical) Input Acquisition (Standby) tACQ MCP331x1D-10: 490 ns (typical) MCP331x1D-05: 800 ns (typical) (a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST. (a) At the falling edge of CNVST, ADC output is available at SDO. (b) No ADC output is available yet. (b) All circuits are turned-on. (b) ADC output can be clocked out (c) Most analog circuits are (c) ADC output is not available yet. by providing clocks. turned off. (c) ADC acquires input sample #2. MCP331x1D-10: ~0.66 mA (d) Most analog circuits are turned off. MCP331x1D-05: ~0.33 mA I ~ 1.5 A Off (a) Device is first powered-up and (b) Performs a power-up self-calibration. Output Data SDO FIGURE 5-10: DS20006219A-page 36 Device Operating Sequence. 2019 Microchip Technology Inc. MCP33151D/41D-XX 5.4.3 SAMPLE THROUGHPUT RATE The device completes data conversion within the maximum specification of the data conversion time (tCNV). The continuous input sample rate is the inverse of the sum of input acquisition time (tACQ) and data conversion time (tCNV). Equation 5-9 shows the continuous sample rate calculation using the minimum and maximum specifications of the input acquisition time (tACQ) and data conversion time (tCNV). EQUATION 5-9: EQUATION 5-10: t ACQ = N T SCLK + t QUIET + t EN 1 N fSCLK = -------------- = ----------------------------------------------------T SCLK t ACQ - tQUIET + t EN Where: fSCLK = minimum SPI serial clock frequency required to transfer all N-bits of output data during tACQ SAMPLE RATE 1 Sample Rate = ---------------------------------- t ACQ + t CNV N = number of output data bits TSCLK = Period of SPI clock N x TSCLK = Output data window tQUIET = Quiet time between the last output bit and beginning of the next conversion start = 10 ns (Min.) = Output enable time = 10 ns (Max.) with DVIO 2.3V (a) MCP331X1D-10: 1 Sample Rate = -------------------------------------------- = 1 Msps 250 ns + 750 ns (b) MCP331X1D-05: 1 Sample Rate = ----------------------------------------------- = 500 kSPS 600 ns + 1400 ns 5.4.4 tEN Note: SERIAL SPI CLOCK FREQUENCY REQUIREMENT The ADC output is collected during the input acquisition time (tACQ). For continuous input sampling and data conversion sequence, the SPI clock frequency should be fast enough to clock out all output data bits during the input acquisition time (tACQ). For the continuous sampling rate (fS), the minimum SPI clock frequency requirement is determined by Equation 5-10: 2019 Microchip Technology Inc. SPI CLOCK FREQUENCY REQUIREMENT 5.4.5 Refer to Serial Interface Timing Specifications for relevant timing information and see Figure 1-1 for interface timing diagram. SERIAL SPI CLOCK FREQUENCY REQUIREMENT The ADC output is collected during the input acquisition time (tACQ). For continuous input sampling and data conversion sequence, the SPI clock frequency should be fast enough to clock out all output data bits during the input acquisition time (tACQ). For the continuous sampling rate (fS), the minimum SPI clock frequency requirement is determined by Equation 5-10: DS20006219A-page 37 MCP33151D/41D-XX 5.5 Transfer Function 5.6 The differential analog input is VIN = (VIN+) - (VIN-). The LSB size is given by Equation 5-11. and an example of LSB size vs. reference voltage is summarized in Table 5-3. EQUATION 5-11: LSB SIZE (EXAMPLE) 2VREF LSB = -------------N 2 Where N is the resolution of the ADC in bits. TABLE 5-3: LSB SIZE VS. REFERENCE LSB Size Reference Voltage (VREF) MCP33151D-XX MCP33141D-XX (14-bit) (12-bit) 1.8V 219.7 V 879.8 V 2V 244 V 976.6 V 2.5V 305.2 V 1.2207 mV 3V 366.2 V 1.4648 mV 3.3V 402.8 V 1.6113 mV 3.5V 427.3 V 1.7090 mV 4V 488.3 V 1.9531 mV 4.5V 549.3 V 2.1973 mV 5V 610.4 V 2.4414 mV 5.1V 622.6 V 2.4902 mV Digital Output Code The digital output code is proportional to the input voltage. The output data is in binary two's complement format. With this coding scheme the MSB can be considered a sign indicator. When the MSB is a logic `0', the input is positive. When the MSB is a logic `1', the input is negative. The following is an example of the output code: (a) for a negative full-scale input: Analog Input: (VIN+) - (VIN-) = -VREF Output Code: 1000...0000 (b) for a zero differential input: Analog Input: (VIN+) - (VIN-) = 0V Output Code: 0000...0000 (c) for a positive full-scale input: Analog Input: (VIN+) - (VIN-) = +VREF Output Code: 0111...1111 The MSB (sign bit) is always transmitted first through the SDO pin. The code will be locked at 0111...11 for all voltages greater than (VREF - 1 LSB) and 1000...00 for voltages less than -VREF. Table 5-4 shows an example of output codes of various input levels. Figure 5-11 shows the ideal transfer function and Table 5-4 shows the digital output codes for the MCP33151D/41D-XX. 011 ... 111 Digital Output Code (Two's Complement) 011 ... 110 000 ... 000 100 ... 001 100 ... 000 0V -VREF + 1 LSB -VREF + 0.5 LSB -VREF +VREF - 2 LSB +VREF - 1.5 LSB +VREF - 1 LSB Differential Analog Input Voltage FIGURE 5-11: Ideal Transfer Function for Fully-Differential Input Signal. DS20006219A-page 38 2019 Microchip Technology Inc. MCP33151D/41D-XX TABLE 5-4: DIGITAL OUTPUT CODE Digital Output Codes Input Voltage (V) MCP33151D-XX (14-bit) MCP33141D-XX (12-bit) VREF 01-1111-1111-1111 0111-1111-1111 VREF - 1 LSB 01-1111-1111-1111 0111-1111-1111 . . . . . . 2 LSB 00-0000-0000-0010 0000-0000-0010 1 LSB 00-0000-0000-0001 0000-0000-0001 00-0000-0000-0000 0000-0000-0000 11-1111-1111-1111 1111-1111-1111 -2 LSB 11-1111-1111-1110 1111-1111-1110 . . . . . . -VREF 10-0000-0000-0000 1000-0000-0000 < -VREF 10-0000-0000-0000 1000-0000-0000 The MCP33151D/41D-XX devices feature an internal integrator capable of accumulating consecutive sample data and transmitting the accumulated data directly from the ADC, without requiring any special SPI settings to operate. This enables the user to achieve a higher ENOB through consecutive sample integration utilizing the ADC hardware, without requiring any external computational resources and reducing the amount of data transmitted on the serial bus. See Figure 5-12 for an example FFT performance plot after 1024 integrated samples while sampling a 75Hz input signal with a 5V reference voltage. Refer to Figure 5-13 for an example of FFT performance across possible integration lengths. 0 Amplitude (dBFS) -20 VREF = 5V -40 -60 -80 -80 110 -85 105 -90 100 -95 SNR (dB) SINAD(dB) SFDR(dBc) THD (dB) 95 90 -100 -105 85 -110 80 -115 75 1 4 16 64 256 -120 1024 Integration Length FIGURE 5-13: FFT with 1024 integrated samples: Input Freq = 75Hz. 5.7.1 Data accumulation is performed automatically within the device between each sequential Conversion/Acquisition cycle (TCYC) whenever the current conversion results are not read out, up to a total of 1024 consecutive conversions for an ENOB increase of up to 5 bits above typical. To begin data accumulation, the user simply avoids transmitting any SCLK pulses during each sequential conversion cycle. -140 0.1 115 SNR = 116.7 dBFS SINAD = 111.5 dBFS SFDR = 117.2 dBc THD = -113.5 dBc ENOB = 18-bit Resolution = 24-bit -120 0 -75 fs = 1/1024 Msps -100 -160 120 THD (dB) Data Accumulator SNR/SINAD (dB), SFDR (dBc) 5.7 0V -1 LSB 0.2 0.3 0.4 0.5 Frequency (kHz) FIGURE 5-12: FFT with 1024 integrated samples: Input Freq = 75Hz. 2019 Microchip Technology Inc. Note: DATA ACCUMULATOR USAGE If a sample has been converted but not read out, the sample can be discarded by providing at least 1 SCLK pulse before initiating the next conversion. Providing at least 1 SCLK will reset the system for single acquisition. Otherwise all consecutive conversions without an SCLK pulse will automatically be integrated with the previous conversion results. DS20006219A-page 39 MCP33151D/41D-XX Consecutive sample integration increases the bit size of the output data, up to the maximum output size of the ADC (24-bits / 18.5 ENOB at 1024 samples for a 14-bit ADC). Because the addition of two binary values can produce a sum with an increased bit size, the ADC will need to output data proportional to the amount of samples being integrated. See Table 5-5 for an estimate of the data size and ENOB capability depending on the number of conversions the user chooses to integrate. When using the accumulator, it is important to consider the frequency content of the input signal being sampled. Because the accumulator is averaging all consecutive conversions over the accumulated time period, the input frequency must be low enough to ensure that no signal information is being filtered out. This means that there is a performance trade-off between sample integration length (and resulting ENOB improvement) and the maximum input frequency that can be sampled. Refer to Table 5-6 to understand the roll-off frequencies for various integration lengths, and refer to Figure 5-14 for an example of the dB attenuation across integration lengths. TABLE 5-5: ACCUMULATED DATA SIZE AND ENOB FOR 14-BIT ADC Number of Conversions ADC transmission size (bits) Effective Number of bits (ENOB) (1) 1 14 13.5 2 15 14 3-4 16 14 - 14.5 5-8 17 14.5 - 15 9 - 16 18 15 - 15.5 17 - 32 19 15.5 - 16 33 - 64 20 16 - 16.5 65 - 128 21 16.5 - 17 129 - 256 22 17 - 17.5 257 - 512 23 17.5 - 18 513 - 1024 24 18 - 18.5 Note: The discrepancy between the output data size and the actual ENOB is a result of sample integration doubling both the signal amplitude and the noise power for each factor of two that the samples are integrated. By integrating 2 samples, the signal amplitude increases SNR by 6 dB, and the noise power decreases SNR by 3 dB, resulting in an overall SNR increase of 3 dB (+0.5 ENOB). TABLE 5-6: INPUT SIGNAL ROLL-OFF FREQUENCY VS INTEGRATION LENGTH Integration Length Roll-Off (Hz @ 1MSPS) 0.1 dB 0.01 dB 0.001 dB 2 41781.9 13226.3 4183.0 4 20890.9 6613.2 2091.5 8 10445.5 3306.6 1045.7 16 5222.7 1653.3 522.9 32 2611.4 826.6 261.4 64 1305.7 413.3 130.7 128 652.8 206.7 65.4 256 326.4 103.3 32.7 512 163.2 51.7 16.3 1024 81.6 25.8 8.2 0.02 0 Attenuation (dB) After completing the desired number of conversions to achieve the target ENOB, the user can begin transferring the total accumulated data by transmitting the necessary number of SCLK pulses to transfer all stored bits. Refer to Table 5-5 for number of conversions, bit size and ENOB relationship. See Figure 6-5 and Figure 6-8 for example Conversion/Acquisition control and SPI timing operation. -0.02 -0.04 -0.06 -0.08 1 4 16 64 256 1024 Integration Length FIGURE 5-14: Measured Attenuation of Fundamental Frequency (dB) vs Integration Length: Input Freq = 75 Hz. Note 1: ENOB values based on typical 14b device characteristics under nominal conditions and setting N to the maximum value in the corresponding row. DS20006219A-page 40 2019 Microchip Technology Inc. MCP33151D/41D-XX 6.0 DIGITAL SERIAL INTERFACE The device has an SPI compatible serial digital interface using four digital interface pins: CNV, SDI, SDO and SCLK. The following sections describe the operation of the MCP33151D/41D-XX using the digital serial interface. Table 6-1 summarizes the descriptions of both digital interface pins and interface options, respectively. The communication is always started by the host device (Master). Note: This device supports a standard SPI Mode 0,0 only. SPI MODE 0,0: In this mode, the SCLK Idle state is "Low". Data is clocked out on the SDO pin on the falling edge of the SCLK pin. For the MCP33151D/41D-XX, this means that there will be a rising edge before there is a falling edge. TABLE 6-1: 6.1 Serial Interface Options and Serial Communications The device offers a CS mode with 3-wire interface, and can operate either with or without a BUSY indicator status output. This BUSY status output bit is followed by the conversion output bits, and can be used as an interrupt request (IRQ) input for the digital host device. The 3-Wire CS mode (using CNV, SCLK, SDO) interface is simple and useful when the host device handles a single MCP33151D/41D-XX device. The following sections detail the serial communication of the 3-Wire CS modes with or without a BUSY output. INTERFACE MODE SELECTION SUMMARY SDI Pin Interface Mode At CNV Rising Edge After CNV Rising Edge CNV Pin at tCNV (recommended) SCLK at CNV Rising Edge BUSY bit at SDO 3-Wire CS Mode without BUSY output bit "High" Transition from "High" to "Low" after tCNV (Max) -- No 3-Wire CS Mode with BUSY output bit "Low" Transition from "High" to "Low" before tCNV (Max) -- Yes 6.1.1 Note: 6.1.1.1 CS MODES The timing diagram examples in the following subsections are shown for 14-bit mode only. The examples are applicable for 12-bit mode in the same way with reduced bits. 3-Wire CS MODE WITHOUT BUSY OUTPUT BIT This interface option is most useful when a single MCP33151D/41D-XX is connected to an SPI-compatible digital host. Figure 6-1 shows the connection diagram with the host device. In this mode, CNV functions as both conversion control and chip select (CS). To enable this interface option, SDI can either be tied to VIO, or otherwise permanently held in a Logic = 1 state. By doing so, the device will never output a BUSY status bit. As shown in Figure 6-2, at the rising edge of CNV, the conversion is initiated. The SDO pin becomes high-Z state (if no external pull-up is used). Once the conversion is initiated, it continues and the ADC 2019 Microchip Technology Inc. completes the conversion regardless of the state of the CNV pin. This means the CNV pin can be used for other SPI devices after the conversion is initiated. When conversion is complete, the device enters the acquisition phase (Power-Down state), and SDO comes out of the high-Z state when CNV is lowered. The device exits the acquisition phase when CNV goes "High". SDO returns to a high-Z state after the 14th SCLK falling edge or when CNV goes high, whichever occurs first. The device will output the MSB on the SDO pin following the falling edge of CNV, or once the Converting Phase (tCNV) completes, whichever happens later. The remaining data bits are then clocked out on the subsequent SCLK falling edges. Data is valid on both edges of SCLK and can be captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster read out rate. It is recommended to use this mode only when the ADC Converting Phase (tCNV) will complete before the falling edge of CNV. Figure 6-2 and Figure 6-3 show the timing diagrams for both early and late CNV lowering scenarios. DS20006219A-page 41 MCP33151D/41D-XX VIO CNVST VIO CNV 47 k SDI SDO SC>K SDI (Data In) SC>K (a) MCP331xx (b) Digital Host (Master) FIGURE 6-1: Connection Diagram for 3-Wire CS Mode without BUSY Status Indicator Output Bit. TCYC = 1/fs SDI = 1 tCNVH tSU_SDIH_CNV CNV (CS) tSCLK tEN SC>K SDO 1 tDO "High" (with pull-up) ,-Z (with no pull-up) D13 2 3 tQUIET 4 tSCLK_L D12 D11 5 12 13 tSCLK_H D10 D9 14 tDIS D2 D1 D0 ADC State Converting Phase (tCNV ) Input Acquisition (tACQ) FIGURE 6-2: Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output Bit, Late CNV (Recommended). DS20006219A-page 42 2019 Microchip Technology Inc. MCP33151D/41D-XX TCYC = 1/fs SDI = 1 tCNVH tSU_SDIH_CNV CNV (CS) tSCLK SC>K 1 tDO "High" (with pull-up) SDO H-Z (with no pull-up) D13 2 3 tQUIET 4 tSCLK_L D12 D11 5 12 13 14 tSCLK_H D10 tDIS D2 D9 D1 D0 tEN ADC State Converting Phase (tCNV ) FIGURE 6-3: Bit, Early CNV. Input Acquisition (tACQ) Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output TCYC(1) = 1/fs TCYC(2) = 1/fs TCYC(3) ... TCYC(N-1) TCYC(N) = 1/fs SDI = 1 tSU_SDIH_CNV tCNVH tCNVH tCNVH CNV (CS) tSCLK tEN 1 tDO SCLK D14 SDO D15 DM-1 2 tQUIET 3 4 M-1 tSCLK_L tSCLK_H DM-2 M-2 DM-3 DM-4 M tDIS D2 D1 D0 ADC State tCNV tACQ tCNV tACQ tACQ tCNV tACQ Legend No signal transitions during compressed time Signal transitions during compressed time FIGURE 6-4: Interface Timing Diagram for Accumulator Operation in 3-Wire CS Mode without BUSY Status Indicator Output Bit. Note: Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature. 2019 Microchip Technology Inc. DS20006219A-page 43 MCP33151D/41D-XX 6.1.1.2 3-Wire CS Mode with BUSY Output Bit CNVST This interface option is typically used when a single MCP33151D/41D-XX is connected to an SPI-compatible digital host that has an interrupt (IRQ) input. VIO CNV Figure 6-5 shows the connection diagram with the host device. In this mode, CNV functions as both conversion control and chip select (CS). To enable this interface option, SDI can either be tied to GND, or otherwise permanently held in a Logic = 0 state. By doing so, the device will output a BUSY bit before each conversion data sample. As shown in Figure 6-6, at the rising edge of CNV, conversion is initiated. The SDO pin becomes high-Z state (if no external pull-up is used). Once the conversion is initiated, it continues and the ADC completes the conversion regardless of the state of the CNV pin. This means the CNV pin can be used for other SPI devices after the conversion is initiated. When conversion is complete, the device enters an acquisition phase and Power-Down state, SDO comes out of the high-Z state, and outputs a BUSY status indicator bit ("Low" level). The device exits the acquisition phase when CNV once again returns to a "High" state. SDO then returns to a high-Z state after the 15th SCLK falling edge or when CNV goes high, whichever occurs first. Note: 47 k SDI SDO SC>K (a) MCP331xx SDI (Data In) IRQ SC>K (b) Digital Host (Master) FIGURE 6-5: Connection Diagram for 3-Wire CS Mode with BUSY Status Indicator Output Bit. IRQ Pin in the Host Device Is Used for Interrupt Event. Note: The pull-up resistor on the SDO pin is required in this mode as it ensures that the IRQ pin of the digital host is held high when SDO goes to high-Z state. It is recommended that CNV be driven low before the minimum conversion time (tCNV) expires, and remain "Low" until the maximum possible conversion time (tCONV) expires. A "Low" level on the CNV input at the end of a conversion ensures the device generates a BUSY status indicator bit when the ADC has finished converting. This configuration provides a high-to-low transition on the IRQ pin of the digital host caused by the BUSY bit. The data bits are clocked out, MSB first, on the subsequent SCLK falling edges. Data are valid on both edges of SCLK and can be captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster reading rate. Figure 6-6 and Figure 6-7 show the timing diagrams for both early and late CNV lowering scenarios. DS20006219A-page 44 2019 Microchip Technology Inc. MCP33151D/41D-XX TCYC = 1/fs SDI = 0 tSU_SDIL_CNV tCNVH CNV (CS) tSCLK SC>K SDO 1 tDO "High" (with pull-up) 2 4 tSCLK_L BUSY Hi-Z (with no pull-up) 3 tQUIET D13 5 13 14 tSCLK_H D12 D11 15 tDIS D10 D2 D1 D0 tEN ADC State Converting Phase (tCNV ) Input Acquisition (tACQ) FIGURE 6-6: Timing Diagram for 3-Wire CS Mode with BUSY Status indicator Output Bit, Early CNV (Recommended). TCYC = 1/fs SDI = 0 tSU_SDIL_CNV tCNVH CNV (CS) tSCLK tEN SC>K 1 2 tDO SDO "High" (with pull-up) Hi-Z (with no pull-up) BUSY 3 tQUIET 4 tSCLK_L D13 D12 5 13 14 tSCLK_H D11 D10 15 tDIS D2 D1 D0 ADC State Converting Phase (tCNV ) FIGURE 6-7: CNV. Input Acquisition (tACQ) Timing Diagram for 3-Wire CS Mode with BUSY Status Indicator Output Bit, Late 2019 Microchip Technology Inc. DS20006219A-page 45 MCP33151D/41D-XX TCYC(1) = 1/fs TCYC(2) = 1/fs TCYC(3) ... TCYC(N-1) TCYC(N) = 1/fs SDI = 1 tSU_SDIH_CNV tCNVH tCNVH tCNVH CNV (CS) tSCLK 1 tDO SCLK BUSY SDO BUSY BUSY BUSY 2 tQUI 3 tSCLK_L tSCLK_H DM-2 M-2 4 M-1 DM-3 DM-4 M tDIS D2 D1 D0 tEN ADC State tCNV tACQ tCNV tACQ tACQ tCNV tACQ Legend No signal transitions during compressed time Signal transitions during compressed time FIGURE 6-8: Timing Diagram for Accumulator Operation in 3-Wire CS Mode with BUSY Status Indicator Output Bit. Note: Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature. DS20006219A-page 46 2019 Microchip Technology Inc. MCP33151D/41D-XX 6.2 Recalibrate Command A self-calibration is initiated by sending the recalibrate command. The host device sends a recalibrate command by transmitting 1024 SCLK pulses (including the clocks for data bits) while the device is in the acquisition phase (Standby). The recalibrate command may be used in the following cases: * When the reference voltage was not fully settled during the initial power-on sequence. * During operation, to ensure optimum performance across varying environment conditions, such as reference voltage and temperature. The device drives SDO low during the recalibration procedure, and returns to high-Z once completed. The status of the recalibration procedure can be monitored by placing a pull-up on SDO, so that SDO goes high when the recalibration is complete. Figure 6-9 shows the recalibrate command timing diagram. The calibration takes approximately 500 ms (tCAL). (Note 1) SDI = 1 Start recalibration Finish recalibration Complete data reading Device Recalibration CNV (CS) 1024 clocks (SPITM Recalibrate command) 1 2 3 ... 13 14 ... 1023 1024 tCAL SC>K (Note 2) "High" (with pull-up) SDO Hi-Z (with no pull-up) ADC Output Data Stream "Low" (Note 3) ADC State tCNV Note 1: SDI must remain "High" during the entire recalibration cycle. 2: The 1024 clocks include the clocks for data bits. 3: SDO outputs "Low" during calibration, and high-Z when exiting the calibration. This SDO activity is only present during manual recalibration and is not present during initial power-on auto-calibration. (See Section 4.3 "Power-Up Sequence and Auto-Calibration" for more details) 4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately. FIGURE 6-9: Note: (Note 4) Recalibrate Command Timing Diagram. When the device performs a calibration, it is important to note that the analog supply voltage (AVDD), the reference voltage (VREF) and the digital I/O interface supply voltage (DVIO) must be stabilized for a correct calibration. This is particularly relevant during the initial power-on sequence. Refer to Section 4.3 "Power-Up Sequence and Auto-Calibration" for more details. 2019 Microchip Technology Inc. DS20006219A-page 47 MCP33151D/41D-XX NOTES: DS20006219A-page 48 2019 Microchip Technology Inc. MCP33151D/41D-XX 7.0 DEVELOPMENT SUPPORT 7.1 Device Evaluation Board Microchip Technology Inc. offers a high speed/high precision SAR ADC evaluation platform which can be used to evaluate Microchip's latest high speed/high resolution SAR ADC products. The platform consists of an MCP331x1D-XX evaluation board, a data capture board (PIC32 MZ EF Curiosity Board), and a PC-based Graphical User Interface (GUI) software. Figure 7-1 and Figure 7-2 show this evaluation tool. This evaluation platform allows users to quickly evaluate the ADC's performance for their specific application requirements. Note: Contact Microchip Technology Inc. for the PIC32 MCU firmware and the MCP331x1D-XX Evaluation Kit. (a) MCP331x1D-XX Evaluation Board (b) PIC32MZ EF Curiosity Board FIGURE 7-1: MCP331x1D-XX Evaluation Kit. FIGURE 7-2: PC-Based Graphical User Interface Software. 2019 Microchip Technology Inc. DS20006219A-page 49 MCP33151D/41D-XX 7.2 PCB Layout Guidelines The following four layers are recommended: (a) Top Layer: Most of the noise-sensitive analog components are populated on the top layer. Use all unused surface area as ground planes: analog ground plane in analog circuit section and digital ground in digital circuit section. These ground planes need to be tied to the corresponding ground planes in the second and bottom layers using multiple vias. Microchip provides the schematics and PCB layout of the MCP331x1D-XX Evaluation Board (P/N: ADM00873). It is strongly recommended that the user references the example circuits and PCB layouts. A good schematic with low noise PCB layout is critical for high performing ADC application system designs. A few guidelines are listed below: * Use low noise supplies (AVDD, DVIO, and VREF). * All supply voltage pins, including reference voltage, need decoupling capacitors. Decoupling capacitor requirements for each supply pin are shown in Figure 4-1. * Use NPO or COG type capacitor for the RC anti-aliasing filters in the analog input network. * Keep the analog circuit section (analog input driver amplifiers, filters, voltage reference, ADC, etc.) with an analog ground plane, and the digital circuit section (MCU, digital I/O interface) with a digital ground plane. Keep these sections as much apart as possible. This will minimize any digital switching noise coupling into the analog section. * Connect the analog and digital ground planes at a single point (away from the sensitive analog sections) with a 0resistor or with a ferrite bead. See Figure 7-3 as an example of separated ground planes. * Keep the clock and digital output data lines short and away from the sensitive analog sections as much as possible. * PCB Material and Layers: Low-loss FR-4 material is most commonly used. (b) 2nd Layer: Use this layer as the ground plane: Analog ground plane under the analog circuit section of the top layer and digital ground plane under the digital circuit section on the top layer. Each ground plane is tied to its corresponding ground plane of top and bottom layers using multiple vias. (c) 3rd Layer: This layer is used to distribute various power supplies of the circuits. Use separate trace paths for the power supplies of analog and digital sections. Do not use the same power supply source for both analog and digital circuits. (d) Bottom Layer: This layer is mostly used as a solid ground plane: Analog ground plane under the analog circuit section of the top layer and digital ground plane under the digital circuit section on the top layer. Each ground plane is tied to its corresponding ground plane of all layers using multiple vias. Figure 7-3 and Figure 7-4 show brief examples of the PCB layout. See more details of the schematics and PCB layout in the MCP331x1D-XX Evaluation Board User's Guide. Analog Ground Plane (GND) MCP331x1D-XX SCLK Analog Ground Plane (GND) SDO R56 Note: Analog and digital ground planes are connected via R56. Digital Interface Connectors for MCU Digital Ground Plane (DGND) FIGURE 7-3: DS20006219A-page 50 (DGND) Digital Ground Plane PCB Layout Example: Analog and Digital Ground Planes. 2019 Microchip Technology Inc. C7 C9 C59 C6 C10 MCP33151D/41D-XX AVDD VREF AIN+ AIN- VIO GND MCP331x1D-XX SDI SCLK SDO CNVST (a) PCB layout example (b) Schematic example from the MCP331x1D-XX Evaluation Board FIGURE 7-4: PCB Layout Example: See More Details in the MCP331x1D-XX EV Kit User's Guide. 2019 Microchip Technology Inc. DS20006219A-page 51 MCP33151D/41D-XX NOTES: DS20006219A-page 52 2019 Microchip Technology Inc. MCP33151D/41D-XX 8.0 TERMINOLOGY Analog Input Bandwidth (Full-Power Bandwidth) EQUATION 8-2: PS SINAD = 10 log ---------------------- PD + P N The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. Aperture Delay or Sampling Delay This is the time delay between the rising edge of the CNVST input and when the input signal is held for a conversion. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. No missing codes indicates that all 16384 codes for 14-bit (4096 codes for 12-bit) must be present over all the operating conditions. = - 10 log 10 SNR - ----------10 - 10 THD - -----------10 SINAD is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: EQUATION 8-3: SINAD - 1.76 ENOB = ---------------------------------6.02 Integral Nonlinearity (INL) INL is the maximum deviation of each individual code from an ideal straight line drawn from negative full scale through positive full scale. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), below the Nyquist frequency and excluding the power at DC and the first nine harmonics. EQUATION 8-1: PS SNR = 10 log ------- PN Gain Error Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error is usually expressed in LSB or as a percentage of full-scale range (%FSR). Offset Error The major carry transition should occur for an analog value of 1/2 LSB below AIN+ = AIN-. Offset error is defined as the deviation of the actual transition from that point. Temperature Drift SNR is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. The temperature drift for offset error and gain error specifies the maximum change from the initial (+25C) value to the value at across the TMIN to TMAX range. The value is normalized by the reference voltage and expressed in V/oC or ppm/oC. Signal-to-Noise and Distortion (SINAD) Maximum Conversion Rate SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD) below the Nyquist frequency, but excluding DC: The maximum clock rate at which parametric testing is performed. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier) or dBFS. 2019 Microchip Technology Inc. DS20006219A-page 53 MCP33151D/41D-XX Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the summed power of the first 13 harmonics (PD). EQUATION 8-4: PS THD = 10 log -------- PD THD is typically given in units of dBc (dB to carrier). THD is also shown by: EQUATION 8-5: 2 2 2 2 V2 + V 3 + V 4 + + V n THD = - 20 log -----------------------------------------------------------------2 V1 Where: V1 = RMS amplitude of the fundamental frequency V1 through Vn = Amplitudes of the second through nth harmonics Common-Mode Rejection Ratio (CMRR) Common-mode rejection is the ability of a device to reject a signal that is common to both sides of a differential input pair. The common-mode signal can be an AC or DC signal or a combination of the two. CMRR is measured using the ratio of the differential signal gain to the common-mode signal gain and expressed in dB with Equation 8-6: EQUATION 8-6: Where: A DIFF CMRR = 20 log ------------------ A CM ADIFF = Output Code/Differential Voltage ADIFF = Output Code/Common-Mode Voltage DS20006219A-page 54 2019 Microchip Technology Inc. MCP33151D/41D-XX 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 10-Lead MSOP (3 x 3 mm) Example Part Number Code MCP33151D-10-E/MS 51D-10 MCP33151D-05-E/MS 51D-05 MCP33141D-10-E/MS 41D-10 MCP33141D-05-E/MS 41D-05 Note: Applies to 10-Lead MSOP. 10-Lead TDFN (3 x 3 x 0.8 mm) XXXX YYWW NNN 51D-10 922256 Example Part Number Code MCP33151D-10-E/MN 51D1 MCP33151D-05-E/MN 51D0 MCP33141D-10-E/MN 41D1 MCP33141D-05-E/MN 41D0 Note: Applies to 10-Lead TDFN. XXXX YYWW NNN 51D1 1922 256 PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2019 Microchip Technology Inc. DS20006219A-page 55 MCP33151D/41D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 H D D 2 A N E 2 E1 2 E1 E 0.20 H 1 0.25 C 2 e B 8X b 0.13 C A B TOP VIEW H C SEATING PLANE A2 A 8X A1 0.10 C SEE DETAIL A SIDE VIEW END VIEW Microchip Technology Drawing C04-021D Sheet 1 of 2 DS20006219A-page 56 2019 Microchip Technology Inc. MCP33151D/41D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4X 1 c C SEATING PLANE L (L1) 4X 1 DETAIL A Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 Mold Draft Angle Foot Angle 1 c Lead Thickness b Lead Width MIN 0.75 0.00 0.40 0 5 0.08 0.15 MILLIMETERS NOM 10 0.50 BSC 0.85 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF - MAX 1.10 0.95 0.15 0.80 8 15 0.23 0.33 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-021D Sheet 2 of 2 2019 Microchip Technology Inc. DS20006219A-page 57 MCP33151D/41D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G SILK SCREEN Z C G1 Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Overall Width Z Contact Pad Width (X10) X1 Contact Pad Length (X10) Y1 Distance Between Pads (X5) G1 Distance Between Pads (X8) G MIN MILLIMETERS NOM 0.50 BSC 4.40 MAX 5.80 0.30 1.40 3.00 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2021B DS20006219A-page 58 2019 Microchip Technology Inc. MCP33151D/41D-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2019 Microchip Technology Inc. DS20006219A-page 59 MCP33151D/41D-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006219A-page 60 2019 Microchip Technology Inc. MCP33151D/41D-XX APPENDIX A: REVISION HISTORY Revision A (June 2019) * Initial release of this document 2019 Microchip Technology Inc. DS20006219A-page 59 MCP33151D/41D-XX NOTES: 2019 Microchip Technology Inc. DS20006219A-page 60 MCP33151D/41D-XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) XX X X /XX Input Type Sample Rate Tape and Reel Temperature Package Range Option Device: MCP33151D-10 MCP33141D-10 MCP33151D-05 MCP33141D-05 = = = = 1 Msps, 14-Bit Differential Input SAR ADC 1 Msps, 12-Bit Differential Input SAR ADC 500 kSPS, 14-Bit Differential Input SAR ADC 500 kSPS, 12-Bit Differential Input SAR ADC Input Type: D = Differential Input Sample Rate: 10 05 = 1 Msps = 500 kSPS Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel (Note 1) Temperature Range: E = -40C to +125C Package: MS = MN = Examples: a) MCP33151D-10-E/MS: 14-bit, 1 Msps, 10-LD MSOP package b) MCP33151D-10T-E/MS: 14-bit, 1 Msps, Tape and Reel, 10-LD MSOP package c) MCP33151D-10-E/MN: 14-bit, 1 Msps, 10-LD TDFN package d) MCP33151D-10T-E/MN: 14-bit, 1 Msps, Tape and Reel, 10-LD TDFN package e) MCP33141D-10-E/MS: 12-bit, 1 Msps, 10-LD MSOP package f) MCP33141D-10T-E/MS: 12-bit, 1 Msps, Tape and Reel, 10-LD MSOP package g) MCP33141D-10-E/MN: 12-bit, 1 Msps, 10-LD TDFN package h) MCP33141D-10T-E/MN: 12-bit, 1 Msps, Tape and Reel, 10-LD TDFN package i) MCP33151D-05-E/MS: 14-bit, 500 kSPS, 10-LD MSOP package j) MCP33151D-05T-E/MS: 14-bit, 500 kSPS, Tape and Reel, 10-LD MSOP package k) MCP33151D-05T-E/MN: 14-bit, 500 kSPS, Tape and Reel, 10-LD TDFN package l) MCP33141D-05-E/MS: 12-bit, 500 kSPS, 10-LD MSOP package m) MCP33141D-05T-E/MN: 12-bit, 500 kSPS, Tape and Reel, 10-LD TDFN package (Extended) Plastic Micro Small Outline Package (MSOP), 10-Lead Thin Plastic Dual Flat No Lead Package (TDFN), 10-Lead (Note 2) Note 1: 2: 2019 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Contact Microchip Technology Inc. for availability. DS20006219A-page 61 MCP33151D/41D-XX NOTES: DS20006219A-page 62 2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip's Quality Management Systems, please visit www.microchip.com/quality. 2019 Microchip Technology Inc. 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