2019 Microchip Technology Inc. DS20006219A-page 1
MCP33151D/41D-XX
Features
• Sample Rate (Throughput):
- MCP33151D/41D-10: 1 Msps
- MCP33151D/41D-05: 500 kSPS
• 14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Wide Operating Voltage Range:
- Analog supply voltage (AVDD): 1.8V
- Digital input/output interface voltage (DVIO):
1.7-5.5V
- External reference voltage (VREF): AVDD -5.1V
• Differential Input Operation
- Input full-scale range: -VREF to +VREF
• Ultra Low Current Consumption (typical):
- During input acquisition (standby): ~1.5 µA
- During conversion:
MCP33151D/41D-10: ~0.66 mA
MCP33151D/41D-05: ~0.33 mA
• SPI-Compatible Serial Communication:
- SCLK clock rate: up to 100 MHz
- 3-wire with optional BUSY indicator
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
- During power-up (automatic)
- On-Demand via user’s command during
normal operation
• Built In Data Accumulator
- Integrate up to 1024 consecutive converted
samples
- Increase ENOB up to 18.5 bits by
automatically averaging conversion results
• AEC-Q100 Qualified:
- Temperature grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
Typical Applications
• High-Precision Data Acquisition
• Medical Instruments
• Test Equipment
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
System Design Supports
The MCP331x1D-XX Evaluation Kit demonstrates the
performance of the MCP331x1D-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1D
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 firmware example codes.
Package Types
MCP331x1D-XX Device Offering (Note 1)
MSOP-10
TDFN-10 *
* Includes Exposed Thermal Pad (see Table 4-1).
Part Number Resolution Sample
Rate Input Type Input Range
(Differential)
Performance (Typical)
SNR
(dBFS)
SFDR
(dB)
THD
(dB)
INL
(LSB)
DNL
(LSB)
MCP33151D-10 14-bit 1 Msps Differential ±5.1V 83.8 107.3 -104.7 ±0.27 ±0.11
MCP33141D-10 12-bit 1 Msps Differential ±5.1V 73.8 100.0 -101.5 ±0.07 ±0.05
MCP33151D-05 14-bit 500 kSPS Differential ±5.1V 83.7 103.8 -100.9 ±0.27 ±0.11
MCP33141D-05 12-bit 500 kSPS Differential ±5.1V 73.8 99.8 -98.9 ±0.07 ±0.05
Note 1: SNR, SFDR, and THD are measured with fIN =10kHz, V
IN = -1 dBFS, VREF =5.1V.
1 Msps/500 kSPS, 14/12-Bit Differential Input SAR ADC
MCP33151D/41D-XX
DS20006219A-page 2 2019 Microchip Technology Inc.
Application Diagram
Description
The MCP33151D/41D-10 and MCP33151D/41D-05
are fully-differential, 14-bit and 12-bit, single-channel,
1 Msps and 500 kSPS ADC family devices,
respectively, featuring low power consumption and
high performance, using a successive approximation
register (SAR) architecture.
The device operates with an external voltage reference
(VREF) from AVDD to 5.1V, which supports a wide range
of input full-scale range from -VREF to +VREF
. The
reference voltage setting is independent of the analog
supply voltage (AVDD). The conversion output is
available through an easy-to-use simple SPI-
compatible 3-wire interface.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7-5.5V) allows the device to interface
with most host devices (Master) available in the current
industry such as the PIC32 microcontrollers, without
using external voltage level shifters.
Once all supply voltages are connected, the device will
power-up and perform an automatic calibration to
minimize offset, gain and linearity errors. The
automatic calibration takes place approximately 40 ms
following power-up, and it is necessary to ensure that
all power supplies are fully settled and stable after this
time. See Section 4.3 “Power-Up Sequence and
Auto-Calibration” for more details. The device
performance stays stable across the specified
temperature range. However, when extreme changes
in the operating environment, such as in the reference
voltage, are made with respect to the initial conditions
(e.g. the reference voltage did not fully settle during the
initial power-up sequence), the user may send a
recalibrate command anytime to initiate another
self-calibration and restore optimum performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode
(also referred to as ‘Standby mode’), where sampling
capacitors are connected to the input pins.
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes approximately 1.5 µA
during Standby. A new conversion is started on the
rising edge of CNVST. When the conversion is
complete and the host lowers CNVST, the output data
is presented on SDO, and the device enters Standby to
begin acquiring the next input sample. The user can
clock out the ADC output data using the
SPI-compatible serial clock during Standby.
The ADC system clock is generated by the internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device is AEC-Q100 qualified for automotive
applications and operates over the extended
temperature range of -40°C to +125°C. The available
package options are Pb-free small 3 mm × 3 mm
TDFN-10 and MSOP-10.
MCP331x1D-XX
A
IN
+
A
IN
-
GND
SDO
SCLK
CNVST
SDI
V
REF
AV
DD
DV
IO
Host Device
(PIC32MZ)
AV
DD
to 5.1V 1.8V 1.8V to 5.5V
0V to V
REF
0V to VREF
15Ω
15Ω
2.2nF
2.2nF
2019 Microchip Technology Inc. DS20006219A-page 3
MCP33151D/41D-XX
1.0 KEY ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
External Analog Supply Voltage (AVDD) ...................................................................................................... -0.3V to 2.0V
External Digital Supply Voltage (DVIO)......................................................................................................... -0.3V to 5.8V
External Reference Voltage (VREF).............................................................................................................. -0.3V to 5.8V
Analog Inputs w.r.t GND ................................................................................................................. -0.3V to VREF +0.3V
Current at Input Pins ..............................................................................................................................................±2 mA
Current at Output and Supply Pins ....................................................................................................................±250 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Maximum Junction Temperature (TJ) ................................................................................................................... +150°C
ESD Protection on All Pins ......................................................................................................≤ 4kV HBM, ≤ 2kV CDM
1.2 Electrical Specifications
†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF, +25°C is applied
for typical values.
MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V Note 3
Digital Input/Output Interface
Voltage Range
DVIO 1.7 — 5.5 Note 3
Analog Supply Current at AVDD
Pin:
During Conversion
During Standby
IDDAN
IDDAN_STBY
—
—
—
660
330
1.5
900
600
—
µA
µA
µA
fS= 1 Msps (MCP331x1D-10)
fS= 500 kSPS (MCP331x1D-05)
During Input Acquisition (tACQ)
Average Digital Supply Current
at DVIO Pin:
During Data Transfer
During Standby
IIO_DATA
IIO_STBY
—
—
—
—
—
400
343
200
171
120
—
—
—
—
—
µA
µA
µA
µA
nA
fS= 1 Msps (MCP33151D-10)
fS= 1 Msps (MCP33141D-10)
fS= 500 kSPS (MCP33151D-05)
fS= 500 kSPS (MCP33141D-05)
During Input Acquisition (tACQ)
External Reference Voltage Input
Reference Voltage (Note 2,
Note 3)
VREF AVDD —5.1V
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
MCP33151D/41D-XX
DS20006219A-page 4 2019 Microchip Technology Inc.
Reference Load Current at
VREF Pin:
During Conversion
During Standby
IREF
IREF_STBY
—
—
—
220
110
40
290
180
—
µA
µA
nA
fS= 1 Msps (MCP331x1D-10)
fS= 500 kSPS (MCP331x1D-05)
During Input Acquisition (tACQ)
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1D-10
at 1 Msps
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
—
3.6
1.8
0.4
3.3
—
—
—
—
mW
mW
mW
µW
Averaged power for tACQ +t
CNV
Input acquisition (tACQ)
MCP331x1D-05
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
1.8
0.4
3.3
—
—
—
mW
mW
µW
Averaged power for tACQ +t
CNV
Input acquisition (tACQ)
Analog Inputs
Input Voltage Range
(Note 2)
VIN+ -0.1 — VREF + 0.1 V Differential Input:
VIN =V
IN+ –V
IN-
VIN- -0.1 — VREF +0.1
Input Full-Scale Voltage Range FSR -VREF —+V
REF VPP Differential Input (Note 2, Note 4)
Input Common-mode Voltage
Range
VCM 0V
REF/2 VREF Note 2
Input Sampling Capacitance CS—10 — pFNote 1
-3dB Input Bandwidth BW-3dB —45 — MHzNote 1
Aperture Delay
(Note 1)
— 2.5 — ns Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog
Input Pin
ILEAK_AN_INPUT — ±2.2 ±200 nA During Standby
System Performance
Sample Rate
(Throughput Rate)
fS— — 1 Msps MCP331x1D-10
— — 500 kSPS MCP331x1D-05
Resolution
(No Missing Codes)
14 — — bits MCP33151D-XX
12 — — bits MCP33141D-XX
Integral Nonlinearity INL -1.5 ±0.27 +1.5 LSB MCP33151D-XX
— ±0.07 — LSB MCP33141D-XX
Differential Nonlinearity DNL -0.8 ±0.11 +0.8 LSB MCP33151D-XX
-0.3 ±0.05 +0.3 LSB MCP33141D-XX
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF, +25°C is applied
for typical values.
MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
2019 Microchip Technology Inc. DS20006219A-page 5
MCP33151D/41D-XX
Offset Error -1.62 ±0.4 1.62 mV MCP33151D-XX
-1.33 ±0.4 1.33 mV MCP33141D-XX
Offset Error Drift with Temperature —±0.1 — µV/°C
Gain Error GER —±1 —LSB MCP33151D-XX
— ±0.2 — LSB MCP33141D-XX
Gain Error Drift with
Temperature
—±8 —µV/°C
Input Common-mode Rejection
Ratio
CMRR — 84 — dB
Power Supply Rejection Ratio PSRR — 75 — dB Note 5
Dynamic Performance
Signal-to-Noise Ratio SNR MCP33151D-10 and MCP33151D-05: 14-bit ADC
— 83.9 — dBFS VREF =5V, f
IN =1kHz
—79.2 — V
REF =1.8V, f
IN =1kHz
82.6 83.7 — VREF =5V, f
IN =10kHz
—78.8 — V
REF =1.8V, f
IN =10kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
— 73.8 — dBFS VREF =5V, f
IN =1kHz
—73.1 — V
REF =1.8V, f
IN =1kHz
73.4 73.8 — VREF =5V, f
IN =10kHz
—73.0 — V
REF =1.8V, f
IN =10kHz
Signal-to-Noise Distortion Ratio
(Note 6)
SINAD MCP33151D-10 and MCP33151D-05: 14-bit ADC
— 83.9 — dBFS VREF =5V, f
IN =1kHz
—79.2 — V
REF =1.8V, f
IN =1kHz
—83.6 — V
REF =5V, f
IN =10kHz
—77.8 — V
REF =1.8V, f
IN =10kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
— 73.8 — dBFS VREF =5V, f
IN =1kHz
—73.1 — V
REF =1.8V, f
IN =1kHz
—73.8 — V
REF =5V, f
IN =10kHz
—73.0 — V
REF =1.8V, f
IN =10kHz
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF, +25°C is applied
for typical values.
MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
MCP33151D/41D-XX
DS20006219A-page 6 2019 Microchip Technology Inc.
Spurious Free Dynamic Range SFDR MCP33151D-10 and MCP33151D-05: 14-bit ADC
— 110.5 — dBc VREF =5V, f
IN =1kHz
— 107.2 — VREF =1.8V, f
IN =1kHz
— 105.9 — VREF =5V, f
IN =10kHz
—96.3 — V
REF =1.8V, f
IN =10kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
— 99.8 — dBc VREF =5V, f
IN =1kHz
—99.4 — V
REF =1.8V, f
IN =1kHz
—99.9 — V
REF =5V, f
IN =10kHz
—95.2 — V
REF =1.8V, f
IN =10kHz
Total Harmonic Distortion
(first five harmonics)
THD MCP33151D-10 and MCP33151D-05: 14-bit ADC
— -105.0 — dBc VREF =5V, f
IN =1kHz
— -105.2 — VREF =1.8V, f
IN =1kHz
— 103.2 — VREF =5V, f
IN =10kHz
—95.2 — V
REF =1.8V, f
IN =10kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
— -100.7 — dBc VREF =5V, f
IN =1kHz
— -100.3 — VREF =1.8V, f
IN =1kHz
— -100.4 — VREF =5V, f
IN =10kHz
—-94.2 — V
REF =1.8V, f
IN =10kHz
System Self-Calibration
Self-Calibration Time tCAL —400 550 msNote 2
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK — 1024 — clocks Includes clocks for data bits
Serial Interface Timing Information: See Serial Interface Timing Specifications
Digital Inputs/Outputs
High-level Input Voltage VIH 0.7 × D
VIO
—DV
IO +0.3 V DV
IO ≥2.3V
0.9 × D
VIO
DVIO <2.3V
Low-level Input Voltage VIL -0.3 — 0.3 × DVIO VDV
IO ≥2.3V
-0.3 0.2 × DVIO DVIO <2.3V
Hysteresis of Schmitt Trigger
Inputs
VHYST —0.2×
DVIO
— V All digital inputs
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF, +25°C is applied
for typical values.
MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
2019 Microchip Technology Inc. DS20006219A-page 7
MCP33151D/41D-XX
Low-level Output Voltage VOL ——0.2×DV
IO VI
OL =500µA (source)
High-level Output Voltage VOH 0.8 × D
VIO
——VI
OH =-500µA (sink)
Input Leakage Current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO
Output Leakage Current ILO — — ±1 µA Output is high-Z, SDO = GND or
DVIO
Internal Capacitance
(all digital inputs and outputs)
CINT —7 — pFT
A=+25°C
TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V,
DVIO = 3.3V, GND = 0V,
Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1
Msps, +25°C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram.
Parameters Sym. Min. Typ. Max. Units Conditions
Serial Clock Frequency fSCLK — — 100 MHz See tSCLK specification
SCLK Period tSCLK 10 — — ns DVIO ≥3.3V, fSCLK = 100 MHz
(Max.)
12 — — DVIO ≥2.3V, fSCLK = 83.3 MHz
(Max.)
16 — — DVIO ≥1.7V, fSCLK = 62.5 MHz
(Max.)
SCLK Low Time tSCLK_L 3——nsD
VIO ≥2.3V
4.5 — — DVIO ≥1.7V
SCLK High Time tSCLK_H 3——nsD
VIO ≥2.3V
4.5 — — DVIO ≥1.7V
Output Valid from SCLK Low tDO — — 10 ns DVIO ≥3.3V
——12 D
VIO ≥2.3V
——16 D
VIO ≥1.7V
Quiet Time tQUIET 10 — — ns
3-wire Operation:
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF, +25°C is applied
for typical values.
MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
MCP33151D/41D-XX
DS20006219A-page 8 2019 Microchip Technology Inc.
FIGURE 1-1: Interface Timing Diagram (14-bit device). CNVST is Used as Chip Select. See
Section 6.0 “Digital Serial Interface” for More Details.
SDI Valid Setup Time tSU_SDIH_CNV 5 — — ns SDI High to CNVST Rising Edge
CNVST Pulse Width Time tCNVH 10 — —
Output Enable Time tEN ——10 D
VIO ≥2.3V
——15 D
VIO ≥1.7V
Output Disable Time tDIS ——15 Note 2
MCP331x1D-10
Sample Rate fS— — 1 Msps Throughput Rate
Input Acquisition Time tACQ 250 490 — ns
Data Conversion Time tCNV —510750ns
Time Between Conversions tCYC 1——µst
CYC =t
ACQ +t
CNV, fS=1Msps
MCP331x1D-05
Sample Rate fS— — 500 kSPS Throughput Rate
Input Acquisition Time tACQ 600 800 — ns
Data Conversion Time tCNV — 1200 1400 ns
Time Between Conversions tCYC 2——µst
CYC =t
ACQ +t
CNV, fS= 500 kSPS
TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V,
DVIO = 3.3V, GND = 0V,
Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1
Msps, +25°C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
SDI = 1
SC>K
SDO
CNV (CS)
TCYC = 1/fs
D13 D12 D11 D10 D9 D0D1D2
Hi-Z (with no pull-up)
tSCLK
tDO tSCLK_L tSCLK_H
12345121314
tCNVH
tQUIET
tDIS
“High” (with pull-up)
ADC
State
Converting Phase
(tCNV)
Input Acquisition
(tACQ)
tSU_SDIH_CNV
tEN (early CNV)
tEN (late CNV)
(Note 1)
(Note 2)
Note 1: tEN when CNVST is lowered after tCNV (MAX).
2: tEN when CNVST is lowered before tCNV (MAX).
2019 Microchip Technology Inc. DS20006219A-page 9
MCP33151D/41D-XX
TABLE 1-3: TEMPERATURE CHARACTERISTICS
Parameters Symbol Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature
Range
TA-40 — +125 °C Note 1
Storage Temperature
Range
TA-65 — +150 °C Note 1
Thermal Package Resistance
Thermal Resistance,
MSOP-10
JA — 202 — °C/W
Thermal Resistance,
TDFN-10
JA —68—°C/W
Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
MCP33151D/41D-XX
DS20006219A-page 10 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 11
MCP33151D/41D-XX
2.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33151D-XX)
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-1: INL vs. Output Code:
VREF =5V.
FIGURE 2-2: INL vs. Output Code:
VREF =1.8V.
FIGURE 2-3: INL vs. Reference Voltage.
FIGURE 2-4: DNL vs. Output Code:
VREF =5V.
FIGURE 2-5: DNL vs. Output Code:
VREF =1.8V.
FIGURE 2-6: DNL vs. Reference Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 4,096 8,192 12,288 16,384
Code
-0.5
-.25
0
0.25
0.5
INL (LSB)
V
REF
= 5V
0 4,096 8,192 12,288 16,384
Code
-0.5
-0.25
0
0.25
0.5
INL (LSB)
V
REF
= 1.8V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1.5
-1
-0.5
0
0.5
1
1.5
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 4,096 8,192 12,288 16,384
Code
-0.25
-0.1
0
0.1
0.25
DNL (LSB)
V
REF
= 5V
0 4,096 8,192 12,288 16,384
Code
-0.25
-0.10
0
0.10
0.25
DNL (LSB)
V
REF
= 1.8V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.5
-0.3
-0.1
0.1
0.3
0.5
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
MCP33151D/41D-XX
DS20006219A-page 12 2019 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-7: INL vs. Temperature.
FIGURE 2-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-10: DNL vs. Temperature.
FIGURE 2-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V.
FIGURE 2-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V.
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-1
-0.5
0
0.5
1
INL (LSB)
V
REF
= 5V
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 1 Msps
SNR = 83.8 dBFS
SINAD = 83.8 dBFS
SFDR = 109.2 dBc
THD = -104.9 dBc
Offset = -1 LSB
Resolution = 14-bit
MCP33151D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 0.5 Msps
SNR = 83.8 dBFS
SINAD = 83.7 dBFS
SFDR = 106.9 dBc
THD = -102.4 dBc
Offset = -1 LSB
Resolution = 14-bit
MCP33151D-05
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
DNL (LSB)
V
REF
= 5V
Max DNL (LSB)
Min DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 1.8V
f
s
= 1 Msps
SNR = 79.1 dBFS
SINAD = 79.0 dBFS
SFDR = 105.6 dBc
THD = -102.6 dBc
Offset = -2 LSB
Resolution = 14-bit
MCP33151D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 1.8V
f
s
= 0.5 Msps
SNR = 79.0 dBFS
SINAD = 78.9 dBFS
SFDR = 101.8 dBc
THD = -98.8 dBc
Offset = -2 LSB
Resolution = 14-bit
MCP33151D-05
2019 Microchip Technology Inc. DS20006219A-page 13
MCP33151D/41D-XX
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-13: SNR/SINAD/ENOB vs.
Reference Voltage.
FIGURE 2-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 2-15: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 2-16: THD/SFDR vs. Reference
Voltage.
FIGURE 2-17: SNR/SINAD vs.
Temperature: VREF = 1.8V.
FIGURE 2-18: THD/SFDR vs.
Temperature: VREF = 1.8V.
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
75
77.5
80
82.5
85
SNR/SINAD (dB)
12
12.5
13
13.5
14
ENOB
SNR (dB)
SINAD(dB)
ENOB
-50 0 50 100 150
Temperature (°C)
83.6
83.7
83.8
83.9
84
84.1
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-108
-107
-106
-105
THD(dB)
108
110
112
114
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 5V
2345
Reference Voltage (V)
-110
-105
-100
-95
THD(dB)
95
100
105
110
SFDR(dB)
THD (dB)
SFDR(dB)
-50 0 50 100 150
Temperature (°C)
78.4
78.6
78.8
79
79.2
79.4
79.6
79.8
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 1.8V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-100
-99
-98
-97
-96
-95
-94
-93
THD(dB)
96
97
98
99
100
101
102
103
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 1.8V
MCP33151D/41D-XX
DS20006219A-page 14 2019 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-19: SNR/SINAD vs.Input
Frequency: VREF = 5V.
FIGURE 2-20: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 2-21: SNR/SINAD vs. Input
Amplitude: VREF = 5V.
FIGURE 2-22: SNR/SINAD vs.Input
Frequency: VREF = 1.8V.
FIGURE 2-23: THD/SFDR vs. Input
Frequency: VREF = 1.8V.
FIGURE 2-24: SNR/SINAD vs. Input
Amplitude: VREF = 1.8V.
1 10 100 200
Input Frequency (kHz)
-115
-110
-105
-100
-95
-90
-85
-80
THD (dB)
80
85
90
95
100
105
110
115
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
83
83.5
84
84.5
85
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 5V
1 10 100 200
Input Frequency (kHz)
76
76.5
77
77.5
78
78.5
79
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
VREF = 1.8V
1 10 100 200
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
-70
THD (dB)
70
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 1.8V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
78
78.5
79
79.5
80
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 1.8V
2019 Microchip Technology Inc. DS20006219A-page 15
MCP33151D/41D-XX
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 2-26: SNR/SINAD/ENOB vs.
Sample Rate: VREF = 5V.
FIGURE 2-27: THD/SFDR vs Sample Rate:
VREF = 5V.
FIGURE 2-28: THD/SFDR vs. Input
Amplitude: VREF = 1.8V.
FIGURE 2-29: SNR/SINAD/ENOB vs.
Sample Rate: VREF = 1.8V.
FIGURE 2-30: THD/SFDR vs Sample Rate:
VREF = 1.8V.
-30 -25 -20 -15 -10 -5 0
Amplitude (dBFS)
-110
-105
-100
-95
THD(dB)
100
105
110
115
SFDR(dB)
THD (dB)
SFDR(dB)
V
REF
= 5V
25 50 100 250 500 1000
Sample Rate (kSPS)
81
81.8
82.6
83.4
84.2
85
SNR/SINAD (dB)
12
12.4
12.8
13.2
13.6
14
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
REF
= 5V
25 50 100 250 500 1000
Sample Rate (kSPS)
-110
-106
-102
-98
-94
-90
THD(dB)
92
96
100
104
108
112
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Amplitude (dBFS)
-103
-102
-101
-100
-99
THD(dB)
103
104
105
106
107
SFDR(dB)
THD (dB)
SFDR(dB)
V
REF
= 1.8V
25 50 100 250 500 1000
Sample Rate (kSPS)
76
76.8
77.6
78.4
79.2
80
SNR/SINAD (dB)
11
11.6
12.2
12.8
13.4
14
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
REF
= 1.8V
25 50 100 250 500 1000
Sample Rate (kSPS)
-110
-106
-102
-98
-94
-90
THD(dB)
94
98
102
106
110
114
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 1.8V
MCP33151D/41D-XX
DS20006219A-page 16 2019 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-31: Shorted Input Histogram:
VREF = 5V.
FIGURE 2-32: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 2-33: Power Consumption vs.
Sample Rate, MCP33151D-10:
CLOAD_SDO = 20 pF.
FIGURE 2-34: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 2-35: Offset and Gain Error vs.
Temperature: VREF = 1.8V.
FIGURE 2-36: Power Consumption vs.
Sample Rate, MCP33151D-05:
CLOAD_SDO = 20 pF.
-3-2-10123
Output Code
0
2
4
6
8
10
Occurrences
105
21725
841918
184932
1
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-1000
-750
-500
-250
0
250
500
750
1000
OFFSET/GAIN ERROR (uV)
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
OFFSET/GAIN ERROR (LSB)
OFFSET ERROR
GAIN ERROR
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Total Power (mW)
MCP33151D-10
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Frequency (kHz)
72
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-350
-150
50
250
450
650
850
OFFSET/GAIN ERROR (uV)
-1.6
-0.7
0.2
1.1
2.0
3.0
3.9
OFFSET/GAIN ERROR (LSB)
OFFSET ERROR
GAIN ERROR
V
REF
= 1.8V
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.1
0.2
0.3
0.4
0.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.6
1.2
1.8
2.4
3
Total Power (mW)
MCP33151D-05
2019 Microchip Technology Inc. DS20006219A-page 17
MCP33151D/41D-XX
Note: Unless otherwise specified, all parameters apply for TA=+25°C, AV
DD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN =10kHz, C
LOAD_SDO =20pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 2-37: Power Consumption vs.
Temperature, MCP33151D-10:
CLOAD_SDO = 20 pF.
FIGURE 2-38: Power Consumption vs.
Temperature during Shutdown (Standby).
FIGURE 2-39: Power Consumption vs.
Temperature, MCP33151D-05:
CLOAD_SDO = 20 pF.
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Total Power (mW)
MCP33151D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
1
2
3
4
5
6
7
8
Current ( A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
2
4
6
8
10
12
14
16
Total Power ( W)
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.1
0.2
0.3
0.4
0.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.6
1.2
1.8
2.4
3
Total Power (mW)
MCP33151D-05
MCP33151D/41D-XX
DS20006219A-page 18 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 19
MCP33151D/41D-XX
3.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33141D-XX)
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-1: INL vs. Output Code:
VREF = 5V.
FIGURE 3-2: INL vs. Output Code:
VREF = 1.8V.
FIGURE 3-3: INL vs. Reference Voltage.
FIGURE 3-4: DNL vs. Output Code:
VREF = 5V.
FIGURE 3-5: DNL vs. Output Code:
VREF = 1.8V.
FIGURE 3-6: DNL vs. Reference Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 1,024 2,048 3,072 4,096
Code
-0.2
-0.1
0
0.1
0.2
INL (LSB)
VREF = 5V
0 1,024 2,048 3,072 4,096
Code
-0.2
-0.1
0
0.1
0.2
INL (LSB)
V
REF
= 1.8V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.5
-0.25
0
0.25
0.5
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 1,024 2,048 3,072 4,096
Code
-0.2
-0.1
0
0.1
0.2
DNL (LSB)
V
REF
= 5V
0 1,024 2,048 3,072 4,096
Code
-0.2
-0.1
0
0.1
0.2
DNL (LSB)
V
REF
= 1.8V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.3
-0.15
0
0.15
0.3
DNL (LSB)
Min DNL (LSB)
Max DNL (LSB)
MCP33151D/41D-XX
DS20006219A-page 20 2019 Microchip Technology Inc.
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-7: INL vs. Temperature.
FIGURE 3-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-10: DNL vs. Temperature.
FIGURE 3-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V.
FIGURE 3-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V.
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-0.5
-0.25
0
0.25
0.5
INL (LSB)
Max INL (LSB)
Min INL (LSB)
V
REF
= 5V
0 100 200 300 400 500
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 1 Msps
SNR = 73.9 dBFS
SINAD = 73.9 dBFS
SFDR = 100.6 dBc
THD = -98.7 dBc
Offset = 0 LSB
Resolution = 12-bit
MCP33141D-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 0.5 Msps
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 99.6 dBc
THD = -99.9 dBc
Offset = -1 LSB
Resolution = 12-bit
MCP33141D-05
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-0.5
-0.25
0
0.25
0.5
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
V
REF
= 5V
0 100 200 300 400 500
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 1.8V
f
s
= 1 Msps
SNR = 73.0 dBFS
SINAD = 73.0 dBFS
SFDR = 101.0 dBc
THD = -100.0 dBc
Offset = -1 LSB
Resolution = 12-bit
MCP33141D-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 1.8V
f
s
= 0.5 Msps
SNR = 73.0 dBFS
SINAD = 73.0 dBFS
SFDR = 100.7 dBc
THD = -94.9 dBc
Offset = -1 LSB
Resolution = 12-bit
MCP33141D-05
2019 Microchip Technology Inc. DS20006219A-page 21
MCP33151D/41D-XX
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-13: SNR/SINAD/ENOB vs.
Reference Voltage.
FIGURE 3-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 3-15: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 3-16: THD/SFDR vs. Reference
Voltage.
FIGURE 3-17: SNR/SINAD vs.
Temperature: VREF = 1.8V.
FIGURE 3-18: THD/SFDR vs.
Temperature: VREF = 5V.
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
71
72
73
74
SNR/SINAD (dB)
11
11.5
12
12.5
ENOB
SNR (dB)
SINAD(dB)
ENOB
-50 0 50 100 150
Temperature (°C)
73.76
73.78
73.8
73.82
73.84
73.86
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-99
-98.8
-98.6
-98.4
-98.2
THD(dB)
97
97.5
98
98.5
99
SFDR(dB)
THD(dB)
SFDR(dB)
V
REF
= 5V
2345
Reference Voltage (V)
-103
-102
-101
-100
-99
-98
-97
-96
THD(dB)
97
97.5
98
98.5
99
99.5
100
100.5
SFDR(dB)
THD (dB)
SFDR(dB)
-50 0 50 100 150
Temperature (°C)
72.85
72.9
72.95
73
73.05
73.1
73.15
73.2
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 1.8V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-97
-96
-95
-94
-93
-92
THD(dB)
94
95
96
97
98
99
SFDR(dB)
THD(dB)
SFDR(dB)
V
REF
= 1.8V
MCP33151D/41D-XX
DS20006219A-page 22 2019 Microchip Technology Inc.
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-19: SNR/SINAD vs. Input
Frequency: VREF = 5V.
FIGURE 3-20: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 3-21: SNR/SINAD vs. Input
Amplitude: VREF = 5V.
FIGURE 3-22: SNR/SINAD vs. Input
Frequency: VREF = 1.8V.
FIGURE 3-23: THD/SFDR vs. Input
Frequency: VREF = 1.8V.
FIGURE 3-24: SNR/SINAD vs. Input
Amplitude: VREF = 1.8V.
1 10 100 200
Input Frequency (kHz)
72.5
72.6
72.7
72.8
72.9
73
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 5V
1 10 100 200
Input Frequency (kHz)
-105
-100
-95
-90
-85
-80
THD (dB)
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
73
73.5
74
74.5
75
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 5V
1 10 100 200
Input Frequency (kHz)
71
71.2
71.4
71.6
71.8
72
72.2
72.4
72.6
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
VREF = 1.8V
1 10 100 200
Input Frequency (kHz)
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 1.8V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
72
72.5
73
73.5
74
SNR/SINAD (dB)
SNR (dB)
SINAD(dB)
V
REF
= 1.8V
2019 Microchip Technology Inc. DS20006219A-page 23
MCP33151D/41D-XX
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 3-26: SNR/SINAD/ENOB vs.
Sample Rate: VREF = 5V.
FIGURE 3-27: THD/SFDR vs. Sample
Rate: VREF = 5V.
FIGURE 3-28: THD/SFDR vs. Input
Amplitude: VREF = 1.8V.
FIGURE 3-29: SNR/SINAD/ENOB vs.
Sample Rate: VREF = 1.8V.
FIGURE 3-30: THD/SFDR vs. Sample
Rate: VREF = 1.8V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
THD(dB)
90
95
100
105
SFDR(dB)
THD (dB)
SFDR(dB)
V
REF
= 5V
25 50 100 250 500 1000
Sample Rate (kSPS)
71
71.6
72.2
72.8
73.4
74
SNR/SINAD (dB)
11
11.4
11.8
12.2
12.6
13
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
REF
= 5V
25 50 100 250 500 1000
Sample Rate (kSPS)
-108
-104
-100
-96
-92
-88
THD(dB)
90
94
98
102
106
110
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
THD(dB)
90
95
100
105
SFDR(dB)
THD (dB)
SFDR(dB)
V
REF
= 1.8V
25 50 100 250 500 1000
Sample Rate (kSPS)
70
70.6
71.2
71.8
72.4
73
SNR/SINAD (dB)
10
10.6
11.2
11.8
12.4
13
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
REF
= 1.8V
25 50 100 250 500 1000
Sample Rate (kSPS)
-106
-102
-98
-94
-90
-86
THD(dB)
89
93
97
101
105
109
SFDR(dB)
THD(dB)
SFDR(dB)
VREF = 1.8V
MCP33151D/41D-XX
DS20006219A-page 24 2019 Microchip Technology Inc.
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-31: Shorted Input Histogram:
VREF = 5V.
FIGURE 3-32: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 3-33: Power Consumption vs.
Sample Rate, MCP33141D-10:
CLOAD_SDO = 20 pF.
FIGURE 3-34: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 3-35: Offset and Gain Error vs.
Temperature: VREF = 1.8V.
FIGURE 3-36: Power Consumption vs.
Sample Rate, MCP33141D-05:
CLOAD_SDO = 20 pF.
-3-2-10123
Output Code
0
2
4
6
8
10
Occurrences
105
779082
269494
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-2500
-2000
-1500
-1000
-500
0
500
1000
1500
OFFSET/GAIN ERROR (uV)
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
OFFSET/GAIN ERROR (LSB)
OFFSET ERROR
GAIN ERROR
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Total Power (mW)
MCP33141D-10
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Frequency (kHz)
72
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
OFFSET/GAIN ERROR (uV)
-1.1
-0.9
-0.7
-0.5
-0.2
0.0
0.2
0.5
0.7
0.9
1.1
OFFSET/GAIN ERROR (LSB)
OFFSET ERROR
GAIN ERROR
V
REF
= 1.8V
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.1
0.2
0.3
0.4
0.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.6
1.2
1.8
2.4
3
Total Power (mW)
MCP33141D-05
2019 Microchip Technology Inc. DS20006219A-page 25
MCP33151D/41D-XX
Note: Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
FIGURE 3-37: Power Consumption vs.
Temperature, MCP33141D-10:
CLOAD_SDO = 20 pF.
FIGURE 3-38: Power Consumption vs.
Temperature during Shutdown (Standby).
FIGURE 3-39: Power Consumption vs.
Temperature, MCP33141D-05:
CLOAD_SDO = 20 pF.
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Total Power (mW)
MCP33141D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
1
2
3
4
5
6
7
8
Current ( A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
2
4
6
8
10
12
14
16
Total Power ( W)
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.1
0.2
0.3
0.4
0.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
0.6
1.2
1.8
2.4
3
Total Power (mW)
MCP33141D-05
MCP33151D/41D-XX
DS20006219A-page 26 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 27
MCP33151D/41D-XX
4.0 PIN DESCRIPTIONS
FIGURE 4-1: Pin Configurations.
TABLE 4-1: PIN FUNCTION TABLE
Pin Number
Pin Name Description
MSOP-10 TDFN-10
11V
REF Reference voltage input (AVDD - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
22AV
DD DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
33A
IN+ Differential positive analog input.
44A
IN- Differential negative analog input.
5 5 GND Power supply ground reference. This pin is a common ground for both the
analog power supply (AVDD) and digital I/O supply (DVIO).
6 6 CNVST Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering
CNVST.
7 7 SDO SPI-compatible serial digital data output: ADC conversion data is shifted out
by SCLK clock, with MSB first.
8 8 SCLK SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9 9 SDI SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10 10 DVIO DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 µF ceramic capacitor.
— 11 EP Exposed Thermal Pad. Not internally bonded (NC).
MSOP-10 TDFN-10 *
* Includes Exposed Thermal Pad (see Tab le 4-1).
MCP33151D/41D-XX
DS20006219A-page 28 2019 Microchip Technology Inc.
4.1 Supply Voltages (AVDD, DVIO)
The device has two power supply pins: (a) 1.8V
analog power supply (AVDD), and (b) 1.7V to 5.5V
digital input/output interface power supply (DVIO).
Since DVIO has a very wide voltage range, some I/O
interface signal parameters have slightly different
timing specifications depending on the DVIO value.
See Serial Interface Timing Specifications for details.
4.2 Reference Voltage (VREF)
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from AVDD to 5.1V. This reference voltage sets the
differential input full-scale range from -VREF to +VREF
.
The reference pin needs a tantalum decoupling
capacitor (10 F, 10V rating). Additional multiple
ceramic capacitors can be added in parallel to
decouple high-frequency noise.
4.2.1 VOLTAGE REFERENCE
SELECTION
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
must be less than 1/2 LSB of the ADC.
4.3 Power-Up Sequence and
Auto-Calibration
The device will perform an automatic calibration on
power-up approximately 40 ms after all three power
rails (AVDD, DVIO, and VREF) are powered by their
respective voltage supplies. The calibration process
will take approximately 400 ms to complete before the
device will be ready for acquisition. To avoid potential
auto-calibration issues, all supplies must be fully
stabilized < 40 ms from the moment power is initially
supplied. All digital activity must be avoided prior to
and during device calibration. At higher operating
temperatures (>85°C) it may be necessary to provide
additional time for the device to complete calibration
(up to 550ms at 125°C). Therefore it is advisable to
wait at least 450-500 ms following power-on before
initiating any other activity. Otherwise, it may be
necessary to send a manual recalibration command to
ensure proper operation. See Figure 4-2 for example
power-on operation timing, and refer to Section 6.2
“Recalibrate Command” for more details regarding
initiating manual recalibration. Once the device
finishes calibration it will automatically enter
Acquisition (ACQ) mode.
FIGURE 4-2: Power-Up Sequence and Auto-Calibration Timing Diagram.
Note: Unlike manual recalibration, there will be no activity on SDO to indicate completion of auto-calibration.
Refer to Section 6.2 “Recalibrate Command” for more details.
Note: Proper decoupling capacitors (1 µF to
AVDD, 0.1 µF to DVIO) should be mounted
as close as possible to the respective
pins.
ADC
State
AVDD
VREF
DVIO
Device Calibration (tCAL = ~ϰ00ms)
Wait (tWAIT = ~40 ms)
WAIT CALIBRATION ACQUISITION MODE
2019 Microchip Technology Inc. DS20006219A-page 29
MCP33151D/41D-XX
5.0 DEVICE OVERVIEW
When the MCP33151D/41D-XX is first powered-up, it
automatically performs a self-calibration and enters a
low-current input acquisition mode (Standby).
The external reference voltage (VREF), ranging from
AVDD to 5.1V, sets the differential input full-scale range
(FSR) from -VREF to +VREF
.
The differential input signal needs an appropriate input
common-mode voltage from 0V to VREF
, depending on
the input signal condition. VREF/2 is typically used for a
symmetric differential input.
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes a typical current of
1.5 µA.
The user can operate the device with an easy-to-use,
SPI-compatible, 3-wire interface.
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data
conversion time (tCNV) is set by the internal clock.
Once the conversion is complete and the host lowers
CNVST, the output data is available on SDO and the
device automatically starts the next input acquisition.
During this input acquisition time (tACQ), the user can
clock out the output data by providing the
SPI-compatible serial clock (SCLK).
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
5.1 Analog Inputs
Figure 5-1 shows a simplified equivalent circuit of the
differential input architecture with a switched capacitor
input stage. The input sampling capacitors
(CS+and CS-) are about 10 pF each. The back-to-back
diodes (D1–D
2) at each input are ESD protection
diodes. Note that these ESD diodes are tied to VREF
, so
that each input signal can swing from 0V to +VREF and
from -VREF to +VREF differentially.
During input acquisition (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈10 pF) in series with the on-resistance of
the sampling switch, RSON (≈350).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
time. Although the device can be driven directly with a
low impedance source, using a low-noise input driver,
such as the MCP6D11, is highly recommended.
FIGURE 5-1: Simplified Equivalent
Analog Input Circuit.
5.1.1 ABSOLUTE MAXIMUM INPUT
VOLTAGE RANGE
The input voltage at each input pin (AIN+ and AIN-)
must meet the following absolute maximum input
voltage limits:
•(V
IN+, VIN-) < VREF + 0.1V
•(V
IN+, VIN-) > GND - 0.1V
Note: The ESD diodes at the analog input pins
are biased from VREF
. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
Where:
CS+, CS-= input sample and hold capacitor ≈10 pF,
RSON = On-resistance of the sampling switch ≈350
CPIN = Package pin + ESD capacitor ≈2pF.
CPIN D2
D1
ILEAKAGE
(~±1 nA)
VREF
VT = 0.6V
SW1
-RSON CS
-SW2
-
(350Ω) (10 pF)
CPIN D2
D1
ILEAKAGE
(~±1 nA)
VREF
VT = 0.6V
SW1
+RSON CS
+SW2
+
(350Ω) (10 pF)
AIN
+
AIN
-
Sample VIN
+
Sample VIN
-
MCP33151D/41D-XX
DS20006219A-page 30 2019 Microchip Technology Inc.
5.1.2 INPUT VOLTAGE RANGE
The differential input (VIN) and common-mode voltage
(VCM) at the input pins are defined by Equation 5-1:
EQUATION 5-1: DIFFERENTIAL INPUT
The input signal swings around an input
common-mode voltage (VCM), typically centered at
VREF/2 for the best performance.
The absolute value of the differential input (VIN) needs
to be less than the reference voltage. The device will
output saturated output codes if the absolute value of
the input (VIN) is greater than the reference voltage.
The differential input full-scale voltage range (FSR) is
given by the external reference voltage (VREF) setting
(see Equation 5-2).
EQUATION 5-2: FSR AND INPUT RANGE
5.2 Analog Input Conditioning
Circuits
The MCP33151D/41D-XX supports various input
types, such as: fully-differential inputs, arbitrary
waveform inputs and single-ended inputs.
5.2.1 FULLY-DIFFERENTIAL INPUT
SIGNALS
The MCP33151D/41D-XX provides the best linearity
performance with fully-differential inputs. Figure 5-2
shows an example of a fully-differential input
conditioning circuit with a differential input driver
followed by an RC anti-aliasing filter. Figure 5-3 shows
its transfer function.
The differential input (VIN) between the two differential
ADC analog input pins (AIN+, AIN-) swings from -VREF
to +VREF centered at the input common-mode voltage
(VOCM).
The front-end differential driver provides a low output
impedance, which provides fast settling of the analog
inputs during the acquisition phase and provides
isolation between the signal source and the ADC. The
RC low-pass anti-aliasing filter band-limits the output
noise of the input driver and attenuates the kick-back
noise spikes from the ADC during conversion.
Figure 5-2 is the reference circuit that is used to collect
most of the linearity performance data shown in
Section 1.0 “Key Electrical Characteristics”.
The differential input driver shown in Figure 5-2 can be
replaced with a low noise dual-channel op-amp. See
Section 5.3 “ADC Input Driver Selection” for the
driver selection.
5.2.2 ARBITRARY WAVEFORM INPUT
SIGNALS
The MCP33151D/41D-XX can convert input signals
with arbitrary waveforms at the inputs AIN+ and AIN-.
These inputs can be symmetric, non-symmetric or
independent with respect to each other.
In the arbitrary input configuration, each ADC analog
input is connected to a single ended source ranging
from 0V to VREF
. In this case, the ADC converts the
voltage difference between the two input signals.
Figure 5-4 shows the configuration example for the
arbitrary input signals.
5.2.3 SINGLE-ENDED INPUT SIGNALS
Although the MCP33151D/41D-10 is a fully-differential
input device, it can also convert single-ended input
signals. The most commonly recommended
single-ended configurations are:
• pseudo-differential bipolar configuration, and
• pseudo-differential unipolar configuration.
5.2.3.1 Pseudo-Differential Bipolar
Configuration
In the pseudo-differential bipolar configuration, one of
the ADC analog inputs (typically AIN-) is driven with a
fixed DC voltage (typically VREF/2), while the other
(AIN+) is connected to a single-ended signal in the
range 0V to VREF
.
In this case, the ADC converts the voltage difference
between the single-ended signal and the DC voltage.
Figure 5-5 shows the configuration example and
Figure 5-6 shows its transfer function.
Note: Saturation output codes:
01111111111111 for VIN > VREF
10000000000000 for VIN < -VREF
VIN VIN+VIN-
–=
VCM
VIN+VIN-
+
2
---------------------------=
Where:
VIN+= the input at the AIN+ pin,
VIN-= the input at the AIN- pin.
Input Full-Scale Range (FSR) 2VREF
=
Input Range: VREF
–VIN VREF 1 LSB–

2019 Microchip Technology Inc. DS20006219A-page 31
MCP33151D/41D-XX
5.2.3.2 Pseudo-Differential Unipolar
Configuration
In the pseudo-differential unipolar input configuration,
one of the ADC analog inputs (typically AIN-) is
connected to ground, while the other (AIN+) is
connected to a single ended signal in the range 0V to
VREF
.
In this case, the ADC converts the voltage difference
between the single ended signal and ground.
Figure 5-7 shows the configuration example and
Figure 5-8 shows its transfer function.
FIGURE 5-2: Input Conditional Circuit for Fully-Differential Input.
FIGURE 5-3: Transfer Function for Figure 5-2.
MCP331x1D-XX
AIN+
AIN-
GND
SDO
SCLK
CNVST
SDI
VREF AVDD DVIO
Host Device
(PIC32MZ)
1.8V 1.8V to 5.5V
R1
R1
C1
C1
Voltage Reference
(MCP1501)
VREF
CR
10 μF
RF
RF
RG
RG
VREF/2
Input Driver
0V
VREF
Differential
Inputs
(Note 2)
(Note 1)
VDC
VOCM
0V
VREF
VREF/2
0V
VREF
VREF/2
0V
VREF
fc =1
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of MCP6D11 differential driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
Differential Input Voltage
+VREF - 1 LSB
Digital Output Code (Two’s Complement)
-VREF
0VIN
Available VIN range
2n/2 - 1
- 2n/2
MCP33151D/41D-XX
DS20006219A-page 32 2019 Microchip Technology Inc.
FIGURE 5-4: Input Configuration for Arbitrary Waveform Input Signals.
FIGURE 5-5: Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal.
FIGURE 5-6: Transfer Function for Figure 5-5.
MCP331x1D-XX
AIN+
AIN-
GND
SDO
SCLK
CNVST
SDI
VREF AVDD DVIO
Host Device
(PIC32MZ)
1.8V 1.8V to 5.5V
R1
R1
C1
C1
Voltage Reference
(MCP1501)
VREF
CR
10 μF
Low Noise Input Buffer
0V
VREF
0V
VREF
Arbitrary Waveform
Differential Input
(Note 2)
(Note 1)
VDC
fc =1
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
MCP331x1D-XX
AIN+
AIN-
GND
SDO
SCLK
CNVST
SDI
VREF AVDD DVIO
Host Device
(PIC32MZ)
1.8V 1.8V to 5.5V
R1
R1
C1
C1
Voltage Reference
(MCP1501)
VREF
CR
10 μF
Low Noise Input Buffer
Single-Ended Input
(Note 2)
(Note 1)
VDC
0V
VREF
VREF/2
0V
VREF
VREF/2
1 μF
fc =1
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
Analog Input Voltage
+VREF - 1 LSB
Digital Output Code (Two’s Complement)
-VREF
- 2n/2
0
VIN
+VREF/2
2n/4
- 2n/4
-VREF/2
Available VIN range
2n/2 - 1
2019 Microchip Technology Inc. DS20006219A-page 33
MCP33151D/41D-XX
FIGURE 5-7: Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal.
FIGURE 5-8: Transfer Function for Figure 5-7.
MCP331x1D-XX
AIN+
AIN-
GND
SDO
SCLK
CNVST
SDI
VREF AVDD DVIO
Host Device
(PIC32MZ)
1.8V 1.8V to 5.5V
R1
R1
C1
C1
Voltage Reference
(MCP1501)
VREF
CR
10 μF
Low Noise Input Buffer
Single-Ended Input
(Note 2)
(Note 1)
VDC
0V
VREF
VREF/2
0V
VREF
VREF/2
fc =
1
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
Analog Input Voltage
+VREF
Digital Output Code (Two’s Complement)
-VREF
0
VIN
+VREF/2
2n/4
-VREF/2
- 2n/4
- 2n/2
Available VIN range
2n/2 - 1
MCP33151D/41D-XX
DS20006219A-page 34 2019 Microchip Technology Inc.
5.3 ADC Input Driver Selection
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance
specifications than the ADC itself. The data sheet of the
driver typically shows the output noise voltage and
harmonic distortion parameters.
Figure 5-9 shows a simplified system noise presenta-
tion block diagram for the front-end driver and ADC.
FIGURE 5-9: Simplified System Noise
Representation.
• Unity Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the
driver should have the unity gain bandwidth greater
than 5 times the -3 dB cutoff frequency of the
anti-aliasing filter:
EQUATION 5-3: BANDWIDTH
REQUIREMENT FOR ADC
INPUT DRIVER
•Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
EQUATION 5-4: RECOMMENDED THD
FOR ADC INPUT DRIVER
• ADC Input-Referred Noise:
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise is
approximated as shown in Equation 5-5:
EQUATION 5-5: ADC INPUT-REFERRED
NOISE
•Noise Contribution from the Front-End Driver:
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise
density and 1/f noise. When an anti-aliasing filter is
used after the input driver, the output noise density of
the input driver is integrated over the -3 dB bandwidth
of the filter.
Equation 5-6 shows the RMS output noise voltage
calculation using the RC filter’s bandwidth and noise
density (eN) of the input driver. GN in Equation 5-6 is
the noise gain of the driver amplifier and becomes 1 for
a unity gain buffer driver.
EQUATION 5-6: NOISE FROM FRONT-END
DRIVER AMPLIFIER
In Equation 5-6, 1/f noise (eNFlicker) is ignored
assuming it is very small compared to the broadband
noise (eN).
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 5-7:
EQUATION 5-7: RECOMMENDED ADC
INPUT DRIVER NOISE
R
C
ADC
Front-End Driver
-+-+
VN_RMS_Driver Noise
VN_ADC Input-Referred Noise
BWInput Driver 5f
B
5
2
RC
--------------
, for a single-pole RC filter.
Where:
fB= -3 dB bandwidth of RC anti-aliasing
filter, as shown in Figure 5-9.
(Hz)
THDInput Driver THDADC 10 (dB)–
VN_ADC Input-Referred Noise
FSR
22
---------- 1 0
SNR
20
----------–
=
VREF
2
------------10
SNR
20
----------–
=
VREF
22
------------10
SNR
20
----------–
=
(V)
, for differential input;
, for single-ended input.
Where FSR is the input full-scale range of the ADC.
VN_RMS_Driver_Noise GN
eN
2
-------
fB
=V
Where eN is the broadband noise density (V/√Hz) of
the front-end driver amplifier and is typically given in
its data sheet.
VN_RMS_Driver_Noise
1
5
---VN_ADC_Input-Referred_Noise
2019 Microchip Technology Inc. DS20006219A-page 35
MCP33151D/41D-XX
Using Equation 5-5 to Equation 5-7, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 5-8:
EQUATION 5-8: NOISE DENSITY FOR ADC
INPUT DRIVER
Using Equation 5-8, the recommended maximum
noise voltage density limit for unity gain input driver for
differential input ADC can be estimated. Table 5-1 and
Table 5-2 show a few example results with GN=1.
These tables may be used as a reference when
selecting the ADC input driver amplifier.
TABLE 5-1: NOISE VOLTAGE DENSITY
(EN) OF INPUT DRIVER FOR
MCP33151D-XX
ADC (Note 1)RC
Filter
ADC Input
Driver
Amplifier
(GN=1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise
Voltage
Density (eN)
1.8V 78.8 146 µV 3 MHz 13.5 nV/√Hz
4MHz 11.7nV/√Hz
5MHz 10.4nV/√Hz
3V 81.8 172 µV 3MHz 15.9 nV/√Hz
4MHz 13.8 nV/√Hz
5MHz 12.3 nV/√Hz
5V 83.7 231 µV 3 MHz 21.3 nV/√Hz
4MHz 18.4nV/√Hz
5MHz 16.5nV/√Hz
Note 1: See Equation 5-5 for the ADC
input-referred noise calculation for
differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing
filter.
GN
eN
2
-------
fB
1
5
---VN_ADC_Input_Referred_Noise
eN
1
5GN
-----------1
fB
------------ V REF10
SNR
20
----------–
V
Hz
-----------


eN
1
10GN
--------------1
fB
------------ V REF10
SNR
20
----------–
V
Hz
-----------


(a) eN for differential input ADC:
(a) eN for single-ended input ADC:
TABLE 5-2: NOISE VOLTAGE DENSITY
(eN) OF INPUT DRIVER FOR
MCP33141D-XX
ADC (Note 1)RC
Filter
ADC Input
Driver
Amplifier
(GN=1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise
Voltage
Density (eN)
1.8V 72 319.7 µV 3 MHz 29.5 nV/√Hz
4MHz 25.5nV/√Hz
5MHz 22.8nV/√Hz
3V 73.6 443.2 µV 3MHz 40.8 nV/√Hz
4MHz 35.4 nV/√Hz
5MHz 31.6 nV/√Hz
5V 73.8 721.9 µV 3 MHz 66.5 nV/√Hz
4MHz 57.6nV/√Hz
5MHz 51.5nV/√Hz
Note 1: See Equation 5-5 for the ADC
input-referred noise calculation for
differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing
filter.
MCP33151D/41D-XX
DS20006219A-page 36 2019 Microchip Technology Inc.
5.4 Device Operation
When the MCP33151D/41D-XX is first powered-up, it
self-calibrates internal systems and automatically
enters Input Acquisition mode. The device operates in
two phases: (a) Input Acquisition (Standby) and (b)
Data Conversion. Figure 5-10 shows the ADC’s
operating sequence.
5.4.1 INPUT ACQUISITION PHASE
(STANDBY)
During the input acquisition phase (tACQ), also called
Standby, the two input sampling capacitors, CS+ and
CS-, are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
be fully settled within 1/2 LSB during tACQ.
The acquisition time (tACQ) is user-controllable. The
system designer can increase the acquisition time
(tACQ) as much as needed to reduce sampling rate for
additional power savings.
5.4.2 DATA CONVERSION PHASE
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
The data conversion time (tCNV) is not user
controllable. After the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO.
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
external environment noise, minimize I/O events and
running clocks during the conversion time.
The output data is clocked out MSB first. While the
output data is being transferred, the device enters the
next input acquisition phase.
FIGURE 5-10: Device Operating Sequence.
Note: Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI interface
and the rising edge on CNVST. See
Figure 1-1 for tQUIET
.
Operating tACQ
(b) All circuits are turned-on.
(a) ADC acquires input sample #1.
Condition
I
(c) Most analog circuits are
(a) Device is first powered-up and
(b) No ADC output is available yet.
(c) ADC output is not available yet.
t
ACQ
(b) Performs a power-up self-calibration.
IDDAN
(a) Conversion is initiated at the rising edge of CNVST.
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(b) ADC output can be clocked out
(c) ADC acquires input sample #2.
(d) Most analog circuits are turned off.
Input Acquisition Data Conversion Input Acquisition
turned off.
SDO Output Data
~ 1.5 µA
Off
(Standby) (Standby)
MCP331x1D-10: 490 ns (typical)
by providing clocks.
t
CNV
tCYC = 1/fS
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: 510 ns (typical)
MCP331x1D-05: 1200 ns (typical)
MCP331x1D-10: 490 ns (typical)
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: ~0.66 mA
MCP331x1D-05: ~0.33 mA
2019 Microchip Technology Inc. DS20006219A-page 37
MCP33151D/41D-XX
5.4.3 SAMPLE THROUGHPUT RATE
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 5-9 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
EQUATION 5-9: SAMPLE RATE
5.4.4 SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by Equation 5-10:
EQUATION 5-10: SPI CLOCK FREQUENCY
REQUIREMENT
5.4.5 SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by Equation 5-10:
(a) MCP331X1D-10:
(b) MCP331X1D-05:
Sample Rate 1
tACQ tCNV
+
-----------------------------------=
Sample Rate 1
250 ns 750 ns+
--------------------------------------------1 Msps==
Sample Rate 1
600 ns 1400 ns+
-----------------------------------------------500 kSPS==
tACQ NT
SCLK tQUIET tEN
++
=
fSCLK
1
TSCLK
-------------- N
tACQ tQUIET tEN
+–
-----------------------------------------------------==
Where:
fSCLK = minimum SPI serial clock
frequency required to transfer all
N-bits of output data during tACQ
N= number of output data bits
TSCLK = Period of SPI clock
N×T
SCLK = Output data window
tQUIET = Quiet time between the last output
bit and beginning of the next
conversion start
=10ns (Min.)
tEN = Output enable time
= 10 ns (Max.) with DVIO ≥2.3V
Note: Refer to Serial Interface Timing
Specifications for relevant timing
information and see Figure 1-1 for
interface timing diagram.
MCP33151D/41D-XX
DS20006219A-page 38 2019 Microchip Technology Inc.
5.5 Transfer Function
The differential analog input is VIN = (VIN+) – (VIN-).
The LSB size is given by Equation 5-11. and an
example of LSB size vs. reference voltage is
summarized in Ta b l e 5 - 3 .
EQUATION 5-11: LSB SIZE (EXAMPLE)
Figure 5-11 shows the ideal transfer function and
Table 5-4 shows the digital output codes for the
MCP33151D/41D-XX.
FIGURE 5-11: Ideal Transfer Function for
Fully-Differential Input Signal.
5.6 Digital Output Code
The digital output code is proportional to the input
voltage. The output data is in binary two’s complement
format. With this coding scheme the MSB can be
considered a sign indicator. When the MSB is a logic
‘0’, the input is positive. When the MSB is a logic ‘1’, the
input is negative. The following is an example of the
output code:
(a) for a negative full-scale input:
Analog Input: (VIN+) – (VIN-) = -VREF
Output Code: 1000...0000
(b) for a zero differential input:
Analog Input: (VIN+) – (VIN-) = 0V
Output Code: 0000...0000
(c) for a positive full-scale input:
Analog Input: (VIN+) – (VIN-) = +VREF
Output Code: 0111...1111
The MSB (sign bit) is always transmitted first through
the SDO pin.
The code will be locked at 0111...11 for all voltages
greater than (VREF - 1 LSB) and 1000...00 for
voltages less than -VREF
. Tab le 5-4 shows an example
of output codes of various input levels.
TABLE 5-3: LSB SIZE VS. REFERENCE
Reference
Voltage
(VREF)
LSB Size
MCP33151D-XX
(14-bit)
MCP33141D-XX
(12-bit)
1.8V 219.7 µV 879.8 µV
2V 244 µV 976.6 µV
2.5V 305.2 µV 1.2207 mV
3V 366.2 µV 1.4648 mV
3.3V 402.8 µV 1.6113 mV
3.5V 427.3 µV 1.7090 mV
4V 488.3 µV 1.9531 mV
4.5V 549.3 µV 2.1973 mV
5V 610.4 µV 2.4414 mV
5.1V 622.6 µV 2.4902 mV
LSB 2VREF
2N
---------------=
Where N is the resolution of the ADC in bits.
011 … 111
100 … 000
100 … 001
000 … 000
-VREF + 1 LSB
-VREF + 0.5 LSB
-VREF
0V
+VREF - 1.5 LSB
+VREF - 1 LSB
Differential Analog Input Voltage
Digital Output Code (Two’s Complement)
011 … 110
+VREF - 2 LSB
2019 Microchip Technology Inc. DS20006219A-page 39
MCP33151D/41D-XX
5.7 Data Accumulator
The MCP33151D/41D-XX devices feature an internal
integrator capable of accumulating consecutive sample
data and transmitting the accumulated data directly
from the ADC, without requiring any special SPI
settings to operate. This enables the user to achieve a
higher ENOB through consecutive sample integration
utilizing the ADC hardware, without requiring any
external computational resources and reducing the
amount of data transmitted on the serial bus. See
Figure 5-12 for an example FFT performance plot after
1024 integrated samples while sampling a 75Hz input
signal with a 5V reference voltage. Refer to Figure 5-13
for an example of FFT performance across possible
integration lengths.
FIGURE 5-12: FFT with 1024 integrated
samples: Input Freq = 75Hz.
FIGURE 5-13: FFT with 1024 integrated
samples: Input Freq = 75Hz.
5.7.1 DATA ACCUMULATOR USAGE
Data accumulation is performed automatically within
the device between each sequential
Conversion/Acquisition cycle (TCYC) whenever the
current conversion results are not read out, up to a total
of 1024 consecutive conversions for an ENOB increase
of up to 5 bits above typical. To begin data
accumulation, the user simply avoids transmitting any
SCLK pulses during each sequential conversion cycle.
Note: If a sample has been converted but not
read out, the sample can be discarded by
providing at least 1 SCLK pulse before ini-
tiating the next conversion. Providing at
least 1 SCLK will reset the system for sin-
gle acquisition. Otherwise all consecutive
conversions without an SCLK pulse will
automatically be integrated with the previ-
ous conversion results.
TABLE 5-4: DIGITAL OUTPUT CODE
Input Voltage (V)
Digital Output Codes
MCP33151D-XX
(14-bit)
MCP33141D-XX
(12-bit)
VREF 01-1111-1111-1111 0111-1111-1111
VREF - 1 LSB 01-1111-1111-1111 0111-1111-1111
.
.
.
.
.
.
2LSB 00-0000-0000-0010 0000-0000-0010
1LSB 00-0000-0000-0001 0000-0000-0001
0V 00-0000-0000-0000 0000-0000-0000
-1 LSB 11-1111-1111-1111 1111-1111-1111
-2 LSB 11-1111-1111-1110 1111-1111-1110
.
.
.
.
.
.
-VREF 10-0000-0000-0000 1000-0000-0000
< -VREF 10-0000-0000-0000 1000-0000-0000
0 0.1 0.2 0.3 0.4 0.5
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
fs = 1/1024 Msps
SNR = 116.7 dBFS
SINAD = 111.5 dBFS
SFDR = 117.2 dBc
THD = -113.5 dBc
ENOB = 18-bit
Resolution = 24-bit
VREF = 5V
1 4 16 64 256 1024
Integration Length
75
80
85
90
95
100
105
110
115
120
SNR/SINAD (dB), SFDR (dBc)
SNR (dB)
SINAD(dB)
SFDR(dBc)
THD (dB)
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
MCP33151D/41D-XX
DS20006219A-page 40 2019 Microchip Technology Inc.
After completing the desired number of conversions to
achieve the target ENOB, the user can begin
transferring the total accumulated data by transmitting
the necessary number of SCLK pulses to transfer all
stored bits. Refer to Ta ble 5 -5 for number of
conversions, bit size and ENOB relationship. See
Figure 6-5 and Figure 6-8 for example
Conversion/Acquisition control and SPI timing
operation.
Consecutive sample integration increases the bit size
of the output data, up to the maximum output size of the
ADC (24-bits / 18.5 ENOB at 1024 samples for a 14-bit
ADC).
Because the addition of two binary values can produce
a sum with an increased bit size, the ADC will need to
output data proportional to the amount of samples
being integrated. See Ta bl e 5 -5 for an estimate of the
data size and ENOB capability depending on the
number of conversions the user chooses to integrate.
When using the accumulator, it is important to consider
the frequency content of the input signal being
sampled. Because the accumulator is averaging all
consecutive conversions over the accumulated time
period, the input frequency must be low enough to
ensure that no signal information is being filtered out.
This means that there is a performance trade-off
between sample integration length (and resulting
ENOB improvement) and the maximum input
frequency that can be sampled. Refer to Ta bl e 5 - 6 to
understand the roll-off frequencies for various
integration lengths, and refer to Figure 5-14 for an
example of the dB attenuation across integration
lengths.
TABLE 5-5: ACCUMULATED DATA SIZE
AND ENOB FOR 14-BIT ADC
Note 1: ENOB values based on typical 14b device
characteristics under nominal conditions
and setting N to the maximum value in the
corresponding row.
Note: The discrepancy between the output data
size and the actual ENOB is a result of
sample integration doubling both the signal
amplitude and the noise power for each
factor of two that the samples are inte-
grated. By integrating 2 samples, the signal
amplitude increases SNR by 6 dB, and the
noise power decreases SNR by 3 dB,
resulting in an overall SNR increase of 3 dB
(+0.5 ENOB).
TABLE 5-6: INPUT SIGNAL ROLL-OFF
FREQUENCY VS
INTEGRATION LENGTH
FIGURE 5-14: Measured Attenuation of
Fundamental Frequency (dB) vs Integration
Length: Input Freq = 75 Hz.
Number of
Conversions
ADC
transmission
size (bits)
Effective
Number of bits
(ENOB) (1)
1 14 13.5
215 14
3 - 4 16 14 - 14.5
5 - 8 17 14.5 - 15
9 - 16 18 15 - 15.5
17 - 32 19 15.5 - 16
33 - 64 20 16 - 16.5
65 - 128 21 16.5 - 17
129 - 256 22 17 - 17.5
257 - 512 23 17.5 - 18
513 - 1024 24 18 - 18.5
Integration
Length
Roll-Off (Hz @ 1MSPS)
0.1 dB 0.01 dB 0.001 dB
2 41781.9 13226.3 4183.0
4 20890.9 6613.2 2091.5
8 10445.5 3306.6 1045.7
16 5222.7 1653.3 522.9
32 2611.4 826.6 261.4
64 1305.7 413.3 130.7
128 652.8 206.7 65.4
256 326.4 103.3 32.7
512 163.2 51.7 16.3
1024 81.6 25.8 8.2
1 4 16 64 256 1024
Integration Length
-0.08
-0.06
-0.04
-0.02
0
0.02
Attenuation (dB)
2019 Microchip Technology Inc. DS20006219A-page 41
MCP33151D/41D-XX
6.0 DIGITAL SERIAL INTERFACE
The device has an SPI compatible serial digital
interface using four digital interface pins: CNV, SDI,
SDO and SCLK.
The following sections describe the operation of the
MCP33151D/41D-XX using the digital serial interface.
Table 6-1 summarizes the descriptions of both digital
interface pins and interface options, respectively. The
communication is always started by the host device
(Master).
6.1 Serial Interface Options and Serial
Communications
The device offers a CS mode with 3-wire interface,
and can operate either with or without a BUSY
indicator status output. This BUSY status output bit is
followed by the conversion output bits, and can be
used as an interrupt request (IRQ) input for the digital
host device.
The 3-Wire CS mode (using CNV, SCLK, SDO)
interface is simple and useful when the host device
handles a single MCP33151D/41D-XX device.
The following sections detail the serial communication
of the 3-Wire CS modes with or without a BUSY output.
6.1.1 CS MODES
6.1.1.1 3-Wire CS MODE WITHOUT BUSY
OUTPUT BIT
This interface option is most useful when a single
MCP33151D/41D-XX is connected to an
SPI-compatible digital host. Figure 6-1 shows the
connection diagram with the host device. In this mode,
CNV functions as both conversion control and chip
select (CS).
To enable this interface option, SDI can either be tied
to VIO, or otherwise permanently held in a Logic = 1
state. By doing so, the device will never output a BUSY
status bit.
As shown in Figure 6-2, at the rising edge of CNV, the
conversion is initiated. The SDO pin becomes high-Z
state (if no external pull-up is used). Once the
conversion is initiated, it continues and the ADC
completes the conversion regardless of the state of the
CNV pin. This means the CNV pin can be used for
other SPI devices after the conversion is initiated.
When conversion is complete, the device enters the
acquisition phase (Power-Down state), and SDO
comes out of the high-Z state when CNV is lowered.
The device exits the acquisition phase when CNV goes
“High”. SDO returns to a high-Z state after the 14th
SCLK falling edge or when CNV goes high, whichever
occurs first.
The device will output the MSB on the SDO pin
following the falling edge of CNV, or once the
Converting Phase (tCNV) completes, whichever
happens later. The remaining data bits are then
clocked out on the subsequent SCLK falling edges.
Data is valid on both edges of SCLK and can be
captured on either edge. However, a digital host
capturing data on the SCLK falling edge can achieve a
faster read out rate.
It is recommended to use this mode only when the ADC
Converting Phase (tCNV) will complete before the fall-
ing edge of CNV.
Figure 6-2 and Figure 6-3 show the timing diagrams for
both early and late CNV lowering scenarios.
Note: This device supports a standard SPI
Mode 0,0 only.
SPI MODE 0,0: In this mode, the SCLK
Idle state is “Low”. Data is clocked out on
the SDO pin on the falling edge of the
SCLK pin.
For the MCP33151D/41D-XX, this means
that there will be a rising edge before
there is a falling edge.
TABLE 6-1: INTERFACE MODE SELECTION SUMMARY
Interface Mode
SDI Pin
CNV Pin at tCNV
(recommended)
SCLK at
CNV
Rising
Edge
BUSY bit
at SDO
At CNV
Rising Edge
After CNV
Rising Edge
3-Wire CS Mode without
BUSY output bit
“High” Transition from “High” to
“Low” after tCNV (Max)
—No
3-Wire CS Mode with
BUSY output bit
“Low” Transition from “High” to
“Low” before tCNV (Max)
—Yes
Note: The timing diagram examples in the
following subsections are shown for 14-bit
mode only. The examples are applicable
for 12-bit mode in the same way with
reduced bits.
MCP33151D/41D-XX
DS20006219A-page 42 2019 Microchip Technology Inc.
FIGURE 6-1: Connection Diagram for
3-Wire CS Mode without BUSY Status Indicator
Output Bit.
FIGURE 6-2: Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output
Bit, Late CNV (Recommended).
CNVST
SDI
(Data In)
SC>K
CNV
SDISDO
SC>K
VIO
(a) MCP331xx (b) Digital Host (Master)
47 kΩ
VIO
SDI = 1
SC>K
SDO
CNV (
CS
)
TCYC = 1/fs
D13 D12 D11 D10 D9 D0D1D2
“High” (with pull-up)
,ŝŐŚ-Z (with no pull-up)
t
SCLK
tDO tSCLK_L tSCLK_H
12345121314
t
CNVH
tEN tQUIET
tDIS
ADC
State
Converting Phase
(t
CNV
)
Input Acquisition
(t
ACQ
)
t
SU_SDIH_CNV
2019 Microchip Technology Inc. DS20006219A-page 43
MCP33151D/41D-XX
FIGURE 6-3: Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output
Bit, Early CNV.
FIGURE 6-4: Interface Timing Diagram for Accumulator Operation in 3-Wire CS Mode without
BUSY Status Indicator Output Bit.
Note: Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature.
SDI = 1
SC>K
SDO
ADC
State
CNV (CS)
TCYC = 1/fs
Converting Phase
(tCNV)
Input Acquisition
(tACQ)
D13 D12 D11 D10 D9 D0D1D2
tSCLK
tDO tSCLK_L tSCLK_H
12345121314
tCNVH
“High” (with pull-up)
HŝŐŚ-Z (with no pull-up)
tEN
tQUIET
tDIS
tSU_SDIH_CNV
SDI = 1
SCLK
SDO
CNV (CS)
TCYC(1)
= 1/fs
DM-1 DM-2 DM-3 D0
D1
D2
tSCLK
tDO tSCLK_H tSCLK_L
123 M-2
tCNVH
tEN tQUIET
tDIS
ADC
State
tCNV
tSU_SDIH_CNV
tACQ tACQ
tCNVH
TCYC(N) = 1/fs
4
DM-4
D14
TCYC(2)
= 1/fs
tCNVH
tCNV
D15
TCYC(3) … TCYC(N-1)
tACQ tACQ tCNV
M-1 M
Legend
No signal transitions during compressed time
Signal transitions during compressed time
MCP33151D/41D-XX
DS20006219A-page 44 2019 Microchip Technology Inc.
6.1.1.2 3-Wire CS Mode with BUSY Output
Bit
This interface option is typically used when a single
MCP33151D/41D-XX is connected to an
SPI-compatible digital host that has an interrupt (IRQ)
input.
Figure 6-5 shows the connection diagram with the host
device. In this mode, CNV functions as both conversion
control and chip select (CS).
To enable this interface option, SDI can either be tied
to GND, or otherwise permanently held in a Logic = 0
state. By doing so, the device will output a BUSY bit
before each conversion data sample.
As shown in Figure 6-6, at the rising edge of CNV,
conversion is initiated. The SDO pin becomes high-Z
state (if no external pull-up is used). Once the
conversion is initiated, it continues and the ADC
completes the conversion regardless of the state of the
CNV pin. This means the CNV pin can be used for
other SPI devices after the conversion is initiated.
When conversion is complete, the device enters an
acquisition phase and Power-Down state, SDO comes
out of the high-Z state, and outputs a BUSY status indi-
cator bit (“Low” level). The device exits the acquisition
phase when CNV once again returns to a “High” state.
SDO then returns to a high-Z state after the 15th SCLK
falling edge or when CNV goes high, whichever occurs
first.
This configuration provides a high-to-low transition on
the IRQ pin of the digital host caused by the BUSY bit.
The data bits are clocked out, MSB first, on the subse-
quent SCLK falling edges. Data are valid on both edges
of SCLK and can be captured on either edge. However,
a digital host capturing data on the SCLK falling edge
can achieve a faster reading rate.
Figure 6-6 and Figure 6-7 show the timing diagrams for
both early and late CNV lowering scenarios.
FIGURE 6-5: Connection Diagram for
3-Wire CS Mode with BUSY Status Indicator
Output Bit. IRQ Pin in the Host Device Is Used
for Interrupt Event.
Note: It is recommended that CNV be driven low
before the minimum conversion time
(tCNV) expires, and remain “Low” until the
maximum possible conversion time
(tCONV) expires. A “Low” level on the CNV
input at the end of a conversion ensures
the device generates a BUSY status
indicator bit when the ADC has finished
converting.
Note: The pull-up resistor on the SDO pin is
required in this mode as it ensures that the
IRQ pin of the digital host is held high
when SDO goes to high-Z state.
CNVST
SDI
(Data In)
SC>K
CNV
SDISDO
SC>K
(a) MCP331xx (b) Digital Host (Master)
47 kΩ
V
IO
IRQ
2019 Microchip Technology Inc. DS20006219A-page 45
MCP33151D/41D-XX
FIGURE 6-6: Timing Diagram for 3-Wire CS Mode with BUSY Status indicator Output Bit, Early
CNV (Recommended).
FIGURE 6-7: Timing Diagram for 3-Wire CS Mode with BUSY Status Indicator Output Bit, Late
CNV.
SDI = 0
CNV (CS)
TCYC = 1/fs
tCNVH
SC>K
SDO
ADC
State
Converting Phase
(tCNV)
Input Acquisition
(tACQ)
D0D1D2
tSCLK
tDO tSCLK_L tSCLK_H
12345131415
“High” (with pull-up)
HiŐŚ-Z (with no pull-up)
tEN
tQUIET
tDIS
D13 D12 D11 D10BUSY
tSU_SDIL_CNV
SC>K
SDO
CNV (
CS
)
T
CYC
= 1/f
s
BUSY D0D1D2
“High” (with pull-up)
HiŐŚ-Z (with no pull-up)
tSCLK
t
DO
tSCLK_L tSCLK_H
12345131415
tCNVH
t
EN
t
QUIET
tDIS
ADC
State
Converting Phase
(tCNV)
Input Acquisition
(tACQ)
D13 D12 D11 D10
SDI = 0
tSU_SDIL_CNV
MCP33151D/41D-XX
DS20006219A-page 46 2019 Microchip Technology Inc.
FIGURE 6-8: Timing Diagram for Accumulator Operation in 3-Wire CS Mode with BUSY Status
Indicator Output Bit.
Note: Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature.
SDI = 1
SCLK
SDO
CNV (CS)
TCYC(1)
= 1/fs
DM-2 DM-3 D0
D1
D2
tSCLK
tDO tSCLK_H tSCLK_L
123 M-2
tCNVH
tEN
tQUI
tDIS
ADC
State
tCNV
tSU_SDIH_CNV
tACQ tACQ
tCNVH
TCYC(N) = 1/fs
4
DM-4
TCYC(2)
= 1/fs
tCNVH
tCNV
TCYC(3) … TCYC(N-1)
tACQ tACQ tCNV
M-1 M
Legend
No signal transitions during compressed time
Signal transitions during compressed time
BUSY
BUSY
BUSYBUSY
2019 Microchip Technology Inc. DS20006219A-page 47
MCP33151D/41D-XX
6.2 Recalibrate Command
The recalibrate command may be used in the following
cases:
• When the reference voltage was not fully settled
during the initial power-on sequence.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
A self-calibration is initiated by sending the recalibrate
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
Figure 6-9 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
FIGURE 6-9: Recalibrate Command Timing Diagram.
Note: When the device performs a calibration, it is important to note that the analog supply voltage (AVDD), the
reference voltage (VREF) and the digital I/O interface supply voltage (DVIO) must be stabilized for a correct
calibration. This is particularly relevant during the initial power-on sequence. Refer to Section 4.3
“Power-Up Sequence and Auto-Calibration” for more details.
SC>K
SDO
CNV (CS)
ADC Output Data Stream
HiŐŚ-Z (with no pull-up)
123
“High” (with pull-up)
ADC
State
tCNV
SDI = 1
13 14 1024
... ... 1023
Device Recalibration
tCAL
“Low”
Start recalibration Finish recalibration
Complete data reading
1024 clocks
(SPITM Recalibrate command)
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Note 1: SDI must remain “High” during the entire recalibration cycle.
2: The 1024 clocks include the clocks for data bits.
3: SDO outputs “Low” during calibration, and high-Z when exiting the calibration. This SDO activity is only present during manual reca-
libration and is not present during initial power-on auto-calibration. (See Section 4.3 “Power-Up Sequence and Auto-Calibration”
for more details)
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
MCP33151D/41D-XX
DS20006219A-page 48 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 49
MCP33151D/41D-XX
7.0 DEVELOPMENT SUPPORT
7.1 Device Evaluation Board
Microchip Technology Inc. offers a high speed/high
precision SAR ADC evaluation platform which can be
used to evaluate Microchip’s latest high speed/high
resolution SAR ADC products. The platform consists of
an MCP331x1D-XX evaluation board, a data capture
board (PIC32 MZ EF Curiosity Board), and a PC-based
Graphical User Interface (GUI) software.
Figure 7-1 and Figure 7-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC's performance for their specific
application requirements.
FIGURE 7-1: MCP331x1D-XX Evaluation Kit.
FIGURE 7-2: PC-Based Graphical User Interface Software.
Note: Contact Microchip Technology Inc. for the
PIC32 MCU firmware and the
MCP331x1D-XX Evaluation Kit.
(a) MCP331x1D-XX Evaluation Board
(b) PIC32MZ EF Curiosity Board
MCP33151D/41D-XX
DS20006219A-page 50 2019 Microchip Technology Inc.
7.2 PCB Layout Guidelines
Microchip provides the schematics and PCB layout of
the MCP331x1D-XX Evaluation Board (P/N:
ADM00873). It is strongly recommended that the user
references the example circuits and PCB layouts.
A good schematic with low noise PCB layout is critical
for high performing ADC application system designs. A
few guidelines are listed below:
• Use low noise supplies (AVDD, DVIO, and VREF).
• All supply voltage pins, including reference
voltage, need decoupling capacitors. Decoupling
capacitor requirements for each supply pin are
shown in Figure 4-1.
• Use NPO or COG type capacitor for the RC
anti-aliasing filters in the analog input network.
• Keep the analog circuit section (analog input
driver amplifiers, filters, voltage reference, ADC,
etc.) with an analog ground plane, and the digital
circuit section (MCU, digital I/O interface) with a
digital ground plane. Keep these sections as
much apart as possible. This will minimize any
digital switching noise coupling into the analog
section.
• Connect the analog and digital ground planes at a
single point (away from the sensitive analog
sections) with a 0resistor or with a ferrite bead.
See Figure 7-3 as an example of separated
ground planes.
• Keep the clock and digital output data lines short
and away from the sensitive analog sections as
much as possible.
•PCB Material and Layers: Low-loss FR-4
material is most commonly used.
The following four layers are recommended:
(a) Top Layer: Most of the noise-sensitive
analog components are populated on the top
layer. Use all unused surface area as ground
planes: analog ground plane in analog circuit
section and digital ground in digital circuit
section. These ground planes need to be tied to
the corresponding ground planes in the second
and bottom layers using multiple vias.
(b) 2nd Layer: Use this layer as the ground
plane: Analog ground plane under the analog
circuit section of the top layer and digital ground
plane under the digital circuit section on the top
layer. Each ground plane is tied to its
corresponding ground plane of top and bottom
layers using multiple vias.
(c) 3rd Layer: This layer is used to distribute
various power supplies of the circuits. Use
separate trace paths for the power supplies of
analog and digital sections. Do not use the same
power supply source for both analog and digital
circuits.
(d) Bottom Layer: This layer is mostly used as
a solid ground plane: Analog ground plane
under the analog circuit section of the top layer
and digital ground plane under the digital circuit
section on the top layer. Each ground plane is
tied to its corresponding ground plane of all
layers using multiple vias.
Figure 7-3 and Figure 7-4 show brief examples of the
PCB layout. See more details of the schematics and
PCB layout in the MCP331x1D-XX Evaluation Board
User’s Guide.
FIGURE 7-3: PCB Layout Example: Analog and Digital Ground Planes.
Digital Ground Plane
Analog Ground Plane
Digital Interface
(DGND)
Connectors for MCU
(GND)
Note: Analog and digital
ground planes are
connected via R56.
MCP331x1D-XX
SDO
SCLK
R56
Analog Ground Plane
(GND)
Digital Ground Plane
(DGND)
2019 Microchip Technology Inc. DS20006219A-page 51
MCP33151D/41D-XX
FIGURE 7-4: PCB Layout Example: See More Details in the MCP331x1D-XX EV Kit User’s Guide.
MCP331x1D-XX
AIN+
AIN-
VREF
AVDD
GND
CNVST
SDO
SCLK
SDI
VIO
C9 C59
C7 C6
C10
(a) PCB layout example
(b) Schematic example from the MCP331x1D-XX Evaluation Board
MCP33151D/41D-XX
DS20006219A-page 52 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 53
MCP33151D/41D-XX
8.0 TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes indicates that all 16384 codes for
14-bit (4096 codes for 12-bit) must be present over all
the operating conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), below the Nyquist
frequency and excluding the power at DC and the first
nine harmonics.
EQUATION 8-1:
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
EQUATION 8-2:
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 8-3:
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
Offset Error
The major carry transition should occur for an analog
value of ½ LSB below AIN+=A
IN−. Offset error is
defined as the deviation of the actual transition from
that point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in µV/oC or ppm/oC.
Maximum Conversion Rate
The maximum clock rate at which parametric testing is
performed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
SNR 10
PS
PN
-------



log=
SINAD 10
PS
PDPN
+
----------------------



log=
10–=10
SNR
10
-----------–
10
THD
10
------------–
–log
ENOB SINAD 1.76–
6.02
----------------------------------=
MCP33151D/41D-XX
DS20006219A-page 54 2019 Microchip Technology Inc.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 8-4:
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 8-5:
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with Equation 8-6:
EQUATION 8-6:
THD 10
PS
PD
--------



log=
THD 20
V2
2V3
2V4
2
Vn
2
++++
V1
2
------------------------------------------------------------------log–=
Where:
V1= RMS amplitude of the
fundamental frequency
V1 through Vn= Amplitudes of the second
through nth harmonics
CMRR 20
ADIFF
ACM
------------------



log=
Where:
ADIFF =Output Code/Differential Voltage
ADIFF =Output Code/Common-Mode Voltage
2019 Microchip Technology Inc. DS20006219A-page 55
MCP33151D/41D-XX
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
10-Lead MSOP (3 × 3 mm) Example
10-Lead TDFN (3 × 3 × 0.8 mm) Example
XXXX
YYWW
NNN
PIN 1
51D-10
922256
XXXX
YYWW
NNN
PIN 1
51D1
1922
256
Part Number Code
MCP33151D-10-E/MS 51D-10
MCP33151D-05-E/MS 51D-05
MCP33141D-10-E/MS 41D-10
MCP33141D-05-E/MS 41D-05
Note: Applies to 10-Lead MSOP.
Part Number Code
MCP33151D-10-E/MN 51D1
MCP33151D-05-E/MN 51D0
MCP33141D-10-E/MN 41D1
MCP33141D-05-E/MN 41D0
Note: Applies to 10-Lead TDFN.
MCP33151D/41D-XX
DS20006219A-page 56 2019 Microchip Technology Inc.
0.13 C A B
12
N
TOP VIEW
SIDE VIEW END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
http://www.microchip.com/packaging
For the most current package drawings, please see the Microchip Packaging Specification located atNote:
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
D
EE1
D
2
E1
2
E
2
0.20 H
0.25 C
0.20 H
A
B
e
8X b
AA2
A1 0.10 C
8X
C
SEATING
PLANE
H
SEE DETAIL A
2019 Microchip Technology Inc. DS20006219A-page 57
MCP33151D/41D-XX
Microchip Technology Drawing C04-021D Sheet 2 of 2
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
3.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
Notes:
2.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M.
protrusions shall not exceed 0.15mm per side.
L1Footprint
Mold Draft Angle
Lead Width
Lead Thickness c
b
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
e
N
Units
0.95 REF
-
-
0.08
0.15
0.23
0.33
MILLIMETERS
0.50 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
0.40
0.00
0.75
MIN NOM
1.10
0.80
0.15
0.95
MAX
10
-
--
8°0°
-
C
SEATING
PLANE
L
(L1)
c
Ĭ
Ĭ
DETAIL A
Foot Angle - 15°5°
Ĭ1
4X Ĭ1
4X Ĭ1
MCP33151D/41D-XX
DS20006219A-page 58 2019 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2021B
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Overall Width
Contact Pitch
Z
MILLIMETERS
0.50 BSC
MIN
E
MAX
4.40
5.80
Contact Pad Length (X10)
Contact Pad Width (X10)
Y1
X1
1.40
0.30
GDistance Between Pads (X8) 0.20
NOM
Distance Between Pads (X5) G1 3.00
E
C
ZG1
X1
G
Y1
SILK SCREEN
2019 Microchip Technology Inc. DS20006219A-page 59
MCP33151D/41D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP33151D/41D-XX
DS20006219A-page 60 2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc. DS20006219A-page 59
MCP33151D/41D-XX
APPENDIX A: REVISION HISTORY
Revision A (June 2019)
• Initial release of this document
2019 Microchip Technology Inc. DS20006219A-page 60
MCP33151D/41D-XX
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 61
MCP33151D/41D-XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. /XX
PackageTemperature
Range
Device
Device: MCP33151D-10 = 1 Msps, 14-Bit Differential Input SAR ADC
MCP33141D-10 = 1 Msps, 12-Bit Differential Input SAR ADC
MCP33151D-05 = 500 kSPS, 14-Bit Differential Input SAR ADC
MCP33141D-05 = 500 kSPS, 12-Bit Differential Input SAR ADC
Input Type: D = Differential Input
Sample Rate: 10 = 1 Msps
05 = 500 kSPS
Tap e and Reel
Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel (Note 1)
Temperature
Range:
E= -40C to +125C (Extended)
Package: MS = Plastic Micro Small Outline Package (MSOP),
10-Lead
MN = Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead (Note 2)
Examples:
a) MCP33151D-10-E/MS: 14-bit, 1 Msps,
10-LD MSOP package
b) MCP33151D-10T-E/MS: 14-bit, 1 Msps,
Tape and Reel,
10-LD MSOP package
c) MCP33151D-10-E/MN: 14-bit, 1 Msps,
10-LD TDFN package
d) MCP33151D-10T-E/MN: 14-bit, 1 Msps,
Tape and Reel,
10-LD TDFN package
e) MCP33141D-10-E/MS: 12-bit, 1 Msps,
10-LD MSOP package
f) MCP33141D-10T-E/MS: 12-bit, 1 Msps,
Tape and Reel,
10-LD MSOP package
g) MCP33141D-10-E/MN: 12-bit, 1 Msps,
10-LD TDFN package
h) MCP33141D-10T-E/MN: 12-bit, 1 Msps,
Tape and Reel,
10-LD TDFN package
i) MCP33151D-05-E/MS: 14-bit, 500 kSPS,
10-LD MSOP package
j) MCP33151D-05T-E/MS: 14-bit, 500 kSPS,
Tape and Reel,
10-LD MSOP package
k) MCP33151D-05T-E/MN: 14-bit, 500 kSPS,
Tape and Reel,
10-LD TDFN package
l) MCP33141D-05-E/MS: 12-bit, 500 kSPS,
10-LD MSOP package
m) MCP33141D-05T-E/MN: 12-bit, 500 kSPS,
Tape and Reel,
10-LD TDFN package
[X](1)
Tape and Reel
Option
X
XX
Sample Rate Input Type
X
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
2: Contact Microchip Technology Inc. for
availability.
MCP33151D/41D-XX
DS20006219A-page 62 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006219A-page 63
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-522-4701-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
DS20006219A-page 64 2019 Microchip Technology Inc.
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