DM74LS109AMX - Fairchild Semiconductor

June 1986

Revised March 2000

DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74LS109A

Dual Positive-Edge-Triggered J-K Flip-Flop with

Preset, Clear, and Complementary Outputs

General Descript ion

This device contains two independent positive-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is accepte d by the fli p-flop on the risin g edge o f the

clock pulse. T he triggering occurs at a voltage l evel and is

not dire ctly related to the tr ansition time o f the rising ed ge

of the clock. The data on the J and K inputs may be

changed w hile th e cloc k is HIG H or LOW as lon g as set up

and hold times are not violated. A low logic level on the

preset or clear inputs will set or reset the outputs regard-

less of the logic levels of the other inputs.

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering c ode.

Connection Diagram Function Table

H = HIGH Lo gic Level

L = LOW Lo gic Level

X = Either LOW or HIGH Logic Level

↑ = Rising Edge of P uls e

Q0 = The out put logic lev el of Q be fore the in dica ted input con ditio ns were

established.

Toggle = Each output changes to the complement of its previous level on

each active transition of the clock pulse.

Note 1: This co nfigu ratio n is nons tab le; tha t is , it wi ll not pers ist w hen p re-

set and/or clear inputs return to their inactive (HIGH) state.

Order Number Package Number Package Description

DM74LS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK J K QQ

LHXXX H L

HLXXX L H

L L X X X H (Not e 1) H (No te 1 )

HH ↑LL L H

HH ↑H L Toggle

HH ↑LH Q

0Q0

HH ↑HH H L

HH LXX Q

0Q0

www.fairchildsemi.com 2

DM74LS109A

Absolute Maximum Ratings(No te 2) Note 2: The “A bsolute Maxim um Ratin gs” are those valu es beyon d which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum ratin gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 5: The symbol (↑) indicate s th e ris ing edge of the clock pulse is used for reference.

Note 6: TA = 25°C an d VCC = 5V.

Supply Voltage 7V

Input Voltag e 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 3) 0 25 MHz

fCLK Clock Frequency (Note 4) 0 20 MHz

tWPulse Width Clock HIGH 18

(Note 3) Preset LOW 15 ns

Clear LOW 15

tWPulse Width Clock HIGH 25

(Note 4) Preset LOW 20 ns

Clear LOW 20

tSU Setup Time Data HIGH 30↑ns

(Note 3)(Note 5) Data LOW 20↑

tSU Setup Time Data HIGH 35↑ns

(Note 5)(Note 4) Data LOW 25↑

tHHold Time (Note 6) 0↑ns

TAFree Air Operating Temperature 0 70 °C

3 www.fairchildsemi.com

DM74LS109A

Electri cal Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 7: All typicals are at VCC = 5V, TA = 25°C.

Note 8: N ot more tha n one output should be shorted at a time, and the durat ion shou ld not ex ce ed one secon d. For dev ic es , with fe edback from the outputs,

where shortin g th e outp uts to ground may ca use the outputs to ch ange l o gic state an equivale nt te st may be perfor med wh ere V O = 2.125V with th e mi nimum

and maxim um limit s reduced by one half fro m t heir stated v alues. This is v ery us eful when using automatic test equipm ent.

Note 9: ICC is meas ured with all output s OPEN, w ith C LOCK grounded a fter setti ng t he Q and Q outputs HIGH in turn.

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol Parameter Conditions Min Typ Max Units

(Note 7)

VIInput Clamp Voltage VCC = Min, I I = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, I OL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max VCC = Max J, K 0.1

Input V oltag e VI = 7V Clock 0.1 mA

Preset 0.2

Clear 0.2

IIH HIGH Level VCC = Max J,K 20

Input Current VI = 2.7V Clock 20 µA

Preset 40

Clear 40

IIL LOW Level VCC = Max J, K −0.4

Input Current VI = 0.4V Clock −0.4 mA

Preset −0.8

Clear −0.8

IOS Short Circuit Output Current VCC = Max (Note 8) −20 −100 mA

ICC Supply Current VCC = Max (Note 9) 4 8 mA

From (Input) RL = 2 kΩ

Symbol Parameter To (Out put) CL = 15 pF CL = 50 pF Units

MinMaxMinMax

fMAX Maximum Clock Frequency 25 20 MHz

tPLH Propagation Delay T ime Cl ock to 25 35 ns

LOW-to-HIGH Level Output Q or Q

tPHL Propagation Delay Time Clock to 30 35 ns

HIGH-to-LOW Level Output Q or Q

tPLH Propagation Delay T ime Clear 25 35 ns

LOW-to-HIGH Level Output to Q

tPHL Propagation Delay T ime Clear 30 35 ns

HIGH-to-LOW Level Output to Q

tPLH Propagation Delay T ime Preset 25 35 ns

LOW-to-HIGH Level Output to Q

tPHL Propagation Delay Time Preset 30 35 ns

HIGH-to-LOW Level Output to Q

www.fairchildsemi.com 4

DM74LS109A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

5 www.fairchildsemi.com

DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described , no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.