AV2572N-SA - Integrated Circuit Systems, Inc.

ICS2572RevC090894

Integrated

Circuit

Systems, Inc.

ICS2572

User-Programmable Dual High-Performance Clock Generator

Block Diagram

XTAL1

XTAL2

Crystal

Oscillator Reference

Divider

Charge

Pump

Phase-

Frequency

Comparator

EXTFREQ

VCO

Prescaler

Strobe

FS0

FS1

FS2

FS3

MS0

MS1

MCLK PLL (as above)

VCLK Set &

Program

Mode

Interface

MCLK Set

/4 MCLK

CLK-

CLK+

LOAD

/1, 4, 5 or 8

Description

The ICS2572 is a dual-PLL (phase-lock ed loop) clock gener-

ator with differential video outputs specifically designed for

high-resolution, high-refresh rate, video applications. The

video PLL generates any of 16 pre-programmed frequencies

through selection of the address lines FS0-FS3. Similarly, the

auxiliary PLL can generate any one of four pre-programmed

fre q uenci es vi a the M S 0 & M S 1 lines.

A unique feature of the ICS2572 is the ability to redefine

frequency selections after power-up. This permits complete

set -up of the fre quency ta ble upon syste m i nit ia l iz a ti on.

Features

•• Advanc e d ICS mono lithi c phase-l oc ked lo op

technology

•• Support s high-resol ution graphics - di ffere ntial CL K out-

pu t to 185 MH z

•• Di v ided do tc lo ck outp ut ( L O A D) a vaila ble

•• Sim plifie d de vice pro grammi ng

•• S ixte e n selectable VC L K f reque n c ies (all user

re-programmable)

•• Four selectable MCLK frequencies (all user

re-programmable)

•• Windows NT compatible

Applications

•• Hig h end PC/l ow end work sta ti on graph ic s desi gns

re qu iring different ia l outp ut

•• X Te rm i na l graph ic s

E-95

Pin Configuration

XTAL1 1 20 VDD

XTAL2 2 19 CLK+

XTFREQ 3 18 CLK-

FS0 4 17 VSS

FS1 5 16 LOAD

STROBE 6 15 VAA

FS2 7 14 VSS

FS3 8 13 VDD

MS0 9 12 MCLK

VSS 10 11 MS1

ICS2572

Pin Descriptions

PIN NUMBER PIN NAME TYPE DESCRI PTION

1 XTAL1 A Quar tz crystal connection 1/Refe rence Frequenc y Input.

2 XTAL2 A Qu artz crystal connection 2.

3 EXT FREQ I Ext e rna l Fre qu en cy Input

4 FS0 I VC LK PLL Freque nc y Sele ct LSB.

5 FS1 I VC LK PLL Freque nc y Sele ct Bit.

7 FS2 I VC LK PLL Freque nc y Sele ct Bit.

8 FS3 I VC LK PLL Freque nc y Sele ct MSB.

6 STROBE I Cont rol f or Latc h of VCLK Se lect Bits (FS0 -FS3).

9 MS0 I MC LK PLL Freque nc y Sele ct LSB.

11 MS1 I MC LK PLL Freque nc y Sele ct MSB.

19 CLK+ O Pixel Clock Output (not inverted)

18 CLK- O Pixel Clock Output (inverted)

1 6 LOA D O Di vi de d Dotc l oc k (/4 , 5, or 8)

12 MCLK O MCLK Frequency Output

17 RESERVED - Mu st Be Connect ed to VSS.

10, 14 VSS P De vi c e Ground . All pin s must be con ne cte d.

1 3, 20 VD D P Ou tpu t Stag e Vdd. All p ins must be c onn ect ed .

1 5 VAA P Sy nthesi zer Vdd.

20-Pin DIP or SOIC

J-4, J-7

ICS2572

E-96

Digital Inputs

The FS0-FS3 pins a nd the STROBE pin are used to select the

desired operating frequency of the VCLK output from the 16

pre-p rogrammed/user-programmed selection s in the ICS2572.

Thes e pins are also used to load new frequency data into the

registers.

Availa ble conf igu rations for the ST ROBE in put inc lude : posi-

tive-edge tri ggered, negative -edge tri ggered, high -level tra n s-

parent , a nd low-l evel tra nsparent (see Ordering Inform ation).

VCLK Output Frequency Selection

To change the VCLK output frequency, simply write the ap-

propriate dat a to the ICS2572 FS inputs. Do not perform any

further writes to the device for 50 milliseconds (assumes a

14.318 MHz reference). The synthesizer will output the new

frequency programmed into that location after a brief delay

(se e time out spec ific a tions).

MCLK Output Frequency Selection

The MS0-MS1 pins are used to directly select the desired

operating frequency of the MCLK output from the four pre-

programmed/user-programmed selections in the ICS2572.

The se inputs ar e not latc hed, nor ar e they invol ved wit h me m-

ory programming operations.

Programming Mode Selection

A pr og ra mmi ng s eq ue n ce is defin ed as a p erio d of at leas t 5 0

milliseconds o f no data w rites to the ICS2572 (to clear the shift

FS0 FS1 FS2 FS3

XXSTART bit (must be “0”) 0

XX ” 1

XXR/W* control 0

XX ” 1

XXL0 (l ocati on LSB) 0

XX ” 1

XXL1 0

XX ” 1

XXL2 0

XX ” 1

XXL3 0

XX ” 1

XXL4 (loc ation MSB) 0

XX ” 1

XXN0 (feedback LSB ) 0

XX ” 1

XXN1 0

XX ” 1

XXN2 0

XX ” 1

XXN3 0

XX ” 1

XXN4 0

XX ” 1

XXN5 0

XX ” 1

XXN6 0

XX ” 1

XXN7 (feedbac k MSB) 0

XX ” 1

XXEXTFREQ bit (selected if “1”) 0

XX ” 1

XXD0 (post-divi de r LSB) 0

XX ” 1

XXD1 (post-di vi de r MSB) 0

XX ” 1

XXSTOP1 bi t (must be “1” 0

XX ” 1

XXSTOP2 bit (m ust b e “1 ”) 0

XX ” 1

ICS2572

E-97

Observe that the internal shift register is “clocked ” by a tran-

sit ion of FS3 data from “0” t o “1.” If a n extended sequ ence of

zation sequence), note that it is not necessary to implement the

50 millisecond delay between them. Simply repeat the se-

quence above as many times as des ired. Writes to the FS port

will not be treated as frequency select data until up to 50

mil lisecond s have tran sp ired sinc e the last writ e. No te t hat FS0

and FS 1 inputs a re “don ’t c are. ”

Data Description

Location Bits (L0-L4)

The first five bits after the start bit control the frequency

location to be re-programmed according to this table. The

rightmost bi t (the LSB) of the f ive sh own in each sel e ctio n of

th e tab le is the first one sen t.

Table 1 - Loca tion Bi t Programming

L[4-0] LOCATION

01 100 VCLK Addr ess 12

01 101 VCLK Addr ess 13

01 1 10 VCLK Addr ess 14

01111 VCLK Address 15

10010 MCLK Addr ess 2

1001 1 MCL K Address 3

Feedb ack Set Bits (N0-N7)

These bits control the feedback divider setting for the location

spec ified. The modulus of the feedback divider will be equa l

t o t he value of t hese bits + 257. The least si gnificant bit ( N0)

is sen t first.

Post-Divider Set Bits (D0-D1)

These bits control the post-divider setting for the location

speci fied acc o rding to this table . The least si gnific ant bit (D0 )

is sen t first.

Table 2 - Post-Divider Programming

D[1-0] POST-DIVIDER

00 9

01 4

10 2

11 1

Read/Write* Control Bit

When set to a “0,” the ICS2572 shift register will transfer its

contents to the s elected memory register at the completion of

th e programming seque nce outli ne d ab ove.

Wh en t h is bi t is a “1 ,” the s elect ed mem ory l ocat io n w il l be

transferred to the shift registe r to permit a subsequent readback

of da ta. No m od ific atio n of de vi ce m em ory wil l be p er form ed.

To readback any location of memory, perform a “dummy”

wri te o f d ata (co mp lete wit h sta rt and st op bi ts) to tha t l oc atio n

but s et t he R/ W* co ntrol bit (make i t “1”) . At t he end of th e

sequence (i.e., after the stop bits have been “clocked”), “clock-

ing” of the FS3 input 11 more t imes will output the data bits

onl y in the same se quence as above on the FS0 pin.

EXTFREQ Input

The EXTFREQ input allows an externally generated frequency

to be routed to the VCLK output pin under device program-

ming control. If the EXTFREQ bit is set (logic “1”) at the

selected address location (VCLK addresses only), the fre-

quency appli ed to the EXTFREQ input will be routed to the

VCL K output.

ICS2572

E-98

Frequency Synthesizer Description

Refe r to Figure 1 for a bl ock diag ra m of t he ICS25 72.

The ICS2572 generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedba ck system that drives the output frequency

to be ratiometrically related to the reference frequency pro-

vided to the PLL. The phase-frequency detector shown in the

block diagram drives the VCO to a frequency that will cause

the two inputs to the phase-frequency detector to be matched

in f re quency a nd pha s e . This occu r s wh e n:

FVCO=FXTAL1*2

where N is the effective modul us of the feedback divider chain

and R is th e modulus of the r ef er en ce di vid er cha i n.

The feed back di vider on the ICS2572 m ay be set to any intege r

value from 257 to 512. This i s done by t he setting of t he N0- N7

bits. The st anda rd refe renc e di vider on the IC S2572 is fixe d to

a value of 43 (this may be set to a different value via ROM

program ming; co ntact f act ory). The ICS2572 is equippe d with

a post-divider and multiplexer that allows the output frequency

range t o be sca led down f rom that of the VCO b y a fac tor of 2,

4, or 8.

Therefore, the VCO frequency range will be from 5.976 to

11.906 (257/43 to 512/43) of the reference frequency. The

output frequency range will be from 0.747 to 11.906 times the

reference frequency. Worst case accuracy for any desired fre-

que ncy within that range will be 0.2%.

If a 14.31818 MHz reference is used, the output frequency

range woul d be from 10. 69 7 MHz to 170. 48 6 MHz.

Programming Example

Suppose that we want differential CLK output to be

45.723 MHz. We will assume the reference frequency to be

14. 31 818 MHz.

The VCO frequency range will be 85.565 MHz to

170.486 MHz (5 .976 * 14.31818 to 11.906 * 14.31818). We

will need to set the post-divider to two to get an output of

45. 72 3 MHz.

The VCO will then need to be programmed to two times

45.723 MHz, or 91.446 MHz. To calculate the required feed-

back divider modulus we divide the VCO frequency by the

re fe rence fre quency a nd m ultiply by the re fe rence di vider:

91.446 *43=274.62

14.31818

which we round off to 275. The exact output frequency will

be:

275 1

*14.31818* =45.784 MHz

43 2

The value of the N programming bits may be calculated by

subtracting 257 from the desired feedback divider modulus.

Thus, the N value will be set to 18 (275-257) or 000100102.

The D bit programming is 102 ( from Table 2).

LOAD Frequency Selection

The LO AD ( or di vided d otclock) ou tput frequency will be the

CLK+/CLK- frequency divided by 1, 4, 5, or 8. The choice of

modulus is a factory option, and is specified along with the

ROM frequen cies in the VCLK and MCLK tables by way of

the two-di gi t suffix of the part num be r.

Reference Oscillator & Crystal

Selection

The ICS2572 has on-board circuitry to implement a Pierce

oscillator with the addition of only one external component, a

qua rtz crysta l. Pi erce oscil lators ope rat e the cry stal i n p aralle l-

resona nt (also ca ll ed ant i-r eson an t mode . See the AC Cha ra c-

teristics for the effective capacitive loading to specify when

or derin g cr ystal s.

Cry sta ls charac teriz ed for the ir serie s-resona nt fre quency m ay

also be used with the ICS2572. Be aware that the os cillation

fre qu ency in c irc uit wil l be slig htly higher than the freq uency

that is sta mp ed on the can ( typ ica lly 0. 025- 0.05% ).

As th e e nt ire op erat io n o f t he ph ase -lo cked l oop d epen ds on

having a stable referenc e frequency, we recommend that the

crysta l be mount ed as closel y as p ossible to the packa ge. Avoid

routing digital signals or the ICS2572 outputs underneath or

near these traces. It is also desirable to ground the crystal can

to the ground pl an e, if po s sible.

ICS2572

E-99

External Reference Sources

An external frequency source may be used as the reference for

the VCLK and MCLK PLLs. To implemen t this, simply con-

nect the reference frequency source to the XTAL1 pin of the

ICS2572. For best results, insure that the clock edges are as

cle an and fast as possi ble a nd that the in put volt age threshol ds

are not violat e d.

Power Supply

The ICS2572 has two VSS pins to reduce the effects of package

inductance. Both pins are connected to the same potential on

the die (the ground bus). BOTH of these pins should connect

to the ground plan e of the video board as close to the pa cka ge

as is possible.

The ICS2572 has a VDD pi n which is the supply of +5 volt

powe r to a ll out put sta ge s. This pin sh ould be c onnecte d to the

power plane (or bus) using standard high-frequency decou-

pling practice. That is, use low-capacitors should have low

serie s indu cta nc e and be mounted cl ose to th e ICS2572 .

The VAA pin is the powe r supply fo r the synthe siz er circ uitr y

and oth er lowe r c ur re nt digi ta l func ti ons. We recom m e nd th at

RC dec ouplin g or zene r regul ation be provided fo r this pin (as

shown in the recommended application circuitry). This will

allow the PLL to “track” through power supply fluctuations

wit hout vi si bl e effec ts.

ICS2572

E-100

Absolute Maximum Ratings

Supply vo ltag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.5V to +7V

Logi c i nput s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- .5 V to VDD +.5V

Ambient op erating temp. . . . . . . . . . . . . . . . . . . . . . . 0 to 7 0°C

Sto ra ge temperat ure . . . . . . . . . . . . . . . . . . . . . . . . . . -85 to + 150°C

Str esses abov e those list ed unde r Absol ute Ma ximum Rat ing s may c ause per mane nt da mag e to t he devi ce. This is a stre ss r ating

onl y a nd funct io na l o pe ra ti on of t he de vi ce at the se or a ny oth er c ond it ion s above those indic a te d in the opera t ion al sec ti ons of

the specifications is not implied. Exposure to abs olute maximum rating conditions for extende d periods may affect product

reliability.

DC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MA X UNITS

TTL-Comp atible Inputs - - -

(FS0-3, MS0-1, STROB E): - - -

Input Hi gh Voltage Vih 2.0 - VDD+0.5 V

Input Low Vol tage Vil VSS-0.5 - 0.8 V

Input Hig h Curren t Iih --10uA

Input Low Curr en t Iil - - 200 uA

Input Capa c itan ce Cin --8pF

XTAL1: - - -

Input High Voltage Vx h VDD*0. 75 - VDD+0. 5 V

Input Low Voltage Vxl VSS-0.5 - VDD*0. 25 V

CL K+/ CL K- Out put

Sink Current Isink - - - mA

High Voltage ( Other

Outputs) Voh 4 - - V

@Ioh=0.4mA - - -

Low Voltag e (Oth er

Outputs) Vol - - 0.4 V

@Iol=8.0mA - - -

ICS2572

E-101

AC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Phase-L oc ked Loo p : - - -

VCLK, MCLK VCO

Frequency Fvco 100 - 235 MHz

PLL Acqui re T i me Tloc k - 500 - u Sec

Crystal Oscillat or - - -

Crystal Frequency

Range Fxtal 5 - 25 MHz

Pa rall el Loadin g

Capacitance -20-pF

XTAL1 Min imum High

Time Txhi 8 - - ns

XTAL1 Minimum Low

Time Txlo 8 - - ns

Power Suppl ies: - - - -

VDD Supply Current idd - - 35 mA

VAA Supply Curre nt Iaa - - 10 mA

Digital Outputs: - - -

CL K+/ CL K - Re c om-

men ded Terminat ion 50 - 2 ohms

Othe r Outputs Rise

T im e @ Cl oa d= 2 0p F Tf - - 2 ns

Othe r Ou tpu ts Fa ll Tim e

@ Cload=20 p F Tf - - - ns

ICS2572

E-102

PATTERN ICS2572-01

Re ferenc e Divider 43

VCLK ADDR FbkDiv/PostDi v - F VCLK(MHz)

0 300/1 - 99.89

1 3 78/ 1 - 125.87

2 277/1 - 92.2 4

3 432/4 - 35.9 6

4 302/2 - 50.2 8

5 340/2 - 56.6 1

6 EXTFREQ-

7 270/2 - 44.9 5

8 4 05/ 1 - 134.86

9 384/4 - 31.9 7

A 3 30/ 1 - 109.88

B 481/2 - 80.08

C 479/4 - 39.87

D 270 /2 - 44.95

E 450/2 - 74.9 2

F 390/2 - 64.9 3

MCLK ADDR FbkDiv/PostDiv - FMCLK

0 481/4 - 40.0 4

1 270/2 - 44.9 5

2 396/4 - 32.9 7

3 300/2 - 49.9 5

Ordering Information

ICS2572N-SXX or ICS2572M-SXX (0.300" DIP o r SOIC Packag e)

Example:

ICS XXXX N-SXX

S=Strobe Option/XX=Default Frequenc ies

Package Type

N=DIP ( Plastic)

M=SOIC

Devic e Type (cons i sts of 3 or 4 digi t numbe rs )

Prefix

ICS, AV=Standard Device; GSP=Genlock Device

Where:

“s” denotes str obe option: A - positi ve le vel tr ansparen t (i.e., 2 494 inte rface co mpatible)

“xx” de not es default fre qu encie s: B - ne ga ti ve le ve l tr an sp ar ent

C - positiv e edge triggered

D - negative edge triggered

ICS2572

E-103

NOTES

ICS2572

E-104