TPS75003-EP
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Triple-Supply Power Management IC for Powering FPGAs and DSPs
Check for Samples: TPS75003-EP
1FEATURES APPLICATIONS
•FPGA/DSP/ASIC Supplies
2•Two 95% Efficient, 3-A Buck Controllers and •Set-Top Boxes
One 300-mA LDO
•DSL Modems
•Tested and Endorsed by Xilinx for Powering •Plasma TV Display Panels
the Spartan™-3, Spartan-3E, and Spartan-3L
FPGAs DESCRIPTION
•Adjustable (1.2 V to 6.5 V for Bucks, 1 V to 6.5 The TPS75003 is a complete power management
V for LDO) Output Voltages on All Channels solution for FPGA, DSP and other multi-supply
•Input Voltage Range: 2.2 V to 6.5 V applications. The device has been tested with and
•Independent Soft-Start for Each Supply meets all of the Xilinx Spartan-3, Spartan-3E, and
Spartan-3L start-up profile requirements, including
•Independent Enable for Each Supply for monotonic voltage ramp and minimum voltage rail
Flexible Sequencing rise time. Independent Enables for each output allow
•LDO Stable with 2.2-μF Ceramic Output sequencing to minimize demand on the power supply
Capicitor at start-up. Soft-start on each supply limits inrush
•Small, Low-Profile 4,5 mm x 3,5 mm x 0,9 mm current during start-up. Two integrated buck
QFN Package controllers allow efficient, cost-effective voltage
conversion for both low and high current supplies
such as core and I/O. A 300-mA LDO is integrated to
SUPPORTS DEFENSE, AEROSPACE, provide an auxiliary rail such as VCCAUX on the Xilinx
AND MEDICAL APPLICATIONS Spartan-3 FPGA. All three supply voltages are
•Controlled Baseline offered in user-programmable options for maximum
•One Assembly/Test Site flexibility.
•One Fabrication Site The TPS75003 is fully specified from –55°C to
•Available in Military (–55°C/125°C) +125°C and is offered in a QFN package, yielding a
highly compact total solution size with high power
Temperature Range(1) dissipation capability.
•Extended Product Life Cycle
•Extended Product-Change Notification
•Product Traceability
(1) Additional temperature ranges available - contact factory
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Spartan is a trademark of Xilinx, Inc.
PRODUCTION DATA information is current as of publication date. Copyright ©2006–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS75003-EP
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PRODUCT VOUT
Buck1: Adjustable
TPS75003MRHLREP Buck2: Adjustable
LDO: Adjustable
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document or
see the Texas Instruments website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS75003 UNIT
VINX range (IN1, IN2, IN3) -0.3 to +7 V
VENX range (EN1, EN2, EN3) -0.3 to VINX + 0.3 V
VSWX range (SW1, SW2, SW3) -0.3 to VINX + 0.3 V
VISX range (IS1, IS2, IS3) -0.3 to VINX + 0.3 V
VOUT3 range -0.3 to +7 V
VSSX range (SS1, SS2, SS3) -0.3 to VINX + 0.3 V
VFBX range (FB1, FB2, FB3) -0.3 to +3.3 V
Peak LDO output current (IOUT3) Internally limited —
Continuous total power dissipation See the Thermal Information Table —
Junction temperature range, TJ-55 to +150 °C
Storage temperature range -65 to +150 °C
ESD rating, HBM 1 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
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Figure 1. Wirebond Plot
THERMAL INFORMATION TPS75003-EP
THERMAL METRIC(1) UNITS
RHL (20 PINS)
θJA Junction-to-ambient thermal resistance 42.6
θJCtop Junction-to-case (top) thermal resistance 51.8
θJB Junction-to-board thermal resistance 39.5 °C/W
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 14.2
θJCbot Junction-to-case (bottom) thermal resistance 2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF,
TA= -55°C to 125°C, unless otherwise noted. Typical values are at TA= 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Supply and Logic
Input voltage range (IN1, IN2,
VINX 2.2 6.5 V
IN3)(1)
Quiescent current, IQ= IDGND +
IQIOUT1 = IOUT2 = IOUT3= 0 mA 75 150 μA
IAGND
ISHDN Shutdown supply current VEN1 = VEN2 = VEN3 = 0 V 0.05 3 μA
TA= 25°C 1.4
Enable high, enabled
VIH1, 2 V
(EN1, EN2) TA= Full Range 1.45
TA= 25°C 1.14
VIH3 Enable High, enabled (EN3) V
TA= Full Range 1.2
Enable low, shutdown
VILX 0 0.3 V
(EN1, EN2, EN3)
Enable pin current (EN1, EN2,
IENX 0.01 0.5 μA
EN3)
Buck Controllers 1 and 2
VOUT1,2 Adjustable output voltage Range(2) VFBX VINX V
VFB1,2 Feedback voltage (FB1, FB2) 1.22 V
Feedback voltage accuracy(1) ±2%
(FB1, FB2)
IFB1,2 Current into FB1, FB2 pins 0.01 0.5 μA
TA= 25°C 80 120
Reference voltage for current
VIS1,2 100 mV
sense TA= Full Range 75 125
IIS1,2 Current into IS1, IS2 pins 0.01 0.5 μA
Measured with the circuit in Figure 2,
ΔVOUT%/ΔVIN Line regulation(1) 0.1 % / V
VOUT + 0.5 V ≤VIN ≤6.5 V
Measured with the circuit in Figure 2,
ΔVOUT%/ΔIOUT Load regulation 0.6 % / A
30 mA ≤IOUT ≤2 A
Measured with the circuit in Figure 2,
n1,2 Efficiency(3) 94%
IOUT = 1 A
Measured with the circuit in Figure 2,
tSTR1,2 Startup time(3) RL= 6 Ω, COUT = 100 μF, CSS = 2.2 5 ms
nF
VIN1,2 >2.5 V 4
Gate driver P-Channel and
RDS,ON1,2 Ω
N-Channel MOSFET on-resistance VIN1,2 = 2.2 V 6
Gate Driver P-Channel and
ISW1,2 100 mA
N-Channel MOSFET drive current
tON Minimum on time 1.36 1.55 1.84 μs
tOFF Minimum off time 0.44 0.65 0.86 μs
(1) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater.
(2) Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested.
(3) Depends on external components.
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ELECTRICAL CHARACTERISTICS (continued)
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF,
TA= -55°C to 125°C, unless otherwise noted. Typical values are at TA= 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNIT
LDO
VOUT3 Output voltage range (4) 1 6.5 - VDO V
VFB3 Feedback pin voltage 0.507 V
2.95 V ≤VIN3 ≤6.5 V
Feedback pin voltage accuracy(5) ±4%
1 mA ≤IOUT3 ≤300 mA
ΔVOUT%/ΔVIN Line regulation(5) VOUT3 + 0.5V ≤VIN3 ≤6.5 V 0.075 % / V
ΔVOUT%/ΔIOUT Load regulation 10 mA ≤IOUT3 ≤300 mA 0.01 % / mA
Dropout voltage
VDO IOUT3 = 300 mA 250 350 mV
(VIN = VOUT(NOM) - 0.1)(6)
ICL3 Current limit VOUT = 0.9 x VOUT(NOM) 375 600 1000 mA
IFB3 Current into FB3 pin 0.03 0.1 μA
BW = 100 Hz - 100 kHz,
VnOutput noise 400 μVRMS
IOUT3 = 300 mA
Shutdown, temperature increasing 175
Thermal shutdown temperature for
tSD °C
LDO Reset, temperature decreasing 160
Undervoltage lockout threshold VIN rising 1.8 V
UVLO Undervoltage lockout hysteresis VIN falling 100 mV
(4) Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested.
(5) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater.
(6) VDO does not apply when VOUT + VDO <2.2 V.
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SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
IN3
OUT3
FB1
FB2
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
PIN FUNCTIONS
PIN DESCRIPTION
NAME RHL
Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back side
DGND 6, 15, PAD exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet.
AGND 18 Ground connection for LDO
IN1 13 Input supply to BUCK1
IN2 8 Input supply to BUCK2
IN3 20 Input supply to LDO
Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode,
EN1 17 reducing operating current. The enable pin does not trigger on fast negative going transients.
EN2 4 Same as EN1 but for BUCK2 controller
EN3 3 Same as EN1 but for LDO
Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by slowing
SS1 16 the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is important. See the
Typical Characteristics, Applications, and PCB Layout sections for details.
SS2 5 Same as SS1 but for BUCK2 regulator.
Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby slowing
SS3 19 output voltage ramp-up. See the Applications section for details.
Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared to an
IS1 12 internal reference to set current limit. For a robust output start-up ramp, careful layout and bypassing are
required. See the Applications section for details.
IS2 9 Same as IS1, but compared to IN2 and used for BUCK2 controller
SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET
SW2 7 Same as SW1, but for BUCK2 controller
FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator
FB2 10 Same as FB1, but for BUCK2 controller
FB3 2 Same as FB1, but for LDO
Regulated LDO output. A small ceramic capacitor (≥2.2 μF) is needed from this pin to ground to ensure
OUT3 1 stability.
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0.01 Fm
33 mW
0.1 Fm
15 Hm
100 Fm
SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
100 Fm1 Fm
33 mW
0.1 Fm
5 Hm
10 Fm
15.4 kW
61.9 kW
61.9 kW
100 Fm
36.5 kW
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
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Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA
Figure 2.
TYPICAL CHARACTERISTICS
Measured using circuit in Figure 2
Buck ConverterBUCK LOAD REGULATION BUCK LOAD REGULATION
Figure 3. Figure 4.
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TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
BUCK LINE REGULATION BUCK LINE REGULATION
Figure 5. Figure 6.
BUCK SWITCHING FREQUENCY BUCK SWITCHING FREQUENCY
vs vs
IOUT, TAIOUT
Figure 7. Figure 8.
EFFICIENCY vs
BUCK OUTPUT VOLTAGE RIPPLE IOUT
Figure 9. Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
BUCK START-UP BUCK START-UP
vs vs
VIN and IOUT VIN and COUT
Figure 11. Figure 12.
BUCK START-UP BUCK START-UP
vs vs
VIN and CSS IOUT and CSS
Figure 13. Figure 14.
LDO Converter LDO LOAD REGULATION LDO LINE REGULATION
Figure 15. Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
LDO DROPOUT LDO DROPOUT
vs vs
IOUT TA
Figure 17. Figure 18.
RDS,ON PMOS RDS,ON NMOS
vs vs
VIN VIN
Figure 19. Figure 20.
LDO VOUT
vs
TA
Figure 21.
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APPLICATION INFORMATION
The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as
the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to
supply up to 3 A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300 mA.
All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp
time as required by the application.
Figure 2 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 through Table 4
show component values that have been tested for use with 2-A and 3-A load currents. Other similar external
components can be substituted as desired; however, in all cases the circuits that are used should be tested for
compliance to application requirements.
Table 1. Inductors Tested with the TPS75003
PART NUMBER MANUFACTURER INDUCTANCE DC RESISTANCE SATURATION CURRENT
SLF7032T−100M1R4 TDK 10 μH±20% 53 mΩ ±20% 1.4 A
SLF6025−150MR88 TDK 15 μH±20% 85 mΩ ±20% 0.88 A
CDRH6D28−5R0 Sumida 5 μH 23 mΩ2.4 A
CDRH6D38-5R0 Sumida 5 μH 18 mΩ2.9 A
CDRH103R−100 Sumida 10 μH 45 mΩ2.4 A
CDRH4D28−100 Sumida 10 μH 96 mΩ1 A
CDRH8D43-150 Sumida 15 μH 42 mΩ2.9 A
CDRH5D18−6R2 Sumida 6.2 μH 71 mΩ1.4 A
DO3316P−472 Coilcraft 4.7 μH 18 mΩ5.4 A
DT3316P−153 Coilcraft 15 μH 60 mΩ1.8 A
DT3316P−223 Coilcraft 22 μH 84 mΩ1.5 A
744052006 Wurth 6.2 μH 80 mΩ1.45 A
74451115 Wurth 15 μH 90 mΩ0.8 A
Table 2. PMOS Transistors Tested with the TPS75003
PART NUMBER MANUFACTURER RDS,ON (TYP) VDS IDPACKAGE
Si5447DC Vishay Siliconix 0.11 Ωat VGS = −2.5 V −20 V −3.5 A at +25°C 1206
Si5475DC Vishay Siliconix 0.041 Ωat VGS = −2.5 V −12 V −6.6 A at +25°C 1206
Si2323DS Vishay Siliconix 0.052 Ωat VGS = −2.5 V −20 V −4.1 A at +25°C SOT23
Si2301ADS Vishay Siliconix 0.19 Ωat VGS = −2.5 V −20 V −1.4 A at +25°C SOT23
Si2323DS Vishay Siliconix 0.41 Ωat VGS = −2.5 V −20 V −4.1 A at +25°C SOT23
FDG326P Fairchild 0.17 Ωat VGS = −2.5 V −20 V −1.5 A SC70
Table 3. Diodes Tested with the TPS75003
PART NUMBER MANUFACTURER VRIFPACKAGE
MBRM120LT3 ON Semiconductor 20 V 1 A DO216AA
MBR0530T1 ON Semiconductor 30 V 1.5 A SOD123
ZHCS2000TA Zetex 40 V 2 A SOT23−6
B320 Diodes Inc. 20 V 3 A SMA
SS32 Fairchild 20 V 3 A DO214AB
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Table 4. Capacitors Tested with the TPS75003
PART NUMBER MANUFACTURER CAPACITANCE ESR VOLTAGE RATING
6TPB47M (PosCap) Sanyo 47 μF 0.1 Ω6.3 V
T491D476M010AS Kemet 47 μF 0.8 Ω10 V
B45197A Epco 47 μF 0.175 Ω16 V
B45294−R1107−M40 Epco 100 μF 0.045 Ω6.3 V
594D476X0016C2 Vishay 47 μF 0.11 Ω16 V
594D127X96R3C2 Vishay 120 μF 0.085 Ω6.3 V
TPSC107K006R0150 AVX 100 μF 0.15 Ω6.3 V
6TPS100MC Sanyo 100 μF 0.45 Ω6.3 V
OPERATION (BUCK CONTROLLERS)
Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum
off-time hysteretic control. (See Figure 2.) For clarity, BUCK1 is used throughout the discussion of device
operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time,
increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is
reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of
the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on
again when necessary.
When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching
cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current
reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node
capacitance. This is normal operation; it does not affect circuit performance, and can be minimized if desired by
using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22.
Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing
At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at
the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform.
When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on
the external PMOS to allow regulation at lower dropout than would otherwise be possible.
Enable (Buck Controllers)
The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and
input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2,
respectively. If the soft-start feature is being used, enable should be driven high at least 10μs after VIN is applied
to ensure this discharge cycle occurs.
UVLO (Buck Controllers)
An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable
operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from
mis-operation at low input voltages.
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IS1,2
1,2
V
I =
LIMIT R
( )
OUT
RMS OUT OU T
IN
2
DISS RMS
V
I = I D = I
V
P = I R´
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Current Limit (Buck Controllers)
An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These
resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins
that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an
internal reference to determine if an over-current condition exists. When current limit is exceeded, the external
PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10 ns any time the PMOS is
turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled.
Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in
Equation 1.
(1)
The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current
calculated by Equation 2.
(2)
For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or
R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will
protect external components such as the inductor, the diode, and the switch itself from damage as a result of
overcurrent.
Short-Circuit Protection (Buck Controllers)
In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be
exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the
feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is
increased to approximately 4 μs. The increase in off-time is proportional to the difference between the voltage at
the feedback pin and the internal reference.
Soft-Start (Buck Controllers)
The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing
requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the
turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. See the
soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be
discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are high-impedance and cannot
be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any
charge on the SS pin is discharged by an on-chip pulldown transistor. When EN1 is driven high, an on-chip
current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to
the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage
drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the
minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the
soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see
the section, Selecting the Soft-Start Cap.
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( ) ( ) ( )
( )
22
OUTL
IN
RIPPLE IN IN
RIPPLE
1/2 L 0.3 I(1/2)L I
C , MIN = V V V V
´ ´´ D »
´ ´
OUT
C,IN(RMS )
IN
V
IV ,MIN
æ ö
»ç ÷
è ø
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Figure 23. Soft-Start Circuitry
Figure 24. Soft-Start Timing Diagram
Input Capacitor CIN1, CIN2 Selection (Buck Controllers)
It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low
impedance input supply. A capacitance of 10 μF to 22 μF for each buck converter is adequate for most
applications, and should be placed within 100 mils (0.001 in) of the IN1 and IN2 pins to minimize the effects of
pulsed current switching noise on the soft-start circuitry during the first ~1 V of output voltage ramp. Low ESR
capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated
using Equation 3.
(3)
Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be
calculated using Equation 4.
(4)
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( )
(OF F,min) OU T SCHO TTKY L O UT
IN OUT DS(on) L OUT
ON
t V + V + R I
V V IOUT r R I t ,MIN
´ ´
- - ´ - ´ ³
( )
IN OUT OUT DS(on) L OUT ON
MIN
V V I r R I t ,MIN
L = I
- - ´ - ´ ´
D
( )
O UT S CH OTTKY L OUT OF F
MIN
V + V + R I t ,MIN
L = I
´ ´
D
OUT
PMOS(RMS) OUT OUT
IN
V
I I D = I V
»
( ) [ ]( ) ( )
2
(cond) OUT DS(on) J OUT DS(on)
P = I r 1 + TC T 25 C I D r´ ´ ´ - ° » ´D
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Inductor Value Selection (Buck Controllers)
The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current
ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower
DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck
converters work well with inductor values between 4.7 μH and 47 μH in most applications. When selecting an
inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see Current Limit section). To
determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum
off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied.
(5)
where RL= the inductor's DC resistance.
Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6.
(6)
Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7.
(7)
External PMOS Transistor Selection (Buck Controllers)
The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate
capacitance (CG) and voltage rating. The PMOS VTmagnitude must be much lower than the lowest voltage at
IN1 or IN2 that will be used. A VTmagnitude that is 0.5 V less than the lowest input voltage is normally sufficient.
The PMOS gate will see voltages from 0 V to the maximum input voltage, so gate-to-source breakdown should
be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full
voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in
the PMOS can be estimated by using Equation 8.
(8)
The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are
typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and
are calculated by Equation 9.
(9)
16 Copyright ©2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS75003-EP
OUT
(diode)(RMS) OUT OUT
IN
V
I I (1 D) = I 1 V
æ ö
» - -
ç ÷
è ø
1.1
PP
1
V = I ES R + I ESR
8 COUT f
é ù
æ ö
D D ´ » D ´
ç ÷ê ú
´ ´
è ø
ë û
( )
2
O UT
OU T
IN OUT
L ΔI
C =
V V ΔV
´
- ´
TPS75003-EP
www.ti.com
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Diode Selection (Buck Controllers)
The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a
relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the
diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage
current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated
average power dissipation.
(10)
Output Capacitor Selection (Buck Controllers)
The output capacitor is selected based on output voltage ripple and transient response requirements. As a result
of the nature of the hysteretic control loop, a minimum ESR of a few tens of mΩshould be maintained for good
operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most
applications. A 1-μF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency spikes.
The output voltage ripple can be estimated by Equation 11.
(11)
To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero
output to full current, use Equation 12.
(12)
If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must
be passed to the feedback pin. See Application Note, Using Ceramic Output Capacitors with the TPS6420x Buck
Controllers (SLVA210), for detailed application information.
Output Voltage Ripple Effect on VOUT (Buck Controllers)
Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage
ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage.
Soft-Start Capacitor Selection (Buck Controllers)
BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by
ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the
external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current
limit ramp time of approximately 250 μs. Figure 25 shows the effects of R1 and SS1 on the current limit start-up
ramp.
Copyright ©2006–2011, Texas Instruments Incorporated 17
Product Folder Link(s): TPS75003-EP
C = 0.01 F
SS1 mR1 = 33 mW
C = 0.022 F
SS1 m
R1 = 143 mW
C = 0.022 F
SS1 m
C = 0.01 F
SS1 m
5
OUT F B
6
R
V = V +1
R
æ ö
ç ÷
è ø
TPS75003-EP
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
www.ti.com
Figure 25. Effects of CSS1 and R1on Current Ramp Limit
This soft-start current limit ramo can be used to provide inrush current control or output voltage ramp control.
While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a
complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less
important variables are VIN1 and L1.
The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1
to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to
approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth
of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1.
Slowest start-up times occur under opposite conditions.
See Figure 11 to Figure 14 for characterization curves showing how the start-up profile is affected by these
critical parameters.
Output Voltage Setting Selection (Buck Controllers)
Output voltage is set using two resistors as shown for Buck2 in Figure 2. Output voltage is then calculated using
Equation 13.
(13)
where VFB = 1.24V.
LDO OPERATION
The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of
programming to any output voltage. When used to power VCC,AUX it is set to 2.5 V; it can optionally be set to
other output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and
short-circuit and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when
3.3-V JTAG signals are used as described in Application Note SLVA159 (available for download from
www.ti.com).
Input Capacitor Selection (LDO)
Although an input capacitor is not required, it is good analog design practice to connect a 0.1-μF to 10-μF low
ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and
improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast
rise-time load transients are anticipated, or if the device is located far from its power source.
18 Copyright ©2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS75003-EP
1
3
OU T FB
4
R
V = V
R
æ ö
+
ç ÷
è ø
TPS75003-EP
www.ti.com
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Output Capacitor Selection (LDO)
A 2.2 μF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with
any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or
lower ESR output capacitors can be used.
Soft-Start (LDO)
The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control
loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the
current-controlled soft-start used by the buck controllers.
Setting Output Voltage (LDO)
Output voltage is set using two resistors as shown in Figure 2. Output voltage is then calculated using
Equation 14.
(14)
where VFB = 0.507 V.
Internal Current Limit (LDO)
The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current
condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the
device. For good device reliability, the LDO should not operate at current limit.
Enable Pin (LDO)
The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start
capability are not required, EN3 can be tied to IN3.
Dropout Voltage (LDO)
The LDO uses a PMOS transistor to achieve low dropout. When (VIN –VOUT) is less than the dropout voltage
(VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass
transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load
regulation degrade as (VIN –VOUT) falls much below 0.5 V.
Transient Response (LDO)
The LDO does not have an on-chip pulldown circuit for output is over-voltage conditions. This feature permits
applications that connect higher voltage sources such as an alternate power supply to the output. This design
also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of
overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load
resistor.
Thermal Protection (LDO)
Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the
junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the
regulator, protecting it from damage. For good long term reliability, the device should not be continuously
operated at or near thermal shutdown.
Copyright ©2006–2011, Texas Instruments Incorporated 19
Product Folder Link(s): TPS75003-EP
( )
D IN3 OU T3 O UT 3
P = V V I- ´
SS3
AGND
EN1
SS1
SW1
IN1
IS1
DGND
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
TPS75003-EP
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
www.ti.com
Power Dissipation (LDO)
The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The
exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is
configured to remove the amount of power dissipated by the LDO, as calculated by Equation 15.
(15)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using
heavier copper increases the overall effectiveness of removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also improves the heatsink effectiveness.
PCB Layout Considerations
As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and
corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are
shown in Figure 26 through Figure 28.
Note: Most sensitive areas are highlighted by bold lines.
Figure 26. Typical Application Circuit
20 Copyright ©2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS75003-EP
TPS75003-EP
www.ti.com
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
REVISION HISTORY
Changes from Original (December 2006) to Revision A Page
•Replaced the DISSIPATION RATINGS table with the Thermal Information Table .............................................................. 3
Copyright ©2006–2011, Texas Instruments Incorporated 23
Product Folder Link(s): TPS75003-EP
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS75003MRHLREP VQFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS75003MRHLREP VQFN RHL 20 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2013
Pack Materials-Page 2
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PACKAGE OUTLINE
4219071 / A 05/2017
www.ti.com
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RHL0020A
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
SYMM
PIN 1 INDEX AREA
SEATING PLANE
C
1
PIN 1 ID
(OPTIONAL)
2.05±0.1
3.05±0.1
3.6
3.4
4.6
4.4
1 MAX
(0.2) TYP
2X (0.55)
2X
3.5
14X 0.5
2
9
10 11
12
19
20
2X 1.5
4X (0.2)
20X 0.29
0.19
20X 0.5
0.3
21
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271) .
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219071 / A 05/2017
www.ti.com
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
2X (1.5)
6X (0.525)
4X
(0.775)
(4.3)
(3.3)
20X (0.6)
20X (0.24)
14X (0.5)
(3.05)
(2.05)
(R0.05) TYP
(Ø0.2) VIA
TYP)
1
2
9
10 11
12
19
20
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
21
2X (0.75)
2X (0.4)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
4X (0.2)
2X (0.55)
EXPOSED METAL EXPOSED METAL
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
EXAMPLE STENCIL DESIGN
4219071 / A 05/2017
www.ti.com
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 20X
(4.3)
2X (1.5)
(3.3)
(1.05)
TYP
6X (0.92)
6X
(0.85)
14X (0.5)
20X (0.24)
20X (0.6)
(0.56)
TYP
METAL
TYP
21
4X (0.2)
2X (0.25)
(0.55)
TYP
SOLDER MASK EDGE
TYP
2X
(0.775)
1
2
9
10 11
12
19
20
(R0.05) TYP
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