LT1175
1
1175ff
TYPICAL APPLICATION
FEATURES DESCRIPTION
500mA Negative
Low Dropout Micropower
Regulator
The LT
®
1175 is a negative micropower low dropout
regulator. It features 45μA quiescent current, dropping
to 10μA in shutdown. A new reference amplifi er topology
gives precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
effi ciency are obtained with a unique power transistor
anti-saturation design. Adjustable and fi xed 5V versions
are available.
Several new features make the LT1175 very user-friendly.
The SHDN pin can interface directly to either positive or
negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latchup. Un-
like some earlier designs, the increase in quiescent current
during a dropout condition is actively limited.
The LT1175 has complete blowout protection with current
limiting, power limiting and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents,
preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin PDIP and SO packages, 3-lead SOT-
223 as well as 5-pin surface mount DD and through-hole
TO-220 packages. The 8-pin SO package is specially
constructed for low thermal resistance.
Typical LT1175 Connection
APPLICATIONS
n Operating Current: 45μA
n Adjustable Current Limit
n Low Voltage Linear Dropout Characteristics
n Stable with Wide Range of Output Capacitors
n Shutdown Current: 10μA
n Positive or Negative Shutdown Logic
n Fixed 5V and Adjustable Versions
n Tolerates Reverse Output Voltage
n Available in 8-pin PDIP and SO Packages, 3-lead
SOT-223, 5-Pin Surface Mount DD and Through-Hole
TO-220 Packages
n Analog Systems
n Modems
n Instrumentation
n A/D and D/A Converters
n Interface Drivers
n Battery-Powered Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Minimum Input-to-Output Voltage
CIN*
*CIN IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
SECTION FOR DETAILS
COUT
≥ 0.1μF
–5V
UP TO 500mA
–VIN
SHDN GND
LT1175-5
SENSE
OUTPUT
1175 TA01
ILIM4
ILIM2
VIN
+ +
OUTPUT CURRENT (A)
0
INPUT-TO-OUTPUT VOLTAGE (V)
1.0
0.8
0.6
0.4
0.2
0
0.2 0.4 0.5
1175 TA02
0.1 0.3 0.6 0.7
TJ = 25°C
ILIM2, ILIM4 TIED TO VIN
LT1175
2
1175ff
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Transient 1 sec, Note 12) ...................25V
Input Voltage (Continuous) .......................................20V
Input-to-Output Differential Voltage (Note 13) ..........20V
5V SENSE Pin (with Respect to GND Pin) ......... 2V, –10V
ADJ SENSE Pin
(with Respect to OUTPUT Pin) ...................20V, –0.5V
5V SENSE Pin
(with Respect to OUTPUT Pin) ......................20V, –7V
PIN CONFIGURATION
Output Reverse Voltage ..............................................2V
SHDN Pin to GND Pin Voltage (Note 3) ........13.5V, –20V
SHDN Pin to VIN Pin Voltage .............................30V, –5V
Operating Junction Temperature Range (Note 2)
LT1175C ................................................. 0°C to 125°C
LT1175I .............................................. –40°C to 125°C
LT1175MP .......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
1
2
3
4
8
7
6
5
TOP VIEW
VIN
ILIM2
OUTPUT
SENSE
VIN
ILIM4
SHD
N
GND
N8 PACKAGE
8-LEAD PDIP
θJA = 80°C/W TO 120°C/W
DEPENDING ON PC BOARD LAYOUT
SHDN
GND
VIN
SENSE
OUTPUT
Q PACKAGE
5-LEAD PLASTIC DD-PAK
FRONT VIEW
TAB
IS
VIN
5
4
3
2
1
θJA = 27°C/W TO 60°C/W
DEPENDING ON PC MOUNTING.
SEE DATA SHEET FOR DETAILS
3
2
1
FRONT VIEW
TAB IS
VIN
GND
VIN
OUTPUT
ST PACKAGE
3-LEAD PLASTIC SOT-223
θJA = 50°C/W
WITH BACKPLANE AND 10cm2
TOPSIDE LAND SOLDERED TO TAB
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
VIN
ILIM2
OUTPUT
SENSE
VIN
ILIM4
SHD
N
GND
θJA = 60°C/W TO 100°C/W
DEPENDING ON PC BOARD LAYOUT
PINS 1, 8 ARE INTERNALLY CONNECTED TO DIE ATTACH PADDLE FOR HEAT SINKING.
ELECTRICAL CONTACT CAN BE MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE,
PINS 1, 8 SHOULD BE CONNECTED TO AN EXPANDED LAND THAT IS OVER AN INTERNAL
OR BACKSIDE PLANE.
SEE APPLICATIONS INFORMATION
T PACKAGE
5-LEAD PLASTIC TO-220
FRONT VIEW
5
4
3
2
1
SHDN
GND
VIN
SENSE
OUTPUT
TAB IS
VIN
θJA = 50°C/W, θJC = 5°C/W
(Note 1)
LT1175
3
1175ff
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1175CN8#PBF LT1175CN8#TRPBF LT1175CN8 8-Lead Plastic Dip 0°C to 125°C
LT1175CN8-5#PBF LT1175CN8-5#TRPBF LT1175CN8-5 8-Lead Plastic Dip 0°C to 125°C
LT1175CS8#PBF LT1175CS8#TRPBF 1175 8-Lead Plastic SO 0°C to 125°C
LT1175CS8-5#PBF LT1175CS8-5#TRPBF 11755 8-Lead Plastic SO 0°C to 125°C
LT1175CST-5#PBF LT1175CST-5#TRPBF 11755 3-Lead Plastic SOT-223 0°C to 125°C
LT1175CQ#PBF LT1175CQ#TRPBF LT1175CQ 5-Lead Plastic DD-Pak 0°C to 125°C
LT1175CQ-5#PBF LT1175CQ-5#TRPBF LT1175CQ-5 5-Lead Plastic DD-Pak 0°C to 125°C
LT1175CT#PBF LT1175CT#TRPBF LT1175CT 5-Lead Plastic TO-220 0°C to 125°C
LT1175CT-5#PBF LT1175CT-5#TRPBF LT1175CT-5 5-Lead Plastic TO-220 0°C to 125°C
LT1175IN8#PBF LT1175IN8#TRPBF LT1175IN8 8-Lead Plastic Dip –40°C to 125°C
LT1175IN8-5#PBF LT1175IN8-5#TRPBF LT1175IN8-5 8-Lead Plastic Dip –40°C to 125°C
LT1175IS8#PBF LT1175IS8#TRPBF 1175I 8-Lead Plastic SO –40°C to 125°C
LT1175IS8-5#PBF LT1175IS8-5#TRPBF 1175I5 8-Lead Plastic SO –40°C to 125°C
LT1175IST-5#PBF LT1175IST-5#TRPBF 1175I5 3-Lead Plastic SOT-223 –40°C to 125°C
LT1175IQ#PBF LT1175IQ#TRPBF LT1175IQ 5-Lead Plastic DD-Pak –40°C to 125°C
LT1175IQ-5#PBF LT1175IQ-5#TRPBF LT1175IQ-5 5-Lead Plastic DD-Pak –40°C to 125°C
LT1175IT#PBF LT1175IT#TRPBF LT1175IT 5-Lead Plastic TO-220 –40°C to 125°C
LT1175IT-5#PBF LT1175IT-5#TRPBF LT1175IT-5 5-Lead Plastic TO-220 –40°C to 125°C
LT1175MPS8#PBF LT1175MPS8#TRPBF 1175MP 8-Lead Plastic SO –55°C to 125°C
LT1175MPS8-5#PBF LT1175MPS8-5#TRPBF 175MP5 8-Lead Plastic SO –55°C to 125°C
LT1175MPQ#PBF LT1175MPQ#TRPBF LT1175MPQ 5-Lead Plastic DD-Pak –55°C to 125°C
LT1175MPQ-5#PBF LT1175MPQ-5#TRPBF LT1175MPQ-5 5-Lead Plastic DD-Pak –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1175CN8 LT1175CN8#TR LT1175CN8 8-Lead Plastic Dip 0°C to 125°C
LT1175CN8-5 LT1175CN8-5#TR LT1175CN8-5 8-Lead Plastic Dip 0°C to 125°C
LT1175CS8 LT1175CS8#TR 1175 8-Lead Plastic SO 0°C to 125°C
LT1175CS8-5 LT1175CS8-5#TR 11755 8-Lead Plastic SO 0°C to 125°C
LT1175CST-5 LT1175CST-5#TR 11755 3-Lead Plastic SOT-223 0°C to 125°C
LT1175CQ LT1175CQ#TR LT1175CQ 5-Lead Plastic DD-Pak 0°C to 125°C
LT1175CQ-5 LT1175CQ-5#TR LT1175CQ-5 5-Lead Plastic DD-Pak 0°C to 125°C
LT1175CT LT1175CT#TR LT1175CT 5-Lead Plastic TO-220 0°C to 125°C
LT1175CT-5 LT1175CT-5#TR LT1175CT-5 5-Lead Plastic TO-220 0°C to 125°C
LT1175IN8 LT1175IN8#TR LT1175IN8 8-Lead Plastic Dip –40°C to 125°C
LT1175IN8-5 LT1175IN8-5#TR LT1175IN8-5 8-Lead Plastic Dip –40°C to 125°C
LT1175IS8 LT1175IS8#TR 1175I 8-Lead Plastic SO –40°C to 125°C
LT1175IS8-5 LT1175IS8-5#TR 1175I5 8-Lead Plastic SO –40°C to 125°C
LT1175IST-5 LT1175IST-5#TR 1175I5 3-Lead Plastic SOT-223 –40°C to 125°C
LT1175IQ LT1175IQ#TR LT1175IQ 5-Lead Plastic DD-Pak –40°C to 125°C
LT1175IQ-5 LT1175IQ-5#TR LT1175IQ-5 5-Lead Plastic DD-Pak –40°C to 125°C
LT1175
4
1175ff
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1175IT LT1175IT#TR LT1175IT 5-Lead Plastic TO-220 –40°C to 125°C
LT1175IT-5 LT1175IT-5#TR LT1175IT-5 5-Lead Plastic TO-220 –40°C to 125°C
LT1175MPS8 LT1175MPS8#TR 1175MP 8-Lead Plastic SO –55°C to 125°C
LT1175MPS8-5 LT1175MPS8-5#TR 175MP5 8-Lead Plastic SO –55°C to 125°C
LT1175MPQ LT1175MPQ#TR LT1175MPQ 5-Lead Plastic DD-Pak –55°C to 125°C
LT1175MPQ-5 LT1175MPQ-5#TR LT1175MPQ-5 5-Lead Plastic DD-Pak –55°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VOUT = 5V, VIN = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to VIN.
To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values except where
polarity is not obvious.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Feedback Sense Voltage Adjustable Part
Fixed 5V Part
3.743
4.93
3.8
5.0
3.857
5.075
V
V
Output Voltage Initial Accuracy Adjustable, Measured at 3.8V Sense
Fixed 5V
0.5
0.5
1.5
1.5
%
%
Output Voltage Accuracy (All Conditions) VIN – VOUT = 1V to VIN = 20V, IOUT = 0A to 500mA
P = 0 to PMAX, TJ = TMIN to TMAX (Note 4)
l1.5 2.5 %
Quiescent Input Supply Current VIN – VOUT ≤ 12V
l
45 65
80
μA
μA
GND Pin Current Increase with Load (Note 5) l10 20 μA/mA
Input Supply Current in Shutdown VSHDN = 0V
l
10 20
25
μA
μA
Shutdown Thresholds (Note 10) Either Polarity On SHDN Pin (C-, I-Grades)
Either Polarity On SHDN Pin (MP-Grade)
l
l
0.8
0.8
2.5
2.6
V
V
SHDN Pin Current (Note 3) VSHDN = 0V to 10V (Flows Into Pin)
VSHDN = –15V to 0V (Flows Into Pin)
l4
1
8
4
μA
μA
Output Bleed Current in Shutdown (Note 7) VOUT = 0V, VIN = 15V
l
0.1
1
1
5
μA
μA
SENSE Pin Input Current (Adjustable Part Only, Current Flows Out of Pin)
(Fixed Voltage Only, Current Flows Out of Pin)
l
l
75
12
150
20
nA
μA
Dropout Voltage (Note 8) IOUT = 25mA
IOUT = 100mA
IOUT = 500mA
ILIM2 Open, IOUT = 300mA
ILIM4 Open, IOUT = 200mA
ILIM2, ILIM4 Open, IOUT = 100mA
l
l
l
l
l
l
0.1
0.18
0.5
0.33
0.3
0.26
0.2
0.26
0.7
0.5
0.45
0.45
V
V
V
V
V
V
LT1175
5
1175ff
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1175 regulators are tested and specifi ed under pulse load
conditions such that TJ TA. The LT1175C is 100% production tested
at TA = 25°C. Performance at 0°C and 125°C is assured by design,
characterization and correlation with statistical process controls. The
LT1175I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT1175MP is 100% tested and guaranteed over
the –55°C to 125°C operating junction temperature range.
Note 3: SHDN pin maximum positive voltage is 30V with respect to
–VIN and 13.5V with respect to GND. Maximum negative voltage is –20V
with respect to GND and –5V with respect to –VIN.
Note 4: PMAX = 1.5W for 8-pin packages, and 6W for 5-pin packages.
This power level holds only for input-to-output voltages up to 12V, beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 5: GND pin current increases because of power transistor base
drive. At low input-to-output voltages (<1V) where the power transistor
is in saturation, GND pin current will be slightly higher. See Typical
Performance Characteristics.
Note 6: With ILOAD = 0, at TJ > 125°C, power transistor leakage could
increase higher than the 10μA to 25μA drawn by the output divider or fi xed
voltage SENSE pin, causing the output to rise above the regulated value.
To prevent this condition, an internal active pull-up will automatically turn
on, but supply current will increase.
Note 7: This is the current required to pull the output voltage to within 1V
of ground during shutdown.
Note 8: Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
VIN and VOUT. For currents between 100mA and 500mA, with both ILIM
pins tied to VIN, maximum dropout can be calculated from
VDO = 0.15 + 1.1Ω (IOUT).
Note 9: Thermal regulation is a change in the output voltage caused by
die temperature gradients, so it is proportional to chip power dissipation.
Temperature gradients reach fi nal value in less than 100ms. Output voltage
changes after 100ms are due to absolute die temperature changes and
reference voltage temperature coeffi cient.
Note 10: The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used, referenced to GND pin.
Note 11: Load and line regulation are measured on a pulse basis with
pulse width of 20ms or less to keep chip temperature constant. DC
regulation will be affected by thermal regulation (Note 8) and chip
temperature changes. Load regulation specifi cation also holds for currents
up to the specifi ed current limit when ILIM2 or ILIM4 are left open.
Note 12: Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.
Note 13: Operating at very large input-to-output differential voltages
(>15V) with load currents less than 5mA requires an output capacitor with
an ESR greater than 1Ω to prevent low level output oscillations.
ELECTRICAL CHARACTERISTICS
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VOUT = 5V, VIN = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to VIN.
To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values except where
polarity is not obvious.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Limit (Note 12) VIN – VOUT = 1V to 12V
ILIM2 Open
ILIM4 Open
ILIM2, ILIM4 Open
l
l
l
l
520
390
260
130
800
600
400
200
1300
975
650
325
mA
mA
mA
mA
Line Regulation (Note 11) VIN – VOUT = 1V to VIN = 20V l0.003 0.015 %/V
Load Regulation (Note 6, 11) IOUT = 0mA to 500mA l0.1 0.35 %
Thermal Regulation P = 0 to PMAX (Notes 4, 9) 5-Pin Packages
8-Pin Packages
0.04
0.1
0.1
0.2
%/W
%/W
Output Voltage Temperature Drift TJ = 25°C to TJMIN, or 25°C to TJMAX 0.25 1.25 %
LT1175
6
1175ff
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Current Limit
Characteristics Guaranteed Current Limit Output Voltage Temperature Drift
Minimum Input-to-Output Voltage Minimum Input-to-Output Voltage
SENSE Bias Current
(Adjustable Part)
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
0
CURRENT (A)
1.0
0.8
0.6
0.4
0.2
020
1175 G01
510 15 25
ILIM2, ILIM4 TIED TO VIN
ILIM2, ILIM4 OPEN
ILIM4 TIED TO VIN
ILIM2 TIED TO VIN
CURRENT LIMIT CHANGES ONLY SLIGHTLY
WITH TEMPERATURE SO CURVES ARE
REPRESENTATIVE OF ALL TEMPERATURES
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
0
CURRENT (A)
0.6
0.5
0.4
0.3
0.2
0.1
05101520
1175 G02
25
CURVES REPRE-
SENT MINIMUM
GUARANTEED
LIMITS AT ALL
TEMPERATURES
ILIM2, ILIM4 OPEN
ILIM4 TIED TO VIN
ILIM2 TIED TO VIN
ILIM2, ILIM4 TIED TO VIN
JUNCTION TEMPERATURE (°C)
–50
VOLTAGE (V)
5.05
5.00
4.95
3.84
3.80
3.76
050 75
1175 G03
–25 25 100 125
OUTPUT
FIXED 5V PART
FEEDBACK VOLTAGE
ADJUSTABLE PART
OUTPUT CURRENT (A)
0
INPUT-TO-OUTPUT VOLTAGE (V)
1.0
0.8
0.6
0.4
0.2
0
0.2 0.4 0.5
1175 G04
0.1 0.3 0.6 0.7
TJ = 25°C
VIN REDUCED
UNTIL OUTPUT
VOLTAGE
DROPS 1%
ILIM2, ILIM4
OPEN
ILIM2, ILIM4
TIED TO VIN
ILIM4 TIED
TO VIN
ILIM2 TIED
TO VIN
OUTPUT CURRENT (A)
0
INPUT-TO-OUTPUT VOLTAGE (V)
1.0
0.8
0.6
0.4
0.2
0
0.2 0.4 0.5
1175 G05
0.1 0.3 0.6 0.7
VIN REDUCED UNTIL OUTPUT
VOLTAGE DROPS 1%.
ILIM2, ILIM4 TIED TO VIN
TJ = 125°C
TJ = –55°C
TJ = 25°C
TEMPERATURE (°C)
–50
CURRENT (nA)
100
80
60
40
20
0
050 75
1175 G06
–25 25 100 125
LT1175
7
1175ff
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current Ripple Rejection
Shutdown Input Current Shutdown Thresholds SHDN Pin Characteristics
INPUT VOLTAGE (V)
0
INPUT CURRENT (μA)
25
20
15
10
5
020
1175 G07
510 15 25
TJ = 125°C
TJ = –55°C
TJ = 25°C
TEMPERATURE (°C)
–50
THRESHOLD (V)
2.5
2.0
1.5
1.0
0.5
0
05025 75
1175 G08
–25 100 125
POSITIVE THRESHOLD
NEGATIVE THRESHOLD
DEVICE IS OFF
BELOW THRESHOLD
SHUTDOWN TO GROUND VOLTAGE (V)
–25 –20 –10 0
PIN CURRENT (μA)
15
10
5
0
–5
–10 15
1175 G09
–15 –5 10 20
525
VIN = 25V
CHARACTERISTICS DO NOT
CHANGE SIGNIFICANTLY WITH
TEMPERATURE, SO A SINGLE
CURVE IS SHOWN. POSITIVE
CURRENT FLOWS INTO
SHDN PIN
IF SHDN PIN IS NEGATIVE WITH
RESPECT TO INPUT VOLTAGE AND
INPUT VOLTAGE IS LESS THAN 15V,
NEGATIVE BREAKOVER POINT WILL
BE ABOUT 8V BELOW –VIN
OUTPUT CURRENT (A)
0
GROUND PIN CURRENT (mA)
20
16
12
8
4
0
0.2 0.40.3 0.5
1175 G10
0.1 0.6 0.7
POWER
TRANSISTOR
IN DROPOUT
TJ = –55°C
TJ = 25°C
VIN – VOUT ≥ 3V
TJ = 25°C
VIN – VOUT = 2V
TJ = 25°C
FREQUENCY (Hz)
REJECTION (dB)
100
80
60
40
20
010 1k 10k 1M100 100k
VOUT = 12V
(ADJUSTABLE)
IOUT = 100mA
VIN – VOUT = 2V
COUT = 1μF TANT
1175 G11
RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF
INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN
25mA AND 500mA. LARGER OUTPUT CAPACITORS DO
NOT IMPROVE REJECTION FOR FREQUENCIES BELOW
50kHz. AT VERY LIGHT LOADS, REJECTION WILL
IMPROVE WITH LARGER OUTPUT CAPACITORS
VOUT = 12V
(ADJUSTABLE)
WITH 0.1μF ACROSS
DIVIDER RESISTOR
VOUT = 5V
(FIXED)
LT1175
8
1175ff
PIN FUNCTIONS
VIN (Pins 1, 8/Pin 3, Tab/Pin 2, Tab/Pins 1, 8/Pin 3, Tab):
Power is supplied to the device through this pin. A bypass
capacitor is required on this pin if the device is more than
six inches away from the main fi lter capacitor. In general,
the impedance of a battery rises with frequency, so it is
advisable to include a bypass capacitor in battery-powered
circuits. A 1μF or larger tantalum capacitor is suggested
for all applications, but if low ESR capacitors such as
ceramic or fi lm are used for the output and input capaci-
tors, the input capacitor should be three times the value
of the output capacitor.
ILIM2, ILIM4 (Pins 2, 7/NA/NA/Pins 2, 7/NA): The two
current limit pins are emitter sections of the power transis-
tor. When left open, they fl oat several hundred millivolts
above the negative input voltage. When shorted to the
input voltage, they increase current limit by a minimum
of 200mA for ILIM2 and 400mA for ILIM4. These pins must
be connected only to the input voltage, either directly or
through a resistor.
OUTPUT (Pin 3/Pin 1/Pin 1/Pin 3/Pin 1): The OUTPUT pin
is the collector of the NPN power transistor. It can be forced
to the input voltage, to ground or up to 2V positive with
respect to ground without damage or latchup (see Output
Voltage Reversal in Applications Information section). The
LT1175 has foldback current limit, so maximum current at
the OUTPUT pin is a function of input-to-output voltage.
See Typical Performance Characteristics.
SENSE (Pin 4/Pin 2/NA/Pin 4/Pin 2): The SENSE pin is
used in the adjustable version to allow custom selection
of output voltage, with an external divider set to generate
3.8V at the SENSE pin. Input bias current is typically 75nA
fl owing out of the pin. Maximum forced voltage on the
SENSE pin is 2V and –10V with respect to GND pin.
The fi xed 5V version utilizes the SENSE pin to give true
Kelvin connections to the load or to drive an external pass
transistor for higher output currents. Bias current out
of the 5V SENSE pin is approximately 12μA. Separating
the SENSE and OUTPUT pins also allows for a new loop
compensation technique described in the Applications
Information section.
GND (Pin 5/Pin 4/Pin 3/Pin 5/Pin 4): The GND pin has a
quiescent current of 45μA at zero load current, increas-
ing by approximately 10μA per mA of output current. At
500mA output current, GND pin current is about 5mA.
Current fl ows into the GND pin.
SHDN (Pin 6/Pin 5/NA/Pin 6/Pin 5): The SHDN pin is
specially confi gured to allow it to be driven from either
positive voltage logic or with negative only logic. Forc-
ing the SHDN pin 2V either above or below the GND
pin will turn the regulator on. This makes it simple to
connect directly to positive logic signals for active low
shutdown. If no positive voltages are available, the
SHDN pin can be driven below the GND pin to turn the
regulator on. When left open, the SHDN pin will default
low to a regulator “on” condition. For all voltages below
absolute maximum ratings, the SHDN pin draws only a
few microamperes of current (see Typical Performance
Characteristics). Maximum voltage on the SHDN pin is 15V,
–20V with respect to the GND pin and 35V, –5V with
respect to the negative input pin.
(N8/Q/ST/S8/T)
LT1175
9
1175ff
APPLICATIONS INFORMATION
Setting Output Voltage
The LT1175 adjustable version has a feedback sense
voltage of 3.8V with a bias current of approximately 75nA
fl owing out of the SENSE pin. To avoid output voltage
errors caused by this current, the output divider string
(see Figure 1) should draw about 25μA. Table 1 shows
suggested resistor values for a range of output voltages.
The second part of the table shows resistor values which
draw only 10μA of current. Output voltage error caused
by bias current with the lower valued resistors is about
0.4% maximum and with the higher values, about 1%
maximum. A formula is also shown for calculating the
resistors for any output voltage.
Table 1. Suggested Divider Resistors
OUTPUT
VOLTAGE
R1
IDIV = 25μA
R2
NEAREST 1%
R1
IDIV = 10μA
R2
NEAREST 1%
5V 150k 47.5k 383k 121k
6V 150k 86.6k 383k 221k
8V 150k 165k 383k 422k
10V 150k 243k 383k 619k
12V 150k 324k 383k 825k
15V 150k 442k 383k 1.13M
RV
I
RRV V
VSimple formula
RV V
VRI
I Desired
DIV
OUT
OUT
FB
DIV
138
2138
38
138
38 1
=
=−
()
()
=−
()
+
()
⎛
⎝
⎜⎞
⎠
⎟
=
.
.
.
.
.
R2 Taking SENSE pin bias
current into account
divider current
Note to Reader: To avoid confusion when working with
negative voltages (is –6V more or less than –5V?), I have
decided to treat the LT1175 as if it were a positive regulator
and express all voltages as positive values, both in text and
in formulas. If you do the same and simply add a negative
sign to the eventual answer, confusion should be avoided.
Please don’t give me a hard time about “preciseness” or
“correctness.” I have to fi eld phone calls from around
the world and this is my way of dealing with a multitude
of conventions. Thanks for your patience.
The LT1175-5 is a fi xed 5V design with the SENSE pin
acting as a Kelvin connection to the output. Normally the
SENSE pin and the OUTPUT pin are connected directly
together, either close to the regulator or at the remote
load point.
Setting Current Limit
The LT1175 uses two ILIM pins to set current limit (typical)
at 200mA, 400mA, 600mA or 800mA. The corresponding
minimum guaranteed currents are 130mA, 260mA, 390mA
and 520mA. This allows the user to select a current limit
tailored to his specifi c application and prevents the situa-
tion where short-circuit current is many times higher than
full-load current. Problems with input supply overload or
excessive power dissipation in a faulted load are prevented.
Power limiting in the form of foldback current limit is built
in and reduces current limit as a function of input-to-output
voltage differential for differentials exceed
ing 14V. See the
graph in Typical Performance Characteristics. The LT1175
is guaranteed to be blowout-proof regardless of current
limit setting. The power limiting combined with thermal
shutdown protects the device from destructive junction
temperatures under all load conditions.
Shutdown
In shutdown, the LT1175 draws only about 10μA. Special
circuitry is used to minimize increases in shutdown cur-
rent at high temperatures, but a slight increase is seen
above 125°C. One option not taken was to actively pull
down on the output during shutdown. This means that the
output will fall slowly after shutdown is initiated, at a rate
determined by load current plus the 12μA internal load,
and the size of the output capacitor. Active pull-down is
Figure 1. Typical LT1175 Adjustable Connection
+
CIN
COUT
≥ 0.1μF
VOUT
–12V
R2
825k
1%
R1
383k
1%
SHUTDOWN
LOGIC
SHDN GND
LT1175
SENSE
OUTPUT
> 2V OR < –2V TO
TURN REGULATOR ON
1175 F01
ILIM4
ILIM2
VIN
+
LT1175
10
1175ff
APPLICATIONS INFORMATION
normally a good thing when the regulator is used by itself,
but it prevents the user from shutting down the regulator
when a second power source is connected to the LT1175
output. If active output pull-down is needed in shutdown,
it can be added externally with a depletion mode PFET as
shown in Figure 2. Note that the maximum pinch-off volt-
age of the PFET must be less than the positive logic high
level to ensure that the device is completely off when the
regulator is active. The Motorola J177 device has 300Ω
on resistance for zero gate source voltage.
yet allows the power transistor to approach its theoretical
saturation limit.
Output Capacitor
Several new regulator design techniques are used to make
the LT1175 extremely tolerant of output capacitor selection.
Like most low dropout designs which use a collector or
drain of the power transistor to drive the output node, the
LT1175 uses the output capacitor as part of the overall
loop compensation. Older regulators generally required
the output capacitor to have a minimum value of 1μF to
100μF, a maximum ESR (Effective Series Resistance) of
0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to
0.3Ω. These restrictions usually could be met only with
good quality solid tantalum capacitors. Aluminum capaci-
tors have problems with high ESR unless much higher
values of capacitance are used (physically large). The ESR
of ceramic or fi lm capacitors was too low, which made
the capacitance/ESR zero frequency too high to maintain
phase margin in the regulator. Even with optimum capaci-
tors, loop phase margin was very low in previous designs
when output current was low. These problems led to a new
design technique for the LT1175 error amplifi er and internal
frequency compensation as shown in Figure 3.
A conventional regulator loop consists of error amplifi er
A1, driver transistor Q2 and power transistor Q1. Added
to this basic loop are secondary loops generated by Q3
and CF. A DC negative feedback current fed into the error
amplifi er through Q3 and RN causes overall loop current
gain to be very low at light load currents. This is not a
problem because very little gain is needed at light loads.
In addition to low gain, the parasitic pole frequency at Q2
base is extended by the DC feedback. The combination of
these two effects dramatically improves loop phase margin
at light loads and makes the loop tolerant of large ESR in
the output capacitor. With heavy loads, loop phase and
gain
are not nearly as troublesome and large negative feedback
could degrade regulation. The logarithmic behavior of the
base emitter voltage of Q1 reduces Q3 negative feedback
at heavy loads to prevent poor regulation.
In a conventional design, even with the nonlinear feedback,
poor loop phase margin would occur at medium to heavy
loads if the ESR of the output capacitor fell below 0.3Ω.
Minimum Dropout Voltage
Dropout voltage is the minimum voltage required between
input and output to maintain proper output regulation.
For older 3-terminal regulator designs, dropout voltage
was typically 1.5V to 3V. The LT1175 uses a saturating
power transistor design which gives much lower dropout
voltage, typically 100mV at light loads and 450mV at full
load. Special precautions were taken to ensure that this
technique does not cause quiescent supply current to be
high under light load conditions. When the regulator input
voltage is too low to maintain a regulated output, the pass
transistor is driven hard by the error amplifi er as it tries
to maintain regulation. The current drawn by the driver
transistor could be tens of milliamperes even with little or
no load on the output. This indeed was the case for older
IC designs that did not actively limit driver current when
the power transistor saturated. The LT1175 uses a new
antisaturation technique that prevents high driver current,
Figure 2. Active Output Pull-Down During Shutdown
COUT
≥ 0.1μF
–VIN
Q1*
s
d
SHDN GND
3V TO 5V
LT1175-5
SENSE
OUTPUT
1175 F02
ILIM4
ILIM2
VIN
* MOTOROLA J177
PINCH-OFF VOLTAGE MUST BE LESS THAN
POSITIVE LOGIC HIGH VOLTAGE
+
LT1175
11
1175ff
APPLICATIONS INFORMATION
–
+
LT1175
A1
3.8V
R1
ESR
OUTPUT
1175 F03
COUT
OUTPUT
GND
SENSE
R2
RC
0.5Ω
RLIM
RN
CF
20pF
+
PARASITIC
COLLECTOR
RESISTANCE
POWER
TRANSISTOR
NEGATIVE DC
FEEDBACK
AT LIGHT
LOADS
AC
FEEDFORWARD
PATH
CURRENT LIMIT
SENSE RESISTOR
Q2
Q1
VIN
LOAD
Q3
This condition can occur with ceramic or fi lm capacitors
which often have an ESR under 0.1Ω. With previous de-
signs, the user was forced to add a real resistor in series
with the capacitor to guarantee loop stability. The LT1175
uses a unique AC feedforward technique to eliminate
this problem. CF is a conventional feedforward capacitor
often used in regulators to cancel the pole formed by the
output capacitor. It would normally be connected from the
regulated output node to the feedback node at the R1/R2
junction or to an internal node on the amplifi er as shown.
In this case, however, the capacitor is connected to the
internal structure of the power transistor. RC is the unavoid-
able parasitic collector resistance of the power transistor.
Access to the node at the bottom of RC is available only
in monolithic structures where Kelvin connections can
be made to the NPN buried collector layer. The loop now
responds as if RC were in series with the output capacitor
and good loop stability is achieved even with extremely
low ESR in the output capacitor.
The end result of all this attention to loop stability is that
the output capacitor used with the LT1175 can range in
value from 0.1μF to hundreds of microfarads, with an ESR
from 0Ω to 10Ω. This range allows the use of ceramic,
solid tantalum, aluminum and fi lm capacitors over a wide
range of values.
The optimum output capacitor type for the LT1175 is
still solid tantalum, but there is considerable leeway in
selecting the exact unit. If large load current transients
are expected, larger capacitors with lower ESR may be
needed to control worst-case output variation during
transients. If transients are not an issue, the capacitor
can be chosen for small physical size, low price, etc.
Concerns about surge currents in tantalum capacitors are
not an issue for the output capacitor because the LT1175
limits inrush current to well below the level which can
cause capacitor damage. Surges caused by shorting the
regulator output are also not a problem because tantalum
Figure 3
LT1175
12
1175ff
APPLICATIONS INFORMATION
capacitors do not fail during a “shorting out” surge, only
during a “charge up” surge.
The output capacitor should be located within several
inches of the regulator. If remote sensing is used, the output
capacitor can be located at the remote sense node, but the
GND pin of the regulator should also be connected to the
remote site. The basic rule is to keep SENSE and GND pins
close to the output capacitor, regardless of where it is.
Operating at very large input-to-output differential volt-
ages (>15V) with load currents less than 5mA requires an
output capacitor with an ESR greater than 1Ω to prevent
low level output oscillations.
Input Capacitor
The LT1175 requires a separate input bypass capacitor
only if the regulator is located more than six inches from
the raw supply output capacitor. A 1μF or larger tantalum
capacitor is suggested for all applications, but if low ESR
capacitors such as ceramic or fi lm are used for the out-
put and input capacitors, the input capacitor should be
at least three times the value of the output capacitor. If a
solid tantalum or aluminum electrolytic output capacitor
is used, the input capacitor is very noncritical.
High Temperature Operation
The LT1175 is a micropower design with only 45μA qui-
escent current. This could make it perform poorly at high
temperatures (>125°C), where power transistor leakage
might exceed the output node loading current (5μA to
15μA). To avoid a condition where the output voltage
drifts uncontrolled high during a high temperature no-load
condition, the LT1175 has an active load which turns on
when the output is pulled above the nominal regulated
voltage. This load absorbs power transistor leakage and
maintains good regulation. There is one downside to this
feature, however. If the output is pulled high deliberately, as
it might be when the LT1175 is used as a backup to a slightly
higher output from a primary regulator, the LT1175 will act
as an unwanted load on the primary regulator. Because of
this, the active pull-down is deliberately “weak.” It can be
modeled as a 2k resistor in series with an internal clamp
voltage when the regulator output is being pulled high. If
a 4.8V output is pulled to 5V, for instance, the load on the
primary regulator would be (5V – 4.8V)/2kΩ = 100μA.
This also means that if the internal pass transistor leaks
50μA, the output voltage will be (50μA)(2kΩ) = 100mV
high. This condition will not occur under normal operating
conditions, but could occur immediately after an output
short circuit had overheated the chip.
Thermal Considerations
The LT1175 is available in a special 8-pin surface mount
package which has Pins 1 and 8 connected to the die attach
paddle. This reduces thermal resistance when Pins 1 and 8
are connected to expanded copper lands on the PC board.
Table 2 shows thermal resistance for various combinations
of copper lands and backside or internal planes. Table 2
also shows thermal resistance for the 5-pin DD surface
mount package and the 8-pin DIP and package.
Table 2. Package Thermal Resistance (°C/W)
LAND AREA DIP ST SO Q
Minimum 140 90 100 60
Minimum with
Backplane
110 70 80 50
1cm2 Top Plane with
Backplane
100 64 75 35
10cm2 Top Plane
with Backplane
80 50 60 27
To calculate die temperature, maximum power dissipation
or maximum input voltage, use the following formulas
with correct thermal resistance numbers from Table 2.
For through-hole TO-220 applications use θJA = 50°C/W
without a heat sink and θJA = 5°C/W + heat sink thermal
resistance when using a heat sink.
Die V V I
Maximum
JA IN OUT LOAD
Temp=T +
Aθ−
()()
Power Dissipation = TMAX −TA
JA
θ
=TMAX −TAA
JA LOAD
OUT
IV
θ
()
+
Maximum Input Voltage
for Thermal Considerations
LT1175
13
1175ff
APPLICATIONS INFORMATION
TA = Maximum ambient temperature
TMAX = Maximum LT1175 die temperature (125°C for
commercial and industrial grades)
θJA = LT1175 thermal resistance, junction to ambient
VIN = Maximum continuous input voltage at maximum
load current
ILOAD = Maximum load current
Example: LT1175S8 with ILOAD = 200mA, VOUT = 5V,
VIN = 7V, TA = 60°C. Maximum die temperature for the
LT1175S8 is 125°C. Thermal resistance from Table 2 is
found to be 80°C/W.
Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C
Maximum W
V
Power Dissipation = 125 – 60
80
125 – 60
=
=
()
+=
081
80 0 2 59
.
.
Maximum Continuous
Input Voltage
(for Thermal Considerations)
Output Voltage Reversal
The LT1175 is designed to tolerate an output voltage
reversal of up to 2V. Reversal might occur, for instance,
if the output was shorted to a positive 5V supply. This
would almost surely destroy IC devices connected to the
negative output. Reversal could also occur during start-
up if the positive supply came up fi rst and loads were
connected between the positive and negative supplies.
For these reasons, it is always good design practice to
add a reverse biased diode from each regulator output to
ground to limit output voltage reversal. The diode should
be rated to handle full negative load current for start-up
situations, or the short-circuit current of the positive supply
if supply-to-supply shorts must be tolerated.
Input Voltage Lower Than Output
Linear Technology’s positive low dropout regulators
LT1121 and LT1129, will not draw large currents if the
input voltage is less than the output. These devices use a
lateral PNP power transistor structure that has 40V emitter
base breakdown voltage. The LT1175, however, uses an
NPN power transistor structure that has a parasitic diode
between the input and output of the regulator. Reverse
voltages between input and output above 1V will damage
the regulator if large currents are allowed to fl ow. Simply
disconnecting the input source with the output held up
will not cause damage even though the input-to-output
voltage will become slightly reversed.
High Frequency Ripple Rejection
The LT1175 will sometimes be powered from switching
regulators that generate the unregulated or quasi-regulated
input voltage. This voltage will contain high frequency ripple
that must be rejected by the linear regulator. Special care
was taken with the LT1175 to maximize high frequency
ripple rejection, but as with any micropower design,
rejection is strongly affected by ripple frequency. The
graph in the Typical Performance Characteristics section
shows 60dB rejection at 1kHz, but only 15dB rejection at
100kHz for the 5V part. Photographs in Figures 4a and 4b
show actual output ripple waveforms with square wave
and triwave input ripple.
Figure 4a.
Figure 4b.
5μs/DIV
OUTPUT
20mV/DIV COUT = 1μF TANT
f = 50kHz
COUT = 4.7μF TANT
INPUT
RIPPLE
100mV/DIV
1175 F04a
2μs/DIV
OUTPUT
100mV/DIV COUT = 1μF TANT
f = 100kHz
COUT = 4.7μF TANT
INPUT
RIPPLE
100mV/DIV
1175 F04b
LT1175
14
1175ff
To estimate regulator output ripple under different
conditions, the following general comments should be
helpful:
1. Output ripple at high frequency is only weakly affected
by load current or output capacitor size for medium
to heavy loads. At very light loads (<10mA), higher
frequency ripple may be reduced by using larger output
capacitors.
2. A feedforward capacitor across the resistor divider used
with the adjustable part is effective in reducing ripple
only for output voltages greater than 5V and only for
frequencies less than 100kHz.
3. Input-to-output voltage differential has little effect on
ripple rejection until the regulator actually enters a
dropout condition of 0.2V to 0.6V.
If ripple rejection needs to be improved, an input fi lter can
be added. This fi lter can be a simple RC fi lter using a 1Ω
to 10Ω resistor. A 3.3Ω resistor for instance, combined
with a 0.3Ω ESR solid tantalum capacitor, will give an ad-
ditional 20dB ripple rejection. The size of the resistor will
be dictated by maximum load current. If the maximum
voltage drop allowable across the resistor is “VR,” and
maximum load current is ILOAD, R = VR/ILOAD. At light
loads, larger resistors and smaller capacitors can be used
to save space. At heavier loads an inductor may have to
be used in place of the resistor. The value of the inductor
can be calculated from:
LESR
f
FIL rr
=
()
()
210 20
π
/
ESR = Effective series resistance of fi lter capacitor. This
assumes that the capacitive reactance is small com-
pared to ESR, a reasonable assumption for solid
tantalum capacitors above 2.2μF and 50kHz.
f = Ripple frequency
rr = Ripple rejection ratio of fi lter in dB
Example: ESR = 1.2Ω, f = 100kHz, rr = –25dB.
LH
FIL =⎛
⎝⎞
⎠⎛
⎝⎞
⎠
=
−
12
63 10 10
34
525 20
.
./μ
Solid tantalum capacitors are suggested for the fi lter to
keep fi lter Q fairly low. This prevents unwanted ringing at
the resonant frequency of the fi lter and oscillation problems
with the fi lter/regulator combination.
APPLICATIONS INFORMATION
LT1175
15
1175ff
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
12 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
LT1175
16
1175ff
PACKAGE DESCRIPTION
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461)
Q(DD5) 0502
.028 – .038
(0.711 – 0.965)
TYP
.143 +.012
–.020
()
3.632 +0.305
–0.508
.067
(1.702)
BSC
.013 – .023
(0.330 – 0.584)
.095 – .115
(2.413 – 2.921)
.004 +.008
–.004
()
0.102 +0.203
–0.102
.050 ± .012
(1.270 ± 0.305)
.059
(1.499)
TYP
.045 – .055
(1.143 – 1.397)
.165 – .180
(4.191 – 4.572)
.330 – .370
(8.382 – 9.398)
.060
(1.524)
TYP
.390 – .415
(9.906 – 10.541)
15° TYP
.420
.350
.565
.090
.042
.067
RECOMMENDED SOLDER PAD LAYOUT
.325
.205
.080
.565
.090
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
.042
.067
.420
.276
.320
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
.300
(7.620)
.075
(1.905)
.183
(4.648)
.060
(1.524)
.060
(1.524)
.256
(6.502)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
LT1175
17
1175ff
PACKAGE DESCRIPTION
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.114 – .124
(2.90 – 3.15)
.248 – .264
(6.30 – 6.71)
.130 – .146
(3.30 – 3.71)
.264 – .287
(6.70 – 7.30)
.0905
(2.30)
BSC
.033 – .041
(0.84 – 1.04)
.181
(4.60)
BSC
.024 – .033
(0.60 – 0.84)
.071
(1.80)
MAX
10°
MAX
.012
(0.31)
MIN
.0008 – .0040
(0.0203 – 0.1016)
10° – 16°
.010 – .014
(0.25 – 0.36)
10° – 16°
RECOMMENDED SOLDER PAD LAYOUT
ST3 (SOT-233) 0502
.129 MAX
.059 MAX
.059 MAX
.181 MAX
.039 MAX
.248 BSC
.090
BSC
ST Package
3-Lead Plastic SOT-223
(Reference LTC DWG # 05-08-1630)
LT1175
18
1175ff
PACKAGE DESCRIPTION
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
T5 (TO-220) 0801
.028 – .038
(0.711 – 0.965)
.067
(1.70) .135 – .165
(3.429 – 4.191)
.700 – .728
(17.78 – 18.491)
.045 – .055
(1.143 – 1.397)
.095 – .115
(2.413 – 2.921)
.013 – .023
(0.330 – 0.584)
.620
(15.75)
TYP
.155 – .195*
(3.937 – 4.953)
.152 – .202
(3.861 – 5.131)
.260 – .320
(6.60 – 8.13)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.330 – .370
(8.382 – 9.398)
.460 – .500
(11.684 – 12.700)
.570 – .620
(14.478 – 15.748)
.230 – .270
(5.842 – 6.858)
BSC
SEATING PLANE
* MEASURED AT THE SEATING PLANE
LT1175
19
1175ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
E 11/09 Revised Typical Application.
Revised Pin Confi guration drawings and layout.
Updated Order Information.
VIN added and pin numbers added to Pin Functions.
Title added to Table 1.
Revised Figures 1, 2, 3, 4a and 4b.
Value correction in fi nal paragraph of the Output Capacitor section.
1
2
3
7
8
8, 9, 10, 12
11
F 7/10 Added MP-grade.
Replaced Note 2, renumbered all other notes and revised shutdown thresholds in the Electrical Characteristics section.
Updated Related Parts.
2–4
4, 5
20
(Revision history begins at Rev E)
LT1175
20
1175ff
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1995
LT 0710 REV F • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1121 150mA Positive Micropower Low Dropout Regulator with Shutdown SOT-223, 8-Lead SO, TO-92 Packages
LT1129 700mA Positive Micropower Low Dropout Regulator with Shutdown DD-Pak, SOT-223, 8-Lead SO, TO-220, 20-Lead TSSOP Packages
LT1185 3A Negative Low Dropout Regulator DD-Pak, TO-220 Packages
LT1521 300mA Positive Micropower Low Dropout Regulator with Shutdown SOT-223, 8-Lead SO, 8-Lead MSOP Packages
LT1529 3A Positive Micropower Low Dropout Regulator with Shutdown DD-Pak, TO-220 Packages
LT1964 200mA Negative Low Dropout Linear Regulator 5-Lead TSOT-23, 8-Lead (3mm × 3mm) DFN Packages
