MRF1508T1 - Motorola / Freescale Semiconductor

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MRF1508MOTOROLA RF DEVICE DATA

The RF MOSFET Line

RF Power Field Effect Transistor

N–Channel Enhancement–Mode Lateral MOSFETs

The MRF1508 is designed for broadband commercial and industrial

applications at frequencies to 520 MHz. The high gain and broadband

performance of this device makes it ideal for large–signal, common source

amplifier applications in 12.5 volt mobile FM equipment.

•Specified Performance @ 520 MHz, 12.5 Volts

Output Power — 8 Watts

Power Gain — 14 dB

Efficiency — 60%

•Characterized with Series Equivalent Large–Signal

Impedance Parameters

•Excellent Thermal Stability

•Capable of Handling 20:1 VSWR, @ 15.5 Vdc,

520 MHz, 2 dB Overdrive

•RF Power Plastic Surface Mount Package

•Broadband UHF/VHF Demonstration Amplifier

Information Available Upon Request

•Available in Tape and Reel by Adding T1 Suffix to

Part Number. T1 Suffix = 1,000 Units per 12 mm, 7 Inch Reel.

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain–Source Voltage VDSS 40 Vdc

Gate–Source Voltage VGS ±20 Vdc

Drain Current — Continuous ID4 Adc

Total Device Dissipation @ TC = 25°C (1)

Derate above 25°CPD62.5

0.50 Watts

W/°C

Storage Temperature Range Tstg –65 to +150 °C

Operating Junction Temperature TJ150 °C

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Thermal Resistance, Junction to Case RθJC 2°C/W

(1) Calculated based on the formula PD =

NOTE – CAUTION – MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and

packaging MOS devices should be observed.

Order this document

by MRF1508/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MRF1508

(Cancelled)

MRF1508T1

8 W, 520 MHz, 12.5 V

LATERAL N–CHANNEL

BROADBAND

RF POWER MOSFET

CASE 466–02, STYLE 1

(PLD 1.5)

PLASTIC

 Motorola, Inc. 1998

TJ–TC

RθJC

REV 1

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ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Zero Gate Voltage Drain Current

(VDS = 40 Vdc, VGS = 0) IDSS — — 10 µAdc

Gate–Source Leakage Current

(VGS = 20 Vdc, VDS = 0) IGSS — — 1 µAdc

ON CHARACTERISTICS

Gate Threshold Voltage

(VDS = 10 Vdc, ID = 100 µA) VGS(th) 2.4 3 — Vdc

Drain–Source On–V oltage

(VGS = 10 Vdc, ID = 2 Adc) VDS(on) 0.3 0.5 — Vdc

Forward T ransconductance

(VDS = 10 Vdc, ID = 2 Adc) gfs 1.3 1.75 — S

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz) Ciss — 47 — pF

Output Capacitance

(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz) Coss — 35 — pF

Reverse T ransfer Capacitance

(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz) Crss — 4.1 — pF

FUNCTIONAL TESTS (In Motorola Test Fixture)

Common–Source Amplifier Power Gain

(VDD = 12.5 Vdc, Pout = 8 W atts, I DQ = 150 mA, f = 520 MHz) Gps 12 14 — dB

Drain Efficiency

(VDD = 12.5 Vdc, Pout = 8 W atts, I DQ = 150 mA, f = 520 MHz) η55 60 — %

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Figure 1. 500 – 520 MHz Broadband Test Circuit

B1 Fair Rite Products Long Ferrite Bead

C1, C5 10 µF, 50 V Electrolytic Capacitor

C2, C4 0.1 µF, 100 mil Chip Capacitor

C3, C6, C7, C8 130 pF, 100 mil Chip Capacitor

C9 0.8–8 pF, Variable Capacitor, Gigatrim

C10 0.8–18 pF, Variable Capacitor, Johanson

C11 16 pF, 100 mil Chip Capacitor

C12 0.8–18 pF, Variable Capacitor, Johanson

C13 0.8–8 pF, Variable Capacitor, Gigatrim

L1 4 Turns, #20 AWG Enamel Coil, 0.1″ID

N1, N2 T ype–N Flange Mount Connector

R1 1.1 MΩ, 1/4 W Carbon Resistor

R2 1.0 kΩ, 0.1 W Chip Resistor

R3 1 kΩ, 1/4 W Carbon Resistor

VGG VDD

C1 R1

C2 C3 C5C4 +

INPUT

OUTPUT

Z1 Z2 Z3 Z4

C7 C9

DUT

C11

Z10 Z11

Z5 Z6

Z9 N2

Z1, Z13 0.290″ x 0.081″ Microstrip

Z2 0.070″ x 0.217″ Microstrip

Z3 2.950″ x 0.217″ Microstrip

Z4 0.150″ x 0.217″ Microstrip

Z5 0.250″ x 0.217″ Microstrip

Z6 0.250″ x 0.0073″ Microstrip AIO2

Z7 0.250″ x 0.0073″ Microstrip AIO2

Z8 0.050″ x 0.217″ Microstrip

Z9 0.100″ x 0.217″ Microstrip

Z10 0.150″ x 0.217″ Microstrip

Z11 1.500″ x 0.217″ Microstrip

Z12 1.550″ x 0.217″ Microstrip

Board Glass Teflon, 31 mils, 2 oz. Copper

C13

Z12 Z13

C10

C12

TYPICAL CHARACTERISTICS

Pout, OUTPUT POWER (WATTS)

IRL, INPUT RETURN LOSS (dB)

010

6120

14842

510 MHz

520 MHz

500 MHz

Figure 2. Output Power versus Input Power

Pin, INPUT POWER (W ATTS)

0.35

Figure 3. Input Return Loss

versus Output Power

0.15

Pout, OUTPUT POWER (WATTS)

0.250.05 0.45

520 MHz 510 MHz

500 MHz

0.400.20 0.300.10

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TYPICAL CHARACTERISTICS

10 4

Pout, OUTPUT POWER (WATTS)

014

Eff, DRAIN EFFICIENCY (%)

6210

500 MHz

520 MHz

510 MHz

500 MHz

Eff, DRAIN EFFICIENCY (%)

Figure 4. Gain versus Output Power

Pout, OUTPUT POWER (WATTS)

10 8

Figure 5. Drain Efficiency versus Output Power

412

GAIN (dB)

Figure 6. Output Power versus Biasing Current

IDQ, BIASING CURRENT (mA)

Figure 7. Drain Efficiency versus

Biasing Current

IDQ, BIASING CURRENT (mA)

700

Figure 8. Output Power versus Supply Voltage

8VDD, SUPPLY VOLTAGE (VOL TS)

215

Figure 9. Drain Efficiency versus Supply Voltage

VDD, SUPPLY VOLTAGE (VOL TS)

30 12

11 8

40 400 5000

600 700 800

200

Pout, OUTPUT POWER (WATTS)

100 200 300 800400 500 600

VDD = 12.5 V

Pin = 27 dBm

Pout, OUTPUT POWER (WATTS)

9121310 14 16

IDQ = 150 mA

Pin = 27 dBm

91011 1413 16

1062

520 MHz 510 MHz

500 MHz

510 MHz

520 MHz

VDD = 12.5 V

Pin = 27 dBm

100 300

520 MHz

500 MHz 510 MHz

Eff, DRAIN EFFICIENCY (%)

500 MHz 510 MHz

520 MHz

IDQ = 150 mA

Pin = 27 dBm

510 MHz

520 MHz

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Figure 10. 400 – 470 MHz Broadband Test Circuit

B1 Fair Rite Products Long Ferrite Bead

C1, C5 10 µF, 50 V Electrolytic Capacitor

C2, C4 0.1 µF, 100 mil Chip Capacitor

C3, C6, C7, C8 130 pF, 100 mil Chip Capacitor

C9 10 pF, 100 mil Chip Capacitor

C10 0.8–8 pF, Variable Capacitor, Gigatrim

C11 47 pF, 100 mil Chip Capacitor

C12 16 pF, 100 mil Chip Capacitor

C13 6.2 pF, 100 mil Chip Capacitor

C14 5.1 pF, 100 mil Chip Capacitor

L1 4 Turns, #20 AWG Enamel Coil, 0.1″ID

N1, N2 T ype–N Flange Mount Connector

R1 1.1 MΩ, 1/4 W Carbon Resistor

R2 1.0 kΩ, 0.1 W Chip Resistor

VGG VDD

C1 R1

C2 C3 C5C4 +

INPUT

OUTPUT

Z1 Z2 Z3 Z4

C7 C10

DUT

Z9 Z10 Z11

Z5 Z6

R3 1 kΩ, 1/4 W Carbon Resistor

Z1, Z13 0.290″ x 0.081″ Microstrip

Z2 0.150″ x 0.217″ Microstrip

Z3 2.650″ x 0.217″ Microstrip

Z4 0.200″ x 0.217″ Microstrip

Z5 0.300″ x 0.217″ Microstrip

Z6 0.050″ x 0.217″ Microstrip

Z7, Z8 0.313″ x 0.160″ Microstrip

Z9 0.200″ x 0.217″ Microstrip

Z10 0.800″ x 0.217″ Microstrip

Z11 2.400″ x 0.217″ Microstrip

Z12 0.100″ x 0.217″ Microstrip

Board Glass Teflon, 31 mils, 2 oz. Copper

Insert Glass Teflon, 31 mils, 2 oz. Copper

C14

Z12 Z13

C11

C13

C12

TYPICAL CHARACTERISTICS

Pout, OUTPUT POWER (WATTS)

IRL, INPUT RETURN LOSS (dB)

–4

–16

–20 10

–12

6120

–8

14842

Figure 11. Output Power versus Input Power

Pin, INPUT POWER (MILLIW ATTS)

Figure 12. Input Return Loss

versus Output Power

600

Pout, OUTPUT POWER (WATTS)

0 200 1000

470 MHz 400 MHz

440 MHz

800400

470 MHz

400 MHz

440 MHz

–6

–18

–14

–10

–2

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TYPICAL CHARACTERISTICS

400 MHz

Pout, OUTPUT POWER (WATTS)

014

Eff, DRAIN EFFICIENCY (%)

6210

Eff, DRAIN EFFICIENCY (%)

Figure 13. Gain versus Output Power

Pout, OUTPUT POWER (WATTS)

Figure 14. Drain Efficiency versus Output Power

412

GAIN (dB)

Figure 15. Output Power versus Biasing Current

IDQ, BIASING CURRENT (mA)

Figure 16. Drain Efficiency versus

Biasing Current

IDQ, BIASING CURRENT (mA)

700

Figure 17. Output Power versus Supply Voltage

6VDD, SUPPLY VOLTAGE (VOL TS)

214

Figure 18. Drain Efficiency versus Supply Voltage

VDD, SUPPLY VOLTAGE (VOL TS)

10 13

10 400 5000

600 700 800

200

Pout, OUTPUT POWER (WATTS)

100 200 300 800400 500 600

VDD = 12.5 V

Pin = 27 dBm

Pout, OUTPUT POWER (WATTS)

7101181216

IDQ = 150 mA

Pin = 27 dBm

810121416

1062

VDD = 12.5 V

Pin = 27 dBm

100 300

Eff, DRAIN EFFICIENCY (%)

470 MHz 440 MHz 400 MHz

470 MHz

440 MHz

470 MHz

400 MHz 470 MHz

400 MHz

440 MHz

1513

440 MHz

470 MHz

400 MHz

IDQ = 150 mA

Pin = 27 dBm

7911

470 MHz

400 MHz

440 MHz

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Figure 19. 136 – 175 MHz Broadband Test Circuit

B1 Fair Rite Products Long Ferrite Bead

C1, C5 10 µF, 50 V Electrolytic Capacitor

C2, C4 0.1 µF, 100 mil Chip Capacitor

C3, C6, C7, C8 130 pF, 100 mil Chip Capacitor

C9 82 pF, 100 mil Chip Capacitor

C10 6.2 pF, 100 mil Chip Capacitor

C11 30 pF, 100 mil Chip Capacitor

C12 75 pF, 100 mil Chip Capacitor

C13 39 pF, 100 mil Chip Capacitor

L1 4 Turns, #20 AWG Enamel Coil, 0.1″ID

L2 17.5 nH Air Core Inductor, Coilcraft A06T

L3 22 nH Air Core Inductor, Coilcraft A07T

L4 18.5 nH Air Core Inductor, Coilcraft A05T

L5 5 nH Air Core Inductor, Coilcraft A02T

N1, N2 T ype–N Flange Mount Connector

R1 1.1 MΩ, 1/4 W Carbon Resistor

R2 1.0 kΩ, 0.1 W Chip Resistor

VGG VDD

C1 R1

C2 C3 C5C4 +

INPUT

OUTPUT

Z1 Z2 Z3 Z4

C7 C10

C11

DUT

Z10 Z11

Z5 Z6

R3 50 Ω, 1/4 W Carbon Resistor

R4 20 Ω, 0.1 W Chip Resistor

Z1 0.200″ x 0.081″ Microstrip

Z2 0.050″ x 0.081″ Microstrip

Z3 0.450″ x 0.081″ Microstrip

Z4 0.050″ x 0.081″ Microstrip

Z5 0.550″ x 0.081″ Microstrip

Z6 0.350″ x 0.081″ Microstrip

Z7 1.150″ x 0.081″ Microstrip

Z8 0.250″ x 0.081″ Microstrip

Z9 0.350″ x 0.081″ Microstrip

Z10 0.500″ x 0.081″ Microstrip

Z11 1.150″ x 0.081″ Microstrip

Z12 1.450″ x 0.081″ Microstrip

Z13 0.050″ x 0.081″ Microstrip

Z14 0.200″ x 0.081″ Microstrip

Board Glass Teflon, 31 mils, 2 oz. Copper

C13

Z13 Z14

C12

Z9Z7 Z8

Z12

L3 L4

TYPICAL CHARACTERISTICS

Pout, OUTPUT POWER (WATTS)

IRL, INPUT RETURN LOSS (dB)

–4

–16

–20 10

–12

6120

–8

14842

Figure 20. Output Power versus Input Power

Pin, INPUT POWER (MILLIW ATTS)

Figure 21. Input Return Loss

versus Output Power

600

Pout, OUTPUT POWER (WATTS)

0 200 1000

136 MHz

175 MHz

155 MHz

800400

–6

–18

–14

–10

–2

155 MHz

136 MHz

175 MHz

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TYPICAL CHARACTERISTICS

10 4

Pout, OUTPUT POWER (WATTS)

014

Eff, DRAIN EFFICIENCY (%)

6210

Eff, DRAIN EFFICIENCY (%)

Figure 22. Gain versus Output Power

Pout, OUTPUT POWER (WATTS)

Figure 23. Drain Efficiency versus Output Power

412

GAIN (dB)

Figure 24. Output Power versus Biasing Current

IDQ, BIASING CURRENT (mA)

Figure 25. Drain Efficiency versus

Biasing Current

IDQ, BIASING CURRENT (mA)

700

Figure 26. Output Power versus Supply Voltage

6VDD, SUPPLY VOLTAGE (VOL TS)

214

Figure 27. Drain Efficiency versus Supply Voltage

VDD, SUPPLY VOLTAGE (VOL TS)

10 10

10 400 5000

600 700 800

200

Pout, OUTPUT POWER (WATTS)

100 200 300 800400 500 600

VDD = 12.5 V

Pin = 27 dBm

Pout, OUTPUT POWER (WATTS)

7101181216

IDQ = 150 mA

Pin = 27 dBm

789 1211 16

1062

VDD = 12.5 V

Pin = 27 dBm

100 300

Eff, DRAIN EFFICIENCY (%)

IDQ = 150 mA

Pin = 27 dBm

155 MHz

136 MHz

175 MHz

155 MHz

175 MHz

136 MHz

155 MHz

136 MHz

175 MHz

155 MHz

136 MHz

1513

155 MHz

175 MHz

136 MHz

13 15

175 MHz

155 MHz

136 MHz

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MRF1508MOTOROLA RF DEVICE DATA

MHz Zin

ΩZOL*

Ω

135 11.7 – j4.4 8.7 – j0.2

Zin = Conjugate of source impedance

with parallel 20 Ω resistor and

82 pF capacitor in series with gate.

(See Figure 19).

ZOL* = Conjugate of the load impedance

at given output power, voltage,

frequency, and ηD > 50 %.

VDD = 12.5 V, IDQ = 150 mA, Pout = 8 W

155 11.8 – j6.8 7.2 – j3.8

Note: ZOL* was chosen based on tradeoffs between gain, drain efficiency , and device stability.

Zin

ZOL*

Figure 28. Series Equivalent Input and Output Impedance

175 11.3 – j8.8 6.3 – j7.7

Zo = 10 Ω

f = 500 MHz

520

MHz Zin

ΩZOL*

Ω

400 2.5 – j3.9 7.1 – j0.1

Zin = Conjugate of source impedance

with parallel 20 Ω resistor and

82 pF capacitor in series with gate.

(See Figure 10).

ZOL* = Conjugate of the load impedance

at given output power, voltage,

frequency, and ηD > 50 %.

VDD = 12.5 V, IDQ = 150 mA, Pout = 8 W

440 3.0 – j4.1 6.8 – j2.3

470 2.4 – j4.3 6.8 – j4.2

MHz Zin

ΩZOL*

Ω

500 2.0 – j4.8 3.5 – j3.5

Zin = Conjugate of source impedance

with parallel 20 Ω resistor and

82 pF capacitor in series with gate.

(See Figure 1).

ZOL* = Conjugate of the load impedance

at given output power, voltage,

frequency, and ηD > 50 %.

VDD = 12.5 V, IDQ = 150 mA, Pout = 8 W

510 2.4 – j3.4 3.5 – j2.7

520 2.2 – j3.8 3.5 – j2.6

ZOL*Zin

ZOL*

f = 500 MHz

520

470

400

Zin

470

f = 400 MHz

f = 135 MHz

175

f = 135 MHz

175

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Table 1. Common Source Scattering Parameters (VDS = 12.5 Vdc, IDQ = 150 mA)

S11 S21 S12 S22

MHz |S11|φ|S21|φ|S12|φ|S22|φ

50 0.770 –136 16.04 101 0.040 12 0.670 –137

100 0.760 –154 8.15 86 0.040 –3 0.680 –153

150 0.770 –160 5.30 77 0.040 –11 0.700 –158

200 0.780 –163 3.83 70 0.040 –18 0.720 –160

250 0.800 –165 2.91 64 0.040 –23 0.750 –161

300 0.820 –166 2.29 58 0.030 –27 0.780 –162

350 0.840 –167 1.87 54 0.030 –31 0.800 –163

400 0.850 –168 1.54 50 0.030 –35 0.820 –164

450 0.860 –168 1.29 47 0.030 –38 0.840 –165

500 0.870 –169 1.09 44 0.030 –39 0.850 –166

550 0.880 –170 0.96 41 0.020 –42 0.870 –166

600 0.890 –170 0.83 39 0.020 –43 0.880 –167

650 0.900 –171 0.72 37 0.020 –44 0.890 –168

700 0.910 –171 0.65 35 0.020 –44 0.890 –168

750 0.910 –172 0.59 32 0.020 –45 0.900 –169

800 0.920 –172 0.52 30 0.020 –48 0.910 –169

850 0.930 –173 0.46 29 0.020 –50 0.910 –170

900 0.930 –173 0.42 28 0.010 –51 0.920 –170

950 0.930 –173 0.38 26 0.010 –54 0.920 –170

1000 0.930 –173 0.35 24 0.010 –52 0.920 –171

1050 0.930 –174 0.31 23 0.010 –51 0.930 –171

1100 0.930 –174 0.28 22 0.010 –45 0.930 –171

1150 0.940 –174 0.26 21 0.010 –53 0.930 –172

1200 0.940 –174 0.24 21 0.010 –60 0.930 –172

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Table 2. Common Source Scattering Parameters (VDS = 12.5 Vdc, IDQ = 800 mA)

S11 S21 S12 S22

MHz |S11|φ|S21|φ|S12|φ|S22|φ

50 0.840 –152 19.13 99 0.020 10 0.740 –158

100 0.820 –165 9.60 88 0.020 0 0.760 –167

150 0.820 –169 6.33 82 0.020 –6 0.760 –170

200 0.830 –171 4.68 77 0.020 –10 0.770 –170

250 0.830 –172 3.64 73 0.020 –13 0.780 –171

300 0.840 –172 2.94 69 0.020 –15 0.790 –171

350 0.850 –173 2.48 66 0.020 –18 0.800 –171

400 0.850 –173 2.09 62 0.020 –21 0.810 –171

450 0.860 –173 1.80 60 0.020 –22 0.820 –170

500 0.870 –174 1.56 57 0.020 –24 0.830 –171

550 0.870 –174 1.39 54 0.020 –25 0.840 –171

600 0.880 –174 1.23 52 0.020 –27 0.850 –171

650 0.880 –174 1.09 50 0.020 –26 0.860 –171

700 0.890 –174 1.00 48 0.010 –28 0.860 –171

750 0.900 –174 0.91 45 0.010 –29 0.870 –172

800 0.900 –174 0.82 43 0.010 –31 0.870 –172

850 0.910 –175 0.74 41 0.010 –32 0.880 –172

900 0.910 –175 0.68 40 0.010 –32 0.880 –172

950 0.910 –175 0.62 37 0.010 –36 0.880 –172

1000 0.910 –175 0.56 36 0.010 –33 0.880 –173

1050 0.920 –175 0.51 34 0.010 –35 0.880 –172

1100 0.920 –175 0.46 33 0.010 –25 0.890 –173

1150 0.920 –175 0.43 33 0.010 –34 0.880 –173

1200 0.920 –175 0.39 32 0.010 –40 0.880 –173

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Table 3. Common Source Scattering Parameters (VDS = 12.5 Vdc, IDQ = 1.5 A)

S11 S21 S12 S22

MHz |S11|φ|S21|φ|S12|φ|S22|φ

50 0.860 –152 18.90 100 0.020 11 0.740 –160

100 0.830 –165 9.46 89 0.020 1 0.770 –168

150 0.830 –169 6.24 83 0.020 –4 0.770 –171

200 0.840 –171 4.61 78 0.020 –9 0.780 –171

250 0.840 –172 3.59 74 0.020 –12 0.790 –171

300 0.840 –173 2.91 70 0.020 –15 0.800 –171

350 0.850 –173 2.45 67 0.020 –17 0.810 –171

400 0.860 –174 2.07 63 0.020 –20 0.820 –171

450 0.860 –174 1.78 60 0.020 –21 0.820 –171

500 0.870 –174 1.55 58 0.020 –22 0.840 –171

550 0.880 –174 1.39 55 0.020 –24 0.840 –171

600 0.880 –174 1.23 53 0.020 –24 0.850 –171

650 0.890 –175 1.09 51 0.010 –24 0.860 –172

700 0.890 –175 1.00 49 0.010 –25 0.860 –172

750 0.900 –175 0.91 46 0.010 –27 0.870 –172

800 0.900 –175 0.82 43 0.010 –28 0.870 –172

850 0.910 –175 0.74 42 0.010 –31 0.870 –173

900 0.910 –175 0.68 40 0.010 –30 0.870 –173

950 0.910 –175 0.62 38 0.010 –32 0.870 –173

1000 0.910 –175 0.56 36 0.010 –31 0.860 –173

1050 0.920 –175 0.51 35 0.010 –29 0.860 –173

1100 0.920 –175 0.46 34 0.010 –22 0.860 –173

1150 0.920 –175 0.43 34 0.010 –30 0.850 –173

1200 0.920 –175 0.39 33 0.010 –35 0.850 –172

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APPLICATIONS INFORMATION

DESIGN CONSIDERATIONS

The MRF1508 is a common–source, RF power, N–Channel

enhancement mode, Lateral Metal–Oxide Semiconductor

Field–Effect T ransistor (MOSFET). Motorola Application Note

AN21 1A, “FETs in Theory and Practice”, is suggested reading

for those not familiar with the construction and characteristics

of FETs.

This surface mount packaged device was designed primari-

ly for VHF and UHF portable power amplifier applications.

Manufacturability is improved by utilizing the tape and reel

capability for fully automated pick and placement of parts.

However, care should be taken in the design process to insure

proper heat sinking of the device.

The major advantages of Lateral RF power MOSFETs

include high gain, simple bias systems, relative immunity from

thermal runaway, and the ability to withstand severely

mismatched loads without suffering damage.

MOSFET CAPACITANCES

The physical structure of a MOSFET results in capacitors

between all three terminals. The metal oxide gate structure

determines the capacitors from gate–to–drain (Cgd), and

gate–to–source (Cgs). The PN junction formed during fabrica-

tion of the RF MOSFET results in a junction capacitance from

drain–to–source (Cds). These capacitances are characterized

as input (Ciss), output (Coss) and reverse transfer (Crss)

capacitances on data sheets. The relationships between the

inter–terminal capacitances and those given on data sheets

are shown below. The Ciss can be specified in two ways:

1. Drain shorted to source and positive voltage at the gate.

2. Positive voltage of the drain in respect to source and

zero volts at the gate.

In the latter case, the numbers are lower . However, neither

method represents the actual operating conditions in RF

applications.

Drain

Cds

Source

Gate

Cgd

Cgs

Ciss = Cgd + Cgs

Coss = Cgd + Cds

Crss = Cgd

DRAIN CHARACTERISTICS

One critical figure of merit for a FET is its static resistance

in the full–on condition. This on–resistance, RDS(on), occurs in

the linear region of the output characteristic and is specified

at a specific gate–source voltage and drain current. The

drain–source voltage under these conditions is termed

VDS(on). For MOSFETs, VDS(on) has a positive temperature

coefficient at high temperatures because it contributes to the

power dissipation within the device.

BVDSS values for this device are higher than normally

required for typical applications. Measurement of BVDSS is not

recommended and may result in possible damage to the

device.

GATE CHARACTERISTICS

The gate of the RF MOSFET is a polysilicon material, and

is electrically isolated from the source by a layer of oxide. The

DC input resistance is very high – on the order of 109 Ω —

resulting in a leakage current of a few nanoamperes.

Gate control is achieved by applying a positive voltage to

the gate greater than the gate–to–source threshold voltage,

VGS(th).

Gate Voltage Rating — Never exceed the gate voltage

rating. Exceeding the rated VGS can result in permanent

damage to the oxide layer in the gate region.

Gate Termination — The gates of these devices are

essentially capacitors. Circuits that leave the gate open–cir-

cuited or floating should be avoided. These conditions can

result in turn–on of the devices due to voltage build–up on the

input capacitor due to leakage currents or pickup.

Gate Protection — These devices do not have an internal

monolithic zener diode from gate–to–source. If gate protec-

tion is required, an external zener diode is recommended.

Using a resistor to keep the gate–to–source impedance low

also helps dampen transients and serves another important

function. V oltage transients on the drain can be coupled to the

gate through the parasitic gate–drain capacitance. If the

gate–to–source impedance and the rate of voltage change on

the drain are both high, then the signal coupled to the gate may

be large enough to exceed the gate–threshold voltage and

turn the device on.

DC BIAS

Since the MRF1508 is an enhancement mode FET, drain

current flows only when the gate is at a higher potential than

the source. RF power FET s operate optimally with a quiescent

drain current (IDQ), whose value is application dependent. The

MRF1508 was characterized at IDQ = 150 mA, which is the

suggested value of bias current for typical applications. For

special applications such as linear amplification, IDQ may have

to be selected to optimize the critical parameters.

The gate is a dc open circuit and draws no current.

Therefore, the gate bias circuit may generally be just a simple

resistive divider network. Some special applications may

require a more elaborate bias system.

GAIN CONTROL

Power output of the MRF1508 may be controlled to some

degree with a low power dc control signal applied to the gate,

thus facilitating applications such as manual gain control,

ALC/AGC and modulation systems. This characteristic is very

dependent on frequency and load line.

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MRF1508

14 MOTOROLA RF DEVICE DATA

MOUNTING

The specified maximum thermal resistance of 2°C/W

assumes a majority of the 0.065″ x 0.180″ source contact on

the back side of the package is in good contact with an

appropriate heat sink. As with all RF power devices, the goal

of the thermal design should be to minimize the temperature

at the back side of the package. Refer to Motorola

Application Note AN4005/D, “Thermal Management and

Mounting Method for the PLD–1.5 RF Power Surface Mount

Package,” and Engineering Bulletin EB209/D, “Mounting

Method for RF Power Leadless Surface Mount T ransistor” for

additional information.

AMPLIFIER DESIGN

Impedance matching networks similar to those used with

bipolar transistors are suitable for the MRF1508. For

examples see Motorola Application Note AN721, “Impedance

Matching Networks Applied to RF Power Transistors.”

Large–signal impedances are provided, and will yield a good

first pass approximation.

Since RF power MOSFETs are triode devices, they are not

unilateral. This coupled with the very high gain of the

MRF1508 yields a device capable of self oscillation. Stability

may be achieved by techniques such as drain loading, input

shunt resistive loading, or output to input feedback. The RF

test fixture implements a parallel resistor and capacitor in

series with the gate, and has a load line selected for a higher

efficiency, lower gain, and more stable operating region.

Two–port stability analysis with the MRF1508

S–parameters provides a useful tool for selection of loading or

feedback circuitry to assure stable operation. See Motorola

Application Note AN215A, “RF Small–Signal Design Using

Two–Port Parameters” for a discussion of two port network

theory and stability.

MRF1508MOTOROLA RF DEVICE DATA

PACKAGE DIMENSIONS

CASE 466–02

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH

3. RESIN BLEED/FLASH ALLOWABLE IN ZONE V, W,

AND X.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.255 0.265 6.48 6.73

B0.225 0.235 5.72 5.97

C0.065 0.072 1.65 1.83

D0.130 0.150 3.30 3.81

E0.021 0.026 0.53 0.66

F0.026 0.044 0.66 1.12

G0.050 0.070 1.27 1.78

H0.045 0.063 1.14 1.60

K0.273 0.285 6.93 7.24

L0.245 0.255 6.22 6.48

N0.230 0.240 5.84 6.10

P0.000 0.008 0.00 0.20

Q0.055 0.063 1.40 1.60

R0.200 0.210 5.08 5.33

S0.006 0.012 0.15 0.31

U0.006 0.012 0.15 0.31

ZONE V 0.000 0.021 0.00 0.53

ZONE W 0.000 0.010 0.00 0.25

ZONE X 0.000 0.010 0.00 0.25

STYLE 1:

PIN 1. DRAIN

2. GATE

3. SOURCE

4. SOURCE

ÉÉÉÉ

ZONE X

ZONE W

0.89 (0.035) X 45 5

10 DRAFT

ZONE V

ÉÉÉ

RESIN BLEED/FLASH ALLOWABLE

J0.160 0.180 4.06 4.57

MRF1508

16 MOTOROLA RF DEVICE DATA

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”

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