PEB 2465
Four Channel Codec Filter
Never stop thinking.
Transceivers
Data Sheet, V2.3, Feb. 2000
Edition 2000-02-08
Published by Infineon Technologies AG,
St.-Marti n -Str asse 53,
D-81541 München, Germany
© Infineon Technologies AG 2/25/00.
All Rights R eserved.
Attentio n pl ease!
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characteristics.
Terms of delivery and rights to technical change reserved.
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circuits, des c ript ions and charts s ta te d herein.
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Information
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list).
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Transceivers
PEB 2465
Four Channel Codec Filter
Data Sheet, V2.3, Feb. 2000
Never stop thinking.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEB 2465
Revision History: 2000-02-08 DS 3
Previous Versio n: 02.97
Page Subjects (major changes since last revision)
SICOFI-4
PEB 2465
Table of Contents Page
Data Sheet 5 2000-02-08
1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 SICOFI-4 Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Programming the SICOFI-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Types of Monitor Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Storage of Programming Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 SICOFI-4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 SOP – Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 XOP – Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 COP – Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.4 SOP – Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.5 XOP – Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.6 COP – Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.7 Example for a Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.1 CR1 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.2 CR2 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.3 CR3 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.4 CR4 Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 How to Program the Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.6 XOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6.1 XR1 Extended Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6.2 XR2 Extended Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6.3 XR3 Extended Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6.4 XR4 Extended Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4 SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Data-downstream C/I Channel Byte Format (receive) . . . . . . . . . . . . . . . . 46
4.3 Data Upstream C/I Channel Byte Format (transmit) . . . . . . . . . . . . . . . . . 46
5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1 RESET (Basic setting mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1 Impedance Matching Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SICOFI-4
PEB 2465
Table of Contents Page
Data Sheet 6 2000-02-08
6.2 Transhybrid Balancing (TH) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 Filters for Frequency Response Correction . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4 Amplification/Attenuation-Filters AX1, AX2, AR1, AR2 . . . . . . . . . . . . . . . 54
6.5 Amplification/Attenuation Receive (AR1, AR2)-Filter . . . . . . . . . . . . . . . . . 54
6.6 Amplification/Attenuation Transmit (AX1, AX2)-Filter . . . . . . . . . . . . . . . . 54
7 QSICOS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.1 QSICOS Supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.2 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.3 Out-of-Band Signals at Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4 Out-of-Band Signals at Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.5 Out of Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . . . 64
8.6 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.7 Gain Tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.8 Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.8.1 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . . 67
8.8.2 Total Distortion Measured with Noise According to CCITT . . . . . . . . . . 68
8.9 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.10 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.3 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.4 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.5 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.5.1 IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.5.2 4-MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.5.3 2-MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.6 IOM-2 Command/Indication Interface Timing . . . . . . . . . . . . . . . . . . . . . . 77
9.6.1 4-MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.6.2 2-MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.7 Detector Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1 IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.1 Monitor Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.2 Monitor Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.1.3 State Diagram of the SICOFI-4 Monitor Transmitter . . . . . . . . . . . . . . . 82
10.1.4 State Diagram of the SICOFI-4 Monitor Receiver . . . . . . . . . . . . . . . . . 83
10.1.5 Monitor Channel Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SICOFI-4
PEB 2465
Data Sheet 7 2000-02-08
10.2 IOM-2 Interface Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.3.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.3.2 The TAP-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.3.3 Level Metering Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.3.4 Using the Level Metering Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.4 Programming the SICOFI-4 Tone Generators . . . . . . . . . . . . . . . . . . . . . . 96
11 Proposed Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12 Board Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2 Filter Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SICOFI-4
PEB 2465
List of Figures Page
Data Sheet 8 2000-02-08
Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2 SICOFI-4 Signal Flow Graph (for either channel) . . . . . . . . . . . . . . . . 16
Figure 3 SICOFI-4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4 IOM-2 Interface Timing for 16 Voice Channels (per 8 kHz frame). . . . 19
Figure 5 IOM-2 Interface Timing (DCL=4096 kHz, MODE=1, per 8 kHz frame) 20
Figure 6 IOM-2 Interface Timing (DCL = 2048 kHz, MODE = 0) . . . . . . . . . . . . 21
Figure 7 CUT OFFs and Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9 SLICs with Multiplexed Loop/Ground Key Detect . . . . . . . . . . . . . . . . 43
Figure 10 Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 11 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12 QSICOS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13 Receive: Reference Frequency 1 kHz, Input Signal Level 0 dBm0 . . . 59
Figure 14 Transmit: Reference Frequency 1 kHz, Input Signal Level 0 dBm0 . . 59
Figure 15 Group Delay Distortion Transmit: Input Signal Level 0 dBm0 . . . . . . . 60
Figure 16 Group Delay Distortion Receive: Input Signal Level 0 dBm0. . . . . . . . 61
Figure 17 µ-Law, Transmit: measured with sine wave f = 1014 Hz. . . . . . . . . . . 65
Figure 18 Gain Tracking: . . . . . . . . . . . . .(measured with sine wave f = 1014 Hz 66
Figure 19 Receive or Transmit: measured with sine wave f = 1014 Hz. . . . . . . . 67
Figure 20 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21 Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SICOFI-4
PEB 2465
List of Tables Page
Data Sheet 9 2000-02-08
Table 1 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2 IOM-2 Timeslot Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3 Transmission Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 4 Group Delay Absolute Values: Input signal level 0 dBm0 . . . . . . . . . . 60
Table 5 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 6 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 7 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 8 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SICOFI-4
PEB 2465
General Description
Data Sheet 10 2000-02-08
1 General Description
The four Channe l CODEC Filt er PEB 246 5 SICOFI-4 is the log ic con tinu atio n of a well -
established family of SIEMENS codec-filter-ICs.
The SICOFI-4 is a fully integrated PCM CODEC and FILTER fabricated in low power 1µ
CMOS technology for applications in digital communication systems. Based on an
advanced digital filter concept, the PEB 2465 provides excellent transmission
performance a nd high flexibilit y. The new filter co ncept (second generation) lends to a
maximum of independence between the different filter blocks. Each filter block can be
seen like an one to one representative of the corresponding network element.
Only very few external components are needed, to complete the functionality of the
SICOFI-4. The int ernal level accuracy i s based on a very accura te bandgap reference.
The frequency behavior is mainly determined by digital filters, which do not have any
fluctuations. As a result of the new ADC - and DAC - concepts linearity is only limited by
second order parasitic effects. Although the device works with only one single 5 V supply
there is a very good dynamic range available.
Data Sheet 11 2000-02-08
Type Package
PEB 2465
Four Channel Codec Filter
SICOFI-4 PEB 2465
V2.3
1.1 Features
•Single chip CODEC and FILTER to handle four CO- or
PABX-channels
•Specification according to relevant CCITT, EIA and
LSSGR recommendations
•Digital signal processing technique
•Programmable interface optimized to current feed
SLICs and transformer solutions
•Four pin serial IOM-2 Interface
•Single power supply 5 V
•Advanced lo w power 1 µm analog CMOS technology
•Standard 64 pin P-MQFP-64 package
•High performance Analog to Digital Conversion
•High performance Digital to Analog Conversion
•Programmable digital filters to adapt the transmission behavior especially for
–AC impedance matching
–transhybrid balancing
–frequency response
–gain
•Advanced test capabilities
–all digital pins can be tested within a boundary scan scheme (IEEE 1149.1)
–five digital loops
–four analog loops
–two programmable tone generators per channel
•Comprehensive Development Platform available
–software for automatic filter coefficient calculation - QSICOS
–Hardware develo pme nt board - STUT 2465
P-MQFP-64
SICOFI-4
PEB 2465
General Description
Data Sheet 12 2000-02-08
ITP06788
PEB 2465 H
SICOFI -4
R
12
SO3_2
4748
SO2_2
SI1_0
50 31
3249
SO3_1
3
SO3_0
4 5
GNDA3
6 7 8 9 10
GNDA4
11 12
SO4_0
13
SO4_1
14
SO4_2
15
SB4_0*
16
SO2_1
46
SO2_0
45 44
GNDA2
43 42 41 40 39
GNDA1
38 37
SO1_0
36
SO1_1
35
SO1_2
34
SB1_0
33
3051
SI1_1
2952
SI1_2
2853
LGKM0
2754
FSC
2655
DCL
2556
DU
2457 2358 2259 2160 2061
SI4_2
1962
SI4_1
1863
SI4_0
SB3_1
1764
SB4_1
SB3_0
V
DDD
SB1_1
SB2_0
OUT3
V
V
IN3
V
H34
V
DDA34
V
IN4
OUT4
V
RESET
LGKM1
DD
V
OUT2
V
IN2
IN1
V
DDA12
V
H12
V
V
OUT1
SI3_0
SI3_1
SI3_2
TSS0
TSS1
GNDD
MODE
TCK
TMS
TDI
TDO
SI2_2
SI2_1
SI2_0
SB2_1
1.2 Pin Configurati on
(top view)
Figure 1 Pin Configuration
*pin designat ion is correcte d in 01. 00
P-MQFP-64
SICOFI-4
PEB 2465
General Description
Data Sheet 13 2000-02-08
1.3 Pin Definition and Functions
Table 1 Pin Definition and Functions
Pin No. Symbol Input (I)
Output (O) Function
Common Pins for All Channels
23 VDDD I + 5 V supply for the digital circuitry 1)
58 GNDD I Ground Digital, not internally connected to
GNDA 1, 2, 3, 4
All digital signals are referred to this pin
40 VDDA12 I + 5 V Analog supply voltage for channel 1 and 2 1)
9VDDA34 I + 5 V Analog supply voltage for channel 3 and 4 1)
27 FSC I IOM-2: Frame synchronization clock , 8 kHz
26 DCL I IOM-2: Data clock, 2048 kHz or 4096 kHz depending
on MODE
25 DU O IOM-2: Data upstream, open drain output
24 DD I IOM-2: Data downstream, input
22 RESET I Reset input - forces the device to the default mode,
active high
57 MODE I IOM-2: Mode Selection
60 TSS0 I IOM-2: Time slot selection pin 0
59 TSS1 I IOM-2: Time slot selection pin 1
56 TCK I Boundary scan: Test Clock
55 TMS I Boundary scan: Test Mode Select
54 TDI I Boundary scan: Test Data Input
53 TDO O Boundary scan: Test Data Output
28 LGKM0 O Loop/Ground Key Multiplexing output 0 for
channel 1, 2
21 LGKM1 O Loop/Ground Key Multiplexing output 1 for
channel 3, 4
41 VH12 I/O Reference voltage for channel 1 and 2, has to be
connected via a 220 nF cap. to ground
8VH34 I/O Reference voltage for channel 3 and 4, has to be
connected via a 220 nF cap. to ground
1) A 100 nF cap. should be used for blocking t hese pins, see also on Page 75.
SICOFI-4
PEB 2465
General Description
Data Sheet 14 2000-02-08
Specific Pins for Channel 1
38 GNDA1 I Ground Analog for channel 1, not internally
connected to GNDD or GN DA 2, 3, 4
39 VIN1 I Analog voice (voltage) input for channel 1
37 VOUT1 O Analog voice (voltage) output for channel 1
31 SI1_0 I Signaling indication input pin 0 for channel 1
30 SI1_1 I Signaling indication input pin 1 for channel 1
29 SI1_2 I Signaling indication input pin 2 for channel 1
36 SO1_0 O Signaling command output pin 0 for channel 1
35 SO1_1 O Signaling command output pin 1 for channel 1
34 SO1_2 O Signaling command output pin 2 for channel 1
33 SB1_0 I/O Bi-directional signal. command indication pin 0 for
channel 1
32 SB1_1 I/O Bi-directional signal. command indication pin 1 for
channel 1
Specific Pins for Channel 2
43 GNDA2 I Ground Analog for channel 2, not internally
connected to GNDD or GNDA 1 , 3, 4
42 VIN2 I Analog voice (voltage) input for channel 2
44 VOUT2 O Analog voice (voltage) output for channel 2
50 SI2_0 I Signaling indication input pin 0 for channel 2
51 SI2_1 I Signaling indication input pin 1 for channel 2
52 SI2_2 I Signaling indication input pin 2 for channel 2
45 SO2_0 O Signaling command output pin 0 for channel 2
46 SO2_1 O Signaling command output pin 1 for channel 2
47 SO2_2 O Signaling command output pin 2 for channel 2
48 SB2_0 I/O Bi-directional signal. command indication pin 0 for
channel 2
49 SB2_1 I/O Bi-directional signal. command indication pin 1 for
channel 2
Table 1 Pin Definition and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
SICOFI-4
PEB 2465
General Description
Data Sheet 15 2000-02-08
Specific Pins for Channel 3
6 GNDA3 I Ground Analog for channel 3, not internally
connected to GNDD or GNDA1 , 2, 4
7VIN3 I Analog voice (voltage) input for channel 3
5VOUT3 O Analog voice (voltage) output for channel 3
63 SI3_0 I Signaling indication input pin 0 for channel 3
62 SI3_1 I Signaling indication input pin 1 for channel 3
61 SI3_2 I Signaling indication input pin 2 for channel 3
4 SO3_0 O Signaling command output pin 0 for channel 3
3 SO3_1 O Signaling command output pin 1 for channel 3
2 SO3_2 O Signaling command output pin 2 for channel 3
1 SB3_0 I/O Bi-directional signal. command indication pin 0 for
channel 3
64 SB3_1 I/O Bi-directional signal. command indication pin 1 for
channel 3
Specific Pins for Channel 4
11 GNDA4 I Ground Analog for channel 4, not internally
connected to GNDD or GN DA1,2,3
10 VIN4 I Analog voice (voltage) input for channel 4
12 VOUT4 O Analog voice (voltage) output for channel 4
18 SI4_0 I Signaling indication input pin 0 for channel 4
19 SI4_1 I Signaling indication input pin 1 for channel 4
20 SI4_2 I Signaling indication input pin 2 for channel 4
13 SO4_0 O Signaling command output pin 0 for channel 4
14 SO4_1 O Signaling command output pin 1 for channel 4
15 SO4_2 O Signaling command output pin 2 for channel 4
16 SB4_0 I/O Bi-directional signal. command indication pin 0 for
channel 4
17 SB4_1 I/O Bi-directional signal. command indication pin 1 for
channel 4
Table 1 Pin Definition and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O) Function
SICOFI-4
PEB 2465
Functional Description
Data Sheet 16 2000-02-08
2 Functional Description
2.1 SICOFI-4 Principles
The change from 2 µm to 1 µm CMOS pr oc ess r e qui res n ew co nc e pts in t he r ea li z ati o n
of the analog functions. High performance (in the terms of gain, speed, stability…) 1 µm
CMOS devices can not withstand more than 5.5 V of supply-voltage. On that account the
negative s upply voltag e VSS of the previous SICOFI®s will be omitte d. This is a benefit
for the user but it makes a very high demand on the analog circuitry.
ADC and DAC are changed to Sigma-Delta-concepts to fulfill the stringent requirements
on the dynamic parameters.
Using 1 µm CMOS does not only lend to problems − it is the only acceptable solution in
terms of area and power consumption for the integration of more then two SICOFI
channels on a single chip.
It is rather pointl ess to implement 4 codec -filter-channel s on one chip with pure analog
circuitry. The use of a DSP-concept (the SICOFI® and the SICOFI®-2-approach) for this
function seems to be a must for an adequate four channel architecture.
Figure 2 SICOFI-4 Signal Flow Graph (for either channel)
SICOFI-4
PEB 2465
Functional Description
Data Sheet 17 2000-02-08
Transmit Path
The analog input si gna l ha s to be DC-free co nnec ted by an external cap aci tor b eca use
there is an internal virtual reference ground potential. After passing a simple antialiasing
prefilter (PREFI) the voice signal is converted to a 1-bit digital data stream in the Sigma-
Delta-converter. The first downsampling steps are done in fast running digital hardware
filters. The following steps are implemented in the micro-code which has to be executed
by the central Digital Signal Processor. This DSP-machine is able to handle the workload
for all four channels. At the end the fully processed signal (flexibly programmed in many
parameters) is transferred to the IOM-2 interface in a PCM-compressed signal
representation.
Receive Path
The digital input si gnal is rec eiv ed via the IOM -2 i nterface. Exp ans ion , PC M-La w-p ass -
filtering, gain correction and frequency response correction are the next steps which are
done by the D SP-m ach ine. The upsa mpli ng in terpolation s teps are ag ain p r oce sse d by
fast hardware structures to reduce the DSP-workload. The upsampled 1-bit data stream
is then conv erted to an analog eq uivalent which is smoothe d by a POST-Filter (POFI).
As the signal VOUT is also referenced to an internal virtual ground potential, an external
capacitor is required for DC-decoupling.
Loops
There are two loop s im plem ent ed. The first is to generate the AC-inpu t imp edance (IM)
and the second is to perform a proper hybrid balancing (TH). A simple extra path IM2
(from the transmit to the receive path) supports the impedance matching function.
Test Features
There are four analog and five digital test loops implemented in the SICOFI-4. For
special tes ts it is poss ible to ‘Cut Off’ the receive and the transmit path at two diff erent
points.
SICOFI-4
PEB 2465
Functional Description
Data Sheet 18 2000-02-08
Figure 3 SICOFI-4 Block Diagram
The SICOFI-4 bridges the gap between analo g and digital v oice signal t ransmission in
modern telecom munication systems. High perfo rmance over sampling Analog-to-D igital
Converters (ADC) and Digital-to-Analog Converters (DAC) provide the required
conversion accuracy. Analog antialiasing prefilters (PREFI) and smoothing postfilters
(POFI) are included. The connection between the ADC and the DAC (with high sampling
rate) and the DSP, is done by specific Hardware Filters, for filtering like interpolation and
decimation. The dedicated Digital Signal Processor (DSP) handles all the algorithms
necessary e.g. for PCM bandpass filtering, sample rate conversion and PCM
compandin g. The IO M-2 Int erface h andles digital voice transm ission , SICOFI-4 fe ature
control and transparent access to the SICOFI-4 command and indication pins. To
program the filters, precalculated sets of coefficients are downloaded from the system to
the on chip coefficient ram (CRAM).
SICOFI-4
PEB 2465
Functional Description
Data Sheet 19 2000-02-08
2.2 IOM-2 Interface
The IOM- 2 Int erfac e c ons ists of two data li nes and tw o c loc k li nes . D U (data ups tream )
carries data from the SICOFI-4 to a master device. This master device performs the
interface between the PCM-backplane, the µ-controller and up to 24 SICOFI-4’s. DD
(data downstream) carries data from the master device to the SICOFI-4. A frame
synchronization clock signal (8 kHz, FSC) as well as a data clock signal (2048 kHz or
4096 kHz DCL) has to be supplied to the SICOFI-4. The SICOFI-4 handles data as
described in the IOM-2 specification for analog devices.
Figure 4 IOM-2 Interface Timing for 16 Voice Channels (per 8 kHz frame)
SICOFI-4
PEB 2465
Functional Description
Data Sheet 20 2000-02-08
Figure 5 IOM-2 Interface Timing (DCL=4096 kHz, MODE=1, per 8 kHz frame)
SICOFI-4
PEB 2465
Functional Description
Data Sheet 21 2000-02-08
Figure 6 IOM-2 Interface Timing (DCL = 2048 kHz, MODE = 0)
IOM-2 Timeslot Selection
The four channels of each SICOFI-4 can be assigned to 4 pairs of timeslots by pin-
strapping th e pins TSS0 and TSS1. (TS0 + TS1, TS2 + TS3, TS4 + TS5, TS6 + TS7).
The IOM-2 operating mode is selected by the MODE pin.
Table 2 IOM-2 Timeslot Selection
TSS1 TSS0 MODE IOM-2 Ope rating Mode
0 0 1 Timeslot 0 + 1; DCL = 4096 kHz
0 1 1 Timeslot 2 + 3; DCL = 4096 kHz
1 0 1 Timeslot 4 + 5; DCL = 4096 kHz
1 1 1 Timeslot 6 + 7; DCL = 4096 kHz
0 0 0 Timeslot 0 + 1; DCL = 2048 kHz
0 1 0 Timeslot 2 + 3; DCL = 2048 kHz
1 0 0 Timeslot 4 + 5; DCL = 2048 kHz
1 1 0 Timeslot 6 + 7; DCL = 2048 kHz
SICOFI-4
PEB 2465
Functional Description
Data Sheet 22 2000-02-08
Each IOM-timeslot contains 2 voice channels (A and B). Those two voice channels share
a common IOM-Monitor-byte as well as a common C/I-byte. The AD-bit in the Monitor
command defines which of the two voice channels should be affected (programmed).
(For more information on IOM-2 specific Monitor Channel Data Structure see appendix,
Page 64).
In the following sections, only SICOFI-4 channels 1 and 2 are discussed.
Channel 3 and channel 4 behave accordingly.
SICOFI-4
Channels TSS1 = 0,
TSS0 = 0 TSS1 = 0,
TSS0 = 1 TSS1 = 1,
TSS0 = 0 TSS1 = 1,
TSS0 = 1
TS Voice
Channel TS Voice
Channel TS Voice
Channel TS Voice
Channel
1 TS0 A TS2 A TS4 A TS6 A
2 TS0 B TS2 B TS4 B TS6 B
3 TS1 A TS3 A TS5 A TS7 A
4 TS1 B TS3 B TS5 B TS7 B
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 23 2000-02-08
3 Progr am min g the SICOFI- 4
With the appropriate commands, the SICOFI-4 can be programmed and verified very
flexibly via the IOM-2 Interface monitor channel.
Data transfer to the SICOFI-4 starts with a SICOFI-specific address byte (81H).
With the second byte one of 3 different types of commands (SOP, XOP and COP) is
select ed. Ea ch o f thos e c an be used as a wr ite o r read c omm and . Due to the e xten ded
SICOFI-4 feature control facilities, SOP, COP and XOP commands contain additional
information (e.g. number of subsequent bytes) for programming (write) and verifying
(read) the SICOFI-4 status.
A write command is followed by up to 8 bytes of data. The SICOFI-4 responds to a read
command w ith its IOM -2 s pec ific add ress and the requ est ed i nform atio n, th at is up to 8
bytes of data (see Programming Procedure, Page 66).
Attention: Each byte on the monitor channel, has to be sent twice at least, according to
the IOM-2 Monitor handshake procedure. (For more information on IOM-2 specific
Monitor Channel Data Structure see appendix, Page 64).
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 24 2000-02-08
3.1 Types of Monitor Bytes
The 8-bit Monitor bytes have to be interpreted as either commands or status information
stored in Configuration Registers or the Coefficient Ram. There are three different types
of SICOFI-4 commands which are selected by bit 3 and 4 as shown below.
SOP STATUS OPERATION: SICOFI-4 status setting/monitoring
XOP EXTENDED OPERATION: C/I channel configuration/evaluation
COP COEFFICIENT OPERATION: filter coefficient setting/monitoring
3.2 Storage of Programming Information
4 configuration registers per channel:CR1, CR2, CR3, CR4 accessed by SOP
commands
4 common configuration registers:XR1, XR2, XR3 and XR4 accessed by XOP
commands (the contents are valid for two voice channels i.e. 1 IOM-2 timeslot)
1 Coefficient RAM per channel:CRAM accessed by COP commands
Bit76543210
10
Bit76543210
X11
Bit76543210
0
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 25 2000-02-08
3.3 SICOFI-4 Commands
3.3.1 SOP – Write Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Write 1 Byte 0 10001 Idle
CR1 Data Idle
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Write 2 Bytes 0 10010 Idle
CR2 Data Idle
CR1 Data Idle
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Write 3 Bytes 0 10011 Idle
CR3 Data Idle
CR2 Data Idle
CR1 Data Idle
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Write 4 Bytes 0 10100 Idle
CR4 Data Idle
CR3 Data Idle
CR2 Data Idle
CR1 Data Idle
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 26 2000-02-08
3.3.2 XOP – Write Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
XOP-Write 2 Bytes 0 11010 Idle
XR2 Data Idle
XR1 Data Idle
DD 76543210Bit 76543210 DU
Address 10000001 Idle
XOP-Write 3 Bytes 0 11010 Idle
XR3 Data Idle
XR2 Data Idle
XR1 Data Idle
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 27 2000-02-08
3.3.3 COP – Write Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
COP-Write 4 Bytes 0 0 1 Idle
Coeff. 4 Data Idle
Coeff. 3 Data Idle
Coeff. 2 Data Idle
Coeff. 1 Data Idle
DD 76543210Bit 76543210 DU
Address 10000001 Idle
COP-Write 8 Bytes 0 0 0 Idle
Coeff. 8 Data Idle
Coeff. 7 Data Idle
Coeff. 6 Data Idle
Coeff. 5 Data Idle
Coeff. 4 Data Idle
Coeff. 3 Data Idle
Coeff. 2 Data Idle
Coeff. 1 Data Idle
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 28 2000-02-08
3.3.4 SOP – Read Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Read 1 Byte 1 10001 Idle
Idle 10000001Address
Idle Data CR1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Read 2 Bytes 1 10010 Idle
Idle 10000001Address
Idle Data CR2
Idle Data CR1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Read 3 Bytes 1 10011 Idle
Idle 10000001Address
Idle Data CR3
Idle Data CR2
Idle Data CR1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Read 4 Bytes 1 10100 Idle
Idle 10000001Address
Idle Data CR4
Idle Data CR3
Idle Data CR2
Idle Data CR1
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 29 2000-02-08
3.3.5 XOP – Read Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
XOP-Read 1 Byte 1 11001 Idle
Idle 10000001Address
Idle Data XR1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
XOP-Read 2 Bytes 1 11010 Idle
Idle 10000001Address
Idle Data XR2
Idle Data XR1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
XOP-Read 3 Bytes 1 11011 Idle
Idle 10000001Address
Idle Data XR3
Idle Data XR2
Idle Data XR1
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 30 2000-02-08
3.3.6 COP – Read Commands
DD 76543210Bit 76543210 DU
Address 10000001 Idle
COP-Read 4 Bytes 1 0 1 Idle
Idle 10000001Address
Idle Data Coeff. 4
Idle Data Coeff. 3
Idle Data Coeff. 2
Idle Data Coeff. 1
DD 76543210Bit 76543210 DU
Address 10000001 Idle
COP-Read 8 Bytes 1 0 0 Idle
Idle 10000001Address
Idle Data Coeff. 8
Idle Data Coeff. 7
Idle Data Coeff. 6
Idle Data Coeff. 5
Idle Data Coeff. 4
Idle Data Coeff. 3
Idle Data Coeff. 2
Idle Data Coeff. 1
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 31 2000-02-08
3.3.7 Example for a Mixed Command
DD 76543210Bit 76543210 DU
Address 10000001 Idle
SOP-Write 4 Bytes 0 10100 Idle
CR4 Data Idle
CR3 Data Idle
CR2 Data Idle
CR1 Data Idle
XOP-Write 2 Bytes 0 11010 Idle
XR2 Data Idle
XR1 Data Idle
COP-Write 4 Bytes 0 0 1 Idle
Coeff. 4 Data Idle
Coeff. 3 Data Idle
Coeff. 2 Data Idle
Coeff. 1 Data Idle
SOP-Read 3 Bytes 1 10011 Idle
Idle 10000001Address
Idle Data CR3
Idle Data CR2
Idle Data CR1
Address 10000001 Idle
COP-Read 4 Bytes 1 0 1 Idle
Idle 10000001Address
Idle Data Coeff. 4
Idle Data Coeff. 3
Idle Data Coeff. 2
Idle Data Coeff. 1
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 32 2000-02-08
Address 10000001 Idle
XOP-Read 1 Byte 1 11001 Idle
Idle 10000001Address
Idle Data XR1
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 33 2000-02-08
3.4 SOP Command
To modify or evaluate the SICOFI-4 status, the contents of up to four configuration
registers C R1, CR 2, C R3 an d C R 4 may b e tra nsf erred to or from the SIC OFI-4 . Th is is
started by a SOP-Command (status operation command).
AD Address Information
AD = 0 SICOFI-4 channel 1(3) is addressed with this command
AD = 1 SICOFI-4 channel 2(4) is addressed with this command
RW Read/Write Information: Enables reading from the SICOFI-4 or writing
information to the SICOFI-4
RW = 0 Write to SICOFI-4
RW = 1 Read from SICOFI-4
PWRUP Power Up / Powe r Down
PWRUP = 1 sets the assigned channel (see bit AD) of SICOFI-4 to
power-up (operating mode)
PWRUP = 0 resets the assigned channel of SICOFI-4 to power-down
(standby mode)
LSEL Length select information (see also Programming Procedure, Page 66)
This field identifies the number of subsequent data bytes
LSEL = 000 0 bytes of data are following
LSEL = 001 1 byte of data is following (CR1)
LSEL = 010 2 bytes of data are following (CR2, CR1)
LSEL = 011 3 bytes of data are following (CR3, CR2, CR1)
LSEL = 100 4 bytes of data are following (CR4, CR3, CR2, CR1)
All other codes are reserved for future use!
It is possible to program each Configuration register separately, just by putting only one
byte into the FIFO of the upstream master device (e.g. EPIC), and aborting after
transmission of one (or n) byte.
Bit76543210
AD RW PWRUP 1 0 LSEL2 LSEL1 LSEL0
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 34 2000-02-08
3.4.1 CR1 Configuration Register 1
Configuration register CR1 defines the basic SICOFI-4 settings, which are: enabling/
disabling the progra mma ble digital filters and tone gene rators .
TH Enable TH- (TransHybrid Balancing) Filter
TH = 0: TH-filter disabled
TH = 1: TH-filter enabled
IM/R1 Enable IM-(Impedance Matching) Filter and R1-Filter
IM/R1 = 0: IM-filter and R1-filter disabled
IM/R1 = 1: IM-filter and R1-filter enabled
FRX Enable FRX (Frequency Response Transmit)-Filter
FRX = 0: FRX-filter disabled
FRX = 1: FRX-filter enabled
FRR Enable FRR (Frequency Re sponse Receive )-Fi lter
FRR = 0: FRR-filter disabled
FRR = 1: FRR-filter enabled
AX Enable AX-(Amplification/Attenuation Transmit) Filter
AX = 0: AX-filter disa bled
AX = 1: AX-filter enabled
AR Enable AR-(Amplification/Attenuation Receive) Filter
AR = 0: AR-filter disabled
AR = 1: AR-filter enabled
ETG2 Enable programma ble tone generato r 21)
ETG2 = 0 : p rogrammable tone generator 2 is disabled
ETG2 = 1: programmable tone generator 2 is enabled
ETG1 Enable programma ble tone generato r 1
ETG1 = 0 : p rogrammable tone generator 1 is disabled
ETG1 = 1: programmable tone generator 1 is enabled
Bit76543210
TH IM/R1 FRX FRR AX AR ETG2 ETG1
1) Tone gen erat or 2 is not available if Lev el M et ering Function is enabled!
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 35 2000-02-08
3.4.2 CR2 Configuration Register 2
TH-Sel 2 bit field to select one of four programmed TH-filter coefficient sets
TH-Sel = 0 0: TH-filter coefficient set 1 is selected
TH-Sel = 0 1: TH-filter coefficient set 2 is selected
TH-Sel = 1 0: TH-filter coefficient set 3 is selected
TH-Sel = 1 1: TH-filter coefficient set 4 is selected
LM Level Metering function11)
LM = 0 : level metering function is disabled
LM = 1: level metering function is enabled
LMR Result of Level Metering function (this bit can not be written)
LMR = 0: level detected was lower than the reference
LMR = 1: level detected was higher than the reference
LAW PCM - law selection
LAW = 0: A-Law is selected
LAW = 1: µ-Law (µ255 PCM) is selected
LIN Linear mode selection
LIN = 0: PCM-mode is selected
LIN = 1: linear mode is selected2)
PTG2 User programmed frequency or fixed frequency is selected
PTG2 = 0: fixed frequency for tone generator 2 is selected (1 kHz)
PTG2 = 1: programmed frequency for tone generator 2 is selected
PTG1 User programmed frequency or fixed frequency is selected
PTG1 = 0: fixed frequency for tone generator 1 is selected (1 kHz)
PTG1 = 1: programmed frequency for tone generator 1 is selected
Bit76543210
TH-Sel LM LMR LAW LIN PTG2 PTG1
1) Explan at ion of th e level metering f unc t ion:
A signal fed to A/µ-Law compression via AX- and HPX-filters (from a digital loop, or externally via VIN), is
rectifie d, and the power is me asured. If the power exceeds a cert ain value, loaded t o XR4, bit LMR is set to
‘1’. The power of th e inc om i ng signal can be adjusted by AX-f ilt ers .
2) During Linear operation only one 16 bit voice channel, is available per timeslot. Depending on the address bit
(AD) the voice-data of channel 1 or 2 is transmitted. The other voice channel is not available during this time.
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 36 2000-02-08
3.4.3 CR3 Configuration Register 3
COT/R Selection of Cut of Transmit/Receive Paths
0 0 0: Normal Operation
0 0 1: COT_16KCut Off Transmit Path at 16 kHz (input of TH-
Filter) 0 1 0: COT_PCMCut Off Transmit Path at 8 kHz (input of
compression) (output is zero for µ-law
and linear mode, 1 LSB for A-law)
1 0 1: COR_PFICut Off Receive Path at 4 MHz (POFI-output)
1 1 0: COR_64KCut Off Receive Path at 64 kHz (IM-filter input)
IDR Initialize Data RAM
IDR = 0: normal operation is selected
IDR = 1: contents of Data RAM is set to 0
(used for production test purposes)
Version The Version number shows the actual design version of SICOFI-4
( 001 for PEB 2465 V1.1
010 for PEB 2465 V1.2
011 for PEB 2465 V2.1
100 for PEB 2465 V2.2 and V2.3)
Bit76543210
COT/R 0 IDR Version
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 37 2000-02-08
CUT OFFs’ and Loops‘
Figure 7 CUT OFFs and Loops
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 38 2000-02-08
3.4.4 CR4 Configuration Register 4
Test-Loops 4 bit field for selection of Analog and Digital Loop Backs
0 0 0 0: no loop back is selected (normal operation)
0 0 0 1: ALB-PFI analog loop back via PREFI-POFI is selected
0 0 1 1: ALB-4M analog loop back via 4 MHz is selected
0 1 0 0: ALB-PCM analog loop back via 8 kHz (PCM) is selected
0 1 0 1: ALB-8K analog loop back via 8 kHz (linear) is selected
1 0 0 0: DLB-ANA digital loop back via analog port is selected
1 0 0 1: DLB-4M digital loop back via 4 MHz is selected
1 1 0 0: DLB-128K digital loop back via 128 kHz is selected
1 1 0 1: DLB-64K digital loop back via 64 kHz is selected
1 1 1 1: DLB-PCM digital loop back via PCM-registers is selected
AGX Anal og gain in transmit direct io n
AGX = 0: analog gain is disabled
AGX = 1: analog gain is enabled (6.02 dB amplification)
AGR Anal og gain in receive directio n
AGR = 0: analog gain is disabled
AGR = 1: analog gain is enabled (6.02 dB attenuation)
D-HPX Disable highpass in transmit direction
D-HPX = 0: transmit high pass is enabled
D-HPX = 1: transmit high pass is disabled1)
D-HPR Disable highpass in receive direction
D-HPR = 0: receive high pass is enabled
D-HPR = 1: receive high pass is disabled2)
Bit76543210
Test-Loops AGX AGR D-HPX D-HPR
1) In this case the transmit-p at h signal is attenua te d 0. 06 dB
2) In this case the receive-pa th sig nal is at te nuated 0.12 dB
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 39 2000-02-08
3.5 COP Command
With a COP Command coefficients for the programmable filters can be written to the
SICOFI-4 Coefficient RAM or read from the Coefficient RAM via the IOM-2 interface for
verification.
AD Address
AD = 0 SICOFI-4 channel 1 (3) is addressed
AD = 1 SICOFI-4 channel 2 (4) is addressed
RW Read/Write
RW = 0 Subsequent data is written to the SICOFI-4
RW = 1 Read data from SICOFI-4
RST Reset
RST = 1 Reset SICOFI-4
(same as RESET-pin, valid for all four channels)
CODE includes number of following bytes and filter-address
Bit76543210
AD RW RST 0 CODE3 CODE2 CODE1 CODE0
0000 TH-Filter coefficients (part 1) (followed by 8 bytes of data)
0001 TH-Filter coefficients (part 2) (followed by 8 bytes of data)
0010 TH-Filter coefficients (part3) (followed by 8 bytes of data)
0100 IM-Filter coefficients (part1) (followed by 8 bytes of data)
0101 IM-Filter coefficients (part2) (followed by 8 bytes of data)
0110 FRX-Filter coefficients (followed by 8 bytes of data)
0111 FRR-Filter coefficients (followed by 8 bytes of data)
1000 AX-Filter coefficients (followed by 4 bytes of data)
1001 AR-Filter coefficients (followed by 4 bytes of data)
1100 TG1-Filter coefficients (followed by 4 bytes of data)
1101 TG2-Filter coefficients (followed by 4 bytes of data)
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 40 2000-02-08
3.6 How to Program the Filter Coefficients
TH-Filter: Four sets of TH-filter coefficients can be loaded to the SICOFI-4.
Each of the fo ur sets c an be se lected for an y of the f our SICOFI-4 ch annels , by set ting
the value of TH-Sel in configuration register CR2. Coefficient set 1 is loaded to the
SICOFI-4 via channel 1, set 2 is loaded via channel 2 and so on.
AX, AR, IM,
FRX, FRR-Filter: An individual coefficient set is available for each of the four channels
Tone-generators: An individual coefficient set is available for each of the four channels
An independent set of coefficients is available for all the four channels, for all the filters
and Tone-Generators. So AX, AR, FRR, FRX, IM and TG1 and TG2 behave like AX and
AR-filters in Version V1.*.
The programming flexibility for the TH-filter was not changed from Version V1.* to
Version V2.*. Four set s of TH-filter co efficien ts can be loaded to the SICOFI-4. Each of
the four sets can be selected for any of the four SICOFI-4 channels, by setting the value
of TH-SEL in configuration register CR2. Coefficients set #1 is loaded to the SICOFI-4
via channel 1, set #2 is loaded via channel 2 and so on.
Note: After RESET coefficient set #1 is used for all of the four channels, as all bits in
configuration register CR2 are set to ‘0’.
Figure 8 Channel Registers
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 41 2000-02-08
3.7 XOP Command
With the XOP command the SICOFI-4 C/I channel is configured and evaluated. The
XR registers are valid for two voice channels 1, 2 or 3, 4 , depending on the selected
IOM-2 timeslot1) (i.e. TS0+TS1: channel 1, 2 in TS0, channel 3, 4 in TS1).
RW Read / Write Information: Enables reading from the SICOFI-4 or writing
information to the SICOFI-4
RW = 0 Write to SICOFI-4
RW = 1 Read from SICOFI-4
LSEL Length select information, for setting the number of subsequent data bytes
LSEL = 000 0 bytes of data are following
LSEL = 001 1 byte of data is following (XR1)
LSEL = 010 2 bytes of data are following (XR2, XR1)
LSEL = 011 3 bytes of data are following (XR3, XR2, XR1)
LSEL = 100 4 bytes of data are following (XR4, XR3, XR2, XR1)
3.7.1 XR1 Extended Register 12)
SB2[4]_1 status of pin SB2[4]_1 is transferred to the upstream master device
SB2[4]_0 status of pin SB2[4]_0 is transferred to the upstream master device
SI2[4]_0 status of pin SI2[4]_0 is transferred to the upstream master device
SB1[3]_1 status of pin SB1[3]_1 is transferred to the upstream master device
SB1[3]_0 status of pin SB1[3]_0 is transferred to the upstream master device
SI1[3]_0 status of pin SI1[3]_0 is transferred to the upstream master device
1) IOM-2 timeslots TS0+TS1, TS2+TS3, TS4+TS5 or TS6+TS7, by pin-strapping the pins TSS0 and TSS1 (see
page s <F ett>17 and <F ett>18)
Bit76543210
0 RW 0 1 1 LSEL2 LSEL1 LSEL0
2) Registe r XR1 can be read on ly .
3) Bits SI1[3]_0 and SI2[4]_0 have special meaning depending on contents of XR2 (see Page 35).
Bit76543210
SB2[4]_1 SB2[4]_0 SI2[4]_0
33) SI2[4]_0
3) SB1[3]_1 SB1[3]_0 SI1[3]_0
3) SI1[3]_0
3)
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 42 2000-02-08
3.7.2 XR2 Extended Register 2
Register XR2 configures the data-upstream command/indication channel.
Upstream Update Interval N
To restrict the rate of upstream C/I-bit changes, deglitching (persistence checking) of the
status information from the SLIC may be applied. New status information will be
transmitt ed upstrea m, after it has been stabl e for N millis econds . N is program mable in
the range of 1 to 15 ms in steps of 1 ms, with N = 0 the deglitching is disabled.
Detector Select Sampling Interval T
SLICs wi th multipl exed l oop- and g round-key-sta tus, whi ch have a single status ou tput
pin for carrying the loop- and ground-key-status information, need a special detector
select input.
LGKM0[1] is detector select output for channel 1[3] and 2[4]
Bit76543210
NT
Field N Update Interval Time
0 0 0 0 Deglitching is disabled
0 0 0 1 Upstream transmission after 1 ms
0 0 1 0 Upstream transmission after 2 ms
.....
.....
1 1 1 0 Upstream transmission after 14 ms
1 1 1 1 Upstream transmission after 15 ms
Field T Time Interval T between Detector Selected High States
0 0 0 0 Detector select output LGKM0,1 program. to 0 permanently
0 0 0 1 Time interval T is 1 ms
0 0 1 0 Time interval T is 2 ms
.....
.....
1 1 1 0 Time interval T is 14 ms
1 1 1 1 Detector select output LGKM0,1 is program. to 1 permanently
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 43 2000-02-08
SLICs with Multiplexed Loop/Ground Key Detect
Figure 9 SLICs with Multiplexed Loop/Ground Key Detect
SICOFI-4 pins LGKM 0,[1 ] are de tec t or sele ct outputs. The se co mmand outp ut p ins are
normally set to logical ‘0’, such that the SLIC outputs loop status, which is passed to XR1
- bits 0 and 4 via indication pins SI1_0 and SI2_0.
Every T milliseconds, the detector select outputs change to logical ‘1’ for a time of 125 µs
(Period FSC). During this time the ground key status is read from the SLIC and
transferred upstream using XR1 - bits 1 and 5 via indication pins SIx_0 and SIy_0.
The time i nterval T is p rogrammab le from 1 ms to 14 m s in 1 ms steps. It is pos sible to
program the output to be permanently logical ‘0’ or ‘1’.
SICOFI-4
PEB 2465
Programming the SICOFI-4
Data Sheet 44 2000-02-08
3.7.3 XR3 Extended Register 3
This register controls the direction of the programmable C/I pins.
PSB2[4]_1 Programmable bi-directional C/I pin SB2[4]_1 is programmed
PSB2[4]_1 = 0:pin SB2[4]_1 is indication input
PSB2[4]_1 = 1:pin SB2[4]_1 is command output
PSB2[4]_0 Programmable bi-directional C/I pin SB2[4]_0 is programmed
PSB2[4]_0 = 0:pin SB2[4]_0 is indication input
PSB2[4]_0 = 1:pin SB2[4]_0 is command output
PSB1[3]_1 Programmable bi-directional C/I pin SB1[3]_1 is programmed
PSB1[3]_1 = 0:pin SB1[3]_1 is indication input
PSB1[3]_1 = 1:pin SB1[3]_1 is command output
PSB1[3]_0 Programmable bi-directional C/I pin SB1[3]_0 is programmed
PSB1[3]_0 = 0:pin SB1[3]_0 is indication input
PSB1[3]_0 = 1:pin SB1[3]_0 is command output
3.7.4 XR4 Extended Register 4
This register holds the offset value for the level metering function. It is only available via
the first used timeslot.
Bit76543210
PSB2[4]
_1 PSB2[4]
_0 0 0 PSB1[3]
_1 PSB1[3]
_0 00
Bit76543210
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
SICOFI-4
PEB 2465
SLIC Interface
Data Sheet 45 2000-02-08
4 SLIC Interface
The signaling con nection betwe en SICOFI-4 and a SLIC is performed by the SICOFI-4
command/indication pins. Data received from the downstream C/I byte are inverted and
transferred to command o utput pins (SB, SO). Data on inpu t pins (SI, SB) a re inverted
and transferred to the upstream C/I-byte.
4.1 IOM-2 Interface Command/Indic ation Byte
The SICOFI-4 offers a 8 pin parallel command/indication SLIC interface per channel
Indication input pins: SIx_0, SIx_1 SIx_2
Command output pins: SOx_0, SOx _1, SOx_ 2
Program. command/indication pins: SBx_0, SBx_1 (with x: 1 … 4)
Data present at SIx_0, SIx_1, SIx_2 and SBx_0, SBx_1 (if programmed as input) are
sampled, inverted and transferred upstream. Data received downstream from IOM-2
interface are l atched , inverted and fed to SOx_0, SOx _1, SOx _2 and SBx_ 0, SBx_1 (if
output).
SICOFI-4
PEB 2465
SLIC Interface
Data Sheet 46 2000-02-08
4.2 Data-downstream C/I Channel Byte Format (receive)
The IOM-2 channel contains 6 bits (for two voice channels) in both directions for analog
devices like the SICOFI-4. As the SICOFI-4 has up to five command output pins per
channel (dep ending on XR3) it is not possible t o send commands to all pins at a t ime.
So C/I-channel bit 5 is used as an address bit to select the channel for the command data
on C/I-channel bits 4 … 0.
General Case:
Example for SICOFI-4 channels 1 and 2 (IOM-2 timeslot 0):
4.3 Data Upstream C/I Channel Byte Format (transmit)
As the C/I-cha nne l ho lds only 6 bi ts fo r two voice cha nnels and the SIC OFI-4 has up to
five indication pins per voice channel, only pins SI1_1 and SI1_2 for voice channel 1, and
pins SI2_1 and SI2_2 for voice channel 2 are fed directly to the C/I-channel. Any change
at one of the other in dication pin s (SIx_0, SBx_0 and SBx_1) wi ll generate an in terrupt
per channel, which is transmitted upstream immediately (C/I-channel bits 2 and 5). Data
on those pins is fed to register XR1 and can be evaluated with a XOP-read command.
Bit543210
AD SBx_1 SBx_0 SOx_2 SOx_1 SOx_0
Bit543210
1 SB1_11)
1) If SBx_y is programmed as command output.
SB1_01) SO1_2 SO1_1 SO1_0
Bit543210
0 SB2_11) SB2_01) SO2_2 SO2_1 SO2_0
SICOFI-4
PEB 2465
SLIC Interface
Data Sheet 47 2000-02-08
There was a functional connection between two neighboring channels sharing the same
C/I-channel of an IOM-2 interface in V1.*. When an interrupt occurred in the C/I-channel,
changes on all signali ng in put pi ns of th is channel and of the ne ighb orin g cha nnel were
ignored, until the interrupt was cleared.
In Version V2. * this functio nal connection no longer exists. If an interrupt occurs in
one channel, changes in the neighboring channel will also generate an interrupt.
SICOFI-4
PEB 2465
SLIC Interface
Data Sheet 48 2000-02-08
Figure 10 Data Flow
SICOFI-4
PEB 2465
Operating Modes
Data Sheet 49 2000-02-08
5 Operating Modes
Figure 11 Operating Modes
SICOFI-4
PEB 2465
Operating Modes
Data Sheet 50 2000-02-08
5.1 RESET (Basic setting mode)
Upon initial application of VDD or resetting pin RESET to ‘1’ during operation, or by
software-reset (see COP command, Page 31), the SICOFI-4 enters a basic setting
mode. Basic setting means, t hat the SIC OFI-4 co nfigurati on regis ters CR1 … CR4 and
XR1 … XR3 are initialized to ‘0’ for all channels.
All programmable filters are disabled, A-law is chosen, all programmable command/
indication pins are inputs. The two tone generators as well as any testmodes are
disabled. There is no persistence checking. Receive signaling registers are cleared. DU-
pin is in high im pedance sta te, the analog ou tputs and the sig naling outpu ts are forced
to ground.
If any volta ge is applied to any input-pin be fore initial appl ication of VDD, the SICOFI-4
may not enter the bas ic settin g mod e. In thi s cas e it is ne ces sa ry to rese t the SICOFI-4
or to initialize the SICOFI-4 configuration registers to ‘0’.
The SICOFI-4 leaves this mode automatically with the beginning of the next 8 kHz frame
(RESET-pin is released).
CR1 … CR4 00 Hex
XR1 … XR4 00 Hex
Coefficient RAM not defined
Command Stack cleared
DD-input ignored
DU-output high impedance
VOUT1, 2, 3, 4 GNDA1, 2, 3, 4
SBx_y Input
SOx_y GNDD
SICOFI-4
PEB 2465
Operating Modes
Data Sheet 51 2000-02-08
5.2 Standby Mode
After releasing the RESET-pin, (RESET-state), beginning with the next 8 kHz frame, the
SICOFI-4 will enter the Standby mode. The SICOFI-4 is forced to standby mode with the
PWRUP bit set to ‘0’ in the SOP command (POWERDOWN). All 4 channels must be
programmed separately. During standby mode the serial SICOFI-4 IOM-2 interface is
ready to rece ive and trans mit com mands and data . Rece ived vo ice dat a on DD-pi n will
be ignored. SICOFI-4 configuration registers and coefficient ram can be loaded and read
back in this mode. Data downstream C/I-channel data is fed to appropriate Command
pins. Data on indication pins is transmitted Data upstream.
5.3 Operating Mode
The operating mode for any of the four channels is entered upon recognition of a
PWRUP bit set to ‘1’ in a SOP command for the specific channel.
IOM-2 Voice Channels ‘11111111’ (idle)
VOUT1, 2, 3, 4 GNDA1, 2, 3, 4
SICOFI-4
PEB 2465
Programmable Filters
Data Sheet 52 2000-02-08
6 Programmable Filters
Based on an advanced digital filter concept, the PEB 2465 provides excellent
transmission performance and high flexibility. The new filter concept leads to a maximum
independence between the different filter blocks.
6.1 Impedance Matching Filter
•Realization by 3 different loops
4 MHz: Multiplication by a constant (12 bit)
128 kHz: Wave Digital Filter (IIR) (60 bit)
(improves low frequency response)
64 kHz: FIR-Filter (48 bit)
(for fine-tuning)
•Improved stability behavior of feedback loops
•Real part of termination impedance positive under all conditions
•Improved overflow performance for transients
•Return loss better 30 dB
6.2 Transhybrid Balancing (TH) Filter
•New concept: 2 loops at 16 kHz
•Flexible realization allows optimization of wide impedance range
•Consists of a fixed and a programmable part
2nd order Wave Digital Filter (IIR) (106 bit)
(improves low frequency response)
7-TAP FIR-Filter (84 bit)
(for fine-tuning)
•Trans-Hybrid-Loss better 30 dB (typically better 40 dB, device only)
•Adaptation to different lines by:
Easy selection between four different downloaded coefficient sets
SICOFI-4
PEB 2465
Programmable Filters
Data Sheet 53 2000-02-08
6.3 Filters for Frequency Response Correction
•For line equalization and compensation of attenuation distortion
•Improvement of Group-Delay-Distortion by using minimum phase filters
(instead of linear phase filters)
•FRR filter for correction of receive path distortion
5 TAP programmable FIR filter operating at 8 kHz (60 bit)
•FRX filter for correction of transmit path distortion
5 TAP programmable FIR filter operating at 8 kHz (60 bit)
•Frequency response better 0.1 dB
SICOFI-4
PEB 2465
Programmable Filters
Data Sheet 54 2000-02-08
6.4 Amplification/Attenuation-Filters AX1, AX2, AR1, AR2
•Improved level adjustment for transmit and receive
•Two separate filters at each direction for
Improved trans-hybrid balancing
Optimal adjustment of digital dynamic range
Gain adjustments independent of TH-filter
6.5 Amplification/Attenuation Receive (AR1, AR2)-Filter
Step size for AR-Filter range 3 … − 14 dB: step size 0.02 … 0.05 dB
range − 14 … − 24 dB: step size 0.5 dB
6.6 Amplification/Attenuation Transmit (AX1, AX2)-Filter
Step size for AX-Filter range − 3 … 14 dB: step size 0.02 … 0.05 dB
range 14 … 24 dB: step size 0.5 dB
SICOFI-4
PEB 2465
QSICOS Software
Data Sheet 55 2000-02-08
7 QSICOS Software
The QSICOS-software has been developed to help to obtain an optimized set of
coefficients both quickly and easily. The QSICOS program runs on any PC with at least
575 Kbytes of memory. This also requires MS-DOS Version 5.0 or higher, as well as
extended memory.
Figure 12 QSICOS Software
SICOFI-4
PEB 2465
QSICOS Software
Data Sheet 56 2000-02-08
7.1 QSICOS Supports
•Calculation of coefficients for the
Impedance Filter (IM) for return loss calculation
FRR and FRX-Filters for frequency response in receive and transmit path
AR1, AR2 and AX1, AX2-Filter for level adjustment in receive and transmit path
Trans-Hybrid Bal ancing Filter (TH) and
two programmable tone generators (TG 1 and TG 2)
•Simulation of the PEB 2465 and SLIC system with fixed filter coefficients allows
simulations of tolerances which may be caused e.g. by discrete external components.
•Graphical output of transfer functions to the screen for
Return Loss
Frequency responses in receive and transmit path
Transhybrid Loss
•Calculation of the PEB 2465 and SLIC system stability. The IM-Filter of the
PEB 2465 adjust the total system impedance by making a feedback loop. Because the
line is also a part of the total system, a very robust method has to used to avoid
oscillations and to ensure system stability. The input impedance of the PEB 2465 and
SLIC combination is calculated. If the real part of the system input impedance is
positive, the total system stability can be guaranteed.
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 57 2000-02-08
8 Transmission Characteristics
The proper adjustment of the programmable filters (transhybrid balancing, impedance
matching, frequency-response correction) needs a c omplete kno wledg e of the SICOFI-
4’s analog environment, and it is suggested to use the QSICOS-program for calculating
the propriate coeffi cients. Unless otherwise sta ted, the transmissi on charact eristics are
guaranteed within the test conditions.
Test Conditions
TA = 0 °C to 70 °C; VDD = 5 V ± 5%; GNDA1 … 4 = GNDD = 0 V;
RL1) > 20 kΩ; CL < 20 pF;
H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1;
HPR and HPX enabled;
AR2) =0 to − 13 dB for sine-wave-, and
0 to − 11 dB for CCITT-noise-measurements
AX3) = 0 to 13 dB for sine-wave-, and
0 to 11 dB for CCITT-noise-measurements
f = 1014 Hz; 0 dBm0; A-Law or µ-Law;
AGX = 0 dB, 6.02 dB, AGR = 0 dB, − 6.02 dB;
In Transmit direction for µ-law an additional gain of 1.94 dB is implemented
automatically, in the companding block (CMP). This additional gain has to be considered
at all gain calculations, and reduces possible AX-gain.
A 0 dBm044)) signal is equivalent to 1.095 [1.0906] Vrms. A + 3.14 [3.17] dBm0 signal is
equivalent to 1.57 Vrms which corresponds to the overload point of 2.223 V
(A-law,[µ-law]).
When the gain in the receive path is set at 0 d B, an 1014 H z PCM sinewav e input with
a level 0 dBm0 will correspond to a voltage of 1.095 Vrms at A-Law (1.0906 V µ-Law) at
the analog output.
When the gain in the transmit path is set at 0 dB, an 1014 Hz sine wave signal with a
voltage of 1.095 Vrms A-Law (1.0906 V µ-Law ) will correspond to a level of 0 dBm0 at
the PCM output.
1) RL, CL forms the load on VOUT
2) Cons ider, in a complete System, AR = AR 1 + AR2 + FRR + R1
3) Consider, in a complete System, AX = AX1 + AX2 + FRX
4) The ab s olute powe r level in deci bels refer red to th e PCM int erface levels.
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 58 2000-02-08
Table 3 Transmission Characteristics
Parameter Symbol Limit Values Unit
min. typ. max.
Gain absolute (AGX = AGR = 0)
TA=25°C; VDD =5V
TA=0–70 °C; VDD =5V±5%
G–0.15
–0.25 ±0.10 + 0.15
+0.25 dB
dB
Gain absolute (AGX = 6.02 dB,
AGR = –6.02 dB)
TA=25°C; VDD =5V
TA=0–70 °C; VDD =5V±5%
G
–0.15
–0.25 ±0.10 + 0.15
+0.25 dB
dB
Harmoni c distortion, 0 dB m0;
f= 1000 Hz; 2nd,3
rd order HD –50 –44 dB
Intermodulation1) R2
R3 IMD
IMD –46
–56 dB
dB
Crosstalk 0 dBm0; f= 200 Hz to 3400 Hz
any combination of direction and channel CT –85 –80 dB
Idle channel noise,
transmit, A-law, psophometric VIN =0V
transmit, µ-law, C-message VIN =0V
receive, A-law, psophometric idle code + 0
receive, µ-law, C-message idle code + 0
NTP
NTC
NRP
NRC
–85
5
–67.4
17.5
–78.0
12.0
dBm0p
dBmc
dBm0p
dBmc
1) Using equal-level, 4-tone method (EIA) at a composite level of –13 dBm0 with frequencies in the range
between 300 Hz and 3400 Hz.
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 59 2000-02-08
8.1 Frequency Response
Figure 13 Receive: Reference Frequency 1 kHz, Input Signal Level 0 dBm0
Figure 14 Transmit: Reference Frequency 1 kHz, Input Signal Level 0 dBm0
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 60 2000-02-08
8.2 Group Delay
Maximum delays when the SICOFI-4 is operating with H(TH) = H(IM) = 0 and
H(FRR) = H(FRX) = 1 including delay through A/D- and D/A converters. Specific filter
programming may cause additional group delays.
Group Delay deviations stay within the limits in the figures below.
Figure 15 Group Delay Distortion Transmit: Input Signal Level 0 dBm0
Table 4 Group Delay Absolute Values: Input signal level 0 dBm0
Parameter Symbol Limit Values Unit Reference
min. typ. max.
Transmit delay DXA 300. µs
Recei ve dela y DRA 250 µs
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 61 2000-02-08
Figure 16 Group Delay Distortion Receive: Input Signal Level 0 dBm01)
1) HPR is switched on: reference point is at tGmin
HPR is s w i t c hed off: reference is at 1.5 kHz
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 62 2000-02-08
8.3 Out-of-Band Signals at Analog Input
With an 0 dBm0 out-of-band sine wave signal with frequency f (<< 100 Hz or 3.4 kHz to
100 kHz) a ppli ed to the ana log inp ut, th e le vel of any resulting frequ enc y c omp one nt at
the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference
signal at the analog input1).
1) Poles at 12 k H z ± 150 Hz and 16 kHz ± 150 Hz are provided
3.4 … 4.0 kHz: X 14–π4000 f–
1200
---------------------
sin 1–
=
4,0 … 4.6 kHz:
·X18–π4000 f–
1200
---------------------
sin 7
9
---
–
=
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 63 2000-02-08
8.4 O ut-of-Band Signals at Analog Output
With a 0 dBm0 sine wave with frequency f (300 Hz to 3.99 kHz) applied to the digital
input, the l eve l of any resulti ng out-of -band si gna l at the analog output w ill st ay at le ast
X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
3.4 … 4.6 kHz: X 14–π4000 f–
1200
---------------------
sin 1–
=
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 64 2000-02-08
8.5 Out of Band Idle Channel Noise at Analog Output
With an idle code applied to the digital input, the level of any resulting out-of-band power
spectral density (measured with 3 kHz bandwidth) at the analog output, will be not
greater than the limit curve shown in the figure below.
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 65 2000-02-08
8.6 Overload Compression
Figure 17 µ-Law, Transmit: measured with sine wave f = 1014 Hz.
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 66 2000-02-08
8.7 Gain Tracking (receive or transmit)
The gain deviations stay within the limits in the figures below.
Figure 18 Gain Tracking: (measured with sine wave f = 1014 Hz
(reference level is 0 dBm0)
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 67 2000-02-08
8.8 Total Distortion
The signal to distortion ratio exceeds the limits in the following figure.
8.8.1 Total Distortion Measured with Sine Wave
Figure 19 Receive or Transmit: measured with sine wave f = 1014 Hz
(C-message weighted for µ-law, psophometricaly weighted for A-law)
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 68 2000-02-08
8.8.2 Total Distortion Measured with Noise According to CCITT
Figure 20 Receive
Figure 21 Transmit
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 69 2000-02-08
8.9 Single Frequency Distortion
An input signal with its frequency swept between 0.3 to 3 kHz for the receive path, or 0 to
12 kH z fo r the trans mit path, an y g enera ted output signal w ith oth er freq uen cy than the
input frequency will stay 28 dB below the maximum input level of 0 dBm0.
Receive Transmit
Frequency max. Input Level Frequency max. Input Level
300 Hz to 3.4 kHz 0 dBm0 0 to 12 kHz 0 dBm 0
SICOFI-4
PEB 2465
Transmission Characteristics
Data Sheet 70 2000-02-08
8.10 Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group
delay - deviations inherent to the SICOFI-4 A/D- and D/A-converters as well as to all
external components used on a line card (SLIC, OP’s etc.)
Measurement of SICOFI-4 Transhybrid-Loss: A 0 dBm0 sine wave signal and a
frequency in the range between 300 - 3400 Hz is applied to the digital input. The resulting
analog output signal at pin VOUT is directly connected to VIN, e.g. with the SICOFI-4
testmode “Digital Loop Back via Analog Port”. The pr ogr amm able fil ters FRR, AR, FR X,
AX and IM are disabled, the balancing filter TH is enabled with coefficients optimized for
this configuration (VOUT =VIN).
The resultin g ec ho measured a t the digita l ou tpu t is at lea st X dB below the l eve l of the
digital input signal as shown in the table below. (Filter coefficients will be provided)
The listed values for THL correspond to a typical variation of the signal amplitude
and -delay in the analog blocks.
∆amplitude= typ ±0.15 dB
∆delay = typ ±0.5 µs
Parameter Symbol Limit Values Unit Test Condition
min. typ.
Transhybrid Loss at 300 Hz THL300 27 40 dB TA=25°C; VDD =5V
Transhybrid Loss at 500 Hz THL500 33 45 dB TA=25°C; VDD =5V
Transhybrid Loss at 2500 Hz THL2500 29 40 dB TA=25°C; VDD =5V
Transhybrid Loss at 3000 Hz THL3000 27 35 dB TA=25°C; VDD =5V
Transhybrid Loss at 3400 Hz THL3400 27 35 dB TA=25°C; VDD =5V
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 71 2000-02-08
9 Electrical Characteristics
9.1 Absolute Maximum Ratings
Note: Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
The liste d characteristic s are ensured ov er the operating ra nge of the integ rated
circuit. Typ ical characte ristics spec ify mean values expected over the produc tion
spread. If not otherwis e specifi ed, typical charact eristics app ly at TA = 25°C and
the given supply voltage.
Parameter Symbol Limit Values Unit Test Condition
min. max.
VDD referred to GNDD −0.3 7.0 V
GNDA to GNDD −0.6 0.6 V
Analog input and output voltage
referred to VDD =5V;
referred to GNDA = 0 V −5.3
−0.3 0.3
5.3 V
V
All digital input voltages
referred to GNDD = 0 V;
(VDD =5V)
referred to VDD =5V;
(GNDD = 0 V)
−0.3
−5.3
5.3
0.3
V
V
DC input and output current at
any input or output pin (free from
latch-up)
10 mA
Storage temperature
Ambient temperature under bias TSTG
TA
−60
−10 125
80 °C
°C
Power dissipation (package) PD1W
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 72 2000-02-08
9.2 Operating Range
Note: In the operating range the functions given in the circuit description are fulfilled.
TA=0to70°C; VDD =5 V±5 %; GNDD = 0 V; GNDA = 0 V
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
VDD supply current
standby
operating (4 channels)
IDD 1.2
27 1.5
40 mA
mA
Power supply rejection
of either supply/direction
receive VDD guaranteed
receive VDD target value
PSRR
30
14
30
dB
dB
dB
ripple: 0 to 150 kHz,
70 mVrms
measured: 300 Hz to
3.4 kHz
measured: at f: 3.4 to
150 kHz
Power dissipation standby PDS 15 20 mW
Power dissipation operating PDo1 75 110 mW 1 channel operating
Power dissipation operating PDo2 100 140 mW 2 channels operating
Power dissipation operating PDo3 120 175 mW 3 channels operating
Power dissipation operating PDo4 140 210 mW 4 channels operating
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 73 2000-02-08
9.3 Digital Interface
TA=0to70°C; VDD =5V±5%;GNDD=0V;GNDA=0V
All input-pins, with exception of the RESET-pin, have a TTL-input characteristic.
Parameter Symbol Limit Values Unit Test Condition
min. max.
Low-input voltage VIL −0.3 0.8 V
High-input voltage VIH 2.0 V
Low-output vol tage VOL 0.45 V IO = −5 mA
Low-output vol tage DU-pin VOL 0.45 V IO = −7 mA,
RL=1 kΩ
High-output voltage VOH 4.4 V IO = 5 mA
Input leakage current IIL ± 1µA−0.3 ≤ VIN ≤ VDD
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 74 2000-02-08
9.4 Analog Interface
9.5 Reset Timing
To reset the SICOFI-4 to basic setting mo de, positive pulses applie d to pin RS have to
be higher than 2.4 V (CMOS-Schmitt-Trigger Input) and longer than 3 µs. Signals
shorter than 1 µs will be ignored.
9.5.1 IOM-2 Interface Timing
9.5.2 4 -MHz Op eration Mode (Mode = 1)
TA=0to70°C; VDD =5V±5 %; GNDD = 0 V; GNDA = 0 V
Parameter Sym bol Limit Values Unit Test Condition
min. typ. max.
Analog input resistance Ri160 270 480 kΩ
Analog output resistance Ro10 Ω
Analog output load RL
CL
20 20 kΩ
pF
Input leakage current IIL ±0.1 ±1.0 µA0 ≤ VIN ≤ VDD
Input voltage range (AC) VIR ± 2.223 V
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 75 2000-02-08
9.5.3 2 -MHz Op eration Mode (Mode = 0)
Table 5 Switching Characteristics
Parameter Symbol Limit Values Unit
min. typ. max.
Period DCL ‘fast’ mode 1)
1) DCL = 4096 kHz: tFSC = 512 × tDCL
tDCL 1/4096 kHz
DCL Du ty Cycle 4 0 60 %
Period FSC1) tFSC 125 µs
FSC setup time tFSC_S 70 tDCLh ns
FSC hold time tFSC_H 40 ns
DD data in setup time tDD_S 20 ns
DD data in hold time tDD_H 50 ns
DU data out delay2)
2) Depe ndin g on Pull up resi s tor (typical 1 kΩ), DU and DD are “open drain”-lines.
tdDU 150 320 ns
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 76 2000-02-08
Table 6 Switching Characteristics
Parameter Symbol Limit Values Unit
min. typ. max.
Period DCL ‘slow’ mode1) tDCL 1/2048 kHz
DCL Du ty Cycle 4 0 60 %
Period FSC1) tFSC 125 µs
FSC setup time tFSC_S 70 tDCLh ns
FSC hold time tFSC_H 40 ns
DD data in setup time tDD_S 20 ns
DD data in hold time tDD_H 50 ns
DU data out delay2) tdDU 150 175 ns
1) DCL = 2048 kHz: tFSC = 256 × tDCL
2) Depe ndin g on Pull up resi s tor (typical 1 kΩ) , DU and DD are “open drain”-lines.
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 77 2000-02-08
9.6 IOM-2 Command/Indication Interface Timing
9.6.1 4 -MHz Op eration Mode (Mode = 1)
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 78 2000-02-08
9.6.2 2 -MHz Op eration Mode (Mode = 0)
Table 7 Switching Characteristics
Parameter Symbol Limit Values Unit
min. typ. max.
Command out delay tdCout 150 250 ns
Command out high impedance tdCZ 150 250 ns
Command out active tdCA 150 250 ns
Indication in setup time tlin_s 50 ns
Indication in hold time tlin_h 100 ns
SICOFI-4
PEB 2465
Electrical Characteristics
Data Sheet 79 2000-02-08
9.7 Detector Select Timing
Table 8 Switching Characteristics
Parameter Symbol Limit Values Unit
min. typ. max.
Detector select high time tLGKMh 125 µs
Detector se lect repeat tLGKM 1 … 14 ms
Indication in setup time tlin_s 50 ns
Indication in hold time tlin_h 100 ns
SICOFI-4
PEB 2465
Appendix
Data Sheet 80 2000-02-08
10 Appendix
10.1 IOM-2 Interface Monitor Transfer Protocol
10.1.1 Mon itor Channel Operation
The monitor channel is used for the transfer of maintenance information between two
functional blocks. Using two monitor control bits (MR and MX) per direction, the data are
transferred in a complete handshake procedure. The MR and MX bits in the fourth octet
(C/I channel) of the IOM-2 frame are used for the handsha ke procedure of the monito r
channel.
The monitor channel transmission operates on a pseudo-asynchronous basis:
–Data transfer (bits) on the bus is synchronized to Frame Sync FSC
–Data flow (bytes) are asynchronously controlled by the handshake procedure.
For example: Data is placed onto the DD-Monitor-Channel by the Monitor-transmitter of
the master device (DD-MX-Bit is activated i.e. set to ‘0’). This data transfer will be
repeated within each frame (125 µs rate) until it is acknowledged by the SICOFI-4
Monitor-receiver by setting the DU-MR-bit to ‘0’, which is checked by the Monitor-
transmitter of the master device. Thus, the data rate is not 8-kbytes/sec.
SICOFI-4
PEB 2465
Appendix
Data Sheet 81 2000-02-08
10.1.2 Mon itor Handshake Procedure
The monitor channel works in 3 states
–idle stat e: A pair of inactive (set to ‘1’) MR- and MX-bits during two or more
consecutive frames: End of Message (EOM)
–sending state: MX-bit is activated (set to ‘0’) by the Monitor-transmitter, together
with data-bytes (can be changed) on the Monitor-channel
–acknowledging: MR-bit is set to active (set to ‘0’) by the Monitor-receiver, together
with a data-byte remaining in the Monitor-channel.
A start of t rans mis sio n is in itia ted b y a Mon itor-tra nsm itte r in s ending out an a cti ve M X-
bit together with the first byte of d ata (the address of the receiver) to be transmitted in
the Monitor-chann el.
This state remains until the addressed Monitor-Receiver acknowledges the received
data by sending out an active MR-bit, which means that the data-transmission is
repeated ea ch 125 µs fram e (minimum is one repetition). During this time the Monitor-
transmitter evaluates the MR-bit.
Flow control, means in the form of transmission delay, can only take place when the
transmitters MX and the receivers MR bit are in active state.
Since the receiv er is able to receive the monitor data at leas t twice (in two conse cutive
frames), it is able to check for data errors. If two different bytes are received the receiver
will wait for the receipt of two identical successive bytes (last look function).
A collision resolution mechanism (check if an other device is trying to send data during
the same time) is implemented in the transmitter. This is done by looking for the inactive
(‘1’) phase of the MX-bit and making a per bit collision check on the transmitted monitor
data (check if transmitted ‘1’s are on DU/DD-line; DU/DD-line are open-drain lines).
Any abort leads to a reset of the SICOFI-4 command stack, the device is ready to receive
new commands.
To obtain a maximum speed data transfer, the transmitter anticipates the falling edge of
the receivers ackn ow ledg men t.
Due to the inherent programming structure, duplex operation is not possible. It is not
allowed to send any data to the SICOFI-4, while transmission is active.
SICOFI-4
PEB 2465
Appendix
Data Sheet 82 2000-02-08
10.1.3 State Diagram of the SICOFI-4 Monitor Transmitter
MR … MR - bit received on DD-line
MX … MX - bit calculated and expected on DU-line
MXR … MX - bit sampled on DU-line
CLS … Collision within the monitor data byte on DU-line
RQT … Request for transmission form internal source
ABT … Abort request/indication
• … logical AND
+ … logical OR
SICOFI-4
PEB 2465
Appendix
Data Sheet 83 2000-02-08
10.1.4 State Diagram of the SICOFI-4 Monitor Receiver
MR … MR - bit calculated and transmitted on DU-line
MX … MX - bit received data downstream (DD-line)
LL … Last lock of monitor byte received on DD-line
ABT … Abort indication to internal source
• … logical AND
+ … logical OR
SICOFI-4
PEB 2465
Appendix
Data Sheet 84 2000-02-08
10.1.5 Monitor Channel Data Structure
The monitor channel is used for the transfer of maintenance information between two
functional blocks. By use of two monitor control bits (MR and MX) per direction, the data
are transferred in a complete handshake procedure.
Address Byte
Messages to and from the SICOFI-4 are started with the following Monitor byte:
Thus providing information for two voice channels, the SICOFI-4 is one device on one
IOM-2 timeslot. Monitor data for a specific voice channel is selected by the SICOFI-4
specific command (SOP or COP).
Identification Command
In order to be able to unambiguously identify different devices by software, a two byte
identification command is defined for analog lines IOM-2 devices.
Each device will then respond with its specific identification code. For the SICOFI-4 this
two byte identification code is:
Each byte is transferred at least twice (in two consecutive frames).
Bit76543210
10000001
10000000
00000000
10000000
10000010
SICOFI-4
PEB 2465
Appendix
Data Sheet 85 2000-02-08
10.2 IOM-2 Interface Programming Procedure
Example for a typical IOM-2 Interface programming procedure, consisting of
identification request and answer, a SOP Write command with three byte following, and
SOP Read to verify the programming.
Frame Data down Data up
Monitor MR/MX Monitor MR/MX
1 11111111 11 11111111 11
2IDRQT. 1
st byte 10 11111111 11
3IDRQT. 1
st byte 10 11111111 01
4IDRQT. 2
nd byte 11 11111111 01
5IDRQT. 2
nd byte 10 11111111 11
6 11111111 11 11111111 01
7 11111111 11 IDANS. 1st byte 10
8 11111111 01 IDANS. 1st byte 10
9 11111111 01 IDANS. 2nd byte 11
10 11111111 11 IDANS. 2nd byte 10
11 11111111 01 11111111 11
12 Address 10 11111111 11
13 Address 10 11111111 01
14 SOP Write 11 11111111 01
15 SOP Write 10 11111111 11
16 CR3 11 11111111 01
17 CR3 10 11111111 11
18 CR2 11 11111111 01
19 CR2 10 11111111 11
20 CR1 11 11111111 01
21 CR1 10 11111111 11
22 SOP Read 11 11111111 01
23 SOP Read 10 11111111 11
24 11111111 11 11111111 01
25 11111111 11 Address 10
26 11111111 01 Address 10
SICOFI-4
PEB 2465
Appendix
Data Sheet 86 2000-02-08
IDRQT … identification request (80H, 00H)
IDANS … answer to identification request (80H, 82H)
Address …SICOFI-4 specific address byte (81H)
CRx … Data for/from configuration register x.
27 11111111 01 CR3 11
28 11111111 11 CR3 10
29 11111111 01 CR2 11
30 11111111 11 CR2 10
31 11111111 01 CR1 11
32 11111111 11 CR1 10
33 11111111 01 11111111 11
Frame Data down Data up
Monitor MR/MX Monitor MR/MX
SICOFI-4
PEB 2465
Appendix
Data Sheet 87 2000-02-08
10.3 Test Features
10.3.1 Bou ndary Scan
General
The SICOFI-4 provides fully IEEE Std. 1149.1 compatible boundary scan support
co nsisting o f:
–a complete boundary scan (digital pins)
–a test access port controller (TAP)
–four dedicated pins (TCK, TMS, TDI, TDO)
–a 32 bit ICODE register
All SICOFI-4 digital pins expect power supply VDDD and ground GNDD are included in
the boundary sc an. Depen din g on the pin func tio nali ty one, two or t hree boun dary ce lls
are provided.
When the TAP controller is in the appropriate mode, data is shifted into/out of the
boundary scan via the pins TDI/TDO controlled by the clock applied to pin TCK.
Pin Type Number of Boundary
Scan Cells Usage
Input 1 Input
Output 2 Output, enable
I/O 3 Input, output, enable
SICOFI-4
PEB 2465
Appendix
Data Sheet 88 2000-02-08
The SICOFI-4 pins are included in the following sequence in the boundary scan:
Pin No. Pin Name Type
57 MODE I
59 TSS1 I
60 TSS0 I
61 SI3_2 I
62 SI3_1 I
63 SI3_0 I
64 SB3_1 I/O
1 SB3_0 I/O
2SO3_2O
3SO3_1O
4SO3_0O
13 SO4_0 O
14 SO4_1 O
15 SO4_2 O
16 SB4_0 I/O
17 SB4_1 I/O
18 SI4_0 I
19 SI4_1 I
20 SI4_2 I
21 LGKM1 O
22 RESET I
24 DD I
25 DU O (open drain)
26 DCL I
27 FSC I
28 LGKM0 O
29 SI1_2 I
30 SI1_1 I
31 SI1_0 I
32 SB1_1 I/O
33 SB1_0 I/O
SICOFI-4
PEB 2465
Appendix
Data Sheet 89 2000-02-08
10.3.2 The TAP-Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE Std. 1149.1. Transitions on pin TMS (Test Mode Select) cause the
TAP controller to perform a state change. According to the standard definition five
instructions are executable:
34 SO1_2 O
35 SO1_1 O
36 SO1_0 O
45 SO2_0 O
46 SO2_1 O
47 SO2_2 O
48 SB2_0 I/O
49 SB2_1 I/O
50 SI2_0 I
51 SI2_1 I
52 SI2_0 I
Pin No. Pin Name Type
SICOFI-4
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Appendix
Data Sheet 90 2000-02-08
SICOFI-4
PEB 2465
Appendix
Data Sheet 91 2000-02-08
EXTEST: Is used to examine the board interconnections.
INTEST: Supports internal chip testing (is the default value of the
instruction register)
SAMPLE/PRELOAD: Pro v ides a snap -shot of the pin level duri ng normal operation,
or
is used to preload the boundary scan with a test vector
ICODE: The 32 bit identification register is serially read out via TDO. It
contains a version number (4 bit), a device code (16 bit) and
the manufacture code (11bit). The LSB is fixed to ‘1’.
For the SICOFI-4 V2.2 and V2.3 the Code is:
‘0011 0000 0000 0001 0101 0000 1000 001 1’
TAP_TEST1 39 bit field for selecting operation
(Level Metering Offset, Loops, Tone Generator…)
TAP_TEST2: Wait for Level Metering result ready (should be > t.b.d. mS)
TAP_TEST5: Level Metering Data output (1 bit result of Level Metering per
channel)
TAP_TEST4: Level Metering Operation is switched off
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle
Code Instruction Function
0000 EXTEST External testing
0001 INTEST Internal testing
0010 SAMPLE/
PRELOAD Snap-shot testing
0011 ICODE Reading ID code
0100 Tap_Test 1 Configuration for Level Metering
0101 Tap_Test 2 Wait for result
1000 Tap_Test 5 Serial testdata output (Level Metering Results)
0111 Tap_Te st 4 Swi tch off Test
11xx BYPASS Bypass operation
SICOFI-4
PEB 2465
Appendix
Data Sheet 92 2000-02-08
10.3.3 Level Metering Function
The Level Metering Function is a functional selftest (available per channel), which allows
selftest of the chip (digital, or digital and analogue), and also selftest of the board
(including the SLIC).
An external or internally generated sine-wave signal is fed to the receive path. After
switching a loop (intern al or external via the SLIC) to the Transmit-pa th the return level
is measured and compared to a programmable offset value. The result of this operation
(greater or smaller than offset) can be read out via the IOM-2 interface (bit LMR in
configur ation register CR2).
There is a single 8 bit Offset-Register available for all the 4 channels. This offset register
can be accessed as XR4 with a XOP-Command (Field LSEL = 100)
This register contains the 2’s complement offset value for the level metering function.
Bit76543210
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
SICOFI-4
PEB 2465
Appendix
Data Sheet 93 2000-02-08
Figure 22 Block Diagram
(For further information, an application-note describing the calculation of the offset value
and the sensitivity, is available)
SICOFI-4
PEB 2465
Appendix
Data Sheet 94 2000-02-08
10.3.4 Using the Level Metering Function
Task
An external sine wave (applied to the analog input pin VIN ) or an internally generated
sine wave signal (via tone generator TG1 or via test loops) is send to the SICOFI-4
transmit pat h. This signal will be rectif ied and the power of this signal will be comp ared
to the programmabl e offset value of the lev el metering func tion. If the measured power
exceeds a certain value the LMR bit of the register CR2 is set to ‘1’.
In the appendix you will find a printout of the Track file to test the SICOFI-4 level metering
function.
The following steps show how to detect a sine wave with a frequency of 2 kHz and a
PCM level L = 0 dB (like measured with the PCM4 in the A/D measurement).
Step 1
The SICOFI-4 extended register XR4 holds the offset value for the level metering
function. With the QSICOS utility program ‘Calculation of Level Metering Function’ the
programming byte for this register XR4 can be calculated. In our case the Level L will be
0 dB.
Bytes for Level Metering Register XR4: 71
Step 2
The level metering function is always used together with a bandpass filter. The
programming of this bandpass filter has to be done by programming the tone-generator
coefficients of the tone generator TG2. (During Level Metering Function enabled, TG2 is
not available). For this example the coefficients of the TG2 for a frequency of f=2000Hz
have to be calculated using the QSICOS utility program ‘Calculate Tone Generator
Coefficients’:
Bytes for Tone Generator 2 (0D): 00, 80, 40, 09
Step 3
The SICOFI-4 extended register XR4 has to be programmed.
Step 4
In the SICOFI-4 configuration register CR2 the level metering bit LM has to be set to ‘1’
and the programmed frequency for the tone generator 2 has to chosen by setting the
PTG2 bit to ‘1’.
Example for writing the CR2 register: 0 0 1 0 0 0 1 0 = 22H (A-Law is select ed)
SICOFI-4
PEB 2465
Appendix
Data Sheet 95 2000-02-08
Step 5
After sending the sine wave in the SICOFI-4 transmit path the result of the Level
Metering function will be present in the LMR bit of the configuration register CR2.
Examples for reading back the CR2 register:
0 0 1 0 0 0 1 0 = 22H Level was lower than reference
0 0 1 1 0 0 1 0 = 32H Level was higher than reference
Step 6
By programming different levels for the level metering function the actual PCM coded
level can be found. Also a change of the AX1 gain filter will change the PCM level in the
transmit path.
If an analog signal is applied to the SICOFI-4 analog input, the level of this analog signal
can be c alc ula ted. To ca lcu late th e anal og level, th e g ain s ettin g of t he SICOFI-4 fi lters
together with the 0 dBm0 reference voltage have to be taken into account.
SICOFI-4
PEB 2465
Appendix
Data Sheet 96 2000-02-08
10.4 Programm in g the SICOFI-4 Tone Gener ators
Two indepe ndent Tone Gen erators are availa ble per channel . When one or both tone-
generators are switched on, the voice signal is switched off automatically for the selected
voice channel. To make the generated signal sufficient for DTMF, a programmable
bandpass-filter is included. The default frequency for both tone generators is 1000 Hz.
The QSICOS-program contains a program for generating coefficients for variable
frequencies.
Byte sequences for programming both the tone generators and the bandpass-filters:
The resulting signal amplitude can be set by transmitting the AR1 and AR2 filters. By
switching a ‘digital loop’ the generated sine-wave signal can be fed to the transmit path.
Frequency Command Byte 1 Byte 2 Byte 3 Byte 4
697 Hz 0C/0D1)
1) 0C is used for programming Tone Generator 1, in channel 1(3).
0D is used for programming Tone Generator 2, in channel 1(3).
0A 33 5A 2C
770 Hz 0C/0D1) 12 33 5A C3
852 Hz 0C/0D1) 13 3C 5B 32
941 Hz 0C/0D1) 1D 1B 5C CC
1209 Hz 0C/0D1) 32 32 52 B3
1336 Hz 0C/0D1) EC 1D 52 22
1477 Hz 0C/0D1) AA AC 51 D2
800 Hz 0C/0D1) 12 D6 5A C0
950 Hz 0C/0D1) 1C F0 5C C0
1008 Hz 0C/0D1) 1A AE 57 70
2000 Hz 0C/0D1) 00 80 50 09
SICOFI-4
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Proposed Test Circuit
Data Sheet 97 2000-02-08
11 Proposed Test Circuit
SICOFI-4
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Board Layout Recommendation
Data Sheet 98 2000-02-08
12 Board Layout Recommendation
12.1 Board Layout
Keep in mi nd that inside the SICOFI-4 all the different VDD-supplie s are conn ected via
the substrate of the chip, and the areas connected to different grounds are separated on
chip.
a) Separate all digital supply lines from analog supply lines as long as possible.
b) Use a separate GND-connection for the capacitors which are filtering the Reference
voltage (220 nF ceramic-capacitor at VH12/VH34).
c) Don’t use a common ground-plane under the SICOFI-4.
d) Use a large ground-plane (distant from the SICOFI-4) and use different ground lines
for connecting the SICOFI-4: one common analog ground and a separate digital
ground.
12.2 Filter Ca pacitors
a) To achieve a good filtering for the high frequency band, place SMD ceramic-
capacitors with 100 nF from VDDA12 and VDDA34 to GNDA.
b) One 100 nF SMD ceramic-capacitor is needed to filter the digital sup ply (VDDD to
GNDD).
c) Use 220 nF ceramic-capacitors to connect VH12 and VH34 to analog ground.
d) Place all filter capacitors as close as possible to the SICOFI-4 (most important!!!).
e) Use one central Tantalum-capacitor with about 1 µF to 10 µF to block VDD to GND.
SICOFI-4
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Board Layout Recommendation
Data Sheet 99 2000-02-08
SICOFI-4
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Package Outlines
Data Sheet 100 2000-02-08
13 Package Outlines
Plastic Package, P-MQFP-64 (SMD)
(Plastic Metric Quad Flat Package)
GPM0525
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Dimensions in mm
SMD = Surface Mounted Device
SICOFI-4
PEB 2465
Package Outlines
Data Sheet 101 2000-02-08
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