MC33501SNT1G - ON SEMICONDUCTOR

July, 2006 − Rev. 10 1Publication Order Number:

MC33501/D

MC33501, MC33503

1.0 V, Rail−to−Rail, Single

Operational Amplifiers

The MC33501/503 operational amplifier provides rail−to−rail

operation on both the input and output. The output can swing within 50

mV of each rail. This rail−to−rail operation enables the user to make

full use of the entire supply voltage range available. It is designed to

work at very low supply voltages (1.0 V and ground), yet can operate

with a supply of up to 7.0 V and ground. Output current boosting

techniques provide high output current capability while keeping the

drain current of the amplifier to a minimum.

Features

•Low Voltage, Single Supply Operation (1.0 V and Ground to 7.0 V

and Ground)

•High Input Impedance: Typically 40 fA Input Bias Current

•Typical Unity Gain Bandwidth @ 5.0 V = 4.0 MHz,

@ 1.0 V = 3.0 MHz

•High Output Current (ISC = 40 mA @ 5.0 V, 13 mA @ 1.0 V)

•Output Voltage Swings within 50 mV of Both Rails @ 1.0 V

•Input Voltage Range Includes Both Supply Rails

•High Voltage Gain: 100 dB Typical @ 1.0 V

•No Phase Reversal on the Output for Over−Driven Input Signals

•Typical Input Offset of 0.5 mV

•Low Supply Current (ID = 1.2 mA/per Amplifier, Typical)

•600 W Drive Capability

•Extended Operating Temperature Range (−40 to 105°C)

•Pb−Free Packages are Available

Applications

•Single Cell NiCd/Ni MH Powered Systems

•Interface to DSP

•Portable Communication Devices

•Low Voltage Active Filters

•Telephone Circuits

•Instrumentation Amplifiers

•Audio Applications

•Power Supply Monitor and Control

•Transistor Count: 98

SOT23−5

SN SUFFIX

CASE 483

MARKING

DIAGRAM

1

5

Device Package Shipping†

ORDERING INFORMATION

MC33501SNT1 SOT23−5 3000 Tape & Ree

l

MC33503SNT1 SOT23−5 3000 Tape & Ree

l

MC33501

MC33503

15

2

34

Non−Inverting

Input

Output

VCC

VEE

Inverting Input

(Top View)

+−

15

2

34

Non−Inverting

Input

Output

VEE

VCC

Inverting Input

(Top View)

+−

PIN CONNECTIONS

http://onsemi.com

MC33501SNT1G SOT23−5

(Pb−Free) 3000 Tape & Ree

l

MC33503SNT1G SOT23−5

(Pb−Free) 3000 Tape & Ree

l

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

s

Brochure, BRD8011/D.

1

5

xxx AYWG

G

xxx = AAA; MC33501

AAB; MC33503

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

MC33501, MC33503

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2

Figure 1. Simplified Block Diagram

This device contains 98 active transistors per amplifier.

Inputs Input

Stage Outputs

Buffer with 0 V

Level Shift

Saturation

Detector

Offset

Voltage

Trim

Base

Current

Boost

Base

Current

Boost

Output

Stage

MAXIMUM RATINGS

Rating Symbol Value Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply Voltage (VCC to VEE)

ÁÁÁÁÁÁÁ

VS

ÁÁÁÁÁÁÁ

7.0

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ESD Protection Voltage at any Pin

Human Body Model

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

VESD

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

2000

ÁÁÁ

Á

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Voltage at Any Device Pin

ÁÁÁÁÁÁÁ

VDP

ÁÁÁÁÁÁÁ

VS ±0.3

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Dif ferential Voltage Range

ÁÁÁÁÁÁÁ

VIDR

ÁÁÁÁÁÁÁ

VCC to VEE

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common Mode Input Voltage Range

ÁÁÁÁÁÁÁ

VCM

ÁÁÁÁÁÁÁ

VCC to VEE

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Short Circuit Duration

ÁÁÁÁÁÁÁ

tS

ÁÁÁÁÁÁÁ

Note 1

ÁÁÁ

s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Maximum Junction Temperature

ÁÁÁÁÁÁÁ

TJ

ÁÁÁÁÁÁÁ

150

ÁÁÁ

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Storage Temperature Range

ÁÁÁÁÁÁÁ

Tstg

ÁÁÁÁÁÁÁ

−65 to 150

ÁÁÁ

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Maximum Power Dissipation

ÁÁÁÁÁÁÁ

PD

ÁÁÁÁÁÁÁ

Note 1

ÁÁÁ

mW

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended O p e r a t i n g Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.

2. ESD data available upon request.

MC33501, MC33503

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3

DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, RL to VCC/2, TA = 25°C, unless

otherwise noted.)

Characteristic Symbol Min Typ Max Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Offset Voltage (VCM = 0 to VCC)

ÁÁÁÁÁ

VIO

ÁÁÁÁ

ÁÁÁ

mV

VCC = 1.0 V

TA = 25°C −5.0 0.5 5.0

TA = −40° to 105°C −7.0 − 7.0

VCC = 3.0 V

TA = 25°C −5.0 0.5 5.0

TA = −40° to 105°C −7.0 − 7.0

VCC = 5.0 V

TA = 25°C −5.0 0.5 5.0

TA = −40° to 105°C −7.0 − 7.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Offset Voltage Temperature Coefficient (RS = 50 W)

ÁÁÁÁÁ

DVIO/DT

ÁÁÁÁ

−

ÁÁÁÁ

8.0

ÁÁÁÁ

−

ÁÁÁ

mV/°C

TA = −40° to 105°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current (VCC = 1.0 to 5.0 V)

ÁÁÁÁÁ

I IIB I

ÁÁÁÁ

−

ÁÁÁÁ

0.00004

ÁÁÁÁ

1.0

ÁÁÁ

nA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common Mode Input Voltage Range

ÁÁÁÁÁ

VICR

ÁÁÁÁ

VEE

ÁÁÁÁ

−

ÁÁÁÁ

VCC

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Large Signal Voltage Gain

ÁÁÁÁÁ

AVOL

ÁÁÁÁ

ÁÁÁ

kV/V

VCC = 1.0 V (TA = 25°C)

RL = 10 kW25 100 −

RL = 1.0 kW5.0 50 −

VCC = 3.0 V (TA = 25°C)

RL = 10 kW50 500 −

RL = 1.0 kW25 100 −

VCC = 5.0 V (TA = 25°C)

RL = 10 kW50 500 −

RL = 1.0 kW25 200 −

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Voltage Swing, High (VID = ±0.2 V)

ÁÁÁÁÁ

VOH

ÁÁÁÁ

ÁÁÁ

V

VCC = 1.0 V (TA = 25°C)

RL = 10 kW0.9 0.95 −

RL = 600 W0.85 0.88 −

VCC = 1.0 V (TA = −40° to 105°C)

RL = 10 kW0.85 − −

RL = 600 W0.8 − −

VCC = 3.0 V (TA = 25°C)

RL = 10 kW2.9 2.93 −

RL = 600 W2.8 2.84 −

VCC = 3.0 V (TA = −40° to 105°C)

RL = 10 kW2.85 − −

RL = 600 W2.75 − −

VCC = 5.0 V (TA = 25°C)

RL = 10 kW4.9 4.92 −

RL = 600 W4.75 4.81 −

VCC = 5.0 V (TA = −40° to 105°C)

RL = 10 kW4.85 − −

RL = 600 W4.7 − −

MC33501, MC33503

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4

DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, RL to VCC/2, TA = 25°C, unless

otherwise noted.)

Characteristic UnitMaxTypMinSymbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Voltage Swing, Low (VID = ±0.2 V)

ÁÁÁÁÁ

VOL

ÁÁÁÁ

ÁÁÁ

V

VCC = 1.0 V (TA = 25°C)

RL = 10 kW0.05 0.02 −

RL = 600 W0.1 0.05 −

VCC = 1.0 V (TA = −40° to 105°C)

RL = 10 kW0.1 − −

RL = 600 W0.15 − −

VCC = 3.0 V (TA = 25°C)

RL = 10 kW0.05 0.02 −

RL = 600 W0.1 0.08 −

VCC = 3.0 V (TA = −40° to 105°C)

RL = 10 kW0.1 − −

RL = 600 W0.15 − −

VCC = 5.0 V (TA = 25°C)

RL = 10 kW0.05 0.02 −

RL = 600 W0.15 0.1 −

VCC = 5.0 V (TA = −40° to 105°C)

RL = 10 kW0.1 − −

RL = 600 W0.2 − −

Common Mode Rejection (Vin = 0 to 5.0 V) CMR 60 75 − dB

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply Rejection

ÁÁÁÁÁ

PSR

ÁÁÁÁ

60

ÁÁÁÁ

75

ÁÁÁÁ

−

ÁÁÁ

dB

VCC/VEE = 5.0 V/Ground to 3.0 V/Ground

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Short Circuit Current (Vin Diff = ±1.0 V)

ÁÁÁÁÁ

ISC

ÁÁÁÁ

ÁÁÁ

mA

VCC = 1.0 V

Source 6.0 13 26

Sink 10 13 26

VCC = 3.0 V

Source 15 32 60

Sink 40 64 140

VCC = 5.0 V

Source 20 40 140

Sink 40 70 140

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply Current (Per Amplifier, VO = 0 V)

ÁÁÁÁÁ

ID

ÁÁÁÁ

ÁÁÁ

mA

VCC = 1.0 V − 1.2 1.75

VCC = 3.0 V − 1.5 2.0

VCC = 5.0 V − 1.65 2.25

VCC = 1.0 V (TA = −40 to 105°C) − − 2.0

VCC = 3.0 V (TA = −40 to 105°C) − − 2.25

VCC = 5.0 V (TA = −40 to 105°C) − − 2.5

MC33501, MC33503

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5

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, TA = 25°C, unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Slew Rate (VS = ±2.5 V, VO = −2.0 to 2.0 V, RL = 2.0 kW, AV = 1.0)

ÁÁÁÁÁ

SR

ÁÁÁÁ

ÁÁÁ

V/ms

Positive Slope 1.8 3.0 6.0

Negative Slope 1.8 3.0 6.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gain Bandwidth Product (f = 100 kHz)

ÁÁÁÁÁ

GBW

ÁÁÁÁ

ÁÁÁ

MHz

VCC = 0.5 V, VEE = −0.5 V 2.0 3.0 6.0

VCC = 1.5 V, VEE = −1.5 V 2.5 3.5 7.0

VCC = 2.5 V, VEE = −2.5 V 3.0 4.0 8.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gain Margin (RL =10 kW, CL = 0 pF)

ÁÁÁÁÁ

Am

ÁÁÁÁ

−

ÁÁÁÁ

6.5

ÁÁÁÁ

−

ÁÁÁ

dB

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Phase Margin (RL = 10 kW, CL = 0 pF)

ÁÁÁÁÁ

fm

ÁÁÁÁ

−

ÁÁÁÁ

60

ÁÁÁÁ

−

ÁÁÁ

Deg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Channel Separation (f = 1.0 Hz to 20 kHz, RL = 600 W)

ÁÁÁÁÁ

CS

ÁÁÁÁ

−

ÁÁÁÁ

120

ÁÁÁÁ

−

ÁÁÁ

dB

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Bandwidth (VO = 4.0 Vpp, RL = 1.0 kW, THD ≤1.0%)

ÁÁÁÁÁ

BWP

ÁÁÁÁ

−

ÁÁÁÁ

200

ÁÁÁÁ

−

ÁÁÁ

kHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Total Harmonic Distortion (VO = 4.5 Vpp, RL = 600 W, AV = 1.0)

ÁÁÁÁÁ

THD

ÁÁÁÁ

ÁÁÁ

%

f = 1.0 kHz − 0.004 −

f = 10 kHz − 0.01 −

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Differential Input Resistance (VCM = 0 V)

ÁÁÁÁÁ

Rin

ÁÁÁÁ

−

ÁÁÁÁ

>1.0

ÁÁÁÁ

−

ÁÁÁ

terraW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Differential Input Capacitance (VCM = 0 V)

ÁÁÁÁÁ

Cin

ÁÁÁÁ

−

ÁÁÁÁ

2.0

ÁÁÁÁ

−

ÁÁÁ

pF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Equivalent Input Noise Voltage (VCC = 1.0 V, VCM = 0 V, VEE = GND,

ÁÁÁÁÁ

en

ÁÁÁÁ

ÁÁÁ

nV/√Hz

RS = 100 W)

f = 1.0 kHz − 30 −

Figure 2. Representative Block Diagram

Offset

Voltage

Trim

Output

Voltage

Saturation

Detector

Body

Bias

Clamp

VCC VCC

VCC

IN−

Out

IN+

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6

General Information

The MC33501/503 dual operational amplifier is unique in

its ability to provide 1.0 V rail−to−rail performance on both

the input and output by using a SMARTMOSt process. The

amplifier output swings within 50 mV of both rails and is

able to provide 50 mA of output drive current with a 5.0 V

supply, and 10 mA with a 1.0 V supply. A 5.0 MHz

bandwidth and a slew rate of 3.0 V/ms is achieved with high

speed depletion mode NMOS (DNMOS) and vertical PNP

transistors. This device is characterized over a temperature

range of −40°C to 105°C.

Circuit Information

Input Stage

One volt rail−to−rail performance is achieved in the

MC33501/503 a t the input by using a single pair of depletion

mode NMOS devices (DNMOS) to form a differential

amplifier with a very low input current of 40 fA. The normal

input common mode range of a DNMOS device, with an ion

implanted negative threshold, includes ground and relies on

the body effect to dynamically shift the threshold to a

positive value as the gates are moved from ground towards

the positive supply. Because the device is manufactured in

a p−well process, the body effect coefficient is sufficiently

large to ensure that the input stage will remain substantially

saturated when the inputs are at the positive rail. This also

applies at very low supply voltages. The 1.0 V rail−to−rail

input stage consists of a DNMOS differential amplifier, a

folded cascode, and a low voltage balanced mirror. The low

voltage cascaded balanced mirror provides high 1st stage

gain and base current cancellation without sacrificing signal

integrity. A common mode feedback path is also employed

to enable the offset voltage to track over the input common

mode voltage. The total operational amplifier quiescent

current drop is 1.3 mA/amp.

Output Stage

An additional feature of this device is an “on demand”

base current cancellation amplifier. This feature provides

base drive to the output power devices by making use of a

buffer amplifier to perform a voltage−to−current

conversion. This is done in direct proportion to the load

conditions. This “on demand” feature allows these

amplifiers to consume only a few micro−amps of current

when the output stage is in its quiescent mode. Yet it

provides high output current when required by the load. Th e

rail−to−rail output stage current boost circuit provides

50 mA of output current with a 5.0 V supply (For a 1.0 V

supply output stage will do 10 mA) enabling the operational

amplifier to drive a 600 W load. A buffer is necessary to

isolate the load current effects in the output stage from the

input stage. Because of the low voltage conditions, a

DNMOS follower is used to provide an essentially zero

voltage level shift. This buffer isolates any load current

changes on the output stage from loading the input stage. A

high speed vertical PNP transistor provides excellent

frequency performance while sourcing current. The

operational amplifier is also internally compensated to

provide a phase margin of 60 degrees. It has a unity gain of

5.0 MHz with a 5.0 V supply and 4.0 MHz with a 1.0 V

supply.

Low Voltage Operation

The MC33501/503 will operate at supply voltages from

0.9 to 7.0 V and ground. When using the MC33501/503 at

supply voltages of less than 1.2 V, input offset v oltage may

increase slightly as the input signal swings within

approximately 5 0 m V o f t he p ositive s upply r ail. This ef fect

occurs only for supply voltages below 1.2 V, due to the input

depletion mode MOSFETs starting to transition between the

saturated to linear region, and should be considered when

designing high side dc sensing applications operating at the

positive supply rail. Since the device is rail−to−rail on both

input and output, high dynamic range single battery cell

applications are now possible.

MC33501, MC33503

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7

20 mV/DIV

0

1000

100

0

t, TIME (1.0 ms/DIV)t, TIME (500 ms/DIV)

TA, AMBIENT TEMPERATURE (°C)

Figure 3. Output Saturation

versus Load Resistance

RL, LOAD RESISTANCE (W)

VCC = 0.5 V

VEE = −0.5 V

ACL = 1.0

CL = 10 pF

RL = 10 k

TA = 25°C

VCC = 2.5 V

VEE = −2.5 V

ACL = 1.0

CL = 10 pF

RL = 600 W

TA = 25°C

VCC

100

200

10

400

1.0

600

0.1

600

0.01

400

0.001

200

01.0 k

25

10 k

50

100 k

75

1.0 M

100

10 M

125

VEE

VCC = 5.0 V

VEE = 0 V

RL to VCC/2

Figure 4. Drive Output Source/Sink Saturation

Voltage versus Load Current

Source

Saturation

TA = −55°C

IO, OUTPUT CURRENT (mA)

VCC

VEE

TA = 25°C

TA = 125°C

Sink

Saturation TA = 125°C

TA = 25°C

TA = −55°C

VCC − VEE = 5.0 V

0

−0.5

−1.0

1.0

0.5

08.00 4.0 12 16 20 24

Figure 5. Input Current versus Temperature Figure 6. Gain and Phase versus Frequency

Figure 7. Transient Response Figure 8. Slew Rate

Vsat, OUTPUT SATURATION VOLTAGE (mV)

Vsat, OUTPUT SATURATION VOLTAGE (V)

AVOL, GAIN (dB)

IIB, INPUT CURRENT (pA)

1.0 V/DIV (mV)

1.0

100

f, FREQUENCY (Hz)

VCC = 2.5 V

VEE = −2.5 V

RL = 10 k

Phase

Gain

Phase Margin = 60°

φm, EXCESS PHASE (DEGREES)

0

80

60

45

40

90

180

135

20

010 100 1.0 k 10 k 100 k 1.0 M 10 M

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8

f, FREQUENCY (Hz)

100

0

1.0

2.0

3.0

8.0

4.0

5.0

1.0 k 10 k 100 k 1.0 M

VCC = 2.5 V

VEE = −2.5 V

AV = 1.0

RL = 600 W

TA = 25°C

10

6.0

7.0

−55 −25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Figure 9. Maximum Power Dissipation

versus Temperature

0

200

400

600

800

1000

1200

1400

1600

DIP Pkg

SO−8 Pkg

Figure 10. Open Loop Voltage Gain

versus Temperature

f, FREQUENCY (Hz)

100 1.0 k 10 k 100 k10

20

60

80

120

40

100

0

0 0.5 1.0 1.5 2.0 2.5

0

20

40

60

80

100

Source

Sink

|VS| − |VO| (V)f, FREQUENCY (Hz)

100 1.0 k 10 k10 100 k

PSR, POWER SUPPLY REJECTION (dB)

1.0 M

VCC = 2.5 V

VEE = −2.5 V

TA = 25°C

CMR, COMMON MODE REJECTION (dB)

−55 −25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

025

120

110

100

90

80

70

60

50

40

30

20

ΔAVOL, OPEN LOOP GAIN (dB)

VCC = 2.5 V

VEE = −2.5 V

RL = 600 W

VCC = 2.5 V

VEE = −2.5 V

TA = 25°C

Figure 11. Output Voltage versus Frequency Figure 12. Common Mode Rejection

versus Frequency

Figure 13. Power Supply Rejection

versus Frequency Figure 14. Output Short Circuit Current

versus Output Voltage

0

40

60

100

20

80

120

140

Either VCC or VEE

TA = 25°C

VCC = 0.5 V

VEE = −0.5 V

VCC = 2.5 V

VEE = −2.5 V

VO, OUTPUT VOLTAGE (Vpp)

IISCI, OUTPUT SHORT CIRCUIT CURRENT (mA)

PDmax, MAXIMUM POWER DISSIPATION (mW)

MC33501, MC33503

http://onsemi.com

9

40

PERCENTAGE OF AMPLIFIERS (%)

INPUT OFFSET VOLTAGE (mV)

0

10

20

30

40

50

−5.0

VCC = 3.0 V

VO = 1.5 V

VEE = 0 V

TA = 25°C

60 Amplifiers Tested

from 2 Wafer Lots

−4.0 −3.0 −2.0 −1.0 0 1.0 2.0 3.0 4.0 5.0

ICC, SUPPLY CURRENT PER AMPLIFIER (mA)

TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C)

0

10

20

30

50

−50

VCC = 3.0 V

VO = 1.5 V

VEE = 0 V

60 Amplifiers Tested

from 2 Wafer Lots

−55 −25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

100

0

Figure 15. Output Short Circuit Current

versus Temperature

20

40

60

80 Sink

Source

VCC = 2.5 V

VEE = −2.5 V

VCC, |VEE|, SUPPLY VOLTAGE (V)

±2.5

0±0.5 ±1.00

0.5

1.0

1.5

Figure 16. Supply Current per Amplifier

versus Supply Voltage with No Load

±1.5 ±2.0

2.0

2.5

TA = 125°C

100 k

f, FREQUENCY (Hz)

0.001

0.01

100 1.0 k 10 k10

10

0.1

1.0

AV = 1000

VCC − VEE = 1.0 V

TA = 25°CTA = −55°C

−40 −30 −20 −10 0 10 20 30 40 50

AV = 100

AV = 10

AV = 1.0

100 k

f, FREQUENCY (Hz)

0.001

0.01

100 1.0 k 10 k10

10

0.1

1.0 AV = 1000

VCC − VEE = 5.0 V

AV = 100

AV = 10

AV = 1.0

Figure 17. Input Offset Voltage

Temperature Coefficient Distribution Figure 18. Input Offset Voltage Distribution

Figure 19. Total Harmonic Distortion

versus Frequency with 1.0 V Supply Figure 20. Total Harmonic Distortion

versus Frequency with 5.0 V Supply

Vout = 0.5 Vpp

RL = 600 W

Vout = 4.0 Vpp

RL = 600 W

IISCI, OUTPUT SHORT CIRCUIT CURRENT (mA)

PERCENTAGE OF AMPLIFIERS (%)

THD, TOTAL HARMONIC DISTORTION (%)

MC33501, MC33503

http://onsemi.com

10

0

1.0

2.0

3.0

4.0

5.0

−25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

−55

0

20

40

60

−20

−40

1.0 M 10 M

f, FREQUENCY (Hz)

10 k 100 k

Figure 21. Slew Rate versus Temperature

−55 −25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

0

1.0

2.0

3.0

4.0

VCC − VEE = 5.0 V

+ Slew Rate

−25 0 25 50 75 100 125−55

0

20

40

0

20

40

60

80

100

60

80

100

VCC − VEE = 5.0 V

RL = 600 W

CL = 100 pF

10 1.0 k 1.0 M100 100 k10 k

0

20

40

60

70

RT, DIFFERENTIAL SOURCE RESISTANCE (W)

Phase Margin

Gain Margin

CL, CAPACITIVE LOAD (pF)

3.0 10 100 1000 300030 300

0

10

20

50

60

30

40

VCC − VEE = 1.0 V

+ Slew Rate

VCC − VEE = 1.0 V

− Slew Rate

VCC − VEE = 5.0 V

− Slew Rate

SR, SLEW RATE (V/ s)μ

VCC − VEE = 5.0 V

f = 100 kHz

GBW, GAIN BANDWIDTH PRODUCT (MHz)

VCC − VEE

= 1.0 V

VCC − VEE = 5.0 V

VCC − VEE

= 5.0 V

VCC − VEE = 1.0 V

RL = 600 W

CL = 0

TA = 25°C

0

20

40

60

70

Phase Margin

Gain Margin

TA, AMBIENT TEMPERATURE (°C)

AV, GAIN MARGIN (dB)

VCC − VEE = 5.0 V

RL = 600 W

CL = 100 pF

TA = 25°C

0

10

20

50

60

30

40

AV, GAIN MARGIN (dB)

Figure 22. Gain Bandwidth Product

versus Temperature

Figure 23. Voltage Gain and Phase

versus Frequency Figure 24. Gain and Phase Margin

versus Temperature

Figure 25. Gain and Phase Margin versus

Differential Source Resistance Figure 26. Feedback Loop Gain and Phase

versus Capacitive Load

VCC − VEE = 5.0 V

RL = 600 W

TA = 25°C

50

30

10

Phase Margin

Gain Margin

10

30

50

AVOL, GAIN (dB)

Fm, PHASE MARGIN (°)

AV GAIN MARGIN (dB)

MC33501, MC33503

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11

Fm, PHASE MARGIN (°)

1234567

VCC − VEE, SUPPLY VOLTAGE (V)

0

20

40

20

40

60

80

100

60

80

100

Phase Margin

Gain Margin

RL = 600 W

CL = 0

TA = 25°C

10 1.0 k100 100 k

10

20

30

40

50

60

70

10 k

f, FREQUENCY (Hz)

VCC − VEE = 5.0 V

TA = 25°C

−55 −25 0 25 50 75 100 125

0

0.4

0.8

1.2

1.6

AVOL ≥ 10 dB

RL = 600 W

VCC − VEE, SUPPLY VOLTAGE (V)

0 1.0 2.0 3.0 4.0

0

20

40

60

120

5.0 6.0

RL = 600 W

TA = 25°C

80

100

VCC, |VEE|, SUPPLY VOLTAGE (V)

0±0.5 ±1.0 ±1.5 ±2.0 ±2.5 ±3.0 ±3.5

0

2.0

4.0

6.0

8.0

RL= 600 W

TA = 25°C

Figure 27. Channel Separation

versus Frequency

30 100 10 k 100 k 300 k300 30 k

AV = 100

0

20

40

100

120

60

80

VCC − VEE = 5.0 V

RL = 600 W

VO = 4.0 Vpp

TA = 25°C

f, FREQUENCY (Hz)

AV = 10

CS, CHANNEL SEPARATION (dB)

0

en, EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)

0

TA, AMBIENT TEMPERATURE (°C)

Figure 28. Output Voltage Swing

versus Supply Voltage

Figure 29. Equivalent Input Noise Voltage

versus Frequency Figure 30. Gain and Phase Margin

versus Supply Voltage

Figure 31. Useable Supply Voltage

versus Temperature Figure 32. Open Loop Gain

versus Supply Voltage

VO, OUTPUT VOLTAGE (Vpp)

VCC−VEE, USEABLE SUPPLY VOLTAGE (V)

AVOL, OPEN LOOP GAIN (dB)

AV, GAIN MARGIN (dB)

MC33501, MC33503

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12

R

T

470 k

R2

470 k

R1b

470 k

R1a

470 k

CT

1.0 nF

1.0 V

fO

1.0 kHz

1.0 Vpp

R1

10 k

Rf

100 k

R2

10 k

Cf

400 pF

0.5 V

−0.5 V

C1

80 nF

VO

Af

fL

Figure 33. 1.0 V Oscillator

Figure 34. 1.0 V Voiceband Filter

fL+1

2pR1C1[200 Hz

fH+1

2pRfCf[4.0 kHz

Af+1)Rf

R2+11

+

−

+

−

fH

fO+1

RTCTInƪ2(R

1a )R1b)

R2ƫ

VCC

MC33501, MC33503

http://onsemi.com

13

15 V

10

79

MC34025

5

15 13

Output A

Output B

22 k

470 pF

100 k

1.0 k

From

Current Sense

3320

1.0 k

MC33502

Provides current sense

amplification and eliminates

leading edge spike.

FB 4.7

4.7

0.1

Figure 35. Power Supply Application

IODIO/DIL

Figure 36. 1.0 V Current Pump

+

−

12

8

14

11

4

16

6

1

3

2

IL

435 mA 463 mA

212 mA 492 mA−120 x 10−6

5.0 V

Vref

R2

3.3 k

R3

1.0 k

R1

1.0 k

IO1.0 V

R4

2.4 k VL

VO

For best performance, use low tolerance resistors.

IL

+

−

Rsense

R5

1.0 k

RL

75

MC33501, MC33503

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14

PACKAGE DIMENSIONS

SOT23−5

(TSOP−5, SC59−5)

SN SUFFIX

CASE 483−02

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

4. A AND B DIMENSIONS DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.1142 0.1220

B1.30 1.70 0.0512 0.0669

C0.90 1.10 0.0354 0.0433

D0.25 0.50 0.0098 0.0197

G0.85 1.05 0.0335 0.0413

H0.013 0.100 0.0005 0.0040

J0.10 0.26 0.0040 0.0102

K0.20 0.60 0.0079 0.0236

L1.25 1.55 0.0493 0.0610

M0 10 0 10

S2.50 3.00 0.0985 0.1181

0.05 (0.002)

123

54

S

AG

L

B

D

H

C

KM

J

__ _ _

0.7

0.028

1.0

0.039

ǒmm

inchesǓ

SCALE 10:1

0.95

0.037

2.4

0.094

1.9

0.074

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC33501/D

SMARTMOS is a trademark of Motorola, Inc.

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