Enpirion(R) Power Datasheet EN6310QA 1A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor Description Features The EN6310QA is a member of Altera Enpirion's high efficiency EN6300 family of PowerSoCs. The EN6310QA is a 1A PowerSoC that is AEC-Q100 qualified for automotive applications. The EN6310QA employs Altera Enpirion's EDMOS MOSFET technology for monolithic integration and very low switching loss. The device switches at 2.2MHz in fixed PWM operation to eliminate the low frequency noise that is created by pulse frequency modulation operating modes. The MOSFET ratios are optimized to offer high conversion efficiency for lower VOUT settings. Output voltage settings are programmable via a simple resistor divider circuit. Output voltage can be programmed from as low as 0.6V to 3.3V. The device has a programmable soft-start ramp rate to accommodate sequencing and to prevent un-wanted current inrush at start up. A Power OK (POK) flag is provided to indicate a fault condition. The Altera Enpirion power solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. Integrated inductor, MOSFET and Controller All Altera Enpirion products are RoHS compliant and lead-free manufacturing environment compatible. Low Power FPGA Applications -40C to 105C Ambient Temperature Range AEC-Q100 Qualified for Automotive Applications Small 4mm x 5mm x 1.85mm QFN High Efficiency up to 96% Solution Footprint Less than 65mm2 1A Continuous Output Current VIN Range of 2.7V to 5.5V VOUT Range from 0.6V to 3.3V Programmable Soft Start and Power OK Flag Fast Transient Response and Recovery Time Low Noise and Low Output Ripple; 4mV Typical 2.2MHz Switching Frequency Under Voltage Lock-out (UVLO), Short Circuit, Over Current and Thermal Protection Applications Automotive Applications Altera FPGAs (MAX, ARRIA, CYCLONE, STRATIX) Noise Sensitive Wireless and RF Applications Efficiency vs. Output Current 100 VOUT VIN EN6310QA RAVIN CIN1 20 100pF ON OFF ENABLE AVIN COUT 2x22F 1206 X7R 90 RA CA CAVIN 0.47F RCA VFB SS PGND PGND CSS 10nF AGND RB EFFICIENCY (%) CIN2 4.7F 0603 X7R 95 VOUT PVIN 85 80 75 70 VOUT = 2.5V 65 VOUT = 1.0V CONDITIONS VIN = 3.3V 60 0 Figure 1. Simplified Applications Circuit 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Figure 2. Highest Efficiency in Smallest Solution Size www.altera.com/enpirion 10406 March 4, 2016 Rev D EN6310QA Ordering Information Part Number EN6310QA EVB-EN6310QA Package Markings 6310A 6310A TA (C) -40 to +105 Package Description 30-pin (4mm x 5mm x 1.85mm) QFN T&R QFN Evaluation Board Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html NC(SW) NC(SW) NC(SW) NC(SW) NC(SW) NC(SW) NC(SW) PVIN PVIN Pin Assignments (Top View) 30 29 28 27 26 25 24 23 22 NC(SW) 1 21 PGND NC(SW) 2 20 PGND PGND 3 19 AVIN PGND 4 18 ENABLE VOUT 5 17 POK VOUT 6 16 CSS 31 PGND Bottom Pad 7 8 9 10 11 12 13 14 15 VOUT VOUT VOUT VOUT VOUT NC VFB AGND NC Figure 3: Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: White `dot' on top left is pin 1 indicator on top of the device package. www.altera.com/enpirion, Page 2 10406 March 4, 2016 Rev D EN6310QA Pin Description PIN NAME 1, 2, 2430 NC(SW) 3, 4 PGND 5-11 VOUT 12, 15 NC 13 14 16 VFB AGND CSS 17 POK 18 ENABLE 19 AVIN 20, 21 PGND 22, 23 PVIN 31 PGND Bottom Pad FUNCTION NO CONNECT. Do not connect to any signal, voltage, or ground. These pins are connected internally to the MOSFET common switch node. Power ground. The output filter capacitor ground terminal should be connected to these pins. Refer to application details for proper layout and ground routing. Regulated output. Connect output capacitors from these pins to PGND (pins 3, 4). NO CONNECT. Do not connect to any signal, voltage, or ground. These pins may be connected internally. Output feed-back node. Connect to center of VOUT resistor divider. Quiet analog ground for control circuits. Connect to system ground plane. Soft Start startup time programming pin. Connect CSS capacitor from this pin to AGND. Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power system state indication. POK is logic high when VOUT is above 90% of VOUT nominal. Leave this pin floating if not used. Output enable; Enable = logic high, Disable = logic low. Quiet input supply for circuitry. Power ground. The input filter capacitor ground terminal should be connected to these pins. Refer to application details for proper layout and ground routing. Input supply voltage for high side MOSFET Switch. Connect input filter capacitor from this pin to PGND. Device thermal pad to be connected to the system GND plane. See Layout Recommendations section. www.altera.com/enpirion, Page 3 10406 March 4, 2016 Rev D EN6310QA Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. MIN MAX UNITS Voltages on : PVIN, AVIN, VOUT PARAMETER SYMBOL -0.3 6.6 V Voltages on: ENABLE, POK -0.3 VIN+0.3 V Voltages on: VFB, SS -0.3 2.7 V -65 150 C 150 C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 C ESD Rating (based on Human Body Model) 2000 V ESD Rating (based on CDM) 500 V Storage Temperature Range TSTG Maximum Operating Junction Temperature TJ-ABS Max Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS VIN 2.7 5.5 V Output Voltage Range VOUT 0.60 3.3 V Output Current IOUT 1 A Input Voltage Range Operating Ambient Temperature TA -40 +105 C Operating Junction Temperature TJ -40 +125 C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Shutdown TSD 140 C Thermal Shutdown Hysteresis TSDH 20 C JA 60 C/W Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) Thermal Resistance: Junction to Case (0 LFM) 3 C/W JC Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. www.altera.com/enpirion, Page 4 10406 March 4, 2016 Rev D EN6310QA Electrical Characteristics NOTE: VIN (PVIN and AVIN) = 5.0V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER Input Voltage Range Under Voltage Lockout VIN Rising Under Voltage Lockout VIN Falling Output Voltage Range Maximum Duty Cycle Feedback Pin Voltage Initial Accuracy SYMBOL VIN MAX 5.5 UNITS V V UVLO_F 1.9 V VOUT DMAX VFB 0.6 TA = 25C, VIN = 5.0V, ILOAD = 100mA VIN = 3.3V; 0A IOUT 1.0A; -40C TA +105C VIN = 5.0V; 0A IOUT 1.0A; -20C TA +105C VIN = 5.0V; 0A IOUT 1.0A; -40C TA +105C ENABLE Lock-out ENLO 3.3 V % 0.60 V +2.25 % -2.0 +2.0 % -3.0 +2.0 % 100 nA 1 1.2 ENABLE = Low ENABLE = Low 2.7 VIN 5.5V Pin = Low Pin = High ENABLE = High Time before enable will re-assert internally after being pulled low CSS = 10nF CSS 5 A A A A A V V A 12.5 ms 2.2 MHz 1.8 175 2.2 1.2 0.0 1.8 fSW TSS 85 -2.0 IVFB ENABLE Pin Input Current Switching Frequency Soft Start Time (Note 2) (Note 3) Allowable Soft Start Capacitor Range (Note 3) TYP 2.3 IOUT IOCP ISD ISD IOCP ENLOW ENHIGH IENABLE ENABLE Pin Logic Threshold MIN 2.7 UVLO_R Output Voltage DC Accuracy Feedback Pin Input Current (Note 3) Continuous Output Current Over Current Trip Point AVIN Shut-Down Current PVIN Shut-Down Current OCP Threshold TEST CONDITIONS VIN = AVIN = PVIN 5.2 0.47 0.4 VIN 6.5 7.8 ms 10 nF Note 2: Soft Start Time range does not include capacitor tolerances. Note 3: Parameter not production tested but is guaranteed by design. www.altera.com/enpirion, Page 5 10406 March 4, 2016 Rev D EN6310QA Typical Performance Curves Efficiency vs. Output Current 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs. Output Current 100 80 75 VOUT = 2.5V 70 VOUT = 1.8V 65 VOUT = 1.5V 60 VOUT = 1.2V 55 VOUT = 1.0V 80 75 VOUT = 3.3V 70 VOUT = 2.5V VOUT = 1.8V 65 VOUT = 1.5V 60 CONDITIONS VIN = 3.3V VOUT = 1.2V 55 50 VOUT = 1.0V CONDITIONS VIN = 5.0V 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Output Voltage vs. Output Current Output Voltage vs. Output Current 1.220 1.030 VIN = 5V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VIN = 3.3V 1.020 1.010 1.000 0.990 CONDITIONS VOUT = 1.0V 0.980 VIN = 3.3V 1.210 VIN = 5.0V 1.200 1.190 1.180 CONDITIONS VOUT = 1.2V 1.170 0.970 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 0 1 1 Output Voltage vs. Output Current Output Voltage vs. Output Current 1.820 1.520 1.510 OUTPUT VOLTAGE (V) VIN = 3.3V OUTPUT VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) VIN = 5.0V 1.500 1.490 1.480 CONDITIONS VOUT = 1.5V VIN = 3.3V 1.810 VIN = 5.0V 1.800 1.790 1.780 1.770 CONDITIONS VOUT = 1.8V 1.760 1.750 1.470 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 www.altera.com/enpirion, Page 6 10406 March 4, 2016 Rev D EN6310QA Typical Performance Curves (Continued) Output Voltage vs. Output Current Output Voltage vs. Output Current 3.320 2.540 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VIN = 5.0V VIN = 3.3V 2.530 VIN = 5.0V 2.520 2.510 2.500 2.490 CONDITIONS VOUT = 2.5V 2.480 3.310 3.300 3.290 3.280 CONDITIONS VOUT = 3.3V 3.270 2.470 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 0 1 1.020 CONDITIONS VIN = 3.3V VOUT_NOM = 1.0V 1.015 1.010 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1 Output Voltage vs. Temperature Output Voltage vs. Temperature 1.020 1.005 1.000 LOAD = 0A 0.995 LOAD = 0.2A 0.990 LOAD = 0.4A LOAD = 0.8A 0.985 CONDITIONS VIN = 5.0V VOUT_NOM = 1.0V 1.015 1.010 1.005 1.000 LOAD = 0A 0.995 LOAD = 0.2A 0.990 LOAD = 0.4A LOAD = 0.8A 0.985 LOAD = 1A LOAD = 1A 0.980 0.980 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ( C) 110 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ( C) 110 Output Voltage vs. Temperature Output Voltage vs. Temperature 3.380 2.580 CONDITIONS VIN = 3.3V VOUT_NOM = 2.5V 2.530 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 2.480 LOAD = 0A LOAD = 0.2A LOAD = 0.4A 2.430 LOAD = 0.8A CONDITIONS VIN = 5.0V VOUT_NOM = 3.3V 3.360 3.340 3.320 3.300 LOAD = 0A 3.280 LOAD = 0.2A 3.260 LOAD = 0.4A LOAD = 0.6A 3.240 LOAD = 1A LOAD = 1A 3.220 2.380 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ( C) 110 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ( C) 110 www.altera.com/enpirion, Page 7 10406 March 4, 2016 Rev D EN6310QA Typical Performance Curves (Continued) Output Voltage vs. Input Voltage OUTPUT VOLTAGE (V) 1.815 1.810 1.805 1.800 1.795 1.790 LOAD = 0A LOAD = 0.05A LOAD = 0.25A LOAD = 0.5A LOAD = 1A 1.785 1.780 1.775 CONDITIONS VOUT_NOM = 1.8V TA = 25 C 1.770 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 5.5 GUARANTEED OUTPUT CURRENT (A) No Thermal Derating 1.820 1.2 1 0.8 0.6 0.4 CONDITIONS VIN = 5.0V VOUT = 1.0V 0.2 0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE( C) 110 GUARANTEED OUTPUT CURRENT (A) No Thermal Derating 1.2 1 0.8 0.6 0.4 CONDITIONS Conditions VINVIN = 5.0V = 5.0V VOUT VOUT = 3.3V = 3.3V 0.2 0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE( C) 110 www.altera.com/enpirion, Page 8 10406 March 4, 2016 Rev D EN6310QA Typical Performance Characteristics Output Ripple at 20MHz Bandwidth Output Ripple at 20MHz Bandwidth VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 2x22F (106) Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 5V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) www.altera.com/enpirion, Page 9 10406 March 4, 2016 Rev D EN6310QA Typical Performance Characteristics (Continued) Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 5V VOUT = 3.3V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.8V (AC Coupled) 50mV / DIV VOUT = 1V (AC Coupled) 50mV / DIV CONDITIONS VIN = 3.3V, VOUT = 1V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 3.3V, VOUT = 1.8V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components LOAD Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.0V (AC Coupled) 50mV / DIV VOUT = 2.5V (AC Coupled) 50mV / DIV LOAD VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 3.3V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) CONDITIONS VIN = 3.3V, VOUT = 2.5V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 5.0V, VOUT = 1.0V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components www.altera.com/enpirion, Page 10 10406 March 4, 2016 Rev D EN6310QA Typical Performance Characteristics (Continued) Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.8V (AC Coupled) 50mV / DIV VOUT = 1.8V (AC Coupled) 50mV / DIV LOAD CONDITIONS VIN = 5.0V, VOUT = 1.8V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 5.0V, VOUT = 3.3V CIN = 4.7F (0603) + 100pF COUT = 2x22F (1206) Using Datasheet Recommended Components Enable Startup/Shutdown Waveform (0A) Enable Startup/Shutdown Waveform (1A) ENABLE ENABLE VOUT VOUT POK POK CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 2x22F (1206) LOAD LOAD Enable Startup Waveform (0A) CONDITIONS VIN = 5V, VOUT = 1.8V, 1A Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 2x22F (1206) Enable Shutdown Waveform (0A) ENABLE ENABLE VOUT VOUT POK POK CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 2x22F (1206) CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 2x22F (1206) LOAD LOAD www.altera.com/enpirion, Page 11 10406 March 4, 2016 Rev D EN6310QA Functional Block Diagram PVIN UVLO Thermal Limit Current Limit NC(SW) P-Drive (-) PWM Comp (+) Logic VOUT N-Drive PGND PLL/Sawtooth Generator Compensation Network (-) Error Amp (+) VFB Power OK POK ENABLE Soft Start Internal Reference CSS Internal Regulator AGND AVIN Figure 4: Functional Block Diagram www.altera.com/enpirion, Page 12 10406 March 4, 2016 Rev D EN6310QA Functional Description Functional Overview Integration for Low-Noise Low-EMI The EN6310QA is a synchronous buck converter with integrated MOSFET switches and Inductor. The device can deliver up to 1A of continuous load current. The EN6310QA has a programmable soft start rise time and a power OK (POK) signal. The device operates in a fixed 2.2MHz PWM mode to eliminate noise associated with pulse frequency modulation schemes. The control topology is a low complexity type IV voltage mode providing high noise immunity and stability over the entire operating range. Output voltage is set with a simple resistor divider. The high switching frequency enables the use of small MLCC input and output filter capacitors. Figure 4 shows the EN6310QA block diagram. The EN6310QA utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Furthermore, the package layout is optimized to reduce the electrical path length for the high di/dt input AC ripple currents that are a major source of radiated emissions from DCDC converters. Careful package and IC design minimize common mode noise that can be difficult to mitigate otherwise. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC converter design. Protection Features: The EN6310QA has the following protection features. Over-current protection (to protect the IC from excessive load current) Short-Circuit protection Thermal shutdown with hysteresis Under-voltage lockout circuit to disable the converter output when the input voltage is below a pre-defined level Additional Features: Soft-start circuit, limiting the in-rush current when the converter is initially powered up. The soft start time is programmable with appropriate choice of soft start capacitor value High Efficiency Technology The key enabler of this revolutionary integration is Altera Enpirion's proprietary power MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry. The proprietary magnetics design provides highdensity/high-value magnetics in a very small footprint. Altera Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. Control Topology The EN6310QA utilizes an internal type IV voltage mode compensation scheme. Voltage mode control provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. The EN6310QA is optimized for fast transient recovery for applications with demanding transient performance. Voltage mode control enables a high degree of stability over the entire operating range. Enable The EN6310QA ENABLE pin enables and disables operation of the device. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter and initiate a normal soft start operation. When ENABLE is pulled low, the Power MOSFETs stop switching and the output is discharged in a controlled manner with a soft pull down MOSFET. Once the enable pin is pulled low, there is a lockout period before the device can be re-enabled. The lock out period can be found in the Electrical Characteristics Table. Do not leave ENABLE pin floating or it will be in an unknown random state. The EN6310QA supports startup into a pre-biased output of up to 1.5V. The output of the EN6310QA can be pre-biased with a voltage up to 1.5V when it is first enabled. www.altera.com/enpirion, Page 13 10406 March 4, 2016 Rev D EN6310QA POK Operation The POK signal is an open drain signal (requires a pull up resistor to AVIN or similar voltage) from the converter indicating the output voltage is within the specified range. Typically, a 100k or lower resistance is used as the pull-up resistor. The POK signal will be logic high (AVIN) when the output voltage is above 90% of the programmed voltage level. If the output voltage is below this point, the POK signal will be a logic low. If the input voltage is in UVLO or if the ENABLE is pulled low, the POK will also be a logic low. The POK signal can be used to sequence down-stream converters by tying to their enable pins. Programmable Soft Start Operation Soft start is externally programmable by adjusting the value of the CSS capacitor, which is placed between the respective CSS pin and AGND pin. When the enable pin is pulled high, the output will ramp up monotonically at a rate determined by the CSS capacitor. Soft start ramp time is programmable over a range of 0.5ms to 10ms. The longer ramp times allow startup into very large bulk capacitors that may be present in applications such as wireless broadband or solid state storage, without triggering an Over Current condition. The rise time is given as: TRISE [ms] = CSS [nF] 0.65 25% NOTE: Rise time does not include capacitor tolerances. If a 10nF soft-start capacitor is used, then the output voltage rise time will be around 6.5ms. The rise time is measured from when VIN VUVLOR and ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its programmed value. Over Current/Short Circuit Protection The current limit and short-circuit protection is achieved by sensing the current flowing through a sense PFET. When the sensed current exceeds the current limit, both NFET and PFET switches are turned off and the output is discharged. After 1.6ms the device will be re-enabled and will then go through a normal soft-start cycle. If the over current condition persists, the device will enter a hiccup mode. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold, the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Thermal Shutdown When excess power is dissipated in the EN6310QA the junction temperature will rise. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases to a safe operating level, the part will go through the normal startup process. The thermal shutdown temperature and hysteresis values can be found in the thermal characteristics table. www.altera.com/enpirion, Page 14 10406 March 4, 2016 Rev D EN6310QA Application Information VOUT Output Voltage Programming VOUT The EN6310QA output voltage is programmed using a simple resistor divider network (RA and RB). The feedback voltage at VFB is nominally 0.6V. RA is fixed at 200k and RB can be calculated based on Figure 5. The values recommended for COUT, CA, and RCA make up the external compensation of the EN6310QA. It will vary with each VIN and VOUT combination to optimize on performance. Please see Table 1 for a list of recommended RA, CA, RCA, and COUT values for each solution. Since VFB is a sensitive node, do not touch the VFB node while the device is in operation as doing so may introduce parasitic capacitance into the control loop that causes the device to behave abnormally and damage may occur. The output voltage is set by the following formula: = (1 + ) Rearranging to solve for RB: = - Where: RA = 200k VREF = 0.60V COUT RCA VFB = 0.6V PGND RB = EN6310QA 120 - 0.6 VOUT - VFB CIN = 4.7F/0603 + 100pF CAVIN = 20 + 0.47F COUT = 2x22F/1206 RA = 200k, RCA = 1k, RB = 0.6RA/(VOUT - 0.6) VIN (V) 5.5 VOUT (V) Ca (pF) 15 VIN (V) 5.5 5 3.3 15 5 4.5 15 4.5 5.5 15 3.3 33 15 2.7 39 15 5.5 39 3.3 15 5 39 5.5 15 4.5 5 15 3.3 47 15 2.7 47 3.3 22 5.5 39 2.7 22 5 39 5.5 22 4.5 5 22 3.3 56 22 2.7 56 4.5 RA is chosen as 200k to provide constant loop gain. The output voltage can be programmed over the range of 0.6V to 3.3V. VFB x RA Figure 5. External Compensation 4.5 = CA VFB 5 Then RB is given as: RA 4.5 2.5 1.8 1.5 3.3 27 2.7 33 VOUT (V) Ca (pF) 27 27 1.2 1 0.6 33 39 47 Table 1. Compensation values. For output voltages in between, use the values from the higher output voltage. www.altera.com/enpirion, Page 15 10406 March 4, 2016 Rev D EN6310QA Input Filter Capacitor Output Filter Capacitor The EN6310QA requires at least a 4.7F/0603 and a 100pF input capacitor near the PVIN pins. Lowcost, low-ESR ceramic capacitors should be used as input capacitors for this converter. The dielectric must be X7R rated. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. Table 2 contains a list of recommended input capacitors. The EN6310QA requires at least two 22F/1206 output filter capacitors. Low ESR ceramic capacitors are required with X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. Table 3 contains a list of recommended output capacitors. Description MFG 4.7F, 6.3V, X7R, 0603 Taiyo Yuden P/N Description 22F, 10V, X7R, 1206 MFG Murata Taiyo Yuden AVX P/N GRM31CR71A226ME15 LMK316AB7226KL-TR 1206ZC226KAT2A Table 3. Recommended Output Capacitors JMK107BB7475KA-T Table 2. Recommended Input Capacitors www.altera.com/enpirion, Page 16 10406 March 4, 2016 Rev D EN6310QA Thermal Considerations Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Altera Enpirion PowerSoC helps alleviate some of those concerns. The Altera Enpirion EN6310QA DC-DC converter is packaged in a 4x5x1.85mm 30-pin QFN package. The QFN package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 140C. The following example and calculations illustrate the thermal performance of the EN6310QA. Example: VIN = 5V VOUT = 3.3V = POUT / PIN = 91% = 0.91 PIN = POUT / PIN 3.3W / 0.91 3.63W The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN - POUT 3.63W - 3.3W 0.33W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (JA). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN6310QA has a JA value of 60 C/W without airflow. Determine the change in temperature (T) based on PD and JA. T = PD x JA T 0.33W x 60C/W 19.8 C 20C The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in temperature. We assume the initial ambient temperature to be 25C. TJ = TA + T IOUT = 1A TJ 25 C + 20 C 45C First calculate the output power. POUT = 3.3V x 1A = 3.3W Next, determine the input power based on the efficiency () shown in Figure 6. Efficiency vs. Output Current The maximum operating junction temperature (TJMAX) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated. TAMAX = TJMAX - PD x JA 100 125 C - 20 C 105C 95 The maximum ambient temperature the device can reach is 105C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. 90 EFFICIENCY (%) For VIN = 5V, VOUT = 3.3V at 1A, 91% 85 80 75 70 65 60 VOUT = 3.3V 55 CONDITIONS VIN = 5.0V 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Figure 6. Efficiency vs. Output Current www.altera.com/enpirion, Page 17 10406 March 4, 2016 Rev D EN6310QA Engineering Schematic VOUT VIN VOUT PVIN CIN2 4.7F 0603 X7R CIN1 100pF EN6310QA RAVIN 20 ON OFF ENABLE AVIN COUT 2x22F 1206 X7R RA CAVIN 0.47F CA RCA VFB SS PGND PGND CSS 10nF AGND RB Figure 7. Typical Engineering Schematic www.altera.com/enpirion, Page 18 10406 March 4, 2016 Rev D EN6310QA Layout Recommendation Figure 8. Evaluation Board Layout Recommendations Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN6310QA package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN6310QA should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the www.altera.com/enpirion, Page 19 10406 March 4, 2016 Rev D EN6310QA Gerber files on the www.altera.com/enpirion. Altera website reliefs or spokes to connect these vias to the ground plane. Recommendation 3: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be connected to the input voltage at a quiet point. A good location is to place the AVIN connection on the source side of the input capacitor, away from the PVIN pins. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. See Figure 8. Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see Figure 8. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not use thermal Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 8. See the section regarding exposed metal on bottom of package. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace as short as possible in order to avoid noise coupling into the control loop. Recommendation 8: Keep RA, CA, and RB close to the VFB pin (see Figures 7 and 8). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. www.altera.com/enpirion, Page 20 10406 March 4, 2016 Rev D EN6310QA Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom of Package Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package, as shown in Figure 9. Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN6310QA should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. The "shaded-out" area in Figure 9 represents the area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Figure 9. Lead-Frame exposed metal (Bottom View) Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. www.altera.com/enpirion, Page 21 10406 March 4, 2016 Rev D EN6310QA Recommended PCB Footprint Figure 10. EN6310QA PCB Footprint (Top View) www.altera.com/enpirion, Page 22 10406 March 4, 2016 Rev D EN6310QA Package and Mechanical Figure 11. EN6310QA Package Dimensions (Bottom View) Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html Contact Information Altera Corporation 101 Innovation Drive San Jose, CA 95134 Phone: 408-544-7000 www.altera.com (c) 2014 Altera Corporation--Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion, Page 23 10406 March 4, 2016 Rev D