24LCS22A-I/SNG - Microchip Technology

24LCS22A

Features:

• Single supply with operation down to 2.5V

• Supports Enhanced EDID™ (E-EDID™) 1.3

• Completely implements DDC1™/DDC2™ interface

for monitor identification, including recovery to

DDC1

• 2 Kbit Serial EEPROM Low-power CMOS

technology:

- 1 mA active current, typical

-10μA standby current, typical at 5.5V

• 2-wire serial interface bus, I2C™ compatible

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self timed write cycle (including auto-erase)

• Hardware write-protect pin

• Page write buffer for up to eight bytes

• 1,000,000 erase write cycles

• Data retention > 200 years

• ESD protection > 4000V

• 8-pin DIP and SOIC packages

• Available temperature ranges:

Description:

The Microchip Technology Inc. 24LCS22A is a 256 x 8-bit

dual-mode Electrically Erasable PROM (EEPROM). This

device is designed for use in applications requiring

storage and serial transmission of configuration and

control information. Two modes of operation have been

implemented: Transmit-Only mode (1 Kbit) and

Bidirectional mode (2 Kbit). Upon power-up, the device

will be in the Transmit-Only mode, sending a serial bit

stream of the memory array from 00h to 7Fh, clocked by

the VCLK pin. A valid high-to-low transition on the SCL pin

will cause the device to enter the Transition mode, and

look for a valid contr ol byt e on the I2C bus. If it detects a

valid control byte from the master, it will switch into

Bidirectional mode, with byte selectable read/write

capability of the entire 2K memory array using SCL. If no

control byte is received, the device will revert to the Trans-

mit-Only mode after it receives 128 consecutive VCLK

pulses while the SCL pin is idle. Th e 24LCS22A is avail-

able in standard 8-pin PDIP and SOIC packages. The

24LCS22A features a flexible Write-Protect pin which is

enabled by writing to address 7Fh (usually the checksum

in VE SA® applications.

Package Types

Block Diagram

- Industrial (I) -40°C to +85°C

PDIP/SOIC

24LCS22A

*NC

VSS

VCC

VCLK

SCL

SDA

* Pins labeled ‘NC’ have no internal connection

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

Memory

Control

Logic

I/O

Control

Logic

SDA SCL

Vcc

Vss

VCLK

2K VESA® E-EDID™ Serial EEPROM

24LCS22A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† Not ice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a st ress rating only and fun ctional op eration of the device at th ose or any ot her conditi ons above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DC CHARACTERISTICS Vcc = +2.5V to 5.5V

Industrial (I): TA = -40°C to +85°C

Param.

No. Sym Characteristic Min. Max. Units Test Conditions

SCL and SDA pins:

D1 VIH High-level input voltage 0.7 VCC —V

D2 VIL Low-level input voltage — 0.3 VCC V

Input levels on VCLK pin:

D3 VIH High-level input voltage 2.0 — V VCC ≥ 2.7V (Note)

D4 VIL Low-level input voltage — 0.2 VCC VVCC ≤ 2.7V (Note)

D5 VHYS Hysteresis of Schmit t Trigger

Inputs .05 VCC —V(Note)

D6 VOL1 Low-lev el outp ut vol t ag e — 0. 4 V IOL = 3 mA, VCC = 2.5V (Note)

D7 VOL2 Low-lev el outp ut vol t ag e — 0. 6 V IOL = 6 mA, VCC = 2.5V

D8 ILI Input leakage current — ±1 μAVIN = 0.1V to VCC

D9 ILO Output leakage current — ±1 μAVOUT = 0.1V to VCC

D10 CIN, COUT Pin capacitance

(all inputs/outputs) —10pFVCC = 5.0V (Note)

TA = 25°C, FCLK = 1 MHz

Operating current:

D10 ICC WRITE Operatin g current — 3 mA VCC = 5.5V,

D11 ICC READ Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz

D12 ICCS Standby current —

—30

100 μA

μAVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC

VCLK = VSS

Note: This parameter is periodically sampled and not 100% tested.

© 2005 Microchip Technology Inc. DS21682C-page 3
24LCS22A
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Vcc = +2.5V to 5.5V
Industrial (I): TA = -40°C  to +85°C
Param. 
No. Sym Parameter Min Max Units Conditions
1F
CLK Clock frequency —
—100
400 kHz 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2T
HIGH Clock high time 4000
600 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
3T
LOW Clock low time 4700
1300 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
4T
RSDA and SCL rise time —
—1000
300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
4.5V ≤ VCC ≤ 5.5V (Note 1)
5T
FSDA and SCL fall time —
—300
300 ns (Note 1)
6T
HD:STA Start condition hold time 4000
600 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
7T
SU:STA Start conditio n setup time 4700
600 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
8T
HD:DAT Data in p u t  ho ld t ime 0
0—
—ns (Note 2)
9T
SU:DAT Data input setup time 250
100 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
10 TSU:STO Stop condition setup time 4000
600 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
11 TAA Output valid from clock
(Note 2)—
—3500
900 ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
12 TBUF Bus free time: Time the bus must be 
free before a new transmission can 
start
4700
1300 —
—ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
13 TOF Output fall time from VIH
minimum to VIL maximum —
20+0.1CB250
250 ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
4.5V ≤ VCC ≤ 5.5V (Note 1)
14 TSP In put filter spike suppression
(SDA and SCL pins) —
—50
50 ns (Notes 1 and 3)
15 TWR Write cycle time (byte or page) —
—10
10 ms
16 TVAA Output valid from VCLK —
—2000
1000 ns
17 TVHIGH VCLK high time 4000
600 —
—ns
18 TVLOW VCLK low time 4700
1300 —
—ns
19 TVHST VCLK setup time 0
0—
—ns
20 TSPVL VCLK hold time 4000
600 —
—ns
21 TVHZ Mode transition time —
—1000
500 ns
22 TVPU Transmit-only power-up time 0
0—
—ns
23 TSPV Input filter spike suppression (VCLK 
pin) —
—100
100 ns
24 — Enduranc e 1M — cycles 25°C, VCC = 5.0V, Block mode 
(Note 4)
Note 1: Not 100% tested. CB = t otal capacitance of one bus line in pF.
2: As a transmitter , the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge  of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications  are due to Schmitt Trigger inputs which prov ide improved noi se spike suppres sion.
This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult
the Total Endur ance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

24LCS22A

2.0 FUNCTIONAL DESCRIPTION

The 24LCS22A is designed to comply to the DDC

Standard proposed by VESA (Figure 3-3) with the

exception that it is not Access.bus™ capable. It oper-

ates in two modes, the Transmit-Only mode (1 Kbit)

and the Bi directional m ode (2 Kbit). The re is a sep arate

2-wire protocol to support each mode, each having a

separate clock input but sharing a common data line

(SDA). The device enters the Transmit-Only mode

upon pow er-up. In thi s mode, the device transm its da ta

bits on the SDA pin in response to a cl ock signa l on the

VCLK pin. The device will remain in this mode until a

valid high-to-low transition is placed on the SCL input.

When a valid transition on SCL is recognized, the

device will switch into the Bidirectional mode and look

for its control byte to be sent by the master. If it detects

its control byte, it will stay in the Bidirectional mode.

Otherwis e, it will revert to the T ransmi t-Only mode af ter

it sees 128 VCLK pulses.

2.1 Transmit-Only Mode

The devic e wil l pow e r up in the Transmit-O nly mod e at

address 00H. This mode supports a unidirectional

2-wire protocol for continuous transmission of the first

1 Kbit of the memory array. This device requires that it

be initialized prio r to va lid data being se nt i n t he Trans-

mit-Only mode (Section 2.2 “Initialization Proce-

dure”). In this mode, data is transmitted on the SDA

pin in 8-bit bytes, with each byte followed by a ninth,

Null bit (Figure 2-1). The clock source for the Transmit-

Only mode is provided on the VCLK pin, and a data bit

is output on the rising e dge on this pi n. The eight bi ts in

each byte are transmitted Most Significant bit first.

Each byte within the memory array will be output in

sequence. After address 7Fh in the memory array is

transmitted, the internal Address Pointers will wrap

aroun d to the first memory location (00h) and c ontinue.

The Bidirectional mode clock (SCL) pin must be held

high for the device to remain in the Transmit-Only

mode.

2.2 Initialization Procedure

After VCC has st abilized, th e device w ill be in the Tr ans-

mit-Only mode. Nine clock cycles on the VCLK pin

must be given to the device for it to perform internal

sychronization. During this period, the SDA pin will be

in a high-impedance state. On the rising edge of the

tenth clock cycle, the device will output the first valid

data bit which will be the Most Significant bit in address

00h. (Figure 2-2).

FIGURE 2-1: TRANSMIT-ONLY MODE

FIGURE 2-2: DEVICE INITIALIZATION

SCL

SDA

VCLK

TVAA TVAA

Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7

TVLOWTVHIGH

TVAA TVAA

Bit 8 Bit 7High-impedance for 9 clock cycles

TVPU

12 891011

SCL

SDA

VCLK

VCC

24LCS22A

3.0 BIDIRECTIONAL MODE

Before the 24LCS22A can be switched into the

Bidirectional mode (Figure 3-1), it must enter the

Transition mode, which is done by applying a valid

high-to-low transition on the Bidirectional mode clock

(SCL). As soon as it enters the Transition mode, it looks

for a c ontr ol byte ‘1010 000X’ on the I2C™ bus, and

starts to count pulses on VCLK. Any high-to-low

transition on the SCL line will reset the count. If it sees

a pulse count of 128 on VCLK whil e the SCL line i s idle,

it will revert back to the Transmit-Only mode, and

transmit its contents starting with the Most Significant

bit in address 00h. However, if it detects the control

byte on the I2C bus (Figure 3-2), it will switch to the

Bidirectional mode. Once the device has made the

transition to the Bidirectional mode, the only way to

switc h the devi ce back to the T r ansm it-Only m ode is to

remove power from the device. The mode transition

process is shown in detail in Figure 3-3.

Once the device has switched into the Bidirectional

mode, the VCLK input is disregarded, with the

exception that a logic high level is required to enable

write capability. In Bidirectional mode the user has

acces s t o th e enti re 2K array, whereas i n th e Transmit-

Only mode, the user can only access the first 1K. This

mode supports a two-wire Bidirectional data

transmission protocol (I2C). In this protocol, a device

that sends data on the bus is defined to be the

transmitter, and a device that receives data from the

bus is defined to be the receiver. The bus must be

controlled by a master device that generates the

Bidi rec t iona l mo d e cl oc k (SC L) , con t rol s ac ce ss to t he

bus and generates the Start and Stop conditio ns, while

the 24LCS22A acts as the slave. Both master and

slave can operate as transmitter or receiver, but the

master device determines which mode is activated. In

the Bidirectional mode, the 24LCS22A only responds

to commands for device ‘1010 000X’.

FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

FIGURE 3-2: SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

TVHZ

SCL

SDA

VCLK

Transmit-

Only

MODE Bidirectional Recovery to Transmit-Only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

Transition mode with possibility to return to Transmit-Only mode Bidirectional

permanently

SCL

SDAVCLK count = 1 2 n 0

VCLK

Transmit-

Only mode

MODE

S1010 0000 ACK

n < 128

24LCS22A

FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA®

Communication

is idle

Is Vsync

present? No

Send EDID™ continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

S top sending EDID.

Switch to DDC2™ mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

No VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1™

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus™

Yes

Valid Access.bus

address? No

Yes

See Access.bus

specification to determine

correct procedure.

Yes

The 24LCS22A was designed to

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer Reset counter or timer

(if appropria te)

Counter=128 or

timer expired?

High-to-low

transition on

SCL? No

Yes

comply to the portion of flowchart inside dash box

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash b ox and tex t “The 24LCS2 2A and.. . inside d ash box.” are added b y Microchi p Technology In c.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS22A.

capable?

24LCS22A

3.1 Bidirectional Mode Bus

Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition

Accordingly, the following bus conditions have been

defined (Figure 3- 4).

3.1.1 BUS NOT BUSY (A)

Both data and clock lines remain high.

3.1.2 START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.1.3 STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of t he cl oc k sig na l. Ther e is one cloc k puls e per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last eight will

be stored when doing a write operation. When an

overwri te does occur it will replace da ta in a firs t-in first-

out (FIFO) fashion.

3.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line du ring the Acknow ledge cl ock pulse in s uch a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by no t g ene rati ng an Acknowledge bi t on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the master to generate the Stop cond ition.

FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: Onc e switch ed into Bi direction al mode , the

24LCS22A will remain in that mode until

powe r is r e mo ved. Re mo vi ng po we r i s the

only way to reset the 24LCS22A into the

Tran smi t-Only mode.

Note: The 24LCS22A does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

SDA

24LCS22A

FIGURE 3-5: BUS TIMING START/STOP

FIGURE 3-6: BUS TIMING DATA

3.1.6 SLAVE ADDRESS

After generating a Start condition, the bus master

transmi ts t he slav e addre ss co nsis ting of a 7 -bit dev ice

code (1010000) for the 24LC S22A.

The eigh th bit of s lave address determin es whether th e

master device wants to read or write to the 24LCS22A

(Figure 3-7).

The 24LCS22A monitors the bus for its corresponding

slave address continuously. It generates an

Ackno w l edg e bi t if the sl av e ad d r es s was tru e an d i t is

not in a Programming mode.

FIGURE 3-7: CONTROL BYTE

ALLOCATION

SCL

SDA

Start Stop

VHYS TSU:STO

THD:STA

TSU:STA

SCL

SDA

OUT

TSU:STA

TSP

TAA

TLOW

THIGH

THD:STA THD:DAT TSU:DAT TSU:STO

TBUF

TAA

Operation Slave Address R/W

Write 1010000 0

R/W A

1 0100 0 0

Read/Write

Start

Slave Address

24LCS22A

4.0 WRITE OPERATION

4.1 Byte Wr ite

Following the Start signal from the master, the slave

address (four bits), three zero bits (000) and the R/W

bit which is a logic low are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has gener ated an Ackno wledge bit durin g

the ninth clock cycle. Therefore, the next byte

tran smit ted by the ma ster is the word add res s and wi ll

be written into the Address Pointer of the 24LCS22A.

After receiving another Acknowledge signal from the

24LCS22A the master device will transmit the data

word to be wr itten into the addressed mem ory locatio n.

The 24LCS22A acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle, and during this time the 24LCS22A will not

generate Acknowledge signals (Figure 4-1).

It is required that VCLK be held at a logic high level

during command and data transfer in order to program

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high-to-low during the self-timed

program operation will not halt programming of the

device.

4.2 Page Write

The write control byte, word address and the first data

byte are tra nsmitted to the 24L CS22A in the same way

as in a byte write. But instead of generating a Stop

conditi on the m aster tran smit s up to eigh t dat a byt es to

the 24LCS22A which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the mas ter has tra nsmit ted a Stop conditi on. After

the rece ipt of eac h word, the three low er order Add ress

Pointer bits are internally incremented by one. The

higher order five bits of the word address remains

const a nt. If the maste r s hou ld tra nsm it m ore than eight

words prior to generating the Stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the Stop condition is received an

internal write cycle will begin (Figure 5-2).

It is required that VCLK be held at a logic high level

during command and data trans fer in order to progr am

the device. This applies to both byte write and page

write operation. Note, however, that the VCLK is

ignored during the self-timed program operation.

Changing VCLK from high-to-low during the self-timed

program operation will not halt programming of the

device.

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes actua ll y

being written. Physical page boundaries

start at addresses that are integer

multiples of the page buffer size (or ‘page

size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to th e nex t page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

24LCS22A

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: VCLK WRITE ENABLE TIMING

Bus Activity

Master

SDA Line

Bus Acti vity

Control

Byte Word

Address Data S

VCLK

SCL

SDA

VCLK

THD:STA TSU:STO

TVHST TSPVL

24LCS22A

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 5-1 for the flow

diagram.

FIGURE 5-1: ACKNOWLEDGE

POLLING FLOW

FIGURE 5-2: PAG E WRITE

Did Device

Acknowledge

(ACK = 0)?

Send

Write Command

Send St op

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

SDA Line

Control

Byte Word

Address

Data n + 1 Data n + 7

Data (n)

VCLK

Bus Activity

Master

Bus Activity

24LCS22A

6.0 WRITE PROTECTION

When using the 24LCS22A in the Bidirectional mode,

the VCLK pin can be used as a write-protect control

pin. Setting VCLK high allows normal write operations,

while setting VCLK low prev ent s writing to any locatio n

in the array. Connecting the VCLK pin to VSS would

allow the 24LCS22A to operate as a serial ROM,

although this configuration would prevent using the

device in the Transmit-Only mode.

Additionally, pin 3 performs a flexible write-protect

function. The 24LCS22A contains a write protection

control fuse whose factory default state is cleared.

Writing any data to address 7Fh (normally the

checksum in DDC applications) sets the fuse which

enables the WP pin. Until this fuse is set, the

24LCS2 2A is alway s write enabled (if VCLK = 1). After

the fuse is set, the write capability of the 24LCS22A is

determined by both VCLK and WP pins (Table 6-1).

TABLE 6-1: WRITE-PROTECT TRUTH

TABLE

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There a re three basic types

of read operations: current address read, random read

and sequential read.

7.1 Current Address Read

The 24LCS22A contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address n, the next current address read operation

would ac ce ss d at a from a ddress n + 1. Upon rec ei pt of

the slave address with R/W bit set to one, the

24LCS22A issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer , but does generate a S top condit ion and the

24LCS22A discontinues transmission (Figure 7-1).

FIGURE 7-1: CURRENT ADDRESS

READ

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad o peration, first the wo rd ad dres s m us t

be set. This is done b y sending the word address to the

24LCS22A as part of a write operation. After the word

address is sent, the master generat es a Start co nditio n

following the acknowledge. This terminates the write

operatio n, but not before the internal Address Pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24LCS22A will then

issue an acknowledge and transmits the 8-bit data

word. The master will not acknowledge the transfer, but

does generate a Stop condition and the 24LCS22A

discontinues transmission (Figure 7 -2).

VCLK WP Address

7Fh Written

Mode

for

00h - 7Fh

0X XRead-only

1X No R/W

11/open XR/W

10 Yes Read-only

Control

Byte Data n

Bus Ac tivit y

SDA Line

Bus Ac tivit y A

Master

10100001

24LCS22A

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

7.3 Sequential Read

Sequential reads are initiated in the same way as a

random r ead exce pt that after the 24LCS22 A tran smit s

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

direct s the 24LCS22A to transmit the nex t se que ntially

addressed 8-bit word (Figure 7-3).

To provide sequen tial reads the 24L CS22A cont ains an

internal Address Pointer which i s incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operati on .

7.4 Noise Protection

The 24LCS22A employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SDA, SCL and VCLK inputs have Schmitt Trigger

and filte r circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

Bus Activity

Master

SDA Line

Bus Activit y

Control

Byte Word

Address Data n

RControl

Byte

10100000 00000111

Bus Activit y

Master

SDA Line

Bus Activit y

Control

Byte Data n Data n+1 Data n+2 Data n+X

24LCS22A

8.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 8-1.

TABLE 8-1: PIN FUNCTION TABLE

8.1

W rite -Protect

(W P)

This pin is used for flexible write protection of the

24LCS22A. When memory location 7Fh is written with

any data, this pin is enabled and determines the write

capability of the 24LCS22A (Table 6-1).

8.2 Serial Address/Data Input/Output

(SDA)

This p in is use d to transfer addresses and data into and

out of th e device, w hen the dev ice is in th e Bidirectional

mode. In the Transmit-Only mode, which only allows

data to be read from the device, dat a is also tr ansferred

on the SDA pin. This pin is an open drain terminal,

therefore the SDA bus requires a pull-up resistor to

VCC (typical 10 kΩ for 100 kHz, 2 k Ω for 400 kHz).

For normal data transfer in the Bidirection al mode, SDA

is allowed to change only during SCL low. Changes

during SCL high are reserved for indicating the Start

and Stop conditions.

8.3 Serial Clock (SCL)

This pin is the clock input for the Bidirectional mode,

and is used to synchronize data transfer to and from the

device. It is also used as the signaling input to switch

the device from the Transmit-Only mode to the

Bidirectional mode. It must remain high for the chip to

continue operation in the Transmit-Only mode.

8.4 Serial Clock (VCLK)

This pin is the clock input for the Transmit-Only mode

(DDC1). In the Transmit-Only mode, each bit is clocked

out on the ris ing edg e of this si gnal. In the Bidire ctiona l

mode, a high logic level is req uired on this pi n to enable

write capability.

Name Function

Write-Protect

(active low)

VSS Ground

SDA Serial Address/Data I/O

SCL Serial Clock (Bidirectional mode)

VCLK Serial Clock (Transmit-Only mode)

VCC +2.5V to 5.5V Power Supply

NC No Inte rna l Connecti on

24LCS22A

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

24LCS22A

I/PNNN

0145

8-Lead SOIC (150 mil) Example:

*Standard marking consists of Microchip part number, year code, week code, traceability code (facility

code, mask re v#, and assembly code).

XXXXXXXX

XXXXYYWW

NNN

24LCS22A

I/SN0145

NNN

Legend: XX...X Part num ber or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the eve nt the full Microchi p part number c annot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific informati on.

24LCS22A

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24LCS22A

8-Lead Plastic Dual In-8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

24LCS22A

APPENDIX A: REVISION HIST ORY

Revision B

Corrections to Section 1.0, Electrical Characteristics.

Revision C

Revised Section 8.1. Added new pac kage legend.

24LCS22A

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24LCS22A

READER RESPONSE

It is ou r intention to pro vi de you with the best documentation po ss ib le to e ns ure successful u se of your Microchip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, su bject m atter , a nd ways in whic h our doc umenta tion

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DS21682C24LCS22A

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

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6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24LCS22A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.micr ochip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. X/XX

PackageTemperature

Range

Device

Device: 24LCS22A: 2K VESA E-EDI D Ser ial EEPROM

24LCS22AT: 2K VESA E-EDID Serial EEPROM

(Ta pe and Reel )

Temperature Range: I = -40°C to +85°C

Package: P = Plastic DIP (300 mil Body), 8-Lead

SN = Plastic SOIC (150 mil Body), 8-Lead

Examples:

a) 24LCS22A-I/P: Industrial temperature, PDIP

package.

b) 24LCS22A-I/SN: Industrial temperature, SOIC

package.

c) 24LCS22AT-I/SN:Tape and Reel, Industrial

temperature, SOIC package.

24LCS22A

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

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RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

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Microchip disclaims all liability arising from this information and

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written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

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