GAL22V10/883
High Performance E2CMOS PLD
Generic Array Logic™
1
Devices have been discontinued.
228
NC
I/CLK
I
I
I
I
I
I
I
I
NC NC
NC
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q I/O/Q
4
5
7
9
11
12 14 16 18
19
21
23
25
26
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 7ns Maximum from Clock Input to Data Output
— TTL Compatible 12 mA Outputs
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% REDUCTION IN POWER VERSUS BIPOLAR
•E
2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL22V10
Top View
LCC
1
12 13
24
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
6
18
GAL
22V10
CERDIP
Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. May 2010
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22v10mil_05
Description
The GAL22V10/883 is a high performance E2CMOS programmable
logic device processed in full compliance to MIL-STD-883. This
military grade device combines a high performance CMOS process
with Electrically Erasable (E2) floating gate technology to provide
the highest speed performance available of any military qualified
22V10 device. CMOS circuitry allows the GAL22V10 to consume
much less power when compared to bipolar 22V10 devices. E2
technology offers high speed (<100ms) erase times, providing the
ability to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Specifications GAL22V10D/883
2
Devices have been discontinued.
VIL Input Low Voltage Vss - 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -100 μA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 12 mA
IOH High Level Output Current — — -2.0 mA
IOS2Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C -50 — -135 mA
ICC Operating Power VIL = 0.5V VIH = 3.0V L -10/-15/-20/-25/-30 — 90 150 mA
Supply Current ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C.
Recommended Operating Conditions
Case Temperature (TC) ............................... -55 to 125°C
Supply Voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS
Absolute Maximum Ratings(1)
Supply voltage VCC ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Specifications GAL22V10D/883
3
Devices have been discontinued.
AC Switching Characteristics
Over Recommended Operating Conditions
tpd A Input or I/O to Combinatorial Output — 10 — 15 ns
tco A Clock to Output Delay — 7 — 8 ns
tcf2— Clock to Feedback Delay — 7 — 8 ns
tsu — Setup Time, Input or Feedback before Clock↑6—12—ns
th — Hold Time, Input or Feedback after Clock↑0—0—ns
A Maximum Clock Frequency with 76.9 — 50 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 76.9 — 50 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 166 — 62.5 — MHz
No Feedback
twh — Clock Pulse Duration, High 3 — 8 — ns
twl — Clock Pulse Duration, Low 3 — 8 — ns
ten B Input or I/O to Output Enabled — 10 — 15 ns
tdis C Input or I/O to Output Disabled — 12 — 15 ns
tar A Input or I/O to Asynchronous Reset of Register — 12 — 20 ns
tarw — Asynchronous Reset Pulse Duration 10 — 15 — ns
tarr — Asynchronous Reset to Clock Recovery Time 6 — 15 — ns
tspr — Synchronous Preset to Clock Recovery Time 10 — 12 — ns
-15
MIN. MAX.
PARAMETER UNITS
TEST
COND.1DESCRIPTION
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CIInput Capacitance 10 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 10 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
Capacitance (TA = 25°C, f = 1.0 MHz)
-10
MIN. MAX.
Specifications GAL22V10/883
4
Devices have been discontinued.
AC Switching Characteristics
Over Recommended Operating Conditions
tpd A Input or I/O to Combinatorial Output — 20 — 25 — 30 ns
tco A Clock to Output Delay — 15 — 20 — 20 ns
tcf2— Clock to Feedback Delay — 15 — 20 — 20 ns
tsu — Setup Time, Input or Feedback before Clock↑17 — 20 — 25 — ns
th — Hold Time, Input or Feedback after Clock↑0—0—0—ns
A Maximum Clock Frequency with 31.2 — 25 — 22 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 31.2 — 25 — 22 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 33 — 33 — 25 — MHz
No Feedback
twh — Clock Pulse Duration, High 15 — 15 — 20 — ns
twl — Clock Pulse Duration, Low 15 — 15 — 20 — ns
ten B Input or I/O to Output Enabled — 20 — 25 — 25 ns
tdis C Input or I/O to Output Disabled — 20 — 25 — 25 ns
tar A Input or I/O to Asynchronous Reset of Register — 25 — 30 — 30 ns
tarw — Asynchronous Reset Pulse Duration 20 — 25 — 30 — ns
tarr — Asynchronous Reset to Clock Recovery Time 20 — 25 — 30 — ns
tspr — Synchronous Preset to Clock Recovery Time 17 — 20 — 25 — ns
-30
MIN. MAX.
PARAMETER UNITS
TEST
COND.1DESCRIPTION -25
MIN. MAX.
-20
MIN. MAX.
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CIInput Capacitance 10 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 10 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
Capacitance (TA = 25°C, f = 1/0 MHz)
Specifications GAL22V10D/883
Specifications GAL22V10/883
5
Devices have been discontinued.
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/
f
max
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
Clock Width
fmax with Feedback
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
REGISTERED
OUTPUT
CLK
t
arw
t
ar
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
CLK
(
w/o fdbk
)
t
wh
1/
f
max
t
wl
Asynchronous ResetSynchronous Preset
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
Switching Waveforms
Specifications GAL22V10/883
6
Devices have been discontinued.
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
REGISTER
LOGIC
ARRAY
CLK
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition R1R2CL
A 390Ω750Ω50pF
B Active High ∞750Ω50pF
Active Low 390Ω750Ω50pF
C Active High ∞750Ω5pF
Active Low 390Ω750Ω5pF
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
fmax Descriptions
Switching Test Conditions
Specifications GAL22V10/883
7
Devices have been discontinued.
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Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
1. Discontinued per PCN #05A-10.
GAL22V10 Ordering Information (MIL-STD-883 and SMD)
Part Number Description
MIL Process /883 = 883 Process
Package
PowerL = Low Power
Speed (ns)
XXXXXXXX XX X X X
Device Name
_
D = CERDIP
R = LCC
GAL22V10D
