1
©1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
DSC-3821/2
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Pin Description Summary
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
Features
◆◆
◆◆
◆128K x 36 memory configuration, pipelined outputs
◆◆
◆◆
◆Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized registered outputs eliminate the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆Single 3.3V power supply (+/- 5%)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin TQFP package
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not active
when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the LBO input
pin. The LBO pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
IDT71V546
128K x 36, 3.3V Synchronous
SRAM with ZBT
Feature,
Burst Counter and Pipelined Outputs
A0 - A16 Address Inputs Input Synchronous
CE1, CE2, CE2Three Chip Enables Input Synchronous
OE Output Enable Input Asynchronous
R/WRead/Write Signal Input Synchronous
CEN Clock Enable Input Synchronous
BW1, BW2, BW3, BW4Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV/LD Advance Burst Address / Load New Address Input Synchronous
LBO Linear / Interleaved Burst Order Input Static
I/O0 - I/O31
, I/OP1 - I/OP4 Data Inp ut/Output I/O Synchronous
VDD 3.3V Power Supply Static
VSS Ground Supply Static
3821 tbl 01
2
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A0 - A16 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/LD Low, CEN Low and true
chip enables.
ADV/LD Address/Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/WRead/Write I N/A R/W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low
at rising edge of clock.
BW1 - BW4Individual Byte
Write Enables
I LOW Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low)
the appropriate byte write signal (BW1 - BW4) must be valid. The byte write
signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later. BW1 - BW4 can all be tied low if always doing
write to the entire 36-bit word.
CE1, CE2Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to
enable the IDT71V546. (CE1 or CE2 sampled high or CE2 sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
CE2 Chip Enable I HIGH Synchronout active high chip enable. CE2 is used with CE1 and CE2 to enable
the chip . CE2 has inverted polarity but otherwise identical to CE1 and CE2.
CLK Clock I N/A This is the clock input to the IDT71V546. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O0 - I/O31
I/OP1 - I/OP4
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
LBO Linear Burst
Order
I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a
static DC input.
OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V546.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
VDD Power Supply N/A N/A 3.3V power supply input.
VSS Ground N/A N/A Ground pin.
3821 tbl 02
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
3
Functional Block Diagram
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
Input Register
3821 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1,CE
2,
CE2R/W
CEN
ADV/LD
BWx
LBO 128K x 36 BIT
MEMORY ARRAY
.
Grade Temperature VSS VDD
Commercial 0OC to +70OC0V 3.3V
+ 5%
3821 tbl 03
NOTES:
1. VIL (min.) = 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 3.135 3.3 3.465 V
VSS Ground 0 0 0 V
VIH Input High Voltage - Inputs 2.0 ____ 4.6 V
VIH Input High Voltage - I/O 2.0 ____ VDD+0.3(2) V
VIL Input Low Voltage -0.5(1) ____ 0.8 V
38 21 tbl 04
4
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Absolute Maximum Ratings(1) Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Pin Configuration
TOP VIEW
TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O31
I/O30
VDD
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDD
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDD
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDD
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDD
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDD
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDD
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDD
I/O1
I/O0
PK100-1
3821 drw 02
VDD(1)
I/O15
I/OP3
VDD
I/OP4
A
15
A
16
I/OP1
VDD
I/OP2
VSS
.
.
Symbol Rating Commercial Unit
VTE RM(2 ) Te rm i nal Vo l tag e
with Respect to GND
-0.5 to +4.6 V
VTE RM(3 ) Te rm i nal Vo l tag e
with Respect to GND
-0.5 to VDD+0.5 V
TAOperating Temperature 0 to +70 oC
TBIAS Temperature Under Bias -55 to +125 oC
TSTG Storage Temperature -55 to +125 oC
PTPower Dissipation 2.0 W
IOUT DC Output Current 50 mA
3821 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 3dV 5 pF
CI/O I/O Capacitance VOUT = 3dV 7 pF
3821 tbl 06
NOTES:
1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH.
2. Pin 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
5
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = VIL, H = VIH, X = Dont Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
CEN R/WChip(5)
Enable
ADV/LD BWxADDRESS
USED
PREVIOUIS CYCLE CURRENT CYCLE I/O
(2 cycles later)
L L Select L Valid External X LOAD WRITE D(7)
L H Select L X External X LOAD READ Q(7)
L X X H Valid Internal LOAD WRITE/
BURST WRITE
BURST WRITE
(Advance Burst Counter)(2) D(7)
L X X H X Internal LOAD READ/
BURST READ
BURST READ
(Advance Burst Counter)(2) Q(7)
L X Deselect L X X X DESELECT or STOP(3) HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
HXX XXX X SUSPEND
(4) Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Dont Care.
2. Multiple bytes may be selected during the same cycle.
Operation R/WBW1BW2BW3BW4
READ HXXXX
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O [0:7], I/OP1)(2) LLHHH
WRITE BYTE 2 (I/O [8:15], I/OP2)(2) LHLHH
WRITE BYTE 3 (I/O [16:23], I/OP3)(2) LHHLH
WRITE BYTE 4 (I/O [24:31], I/OP4)(2) LHHHL
NO WRITE LHHHH
3821 tbl 08
6
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Functional Timing Diagram(1)
NOTE:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
A37
C37
D/Q35
n+29
A29
C29
D/Q27
ADDRESS
(A0 - A16)
CONTROL
(R/W, ADV/LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
(2)
(2)
(2)
3821 drw 03
n+37
A37
C37
D/Q35 ,
Interleaved Burst Sequence Table (LBO=VDD)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address00011011
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11 10 01 00
3821 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address00011011
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11 00 01 10
3821 tbl 10
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
7
Device Operation - Showing Mixed Load,
Burst, Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Dont Care; Z = High Impedance.
Cycle Address R/WADV/LD CE(1) CEN BWxOE I/O Comments
n A0 H L L L X X X Load read
n+1 X X H X L X X X Burst read
n+2 A1 H L L L X L Q0 Load read
n+3 X X L H L X L Q0+1 Deselect or STOP
n+4 X X H XLXLQ1NOOP
n+5 A2 H L L L X X Z Load read
n+6 X X H X L X X Z Burst read
n+7 X X L H L X L Q2 Deselect or STOP
n+8 A3 L L L L L L Q2+1 Load write
n+9 X X H X L L X Z Burst write
n+10 A4 L L L L L X D3 Load write
n+11 X X L H L X X D3+1 Deselect or STOP
n+12 X X H X L X X D4 NOOP
n+13 A5 L L L L L X Z Load write
n+14 A6 H L L L X X Z Load read
n+15 A7 L L L L L X D5 Load write
n+16 X X H X L L L Q6 Burst write
n+17 A8 H L L L X X D7 Load read
n+18 X X H X L X X D7+1 Burst read
n+19 A9 L L L L L L Q8 Load write
3821 tbl 11
8
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Read Operation(1)
NOTE:
1. H = High; L = Low; X = Dont Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Read Operation(1)
NOTE:
1. H = High; L = Low; X = Dont Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X L X X X Clock Setup Valid
n+2 X X X X X X L Q0 Contents of Address A0 Read Out
3821 tbl 12
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H X L X L Q0 Ad dress A0 Read Out, Inc. Count
n+3 X X H XLXLQ
0+1 Address A0+1 Read Out, Inc. Count
n+4 X X H XLXLQ
0+2 Address A0+2 Read Out, Inc. Count
n+5 A1 H L L L X L Q0+3 Address A0+3 Read Out, Load A1
n+6 X X H X L X L Q0 Ad dress A0 Read Out, Inc. Count
n+7 X X H X L X L Q1 Ad dress A1 Read Out, Inc. Count
n+8 A2 H L L L X L Q1+1 Address A1+1 Read Out, Load A2
3821 tbl 13
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
9
NOTE:
1. H = High; L = Low; X = Dont Care; ? = Dont Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
NOTE:
1. H = High; L = Low; X = Dont Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X XLXXXClock Setup Valid
n+2 X X X X L X X D0 Write to Address A0
3821 tbl 14
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. Count
n+2 X X H X L L X D0 Address A0 Write, Inc. Count
n+3 X X H X L L X D0+1 Address A0+1 Write, Inc. Count
n+4 X X H X L L X D0+2 Address A0+2 Write, Inc. Count
n+5 A1 L L L L L X D0+3 Address A0+3 Write, Load A1
n+6 X X H X L L X D0 Address A0 Write, Inc. Count
n+7 X X H X L L X D1 Address A1 Write, Inc. Count
n+8 A2 L L L L L X D1+1 Address A1+1 Write, Load A2
3821 tbl 15
10
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
NOTE:
1. H = High; L = Low; X = Dont Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation With Clock Enable Used(1)
NOTE:
1. H = High; L = Low; X = Dont Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A1 H L LLXXXClock Valid
n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus
n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus
n+5 A2 H L L L X L Q0 Address A0 Read out (but trans.)
n+6 A3 H L L L X L Q1 Ad dress A1 Read out (bus trans.)
n+7 A4 H L L L X L Q2 Ad dress A2 Read out (bus trans.)
38 21 tb l 16
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A1 L L L L L X X Clock Valid
n+3 X X X XHXXXClock Ignored
n+4 X X X XHXXXClock Ignored
n+5 A2 L L L L L X D0 Write data D0
n+6 A3 L L L L L X D1 Write data D1
n+7 A4 L L L L L X D2 Write data D2
3821 tb l 17
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
11
NOTES:
1. H = High; L = Low; X = Dont Care; ? = Dont Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation With Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Dont Care; ? = Dont Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation With Chip Enable Used(1)
Cycle Address R/WADV/LD CE(1) CEN BWxOE I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 H L L L X L Q0 Address A0 read out. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X L Q1 Address A1 Read out. Deselected
n+7 A2 H L L L X X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X L Q2 Address A2 read out. Deselected
3821 tbl 18
Cycle Address R/WADV/LD CE(1) CEN BWxOE I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 L L L L L X D0 Address D0 Write In. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X X D1 Address D1 Write In. Deselected
n+7 A2 L L L L L X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X X D2 Address D2 Write In. Deselected
38 21 tb l 19
12
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
DC Electrical Characteristics Over the Opearting Temperature
and Supply Voltage Range(1)
(VDD = 3.3V +/-5%, VHD = VDD0.2V, VLD = 0.2V)
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range
(VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads AC Test Conditions
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
3821 drw 05 ,
1.5V
50Ω
I/O Z0=50Ω
3821 drw 04
+
,
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
Symbol Parameter Test Conditions Min. Max. Unit
|ILI| Input Leakage Current VDD = Max., VIN = 0V to VDD ___ 5µA
|ILI
|LBO Input Leakage Current(1) VDD = Max., VIN = 0V to VDD ___ 30 µA
|ILO|Output Leakage Current CE > VIH or OE > VIH, VOUT
= 0V toVDD, VDD = Max. ___ 5µA
VOL Output Low Voltage IOL = 5mA, VDD = Min. ___ 0.4 V
VOH Output High Voltage IOH = -5mA, VDD = Min. 2.4 ___ V
3821 tbl 20
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
Symbol Parameter Test Conditions S133 S117 S100 Unit
IDD Operating Power
Supply Current
Device Selected, Outputs Open, ADV/LD = X,
VDD = Max., VIN > VIH or < VIL, f = fMAX(2) 300 275 250 mA
ISB1 CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD, f = 0(2) 40 40 40 mA
ISB2 Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 110 105 100 mA
ISB3 Idle Power
Supply Current
Device Selected, Outputs Open, CEN > VIH
VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 40 40 40 mA
3821 t bl 21
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figures 1
38 21 tbl 22
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
13
AC Electrical Characteristics (VDD = 3.3V +/-5%, TA = 0 to 70°C)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 2.0V and LOW below 0.8V.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
Symbol Parameter
71V546S133 71V546S117 71V546S100
Unit
Min. Max. Min. Max. Min. Max.
Clock Parameters
tCY C Clock Cycle Time 7.5 ____ 8.5 ____ 10 ____ ns
tF(1) Clock Frequency ____ 133 ____ 117 ____ 100 MHz
tCH(2) Clock High Pulse Width 2.5 ____ 3____ 3.5 ____ ns
tCL(2) Clock Low Pulse Width 2.5 ____ 3____ 3.6 ____ ns
Output Parameters
tCD Clock High to Valid Data ____ 4.2 ____ 4.5 ____ 5ns
tCDC Clock High to Data Change 1.5 ____ 1.5 ____ 1.5 ____ ns
tCL Z(3 , 4,5) Clock High to Output Active 1.5 ____ 1.5 ____ 1.5 ____ ns
tCHZ(3 , 4,5 ) Clock High to Data High-Z 1.5 3.5 1.5 3.5 1.5 3.5 ns
tOE Output Enable Access Time ____ 4.2 ____ 4.5 ____ 5ns
tOLZ(3,4) Output Enable Low to Data Active 0 ____ 0____ 0____ ns
tOHZ(3.4) Output Enable High to Data High-Z ____ 3.5 ____ 3.5 ____ 3.5 ns
Setup Times
tSE Clock Enable Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
tSA Address Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
tSD Data in Setup Time 1.7 ____ 1.7 ____ 2.0 ____ ns
tSW Read/Write (R/W) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
tSADV Advance/Load (ADV/LD) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
tSC Chip Enable/Select Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
tSB Byte Write Enable (BWx) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns
Hold Times
tHE Clock Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHD Data in Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHW Read/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHADV Advance/Load (ADV/LD) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHB Byte Write Enable (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
3821 tbl 23
14
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the
burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
(CENhigh, eliminates
current L-H clock edge)
tCD
tHADV
Pipeline
Read
(Burst Wraps around
to initial state)
tCDC
tCLZ tCHZ
tCD
tCDC
R/W
CLK
CEN
ADV/LD
ADDRESS
OE
DATAOut
tHE
tSE
A1A2
O1(A1) O1(A2) O1(A2)
tCHtCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst Pipeline Read
Pipeline
Read
CE
1,
CE
2(2)
Q(A
2+1
)Q(A
2+2
)Q(A
2+2
)Q(A
2+3
)
3821 drw 06
BW
1,
BW
4
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
15
Timing Waveform of Write Cycles(1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
OE
DATAIn
tHD
tSD
tCHtCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
tHB
tSB
(Burst Wraps around
to initial state)
tHD
tSD
(CENhigh, eliminates
current L-H clock edge)
CE
1,
CE
2
(2)
D(A
2+1
)D(A
2+2
)D(A
2+3
)
D(A1) D(A2) D(A2)
3821 drw 07
BW
1,
BW
4
.
16
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
DATAOut Q(A3)
Q(A1) Q(A6) Q(A7)
tCD
Read
Write
tCLZ
tCHZ
tCHtCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
D(A2) D(A4)
tSDtHD
tCDC
D(A5)
tHADV
tSADV
A6A7A8
A5A9
Read
Write
Read
DATAIn
tHB
tSB
3821 drw 08
CE
1
,CE
2
(2)
BW
1
-BW
4
OE
.
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
17
Timing Waveform of CEN Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH..
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition
did not occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
BW
1
-BW
4
OE
DATAOut Q(A3)
tCD
tCLZ
tCHZ
tCHtCL
tCYC
tHC
tSC
D(A2)
tSDtHD
tCDC
A4A5
tHADV
tSADV
tHW
tSW
tHA
tSA
A3
tHB
tSB
DATAIn
3821 drw 09
CE2
(2)
Q(A1)
B(A2)
CE1,
Q(A1)
.
18
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states two cycles after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATAOut Q(A1)
tCD
tCLZ
tCHZ
tCDC
tCHtCL
tCYC
tHC
tSC
tSDtHD
A5
A3
tSB
DATAIn
tHE
tSE
A2
tHA
tSA
A4
tHW
tSW
tHB
CEN
tHADV
tSADV
3821 drw 10
Q(A2) Q(A3)
D(A3)
BW
1
-BW
4
CE
1
,CE
2
(2)
6.42
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
19
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ tOLZ
tOE
Valid
3821 drw 1
1
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
S
Power
XX
Speed
PF
Package
PF
IDT 71V546
133
117
100 Clock Frequency in Megahertz
3821 drw 12
Device
Type
PART NUMBER SPEED IN MEGAHERTZTCD PARAMETER CLOCK CYCLE TIME
71V546S133PF
71V546S117PF
71V546100PF
133 MHz
117 MHz
100 MHz
4.2 ns
4.5 ns
5ns
7.5 ns
8.5 ns
10 ns
20
IDT71V546 128K x 36
3.3V Synchronous SRAM with ZBT
Feature, Burst Counter and Pipelined Outputs Commercial Temperature Range
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726, x4033
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/15/99 Updated to new format
9/13/99 Pg. 12 Corrected ISB3 conditions
Pg. 20 Added Datasheet Document History