Maxim I nte grat ed Pr od uct s 1
Some revisions of this device may incorporate deviations from published specificatio ns known as errata. Multiple
revisions of any device may be simultaneously available through vario us sales channels . For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, p leas e contact Maxim Dire ct at
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DS26514
4-Port T 1/E1/J1 Tra nscei ver
______________ General Description
The DS26514 is a 4-port framer and line interface
unit (LIU) combination for T1, E1, J1 applications.
Each port is independently configurable, supporting
both long-haul and short-haul lines. The DS26514
single-chip transceiver (SCT) is software and pinout
compatible with the 8-port DS26518. It is nearly
software compatible with the DS26528 and its
derivatives.
___________________ Applications
Routers
Channel S ervic e Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel B ank s
T1/E1 Test Equipmen t
______________ Functional Diagram
DS26514
T1/J1/E1
Transceiver
T1/E1/J1
NETWORK
BACKPLANE
TDM
x4
______________ Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS26514GN -40°C to +85°C 256 TE-CSBGA
DS26514GN+ -40°C to +85°C 256 TE-CSBGA
+Denotes a lead(Pb)-free/RoHS compliant package.
_______________________ Features
♦ Four Co mpl et e T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
♦ Indep end ent T1, E1, o r J1 Select ions f or Each
Transceiver
♦ Fu lly Int e r nal Im pe dance Match, N o E x te r na l
Resistor
♦ Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Tw is t e d Pa ir ,
110Ω J1 Twisted Pair, 120Ω E 1 Twis ted Pair ,
and 75Ω E1 Coaxial Applications
♦ Hitl ess P rotection Switching
♦ Crystal-Less Jitter Attenuato rs Can Be
Select ed for Transmit or Recei ve P ath; Jitter
Attenuat or Meets ETS CTR 12/13, ITU-T
G. 736, G.742, G.823, and AT&T Pub 62411
♦ External Master Clock Can Be Multipl e of
2.048MHz or 1.544M Hz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in th e Host Mode
♦ Receive-Signal Level Indi cat io n from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44 dB in E1
Mode in Approximat e 2.5dB In crements
♦ Transmit Open- and Short-Circui t Detection
♦ LIU LOS in Accordance with G.775, ETS 300
233, and T1 .231
♦ Transmit Synchronizer
♦ Fle x i ble S ig na lin g Extraction an d Insertion
Usin g Either the System Int erf ace or
Microprocessor Port
♦ Alarm Detect ion and In sert io n
♦ T 1 Framing Format s of D4, SLC-96 , and ESF
♦ J1 Support
♦ E1 G. 704 and CRC-4 Multif rame
♦ T1-to-E1 Conversion
Features continued in Section 2.
19-5856; Rev 4; 5/11
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 2 of 305
TABLE OF CONTENTS
1. DETAILED DESCRIPTION ................................................................................................. 9
2. FEATURE HIGHLIGHTS .................................................................................................. 10
2.1 GENERAL ................................................................................................................................... 10
2.2 LINE INTERFACE ......................................................................................................................... 10
2.3 CLOCK SYNTHESIZERS ............................................................................................................... 10
2.4 JITTER ATTENUATOR .................................................................................................................. 10
2.5 FRAMER/FORMATTER ................................................................................................................. 11
2.6 SYSTEM INTERFACE ................................................................................................................... 11
2.7 HDLC CONTROLLERS ................................................................................................................. 12
2.8 TEST AND DIAGNOSTICS ............................................................................................................. 12
2.9 MICROCONTROLLER PARALLEL PORT .......................................................................................... 12
2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES .......................................................... 12
3. APPLICATIONS ............................................................................................................... 13
4. SPECIFICATIONS COMPLIANCE ................................................................................... 14
5. ACRONYMS AND GLOSS ARY ....................................................................................... 16
6. MAJOR OPERATING MODES ......................................................................................... 17
7. BLOCK DIAGR AMS ......................................................................................................... 18
8. PIN DESC RIPTIONS ........................................................................................................ 20
8.1 PIN FUNCTIONAL DESCRIPTION ................................................................................................... 20
9. FUNCTIONAL DESCRIPTION ......................................................................................... 28
9.1 PROCESSOR INTERFACE ............................................................................................................. 28
9.1.1 SPI Serial Por t Mode....................................................................................................................... 28
9.1.2 SPI Functional Timing Diagram s ..................................................................................................... 28
9.2 CLOCK STRUCTURE .................................................................................................................... 31
9.2.1 Backplane Clock Generation ........................................................................................................... 31
9.2.2 CLKO Output Clock Generation ...................................................................................................... 32
9.3 RESETS AND POWER-DOWN MODES ........................................................................................... 33
9.4 INITIALIZATION AND CONFIGURATION ........................................................................................... 34
9.4.1 Example Devic e Init ialization and Seque nc e ................................................................................... 34
9.5 GLOBAL RESOURCES.................................................................................................................. 34
9.6 PER-PORT RESOURCES.............................................................................................................. 34
9.7 DEVICE INTERRUPTS .................................................................................................................. 34
9.8 SYSTEM BACKPLANE INTERFACE ................................................................................................. 36
9.8.1 Elastic S tores .................................................................................................................................. 36
9.8.2 IBO M ultiplexing .............................................................................................................................. 39
9.8.3 H.100 (CT B us) Compatibility .......................................................................................................... 45
9.8.4 Transm it and Receive Channel Block ing Regis ters.......................................................................... 47
9.8.5 Transm it Fractional S uppor t (Gapped Cloc k M ode) ......................................................................... 47
9.8.6 Receive Fr ac tional Support (Gapped Cloc k M ode) .......................................................................... 47
9.9 FRAMERS ................................................................................................................................... 48
9.9.1 T1 Fr aming ..................................................................................................................................... 48
9.9.2 E1 Fram ing ..................................................................................................................................... 51
9.9.3 T1 Tr ansmit Synchr onizer ............................................................................................................... 53
9.9.4 Signaling ......................................................................................................................................... 54
9.9.5 T1 Data Link ................................................................................................................................... 59
9.9.6 E1 Data Link ................................................................................................................................... 61
9.9.7 Maintenance and A lar m s................................................................................................................. 62
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 3 of 305
9.9.8 Alarms ............................................................................................................................................ 65
9.9.9 Error Count Registers ..................................................................................................................... 67
9.9.10 DS0 Monitor ing Function ................................................................................................................. 69
9.9.11 Transmit Per-Channel Idle Code Gener ation ................................................................................... 70
9.9.12 Receive Per-Channel Id le Code Inser tion ........................................................................................ 70
9.9.13 Per-Channel Loopback ................................................................................................................... 70
9.9.14 E1 G. 706 Int er m ediate CRC-4 Updating (E1 Mode Only) ................................................................ 70
9.9.15 T1 Progr am m able In-Band Loop Code Generator............................................................................ 71
9.9.16 T1 Progr am m able In-Band Loop Code Detection ............................................................................ 72
9.9.17 Framer P ay load Loopbac k s............................................................................................................. 73
9.10 HDLC CONTROLLERS ............................................................................................................. 74
9.10.1 HDLC-64 Controller ........................................................................................................................ 74
9.10.2 Transm it HDLC-64 Controller .......................................................................................................... 77
9.10.3 HDLC-256 Controller....................................................................................................................... 78
9.11 POWER-SUPPLY DECOUPLING ................................................................................................. 84
9.12 LINE INTERFACE UNITS (LIUS) ................................................................................................. 85
9.12.1 LIU Operation ................................................................................................................................. 87
9.12.2 Transmitter ..................................................................................................................................... 88
9.12.3 Receiver ......................................................................................................................................... 91
9.12.4 Hitless P r otection Switching ( HP S ) .................................................................................................. 95
9.12.5 Jitt er Attenuator .............................................................................................................................. 96
9.12.6 LIU Loopbacks ................................................................................................................................ 97
9.13 BIT ERROR-RATE TEST FUNCTION (BERT) ..............................................................................100
9.13.1 BERT Repetitive Patt er n Set ......................................................................................................... 101
9.13.2 BERT Error Counter ...................................................................................................................... 101
10. DEVICE REG ISTERS ..................................................................................................... 102
10.1 REGISTER LISTINGS ...............................................................................................................102
10.1.1 Global Regist er Lis t ....................................................................................................................... 103
10.1.2 Framer Regis ter List...................................................................................................................... 104
10.1.3 LIU Register List ........................................................................................................................... 111
10.1.4 BERT Regis ter List ....................................................................................................................... 112
10.1.5 HDLC-256 Register Lis t ................................................................................................................ 113
10.2 REGISTER BIT MAPS ..............................................................................................................114
10.2.1 Global Regist er B it Map ................................................................................................................ 114
10.2.2 Framer Register Bit Map ............................................................................................................... 115
10.2.3 LIU Register Bit Map ..................................................................................................................... 124
10.2.4 BERT Regis ter Bit Map ................................................................................................................. 125
10.2.5 HDLC-256 Regis ter Bit M ap .......................................................................................................... 126
10.3 GLOBAL REGISTER DEFINITIONS .............................................................................................127
10.4 FRAMER REGISTER DESCRIPTIONS .........................................................................................142
10.4.1 Receive Regist er Des c r ipt ions ...................................................................................................... 142
10.4.2 Transm it Register Descriptions ..................................................................................................... 199
10.5 LIU REGISTER DEFINITIONS ....................................................................................................236
10.6 BERT REGISTER DEFINITIONS ................................................................................................246
10.7 EXTENDED BERT REGISTER DEFINITIONS ...............................................................................253
10.8 HDLC-256 REGISTER DEFINITIONS .........................................................................................257
10.8.1 Transm it HDLC-256 Register Definitions ....................................................................................... 257
10.8.2 Receive HDLC-256 Regist er Definitions ........................................................................................ 260
11. FUNCTIONAL TIMING ................................................................................................... 264
11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................264
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................269
11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................274
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................278
12. OPERATING PARAMETERS ......................................................................................... 283
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 4 of 305
12.1 THERMAL CHARACTERISTICS ..................................................................................................284
12.2 LINE INTERFACE CHARACTERISTICS ........................................................................................284
13. AC TIMING CHARACTERISTICS .................................................................................. 285
13.1 MICROPROCESSOR BUS AC CHARACTERISTICS .......................................................................285
13.1.1 SPI Bus Mode ............................................................................................................................... 285
13.2 JTAG INTERFACE TIMING .......................................................................................................296
14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................ 297
14.1 TAP CONTROLLER STATE MACHINE ........................................................................................298
14.1.1 Test-Logic-Reset........................................................................................................................... 298
14.1.2 Run-Test-Idle ................................................................................................................................ 298
14.1.3 Select-DR-Scan ............................................................................................................................ 298
14.1.4 Capture-DR .................................................................................................................................. 298
14.1.5 Shift-DR ........................................................................................................................................ 298
14.1.6 Exit1-DR ....................................................................................................................................... 298
14.1.7 Pause-DR ..................................................................................................................................... 298
14.1.8 Exit2-DR ....................................................................................................................................... 298
14.1.9 Update-DR .................................................................................................................................... 298
14.1.10 Select-IR-Scan .......................................................................................................................... 298
14.1.11 Capture-IR ................................................................................................................................ 299
14.1.12 Shift-IR ...................................................................................................................................... 299
14.1.13 Exit1-IR ..................................................................................................................................... 299
14.1.14 Pause-IR ................................................................................................................................... 299
14.1.15 Exit2-IR ..................................................................................................................................... 299
14.1.16 Update-IR .................................................................................................................................. 299
14.2 INSTRUCTION REGISTER .........................................................................................................301
14.2.1 SAMPLE:PRELOAD ..................................................................................................................... 301
14.2.2 BYPASS ....................................................................................................................................... 301
14.2.3 EXTEST ....................................................................................................................................... 301
14.2.4 CLAMP ......................................................................................................................................... 301
14.2.5 HIGHZ .......................................................................................................................................... 301
14.2.6 IDCODE ....................................................................................................................................... 301
14.3 JTAG ID CODES ....................................................................................................................302
14.4 TEST REGISTERS ...................................................................................................................302
14.4.1 Boundary Sc an Regis ter ............................................................................................................... 302
14.4.2 Bypass Regis ter ............................................................................................................................ 302
14.4.3 Identification Register.................................................................................................................... 302
15. PIN CONF IGURATION ................................................................................................... 303
15.1 PIN CONFIGURATION—256-BALL TE-CSBGA .........................................................................303
16. PACK AGE INFORMAT ION ............................................................................................ 304
17. DOCUMENT REVISION HISTORY ................................................................................ 305
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 5 of 305
LIST OF FIGURES
Figure 7-1. Block Diagr am ................................................................................................................................... 18
Figure 7-2. Detailed Block Diagr am ...................................................................................................................... 19
Figure 9-1. SPI Serial P ort Access f or Read M ode, SP I_CPOL = 0, SPI_CPHA = 0 ............................................. 29
Figure 9-2. SPI Serial P ort Access f or Read M ode, SP I_CPOL = 1, SPI_CPHA = 0 ............................................. 29
Figure 9-3. SPI Serial P ort Access f or Read M ode, SP I_CPOL = 0, SPI_CPHA = 1 ............................................. 29
Figure 9-4. SPI Serial P ort Access f or Read M ode, SP I_CPOL = 1, SPI_CPHA = 1 ............................................. 29
Figure 9-5. SPI Serial P ort Access f or Writ e Mode, S PI_CPOL = 0, SPI_CPHA = 0 .............................................. 29
Figure 9-6. S P I Se r ial P ort Access f or Write Mode, S PI_CPOL = 1, SP I_CPHA = 0 .............................................. 30
Figure 9-7. SPI Serial P ort Access f or Writ e Mode, S PI_CPOL = 0, SPI_CPHA = 1 .............................................. 30
Figure 9-8. SPI Serial P ort Access f or Writ e Mode, S PI_CPOL = 1, SPI_CPHA = 1 .............................................. 30
Figure 9-9. Backplane Cloc k Generation .............................................................................................................. 31
Figure 9-10. Device Interr upt Inf ormation Fl ow Diagr am ....................................................................................... 35
Figure 9-11. IBO Mult iple xer Equivalent Circu it—4.096MHz ................................................................................. 40
Figure 9-12. IBO Multiplexer Equiva lent C ircuit—8.192MHz ................................................................................. 41
Figure 9-13. IBO Mult iple xer Equivalent Circu it—16.384MHz ............................................................................... 42
Figure 9-14. RSYNCn Input in H. 100 ( CT Bus) Mode ........................................................................................... 46
Figure 9-15. TSSYNCIOn (Input Mode) Input in H. 100 (CT B us) Mode ................................................................. 46
Figure 9-16. CRC-4 Recalculate Method .............................................................................................................. 70
Figure 9-17. HDLC Message Receive Ex am ple .................................................................................................... 76
Figure 9-18. HDLC Message Tr ansmit Ex am ple ................................................................................................... 78
Figure 9-19. Receive HDLC Exam ple ................................................................................................................... 81
Figure 9-20. HDLC Message Tr ansmit Ex am ple ................................................................................................... 83
Figure 9-21. Network Connect ion—Longitudinal Prot ection .................................................................................. 86
Figure 9-22. T1 /J1 Trans mit Pulse Templates ...................................................................................................... 89
Figure 9-23. E1 Transmit Pulse Templ ates........................................................................................................... 89
Figure 9-24. Receive LIU Termi nation Options ..................................................................................................... 91
Figure 9-25. Typic al Moni tor Application ............................................................................................................... 93
Figure 9-26. HPS Bl oc k Diagr am ......................................................................................................................... 95
Figure 9-27. Jitter Attenuation .............................................................................................................................. 96
Figure 9-28. Loopback Diagram ........................................................................................................................... 97
Figure 9-29. Anal og Loopback ............................................................................................................................. 97
Figure 9-30. Local Loopback ................................................................................................................................ 98
Figure 9-31. Remote Loopback 2 ......................................................................................................................... 98
Figure 9-32. Dual Loopback ................................................................................................................................. 99
Figure 11-1. T1 Receiv e-Side D4 Timing ............................................................................................................ 264
Figure 11-2. T1 Receiv e-Si de ESF Timi ng ......................................................................................................... 264
Figure 11-3. T1 Receiv e-Si de B oundar y Timing ( El astic Store Disabled) ............................................................ 265
Figure 11-4. T1 Receiv e-Si de 1.544MHz B oundar y Timing ( El astic Store Enabled) ............................................ 265
Figure 11-5. T1 Receiv e-Si de 2.048MHz B oundar y Timing ( El astic Store Enabled) ............................................ 266
Figure 11-6. T1 Receiv e-Si de Int erl eave Bus O per ation—BYTE Mode ............................................................... 267
Figure 11-7. T1 Receiv e-Side Int erl eave Bus Oper ation—FRAME Mode ............................................................ 268
Figure 11-8. T1 Receiv e-Si de RCHCLK n Gapped Mode Dur ing F-Bit ................................................................. 268
Figure 11-9. T1 Transmit-Side D4 Timing ........................................................................................................... 269
Figure 11-10. T1 Transmit -S ide ESF Timing ...................................................................................................... 269
Figure 11-11. T1 Transmit -Side Boundary Timing (Elastic Store Disabl ed) ......................................................... 270
Figure 11-12. T1 Transmit -Side 1.544MHz B oundar y Timing ( El astic Stor e E nabled) ......................................... 270
Figure 11-13. T1 Transmit -Side 2.048MHz B oundar y Timing ( El astic Stor e E nabled) ......................................... 271
Figure 11-14. T1 Transmit -Side Interl eav e B us Oper ation—BYTE Mode ............................................................ 272
Figure 11-15. T1 Transmit -Side Interl eav e B us Oper ation—F RA M E Mode ......................................................... 273
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 6 of 305
Figure 11-16. T1 Transmit -Side TCHCLKn Gapped Mode During F-Bit .............................................................. 273
Figure 11-17. E1 Receive-Si de Timing ............................................................................................................... 274
Figure 11-18. E1 Receive-Si de B oundar y Timing (Elastic Stor e Disabl ed) .......................................................... 274
Figur e 11-19. E1 Rec eiv e-Si de 1.544MHz Boundary Timing (Elastic Store E nabled) .......................................... 275
Figure 11-20. E1 Receive-Si de 2.048MHz Boundary Timi ng ( El astic Stor e E nabled) .......................................... 275
Figure 11-21. E1 Receive-Si de Interleave B us Oper ation—BYTE Mode ............................................................. 276
Figure 11-22. E1 Receive-Si de Interleave B us Oper ation—FRA M E Mode .......................................................... 277
Figure 11-23. E1 Receive-Si de RCHCLK n Gapped Mode During Channel 1 ...................................................... 277
Figure 11-24. E1 Transmit-S ide Timing .............................................................................................................. 278
Figure 11-25. E1 Transmit-Side Boundary Timing (El astic Store Disabled) ......................................................... 278
Figure 11-26. E1 Transmit-Side 1.544MHz B oundar y Timing (Elastic Stor e E nabled) ......................................... 279
Figure 11-27. E1 Transmit-Side 2.048MHz B oundar y Timing (Elastic Stor e E nabled) ......................................... 279
Figure 11-28. E1 Transmit-S ide Interleave Bus Oper ation—BYTE Mode ............................................................ 280
Figure 11-29. E1 Transmit-Side Int erl eave Bus Operation—FRAM E Mode ......................................................... 281
Figure 11-30. E1 G.802 Timing .......................................................................................................................... 282
Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ...................................................... 282
Figure 13-1. SP I Inter face Timing Diagram......................................................................................................... 286
Figure 13-2. Int el Bus Read Timing (BTS = 0) .................................................................................................... 288
Figure 13-3. Intel Bus Write Timing (B TS = 0) .................................................................................................... 288
Figure 13-4. Motor ola B us Read Timi ng ( BTS = 1) ............................................................................................. 289
Figure 13-5 Motorola Bus Write Timing ( BTS = 1) .............................................................................................. 289
Figure 13-6. Receive Fr am er Timi ng—Bac kplane (T1 Mode) ............................................................................. 291
Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 M ode) ................................................................ 292
Figure 13-8. Transmit Formatter Timing—Backplane.......................................................................................... 294
Figure 13-9. Transmit Formatter Timing—Elastic Store Enabled......................................................................... 295
Figure 13-10. BPCLK1 Timing ........................................................................................................................... 295
Figure 13-11. JTAG Int erface Timing Di agr am ................................................................................................... 296
Figure 14-1. JTAG Functional Bl oc k Di agr am ..................................................................................................... 297
Figure 14-2. TAP Contr oller State Di agr am ........................................................................................................ 300
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 7 of 305
LIST OF TABLES
Table 4-1. T 1 -Related Teleco mmunica tions Specifications ................................................................................... 14
Table 4-2. E1-Related Telecommuni c ations Specific ations ................................................................................... 15
Table 5-1. Time Sl ot Numbering Schemes ........................................................................................................... 16
Table 8-1. Detail ed Pi n Descriptions .................................................................................................................... 20
Table 9-1. CLKO Frequency Select ion ................................................................................................................. 32
Table 9-2. Reset Functions .................................................................................................................................. 33
Table 9-3. Registers Rel ated to the El astic Stor e ................................................................................................. 36
Table 9-4. Elastic Store Delay After I nitialization .................................................................................................. 37
Table 9-5. Registers Rel ated to the IBO Multipl ex er ............................................................................................. 39
Table 9-6. RSER Output Pin Defi nitions (GTCR1.GIBO = 0) ................................................................................ 43
Table 9-7. RSIG Output Pin Defi nitions (GTCR1.GIBO = 0) .................................................................................. 43
Table 9-8. TSER Input Pin Definitions (G TCR1.GIBO = 0).................................................................................... 44
Table 9-9. TSIG Input Pin Defi nitions (GTCR1.GIBO = 0) ..................................................................................... 44
Table 9-10. RSYNC Input Pin Defini tions (G TCR1.GI BO = 0) ............................................................................... 45
Table 9-11. D4 Fram ing Mode ............................................................................................................................. 48
Table 9-12. ESF Fr ami ng M ode ........................................................................................................................... 49
Table 9-13. SLC-96 Framing ................................................................................................................................ 49
Table 9-14. E1 FA S/NFAS Fram ing ..................................................................................................................... 51
Table 9-15. Registers Rel ated to Setting Up the Framer ....................................................................................... 52
Table 9-16. Registers Rel ated to the T r ansmit Synchronizer ................................................................................ 53
Table 9-17. Registers Rel ated to Si gnaling........................................................................................................... 54
Table 9-18. Registers Rel ated to SLC-96 ............................................................................................................. 57
Table 9-19. Registers Rel ated to T1 T r ansmit BOC .............................................................................................. 59
Table 9-20. Registers Related to T1 Receive BOC ............................................................................................... 59
Table 9-21. Registers Rel ated to T1 T r ansmit FDL ............................................................................................... 60
Table 9-22. Registers Rel ated to T1 Receive FDL ................................................................................................ 60
Table 9-23. Registers Rel ated to E1 Data Link ..................................................................................................... 61
Table 9-24. Registers Rel ated to Mai ntenance and Al arms .................................................................................. 63
Table 9-25. T1 Alarm Crit eri a ............................................................................................................................... 65
Table 9-26. Registers Rel ated to Transmit RAI (Y ellow Al arm) ............................................................................. 65
Table 9-27. Registers Rel ated to Receive RAI (Yellow Alarm) .............................................................................. 66
Table 9-28. T1 Line Code Violati on Counting Options .......................................................................................... 67
Table 9-29. E1 Li ne Code Vi olation Counting Opti ons .......................................................................................... 67
Table 9-30. T1 Path Code Violati on Counting Arrangements ................................................................................ 68
Table 9-31. T1 Frames Out of Sync Counting Arrangements ................................................................................ 68
Table 9-32. Registers Rel ated to DS0 Monitoring ................................................................................................. 69
Table 9-33. Registers Rel ated to T1 I n-B and Loop Code Generator ..................................................................... 71
Table 9-34. Registers Rel ated to T1 I n-B and Loop Code Detection ...................................................................... 72
Table 9-35. Register Related to Fr am er Payload Loopbac k s ................................................................................ 73
Table 9-36. HDLC-64/HDLC-256 Contr oller Features ........................................................................................... 74
Table 9-37. Registers Rel ated to the HDLC-64 ..................................................................................................... 74
Table 9-38. Recommended Supply Decoupling .................................................................................................... 84
Table 9-39. Registers Rel ated to Control of the LI U .............................................................................................. 87
Table 9-40. Telecomm unic ations Spec ification Complianc e for DS26514 T r ansmit ters ......................................... 88
Table 9-41. Transformer S pecifications ................................................................................................................ 88
Table 9-42. T1.231, G.775, and ET S 300 233 Loss Cri teria Specifi c ations ........................................................... 94
Table 9-43. Ji tter Attenuat or Standar ds Compliance ............................................................................................. 96
Table 9-44. Register s Rel ated to Conf igure, Contr ol, and Status of BERT .......................................................... 100
Table 10-1. Register A ddr ess Ranges (i n Hex ) ................................................................................................... 102
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 8 of 305
Table 10-2. Global Regi ster List ......................................................................................................................... 103
Table 10-3. Framer Regi ster List ........................................................................................................................ 104
Table 10-4. LIU Register List .............................................................................................................................. 111
Table 10-5. BERT Register List .......................................................................................................................... 112
Table 10-6. HDLC-256 Register List ................................................................................................................... 113
Table 10-7. Global Regi ster Bi t Map ................................................................................................................... 114
Table 10-8. Framer Regi ster Bit M ap ................................................................................................................. 115
Table 10-9. Framer Register Bit M ap ................................................................................................................. 115
Table 10-10. LIU Regis ter Bit Map ..................................................................................................................... 124
Table 10-11. BERT Register Bit M ap ................................................................................................................. 125
Table 10-12. HDLC-256 Register B it Map .......................................................................................................... 126
Table 10-13. Global Regi ster S et ....................................................................................................................... 127
Table 10-14. Output Stat us Contr ol .................................................................................................................... 128
Table 10-15. Master Cl oc k Input Selection ......................................................................................................... 131
Table 10-16. Backplane Reference Clock Select ................................................................................................ 132
Table 10-17. Dev ice ID Codes in thi s Produc t F amil y ......................................................................................... 134
Table 10-18. LIU Regi ster Set ............................................................................................................................ 236
Table 10-19. Transmi t Load Impedance Selecti on .............................................................................................. 238
Table 10-20. Transmi t Pulse Shape Selection .................................................................................................... 238
Table 10-21. Receive Level Indicat ion ................................................................................................................ 243
Table 10-22. Receiv e Impedanc e S elec tion ....................................................................................................... 244
Table 10-23. Receiv er Sensitivity Sel ection with Monitor Mode Disabl ed ............................................................ 245
Table 10-24. Receiv er Sensitivity Sel ection with Monitor Mode Enabled ............................................................. 245
Table 10-25. BERT Register Set ........................................................................................................................ 246
Table 10-26. BERT Pattern S elec t ..................................................................................................................... 248
Table 10-27. BERT Error Insert ion Rate ............................................................................................................. 249
Table 10-28. BERT Repetitive Pattern Lengt h S elec t ......................................................................................... 249
Table 10-29. Extended BE RT Register S et ........................................................................................................ 253
Table 10-30. Transmi t Side HDLC-256 Register Map ......................................................................................... 257
Table 10-31. Receiv e Si de HDLC-256 Register Map .......................................................................................... 260
Table 12-1. Recommended DC Operati ng Conditions ........................................................................................ 283
Table 12-2. Capacitance .................................................................................................................................... 283
Table 12-3. Recommended DC Operati ng Conditions ........................................................................................ 283
Table 12-4. Thermal Char ac teristics ................................................................................................................... 284
Table 12-5. Transmitter Characteristi c s .............................................................................................................. 284
Table 12-6. Receiv er Characteristics .................................................................................................................. 284
Table 13-1. SPI Bus Mode Timing ...................................................................................................................... 285
Table 13-2. AC Charact eri stic s—Microprocessor Bus Timing ............................................................................. 287
Table 13-3. Receiv er AC Charac teristic s ............................................................................................................ 290
Table 13-4. Transmit A C Charact er istics ............................................................................................................ 293
Table 13-5. JTAG Interfac e Timing..................................................................................................................... 296
Table 14-1. Instruction Codes for IEEE 1149.1 Architect ur e ............................................................................... 301
Table 14-2. I D Code Str uc ture ........................................................................................................................... 302
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 9 of 305
1. DETAILED DESCRIPTION
The DS26514 is an 4-port monolithic dev ice featuring independent transceivers that c an be software configured for
T1, E 1, or J1 operation. E ac h transceiv er is com posed of a line interface unit, framer, two HDLC co ntrol lers, elasti c
store, and a T DM back plane i nt erfac e. The DS26514 i s control l ed vi a an 8-bit parall el port or t he SPI port. I nternal
im pedance mat ching and termi nation is provi ded f or both tr ansmit and receiv e paths, reduc ing ex ter nal component
count.
Each LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
im pedance depending on the type of m edia used. T1 wav ef orm generation includes DSX-1 line build-outs as well
as CSU l ine build-outs of 0dB, -7.5dB, -15dB, and -22. 5dB. E1 wav ef orm generation includes G.703 wav eshapes
for both 75Ω coax and 120Ω twisted cables. The receive interfac e pr ov ides network terminati on and r ec overs cl oc k
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applicati ons. The jitter attenuat or r em ov es phase jitter from the transmitt ed or r ec eiv ed si gnal. The cry stal -less jitt er
attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be
plac ed in either tr ansmit or receive data paths.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
insert s the CRC cod es, and prov ides the B8Z S/HDB3 (zero code suppression) a nd AMI l ine codi ng. The receiv e-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
inf ormati on, c ounts f raming/codi ng/ CRC errors, and pr ov ides cl ock, data, and f rame-sync si gnals to t he backpl ane
interfac e secti on.
There are two HDLC controllers per transceiv er. Both transmit and receive paths have access to the two HDLC
controllers. One of the HDLC controllers can be assigned to some or all timeslots of the T1/E1 frame. This
controller has a FIFO depth of 256 bytes. The second controller is smaller and can be assigned to at most one
time slot, or a portion of a time slot, or to the FDL (T1) or the S a bits (E1). This controller has a 64-byte FIFO.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for i nterfacing to asynchronou s systems, converti ng from a T1/E1 net work t o a 2.048MHz,
4.096MHz , 8.192MHz , 16. 384M Hz , or N x 64k Hz system bac k plane. The el astic stor es al so manage slip c onditions
(asynchronous interface). An interleave bus option (IBO) is provided to allow up to four transceivers (single
DS26514) to share a high-speed backplane. The DS26514 also contains an internal clock adapter useful for the
creat ion of a synchronous, hi gh-f r equenc y bac k plane timing source.
The microprocessor port provides access for configuration and status of all the DS26514’s features. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code
generation and detec tion.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 10 of 305
2. FEATURE HIGHLIGHTS
2.1 General
17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch)
3.3V suppl y with 5V toler ant i nputs and outputs
IEE E 1149.1 JTAG boundar y scan
Development support includes evaluat ion kit, driv er source code, and r eference designs
2.2 Line Interface
Requir es a single m aster cl oc k (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,
2.048MHz , 3.088MHz, 4.096MHz, 6.176MHz , 8. 192M Hz, 12.352MHz, or 16. 384M Hz.
Fully sof tware configurable
Short- and long-haul applications
Ranges i nc lude 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to
30dB, 0dB to 20dB, and 0dB to -12dB for T1
Receiver signal le vel ind ication fro m -2. 5dB to -36dB in T1 mode and -2.5dB t o -44dB in E 1 mode i n 2.5dB
increments
Software-selectable r ec eive terminati on for 75Ω, 100Ω, 110Ω, and 120Ω lines
Hitless protection switc hing
Monitor applicati on gain settings of 14dB, 20dB, 26dB, and 32dB
G. 703 r ec eiv e synchr onization si gnal m ode
Flexi ble transm it waveform generation
T1 DSX-1 li ne build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB , and -22.5dB
E1 waveforms i ncl ude G. 703 waveshapes for both 75Ω coax and 120Ω twisted cables
Anal og loss-of-signal detection
AIS gener ation independent of loopbacks
Al ternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmit outputs and receive inputs present a hi gh im pedance to t he line when no power is appl ied,
support ing redundancy applications
Transmitter short-circuit limit er with curr ent-limit-exceeded indicati on
Transmit open-circuit-detected indication
2.3 Clock Synthesizers
Backplane clocks output fr equenc ies include 2. 048M Hz, 4.096MHz, 8.192M Hz , and 16. 384MHz
− Derived fro m user-selec ted recovered receiv e clock or REFCLKIO
CLKO output clock selectabl e from a wide range of f r equenci es referenc ed to MCLK
2.4 Jitter Attenuator
32-bit or 128-bit crystal-less jit ter attenuat or
Requir es onl y a 1.544MHz or 2.048MHz master clock or multiple thereof , f or both E1 and T1 operati on
Can be plac ed in either the receive or transmit path or disabled
Limit trip indica tion
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 11 of 305
2.5 Framer/Formatter
Fully i ndependent transmit and receive functionality
Full receiv e and transmit path transparency
T1 f r ami ng form ats D4 and ESF per T1. 403 and ex panded SLC-96 support (TR-TSY-008)
E1 FA S fr ami ng and CRC-4 multiframe per G.704/G.706, and G.732 CA S m ultif r am e
Transmit-side synchronizer
Transmit midpat h CRC recalculate (E1)
Detailed alarm and status reporting with optional inter r upt support
Large path and line error c ounters
− T1: BPV, CV, CRC-6, and frami ng bit errors
− E1: BPV, CV, CRC-4, E -bit, and fram e alignment errors
− Timed or manual update modes
DS1 Idle Code Gener ation on a per-channel basis in both t r ansmit and receiv e paths
− User def ined
− Digital Milli watt
ANSI T1.403-1999 support
G. 965 V 5.2 link detec t
Abil ity to m onitor one DS0 channel in both the transmi t and receive pat hs
In-band repeati ng pattern generators and detec tors
− Three independent gener ators and detector s
− Patterns from 1 to 8 bits or 16 bits in length
Bi t oriented code (BOC) support
Flexi ble si gnaling support
− Software or har dware ba sed
− Int er r upt generated on c hange of signaling data
− Opti onal receive si gnaling freeze on loss of fram e, loss of signal, or fr am e sli p
− Hardware pins prov ided to indicate l oss of fram e ( LOF ), loss of si gnal ( LOS) , loss of transmit clock
(LOTC), or signaling fr eez e c ondition
Autom atic RAI generation to ET S 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to S a and Si bits
Opti on to extend c ar ri er loss cri teria to a 1ms period as per ETS 300 233
Japane se J1 support
Abil ity to c alc ulate and check CRC-6 according to the Japanese stand ar d
Abil ity to gener ate Yellow Alarm ac c or ding to the J apanese standard
T1-to-E1 conversion
2.6 System Interface
Independent two-frame rec eiv e and transmit elasti c stores
Independent c ontrol and cl oc ki ng
Controlled sli p capabi lity with status
Mi nim um delay m ode supported
Flexibl e TDM backplane supports bu s rat es from 1.544MHz to 16.384MHz
Support s T1 to CEPT (E1) c onv er si on
Program mable output cloc k s for frac tional T1, E1, H0, and H12 applications
Int er leaving PCM bus operat ion
Hardware signaling c apability
Receive si gnaling reinsertion to a backpl ane m ultif r am e sync
Availability of si gnaling i n a separate PCM data stream
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 12 of 305
Signaling freezing
Abil ity to pass the T1 F-bi t position through t he elastic stor es i n the 2.048MHz bac k plane mode
User-sel ec table synthesi z ed c lock output
2.7 HDLC Controllers
Two HDLC controller engi nes for eac h T1/ E 1 port
HDLC-64: I ndependent 64-byte Rx and Tx buffers with int er r upt support
HDLC-256: I ndependent 256-byte Rx and Tx buffers with inter r upt support
HDLC-64: Ac c ess FDL, S a, or single DS0 channel
HDLC-256: Ac c ess up to the f ull T1/E1 frame
Com patible with polled or i nterr upt driven environment s
2.8 Test and Diagnostics
IEE E 1149.1 support
Per-channel programm able on-chip bit error-r ate testing (BE RT)
Pseudorandom patterns inc ludi ng QRSS
User-def ined repetitive patterns
Daly patt er n
Error insert ion singl e and c ontinuous
Total-bit and errored-bit counts
Payload error insertion
Error insert ion i n the payload porti on of t he T1 f r am e i n the t r ansmit path
Error s can be insert ed over the enti r e frame or select ed channel s
Insertion options include conti nuous and absolut e num ber with select able insert ion rates
F-bit corrupt ion for line testing
Loopbacks (remote, loc al, analog, and per-channel loopback)
2.9 Microcontroller Parallel Port
8-bit par allel control port
Int el or M otorola nonmul tipl ex ed support
Flexi ble status registers support polled, interrupt, or hybrid program env ir onm ents
Software reset suppor ted
Hardware reset pin
Software acces s to dev ice ID and silicon r ev ision
2.10 Slave Serial Peripheral Interface (SPI) Features
Software acces s to dev ice ID and silicon r ev ision
Three-wir e synchr onous seri al data link operati ng in full-duplex slave mode up to 5Mbps
Glueless connection and fully com pliant to Motorola popul ar c ommuni c ation processors such as MPC8260
and mi c r oc ontrollers such as M68HC11
Software provision ability for active phase of t he serial cl oc k (i. e., ri si ng edge vs. fal ling edge), bit orderi ng
of t he serial data (most si gnificant fi r st v s. least si gnificant bit first)
Flexi ble status registers support polled, int er r upt, or hybrid program env ir onm ents
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 13 of 305
3. APPLICATIONS
The DS26514 is useful in applic ations such as:
Routers
Channel S ervice Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel B ank s
T1/E1 Test Equipment
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 14 of 305
4. SPECIFIC ATIONS COMPLIANCE
The DS26514 meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1
specifications and Table 4-2 provides the E1 specifications and relevant sections that are applicable to the
DS26514.
Table 4-1. T1-Related Telec omm u n ications Specific ati ons
ANSI T1. 102: Di gital Hier ar c hy El ectr ic al Interf ace
AMI Coding
B8ZS S ubstitution Defi nition
DS1 Electrical I nterf ac e. Line rate ±32ppm; Pulse Am plitude between 2.4V to 3.6V peak ; power level bet ween
12.6dBm to 17.9dBm. The T1 pul se mask i s provided that we compl y . DSX-1 for cross connects the r eturn l oss is
greater than -26dB. The DSX-1 cabl e is restric ted up to 655 feet.
This specificati on also prov ides cable characteri stics of DSX-Cross Connect c able—22 AVG cables of 1000 f eet.
ANSI T1. 231: Di gital Hier ar c hy—Lay er 1 in Serv ic e P erformance Monitori ng
BPV E rror Definition; Excessive Zero Definit ion; LOS descri ption; AI S definition.
ANSI T1. 403: Network and Customer Installation Interfac e—DS 1 El ec tri c al Interface
Description of t he Measurem ent of the T1 Charac teristics—100Ω. Pulse shape and tem plate compl iance
according to T1. 102; power level 12.4dBm t o 19.7dBm whe n all ones are transm itted.
LBO for the Customer Interf ac e (CI) i s specified as 0dB, -7.5dB, and -15dB . Line rate is ±32ppm . Pulse Amplitude
is 2.4V to 3.6V .
AIS gener ation as unfr am ed all ones i s defined.
The t otal c able att enuation is defined as 22dB. The DS26514 functions with up to -36dB cable loss.
Note t hat the pulse templat e defined by T1.403 and T1.102 are diff erent, specifically at Times 0.61, -0.27, -34, and
0.77. The DS26514 is com pliant to both templates.
Pub 62411
This specificati on has tighter j itter tolerance and transf er charac teri stics than ot her specifications.
The jit ter transf er charac teri stics are tighter t han G.736 and jitter toleranc e is tighter the G.823.
(ANSI) “Digita l Hierarchy—El ectri c al Interfaces”
(ANSI) “Digita l Hierarchy—Formats Specification”
(ANSI) “Digita l Hierarchy—Layer 1 In-Serv ice Digital Transmission P erformance M onitoring”
(ANSI) “Network and Custom er Installation Int erfaces—DS1 Electrical Interface”
(AT& T) “Requirements for Interfacing D igital Termina l Equip ment to Services Em ploy ing the Extended Super
Frame Format”
(AT &T) “ High Capac ity Digital S ervice Channel Interf ace Specific ation”
(TTC) “Fram e Str uc tures on Primary and Secondary Hier ar c hical Di gital Int erfaces”
(TTC) “ISDN Primary Rate User-Net work I nterface Layer 1 Spec ification”
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 15 of 305
Table 4-2. E1-Relat ed Telec omm u n ications Specific ati ons
ITU-T G.703 P hy si c al/Electr ic al Char ac teri stic s of G. 703 Hier ar c hic al Digi tal Int erfaces
Defines the 2048kbps bit r ate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to-
peak space v oltage is ±0. 237V ; nominal pulse width is 244ns.
Return loss 51Hz t o 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz i s 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse templ ate for E1 is defined in G.703.
ITU-T G.736 Char ac teristics of S y nc hr onous Di gital Multiplex Equipm ent Oper ating at 2048kbps
The peak-to-peak jit ter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitt er transfer bet ween 2.048 synchronization signal and 2.048 transmission si gnal i s provided.
ITU-T G.742 Second-Order Digital Multiplex Equi pm ent O per ating at 8448kbps
The DS26514 jitter att enuator is complaint with jitt er transfer c urve for si nusoi dal jitter input.
ITU-T G.772
This specificati on pr ov ides the method for using r ec eiv er for tr ansceiver 0 as a m onitor f or the rem aini ng seven
transmitt er/r ec eiver combi nations.
ITU-T G.77 5
An LOS detec tion crit eri on is defined.
ITU-T G.823 The cont r ol of jitter and wander within digital networks that are based on 2.048kbps hierar c hy .
G. 823 P r ov ides the jitter amplitude tolerance at different frequencies, specif ically 20Hz , 2. 4k Hz, 18k Hz , and 100kHz .
ETS 300 233
This specificati on pr ov ides LOS and AIS signal c ri teria for E1 m ode.
Pub 62411
This specificati on has tighter j itter toleranc e and transfer charac teristic s than other specifications.
The jit ter transf er charac teri stics are tighter t han G.736 and jitter toleranc e is tighter than G.823.
(ITU-T) “Synchr onous Fr ame Structures used at 1544, 6312, 2048, 8488, and 44736k bps Hi er ar c hical Level s”
(ITU-T) “Fram e Ali gnm ent and Cycl ic Redundancy Check (CRC) Procedur es Rel ating to Basi c Fram e Str uctures
Defined i n Rec ommendation G.704”
(ITU-T) “Char acter istics of P rimary PCM Multiplex Equipment Operati ng at 2048kbps”
(ITU-T) Charac teristics of a Synchronous Digital M ultiplex Equi pm ent O per ating at 2048kbps”
(ITU-T) “Loss Of Si gnal ( LOS) and Al arm I ndic ation Signal ( AIS ) Defect Detection and Clearance Cri teria”
(ITU-T) “The Cont r ol of Jitt er and Wander Wit hin Digital Networks Whic h ar e B ased on the 2048k bps Hi er ar c hy”
(ITU-T) “Primar y Rate User-Network Interface—Layer 1 Specif ic ation”
(ITU-T) “Error P erformance Measuring E quipm ent Operating at the Primary Rat e and Above”
(ITU-T) “In-Servic e Code Vi olation Monitor s for Digital Systems”
(ET S ) “I ntegrated Servic es Di gital Network (ISDN); Prim ar y Rate User-Network I nterface (UNI) ; Par t 1/ Lay er 1
Specification”
(ET S ) “T r ansmission and M ultiplexi ng; Physic al/Electrical Char ac teristi c s of Hier ar c hic al Digital Interfac es for
Equi pm ent Using the 2048kbps-Based Pl esi oc hr onous or S y nc hr onous Di gital Hierar c hies”
(ET S ) “I ntegrated Servic es Di gital Network (ISDN); Access Di gital Section for ISDN Primary Rate”
(ET S ) “I ntegrated Servic es Di gital Network (ISDN); Attachment Requirements f or Terminal E quipm ent to Connec t to
an ISDN Usi ng ISDN P rimary Rate Access”
(ET S ) “Busi ness Tel ec om m unicati ons (BT); Open Network Pr ov ision ( ONP) Technical Requi r em ents; 2048kbps
Digital Unstruct ur ed Leased Li nes (D2048U) Attachment Requir em ents f or Terminal E quipm ent Interface”
(ET S ) “Busi ness Tel ec om m unicati ons (BTC); 2048k bps Di gital Str uc tured Leased Lines (D2048S); Attachment
Requir ement s for Terminal E quipm ent I nterface”
(ITU-T) “Synchr onous Fr ame Structures Used at 1544, 6312, 2048, 8488, and 44736k bps Hi er ar c hical Level s”
(ITU-T) “Fram e Ali gnm ent and Cycl ic Redundancy Check (CRC) Procedur es Rel ating to Basi c Fram e Str uctures
Defined i n Rec ommendation G.704”
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 16 of 305
5. ACRONYMS AND GLOSSARY
This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1
frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is
transmitt ed first. Bit 8, the LS B, is tr ansmitted last.
Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz c lock can be locked to a 2.048MHz cl oc k if they share the same 8kHz component).
Table 5-1. Time Slot Numbering Schemes
TS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Phone
Channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 17 of 305
6. MAJOR OPERATING MODES
The DS26514 has t wo maj or modes of operation: T1 m ode and E1 mode. The m ode of operation f or each LIU is
configured in the LTRCR register. The mode of operation for each framer is configured in the TMMR register. J1
operation i s a special c ase of T1 operating mode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 18 of 305
7. BLOCK DIAGRAMS
Figure 7-1. Block Diagram
x4
DS26514
FRAMER #4
FRAMER #3
FRAMER #2
T1/E1 FRAMER
HDLC
BERT
MICRO PROCESSOR
INTERFACE JTAG PORT CLOCK
GENERATION
LIU #4
LIU #3
LIU #2
LINE
INTERFACE
UNIT
INTERFACE #4
INTERFACE #3
INTERFACE #2
BACKPLANE
INTERFACE
ELASTIC
STORES
RTIP
TRING
RRING
TTIP
CONTROLLER
PORT TEST
PORT CLOCK
ADAPTER
RECEIVE
BACKPLANE
SIGNALS
TRANSMIT
BACKPLANE
SIGNALS
HARDWARE
ALARM
INDICATORS
x4
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 19 of 305
Figure 7-2. Detailed Block Diagram
CLOCK
SYNTHESIZER
MICROPROCESSOR
INTERFACE
JTAG
PORT
RESET
BLOCK
A[12:0]
D[7:0]
CSB
RDB/DSB
WRB/RWB
BTS
INTB
JTDI
JTMS
JTCLK
JTDO
JTRST
RESETB
MCLK
RCHBLK/CLKn
TCHBLK/CLKn
TCLKn
TSERn
TSYNCn/
TSSYNCIOn
TSYSCLKn
RSYSCLKn
RSYNCn
RSERn
RCLKn
BPCLK1
REFCLKIO
TTIPn
TRINGn
RRINGn
RTIPn
Serial Interface Mode:
SPI (SCLK, CPOL, CPHA,
SWAP, MOSI, and MISO)
RSIGn
RM/RFSYNCn
TSIGn
PLL
PRE-SCALER
PLL
SPI_SEL
CLKO
TRANSMIT
LIU
Waveform
Shaper/Line
Driver
RECEIVE
LIU
Clock/Data
Recovery
JITTER ATTENUATOR
TRANSMIT
ENABLE
Tx
BERT
Rx
BERT
Tx
HDLC
Rx
HDLC
Tx FRAMER:
System
IF
B8ZS/
HDB3
Encode
Elastic
Store
Rx FRAMER:
System
IF
B8ZS/
HDB3
Decode
Elastic
Store
ALB
LLB
FLB
RLB
PLB
DS26514
TRANSCEIVER 1 OF 4
BACKPLANE INTERFACE
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 20 of 305
8. PIN DESCRIPTIONS
8.1 Pin Functional Description
Table 8-1. Detailed Pin Descriptions
NAME PIN TYPE FUNCTION
ANALOG T RANSMIT
TTIP1 A1, A2
Analog
Output,
High
Impedance
Transmit Bipolar Tip for Transceiver 1 to 4. These pins are differen tial line
driver tip outputs. These pins can be high impedance if:
If TXENABLE is low, TTIPn/TRINGn will be high impedance. Note that if
TXENABLE is low, the register settings for control of TTIPn/TRINGn are ignored
and output is high impedance.
The d ifferen tial outputs of TTIPn and TRINGn can provide internal matc hed
impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω. The user can turn off
intern al ter mina t ion.
Note: The two pins shown for each tr ansmit bipolar tip (e.g., pins A1 and A2 for
TTIP1) should be tied toge the r.
TTIP2 H1, H2
TTIP3 J1 J2
TTIP4 T1, T2
TRING1 A3, B3
Analog
Output,
High
Impedance
Transmit Bipolar Ring for Transceiver 1 to 4. Th ese p ins ar e differ entia l line
driver ring outputs. These pins can be high impedance if:
If TXENABLE is low, TTIPn/TRINGn will be high impedance. Note that if
TXENABLE is low, the register settings for control of TTIPn/TRINGn are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 7 5Ω, E1 120Ω, T1 100Ω, or J1 110Ω. The user can turn off
intern al ter mina t ion.
Note:
The two pins shown for each transmit bipolar ring (e.g., pins A3 and B3 for
TRI NG1 ) sh oul d be tied toget her.
TRING2 G3, H3
TRING3 J3, K 3
TRING4 R3, T3
TXENABLE/
SCAN_EN L13 Input
Transmit Enable. If this pin is pulled low, all trans mitter outp uts (TTIPn and
TRI NGn ) ar e high imp edanc e. Th e reg ister s et tings f or three-state co ntrol of
TTIPn /TRI NGn are i gn ored if TXENABLE i s lo w. If TXENABLE i s high, the
particular dr iver can be three-stated by the r egister set ti ngs .
Scan Enable. When low, device is in normal operation. Scan enable is selected
by the SCANMODE pin. Note: User should not select scan enable—test mode
only.
ANALOG RE CEIVE
RTIP1 C1 Analog
Input
Recei ve Bipo lar Ti p for Transc eiv er 1 to 4. The differential inputs of RTIPn
and RRINGn can provide internal matched impedance for E1 75Ω, E1 120 Ω, T1
100Ω, or J1 110Ω. The user can t urn o ff int ern al t er min ation via the LI U Receive
Impedance and Sensiti vity Monitor register (LRISMR).
RTIP2 F1
RTIP3 L1
RTIP4 P1
RRING1 C2 Analog
Input
Receive Bipolar Ring for Transceiver 1 to 4. The different ial i nputs of R TIP n
and RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T 1
100Ω, or J1 110Ω. The user has the option of turning off internal termination via
the LIU Receive Im pedance and Sensitivity Monitor register (LRISMR).
RRING2 F2
RRING3 L2
RRING4 P2
RESREF J5 Input
Resistor Reference. This pin i s us ed to cal ibr ate th e int ern al imp edanc e matc h
r esis t ors of t he receive LIU s. This pin sh oul d be tied to VSS through a 10kΩ ±1%
resistor.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 21 of 305
NAME PIN TYPE FUNCTION
TRANSM IT FRAMER
TSER1 F6
Input
Tra nsm i t N RZ Se r ial Data 1 t o 4 . These p in s are s ampl ed on the falling edge of
TCLKn when the transmit-s i de elastic sto re i s disabled. These pins are sampled
on the falling edge of TSYSCLKn when the transmit-sid e ela s ti c stor e is enabled.
In I BO mode, data f or mult iple f ramers can be used i n high -speed multiplexed
s cheme. T his i s d escri bed i n Sectio n 9.8.2. The table t her e presents t he
c ombi natio n o f fr amer data for each o f t he str eams.
TSYSC LKn is used as a refere nce when IBO is invoked. Se e Table 9-8.
TSER2 E7
TSER3 R4
TSER4
N7
TCLK1
C5
Input
Transmit Clock 1 to 4. A 1.544MHz or a 2.048MHz primary clock. Used to clock
data through the transmit side of the transceiver. TSERn data is sampled on the
fal li ng ed ge of T CLKn. T C LKn is us ed to sample T SER n when th e elastic s tore is
not enabled or IBO is not used. W hen the elasti c stor e is enabl ed, TCLKn is
used as the i nternal tr ansmit cl oc k for the fr am er side or the elastic store
including the trans mit framer and LIU. W ith the elastic store enabled,
TCLKn c an be either synchronous or asynchronous to TSYSCLK n whic h
either prevents or allows for slips. W hen IBO mode i s enabled, TCLKn
m ust be synchr onous to TSYSCLK n whi c h pr event s slips i n the el astic
store.
Note: Thi s clock m ust be pr ov ided for proper dev ice operation. The onl y
ex c eption i s when the TCR3 register is configured to source TCLK
internally fro m RCLK.
TCLK2 D7
TCLK3 P5
TCLK4 L8
TSYSCLK1 P13 Input
Tra nsm i t S ystem Clock 1. 1.544MHz, 2.048MHz, 4 .096MH z , 8.192MHz , or
16.384MHz clock. Only used when the transmit-sid e elast ic s t or e funct ion is
enabled. Should be tied low in applications that do not use the transmit-side
elastic store. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO
mode is used. TSYSCLK1 does not have an int ernal pulldown resistor. Note: If
the GTCR1.528MD bit is set, TSYSCLK1 becomes the master TSYSCLK for all
framers.
TSYSCLK2/
AL/RSIGF/FLOS2 F3
Input with
internal
pulldown/
Output
Tra nsm it S ystem Clock 2 t o 4. 1.544MHz , 2.048M H z , 4.096M H z , 8.192M H z , or
16.384MHz clock. Only used when the transmit-sid e elast ic s t or e funct ion is
enabled. Should be tied low in applications that do not use the transmit-side
elastic store. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO
mode is used. TSYSCLK1 does not have an int ernal pulldown resistor. Note: If
the GTCR1.528MD bit is set, TSYSCLK1 becomes the master TSYSCLK for all
framers.
Analog Loss/Receive-Signaling Freeze/Fra mer LOS. Analog LOS reflects the
LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS
detecti on by the corr esp onding framer; t he same pin s can ref l ect r eceive-
signaling freeze indications. This selection can be made by settings in the Global
Transc eiver Clock Cont rol R egist er 1 (GTCCR1).
AL/RSIGF /FL OS[8:2 ] is availab le only by setting the GTCR1.528M D bi t t o 1.
TSYSCLK3/
AL/RSIGF/FLOS3 L3
TSYSCLK4/
AL/RSIGF/FLOS4 P3
TSYNC1/
TSSYNCIO1 B4
Input/
Output
Transmit Synchronization 1 to 4. A p ulse at t hes e pins establi sh es eit her f rame
or multifr am e boundaries for the tr ansmit side. These signals can also be
programmed to output either a frame or mul t i frame pulse. If these p in s are set t o
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signali ng fr am es in T1 mode. The operati on of these signals is
synchronous with TCLK[8:1].
Transmit System Synchronization In. T hes e pins are sel ected when the
transmit-sid e elastic s tore is en abled. A pulse at th ese p ins establis hes eith er
fram e or multiframe boundaries for the transmit side. Should be ti ed low in
applications that do not use the transmit-side elast ic s to re. T he operation of this
signal is synchronous wit h TSYSCLK[8:1].
Transmit System Synchronization Out. If configured as an output and the
transmit elastic store is enabl ed, an 8kHz pulse synchronous to the BPCLK1 will
be generated. This pulse in comb inatio n with BPCLK1 can be used as an IBO
m aster . TS SYN CIOn can b e used a s a source t o RSY NCn and TSSY NCI On of
another DS26514 or RSYNC and TSSYNC of other Dallas Semiconductor parts.
Note: TSSYNCIO[8:1] are not used when GTCR1.528MD is set. When
GTCR1.528MD is set, the TSSYNCIO pin (N13) is used.
TSYNC2/
TSSYNCIO2
F7
TSYNC3/
TSSYNCIO3 M6
TSYNC4/
TSSYNCIO4
M7
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 22 of 305
NAME PIN TYPE FUNCTION
TSSYNCIO N13 Input/
Output
Note: In default operation, this pin is not used. W h en GTCR1.528MD is set,
thi s pin is acti ve. If pin is n ot u s ed, tie low throug h a re sist or.
Transmit System Synchronization In. T his pin is selected when the transmit -
s ide el astic st ore is enabled. A pulse at t his pin establis hes ei ther f rame or
m ult if rame boundari es for t he tra nsmi t sid e. Note tha t if the elastic s tore is
enabled, frame or multifram e boundary will be established for all transmitters.
Should be tied low in applications that do not use the transmit-s i de elastic stor e.
The operation of this signal is synchronous with TSYSCLKn.
Transmit System Synchronization Out. If configured as an output and the
transmit-side elastic store is enabled, an 8kHz pulse synchronous to BPCLK1 will
be generated. This pulse in comb ination with BPCLK1 can be used as an IBO
master. TSSYNCIO can be used as a source to RSYNCn and TSSYNCIO of
another DS26514 or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG1
D5
Input
Transmit Signaling 1 to 4. When enabled, thi s input samples signa ling bits for
insertio n i nto outg oing PC M data st ream. Sampled on t he falli ng edg e of TCLK n
when the transmit-si de elastic store is disabled. Sampled on the falling edge of
TSYSCLKn when the transmit-si de el as t ic stor e is enabled. In I BO mod e, the
TSIG n streams ca n run up t o 16.384M H z . S ee
Table 9-9
.
TSIG2
A6
TSIG3
T4
TSIG4 R6
TCHBLK1/
TCHCLK1
A5
Output
Transmit Channel Block/Transmit Channel Bloc k Clock. A dual function pin.
TCHBLK[1:4]. TCHBLKn is a user-progr am ma ble output that ca n be f orced high
or low during any of the channels. It is synchronous wit h TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-s ide elastic store is enab le d. It is useful for blocking clocks to a serial
UART or LAPD controller in applications where not all channels are used such as
Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PR I. Also usef ul
for locating individual channe ls in drop-and-insert applications, for external per-
channel loopback , and for per-channel conditioning.
TCHCLK[1:4]. TCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It can also be programm ed to output a gated
tr ansm it bit clock contr ol led by TCHBLKn. It is synchronous wit h TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-side elast ic stor e is enabled. Useful for pa rallel-to-ser ial co nversion
of channel data.
TCHBLK2/
TCHCLK2
C7
TCHBLK3/
TCHCLK3
L7
TCHBLK4/
TCHCLK4 P7
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 23 of 305
NAME PIN TYPE FUNCTION
RECEIVE FRAMER
RSER1 E5
Output
Received Serial Data 1 to 4. Received NRZ seri al data. Updated on rising edges
of R CLKn wh en the r eceive-sid e ela s tic store i s disa bled. U pda ted on the r i sin g
edges of RSYSCLKn when the recei ve-side elastic store is enabled.
Wh en IBO m od e is used, t he RS ERn pins c an output dat a for multi ple fr amers.
The RSERn data is synchronous to RSYSCLKn. See Section 9.8.2 and Table
9-6
RSER2
D6
RSER3
N4
RSER4 N6
RCLK1 F4
Output
Receive Clock 1 to 4. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to
c lock data t hro ugh t he r eceiv e-side framer. This clock is recovered from the
signal at RTIPn and RRINGn. RSERn data is output on the rising edge of RCLKn.
RCLKn is used to output RSERn when the elastic store is not enabled or IBO is
not used. W hen the elasti c stor e is enabled or IBO is used, the RSERn is clocked
by RSYSCLKn.
RCLK2 G4
RCLK3 L4
RCLK4
M4
RSYSCLK1 L12 Input
Receive System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8. 192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
stor e function i s enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO mode
is used. Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all fr a mer s.
RSYSCLK2/
RLF/LTC2
E3
Input with
internal
pulldown/
Output
Receive System Clock 2 to 4. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
stor e function i s enabled. Should be tied low in applications that do not use the
receive-side elas tic store. Multiple of 2.048MHz is expected when the IBO Mode
is used.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searchi ng for the
fr ame and multif rame or t o t oggle high if the TCLKn pin has not been toggled for
approxima te ly three clock periods.
RLF/LTC[4: 2] are available when GTCR1.528MD = 1.
Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the mas ter
RSYSCLK for all fr a mer s.
RSYSCLK3/
RLF/LTC3 M3
RSYSCLK4/
RLF/LTC4
N3
RSYNC1
A4
Input/
Output
Receive Synchronization 1 to 4. If the receive-s ide elastic sto re i s enabled, t his
signal is used to input a frame or multifram e boundary pulse . If set to output
fram e boundaries, RSYNCn can be programmed to output double-wid e pulses on
s ignal ing frames in T 1 m od e. In E1 m ode, RS YNC n out ca n be used to i ndicate
CAS and CRC-4 multiframe. The DS26514 can accept an H.100-compatible
synchronizati on signal. The default directi on of this pin at power-up is in put , as
dete rmined by the RSIO contro l bit in the RIOCR. 2 reg ister.
RSYNC2
B6
RSYNC3
N5
RSYNC4 T6
RMSYNC1/
RFSYNC1
C4
Output
Receive Multiframe/Frame Synchronizati on 1 to 4. A dual function pin to
indicate f r ame or m ult if rame s ync hro nizati on. R FSY NCn is a n extracted 8k H z
pulse, one RCLKn wide that identifies frame boundaries. RMSYNCn is an
extracted pulse, one RCLKn wide (elastic store disabled) or one RSYSCLKn wi de
(elastic store enabled), that identifies multiframe boundaries. When the receive
elastic s tore is en abled, the RMS Y NCn s i gn al i ndicates t he multi frame sync on
the sy stem (backp l an e) sid e of the elastic sto re. In E 1 m ode, t his pi n ca n i ndicate
eit her th e C RC-4 or CAS mult if rame as det erm ined by t he RSM S 2 c ont rol bit in
the Rec eive I / O C onfig uratio n reg ister (RIOCR.1).
RMSYNC2/
RFSYNC2 C6
RMSYNC3/
RFSYNC3 P4
RMSYNC4/
RFSYNC4 P6
RSIG1 D4
Output
Receive Signalin g 1 to 4. Outputs signaling bits in a PCM format. Updated on
ri sing edges of RCLKn when the receiv e-side elas tic store is disabled. Updated
on the rising edges of RSYSCLKn when the receive-s ide elasti c stor e is enabled.
See Table 9-7.
RSIG2 E6
RSIG3 M5
RSIG4 R5
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 24 of 305
NAME PIN TYPE FUNCTION
RCHBLK1/
RCHCLK1
E4
Output
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK.
RCHBLK[1:4]. RCHBLKn is a user-pro gramm able output that can be forced high
or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLKn
when the r eceive-side elastic st ore is dis abled. It is s ync hr onou s wi th R SYS C LKn
when the r eceive-side elastic store is enabled. This pin is useful for blocking
c locks to a s erial UART or LAPD c ontro ll er i n appli ca t ions w here n ot al l channels
are used such as fr actional service, 384kbps service, 768kbps, or ISDN-PR I . Also
useful for locating individual channels in drop-and-insert applications, for external
per-channel loopback, and for per-channel conditioning.
RCHCLK[1:4]. RCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It is synchronous with RCLKn when the receive-
s ide el astic st ore is dis abled. It is s yn chronous with RSYSCLKn when the
receive-side elastic store is e nabled. It is useful for parallel-to-serial conversion of
channel data.
RCHBLK2/
RCHCLK2 B5
RCHBLK3/
RCHCLK3
L6
RCHBLK4/
RCHCLK4 T5
BPCLK1 E8 Output
Backplane Clock 1. Programmable clock output that can be set t o 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this cl ock can be
RCLK[8:1], a 1.544MHz or 2.048MHz clock frequency derived from MCLK, or an
ex ternal reference c lock (R EFC LKIO). This all ows sy stem cloc ks t o be referenced
fr om external sources, the T1J1E1 r eco ver ed c locks , or th e MC LK oscil lator.
CLKO/
RLF/LTC1 D3 Output
Clock Out. Clo ck o utput pin t hat ca n be pr ogram med to output numerous
frequenci es referenced to MCLK. Frequencies available: 1.544MHz, 2. 048MHz,
4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz.
GTCCR3. CL KO SEL[2:0] selects the f requenc y.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer i s sea rc hing for the
fram e and multiframe, or to toggle high if the TCLKn pin has not been toggled for
approxima te ly three clock periods.
RLF/LTC1 is available on the DS26514 when GTCR1.528MD = 1.
MICROPROCESSOR INTERFACE
A12 C8
Input Addr ess [1 2:0]. This bus selects a specific register in the DS26514 during
read/write access. A12 is the MSB and A0 is the LSB.
A11 A8
A10 B8
A9
F8
A8
B9
A7
A9
A6
C9
A5
D9
A4
E9
A3 F9
A2 B10
A1 A10
A0 C10
D[7]/SPI_CPOL T9 Input/
Output
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus us ed to input d ata d urin g r egister w r ites
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPOL: This signal selects the clock polari ty when SPI_SEL = 1. See Secti on
9.1.2 f or d etailed timin g and functi ona l it y informatio n. Default setti ng is low.
D[6]/SPI_CPHA N9 Input/
Output
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bi t or 8-bit da ta bus us ed to input d ata d urin g r egister w r ites
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPHA: This signal selects the cl ock phase when SPI_SEL = 1. See Section
9.1.2 f or d etailed timin g and functi ona l it y informatio n. Default setti ng is low.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 25 of 305
NAME PIN TYPE FUNCTION
D[5]/SPI_SWAP M9 Input/
Output
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus us ed to input d ata d urin g r egister w r ites
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are
never cha nged in th e co ntrol word.
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received fir st.
D[4] R8 Input/
Output
Data [4]. B it 4 of the 8-bit data bus used to input data duri ng regis t er writes and
data outputs during register reads. Not driven when CSB = 1.
D[3] T8
Input/
Output
Data [3]. Bit 3 of th e 8-bit data bus used to input data duri ng regist er writes and
data outputs during register reads. Not driven when
CSB
= 1.
D[2]/SPI_SCLK P8 Input/
Output
Data [2]/SPI Serial Interface Clock
D[2]: Bit 2 of t he 8-bit data bus used to input data durin g regis ter wr it es a nd data
outputs during register reads. Not driven when CSB = 1.
SPI_SCLK: SPI Serial Cl ock Input when SPI _ SEL = 1.
D[1]/SPI_MOSI L9 Input/
Ouput
Data [1]/SPI Serial Interface Da ta Master Out-Slave In
D[1]: Bi t 1 of the 8 -bi t d ata bus used to input data during register writes, and data
outputs during register reads. Not driven when CSB = 1.
SPI_MOSI: SPI Serial Data In p ut (Master Out-Slave In) when SPI_SEL = 1.
D[0]/SPI_MISO N8 Input/
Output
Data [0]/SPI Serial Interface Da ta Master In-Slave Out
D[0]: Bit 0 of t he 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_MISO:
SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.
CSB T7 Input Chip-Sel ect Bar . Thi s act i ve-low signal i s used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualif i ed with CSB.
RDB/
DSB M8 Input
Read Ba r/ Data -Strobe Bar. This active -low signal along with CSB qualifies re ad
access to one of the DS26514 registers . The DS2 65 14 dr ives the dat a bu s w it h
the content s of th e addressed register whi le RDB and CSB are low. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be connected through a 10K
ohm resistor to the I/O Supply.
WRB/
RWB R7 Input
Write Bar/Read-Wr it e B ar. This a ct iv e-l ow signal along with CSB q ualifies wr ite
acc ess t o o ne of the DS26514 r egister s. D at a at D[7:0] i s wr itten into the
addressed register at the rising edge of WRB while CSB is low. Note: If S PI mo d e
is selected by the SPI_SEL pin, this pin must be connected through a 10K ohm
resistor to the I/O Supply.
INTB R9 Output,
Three-
Stateable
Int errupt Bar. Thi s a cti ve-low output is assert ed when an unmasked interrupt
event is detected. INTB will be deasserted (and three-stated) whe n all inte r rupts
have been acknowledged and serviced. Extensive mask bits are provided at the
global level, f ramer, LIU, and BE RT lev el.
SPI_SEL/
AL/RSIGF/FLOS1 C3
Input with
internal
pulldown/
Output
SPI Serial Bus Mode Select/Analog Loss/Receive Signaling Freeze/Framer
LOS
SPI_SEL: 0 = P arallel Bus M ode, 1 = S PI S erial Bus Mod e
AL/RSIGF/FLOS1: Analog LO S ref lects the loss of signal detect ed by the LIU
front-end; framer LOS is LOS detection by the corresponding framer. The same
pins c an r efl ect receive-signali ng free ze indicat ions. This sel ection can b e ma de
by s ett ings in Gl oba l Tra ns ceiv er C ontr ol R egist er (GTCR1) . A L / R S IGF/F LOS1
are availabl e by s et tin g the GTCR1.52 8MD bit to 1.
BTS M13 Input Bus Type Select. Set hi gh to select M otoro la bus ti min g, l ow t o selec t Intel b us
timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be tied lo w.
SYSTEM INTERFACE
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 26 of 305
NAME PIN TYPE FUNCTION
MCLK B7 Input
Master Clock. This is an independent free-running clock who se input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multi ple of 2.048MHz can be
int ernally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See Table 10-15.
RESETB J12 Input Reset Bar. Active-low r eset. T his in put for ces t he c omplete DS 26 514 res et. This
includes reset of th e r egis ters, framers, and LIUs.
REFCLKIO A7 Input/
Output
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the use rs to synchron ize the syste m
backplane with the reference clock. The other options for the backplane clock
r eferen ce a re L IU -recei ved clocks or MC LK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz
r eferen ce c lock. Thi s allo ws for m ult iple D S26514 s t o s har e t he s ame referen ce
for generation of the backplane clock. Hence, in a system consisting of multiple
DS 26 514s , one can be a mas ter and others a slav e using t he s ame r eferen ce
clock.
TEST
DIGIOEN D8 Input,
Pullup
Digital Enable. When this pi n an d JTRST are pulled low , al l di gital I/ O pins are
placed in a h igh -impedance s tate. If this pin i s high t he digi tal I / O pi ns oper ate
normally. This pin must be connected to VDD for nor mal o per ation .
JTRST L5 Input,
Pullup
JTAG Reset. JTRST is u sed to a syn chronously reset the t est access port
controller. After power-up, JTRST must be toggled from low to high. This action
s ets th e device int o the JTAG DEVIC E ID mode. Pulli ng JTRST low restores
normal device operation. JTRST i s pull ed high internally via a 10k Ω resistor
operation. If boundary scan is not used, this pin should be held low.
JTMS K4 Input,
Pullup
JTAG Mode Selec t. T his pin is s ampled on t he risin g edge of JTC LK and is used
to place the test access port into the various defined IEEE 1149 .1 s tates . This p in
has a 10kΩ pul lu p resist or.
JTCLK F5 Input JTAG Clock. This si gnal is used to shift data into JTDI on the rising edge and out
of JTDO on th e fall in g edg e.
JTDI H4 Input,
Pullup JTAG Dat a In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTDO J4
Output,
High
Impedance
JTAG Data Out. Test instructions and data are clocked out of this pin on the
falling edge of JTCLK. If not used, this pin should be left unconnected.
SCANMODE H13 Input
Scan Mode. When low, normal operational cloc ks are used to clock the flip flops.
User sh ould tie low.
POWER SUPPLIES
ATVDD
B1, B16,
G1, G16,
K1, K16,
R1, R1 6
— 3.3V
±
5% Analog Transmit Power Supply. These VDD inputs are used for the
transmit LIU sections of the DS26514.
ATVSS
B2, B15,
G2, G15,
K2, K15,
R2, R1 5
— Analog Transmit VSS. These pins are used for transmit analog VSS.
ARVDD
D1, D1 6,
E1, E16,
M1, M16,
N1, N1 6
— 3.3V
±
5% Analog Receive Power Supply. These VDD i nputs are use d for the
receive LIU sections of the DS26514.
ARVSS
D2, D1 5,
E2, E15,
M2, M15,
N2, N1 5
— Analog Receive VSS. These pins are used for analog VSS for the receivers.
ACVDD H7 — 1.8V
±
5% Analog Clock Conversion VDD. Thi s V DD inpu t is use d for the clock
conversion unit (CLAD) of the DS26514.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 27 of 305
NAME PIN TYPE FUNCTION
ACVSS J7 — Analog Clock VSS. This pin is used for clock converter analog VSS.
DVDD33
G5, G6,
G11, G1 2,
H5, H6,
H8, H9,
H10, H11
— 3.3V
±
5% Power S u ppl y f or I/Os
DVDD18 G7–G10 — 1.8V
±
5% Power Supply for Inter nal VDD
DVSS
H12, J6,
J8–J11,
K5–K12 — Digital Ground
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 28 of 305
9. FUNCTIONAL DESCRIPTION
9.1 Processor Interface
Mi croprocessor control of the DS26514 is accomplished through the 28 hardware pi ns of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 13-2 and Figure 13-3.
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 13-4 and Figure 13-5. The
address space is m apped thr ough the use of 13 address lines, A[12: 0]. Multi plexed m ode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
mi c r opr oc essor port. Wi th Intel timing select ed, the read-data bar (RDB) and write-read bar ( WRB) pins ar e used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the read-
write bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the i nterfac e.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
m askable i nterrupt condit ions. This pin is normally connected t o the mic r opr oc essor interrupt input.
9.1.1 SPI Serial Port Mode
The external processor bus can be configured to operate in SPI serial bus mode. See Section 9.1.2 for detailed
timing diagrams.
W hen SPI_SE L = 1, SP I bus m ode is im pl ement ed using f our signal s: cl ock ( SPI_SCLK), m aster out-sl ave i n data
(SPI_MOSI), master in-slave out data (SPI _MISO), and chip select (CSB). Cl ock polarity and phase can be set by
the D[ 7]/ S P I_CPOL and D[6]/SPI _CP HA pins.
The order of the address and data bits i n the serial st r eam is sel ec table usi ng the D[5]/SPI_SWAP pin. The R/W bit
is always first and B bit is always last in the initial control word and are not effected by the D[5]/SPI_SWAP pin
setting.
SPI m ode is not r ec ommended f or HDLC oper ations because of the bandwidt h constr aints of S P I.
9.1.2 SPI Functional Timing Diagra ms
Note: The transmit and rec eiv e or der of t he addr ess and dat a bits are selec ted by the D[5]/S P I_SWAP pin. The
R/W (read/ wri te) MSB bit and B (burst) LSB bit posit ion is not aff ec ted by the D[5]/SPI_SWAP pi n setting.
9.1.2.1 SPI Transmission Format and CPHA Po larity
When SPI_CPHA = 0, CSB may be deasserted between accesses. An access is defined as one or two control
bytes followed by a data byte. CSB cannot be deasserted between the control bytes, or between the last control
byte and the data byte. When SPI_CPHA = 0, CSB may also remain asserted between accesses. If it remains
asserted and the BURST bi t is set, no addi tional cont rol bytes are expected after t he first control byte(s) and data
are tr ansferred. If the BURST bit is set, the addres s will be increm ented for each additi onal byt e of data tr ansfer r ed
until CSB is deasserted. If CSB remains asserted and the BURST bit is not set, a control byte(s) is expected
foll owing the data byt e, and the addres s for the next access will be r ec eived fr om that. Anytime CSB is deas se r ted,
the BURS T acc ess is term inated.
When SPI_CPHA = 1, CSB may remain asserted for more than one access without being toggled high and then
low again between ac c esses. I f t he B URS T bi t is set, t he addr ess should i nc r em ent and no additi onal cont r ol bytes
are expected. If the BURST bit is not s et, each dat a byt e will be followed by the contr ol byte( s) for t he next ac c es s.
Additionally, CSB may also be deasserted between accesses when SPI_CPHA = 1. In the case, any BURST
access i s terminated and t he nex t byte received when CSB is reasserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI _CP HA . They indicat e the cloc k edge that samples the data and the level of the cloc k dur ing no-transfer events
(hi gh or low). Si nce the SPI port of the DS26514 acts as a slave devi ce, the master dev ice prov ides the cl ock. The
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 29 of 305
user must confi gure the SPI_CPOL and SPI _CPHA pins to de scri be which type of clock t hat the m aster devi ce is
providing.
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0
1
A7
A13
A12
A11
A10
A9
A8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
LSB
MSB
SPI_SCLK
CSB
SPI_MOSI
SPI_MISO
B
A6
A5
A4
A3
A2
A1
LSB
MSB
A0
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0
SPI_SCLK
1
A7
A13
A12
A11
A10
A9
A8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
LSB
MSB
SPI_MOSI
SPI_MISO
B
A6
A5
A4
A3
A2
A1
LSB
MSB
A0
CSB
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1
SPI_SCLK
CSB
1
A7
A13
A12
A11
A10
A9
A8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
LSB
MSB
SPI_MOSI
SPI_MISO
B
A6
A5
A4
A3
A2
A1
LSB
MSB
A0
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1
SPI_SLCK
CSB
1
A7
A13
A12
A11
A10
A9
A8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
LSB
MSB
SPI_MOSI
SPI_MISO
B
A6
A5
A4
A3
A2
A1
LSB
MSB
A0
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_C PHA = 0
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 30 of 305
0
A13
LSB
MSB
SPI_SCLK
CSB
SPI_MOSI
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
A4
A3
A2
A1
A0
LSB
MSB
A12
A11
A10
A9
A8
A7
A6
A5
B
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0
SPI_SCLK
CSB
0
A13
LSB
MSB
SPI_MOSI
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
A4
A3
A2
A1
A0
LSB
MSB
A12
A11
A10
A9
A8
A7
A6
A5
B
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1
SPI_SCLK
CSB
0
A13
LSB
MSB
SPI_MOSI
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
A4
A3
A2
A1
A0
LSB
MSB
A12
A11
A10
A9
A8
A7
A6
A5
B
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1
SPI_SCLK
CSB
0
A13
LSB
MSB
SPI_MOSI
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
A4
A3
A2
A1
A0
LSB
MSB
A12
A11
A10
A9
A8
A7
A6
A5
B
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 31 of 305
9.2 Clock Structure
The user should provide a system cl oc k to the MCLK input of 2.048MHz, 1.544M Hz, or a mul tiple of up to 8x the T1
and E1 fr equenc ies. To meet many specifi c ations, the MCLK source should have ±50ppm acc ur ac y.
9.2.1 Backplane Clock Generation
The DS26514 provides facility for provision of BPCLK1 at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 9-9). The Global Transceiver Clock Control Register 1 (GTCCR1) is used to control the backplane clock
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output
sourcing M CLK T1 or MCLKE1 as sho wn in Figure 9-9.
This backplane clock and frame pulse (TSSYNCIOn) can be used by the DS26514 and other IBO-equipped
devi c es as an “IBO Bus Master.” Henc e, the DS 26514 pr ov ides the 8kHz sync pulse and 4MHz , 8MHz, and 16MHz
cl oc k. Thi s can be used by the link lay er dev ic es and frames connected t o the IBO bus.
Figure 9-9. Backplane Clock Generation
Clock
Multiplexor
RCLK3
RCLK4
RCLK1
RCLK2
Pre
Scaler
PLL MCLKT1
MCLKE1
MCLK
BPREFSEL3:0
CLK
GEN
REFCLKIO
REFCLKIO
BPCLK
BPCLK1:0
BFREQSEL
TSSYNCIO
The reference cloc k for the back plane clock generator can be as f ollows:
• Exter nal M aster Clock. A prescaler can be used to generate T1 or E1 frequenc y .
• Exter nal Ref erence Clock REFCLK IO. This allows f or multi ple DS26514s to u se the backplane cl ock from
a common r eference.
• Inter nal LIU recover ed RCLK s 1 to 4.
• The clock generator can be used to generat e BPCLK1 of 2. 048MHz, 4. 096MHz, 8.192MHz , or 16.384MHz
for the IB O.
• If MCLK or RCLKn is used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
cl oc k for exter nal use.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 32 of 305
9.2.2 CLKO Output Clock Generation
This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the GTCCR3
register.The reference for the PLL is not the input clock on MCLK, but the scaled v ersion of MCLK (1.544MHz or
2.048MHz). The LTRCR.T1J1E1S bit also selects the proper P LL for use in generati ng the appropriate frequenc y .
This cloc k output pin is provided as an additional f eature to eliminate the need for another boar d oscillat or.
Table 9-1. CLKO Frequency Selection
CLKOSEL[3:0] CLKO (kHz)
0000
2048
0001
4096
0010
8192
0011
16384
0100
1544
0101
3088
0110
6176
0111
12352
1000
1536
1001
3072
1010
6144
1011
12288
1100
32
1101
64
1110
128
1111
256
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 33 of 305
9.3 Resets and Power-Down Modes
A hard ware reset is i ssued by forc ing t he RESETB pin to l ogi c l ow. The RESETB input pin r esets al l f ramers, LI Us,
and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be
reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing
reserved locations t o 00h.
Table 9-2. Reset Function s
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset RESETB Pin Transition to a logic 0 level r esets the DS 26514.
Hardware JTAG Reset JTRST Pin Resets the JTAG test port.
Global S oft ware Reset GSRR1 Writi ng to this register r esets the framers, LIUs and BERTs
(tr ansmit and rec eiv e).
Fram er Rec eiv e Reset RMMR.1 Writi ng to this bit resets the r ec eive framer.
Framer Transmit Reset TMMR.1 Writi ng to this bit resets the transmit fram er .
HDLC Receive Reset RHC.6 Writing to this bit resets the receive HDLC controller.
HDLC Transmit Reset THC1.5 W riting to this bit resets the t r ansmit HDLC controller.
El astic Store Receive Reset RESCR.2 Writ ing to this bit resets the rec eive elastic store.
El astic Store Transmit Reset TESCR.2 Writi ng to this bit resets the transmit elastic stor e.
Bi t Oriented Code Receiv e
Reset
T1RBOCC.7 Wr iting to this bit resets the rec eive BOC controller.
Loop Code Int egr ation Reset
T1RDNCD1,
T1RUPCD1
Writi ng to these regist er s reset s the pr ogr am mable in-band
code i ntegration per iod.
Spare Code I ntegration Reset T1RSCD1
Writi ng to this regi ster r esets the pr ogr am mable in-band
code i ntegration per iod.
The DS26514 has sev eral features i ncluded to reduce power consum ption. The indiv idual LIU transmitters can be
powered do wn by setti ng t he TPDE bit in t he LIU Mai ntenanc e Control Regi ster (LMCR). Not e that powering down
the transmit LIU results in a high-impedance state for the corresponding TTIPn and TRINGn pins and reduced
operating current. The RPDE in the LMCR register can be used to power do wn the LI U r ec eiver.
The T E (tr ansmit enable) bit i n the LMCR register c an be used to disable t he TTIP n and TRI NGn outputs and place
them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for
equipment prot ection-switching applications.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 34 of 305
9.4 Initialization and Configuration
9.4.1 Example Device Initialization and Sequence
STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software
reset bi ts outlined in S ection 9.3. Clear all r eset bits. Al low time for the reset rec ov er y.
STE P 2: Chec k the Dev ic e ID in t he IDR register.
STEP 3: Write the GTCCR1 register to correctly configure the system clocks. If supplying a 1.544MHz MCLK
foll ows this writ e with at least a 300ns delay in order to allow the cl oc k system t o properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Write value 71h to address 1307h. This increases the frequency of the internally generated clock that is
supplied to the framers.
STEP 6: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR and RMMR
registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit
signaling in E1 mode, program the E1TAF and E1TNAF registers as required. Configure the framer Transmit
Control Registers (TCR1–TCR4). Confi gure the framer Receiv e Control Registers (RCR1–RCR3). Conf igure ot her
fram er featur es as appropri ate.
STEP 7: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR register.
Confi gure t he li ne build-out f or each LIU. Conf i gure other LIU features as appropriat e. S et the TE (transmi t enable)
bit to turn on the TTIPn and TRINGn outputs.
STE P 8: Configure the elastic stor es, HDLC c ontroller , and BERT as needed.
STEP 9: Set the INIT_DONE bit in the TMMR and RMMR registers for each framer.
9.5 Global Resources
All four framers share a common microprocessor port and a common MCLK. There is a common software
configurable BPCLK1 output. A set of global registers includes global resets, global interrupt status, interrupt
m asking, clock confi guration, and the devi ce ID register. See the global register bit map in Table 10-7. A common
JTAG c ontroller is used for all por ts.
9.6 Per-Port Resources
Each port has an associ ated framer, LIU, BE RT, jitter attenuat or , and transmit/ r ec eiv e HDLC c ontroller. Each of the
per-port functions has it s own register space.
9.7 Device Interrupts
Figure 9-10 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR1, GLISR1, and GBISR1 to quickly identify which of the four transceivers is
(are) c ausi ng the interr upt(s). The host c an then r ead the speci fic transceiver ’s i nterrupt informati on r egisters (TIIR,
RIIR) and t he latched status regi ster s (LLSR, BSR)to further identif y the source of the i nterr upt(s). If TIIR or RIIR is
the source, the host reads the transmit latched status or the receive latched status registers for the source of the
int errupt. All interrupt i nf ormati on register bi ts are real-t ime bits that clear once t he appropri ate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
regi ster. A ll lat ched stat us bits m ust be cl eared by t he host wri ti ng a “1” t o the bi t loc ation of the i nterrupt condition
that has been serviced. Latched status bits that have been masked via the interrupt mask registers are masked
from the int errupt i nform ation r egister s. The int errupt mask register bi t s prev ent indivi dual latc hed status condi ti ons
from generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when
servi cing i nt errupt s, the user should XOR the l atc hed s tat us with t he associat ed i nterr upt m ask i n order t o ex clude
bits for which the user wished to prevent interrupt service. This architecture allows the application host to
peri odically poll the l atched status bits f or noni nterrupt conditions, while usi ng only one set of registers.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 35 of 305
Figure 9-10. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear
7
RLS1
RIM1
Receive Alarm Condition Clear
6
Receive Loss of Signal Clear
5
Receive Loss of Frame Clear 4
Receive Remote Alarm Indication
3
Receive Alarm Condition
2
Receive Loss of Signal
1
Receive Loss of Frame
0
Receive Signal All Ones
3
RLS
2
RIM2
Receive Signal All Zeros
2
Receive CRC4 Multiframe
1
Receive Align Frame
0
Loss of Receive Clk Clear / Loss of Receive Clk Clear
7
RLS3
RIM3
Spare Code Detected Condition Clear / -
6
Loop Down Code Clear / V52 Link Clear
5
Loop Up Code Clear / Receive Distant MF Alarm Clear
4
Loss of Receive Clk / Loss of Receive Clk
3
Spare Code Detect / -
2
Loop Down Detect / V52 Link Detect
1
Loop Up Detect / Receive Distant MF Alarm Detect
0
Receive Elastic Store Full
7
RLS4
RIM4
Receive Elastic Store Empty
6
Receive Elastic Store Slip
5
Receive Signaling Change of State (Enable in RSCSE1-4)
3
One Second Timer
2
Timer
1
Receive Multiframe
0
Receive FIFO Overrun
5
RLS5
RIM5
Receive HDLC Opening Byte
4
Receive Packet End
3
Receive Packet Star t
2
Receive Packet High Watermark 1
Receive FIFO Not Empty
0
Receive RAI-CI
5
RLS7
RIM7
Receive AIS-CI
4
Receive SLC-96 Alignment
3
Receive FDL Register Full
2
Receive BOC Clear
1
Receive BOC
0
Transmit Elastic Store Full
7
TLS1
TIM1
Transmit Elastic Store Empty
6
Transmit Elastic Store Slip
5
Transmit SLC96 Mult ifra me
4
Transmit Align Frame
3
Transmit Multiframe
2
Loss of Transmit Clock Clear
1
Loss of Transmit Clock
0
Transmit FDL Register Empty
4
TLS2
TIM2
Transmit FIFO Underrun
3
Transmit Me ssage End
2
Transmit FIFO Below Low Water mar k
1
Transmit FIFO Not Full Set
0
-
-
TLS3
TIM3
-
-
Loss of Frame
1
Loss of Frame Synchronization
0
Jitter Attenuator Limit Trip Clear 7
LLSR
LSIMR
Open Circuit Detect Clear
6
Short Circuit Detect Clear
5
Loss of Signal Detect Clear
4
Jitter Attenuator Limit Trip
3
Open Circuit Detect
2
Short Circuit Detect
1
Loss of Signal Detect
0
BERT Bit Error Detected
6
BLSR
BSIM
BERT Bit Counter Overflow
5
BERT Error Counter Overflow
4
BERT Receive All Ones
3
BERT Receive All Zeros
2
BERT Receive Loss of Synchronization
1
BERT in Synchronization
0
Interrupt Pin
0
RIIR
1
2
3
4
5
2
TIIR
1
0
7
GFISR1
GFIMR1
GTCR1.0
6
5
4
3
2
1
0
7
GLISR1
GLIMR1
6
5
4
3
2
1
0
7
GBISR1
GBIMR1
6
5
4
3
2
1
0
Framers 2-4
LI Us 2-4
BERTs 2-4
Dr a win g Le ge nd:
Interrupt Status
Registers Register Name
Interrupt Mask
Registers
Register Name
DS26514 4-Port T1/E1/J1 Transceiver
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9.8 System Backplane Interface
The DS26514 pr ov ides a v er satile backplane interface that can be c onfigured to:
• Transmi t and receive two-f r am e elastic stor es
• Mapping of T1 c hannels into a 2.048MHz bac k plane
• IBO mode f or multi ple f r am er s to share t he bac k plane si gnals
• Transmi t and receive channel bloc k ing capability
• Fractional T1/E1/ J 1 support
• Hardware-ba sed (t hr ough the backplane interf ac e) or processor-based signal ing
• Fl exi ble bac k plane clock providing frequenc ies of 2.048MHz, 4. 096M Hz, 8.192MHz, 16.384M Hz
• Backplane clock and fram e pulse (T S S Y NCIO n) generat or
9.8.1 Elastic Stores
The DS26514 c ontai ns dual, two-f rame elasti c stores for each f ram er: one f or the rec eiv e di recti on and one f or the
transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be
enabled/disabled independently of each other. Also, the transmit or receive elastic store can interf ace to either a
1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic
store. A ll f our channel s have thei r own TSY SCLKn/RSYSCLK n pins, all owing a uni que backpl ane system clock for
each channel. This allow s for ma ximum fle xibility in the design of the backplane clock structure.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26514 is in
the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the
elasti c store can rat e conv ert the E1 data stream to a 1. 544MHz backpl ane. Second, they can be used to absorb
the differences in phase and frequency between the T1 or E1 clock and an asynchronous (i.e., not locked)
backplane clock, which can be 1.544MHz or 2.048MHz. If the two clocks are not frequency locked, the elastic
stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to
m anage the difference bet ween the net work and t he bac k plane.
If the el astic store is enabled whil e in E1 m ode, then either CAS or CRC4 multif ram e boundaries are i ndicated vi a
the RMSYNCn output as control led by the RSMS2 co ntrol bit (RIOCR.1). If the user selects to appl y a 1.54 4MHz
cl oc k to the RSY S CLK n pin, t he Rec eive Blank Channel S elect Registers (RBCS1–4) deter mi ne whic h c hannel s of
the receiv ed E1 dat a stream will be del eted. I n this m ode an F-bi t loc ation is insert ed int o the RS ERn data and set
to one. Also, in 1.544MHz applications, the RCHBLKn output will not be active in channels 25 to 32 (or in other
words, RCBR4 i s not ac tive). If t he two-f rame elasti c buf fer eit her fi lls or em pti es, a control l ed sli p wil l oc cur. If the
buffer em pties, then a f ull frame of data wi ll be repeated at RSERn and t he RLS4. 5 and RLS4.6 bits will be se t to a
one. If the buffer fills, then a full fr am e of dat a will be deleted and the RLS4. 5 and RLS4.7 bi ts will be set t o a one.
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the
Interleave Bus Option (IBO), which is discussed in Section 9.8.2. Table 9-3 shows the registers related to the
elastic stores.
Table 9-3. Registers Rela ted to the Elastic Store
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive I/O Configurat ion Regi ster ( RIOCR)
084h
Sync and cl oc k sel ec tion for t he receiver.
Receive Elasti c St or e Control Register
(RESCR)
085h Rec eive elastic stor e c ontrol.
Receive Latched Status Register 4 (RLS4)
093h
Receive elastic stor e em pty full status.
Receive Interrupt Mask Register 4( RIM4)
0A3h
Receive interrupt mas k for elastic store.
Transmit Elastic Stor e Control Register
(TESCR)
185h Transmit elastic control such as mi nim um mode.
Transmit Latched Status Register 1 (TLS1)
190h
Transmit elastic store latc hed status.
Transmit Inter r upt Mask Regist er 1 (TIM1)
1A0h
Transmit elastic store inter r upt mask.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 37 of 305
9.8.1.1 Elasti c S tores In itiali z at io n
There are two elastic store initializations that may be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLKn/TSYSCLKn are locked to
RCLKn/TCLKn, respectively). The elastic store reset is used to minimize the delay through the elastic store. The
elastic store align bit is used to cent er the read/write poi nters to the ex tent possible.
Table 9-4. Elastic Store Delay After Initialization
INITIALIZATION REGISTER BIT DELAY
Receive Elasti c St or e Reset
RESCR.2
N bytes < Delay < 1 Frame + N bytes
Transmit Elastic Stor e Reset
TESCR.2
N bytes < Delay < 1 Frame + N bytes
Receive Elasti c St or e Ali gn
RESCR.3
1/2 F r am e < Delay < 1 1/2 Frames
Transmit Elastic Stor e Ali gn
TESCR.3
1/2 F r am e < Delay < 1 1/2 Frames
N = 9 for RSZS = 0; N = 2 for RSZS = 1
9.8.1.2 Minimum Delay Mode
El astic store mi nimum delay m ode m ay be used when the elastic stor e’s system cl oc k is l oc k ed to its network c lock
(i.e., RCLKn locked to RSYSCLKn for the receive side and TCLKn locked to TSYSCLKn for the transmit side).
RESCR. 1 enables the receiv e elastic store minimum delay m ode. W hen enabled, the elasti c stores will be forced to
a maxim um dept h of 32 bits instead of the norm al two-f ram e depth. This f eature is usef ul primarily in appli cati ons
that i nterface to a 2.048MHz bus. Certai n restrictions appl y when minim um delay mode is used. I n additi on to the
restriction mentioned above, RSYNCn must be configured as an output when the receive elastic store is in
minimum delay mode, and TSYNCn must be configured as an output when transmit minimum delay mode is
enabled. In this mode, the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a
typical application RSYSCLKn and TSYSCLKn are locked to RCLKn, and RSYNCn (frame output mode) is
connected to TSSYNCIOn (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All
the slip cont ention logic in the f r am er is disabled (sinc e slips cannot occ ur ) . On po wer-up after the RSY S CLK n and
TSYSCLKn signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2)
should be toggled fr om a zero to a one to ensure prope r oper ation.
9.8.1.3 Additional Recei ve E lastic Store Information
If the r ec eiv e-si de elastic stor e is enabled, t hen the user m ust provi de either a 1.544M Hz or 2.048MHz cl ock at t he
RSYSCLKn pin. See Section 9.8.2 for higher rate system clock applications. The user has the option of either
providing a frame/multiframe sync at the RSYNCn pin or having the RSYNCn pin provide a pulse on
frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the
multiframe sync input on RSYNCn. Otherwise, a multiframe sync input on RSYNCn is treated as a simple frame
boundary by t he elasti c store. T he fr amer will always i ndicate f ram e boundaries on the net work side of the elastic
store via the RFSYNCn output whether the elastic store is enabled or not. Multiframe boundaries will always be
indicated via the RMSYNCn output. If the elastic store is enabled, then RMSYNCn will output the multiframe
boundary on the backpl ane si de of the elastic store. When t he device is receivi ng T1 and the back plane is enabled
for 2.048MHz operation, the RMSYNCn signal will output the T1 multiframe boundaries as delayed through the
elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the
RMSYNCn si gnal will output the E 1 multiframe boundaries as del ay ed through the elastic store.
If the user selec ts to apply a 2. 048M Hz c lock t o the RSY S CLK n pin, the user can use t he bac k plane blank c hannel
select r egisters (RBCS1–4) to det ermine which channels wil l have the data output at RSERn for c ed to all ones.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 38 of 305
9.8.1.4 Receivin g Mapp ed T 1 Channels from a 2.048MHz Backpl ane
Setting the TSCLKM bit in TIOCR.4 enables the transmit elastic store to operate with a 2.048MHz backplane (32
tim e sl ots / frame) . In this mode the user can choo se whi ch of t he backplane channels on TSERn will be mapped
int o the T1 dat a stream by programmi ng the Transmi t Bl ank Channel Select registers (TBCS1–4). A logi c 1 in the
associated bit location forces the t r ansmit elastic store to ignore bac k plane data for that channel. Typicall y the user
will want to progr am ei ght channel s to be ignored. The def ault (power-up) c onfiguration will ignor e c hannels 25–32,
so that t he first 24 backplane c hannels are mapped into the T1 transmi t dat a str eam .
For example, if the user desired to transmit data from the 2.048MHz backplane channels 2–16 and 18–26, the
TBCS registers should be progr am med as follows:
TBCS1 = 01h :: ignore bac k plane channel 1 ::
TBCS2 = 00h
TBCS3 = 01h :: ignore bac k plane channel 17 ::
TBCS4= FCh :: ignor e bac k plane channels 27–32 ::
9.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
Setting the RSCLK M bit in RIOCR.4 will enabl e the receive elastic stor e to operate with a 2.048MHz bac k plane (32
time slots/frame). In this mode the user can choose which of the backplane channels on RSERn receive the T1
data by programming the Receive Blank Channel Select registers (RBCS1–4). A logic 1 in the associated bit
loc ation wi ll forc e RS E Rn high for t hat back plane channel . Typically the user will want t o pr ogr am eight channels to
be blanked. The default (power-up) configuration will blank channels 25 to 32, so that the 24 T1 channels are
mapped into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by
setting RBCS1.0 = 1, then the F-bit will be passed into the MS B of TS0 on RSE Rn.
For example, if:
RBCS1 = 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4 = FCh
Then on RSE Rn:
Channel 1 (MSB) = F-bit
Channel 1 ( bits 1-7) = all ones
Channels 2-16 = T1 channels 1-15
Channel 17 = all ones
Channels 18-26 = T1 channels 16-24
Channels 27-32 = all ones
Note that when two or m ore sequential channel s are chosen to be bl anked, the receiv e sli p zone select bit should
be set to zero. If the blank c hannels are distri buted (su c h as 1, 5, 9, 13, 17, 21, 25, 29) , the RS ZS bi t can be set to
one, which c an pr ov ide a lower occurrenc e of sli ps i n certai n applicati ons.
If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full
fram e of data will be repeated at RSE Rn and the RLS4.5 and RLS4.6 bits wi ll be set to a one. If t he buffer fills, then
a full fr am e of dat a will be deleted and the RLS4.5 and RLS4. 7 bits will be set to a one.
9.8.1.6 Receivin g Mapp ed E1 Transmi t Chann els fro m a 1.544MHz Backplane
The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz
backpl ane (24 channels / f r am e + F-bit). I n this m ode the u ser can choo se which of t he E1 t im e slots wi ll hav e all -
ones data inserted by programming the Transmit Blank Channel Select registers (TBCS1–4). A logic 1 in the
associated bit location will cause the elastic store to force all ones at the outgoing E1 data for that channel.
Typically the user wil l want t o pr ogr am eight channels to be blank ed. The default (power-up) configuration w ill blank
channel s 25 to 32, so that the fir st 24 E 1 channel s are mapped from t he 24 channel s of the 1.544M Hz bac k plane.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 39 of 305
9.8.1.7 Mapping E 1 Channels onto a 1.544M Hz Backplane
The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be
ignor ed (not t ransm itt ed onto RSE Rn) by pro gram mi ng the Receive Blank Channel Sel ect regi sters (RBCS1–4). A
logic 1 in the associated bit location will cause the elastic store to ignore the incoming E1 data for that channel.
Typically, the user will want to program eight channels to be ignored. The default (power-up) configuration will
ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the 1.544MHz
backplane. I n this m ode the F-bit location at RSERn is always set to 1.
For ex am ple, if the user wants to i gnore E1 t ime slot s 0 (channel 1) and T S 16 (channel 17), the RBCS re gisters
would be programmed as foll ows:
RBCS1 = 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4 = FCh
9.8.2 IBO Multiplexing
The DS26514 offers two m ethods of multiplexing dat a streams onto a high-speed backpl ane bus.
The default method multiplexes the data streams internally and then outputs them on one pin, e.g., RSER1. For
example, if the user wants to m ultiplex RSER[4:1] together to m ake a 8 MHz high-speed bus, the data str eam will
be output on RSER1 only. The traditional method, external multiplexing of IBO operation, that allows the user to
gang signal s together on the P CB is supported. RS E Rn and RSIGn will three-state at the appropri ate tim es to allow
the ganging of these signals together. In a 16 MHz IBO bus, 8 channels are multiplexed. In this mode, the
DS26514 is assigned to channels 1-4 of the 8-channel bus. The DS26514 cannot assign its four datastreams to
other channels of the bus, e.g. channels 5-8 cannot be accessed or assigned. This applies to the internal
m ultipl ex ing and well as external m ultiplexing m ethods.
The selec tion between external ganging and internal multiple xing is made via GTCR1.GIBO.
Note that in IBO mode, the channel block signal s TCHBLK n and R CHBLKn are refer enced to as TSYSCLKn and
RSYSCLKn.
Figure 9-11, Figure 9-12, and Figure 9-13 show the equivalent internal circuit for each IBO mode. These figures
only show channels 1-4. Table 9-5 describes the pin fu nction changes for each mode of the IBO mu ltip lexer.
Table 9-5. Registers Related to the IBO Multiplexer
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Globa l Trans ceiver Contro l
Register 1 ( GTCR1) 00F0h T his is a gl obal r egister used to specify ganged operation
for the IB O.
Global Fram er Control Register 1
(GFCR1) 00F1h T his global register defines the num ber of devic es per
bus and bus speed.
Receive Interleave Bus Operat ion
Control Register (RIBOC) 088h This register c onfigures the per-port IBO enable and type
of interlea ving (channel vs . frame) .
Transmit Interleave Bus
Operation Control Register
(TIBOC) 188h This register c onfigures the per-port IBO enable and type
of interlea ving (channel vs . frame) .
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 40 of 305
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 1
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 2
Backplane
Interface
RIBO_OEB
RSER1
RSIG1
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 3
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 4
Backplane
Interface
RIBO_OEB
RSER3
RSIG3
RSYNC3
RSYSCLK
TSER3
TSIG3
TSSYNCIO
TSYSCLK
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 41 of 305
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 1
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 2
Backplane
Interface
RIBO_OEB
RSER1
RSIG1
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 3
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 4
Backplane
Interface
RIBO_OEB
DS26514 #1
DS26514 #1
DS26514 #1
DS26514 #1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 42 of 305
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 1
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 2
Backplane
Interface
RIBO_OEB
RSER1*
RSIG1**
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 3
Backplane
Interface
RIBO_OEB
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
Port # 4
Backplane
Interface
RIBO_OEB
DS26514 #1
DS26514 #1
DS26514 #1
DS26514 #1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 43 of 305
Table 9-6. RSER Output Pin Definitions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4. 096M Hz IBO 8.192MHz I BO 16.384M Hz IBO
RSER1 Rx Serial Data for
Por t # 1 Combined Rx Serial
Data for Ports 1 & 2
Combi ned R x S erial
Dat a for Port s 1, 2 ,
3 , & 4
Combi ned R x S erial
Dat a for Port s 1, 2 ,
3 , & 4
RSER2
Rx Serial Data for
Por t # 2 Reserved Unused Unused
RSER3
Rx Serial Data for
Por t # 3 Combined Rx Serial
Dat a for Port s 3 & 4 Unused Unused
RSER4
Rx Serial Data for
Por t # 4 Unused Unused Unused
Table 9-7. RSIG Output Pin Definitions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4. 096M Hz IBO 8.192MHz I BO 16.384M Hz IBO
RSIG1 Rx Signaling Data
for Port # 1
Combi ned R x
Signali ng Dat a for
Ports 1 & 2
Combi ned R x
Signali ng Dat a for
Ports 1, 2, 3, & 4
Combi ned R x
Signali ng Dat a for
Ports 1, 2, 3, & 4
RSIG2
Rx Signaling Data
for Port # 2 Unused Unused Unused
RSIG3
Rx S ig nali ng Data
for Port # 3
Combi ned R x
Signali ng Dat a for
Ports 3 & 4
Unused Unused
RSIG4
Rx Signaling Data
for Port # 4 Unused Unused Unused
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 44 of 305
Table 9-8. TSER Input Pin Definitions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4. 096M Hz IBO 8.192MHz I BO 16.384M Hz IBO
TSER1 Tx Serial Data for
Por t # 1 Combined Tx Serial
Dat a for Port s 1 & 2
Combi ned Tx Serial
Dat a for Port s 1, 2 ,
3 , & 4
Combi ned Tx Serial
Dat a for Port s 1, 2 ,
3 , & 4
TSER2
Tx Serial Data for
Por t # 2 Unused Unused Unused
TSER3
Tx Serial Data for
Por t # 3 Combined Tx Serial
Dat a for Port s 3 & 4 Unused Unused
TSER4
Tx Serial Data for
Por t # 4 Unused Unused Unused
Table 9-9. TSIG Input Pin Defi nitions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4. 096M Hz IBO 8.192MHz I BO 16.384M Hz IBO
TSIG1 Tx Signaling Data
for Port # 1
Combi ned Tx
Signali ng Dat a for
Ports 1 & 2
Combi ned Tx
Signaling Data for
Ports 1, 2, 3, & 4
Combi ned Tx
Signali ng Dat a for
Ports 1, 2, 3, & 4
TSIG2
Tx Signaling Data
for Port # 2 Unused Unused Unused
TSIG3
Tx Signaling Data
for Port # 3
Combi ned Tx
Signali ng Dat a for
Ports 3 & 4
Unused Unused
TSIG4
Tx Signaling Data
for Port # 4 Unused Unused Unused
DS26514 4-Port T1/E1/J1 Transceiver
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Table 9-10. RSYNC Input Pin D efinit ions (GTCR1.GIBO = 0)
PIN
NAME
NORMAL USE 4. 096M Hz IBO 8.192MHz I BO 16.384M Hz IBO
RSYNC1
Rx Fr ame Puls e f or
port # 1
Rx Fr ame Puls e f or
Ports 1 & 2
Rx Fr ame Puls e f or
Ports 1, 2, 3, & 4
Rx Fr ame Puls e f or
Ports 1, 2, 3, & 4
RSYNC2
Rx Fr ame Puls e f or
port # 2 Unused Unused Unused
RSYNC3
Rx Fr ame Puls e f or
port # 3 Rx F rame Pul se for
Ports 3 & 4 Unused Unused
RSYNC4
Rx Fr ame Puls e f or
port # 4 Unused Unused Unused
9.8.3 H.100 (CT Bus) Compatibility
The H. 100 ( or CT bus) is a synchronou s, bit-seri al, TDM transport bus operati ng at 8.192MHz . The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26514 to accept a CT-bus-
compatible frame-sync signal ( CT_FRAME) at the RS YNCn and TSSYNCIO n (input mode) inputs. S ee Figure 9-14
and Figure 9-15.
The f ollowing rules apply to the H100EN c ontrol bit:
1) The H100EN bit controls the sampling point for the RSYNCn (input mode) and TSSYNCIOn (input
m ode) only . T he RSYNCn out put and other sync si gnals are not affect ed.
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store
buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with
4.096MHz IBO mode or 2.048MHz back plane oper ation.
4) The H100EN bit in RIOCR controls both RSYNCn and TSSYNCIOn (i.e., there is no separate control
bit for the TSSYNCIOn).
5) The H100EN bit does not i nvert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR)
m ust be set high to i nv ert the i nbound sync si gnals.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 46 of 305
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode
BIT 8
BIT 1
BIT 2
RSYNCn1
RSYNCn2
RSYSCLKn
RSERn
tBC
3
NOTE 1: RSYNCn INPUT MODE IN NO RMAL OPERATI ON.
NOTE 2: RSYNCn INPUT MODE, H100EN = 1 AND RSY NCINV = 1.
NOT E 3: tBC (BIT CELL TIME) = 122ns (ty p). t BC = 244ns or 488ns ALSO ACCEP T ABLE.
BIT 8
BIT 1
BIT 2
TSSYNCIOn1
TSSYNCIOn2
TSYSCLKn
TSERn
t
BC
3
NOTE 1: TS SY NCIOn I N NORMA L OPERATION.
NOTE 2: TS SY NCIOn WITH H100EN = 1 and TSSYNCI NV = 1.
NOT E 3: tBC (BIT CELL TIME) = 122ns (ty p). t BC = 244ns OR 488ns ALSO ACCEPTABLE.
DS26514 4-Port T1/E1/J1 Transceiver
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9.8.4 Transmit and Receive Channel Blocking Registers
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking
Register s (TCBR1/T CB R2/TCBR3/TCB R4) c ontrol the RCHB LK n and TCHBLKn pi ns, respectiv ely . The RCHBLKn
and TCHBLKn pins are user-programmable outputs that can be forced either high or low during individual
channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications.
When the appropriate bits are set to a one, the RCHBLKn and TCHBLKn pins will be held high during the entire
corresponding channel time. When used with a T1 (1.544MHz) backplane, only TCBR1 to TCBR3 will be used.
TCBR4 is included to support an E1 (2.048MHz) backplane when the elastic store is configured for T1-to-E1 rate
conversion (See Section 9.8.1).
9.8.5 Transmit Fractional Support (Gapped Clock Mode)
The DS26514 c an be programmed to output gapped cl oc k s for selected channel s i n the receive and t r ansmit paths
to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the
gapped cl oc k feature i s enabl ed, a gated clock is output on t he TCHCLK signal . The channel selecti on is controlled
via the Transmit Gapped Clock Channel Select Registers (TGCCS1–4). The transmit path is enabled for gapped
clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omi tt ed ( only the seven m ost si gnificant bit s of the channel hav e clocks).
9.8.6 Receive Fractional Support (Gapped Clock Mode)
The DS26514 c an be programmed to output gapped cl oc k s for selected channel s i n the receive and t r ansmit paths
to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLKn signal. The channel selection is
contr olled v ia the Receiv e Gapped Cl ock Channel Select Regi sters (RGCCS1–4). The rec eiv e path i s enabled f or
gapped cl oc k m ode with the RG CLK E N bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omi tt ed ( only the seven m ost si gnificant bit s of the channel hav e clocks).
DS26514 4-Port T1/E1/J1 Transceiver
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9.9 Framers
The DS26514 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and
m ultif r am e boundar ies and monitors the data stream f or al arms. It is al so used for ex tracti ng and inserting si gnali ng
data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding,
synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides
clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks,
and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access
and contr ol of the devic e.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
insert s the CRC c odes, and pr ov ides the B8Z S (zer o code suppres si on) and A M I line c oding.
Both t he tr ansmi t and r eceive pat h hav e an HDLC con troll er. The HDLC c ontrol l er t ransmits and rec eiv es data v i a
the f ramer bloc k. The HDLC cont roller m ay be assi gned to any tim e slot, portion of a tim e slot, or to F DL (T1). The
HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to
m anage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for i nterfacing to asynchronous systems, c onverting from a T 1/E1 network to a 2. 048MHz,
4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). An IBO (Interleav e Bus Option) is provided to allow multiple framers in the DS26514 to
share a high-speed bac k plane.
9.9.1 T1 Fra ming
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit
contai ns a fix ed pattern for the rec eiv er to deli neate the fram e boundari es. T he F-bit i s inserted once per f rame at
the beginning of the transmit frame boundary . The frames are furt her gr ouped into bundles of frames 12 for D4 and
24 for ES F.
The D4 and ESF framing modes are outl ined in Table 9-11 and Table 9-12. I n the D4 m ode, f r aming bi t f or f rame
12 is i gnor ed if Japanese Yel low is sel ec ted. Table 9-13 shows SLC-96 f r ami ng.
Table 9-11. D4 Framing Mode
FRAME
NUMBER
Ft Fs SIGNALING
1
1
2
0
3
0
4
0
5
1
6
1
A
7
0
8
1
9
1
10
1
11
0
12
0
B
DS26514 4-Port T1/E1/J1 Transceiver
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Table 9-12. ESF Framing Mode
FRAME
NUMBER
FRAMING FDL CRC SIGNALING
1
√
2
CRC1
3
√
4
0
5
√
6
CRC2
√
7
√
8
0
9
√
10
CRC3
11
√
12
√
13
√
14
CRC4
15
√
16
0
17
√
√
18
CRC5
19
√
20
1
21
√
22
CRC6
23
√
24
1
√
Table 9-13. SLC-96 Framing
FRAM E NUMBER Ft Fs SIGNALING
1
1
2
0
3
0
4
0
5
1
6
1
A
7
0
8
1
9
1
10
1
11
0
12
0
B
13
1
14
0
15
0
16
0
17
1
18
1
C
19
0
20
1
21
1
22
1
23
0
24
C1 (Concentrator Bit)
D
25
1
26
C2 (Concentrator Bit)
27
0
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FRAM E NUMBER Ft Fs SIGNALING
28
C3 (Concentrator Bit)
29
1
30
C4 (Concentrator Bit)
A
31
0
32
C5 (Concentrator Bit)
33
1
34
C6 (Concentrator Bit)
35
0
36
C7 (Concentrator Bit)
B
37
1
38
C8 (Concentrator Bit)
39
0
40
C9 (Concentrator Bit)
41
1
42
C10 (C oncentr ator Bit)
C
43
0
44
C11 (C oncentr ator Bit)
45
1
46
0 (S poiler Bit)
47
0
D
48
1 (S poiler Bit)
49
1
50
0 (S poiler Bit)
51
0
52
M1 (Maintenance Bit)
53
1
54
M2 (Maintenance Bit)
A
55
0
56
M3 (Maintenance Bit)
57
1
58
A1 (Alarm Bit )
59
0
60
A2 (Alarm Bit )
B
61
1
62
S1 (Switch Bit)
63
0
64
S2 (Switch Bit)
65
1
C
66
S3 (Switch Bit )
67
0
68
S4 (Switch Bit)
69
1
70
1 (S poiler Bit)
71
0
72
0
D
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.2 E 1 Framing
The E1 frami ng c onsi sts of FAS, NFAS det ection as shown in Table 9-14.
Table 9-14. E1 F AS/NFAS Framing
CRC-4
FRAME
#
TYPE 1 2 3 4 5 6 7 8
0
FAS
C1
0
0
1
1
0
1
1
1
NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
2
FAS
C2
0
0
1
1
0
1
1
3
NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
4
FAS
C3
0
0
1
1
0
1
1
5
NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
6
FAS
C4
0
0
1
1
0
1
1
7
NFAS
0
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
8
FAS
C1
0
0
1
1
0
1
1
9
NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
10
FAS
C2
0
0
1
1
0
1
1
11
NFAS
1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
12
FAS
C3
0
0
1
1
0
1
1
13
NFAS
E1
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
14
FAS
C4
0
0
1
1
0
1
1
15
NFAS
E2
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
C = C bits are the CRC-4 remainder; A = alarm bits; Sa = bits for data link.
DS26514 4-Port T1/E1/J1 Transceiver
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Table 9-15 shows the registers that ar e r elated to setting up the fr ami ng.
Table 9-15. Registers Related to Setting Up the Framer
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Master Mode Regist er (TMMR) 180h T1/E1 mode.
Transmit Control Regist er 1 (TCR1) 181h S our c e of the F -bit.
Transmit Control Regist er 2 (T1.TCR2) 182h F-bit c or r uption, sel ec tion of SLC-96.
Transmit Control Regist er 3 (TCR3) 183h E S F or D4 mode sel ec tion.
Receive Master Mode Register (RMMR) 080h T1/E1 sel ec tion for r ec eiv er .
Receive Control Register 1 (RCR1) 081h Resynchronization criteria for the framer .
Receive Control Register 2 (T1RCR2) 014h T1 remot e alarm and OOF cri teri a.
Receive Control Register 2 (E1RCR2) 082h E 1 r ec eive loss of signal c riter ia selection.
Receive Latched Status Register 1 (RLS1) 090h Rec eive latched status 1.
Receive Interrupt Mask Register 1 (RIM1) 0A0h Receive interrupt mas k 1.
Receive Latched Status Register 2 (RLS2) 091h Rec eive latched status 2.
Receive Interrupt Mask Register 2 (RIM2) 0A1h Receive interrupt mas k 2.
Receive Latched Status Register 4 (RLS4) 093h Rec eive latched status 4.
Receive Interrupt Mask Register 4 (RIM4) 0A3h Receive interrupt mas k 4.
Fram es Out of Sync Count Regi ster 1
(FOSCR1)
054h Framer out of sync r egister 1.
Fram es Out of Sync Count Regi ster 2
(FOSCR2)
055h Framer out of sync r egister 2.
E1 Receive Align Frame Register (E1RAF) 064h RA F byte.
E1 Receive Non-Align Frame Register
(E1RNAF)
065h RNA F byte.
Transmit SLC-96 Data Li nk Register 1
(T1TSLC1)
164h Transmit SLC-96 bits.
Transmit SLC-96 Data Li nk Register 2
(T1TSLC2)
165h Transmit SLC-96 bits.
Transmit SLC-96 Data Li nk Register 3
(T1TSLC3) 166h Transmit SLC-96 bits.
Receive SLC-96 Data Link Regi ster 1
(T1RSLC1) 064h Rec eive SLC-96 bits.
Receive SLC-96 Data Link Regi ster 2
(T1RSLC2) 065h Rec eive SLC-96 bits.
Receive SLC-96 Data Link Regi ster 3
(T1RSLC3) 066h Rec eive SLC-96 bits.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.3 T1 Transmi t Sy nchronizer
The DS26514 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
loc ated i n the TSYNCC register. The latched status bit TLS3. 0 (LOFD) is provi ded to indicate t hat a loss of f ram e
synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for
fram e/multifram e alignment. The LOFD bit can be enabl ed to cause an int er r upt condition on INTB.
Note that when the transmi t synchroni zer is used, the T SYNCn signal should b e set a s an o utput (TSIO = 1) and
the recov er ed f rame-sync pul se will be output on t his signal . The recov ered CRC-4 m ulti-frame sync pul se wil l be
output if enabled with TIOCR.0 (TSM = 1).
Ot her k ey poi nts concerning the E 1 transmit synchr onizer:
1) The Tx synchr onizer is not oper ational when the tr ansmit elastic stor e is enabl ed, includ ing IBO modes.
2) The Tx synchr onizer does not perform CRC-6 alignment verification ( ESF mode) and does not v er ify
CRC-4 codewords.
The Tx synchronizer c annot search for the CAS m ultifram e. Table 9-16 shows the regi ster s related t o the t r ansmit
synchronizer.
Table 9-16. Register s Related to the Transm it Synch r on izer
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Synchronizer Control Register
(TSYNCC) 18Eh Resynchronization control for the transmit
synchronizer.
Transmit Control Regist er 3 (TCR3) 183h TFM bit selec ts between D4 and ESF for the
transmit synchronizer.
Transmit Latched Status Register 3
(TLS3) 192h P r ov ides latched stat us for the transmit
synchronizer.
Transmit Inter r upt Mask Regist er 3
(TIM3) 1A2h Provides mas k bits for the TLS3 s tatus.
Transmit I/O Confi gur ation Register
(TIOCR) 184h TSYNCn should be set as an output.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
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9.9.4 Signaling
The DS26514 supports both software and hardware-based signaling. Interrupts can be generated on changes of
signaling data. The DS26514 is also equipped with receive-signaling freeze on loss of synchronization (OOF),
carrier loss or change of f r am e alignm ent. The DS26514 also has hardware pins to indicate signali ng freeze.
Feat ur es i ncl ude the following:
Flexi ble si gnaling support:
Software or har dware ba sed
Int er r upt generated on c hange of signaling data
Receive-si gnaling freez e on loss of fram e, loss of signal, or change of fram e alignm ent
Hardware pins for carrier loss and signaling freez e indic ation
Table 9-17. Registers Related to Signaling
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit-Signaling Register s 1 to 16
(TS1 to TS16) 140h to 14B h ( T1/J1)
140h to 14F h ( E 1 CAS) Transmit ABCD signaling.
Software-Signaling Insertion Enable
Register s 1 to 4 ( SSIE1 to SSIE4) 118h, 119h, 11A h, 11Bh When enabl ed, signaling is i nsert ed for
the channel.
Transmit Hardware-Signaling Channel
Sel ec t Registers 1 to 4
(THSCS1 to THSCS4) 1C8h, 1C9h, 1CAh, 1CBh Bits determine which c hannels will have
signal ing inserted in hardware-signaling
mode.
Receive-Signali ng Control Register
(RSIGC) 013h Freeze control for rec eiv e si gnaling.
Receive-Signali ng Al l-Ones Insert ion
Register s 1 to 3
(T1RSAOI1 to T1RSAOI3) 038h, 039h, 03A h Registers for all -ones i nsert ion (T 1 mode
only).
Receive-Signali ng Registers 1 to 16
(RS1 to RS 16) 040h to 04B h ( T1/J1)
040h to 04F h ( E 1) Receive-signali ng by tes.
Receive-Signali ng S tatus Register s 1
to 4 (RSS1 to RSS4) 098h to 09A h ( T1/J1)
98h to 9F h (E1) Receive-signaling c hange of status bits.
Receive-Signali ng Change of State
Enabl e Registers 1 to 4 (RSCSE1 to
RSCSE4)
0A8h, 0A 9h, 0AAh, 0ABh Receive-si gnaling change of state
interrupt enabl e.
Receive Latched Status Register 4
(RLS4) 093h Receive-signaling change of state bi t.
Receive Interrupt Mask Register 4
(RIM4) 0A3h Receive-signali ng c hange of state
interrupt mas k bit.
Receive-Signaling Reins ertion Enable
Register s 1 to 4 ( RSI1 to RSI4) 0C8h, 0C9h, 0CAh, 0CBh Registers for signaling reinsertion.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
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9.9.4.1 Transmit-Sig na lin g Ope r a tion
There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or
hardware based. Processor-based refers to access through the transmit signaling registers, TS1–TS16, while
hardware based r efer s to using the T SIGn pi ns. B oth methods can be used simultaneousl y .
9.9.4.1.1 Processor-Based Transmit Signaling
In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1–TS16) via the host
interface. On m ultifram e boundar ies, the contents of these register s ar e loaded i nto a shift r egister for plac ement in
the appropr iat e bit posi tion in the outgoi ng dat a stream. The user can util ize t he tr ansmit multif ram e i nter rupt in the
Transmi t Lat ched Stat us Register 1 (TLS1.2) to know when t o update t he signal ing bit s. The user need not updat e
any tr ansmit si gnali ng regi ster f or which there i s no change of state for that register .
Each transmit-signaling register contains the robbed-bit signaling (TCR1.4 in T1 mode) or TS16 CAS signaling
(TCR1. 6 in E1 mode) for one time slot that will be insert ed into t he outgoing str eam . Signaling data c an be sour c ed
from the TS registers on a per-channel basis by using the Software Signali ng Insertion Enabl e Register s, SSIE1–4.
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a full
m ultifr ame of signali ng dat a. In T1 D4 f raming mode, there are onl y t wo signal i ng bits per channel (A and B). In T 1
D4 fram ing mode, t he framer uses A and B bi t posi tions f or the next m ultifram e. The C and D bit positi ons becom e
‘don’t car e’ in D4 mode.
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel
Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different
channel num ber schem es in E1. In “ channel ” number ing, T S0–TS31 are label ed channel s 1 through 32. In “Phone
Channel” numbering TS1–TS15 are labeled channel 1 to channel 15 and TS17–TS31 are labeled channel 15 to
channel 30.
9.9.4.1.2 Time Slot Numbering Schemes
TS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Phone
Channel
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
9.9.4.1.3 Hardware-Based Transmi t Signaling
In hardware-based mode, signaling data is input via the TSIGn pin. This signaling PCM stream is buffered and
insert ed to the dat a stream being i nput at the TSERn pin.
Si gnaling data m ay be input via the Transmit Hardware-Si gnaling Channel S elect Regi ster (THSCS1) function. The
framer can be set up to take the signaling data presented at the TSIGn pin and insert the signaling data into the
PCM dat a stream that i s being i nput at the T SERn pi n. T he user can cont rol which chan nel s are t o hav e signal i ng
data from the TSIGn pin inserted into them on a per-channel basis. The signaling insertion capabilities of the
framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled,
the back plane clock (T SYSCLK n) c an be either 1.544MHz or 2.048MHz.
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9.9.4.2 Receive-Signaling Operation
There ar e two methods to access receive-si gnaling data and prov ide tr ansmit-signali ng data: processor based ( i.e.,
soft ware based) or hard ware ba sed. P rocessor-ba sed ref er s to access thr ough t he tran sm it- and receive-signaling
registers, RS1–RS16. Hardware based refers to t he RSIGn pin. Bot h m ethods can be used sim ultaneously.
9.9.4.2.1 Processor-Based Receive Signaling
Signaling information is sampled from the receive data stream and copied into the Receive-Signaling Registers,
RS1–RS16. T he signali ng inform ation in these regi sters is always updat ed on m ul tiframe boundar ies. T his f uncti on
is al ways enabled.
9.9.4.2.2 Change of State
To av oid constant m oni toring of the r eceiv e-signali ng regi sters, the DS 26514 c an be pr ogram m ed to al ert the host
when any specific channel or channels undergo a change of their signaling state. RSCSE1–4 are used to select
which channels can cause a change of state indication. T he c hange of stat e is indicated in Receiv e Latched Status
Register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three
m ultiframes bef ore a change of stat e indication is indicated. The user can enable t he INTB pin to t oggle low upon
detection of a change in si gnaling by setting the int er r upt mask bit RIM4.3. The s ignaling integration mode is global
and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the Receive-
Si gnaling Status Registers (RSS1–4) . The information from these registers will tell the user which RSx register to
read for the new signaling data. All changes are indicated in the RSS1–4 registers regardless of the RSCSE1–4
registers.
9.9.4.2.3 Hardware-Based Receive Signaling
In hardware-ba sed signal i ng the si gnaling dat a is can be obtai ned f rom the RSERn pin or the RSIGn pin. RSIGn is
a signaling PCM stream output on a channel by channel basis from the signaling buffer. The T1 robbed bit or E1
TS16 signaling data is still present in the original data stream at RSERn. The signaling buffer provides signaling
data to the RSIGn pin and also allows signaling data to be reinserted into the original data stream in a different
alignment that is determined by a multiframe signal from the RSYNCn pin. In this mode, the receive elastic store
m ay be enabled or di sabl ed. If the receive elasti c store i s enabled, then the backplane clock (RSYSCLKn) can be
either 1.544M Hz or 2.048M Hz . I n the ES F f r ami ng m ode, t he A B CD si gnaling bi ts are output on RSIG n in the lower
nibbl e of each channel . T he RSI Gn dat a is updated on ce a m ult ifr am e (3ms f or T1 ESF, 1.5ms f or T 1 D4, 2ms f or
E1 CAS) unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on
RSIGn i n the l ower ni bble of each channel. Hence, bit s 5 and 6 contai n the same dat a as bits 7 and 8, r espect iv ely ,
in eac h c hannel.
9.9.4.2.4 Receive-Sign aling Re inse rtio n at R SERn
In this mode, the user will provide a multiframe sync at the RSYNCn pin and the signaling data will be reinserted
based on this alignment. In T1 m ode, t his results in two c opies of the signali ng data in t he RSERn dat a str eam. The
original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied
multiframe sync applied at RSYNCn. In voice channels this extra copy of signaling data is of little consequence.
Reinsert ion c an be avoided i n data channel s si nce thi s f eat ure i s activat ed on a per-channel basi s. For rei nserti on,
the elastic store must be enabled and for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1
signal ing information cannot be reinserted into a 1.544MHz bac k plane.
Si gnaling reinsertion mode i s enabled, on a per-chann el basis by sett ing the receiv e-signali ng reinsertion channel
select bit hi gh in t he RSI1–4 regi ster. The channel s t hat ar e to have si gnali ng rei nserted ar e sel ected by writ i ng to
the RSI1–4 registers. I n E 1 m ode, t he user will generally select all c hannels or none for reinsertion.
9.9.4.2.5 Force Receive-S ignaling All On e s
In T 1 m ode, t he user can on a per-channel ba sis f orce t he robbed-bi t signal i ng bi t posit i ons to a one. Thi s is done
by using t he Receive-Si gnaling All -Ones Inser tion Registers (T1RSAOI1–3). The user sets t he channel select bit in
the T1RSAOI1–3 registers to selec t the channels that are to hav e the signaling forced to one.
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.4.2.6 Receive-Signaling Freeze
The signali ng data i n t he four multifram e si gnaling buffers will be froz en in a known good state upon either a los s of
synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the
requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE
control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2)
high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer
provi des a three m ul tifram e delay i n the signal i ng bits provi ded at the RSI Gn pin ( and at the RS ERn pi n if receiv e-
signal ing reinserti on is enabl ed). W hen freezing is enabled (RSFE = 1), the signaling data will be held in the last
known good state until the corrupting error condition subsides. When the error condition subsides, the signaling
data will be held in the old stat e for at l east an additional 9ms (4. 5m s in D4 fra ming mode, 6ms for E1 mode) before
being allowed to be updated wit h new signal ing data.
The receive-signaling registers are frozen and not updated during a loss of sync condition. They will contain the
m ost r ec ent signaling information befor e the LOF oc c urred.
9.9.4.3 Transmit SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-
frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the norm al Fs pattern. Additional SLC-96
inf orm ation can be f ound in BellCor e docum ent T R-TSY-000008. Regi sters rel ated to the transm it FDL are shown
in Table 9-18.
Table 9-18. Registers Related to SLC-96
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit FDL Regis ter (T1TFDL) 162h
For sendi ng m essages in transmit SLC-96 Ft/Fs
bits.
Transmit SLC-96 Data Li nk Registers 1
to 3 (T1TSLC1:T1TSLC3) 164h, 165h, 166h Registers that c ontrol the SLC-96 over head
values.
Transmit Control Regist er 2 T1.TCR2) 182h
Transmit control for data selection source for the
Ft/Fs bits.
Transmit Latched Status Register 1
(TLS1) 190h S tatus bit for indic ating transmission of data li nk
buffer.
Receive SLC-96 Data Link Regi ster s 1
to 3 (T1RSLC1:T1RSLC3) 064h, 065h, 066h —
Receive Latched Status Register 7
(RLS7) 096h Rec eive SLC-96 ali gnm ent event.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
The T1TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the
T1TFDL regi ster , t he user should c onfigure the DS26514 as shown bel ow:
• T1.TCR2.6 (TSLC96) = 1 Enabl e Transm it SLC-96.
• T1.TCR2.7 (TFDLS) = 0 Sourc e FS bits via T FDL or SLC-96 for matter.
• TCR3.2 (TFM) = 1 D4 framing mode.
• TCR1.6 (TFPT) = 0 Do not “pass through” TSERn F-bits.
The DS26514 will automatically insert the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame.
Data from the T1TSLC1–3 wi ll be insert ed int o the r emaini ng Fs-bit locations of t he SLC-96 mult ifr am e. The stat us
bit TSLC96 located at TLS1. 4 wil l set to indicat e that the SLC-96 dat a l ink buff er has been tr ansmit ted and that the
user should wri te new message data i nto T1TSLC1–3. The host wi ll hav e 9m s after the assertion of TLS1.4 to write
the registers T1TSLC1–3. If no new data i s provided in these registers, t he pr ev ious values wi ll be retr ansmit ted.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 58 of 305
9.9.4.4 Receive SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-
frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36-bits are divided into
alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008.
To enable the DS 26514 to synchroni z e onto a SLC-96 pattern, the fol lowi ng c onfiguration shoul d be used:
• RCR1.5 (RFM) = 1 Set to D4 framing mode.
• RCR1.3 (S Y NCC) = 1 Set to cross-couple Ft and Fs bi ts.
• T1RCR2. 4 ( RS LC96) = 1 Enable S LC-96 synchr onizer.
• RCR1.7 (SY NCT) = 0 Set to minimum sync tim e.
The SLC-96 message bits can be extracted via the T1RSLC1–3 registers. The status bit RSLC96 located at
RLS7.3 is useful for retrieving SLC-96 m essage data. The RSLC96 bit will indicate when the framer has updated
the dat a li nk r egisters T1RSLC1–3 with the latest message data from t he incoming dat a str eam. Once the RSLC96
bit is set, the user wi ll have 9ms (or unt il the next RSLC96 int er r upt) to r etriev e the most recent message data from
the T1RSLC1–3 registers. Note that RSLC96 will not set if the DS26514 is unable to detect the 12-bit SLC-96
alignment pattern.
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.5 T1 Data Link
9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller
The DS26514 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC
function is available only in T1 mode. Table 9-19 shows the regi ster s related t o the transm it bit-ori ented code.
Table 9-19. Register s Related to T1 Tr an sm it BOC
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit BOC Register (T1TBOC) 163h Transmi t bi t-oriented messag e c ode r egister.
Transmit HDLC Control Regist er 2 (THC2) 113h B it to enable sending of transmit BOC.
Transmit Control Regist er 1(TCR1) 181h Determines the sourcing of the F-bit.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
Bits 0 to 5 in the T1TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6)
causes the t r ansmit BOC c ontroll er to imm ediately begin inserting the BOC sequence int o the FDL bit posi tion. The
transm it BOC controller aut omati cally prov ides the abort sequence. BOC m essages wil l be transmi tted as long as
SBO C is set. Note t hat the TFPT (TCR1. 6) control bit m ust be set t o zero f or the BO C m essage to ov erwrite F-bit
information being sampled on TSE Rn.
9.9.5.1.1 To Transmit a BOC
1) Write 6-bit code i nto t he T1TBOC register.
2) Set SBOC bit in THC2 = 1.
9.9.5.2 Receive Bit-Oriented Code (BOC) Controller
The DS26528 fr am ers contai n a BO C generat or on the t ransm it side and a BO C detec tor on t he receive si de. The
BOC f unction i s avail able only in T1, ESF m ode in t he data link bits. Table 9-20 shows the registers rel ated to the
receive BOC operation.
Table 9-20. Registers Related to T1 Receive BOC
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive BOC Control Register
(T1RBOCC)
015h Control s the r ec eiv e BOC f unction.
Receive BOC Register (T1RBOC) 063h Rec eive bit-oriented mes s age.
Receive Latched Status Register 7( RLS7) 096h
Indicates changes to t he r ec eive bit-oriented
messages.
Receive Interrupt Mask Register 7 (RIM7) 0A6h Mask bits f or RBOC for gener ation of
interrupts.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
In ESF mode, the DS26514 continuously monitors the receive message bits for a valid BOC message. The BOC
detect (BD) status bit at RLS7.0 will be set once a valid message has been detected for time determined by the
receiv e BOC fil ter bi ts RBF0 and RBF1 i n the T1RBOCC regi ster . The 6-bit B OC m essage wi ll be avail abl e in t he
RBOC r egister. Once t he user has clear ed the BD bit, it will remai n clear unti l a new BOC is detect ed (or the sam e
BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7.1 is set when a v alid BOC is no
longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the
T1RBOCC register.
The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated
interrupt mas k bits in the RIM7 register.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 60 of 305
9.9.5.3 Legacy T1 Transm it FDL
It is recommended that the DS26514’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 9-21 shows the registers related t o c ont r ol of t he transmit FDL.
Table 9-21. Register s Related to T1 Tr an sm it FDL
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit FDL Regis ter (T1TFDL) 162h FDL code used to i nsert transmit FDL.
Transmit Control Regist er 2 (T1.TCR2) 182h Defines the source of the FDL.
Transmit Latched Status Register 2 (TLS2) 191h Transmit FDL empty bit.
Transmit Inter r upt Mask Regist er 2 (TIM2) 1A1h Mask bit for TFDL empty.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
When enabled with T1.TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the
ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL Register (T1TFDL).
W hen a new v alue is written to the T1TFDL, it will be multi plexed serially (LSB fi rst) int o the proper posit ion in the
outgoi ng T1 dat a stream . Aft er t he f ull ei ght bit s has been shif ted out, the f ramer wi ll signal t he host cont rol ler that
the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. INTB will also toggle low if
enabled v i a TIM2. 4. T he user has 2m s to upd ate t he T1TFDL wit h a ne w v alue. If the T1TFDL i s not updated , t he
old value in the T1TFDL register will be transmitted once again. Note that in this mode, no zero stuffing will be
applied to the FDL data. It is strongly suggested that the HDLC c ontroller be used for FDL messaging applic ations.
In the D4 f raming mode, the framer uses the T1TFDL register t o insert the F s frami ng pattern. To accomplish thi s
the T1TFDL register must be programmed to 1Ch and T1.TCR2.7 should be set to 0 (source Fs data from the
T1TFDL register).
The T1TFDL register c ontains the Facility Data Link (FDL) informati on that is to be i nsert ed on a by te basis i nto the
outgoing T1 dat a stream. The LSB i s tr ansmit ted fir st. In D4 mode, only the lower six bits are used.
9.9.5.4 Legacy T 1 Receive F DL
It is recommended that the DS26514’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 9-22 shows the registers related t o the receive FDL.
Table 9-22. Registers Related to T1 Receive FDL
REGISTER
FRAMER 1
ADDRESSES FUNCTION
Receive FDL Register (T1RFDL) 062h FDL code used to receive FDL.
Receive Latched Stat us Regi ster 7(RLS7) 096h Rec eive FDL ful l bit i s i n this regi ster .
Receive Interrupt Mask Register 7( RIM7) 0A6h Mask bit for R FDL fu ll.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL Register
(T1RFDL). Si nce t he T1RFDL i s 8 bit s in lengt h, it will fill up ev ery 2ms (8 times 250µs). The fr amer will signal an
external controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin will toggle low
indi cati ng that the buff er has fill ed and need s to be r ead. The user ha s 2ms to read thi s data bef or e it i s lost. Not e
that no zero destuffing is applied to the for the data provided through the T1RFDL register. The T1RFDL register
reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing
mode, T1RFDL updates on m ultif r am e boundar ies and reports only the Fs bi ts.
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.6 E1 Data Link
Table 9-23 shows the registers related to E1 data link.
Table 9-23. Registers Related to E1 Data Link
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
E1 Receive Align Fra me Register (E1RAF)
064h
Receive frame alignment register.
E1 Receive Non-Align Frame Register
Register (E1RNAF) 065h Receive non-frame alignm ent regi ster .
E1 Received Si Bi ts of the Align Fr am e
Register ( E1RsiAF)
066h Rec eive Si bits of the frame alignment frames.
Received Si Bits of the Non-Align Frame
Register E1RSiNAF)
067h
Receive Si bits of the non-fr am e alignm ent
frames.
Received Sa4 to Sa8 Bit s Regi ster
(E1RSa4 to E1RSa8)
069h, 06Ah,
06Bh, 06Ch,
06Dh
Receive Sa bits.
Transmit Align Frame Register (E1TAF) 164h Transmit align frame register.
Transmit Non-Align Fram e Register
(E1TNAF)
165h Transmit non-a lign frame register.
Transmit Si Bits of the Align Frame
Register ( E1TSiAF)
166h Transmit Si bits of the fr am e alignm ent fram es.
Transmit Si Bits of the Non-Align Frame
Register ( E1TSiNAF)
167h
Transmit Si bits of the non-frame alignm ent
frames.
Transmit Sa4 to Sa8 Bits Regi ster
(E1TSa4 to E1TSa8)
169h, 16Ah,
16Bh, 16Ch,
16Dh
Transmit Sa4 to Sa8.
E1 Transmit Sa-Bi t Cont r ol Register
(E1TSACR)
114h Transmit sources of S a c ontrol.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 62 of 305
9.9.6.1 Additional E1 Receive Sa- a n d Si-Bit Receive Operat ion (E1 Mode)
The DS26514, when operated i n the E1 m ode, prov ides f or access to both t he Sa and the Si bits vi a two m ethods.
The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves
an expanded version o f the first me thod.
9.9.6.1.1 Internal Register Scheme Based on Double-Fr ame (Method 1)
On t he r ec eiv e si de, t he E1RAF and E1RNAF registers will always report the data as it received in the Sa and Si bit
locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the Receive
Ali gn Frame bit in Rec eive Latched St atus Register 2 (RLS2. 0) will indic ate that the contents of the RAF and RNAF
hav e been updated. T he host c an use the RLS2. 0 bit to k now when to read the E1RAF and E1RNAF register s. The
host has 250µs to retr ieve the data before it is l ost.
9.9.6.1.2 Internal Register Scheme Based on CRC-4 Mu ltifra me (R eceive )
On t he r ec eiv e si de, t her e is a set of eight registers (E1RsiAF, E1RSiNAF, E1RRA, E1RSa4 to E1RSa8) that report
the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in Receive Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for
additional in for mation.
9.9.6.1.3 Internal Register Scheme Based on CRC-4 Mu ltiframe (Transmit)
On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4 to E1TSa8) that, v ia
the E1 Transmit Sa-Bit Control Register (E1TSACR), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1
(TLS1.3). The host can use the TLS1.3 bit t o know when to update these registers. It has 2ms to update the data or
else the old data wi ll be retransmi tt ed. See the r egister descriptions in Section 10 for more information.
9.9.6.2 Sa-Bit Monitoring and Reporting
In addi tion t o the registers out lined abov e, the DS26514 provides status and i nterrupt capabil ity in order to detect
changes in the state of selected Sa bits. The E1RSAIMR register can be used to select which Sa bits are
m onitored for a c hange of state. When a change of state is detect ed in one of the enabled Sa bit positions, a s tatus
bit i s set i n the RLS7 register v i a t he SaXCD bi t ( bit 0). Thi s status bi t c an in t urn be u sed to generate a n i nterr upt
by unmasking RIM7.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SaBITS register at
address 06Eh to determi ne the cur r ent val ue of each Sa bi t.
For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE
regi ster wil l report t he received Sa6 codeword. The codeword m ust be stabl e for a period of three submultiframes
and be dif ferent fr om t he previous stor ed v alue i n order to be updat ed i n this regi ster. See the Sa6CODE register
description for fur ther details on the operation of t his register and the values report ed in it. An additional st atus bi t is
provi ded i n RLS7.1 (Sa6CD) t o i ndic ate if the r eceiv ed Sa6 codeword ha s changed. A m ask bit i s prov i ded f or t his
status bit in RIM7 to allow for i nterr upt generation when enabled.
9.9.7 Maintenance and Alarms
The DS26514 pr ovides extensive functions for alarm detection and generation. It also provides diagnostic funct ions
for monitoring of performanc e and sendi ng of di agnostic i nformation:
• Real-time and l atched status bi ts, interrupts and interrupt mask for transmitter and receiver
• LOS det ection
• RIA det ec tion and generation
• Error counters
• DS0 monitoring
• Milliwatt generation and detecti on
• Slip buffer status for tr ansmit and r ec eiv e
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 63 of 305
Table 9-24 shows som e of the register s related to mai ntenance and alarms.
Table 9-24. Registers Related to Maintenance and Alarms
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive Real-Time Status Register 1 ( RRTS1) 0B0h Real-time rec eiv e status 1.
Receive Interrupt Mask Register 1( RIM1) 0A0h Real-time interrupt mask 1.
Receive Latched Status Register 2 (RLS2) 091h Real-time l atched status 2.
Receive Real-Time Status Register 3 ( RRTS3) 0B2h Real-time rec eiv e status 2.
Receive Latched Status Register 3 (RLS3) 092h Real-time l atched status 3.
Receive Interrupt Mask Register 3 (RIM3) 0A2h Real-time interrupt mas k 3.
Receive Interrupt Mask Register 4 (RIM4) 0A3h Real-time interrupt mas k 3.
Receive Latched Status Register 7 (RLS7) 096h Real-time l atched status 7.
Receive Interrupt Mask Register 7 (RIM7) 0A6h Real-time interrupt mas k 7.
Transmit Latched Status Register 1 (TLS1) 190h Los s of trans mit clock s tatus, etc.
Transmit Latched Status Register 3
(Synchronizer) (TLS3)
192h Los s of frame stat us.
Receive DS0 Monit or Regi ster (RDS0M) 060h Receive DS0 monitor.
Error-Counter Confi gur ation Register (ERCNT) 086h Configur ation of the er r or c ounters.
Line Code V iolation Count Regi ster 1
(LCVCR1) 050h Line code viol ation counter 1.
Line Code V iolation Count Regi ster 2
(LCVCR2) 051h Line code viol ation counter 2.
Path Code Vi olation Count Regi ster 1
(PCVCR1) 052h Rec eive path code vi olation counter 1.
Path Code Vi olation Count Regi ster 2
(PCVCR2) 053h Rec eive path code vi olation counter 2.
Fram es Out of Sync Count Regi ster 1
(FOSCR1) 054h Receive frame out of sync count er 1
Fram es Out of Sync Count Regi ster 2
(FOSCR2) 055h Receive frame out of sync count er 2
E-Bit Count Regi ster 1 ( E1EBCR1) 056h E-bit count register 1.
E-Bit Count Regi ster 2 ( E1EBCR2) 057h E-bit count r egister 2.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 64 of 305
9.9.7.1 Status and Information Bit Operat ion
W hen a part ic ul ar ev ent has occur red (or i s occurri ng), the appr opri at e bit i n one of these regi ster s wil l be set t o a
one. Status bits may operat e in either a l atched or r eal-time fashi on. Some latc hed bits may be enabled to generate
a hardware int er r upt via the INTB signal.
9.9.7.1.1 Real-Time Bit s
Some status bits operate in a real-t ime f ashi on. These bit s are read-only and indicate the present stat e of an alarm
or a condi ti on. Real-time bits will remain stabl e, and vali d during t he host read operation. T he current v alue of t he
int ernal status signal s can be read at any t im e from t he real -time stat us register s without changi ng any the l at ched
status regi ster bits.
9.9.7.1.2 Latched Bits
When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user.
These bits typi c ally r espond on a change-of-state f or an alarm, conditi on, or ev ent; and operate in a read-then-write
f ashion. T he user should read t he v al ue of the desired stat us bit , and t hen wri te a 1 t o that particul ar bit location i n
order to clear the lat ched v alue (wri te a 0 to l ocations not to be cl eared). O nce the bit is cl eared, it will not be set
again until the event has occurr ed again.
9.9.7.1.3 Mask Bits
Som e of the al arms and ev ents can be ei ther m asked or unm asked from the int er r upt pin vi a the Receive I nterr upt
Mask Registers (RIM1, RIM3, RIM4, RIM5, RIM7). When unmasked, the INTB signal will be forced low when the
enabled ev ent or conditi on occur s. The INTB pin will be al lowed to ret urn hi gh (if no other unmasked i nter rupts are
present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that
the latc hed status bit and the INTB pin will clear ev en if the al arm is still present.
Note that some conditions may have multiple status indications. For example, receive loss of frame (RLOF)
provides the follow ing indications :
RRTS1.0
(RLOF)
Real-time indi c ation that t he r ec eiv er is not synchr onized
with incoming dat a str eam . Read-only bit that remai ns hi gh
as long as the condition is present.
RLS1.0
(RLOFD)
Latched indi c ation that t he r ec eiv er has l oss
synchroni z ation si nc e the bit was last cleared. Bit will clear
when writt en by the user, even if the condition i s stil l
present (rising edge det ec t of RRTS1.0).
RLS1.4
(RLOFC)
Latched indi c ation that t he r ec eiv er has reacquired
synchroni z ation si nc e the bit was last cleared. Bit will clear
when writt en by the user, even if the condition i s stil l
present (falling edge detect of RRTS1.0).
DS26514 4-Port T1/E1/J1 Transceiver
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9.9.8 Alarms
Table 9-25. T1 Alarm Criteria
ALARM SE T CRITERIA CLEAR CRITE RIA
AIS
(Blue Alarm) (See Note 1)
When over a 3ms window, 4 or
fewer zer os are rec eived.
When over a 3m s window, 5 or
m or e zeros are received.
RAI
(Yellow
Alarm)
1) D4 Bit 2 Mode
(T1RCR2. 0 = 0)
When bit 2 of 256 consecut ive
channel s i s set to z er o for at l east
254 occurr enc es.
When bit 2 of 256 consecut ive
channel s i s set to z er o for less than
254 occurr enc es.
2) D4 12th F-Bit Mode
(T1RCR2.0 = 1)
(Note: This mode is
also referr ed to as the
“Japanese Y ell ow
Alarm.”)
When the 12th fr ami ng bit i s set to
one for two consecutive
occurrences.
When the 12th fr ami ng bit i s set to
zero for tw o consecutive
occurrences.
3) ESF Mode
When 16 consecutive patter ns of
00FF appear in the FDL.
When 14 or f ewer patterns of 00FF
hex out of 16 possi ble appear i n the
FDL.
4) J1 ESF Mode (J1
LFA)
When 16 consecutive patterns of
FFFF appear in the FDL.
When 14 or f ewer patterns of FFFF
hex out of 16 possi ble appear i n the
FDL.
LOS
(Loss of Signal)
(Note: This alarm is also referr ed to
as receive carrier loss (RCL).)
When 192 consecutive zer os are
received.
When 14 or mor e ones out of 112
possible bit positions are r ec eived
starting with the fi r st one r ec eiv ed.
Not e 1:
The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate
properly in the pres ence of a 10E -3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria
in the DS26514 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit.
Note 2:
The following terms are equivalent:
RAIS = Blue Alarm
RLOS = RCL
RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices)
RRAI = Yellow Alarm
9.9.8.1 Transmi t RAI
Table 9-26 shows the registers related to the transmit RAI ( Y ellow Al arm).
Table 9-26. Registers Related to Transmit RAI (Yellow Alarm)
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Control Regist er 1
(TCR1.TRAI) 181h Enable transmission of RAI.
Transmit Control Regist er 2
(T1.TCR2.TRAIS) 182h Select RAI to be T1 or J1.
Transmit Control Regist er 4
(TCR4.TRAIM) 186h S elect RAI to be norm al or RAI-CI for T1 ESF mode.
Transmit Control Regist er 2
(E1.TCR2.ARA) 182h Selects automatic rem ote al arm generation in E1
mode.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 66 of 305
9.9.8.2 Receive RAI
Table 9-27 shows the registers related to the receiv e RAI ( Y ellow Al arm).
Table 9-27. Registers Related to Receive RAI (Yellow Alarm)
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive Control Register 2
(T1RCR2.RRAIS) 014h Select RAI t o be T1 or J1.
Receive Control Register 2
(T1RCR2.RAIIE) 014h Integration Enable for T1 ES F
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
9.9.8.3 E1 Automatic Alarm Generation
The devi ce can be programm ed to automati cally transmit AI S or remot e alarm . W hen autom atic AIS generation i s
enabled (E1.TCR2.AAIS = 1), the device monitors the receive-side framer to determine if any of the following
conditions are present/loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive
carrier (or signal). If any one (or m or e) of the above conditi ons i s present, then the framer will either for c e an AIS.
W hen autom atic RAI gener ation i s enabled (E1.TCR2.ARA = 1), the f ramer m onitor s the receiv e side t o determi ne
if any of the f ollowing condi tions are prese nt/ loss of r eceiv e f rame synchr oniz ation, AIS al arm (al l ones) rec epti on,
or loss of rec eive carrier (or signal ) or if CRC-4 multif ram e synchronization cannot be found wit hin 128m s of FAS
synchroni zation (if CRC-4 is enabled). If any one (or more) of the abov e conditi ons is present, t hen the f r amer will
transmit a RAI alarm. RAI gener ation conforms to ETS 300 011 and ITU-T G.706 specifications.
Note: It is an illegal stat e to hav e both aut omati c AIS generati on and automatic remot e alarm generation enabled
at t he same tim e.
9.9.8.4 Receive AIS -CI and RAI-CI Detection
AIS-CI is a repetitiv e patt ern of 1.26 second s. It consi sts of 1.11 seconds of an unf ramed all-ones patt ern and 0.15
seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in
lengt h i n whi ch, if t he fir st bi t is num bered bit 0, bit s 3088, 3474 and 5790 are logi cal zer os and all other bits in the
pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The
RAIS-CI bit is set when t he AI S-CI pat tern has been det ect ed and RAIS (RRTS1.2) is set. RAIS-CI is a lat ched bi t
that should be cleared by the host when read. RAIS-CI will continue to set approximately every 1.2 seconds that
the condition is present. The host will need to ‘poll’ the bit, in conjunction with the normal AIS indicators to
determ ine when the condi tion has cleared.
RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially
int erleavi ng 0.99 seconds of “00000000 11111111” (right-to-left ) wit h 90 ms of “00111110 11111111”. The RRAI -
CI bit is set when a bit or iented code of “00111110 111 11111” is detec ted while RRAI (RRTS1.3) is set. T he RRAI-
CI det ector uses the receive BOC fil ter bit s (RBF0 and RBF 1) l ocat ed in RBOCC t o deter mi ne the i ntegr ation tim e
f or RAI-CI detec tion. Li ke RAIS-CI, t he RRAI-CI bit i s latched and shoul d be cl eared by t he host when read. RRA I-
CI will continue to set approx imat ely ev er y 1.1 seconds that t he c ondition is present. The host will need to “poll” the
bit , i n conjuncti on with the normal RAI indi cators to det erm ine when the condition has cleared. It may be usef ul to
enable the 200ms ESF RAI integrat ion tim e with the RAIIE control bit (T1RCR2. 1) in networks that utilize RAI-CI.
9.9.8.5 T1 Receive-Side Digital Milliwatt Code Generation
Receive-side digital milliwatt code generation involves using the T1 Receive Digital Milliwatt Registers
(T1RDMWE1–3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be
ov erwritten wit h a di gital milliwatt pat ter n. The di gital milli watt c ode is an 8-byt e repeati ng patt ern t hat represent s a
1kHz sine wave (1E/0B/0B/1E /9E/8B/8B/9E). Each bit in the T1RDMWEx r egister s represents a part icul ar c hannel.
If a bi t is set to a one, then t he receiv e data in t hat channel will be repl aced wit h the di git al milliwatt code. If a bit i s
set to zer o, no replacement occur s.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 67 of 305
9.9.9 Error Count Registers
The DS26514 contains four counters that are used to accumulate line coding errors, path errors, and
synchroni zati on err ors. Counter update opt ions i nclude one second boundar ies, 42m s (T 1 m ode onl y), 62.5ms (E1
m ode only ) or manuall y. See t he Err or Counter Conf i gurati on Register (ERCNT). W hen updated aut om atic ally, the
user can use the inter r upt f r om the timer to det ermine when to read these registers. A ll four counters will satur ate at
their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count Register
has the potent ial to ov erflow but the bit er r or would have t o ex c eed 10E-2 bef or e this woul d oc c ur .)
The DS26514 can share the one-second timer from Port 1 across all ports. All DS26514 error/performance
counter s can be conf i gured to updat e on the shared one-secon d sourc e or a separate m anual update signal i nput.
See the ERCNT register for more information. By allowing multiple framer cores to synchronously latch their
counter s, the host software can be stream lined to r ead and process performanc e information from multiple spans i n
a more controlled manner.
9.9.9.1 Line Code Violat io n Count Register (LCVCR)
Ei ther bipolar violations or code v iolati ons can be counted. Bi polar viol ati ons are def ined as consecutiv e marks of
the sam e polarity . In T1 m ode, if the B8ZS mode is set for the r eceiv e side, then B8ZS codewords are not counted
as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as
BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU-T O.161. Code violations are
defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be
programm ed t o count BPV s when receiv i ng AMI code and to count CV s when receiv ing B 8ZS or HDB3 code. Thi s
counter inc rement s at all times and is not di sabled by loss of sync c onditi ons. The counter satur ates at 65, 535 and
will not rollover. The bit error rate on an E1 line would have to be greater than 10E-2 before the VCR would
saturate. See Table 9-28 and Table 9-29 for details of exac tly what the LCVCRs count .
Table 9-28. T1 Line Code Violation Counting Options
COUN T EXCESSIVE ZEROS ?
(ERCNT.0)
B8ZS E NABLED?
(RCR1.6)
WHAT IS COUNTED
IN LCVCR1, LCVCR2
No
No
BPVs
Yes
No
BPVs + 16 consecutive zeros
No
Yes
BPVs (B8ZS/HDB3 codewords not c ounted)
Yes
Yes
BPVs + 8 consecutive zeros
Table 9-29. E1 Line Code Violation Counting Options
E1 CODE VIOLAT ION SELECT
(ERCNT.0) WHAT IS COUNTE D
IN LCVCR1, LCVCR2
0
BPVs
1
CVs
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 68 of 305
9.9.9.2 Path Code Viol at ion Count Regi st er ( P CV CR)
In T1 operati on, the Path Code Violati on Count Register records either Ft, Fs, or CRC-6 errors. W hen the receive
side of a f ramer is set to oper ate i n the T1 ESF f raming m ode, PCVCR will record err ors in t he CRC-6 codewords.
When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the
ERCNT. 2 bit, a framer can be programm ed to also report errors in the Fs framing bit position. The PCVCR will be
disabl ed duri ng receiv e loss of synchr oniz ati on (RLOF = 1) c onditi ons. See Table 9-30 f or a det ai led descri ption of
ex ac tly what error s the P CV CR c ounts in T1 operation.
In E1 operation, the Pat h Code Violation Count Register records CRC-4 errors. Since t he m axim um CRC-4 c ount
in a one second peri od is 1000, this counter cannot saturate. The counter is disabled during l oss of sync at eit her
the F A S or CRC-4 level; it will c ontinue to count if loss of multiframe sync oc c ur s at the CAS lev el.
The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and the Path Code Violation
Count Register 2 (PCVCR2) is the least si gnific ant word of a 16-bit counter t hat rec or ds path v iolations (PVs).
Table 9-30. T1 Path Code Viol ation Counting Arrange m ents
FRAMING MODE COUNT Fs ERRORS?
WHAT IS COUNTED IN
PCVCR1, PCVCR2?
D4 No Error s i n the Ft pat tern
D4 Yes Er r or s i n both the Ft and Fs patt er ns
ESF Don’t Care E r r or s i n the CRC-6 codewords
9.9.9.3 Frames Ou t of Sync Count Regist er ( FOSCR)
The FOS CR is used to count the number of mul tif r am es that t he r ec eiv e synchr onizer is out of sync. This number i s
useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events
as described in AT&T publication TR54016. W hen the FOSCR is operated in this mode, it is not disabled during
receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will
count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF
m ode) . When the FO S CR is operated i n this m ode, i t is disabled during receive loss of synchroni z ation ( RLOF = 1)
condi tions. See Table 9-31 for a detai led description of what the FO S CR is capable of counting.
In E1 mode, the FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled
when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or
synchroni zation at either the CAS or CRC-4 m ultiframe lev el. Since the maxim um FAS word error count i n a one-
second period is 4000, this counter cannot saturate.
The F r am es Out of Sync Count Register 1 (FOSCR1) is the most signifi c ant word and the Fram es Out of Sync
Count Register 2 FOSCR2 is the least si gnific ant word of a 16-bit c ounter t hat rec or ds fr am es out of sync.
Table 9-31. T1 Frames Out of Sync Counting Arrangements
FRAMING MODE
(RCR1.5)
COUNT MOS OR F-BIT E RR ORS
(ERCNT.1)
WHAT IS COUNTED
IN FOSCR1, FOSCR2
D4
MOS
Num ber of multif r am es out of sync
D4
F-Bit
Error s i n the Ft pat tern
ESF
MOS
Num ber of multif r am es out of sync
ESF
F-Bit
Error s i n the FPS pat tern
9.9.9.4 E-Bit Count er ( E BCR)
Thi s counter i s only av ailabl e i n E1 mode. The E-Bit Count Regi ster 1 (E1EBCR1) is the m ost signif icant word and
the E-Bit Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block
errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 m ultiframe. These
count r egister s wil l inc rement once each t ime the r eceiv ed E-bit is set to z ero. S inc e the max im um E-bit count in a
one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the
FAS or CRC-4 level; it will continue to count if loss of mul tifram e sync occurs at the CAS level.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 69 of 305
9.9.10 DS 0 Monitoring Function
The DS26514 c an m onitor one DS0 (64kbps) channel in the tr ansmit directi on and one DS0 channel in the receive
dir ec tion at the same time. Table 9-32 shows the regi ster s related to the control of transmit and r ec eiv e DS 0.
Table 9-32. Registers Related to DS0 Monitoring
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit DS0 Channel M onitor Select
Register ( TDS0SEL) 189h Transmit channel to be monitored.
Transmit DS0 Monitor Register
(TDS0M) 1BBh Monitored data.
Receive Channel M onitor Select Register
(RDS0SEL) 012h Receive channel to be mon itored.
Receive DS0 Monit or Regi ster
(RDS0M) 060h Moni tored data.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
In the transmit direc tion the user wil l determine which channel i s to be monit ored by properl y setti ng the TCM[4: 0]
bits in the TDS0SEL register. In the receive direction, the RCM[4:0] bits in the RDS0SEL register need to be
properly set. The DS0 channel pointed to by the TCM[4:0] bits will appear in the Transmit DS0 Monitor Register
(TDS0M) and the DS0 channel pointed to by the RCM[4:0] bits will appear in the Receive DS0 Monitor Register
(RDS0M). The TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate
T1or E 1 c hannel. T1 channels 1 to 24 map to r egister values 0 to 23. E1 channels 1 to 32 map to r egister values 0
to 31. For ex am ple, if DS 0 channel 6 in t he transm i t direc ti on and DS0 chann el 15 i n the rec eiv e di rec tion needed
to be monitored, then t he following v alues would be pr ogr am med int o TDS0SEL and RDS0S E L:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 70 of 305
9.9.11 Transmit Per-Channel Idle Code Generation
Channel data can be replaced by an idle code on a per-channel basi s i n the transmit and receive dir ections.
The Transmit Idle Code Definition Registers (TIDR1–32) are provided to set the 8-bit idle code for each channel.
The T ransmit Channel Idle Code E nable r egister s (TCICE1–4) are used to enabl e idl e code r eplac em ent on a per-
channel basi s.
9.9.12 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The
Receiv e Idle Code Definition Registers (RIDR1–32) are provided to set the 8-bit idle code for each channel. The
Receive Channel Idle Code Enable Registers (RCICE1–4) are used to enable idle code replacement on a per-
channel basi s.
9.9.13 Per-Channel Loopback
The Per-Channel Loopback Enable Registers (PCL1–4) determine which channels (if any) from the backplane
should be repl aced wit h the dat a f rom the r eceive side or i n other words, off of the T1 or E1 li ne. If this l oopback i s
enabled, then t ransm it and receiv e c locks and f ram e syncs m ust be synchroni zed. One m et hod to acc om pli sh this
would be to tie RCLKn to TCLKn and RFSYNCn to TSYNCn. There are no restricti ons on which c hannels can be
looped bac k or on how many channels can be l ooped bac k .
Each of the bit posit ions i n PCL1–4) repr esents a DS0 channel i n t he outgoi ng frame. When t hese bits are set t o a
one, dat a from the corresponding rec eive channel will repl ac e the data on TSERn for that channel.
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mo de Only)
The DS26514 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is
enabled, the data stream presented at TSERn will already have the FAS/NFAS, CRC multiframe alignment word,
and CRC-4 checksum in time slot 0. The user can m odify the Sa-bit positi ons and thi s change i n data content will
be used to modify the CRC-4 checksum. This modification, however, will not corrupt any error information the
ori ginal CRC-4 checksu m may conta in. In th is mode o f operation, TSYNCn must be configured to multifra me mode.
The data at TSERn must be aligned to the TSYNCn signal. If TSYNCn is an input then the user must assert
TSYNCn aligned at the beginning of the multiframe relative to TSERn. If TSYNCn is an output, the user must
multiframe align the data presented to TSERn. This mode is enabled with the TCR3.0 control bit (CRC4R). Note
that the E1 tr ansmit ter must alr eady be enabled for CRC insert ion with the TCR1.0 control bit (TCRC4). S ee Figure
9-16.
Figure 9-16. CRC-4 Recalculate Method
TSERn
XOR
CRC-4
CALCULATOR
EXTRACT
OLD CRC-4
CODE
INSERT
NEW CRC-4
CODE
MODIFY
Sa-BIT
POSITIONS
NEW Sa-BIT
DATA
+
TTIPn/TRINGn
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 71 of 305
9.9.15 T1 Programmable In-Band Loop Code Gene rator
The DS26514 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is ava ilable only in T1 m ode.
Table 9-33. Registers Related to T1 In-Band Loop Code Generator
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Code Defi nition Register 1
(T1TCD1) 1ACh Pattern to be s ent for loop code.
Transmit Code Defi nition Register 2
(T1TCD2)
1ADh Length of the patter n to be sent.
Transmit Control Regist er 3 (TCR3) 183h
TLOOP bit f or contr ol of number of patterns being
sent.
Transmit Control Regist er 4 (TCR4) 186h Lengt h of the code being sent.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
To t r ansmit a pat tern, t he user will load the pat tern to be sent into the Tr ansmit Code Definition Registers (T1TCD1
and T1TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in Transmit Control
Register 4 ( TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern bot h T1TCD1 and T1TCD2 m ust be filled with
the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires T1TCD1 to be filled. Once this is
accomplished, the pattern will be transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally
(unl ess the t ran smit form atter is programm ed t o not insert the F-bit positi on) the fram er will ov erwrit e the r epeati ng
patt er n onc e ev er y 193 bits to all ow the F-bit position to be sent.
As an example, to transmit the standard “loop-up” code for Channel Service Units (CSUs), which is a repeating
patt er n of ... 10000100001..., set TCD1 = 80h, TC0 = 0, TC1 = 0, and TCR3.0 = 1.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 72 of 305
9.9.16 T1 Programmable In-Band Loop Code De tection
The DS26514 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is ava ilable only in T1 m ode.
Table 9-34. Registers Related to T1 In-Band Loop Code Detection
REGISTER FRAMER 1
ADDRESSES FUNCTION
Receive In-Band Code Control Regi ster
(T1RIBCC) 082h Used for selecting l ength of r ec eive in-
band loop c ode r egister.
Receive Up Code Definition Register 1
(T1RUPCD1) 0ACh Receive up code definition register 1.
Receive Up Code Definition Register 2
(T1RUPCD2) 0ADh Receive up code definition r egister 2.
Receive Down Code Definition Regi ster 1
(T1RDNCD1) 0AEh Receive down code def inition register 1.
Receive Down Code Definition Regi ster 2
(T1RDNCD2) 0AFh Receive up code definition regi ster 2.
Receive Spare Code Regist er 1 (T1RSCD1) 09Ch Rec eive spare code regi ster 1.
Receive Spare Code Regist er 2 (T1RSCD2) 09Dh Rec eive spare code regi ster 2.
Receive Real-Time Status Register 3 ( RRTS3) 0B2h Real-time loop code det ec t.
Receive Latched Status Register 3 (RLS3) 092h Latched l oop c ode detect bits.
Receive Interrupt Mask Register 3 (RIM3) 0A2h Mask for latched loop code detect bit s.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and
“loop-down” code detection. The user will program the codes to be detected in the Receive Up Code Definition
Registers 1 and 2 (T1RUPCD1 and T1RUPCD2) and the Receive Down Code Definition Registers 1 and 2
(T1RDNCD1 and T1RDNCD2) re gisters and t he length of each patt ern wil l be selected vi a the T1RIBCC register.
There is a third detector (spare) and it is defined and controlled via the T1RSCD1/T1RSCD2 and T1RSCC
regi sters. W hen detecti ng a 16-bit pattern both receive code defi nition registers are u sed together to f orm a 16-bit
register. For 8-bit patterns, both receiv e code definition registers will be filled with the same value. Detection of a
1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requi res the first receiv e code definiti on register t o be fill ed. The f ram er
will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as
10E–2. The detector s can handle bot h F-bit inserted and F-bit overwrit e patterns. W riting t he least signif icant byte
of receive code definition register resets the integration period for that detector. The code detector has a nominal
integration per iod of 48ms. Hence, after about 48ms of receivi ng a v alid c ode, the proper status bit (LUP , LDN, and
LSP) will be set to a one. Note that r eal-time status bits, as well as l atched set and c lear bits are available for LUP,
LDN and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommend that the
soft ware poll the f ramer ev ery 50m s to 100m s until 5 seconds ha s elapsed t o ensure that the c ode i s conti nuously
present.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 73 of 305
9.9.17 Framer Payload Loopbacks
The f r am er, payl oad, and remot e loopbac k s are controll ed by RCR3.
Table 9-35. Register Related to Framer Payload Lo op ba cks
RECEI V E CONTROL
REGISTER 3 (RCR3)
FRAMER 1
ADDRESSES FUNCTION
Fram er Loopbac k 083h Transmit data output from the framer is looped back to the receiver.
Payload Loopback 083h The 192-bit payload data is looped back to the transmitter.
Rem ote Loopback 083h Data rec overed by the receiver is looped bac k to the transmitter.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 74 of 305
9.10 HDLC Controllers
There ar e two HDLC C ontr oll ers av ail abl e f or eac h port of the DS26514. HDLC-64 i s the d ef ault HDLC c ontrol l er,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the
DS26514 beginning with die revision B1. (Note: Older DS26514 die revisions do not hav e this feature so check
the device errata) . The followi ng tabl e describes the features av ailabl e for each.
Table 9-36. HDLC-64/HDLC-256 Controller Features
HDLC
CONTROLLER FIFO DEPTH
(BYTES) MAP TO FDL MAP TO
Sa BITS MAP TO
SINGLE DS0
MAP TO
MULTIPLE
DS0s
HDLC-64
64
Yes
Yes
Yes
No
HDLC-256
256
Yes
Yes
Yes
Yes, up to 32
9.10.1 HDLC-64 Controller
This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
Mode) or the FDL (T1 Mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user c an select any specific bits withi n the t ime slot (s) t o assign t o the HDLC-64 control ler, as wel l as
specif ic Sa bi ts (E1 Mode)
The HDLC-64 controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detect s abort sequence s, stuf f s and de-stuf f s zeros, and by te al i gns to the data stream . The 64-byt e buff ers in t he
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
The registers rel ated to the HDLC are di spl ay ed in the fol lowing table.
Table 9-37 shows the registers related to the HDLC.
Table 9-37. Registers Related to the HDLC-64
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive HDLC-64 Control Register
(RHC)
010h M apping of the HDLC to DS0 or FDL, Sa Bit s
Receive HDLC-64 Bit Suppress
Register ( RHBSE) 011h Rec eive HDLC bit suppression Register
Receive HDLC-64 FIFO Cont r ol
(RHFC)
087h
Determ ines the watermark of the Rec eiv e
HDLC FIFO
Receive HDLC-64 Packet Bytes
Avail able Register (RHPBA) 0B5h
Tells the user how m any by tes are av ailable in
the Receive HDLC FIFO
Receive HDLC-64 FIFO Register ( RHF)
0B6h
The actual FIFO data
Receive Real-Time Status Regi ster 5
(RRTS5)
0B4h Indicat es the FIFO stat us
Receive Latched Status Register 5
(RLS5)
094h Latched St atus
Receive Interrupt Mask 5 (RIM5) 0A4h
Interrupt Mas k for interrupt generation for the
Latched S tatus
Transmit HDLC-64 Cont r ol 1(THC1)
110h
Mi sc T r ansmit HDLC Control
Transmit HDLC-64 Bit Suppress
(THBSE)
111h
Transmit HDLC Bit Suppr ess f or bits not to be
used
Transmit HDLC-64 Cont r ol 2 (THC2) 113h
HDLC to DS0 c hannel sel ec tion and other
control
Transmit HDLC-64 FI FO Control
(THFC)
187h Used to c ontrol the T r ansmit HDLC FIFO
Transmit HDLC-64 Status (TRTS2) 1B1h
Indicates the Real-Time Status of the Transmit
HDLC FIFO
Transmit HDLC-64 Latched Status
191h
Indicates the FIFO stat us
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 75 of 305
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
(TLS2)
Transmit Inter r upt Mask Regist er 2
(TIM2)
1A1h Interrupt Mask for the Latched S tatus
Transmit HDLC-64 FIFO Buffer
Available
(TFBA)
1B3h Indicat es the num ber of bytes t hat can be
written into t he Transmit FI FO
Transmit HDLC-64 FIFO (THF)
1B4h
Transmit HDLC FIFO
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
9.10.1.1 HDLC-64 FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-64 FIFO Control (RHFC) and
Transmit HDLC-64 FIFO Contr ol (THFC) register s. The FIFO Control r egister s set the watermark s for the FIFO.
When the receive FIFO fills abov e the high watermark, the RHWM bit (RRTS5.1) will be set. RHW M and TLWM
are real-time bits and wil l remain set as l ong as the FI FO ’s wri te point er is above the watermark. W hen the transmit
FIFO empties below the low watermark, the TLWM bit in the TRTS2 register will be set. TLWM is a real-time bit
and will remain set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition
can al so cause an interrupt v ia the I NTB pin.
If the receiv e HDLC FIFO does ov errun, t he current packet bei ng processed is dropped and the receiv e FIFO will
be em ptied . The pack et status bits in RRTS5 and RLS5.5 (ROV R) indi c ate an overr un.
9.10.1.2 Receive P acket Byt es Avail able
The l ower 7 bits of the Receiv e HDLC Packet Bytes Avail able Register (RHPBA) indic ates the num ber of bytes (0
to 64) that can be r ead from the rec eive FIFO. T he v alue indicat ed by thi s register informs the host as to how many
bytes can be read f rom the receiv e FIFO wi thout goi ng past the en d of a message. T his v alue wil l ref er to one of
four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete
packet . After readi ng the number of bytes indic ated by this register the host t hen checks the HDLC status registers
for detailed m essage status.
If the value i n the RHPBA r egister ref ers to the begi nning porti on of a messag e or cont inuati on of a message, then
the MSB of the RHPBA register will ret urn a val ue of 1. This indicat es that the host can saf ely read the number of
bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register
since t he pac k et has not yet termi nated (successfully or otherwise).
9.10.1.3 HDLC-64 S t at us and Informat ion
RRTS5, RLS5, and TLS2 prov ide status information for the HDLC c ontrol ler. When a par ticular event has occurred
(or is occurring), the appropriate bit in one of these register s will be set to a one. Some of the bit s i n these register s
are latched and some are real-time bits that are not latched. This section contains register descriptions that list
which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to a
one, it will remain set until the user reads and clears that bit. The bit will be cleared when a 1 is written to the bit
and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous
condi tions that are oc c ur ri ng and the hi stor y of t hese bits i s not latched.
Lik e the other latched status re gisters, the user will f ollow a read of the status bit wit h a write. The byt e writ ten to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
aff ected by writing to t he stat us regi ster). The user wil l writ e a byte to on e of t hese register s, wit h a one in th e bit
positions he or she wishes to cl ear and a zer o in the bit posit ions he or she does not wish t o c lear.
The HDLC status registers RLS5 and TLS2 have the ability to initiate a hardware interrupt via the INTB output
signal . Each of the ev ents in thi s regi ster can be either m asked or u nmasked f rom the i nterrupt pin vi a the HDLC
interrupt mask regi ster s RIM5 and TIM2. Interr upts wi ll force the INTB si gnal low when the ev ent occur s. The INT B
pin will be allowed to ret urn high (if no other int errupts are present) when the user reads the ev ent bit that caused
the inter r upt to oc c ur .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 76 of 305
9.10.1.4 Receive HDLC-64 Example
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC messages, the host c an c hoos e to be interr upt driven, to poll to desi r ed status registers, or a
combination of polling and interrupt processes can be used. An example routine for using the DS26514 HDLC
receiver is given in Figure 9-17.
Figure 9-17. HDLC Message Receive Example
Res et Rec eive
HDLC Controller
(RHC.6)
Configur e R eceive
HDLC Controller
(RHC, RHBSE, RHFC)
Start New
Mess age Buf f er
Enable Interrupts
RPE and RHW M
Start New
Mess age Buf f er
Interrupt?
Read R egis ter
RHPBA
Read N Bytes From
Rx HDLC FIFO (RHF)
N = RHPB A[5..0]
MS = 1?
(MS = RHPBA[7])
NO
YES
NO
YES
Read RR TS5 for
Packet Status (PS2..0 )
Take appr o pri a te act i on
No Acti on Requi r ed
Work Another Process.
Read N Bytes From
Rx HDLC FIFO (RHF)
N = RHPB A[5..0]
Start New
Mess age Buf f er
Start New
Mess age Buf f er
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 77 of 305
9.10.2 Transmit HD LC-64 Controller
9.10.2.1 FIFO Information
The Transmit HDLC FIFO Buffer Availabl e Register (TFBA) indicat es the num ber of bytes that c an be writ ten into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
duri ng the read cycl e.
9.10.2.2 Tran smit HDLC-64 E xampl e
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
regi sters, or a combinati on of polli ng and int errupt processes can be used. Figure 9-18 shows an exam ple routi ne
for using the DS26514 HDLC receiv er .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 78 of 305
Figure 9-18. HDLC Message Transmit Example
9.10.3 HDLC-256 Controller
Thi s dev i ce has an enhanced HDLC cont rol ler that can be mapped i nto up t o 32 tim e slot s, or Sa4 t o Sa8 bi ts (E1
Mode) or the FDL (T1 Mode). This HDLC controller has a 256-byte FIFO buffer in both the transmit and receive
paths. T he user can select any spec if ic bi ts withi n the t im e slot (s) to assi gn to t he HDLC-256 c ont rol l er, as well as
specif ic Sa bi ts (E1 Mode)
Reset Tr ans mit
HDLC Controller
(THC.5)
Configur e Tra nsm i t
HDLC Controller
(THC1,THC2,THBSE,THFC)
TLWM
Interrupt?
Enable TM END
Interrupt
No Acti on Requi r ed
Work Another Process
Enable TLWM
Interrupt and
Verify TLWM Clear
Read TFBA
N = T FBA[6..0]
Push Me ssage Byte
into Tx HDLC FIFO
(THF)
Last Byte of
Message? YES
NO
Set TEOM
(THC1.2)
Push Last Byt e
into Tx FIFO
Loop N
TMEND
Interrupt?
YES
Read TUDR
Status Bit
TUDR = 1
YES
Disable TMEND Interrupt
Res e nd Me ss ag e
Disable TMEND Interrupt
Prepare New
Message
YES
NO
NO
NO
A
A
A
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 79 of 305
The HDLC-256 controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and de-stuffs zeros, an d by te aligns to the data str eam. The 256-byte buffers in the
HDLC-256 controll er are large enou gh to allow a f ull PRM to be receiv ed or transm itted without host i nterventi on.
They are also large enough to store an entire frame’s worth of data before requiring host intervention. The
regi ster s related t o the HDLC are displ ay ed in the follow ing table.
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive eXpansion P or t Control
Register ( RXPC)
08Ah
Mappi ng of the HDLC to tim esl ots or F DL, Sa
Bits
Receive HDLC-256 Channel S elec t
Register s (RHCS1-4)
0DCh-0DFh
Sel ec tion of timeslot s to map data to t he HDLC
port
Receive HDLC-256 Bit Suppress
Register ( RHBS)
08Dh Rec eive HDLC bit suppression Register
Receive HDLC-256 Control Register 1
(RH256CR1)
1510h Rec eive Miscellaneous Contr ol
Receive HDLC-256 Control Register 2
(RH256CR2)
1511h Rec eive HDLC FIFO Data Level Av ailable
Receive HDLC-256 Status Regi ster
(RH256SR)
1514h Indic ates the FIFO stat us
Receive HDLC-256 FIFO Dat a
Registers (RH256FDR1, RH256FDR2)
151Ch, 151Dh The act ual FI FO data
Transmit eXpansion Port Control
Register ( TXPC) 18Ah
Mappi ng of the HDLC to tim esl ots or F DL, Sa
Bits
Transmit HDLC-256 Channel Select
Register s (THCS1-4)
1DCh-1DFh
Sel ec tion of timeslot s to map data from the
HDLC port
Transmit HDLC-256 Bit Suppr ess
(THBS) 18Dh
Transmit HDLC Bit Suppr ess f or bits not to be
used
Transmit HDLC-256 Cont r ol Register 1
(TH256CR1)
1500h Transmit Miscellaneous Control
Transmit HDLC-256 Control Register 2
(TH256CR2) 1501h
Indicates the num ber of bytes t hat can be
written into t he Transmit FI FO
Transmit HDLC-256 FI FO
(TH256FDR1, TH256FDR2)
1502h, 1503h Transmit HDLC FIFO
Transmit HDLC-256 Stat us
(TH256SR1, TH256SR2)
1504h, 1505h
Indicates the Real-Time Status of the Transmit
HDLC FIFO
Note: Th e addr esses sh own ab ov e are f or Framer 1.
9.10.3.1 HDLC-256 FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-256 Control Register 2
(RH256CR2) and Transmit HDLC-256 Control Register 2 (TH256CR2). The FIFO Control registers set the
watermarks for the FIFO.
When the receive FIFO fills above the data available level, the RHDA bit (RH256SR.0) will be set. RHDA and
THDA are real-time bits and will remain set as long as the FIFO’s write pointer is above the data available level.
When the transmit FIFO empties below the data storage av ailable level , the THDA bit in the TH256SR1 register
will be set. THDA is a real-time bit and will remain set as long as the t r ansmit FI FO ’s writ e pointer is bel ow the level
setting. If enabled, thi s condition can also cause an interrupt v ia the INTB pin.
If a packet start is receiv ed while the receive FIFO is full, the data is discarded and a FIFO overflow condition is
declared (RH256SRL.7). If any other packet data is received while full, the current packet being transferred is
marked with an abort indication, and a FIFO overflow condition is declared. Once a FIFO overflow condition is
decl ared, the Receiv e FIF O will discard incomi ng data until a packet start is receiv ed whil e the Receiv e FIFO has
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 80 of 305
sixteen or more bytes available for storage. If the Receive FIFO is read while the FIFO is empty, the read is
ignor ed, and an i nvalid dat a indic ation giv en.
The Transmit FIFO accept s data f r om the host unt il full. If the T ransm it FIFO i s wri tt en to whil e the FIFO i s f ull, t he
write is ignored, and a FIFO overflow condition is declared. If the Transmit HDLC Controller attempts to read the
Transmit FIFO whil e it is empty, a FIFO underf low condition is decl ar ed.
The transmit FIFO fill level is available real-time in the Transmit HDLC-256 Status Register 2 (TH256SR2),
indicati ng the number of bytes t hat can be wri tt en into the t r ansmit FIFO.
9.10.3.2 HDLC-256 S t at us And Informat ion
RH256SRL, RH256SR, TH256SR1, TH256SR2, and TH256SRL provide status information for the HDLC
contr oller. W hen a particular ev ent has occurred (or i s occurring), the appropriate bit in one of these register s wil l
be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched.
Thi s section c ontai ns register descri pt ions that li st whi ch bi ts are l atched and which ar e real -tim e. With the l atched
bits, when an event oc c ur s and a bi t is set to a one, it will remain set until the user reads and clears that bit . The bit
will be cleared when a ‘1’ is written to the bit and it will not be set again until the event has occurred again. The
real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not
latched.
Lik e the other latched status re gisters, the user will f ollow a read of the status bit with a writ e. The byte written to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
aff ected by writing to t he stat us regi ster). The user wil l writ e a byte to on e of t hese register s, wit h a one in th e bit
positions he or she wishes to cl ear and a zero in the bit posit ions he or she does not wish to clear.
The HDLC stat us registers RH256SRL and TH256SRL have the abili ty to initi ate a hardware i nterr upt via the INTB
output signal . Each of the ev ents in this register can be ei ther m asked or unm asked f rom the interrupt pin via the
HDLC Int errupt Enabl e Register s TH256SRIE and RH256SRIE . Int errupt s wil l force t he INT B signal low when the
event occurs. The INTB pin will be allowed to return high (if no other interrupts are present) when the user reads
the event bi t that caused the interrupt t o oc c ur.
9.10.3.3 Receive HDLC-256 Exampl e
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC messages, the host can chose to be i nterrupt dr iven, or to poll to desi r ed status regist ers, or
a combination of polling and interrupt processes may be used. An example routine for using the DS26514 HDLC
receiver is given in the fo llowing figure.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 81 of 305
Figure 9-19. Receive HDLC Example
Configure Receive
HDLC-256 Controller
(RH256CR1,2)
Read RH256FDR1,2
until end of packet
reached
Read RH256FDR1, 2;
N = 8xRDAL -1
Read RH256SRL
exit
Enable Interrupts
(RHDAIE, RPEIE)
Reset FIFO
(RH256CR1.RFRST)
INTB Active?
RHDAL Set? RPE Set? exit
N = 0 ? exit
Read RH256FDR1, 2;
N = N -1
YES
NO
NONO
NO
YES
YES
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 82 of 305
9.10.3.4 Tran smit HDLC-256 E xampl e
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes may be used. An example routine for using the
DS26514 HDLC receive r is given in the following figure.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 83 of 305
Figure 9-20. HDLC Message Transmit Example
Configure Transmit
HDLC-256 Controller
(TH256CR1,2)
Write TH256FDR1, 2;
N = 8xTDAL -1
Read TH256SRL
exit
Enable Interrupt
(THDA)
Reset FIFO
(TH256CR1.TFRST)
INTB Active?
THDAL Set? exit
N = 0 ?
Write TH256FDR1, 2;
N = N -1
YES
NO
NO
NO
YES
YES exit
Packet End? YES exit
NO
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 84 of 305
9.11 Power-Supply Decoupling
Table 9-38. Recommended Supply Decoupling
SUPPLY PINS
DECOUP LI NG CAPACIT ANCE
NOTES
DVDD33 / DV S S
0.01
µ
F + 0 .1
µ
F + 1
µ
F + 10
µ
F
DVDDI8 / DVSS
0.01
µ
F + 0 .1
µ
F + 1
µ
F + 10
µ
F
ATVDD[4 :1] /
ATVSS[4 :1] 0.1µF (x4) + 1µF (x 2) + 10µF
It is recommended to use one 0.1µF cap for each
ATV DD/ATVSS pair (4 total) , one 1µF for every
two ATVDD/ATVSS pair s (2 total) , and one 10µF
capacitor for the analog transmit supply pins.
These capacitors should be located as cl ose to the
intended power pins as pos si ble.
ARVDD[4 :1] /
ARVSS[4 :1] 0.1µF (x4) + 1µF (x 2) + 10µF
It is recommended to use one 0.1µF cap for each
ARVDD/ A RV S S pai r (4 total) , one 1µF for every
two ARVDD/A RV S S pair s (2 t otal), and one 10µF
capacitor for the analog receive supply pins. These
capacitors should be located as close to the
intended power pins as pos si ble.
ACVDD / ACVSS
0.1µF + 1µF + 10µF
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 85 of 305
9.12 Line Interface Units (LIUs)
The DS26514 has four identical LI U transmit and receiv e front -ends for each of the four framers. E ac h LIU contains
three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock
and data recovery; and the jitter attenuator. The DS26514 LIUs can switch between T1 or E1 networks without
changing any external components on either the transmit or receive side. Figure 9-21 shows a recommended
circuit for software selected termination with protection. In this configuration the device can connect to 100Ω T1
twisted pair, 110Ω J 1 twisted pair, 75Ω or 120Ω E1 twisted pair without addi tional c om ponent changes. The signals
between the framer and LIU are not accessible by the user, thus the framer and LIU cannot be separated. The
transmitt er s have fast high-impedance capability and can be individually powered down.
The DS26514’s transmit waveforms meet the corresponding G.703 and T1.102 specifications. Internal software-
selectable transmit termination is provided for 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1 twisted pair
and 75Ω E1 coaxial appli c ations. The receiver can connec t to 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1
twisted pai r, and 75Ω E1 coaxial. The receive LI U can f uncti on with a receiv e signal attenuation of up to 36dB for
T1 mode and 43dB f or E1 mode. The r eceiver sensit iv ity i s programm able from 12dB to 43dB of cable loss. Also a
m onitor gain setting c an be enabled t o pr ov ide 14dB , 20dB, 26dB , and 32dB of resistive gai n.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 86 of 305
Figure 9-21. Network Connection—Longitudinal Protection
DS26514
TTIPn
TRINGn
RTIPn
RRINGn
S1
S2
S3
S4
S5
S6
S7
S8
T1
T2
T3
T4
2:1
1:1
F1
F2
F3
F4
TX
TIP
TX
RING
RX
TIP
RX
RING
560 pF
R
T
1 uF
NAME DESCRIPTION PART MANUFACTURER NOTES
F1 to F4
1.25A Sl ow Bl ow Fuse
SMP 1.25
Bel Fuse
5
1.25A Sl ow Bl ow Fuse
F1250T
Teccor Electronics
5
S1, S2
25V (max ) Transi ent Suppressor
P0080SA M C
Teccor Electronics
1, 5
S3, S 4, S5,
S6
180V (max ) Transi ent Suppressor P1800SC MC Teccor Electronics 1, 4, 5
S7, S8
40V (max ) Transi ent Suppressor
P0300SC MC
Teccor Electronics
1, 5
T1 and T 2
Transformer 1:1CT and 1: 2CT (3.3V , SMT)
PE-68678
Pul se Engineeri ng
2, 3, 5
T3 and T 4
Dual Common-Mode Choke (SMT )
PE-65857
Pul se Engineeri ng
5
RT Termination Resi stor ( 120Ω, 110Ω, 100Ω, o r
75
Ω
)
— — —
Not e 1: Changing S7 and S8 to P1800SC devices provides symmetrical voltage suppresion between tip, ring, and ground.
Not e 2:
The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated
f rom oth er circuit lin es b y at leas t 15 0 mi l s . Th e ar ea u nd er this p or ti o n of th e circ uit shoul d n ot c ont ai n power plan es .
Not e 3: Som e T1 ( n ev er in E1) app licati ons s our ce or s i nk pow er fr om th e n etwork-side center taps of the Rx/Tx transformers.
Not e 4: The ground trace connected to the S3/S4 pair and the S5/S6 pair should be at least 50 mils wide to conduct the extra current
from a longitudinal power-cross event.
Not e 5:
Alternative component recommendations and line interface circuits can be found by contacting
telecom.support@dalsemi.com or in Applicatio n Note 324, which is a vai labl e at www.maxim-ic.com/AN324.
Not e 6:
The 1µF capacitor in series with TTIPn is only necessary for G.703 clock sync applications.
Not e 7:
The 560pF on TTIPn/TRINGn must be tuned to your application.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 87 of 305
9.12.1 LIU Ope ration
The anal og AMI/ HDB3 wav ef orms off of the E1 lines or t he AMI/B8ZS wavef orm off of the T 1 li nes are transf ormer
coupled into the RTIPn and RRINGn pins of the DS26514. The user has the option to use internal termination,
software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data f r om the analog si gnal and pa sses i t t hrough t he jitt er att enuation m ux. T he DS26514 cont ains an act iv e fil ter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry al so is co nfi gurabl e f or v arious m onit or appli cati ons. The dev i ce has a u sable rec eiv e sen sitiv ity of 0dB to
-43dB for E1 and 0dB to -36dB for T 1, which allows the dev ice to oper ate on 0.63mm ( 22AWG) cables up to 2.5k m
(E1) and 6k feet ( T1) in length. Dat a input t o the trans m it side of t he LIU is sent via the jitter attenuation mux to the
wav e shaping ci rcuitr y and line driver. The DS26514 wi ll drive the E1 or T1 line f rom the TTI Pn and TRINGn pins
v ia a c oupli ng transformer. The line driv er c an handle both CEPT 30/ ISDN-PRI lines for E 1 and long-haul ( CS U) or
short-haul ( DS X-1) lines for T1. The regi ster s that control the LIU operation are shown in Table 9-39.
Table 9-39. Registers Related to Control of the LIU
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Global Transceiver Clock Cont r ol Register 1
(GTCCR1) 00F3h MP S sel ec tions, backplane clock
selections.
Global LIU Sof tware Reset Regi ster 1 ( GSRR1) 00F6h Software reset cont r ol for the LIU.
Global LIU Interrupt Status Register 1 (GLISR1) 00FBh Interrupt status bit f or each of the four
LIUs.
Global LIU Interrupt Mask Register 1 (GLIMR1) 00FEh Interrupt mas k register for the LIU .
LIU T r ansmit Rec eive Control Regist er (LTRCR) 1000h T1/ J 1/E1 selection, out put three-state, loss
criteria.
LIU T r ansmit Impedanc e and P ulse Shape
Sel ec tion Register (LTIPSR) 1001h Transmit pulse shape and impedance
selection.
LIU Maintenance Contr ol Register (LMCR) 1002h Transmit maintenance and jitter
att enuation c ontrol register.
LIU Real St atus Register (LRSR) 1003h LIU real-tim e status register.
LIU Status Interrupt Mask Register (LSIMR) 1004h LI U m ask registers based on latched
st at us bits.
LIU Lat c hed S tatus Regi ster (LLSR) 1005h LIU latched stat us bi ts related to loss, open
circuit, etc.
LIU Receive Signal Lev el Register (LRSL) 1006h LIU receive signal leve l indicator.
LIU Receive Impedance and S ensi tivity Monitor
Register ( LRISMR) 1007h LIU im pedanc e m atch and sensit ivity
monitor.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 4 for Framers 2 to 4.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 88 of 305
9.12.2 Transmitter
NRZ data arriv es f rom the f ram er transmitt er; t he data is encoded with HDB 3 or B8Z S or AMI. The encoded dat a
passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to
generate transmit waveforms compliant with T1.102 and G.703 pul se tem plates.
A line driver is used to driv e an internal matched impedance circuit for provision of 75Ω, 100Ω, 110Ω, and 120Ω
terminations. A 560pF capacitor should be placed between TTIPn and TRINGn for each transmitter for proper
operation, as noted in Figure 9-21. T he transmit ter couples to the E 1 or T1 transmit twi sted pair (or c oax ial c able in
some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper waveforms, the
transformer used must meet the specifications listed in Table 9-41. The transmitter requires a transmit clock of
2.048MHz for E1 or 1.544MHz for T1/J1 oper ation.
The DS26514 drivers have a short-circuit and open-circuit detection driver-fail monitor. The TXENABLE pin can
high im pedance the transmitter outputs for protection switching. The indiv idual transmitters can also be placed in
high impedance through register settings. The DS26514 also has functionality for powering down the transmitters
individually. The relevant telecomm unic ations specific ation com pliance is shown i n Table 9-40.
Table 9-40. Telecommunications Specification Compliance for DS26514 Transmitters
TRANSMITTER FUNCTION
TELECOMMUNICATIO NS COMPLIANCE
T1 T elec om Pul se Tem plate Compli anc e ANSI T1.403
T1 T elec om Pul se Tem plate Compli anc e ANSI T1.102
Transmit Electrical Character istics for E1
Transmission and Return Loss Com pliance ITU-T G.70 3
Table 9-41. Transfor mer Specifi cati ons
SPECIFICATION RECOMMENDED VALUE
Turns Ratio 3.3V Applicat ions
1:1 (r ec eive) and 1:2 (transmit) ±2%
Primary Inductance
600µH mi nim um
Leakage Induc tance
1.0
µ
H maximum
Int er twi ning Capacit anc e
40pF maximum
Transmit Trans for mer DC
Resistance Primary (Device Side) 1.0Ω maximum
Secondary
2.0
Ω
maximum
Receive Transformer DC
Resistance Primary (Device Side)
1.2
Ω
maximum
Secondary 1.2Ω maximum
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 89 of 305
9.12.2.1 Transmit-Line Pulse Shapes
The DS26514 t ransm itt ers can be selec ted indiv iduall y to m eet the pulse tem plates f or E1 and T1/J 1 modes. The
T1/ J1 pulse templ ate i s shown i n Figure 9-22. The E1 pul se tem plate is shown in Figure 9-23. The transmit pul se
shape can b e configured for each LIU on an indiv idual basi s. T he LIU transm it impedance sel ection r egisters can
be used to sel ect an int ernal transmit termi nating impedanc e of 100Ω f or T1, 110Ω for J1 mode, 75Ω or 120Ω for
E1 mode or no internal termination for E1 or T1 mode. The transmit pulse shape and terminating impedance is
selected by LTIPSR registers. The pulse shapes will be compliant to T1.102 and G.703. Pulse shapes are
measured for compliance at the appropriate network interface (NI). For T1 long haul and E1, the pulse shape is
m easured at the far end. F or T1 short haul, the pulse shape i s measured at the near end.
Figure 9-22. T1/J1 Transm it Pul se Templat es
1.2
0
-
0.1
-
0.2
-
0.3
-
0.4
-
0.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
-
500
-
300
-
100
0
300
500
700
-
400
-
200
200
400
600
100
TIME (ns)
NORMALIZED AMPLITUDE
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
-
0.77
-
0.39
-
0.27
-
0.27
-
0.12
0.00
0.27
0.35
0.93
1.16
-
500
-
255
-
175
-
175
-
75
0
175
225
600
750
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-
0.07
0.05
0.05
-
0.77
-
0.23
-
0.23
-
0.15
0.00
0.15
0.23
0.23
0.46
0.66
0.93
1.16
-
500
-
150
-
150
-
100
0
100
150
150
300
430
600
750
-
0.05
-
0.05
0.50
0.95
0.95
0.90
0.50
-
0.45
-
0.45
-
0.20
-
0.05
-
0.05
UI
Time
Amp.
MAXIMUM CURVE
UI
Tim
e
Amp.
MINIMUM CURVE
-
0.77
-
0.39
-
0.27
-
0.27
-
0.12
0.00
0.27
0.34
0.77
1.16
-
500
-
255
-
175
-
175
-
75
0
175
225
600
750
0.05
0.05
0.80
1.20
1.20
1.05
1.05
-
0.05
0.05
0.05
-
0.77
-
0.23
-
0.23
-
0.15
0.00
0.15
0.23
0.23
0.46
0.61
0.93
1.16
-
500
-
150
-
150
-
100
0
100
150
150
300
430
600
750
-
0.05
-
0.05
0.50
0.95
0.95
0.90
0.50
-
0.45
-
0.45
-
0.26
-
0.05
-
0.05
UI
Time
Amp.
MAXIMUM CURVE
UI
Time
Amp.
MINIMUM CURVE
DSX
-
1 Template (pe
r ANSI T1.102
-
1993)
DS1 Template (per ANSI T1.403
-
1995)
Figure 9-23. E1 Transm it Pulse Templa tes
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 90 of 305
0
-0.1
-0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
TIME (ns)
SCALED AMPLITUDE
50 100 150 200 250-50-100-150-200-250
269ns
194ns
219ns
(in 75 ohm syst em s, 1.0 on th e s cale = 2.37 Vpeak
in 120 ohm sy s tems, 1.0 on the s c ale = 3.00Vpeak)
G.703
Template
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 91 of 305
9.12.2.2 Tran smit G.703 Sect ion 10 Synchroniz at io n Signal
The DS26514 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU Transmit
Impedance and Pulse Shape Selection Register (LTIPSR). This mode also requires a 1µF blocking capacitor
between T TI Pn and the t ransf ormer . Additi onall y, the f oll owing regi sters shoul d set t o cent er the pul se to m eet the
pulse templat e:
If c onfiguring for E1 75Ω m ode, set register address 0x1229 = 0xF8.
If c onfiguring for E1 120Ω m ode, set register addresses 0x1229 = 0xF8 and 0x122D = 0x09.
9.12.2.3 Tra nsmit Power-Down
The i ndiv idual transmit ters can be po wered do wn by sett i ng the TPDE bi t i n the LI U Mai ntenance Cont rol Register
(LMCR). Note that powering down the transm it LIU results in a high-impedance stat e for the cor responding TTI Pn
and TRI NGn pi ns.
When transmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference.
Data i nput fr om the framer is ignored. AI S can be sent by setti ng a bit in the LMCR register. Transmit all ones will
also be sent if the correspondi ng r ec eiver goes i nto LOS state and t he ATAIS bit is set in t he LMCRl register.
9.12.2.4 Tra nsmit Short-Circui t Det ector/Limit er
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is
approx imately 25Ω or l ess. TSCS (LRSR.2) provides a real-time indication of when the current limiter is activated.
The LIU Latched Status Register (LLSR) provides latched versions of the information, which can be used to
activate an inter r upt when enable via the LSIMR register.
9.12.2.5 Tra nsmit Open-Circui t Detector
The DS26514 c an al so detect when the T TIPn or TRINGn output s are open circuit ed. OCS (LRSR.1) will pr ov ide a
real-time indication of when an open circuit i s detected. Register LLSR pro vides latched vers ions of the information,
which can be u sed to activate an int errupt when enabl ed v i a the LSIMR regi ster. The open-circuit-detect feature is
not availabl e in T1 CSU operating modes (LBO 5, LBO 6, and LBO 7).
9.12.3 Receiver
9.12.3.1 Receive Internal Termination
The DS26514 c ontains four receivers. The termination cir c uit provides an analog switc h that powers up in the open
setting, providing high impedance to the receive line side. This is useful for redundancy applications and hot
swapability.
Three terminati on m ethods are av ailabl e:
• Partially internal impedance match with 120Ω ext er nal resistor.
• Fully interna l impedance match, no external resistor.
• Exter nal r esi stor terminati on, i nternal terminati on disabl ed.
See the LRISMR regi ster for m ore detail s. Int ernal impedance m atch is conf igur abl e to 75Ω, 100Ω, 110Ω, or 120Ω
termination by setting the appropriate RIMPM[1:0] bits. These bits must be configured to match line impedance
even if internal termination is disabled.
Figure 9-24 shows a diagram of the switch control of termination. If internal impedance match is disabled, the
ex ternal resistor , RT, must match the line impedance.
Figure 9-24. Receive LIU Termination Options
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 92 of 305
RECEIVE LIU
RTIPn
RRINGn
1:1
TFR
Rx LINE
R
T
RT
LRISMR.RIMPON
The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1
transformer . See Table 9-41 for transf ormer details.
Receive sensitiv ity is configurabl e by setting the appropriate RSMS[1:0] bits (LRCR).
The DS26514 uses a digital clock recovery system. The resultant E1, T1 or J1 clock derived from MCLK is
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the
clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This
oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in
Figure 9-27.
Norm ally, the cloc k that is output at the RCLK n pin i s t he recov ered c loc k fr om the E1 AMI /HDB 3 or T1 A MI/B8ZS
wav eform presented at the RTIPn and RRI NGn inputs. If t he jitter attenuator (LTRCR) is pl ac ed in the rec eive path
(as is t he ca se in m ost appl i cations), the j itt er att enuator restore s the RC LKn t o an appr ox im ate 50% dut y cycle. If
the jitt er attenuator is eit her placed i n the transmit path or is di sabl ed, the RCLKn output c an ex hibit sl ightly short er
high cycles of the cl ock. This is due to the highl y ov er-sampled digit al cl ock recov ery circuitry . See Table 13-3 for
more details. When no signal is present at RTIPn and RRINGn, a receive carrier loss (RCL) condition will occur
and the RCLKn will be derived from the MCLK T1 or MCLKE1 source (depending on the configuration).
9.12.3.2 Receive Level Indicat or
The DS26514 wil l report the signal strength at RTIP n and RRINGn in approximately 2.5dB i nc r em ents via RSL[3:0]
located in the LIU Receive Signal Level Register (LRSL). This feature is helpful when trouble shooting line
performanc e probl em s.
9.12.3.3 Receive G.703 Sectio n 10 Synchron ization Signal
The DS26514 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the receive G.703 clock bit (RG703) found in the LIU Receive Control Register
(LRCR.7).
9.12.3.4 Receiver Monitor Mode
The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation
caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to
32dB al ong with cable attenuation of 12dB to 30dB as sho wn in the LIU Receiv e Control Register (LRCR).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 93 of 305
Figure 9-25. Typical Monitor Application
PRIMARY
T1/E1 TERMINATING
DEVICE
MONITOR
PORT JACK
T1/E1 LINE
X
F
M
R
DS2651x
Rt
Rm Rm
SECONDARY T1/E1
TERMINATING
DEVICE
9.12.3.5 Los s of S ig na l
The DS26514 uses both the digital and analog loss-detection method in compliance with the latest T1.231 for
T1/J1 and ITU-T G.775 or ETS 300 233 for E1 m ode of operation.
LOS is detected if the receiv er level falls bellow a threshold analog voltage for certain duration. Alternativ ely, this
can be term ed as hav ing r eceiv ed “zeros” f or a c ertain durati on. T he signal lev el and timing dur ation are defi ned i n
accordanc e with the T 1.231 or G. 775 or ETS 300 233 specifications.
For short -haul mode, t he loss-detec ti on thr esholds are based on c able l oss of 12dB to 18dB f or both T1/J 1 and E1
m odes. The l oss thresholds are selectable based on Table 10-23. For long-haul mode, the LOS-detection thres hold
is based on cable l os s of 30dB to 38dB for T1/ J 1 and 30dB to 45dB for E1 mode. Note there is no explici t bit call ed
short-haul mode selection. Loss declaration level is set at 3dB lower than the maximum sensitivity setting
programmed in Table 10-23.
The loss state is ex ited when the rec eiver detects a certain ones den si ty at t he maximum sensit ivity level or higher ,
which is 3dB higher than the loss-detection level. The loss-detection signal level and loss-reset signal level are
defined with hysteresis to prevent the receiver from bouncing between “LOS” and “no LOS” states. Table 9-42
outlines the specif ications governing the loss function.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 94 of 305
Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications
CRITERIA
STANDARD
T1.231
ITU-T G.7 7 5
ETS 300 233
Loss
Detection
No pulses are detected for 175
±75 bi ts.
No pulses are detected for
duration of 10 to 255 bit
periods.
No pulses are detected f or a
duration of 2048 bit periods or
1ms.
Loss Reset
Loss is term inated if a duration
of 12. 5% ones are det ec ted
ov er dur ation of 175 ± 75 bits.
Loss is not t erminated if 8
consecutive zeros are found if
B8ZS enc oding is used. If
B8ZS is not used, loss i s not
terminated if 100 c onsecut ive
pulses are zero.
The incoming signal has
transi tions for dur ation of 10 t o
255 bit periods.
Loss reset c r iteri a is not
defined.
9.12.3.6 ANSI T1. 231 f or T1 and J1 Modes
For short-haul m ode, loss is declared if the received signal l ev el is 3dB lower f rom t he programmed v alue (based
on Table 10-23) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss is
decl ar ed at 15dB.
LOS is reset if all the fo llowing crier ia are met:
1) 24 or mor e ones are det ec ted i n a 192-bit period with a programmed sensitivit y l ev el m easured at RTI P n
and RRING n.
2) During the 192 bit s, fewer t han 100 c onsecut ive zeros are detect ed.
For long-haul mode, loss is detected if the received signal l ev el is 3dB lower from the progr ammed value ( bas ed on
Table 10-23) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 30dB, the loss
decl ar ation lev el is 33dB.
LOS is reset if all the following crieria are m et:
1) 24 or mor e ones are det ec ted i n a 192-bit period with a programmed sensitivit y l ev el m easured at RTI P n
and RRING n.
2) During the 192 bit s, fewer t han 100 c onsecut ive zeros are detect ed.
9.12.3.7 ITU-T G.775 for E1 Modes
For short-haul m ode, loss is declared if the received signal l ev el is 3dB lower f rom t he programmed v alue (based
on Table 10-23) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss is
declared at 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity
lev el for a duration of 192-bit peri ods.
For long-haul mode, loss is detected if the received signal l ev el is 3dB lower from the progr ammed v alue ( bas ed on
Table 10-23) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 30dB, the loss
declaration level is 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed
sensit ivit y level for a duration of 192-bit periods.
9.12.3.8 ET S 200 233 for E 1 Modes
For short-haul m ode, loss is declared if the received signal l ev el is 3dB lower f rom t he programmed v alue (based
on Table 10-23) continusou duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater
than or equal to the progr ammed sensi tivity level for a duration of 192-bit periods.
For long-haul mode, loss is decl ar ed if t he r ec eiv ed si gnal lev el is 3dB lower from the progr ammed val ue ( bas ed on
Table 10-23) conti nuous durati on of 2048-bit periods (1m s). LOS i s reset if the rec eiv e signal l evel is greater than
or equal to the pr ogr ammed sensitivity level for a duration of 192-bit periods.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 95 of 305
9.12.4 Hitless Protec tion Switching (HPS)
Many current redundancy protection implementations use mechanical relays to switch between primary and
backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The
switc hing ev ent will likely cause f ram e-synchroni zation l oss in any equi pment downstream, aff ecting the quali ty of
service. The same is also true for tri-stating mechanisms that use software or inactive clocks for the triggering of
HPS.
The DS26514 LI Us f eature fast t ristat able outputs f or TTI Pn and TRINGn and fast di sabl ing of int ernal impedance
m atching f or RTIP n and RRING n wi thin one-bi t per iod. T he TXENABLE pin i s used f or hi tl ess protec ti on ci rcuit s in
combination with the LTRCR.RHPM bit. W hen low, the TXENABLE pin three-states all four transmit ters, providing
a high-impedance state on TTIPn and TRINGn. If the RHPM bit is set, the TXENABLE pin, when low, will also
disable the internal termination on RTIPn and RRINGn on a per-port basis, providing a high impedance to the
receive line.
This is a very useful function in that control can be done through a hardware pin, allowing a quick switch to the
backup system for both the rec eiv er and the t r ansmit ter. Figure 9-26 shows a typical HPS appli c ation.
Figure 9-26. HPS Block Diagram
PRIMARY
BOARD
BACKUP
BOARD
SWITCHING
CONTROL
TXENABLE
TRING
RTIP
TTIP
RRING
TRING
RTIP
TTIP
RRING
LINE
INTERFACE
CARD
RX
TX
TXENABLE
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 96 of 305
FREQUENCY (Hz)
0dB
-20dB
-40dB
-60dB
110 100 1K 10K
JITTER ATTENUATION (dB)
100K
TR 62 411 (Dec . 90)
Prohibited Area
Cur ve B
Cur ve A
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
T1E1
9.12.5 Jitter Attenuato r
Each LIU contains a jitter attenuator that can be set to a depth of 32 or 128 bit s v ia the JADS bits in LIU Transm it
and Receive Control Register (LTRCR).
The 128-bi t m ode i s used i n appli cati ons where l arge ex cursi ons of wander are ex pec ted. The 32-bi t mode is use d
in delay sensi tive applications. The characteristic s of the att enuation are sh own i n Figure 9-27. The jitter at tenuator
can be pl ac ed in ei ther the rec eiv e path or the transmit path, or be disabled by appropriately setting the JAPS1 and
JAPS 0 bits in the LIU Transmit and Receiv e Control Register (LTRCR).
For the jitt er attenuator to operate proper ly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x cl oc k m ust be applied
at MCLK. See the Global Transceiver Clock Control Register 1 (GTCCR1) for MCLK options. ITU-T specification
G.703 requires an accuracy of ±50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an
accurac y of ±32ppm for T1/ J1 int erf aces. Circuitry adjusts eit her the recov ered clock f rom the cl ock/data recov ery
bloc k or the cl ock applied at the TCLKn pi n to create a smooth jitt er-free cl ock, which is used to cl ock data out of
the jitter attenuator FIF O. It is acceptable to provide a gapped/bursty c lock at t he TCLKn pin if the jit ter attenuator is
plac ed in the transmit side. If the incomi ng jitter exceeds either 120UI P-P ( buff er depth is 12 8-bits) or 28UIP-P (buffer
depth is 32 bits), then the DS26514 will set the jitter attenuator limit trip (JALTS) bit in the LIU Latched Status
Register ( LLSR.3). In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz, and in E1 mode it is 0.6Hz.
The DS26514 jitter att enuator is compliant with the following specif icati ons shown in Table 9-43.
Table 9-43. Jitter Attenuator Standards Compliance
Standard
ITU-T I.431, G.703, G.736, G.823
ETS 300 011, TB R 12/13
AT&T TR62411, TR43802
TR-TSY 009, TR-TSY 253, TR-TSY 499
Figure 9-27. Jitter Attenuation
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 97 of 305
9.12.6 LIU Loopbac ks
The DS26514 provides four LIU loopbacks for diagnostic purposes: Analog Loopback, Local Loopback, Remote
Loopback 1, and Remot e Loopback 2. Dual Loopback is a com binati on of Local Loopback and Remot e Loopback
1. I n the loopback diagrams that f ollow, TSE Rn, TCLK n, RSE Rn, and RCLKn ar e inputs/output s fr om the fr amer.
Figure 9-28. Loopback Diagram
Jitter
Attenuator
(in RX path)
RSER
Jitter
Attenuator
(in TX path)
Local Loopback
Jitter
Attenuator
can be
assigned to
recei ve path
or transmit
path or
disabled
RTIP
RRING
TTIP
TRING
JACLK
Master Clock
PLL
MCLK
RCLK
Analog Loopback
Remote 2 Loopback
Remote 1 Loopback
TSER
TCLK
RX LIU
TX LIU TX FORMATTER
RX FRAMER
9.12.6.1 A na log Loop ba c k
The analog output of t he transmitter TTI P n and TRI NGn is looped bac k to RTIPn and RRINGn of the rec eiv er . Dat a
at RTIP n and RRINGn is i gnor ed in analog loopback. This is shown in t he Figure 9-29.
Figure 9-29. Analog Loopback
Line
Driver
Transmit
Framer
Optional
Jitter
Attenuator
Transmit
Digital
Transmit
Analog
TCLK
Receive
Framer
Optional
Jitter
Attenuator
Receive
Digital
Receive
Analog
RCLK
RTIP
RRING
TSER
RSER
TTIP
TRING
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 98 of 305
9.12.6.2 Local Loopback
The t r ansmit system data i s l ooped back t o the receive fr am er. This data i s al so enc oded and output on TTIPn and
TRI NGn. Si gnals at RTIPn and RRINGn are ignored. This loopback is conceptually shown in Figure 9-30.
Figure 9-30. Loca l Loo pb a ck
Line
Driver
Transmit
Framer
Optional
Jitter
Attenuator
Transmit
Digital
Transmit
Analog
TCLK
TSER
Receive
Framer
Optional
Jitter
Attenuator
Receive
Digital
Receive
Analog
RCLK
RSER
RTIP
RRING
TTIP
TRING
9.12.6.3 Remot e Lo op back 1
The out puts decoded f rom the rec eiv e LIU ar e l ooped back t o the t ransmit LI U, not incl uding t he jitter at tenuator i n
the path. Remote Loopback 2 includes the jitter attenuator in the loopback path. The inputs from the transmit
fram er ar e ignor ed dur ing Remote Loopback 1.
9.12.6.4 Remot e Lo op back 2
The outputs decoded f rom the receiv e LIU are looped back to the t ransmi t LIU, including t he jitter at tenuator. The
inputs from the transmit framer are ignored during Remote Loopback 2. This loopback is conceptually shown in
Figure 9-31.
Figure 9-31. Remote Loopback 2
Line
Driver
Transmit
Framer
Optional
Jitter
Attenuator
Transmit
Digital
Transmit
Analog
TCLK
TSER
Receive
Framer
Optional
Jitter
Attenuator
Receive
Digital
Receive
Analog
RCLK
RSER
RTIP
RRING
TTIP
TRING
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 99 of 305
9.12.6.5 Dua l Lo opba c k
The i nputs decoded f rom the receiv e LIU are l ooped back t o the t ransm it LIU. T he input s f rom t he t ransm it f ramer
are looped back to the receiver with the optional jitter attenuator. Dual Loopback is a combination of Local
Loopback and Remote Loopback 1. This loopback is invoked by setting the correct bits in the LIU Maintenance
Control Register (LMCR). This loopback is conceptually shown in Figure 9-32.
Figure 9-32. Dual Loopback
Line
Driver
Transmit
Framer
Optional
Jitter
Attenuator
Transmit
Digital
Transmit
Analog
TCLK
TSER
Receive
Framer
Optional
Jitter
Attenuator
Receive
Digital
Receive
Analog
RCLK
RSER
RTIP
RRING
TTIP
TRING
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 100 of 305
9.13 Bit Error-Rate Test Function (BERT)
The BE RT (Bi t Error Rat e Tester ) bl ock can gener ate and det ect bot h pseudorand om and repeat ing bi t patterns. I t
is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
The registers rel ated to the configur e, contr ol, and status of the BE RT are shown in Table 9-44.
Table 9-44. Registers Related to Configure, Control, and Status of BERT
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Global B E RT Inter r upt Status
Register 1 ( GBISR1) 0FAh When any of the 8 BERT s issue an interr upt, a bit
will be set.
Global BERT Int er r upt Mask Register
1 (GBIMR1)
0FDh
When any of the 8 BERT s issue an i nterrupt , a bi t
will be set.
Receive Expansion P or t Cont r ol
Register (RXPC) 08Ah Enable for the rec eiv er BERT.
Receive BERT Port Bit Suppr ess
Register (RBPBS)
08Bh Bit suppressi on for the rec eiv e B E RT.
Receive BERT Port Channel Select
Register s 1 to 4 (RBPCS1-4)
0D4h, 0D5h, 0D6h,
0D7h
Channels to be enabled for the F r am er t o accept
data f r om the BE RT patter n gener ator
Transmit Expansion Port Control
Register (TXPC)
18Ah Enable for the transmit ter BERT.
Transmit BERT Port Bit Suppress
Register (TBPBS)
18Bh Bit suppressi on for the t r ansmit BERT.
Transmit BERT Port Channel S elec t
Register s 1 to 4 ( TBPCS1-4)
1D4h, 1D5h, 1D6h,
1D7h
Channels to be enabled for the f r am er to accept
data from the transmit BERT patter n gener ator.
BERT Alternating Word Count Rate
Register (BAWC)
1100h B E RT al ternating patter n c ount register.
BERT Repetitive Pattern Set Register
1 (BRP1)
1101h B E RT repetitive pattern set register 1.
BERT Repetitive Pattern Set Register
2 (BRP2) 1102h B E RT repetitive pat tern set register 2.
BERT Repetitive Pattern Set Register
3 (BRP3)
1103h B E RT repetitive pattern set register 3.
BERT Repetitive Pattern Set Register
4 (BRP4) 1104h B E RT repetitive pat tern set register 4.
BERT Control Register 1 (BC1)
1105h
Pattern selection and misc control
BERT Contr ol Register 2 ( BC2)
1106h
BERT bit pattern length control
BERT Bit Count Regi ster 1 ( BBC1)
1107h
Incr em ents f or BERT bit cloc k s.
BERT Bit Count Regi ster 2 ( BBC2)
1108h
BERT bit counter.
BERT Bit Count Regi ster 3 ( BBC3)
1109h
BERT bit counter.
BERT Bit Count Regi ster 4 ( BBC4)
110Ah
BERT bit counter.
BERT Error Count Regi ster 1 ( BEC1)
110Bh
BERT er r or counter.
BERT Error Count Regi ster 2 ( BEC2)
110Ch
BERT er r or counter.
BERT Error Count Regi ster 3 ( BEC3)
110Dh
BERT er r or counter.
BERT Latched S tatus Register (BSR)
110Eh
Denotes synchr onizat ion l oss and other stat us.
BERT Status Interr upt Mask Regist er
(BSIM)
110Fh BERT interrupt mask.
BERT Control Register 3 (BC3)
1400h
Pattern selection and misc control
BERT Real-Time Status Register
(BRSR) 1401h Denotes synchr onizat ion l oss and other stat us.
BERT Latched S tatus Register 1
(BLSR1)
1402h Denotes synchroni z ation loss and other stat us.
BERT Status Interr upt Mask Regist er
1 (BSIM1)
1403h BERT interrupt mask.
BERT Latched S tatus Register 2
(BLSR2)
1404h BERT error status.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 101 of 305
BERT Status Interr upt Mask Regist er
2 (BLSR2)
1405h BERT interrupt mask.
Note: The addresses shown above are for Framer 1.
The BE RT block c an gener ate and detect the followi ng patt er ns:
• The pseudorandom patter ns 2E7-1, 2E 9-1, 2E11-1, 2E15-1, and QRSS.
• A repetitive pattern from 1 to 32 bits i n length.
• Alternating ( 16-bit) words that f lip every 1 to 256 words.
• Daly patt er n ( M odified 55 Oc tet patter n), 55 Octet patter n
The BE RT function must be enabl ed and c onfigured in the TXPC and RXPC regi sters f or eac h por t. The BERT can
then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel
f uncti on in the TBPCS1-4 and RBCS1-4 registers. Individual bit positions within the channels can be suppressed
with t he TBPBS and RBPBS register s. Usi ng c ombinations of these functions, the BERT patt er n c an be trans m itted
and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive bandwidth
assignments are independent of each other.
The BERT receiver has a 32-bit bit count er and a 24-bit error counter. The BERT receiv er can generate int errupts
on: a change i n receiv e-synchroni zer status, receive all zeros, receiv e all ones, err or counter ov erfl ow, bit counter
ov erflow, and bi t er ror det ecti on. I nterrupts fr om each of these ev ent s can be masked withi n t he BERT function v ia
the BE RT Status Int er r upt Mask Regist er (BSIM). If t he software det ec ts that the BERT has reported an event, then
the software must read the BERT Latc hed S tatus Register (BSR) to determine whic h ev ent(s) has occurred.
Begi nning with die revision B1, the DS 26514 has a new set of BERT r egister s to c ompl em ent the or iginal r egisters.
These are locat ed at 1400 hex . Addi tional feat ures were added to support t he 55 Octet Pat tern and the abi lity to
byte-ali gn t o the DS0 t i m eslot. I n addit i on, a new set of stat us register s was added t hat i s int ended to repl ace t he
ori ginal status register s. The u ser now ha s the option to use either set of stat us re gisters, but i t is recommended
that he/she use the new ones as they are more complete and easier to use. A BERT real-time status register
(BRSR) was added to pr ov ide better visibility of the status of the BERT.
9.13.1 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a
pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32
bit s, the pat ter n should be rep eated so that all 32 bi ts are used t o descri be t he patter n. F or ex ample, if t he patt ern
was the repeating 5-bit pattern …01101… (where the rightmost bit is the one sent first and received first), then
BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a
pseudo-random pattern, all f our r egister s should be loaded wit h all ones (i.e., FFh). For an alter nating word pa ttern,
one word should be placed into BRP1 and BRP2 an d the ot her word should be placed i nto BRP3 and BRP4. For
ex am ple, if the DDS str ess pat tern “7E” is to be described, t he user wo uld plac e 00h in BRP1, 00h in BRP 2, 7Eh in
BRP3, and 7Eh i n BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h
foll owed by 100 byt es of 7Eh to be sent and rec eived.
9.13.2 BERT Error Counter
Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error.
Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO
status bit in the BSR register.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 102 of 305
10. DEVICE REGISTERS
Thirteen address bits are used to cont r ol the settings of the regi ster s. The register s cont r ol functions of the framers,
LIUs, and BE RTs within the DS26514. The map is divided into four framers, f ollowed by f our LIUs and four BERTs.
Global r egister s (applic able to all four transceiv er s and BERTs) are loc ated wi thi n the address space of Framer 1.
The register details are provided in the following tables. The framer registers bits are provided for Framer 1 and
address bits A[12:8] determine the f r am er addressed.
10.1 Register Listings
The f ramer r egi sters hav e an off set of 200 hex , the LIU regi sters hav e an off set of 20 hex , and the BERT registers
hav e an offset of 10 hex f or each t r ansceiver.
Table 10-1. Register Address Ranges (in Hex)
GLOBAL
REGISTERS
RECEIVE
FRAMER
TRANSMIT
FRAMER
LIU BERT EXT BERT HDLC-256
00F0 – 00FF
—
— — — — —
CH1
—
0000 – 00EF
0100 – 01EF
1000 – 101F
1100 – 110F
1400 – 140F
1500 – 151F
CH 2
—
0200 – 02EF
0300 – 03EF
1020 – 103F
1110 – 111F
1410 – 141F
1520 – 153F
CH 3
—
0400 – 04EF
0500 – 05EF
1040 – 105F
1120 – 112F
1420 – 142F
1540 – 155F
CH 4
—
0600 – 06EF
0700 – 07EF
1060 – 107F
1130 – 113F
1430 – 143F
1560 – 157F
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 103 of 305
10.1.1 Global Register List
Table 10-2. Global Register List
GLOB AL RE G ISTE R LIST
ADDRESS NAME DESCRIPTION R/W
00F0h GTCR1 Global Transceiver Contr ol Register 1 R/W
00F1h GFCR1 Global Fram er Control Register 1 R/W
00F2h GTCR3 Global Transceiver Contr ol Register 3 R/W
00F3h GTCCR1 Global Transceiver Cl ock Cont r ol Register 1 R/W
00F4h GTCCR3 Global Transceiver Cl ock Cont r ol Register 3 R/W
00F5h GHISR Gl obal HDLC-256 Interrupt Stat us Register R
00F6h GSRR1 Global S oft ware Reset Regi ster 1 R/W
00F7h GHIMR Gl obal HDLC-256 Interrupt Mask Register R/W
00F8h IDR De vice Identification Regis ter R
00F9h GFISR1 Globa l Fra mer Interrupt Status Register 1 R
00FAh GBISR1 Global B E RT Inter r upt Status Register 1 R
00FBh GLISR1 Global LIU Interrupt Status Regi ster 1 R
00FCh GFIMR1 Global Fram er s Interrupt Mask Register 1 RW
00FDh GBIMR1 Global B E RT Inter r upt Mask Register 1 RW
00FEh GLIMR1 Global LIU Interrupt Mask Register 1 RW
Not e 1: Reserved registers should only be written with all zeros.
Not e 2: The global registers are located in the framer addre ss space. The corresponding address spa ce for the other seven framers is
“Reserved,” and should be ini tiali z ed with all z er os f or pr oper op erati on.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 104 of 305
10.1.2 Framer Register List
Table 10-3. Framer Re gister List
Note that only Framer 1 address is presented here. The same set of regi sters definitions applies f or tra ns ceiver s 2 to 4 in ac c or d anc e w ith the
DS2651 4 m ap offsets . Tra nsceiver offset is [( n - 1) x 200 hex], where n designates the transceiver in question.
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
000h
E1RDMWE1
E1 Receive Digital Mill iwat t Enabl e Register 1
R/W
001h
E1RDMWE2
E1 Receive Digital Mill iwat t Enabl e Register 2
R/W
002h
E1RDMWE3
E1 Receive Digital Mill iwat t Enabl e Register 3
R/W
003h
E1RDMWE4
E1 Receive Digital Mill iwat t Enabl e Register 4
R/W
004h–00Fh
—
Reserved
—
010h
RHC
Receive HDLC Control Register
R/W
011h
RHBSE
Receive HDLC Bit Suppress Register
R/W
012h
RDS0SEL
Receive Channel M onitor Select Register
R/W
013h
RSIGC
Receive-Signali ng Control Register
R/W
014h T1RCR2 Receive Control Register 2 (T 1 Mode) R/W
E1RSAIMR Receive Sa-Bit Interr upt Mask Register (E1 Mode)
015h
T1RBOCC
Receive BOC Control Register (T1 Mode Only)
R/W
016h–01Fh
—
Reserved
—
020h
RIDR1
Receive Idle Code Defi nition Register 1
R/W
021h
RIDR2
Receive Idle Code Defi nition Register 2
R/W
022h
RIDR3
Receive Idle Code Defi nition Register 3
R/W
023h
RIDR4
Receive Idle Code Defi nition Register 4
R/W
024h
RIDR5
Receive Idle Code Defi nition Register 5
R/W
025h
RIDR6
Receive Idle Code Defi nition Register 6
R/W
026h
RIDR7
Receive Idle Code Defi nition Register 7
R/W
027h
RIDR8
Receive Idle Code Defi nition Register 8
R/W
028h
RIDR9
Receive Idle Code Defi nition Register 9
R/W
029h
RIDR10
Receive Idle Code Defi nition Register 10
R/W
02Ah
RIDR11
Receive Idle Code Defi nition Register 11
R/W
02Bh
RIDR12
Receive Idle Code Defi nition Register 12
R/W
02Ch
RIDR13
Receive Idle Code Defi nition Register 13
R/W
02Dh
RIDR14
Receive Idle Code Defi nition Register 14
R/W
02Eh
RIDR15
Receive Idle Code Defi nition Register 15
R/W
02Fh
RIDR16
Receive Idle Code Defi nition Register 16
R/W
030h
RIDR17
Receive Idle Code Defi nition Register 17
R/W
031h
RIDR18
Receive Idle Code Defi nition Register 18
R/W
032h
RIDR19
Receive Idle Code Defi nition Register 19
R/W
033h
RIDR20
Receive Idle Code Defi nition Register 20
R/W
034h
RIDR21
Receive Idle Code Defi nition Register 21
R/W
035h
RIDR22
Receive Idle Code Definition Register 22
R/W
036h
RIDR23
Receive Idle Code Defi nition Register 23
R/W
037h
RIDR24
Receive Idle Code Defi nition Register 24
R/W
038h
T1RSAOI1
Receive-Signali ng Al l-Ones Insert ion Regi ster 1 (T1 Mode Only)
R/W
RIDR25
Receive Idle Code Defi nition Register 25 ( E 1 Mode)
039h
T1RSAOI2
Receive-Signali ng Al l-Ones Insert ion Regi ster 2 (T1 Mode O nly)
R/W
RIDR26
Receive Idle Code Defi nition Register 26 ( E 1 Mode)
03Ah
T1RSAOI3
Receive-Signali ng Al l-Ones Insert ion Regi ster 3 (T1 Mode O nly)
R/W
RIDR27
Receive Idle Code Defi nition Register 27 ( E 1 Mode)
03Bh
RIDR28
Receive Idle Code Defi nition Register 28 ( E 1 Mode)
—
03Ch
T1RDMWE1
T1 Receive Digit al Milli watt E nable Register 1 (T1 M ode Only)
R/W
RIDR29
Receive Idle Code Defi nition Register 29 ( E 1 Mode)
03Dh
T1RDMWE2
T1 Receive Digit al Milli watt E nable Register 2 (T1 M ode Only)
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 105 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
RIDR30
Receive Idle Code Defi nition Register 30 ( E 1 Mode)
03Eh
T1RDMWE3
T1 Receive Digit al Milli watt E nable Register 3 (T1 M ode Only)
R/W
RIDR31
Receive Idle Code Defi nition Register 31 ( E 1 Mode)
03Fh
RIDR32
Receive Idle Code Defi nition Register 32 ( E 1 Mode)
—
040h
RS1
Receive-Signali ng Register 1
R
041h
RS2
Receive-Signali ng Register 2
R
042h
RS3
Receive-Signali ng Register 3
R
043h
RS4
Receive-Signali ng Register 4
R
044h
RS5
Receive-Signali ng Register 5
R
045h
RS6
Receive-Signali ng Register 6
R
046h
RS7
Receive-Signali ng Register 7
R
047h
RS8
Receive-Signali ng Register 8
R
048h
RS9
Receive-Signali ng Register 9
R
049h
RS10
Receive-Signali ng Register 10
R
04Ah
RS11
Receive-Signali ng Register 11
R
04Bh
RS12
Receive-Signali ng Register 12
R
04Ch
RS13
Receive-Signali ng Register 13 (E1 Mode onl y)
—
04Dh
RS14
Receive-Signali ng Register 14 (E1 Mode onl y)
—
04Eh
RS15
Receive-Signali ng Register 15 (E1 Mode onl y)
—
04Fh
RS16
Receive-Signali ng Register 16 (E1 Mode onl y)
—
050h
LCVCR1
Line Code V iolation Count Regi ster 1
R
051h
LCVCR2
Line Code V iolation Count Regi ster 2
R
052h
PCVCR1
Path Code Vi olation Count Regi ster 1
R
053h
PCVCR2
Path Code Vi olation Count Regi ster 2
R
054h
FOSCR1
Fram es Out of Sync Count Regi ster 1
R
055h
FOSCR2
Fram es Out of Sync Count Regi ster 2
R
056h
E1EBCR1
E-Bit Count 1 (E1 Mode Only )
R
057h
E1EBCR2
E-Bit Count 2 (E1 Mode Only )
R
058h
FEACR1
Error Count A Register 1
R/W
059h
FEACR2
Error Count A Register 2
R/W
05Ah
FEBCR1
Error Count B Register 1
R/W
05Bh
FEBCR2
Error Count B Register 2
R/W
060h
RDS0M
Receive DS0 Monit or Regi ster
R
061h
—
Reserved
—
062h
T1RFDL
Receive FDL Register (T1 M ode)
R
E1RRTS7
Receive Real-Time Status Regi ster 7 ( E 1 Mode)
063h
T1RBOC
Receive BOC Register (T1 Mode)
R
064h
T1RSLC1
Receive SLC-96 Data Link Regi ster 1 (T1 M ode)
R
E1RAF
E1 Receive Align Fra me Register (E1 M ode)
065h
T1RSLC2
Receive SLC-96 Data Link Regi ster 2 (T1 M ode)
R
E1RNAF
E1 Receive Non-Align Frame Register (E1 Mode)
066h
T1RSLC3
Receive SLC-96 Data Link Regi ster 3 (T1 M ode)
R
E1RsiAF
E1 Received Si Bi ts of the Align Fr am e Register ( E 1 Mode)
067h
E1RSiNAF
Received Si Bits of the Non-Align Frame Register ( E 1 Mode)
R
068h
E1RRA
Received Remote Alarm Register (E1 Mode)
R
069h
E1RSa4
E1 Receive Sa4 Bi ts Register (E 1 Mode Only )
R
06Ah
E1RSa5
E1 Receive Sa5 Bi ts Register (E 1 Mode Only )
R
06Bh
E1RSa6
E1 Receive Sa6 Bi ts Register (E 1 Mode Only )
R
06Ch
E1RSa7
E1 Receive Sa7 Bi ts Register (E 1 Mode Only )
R
06Dh
E1RSa8
Receive Sa8 Bits Register ( E 1 M ode Only)
R
06Eh
SaBITS
E1 Receive SaX Bits Register
R
06Fh
Sa6CODE
Received Sa6 Codeword Register
R
070h–07Fh
—
Reserved
—
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 106 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
080h
RMMR
Receive Master Mode Register
R/W
081h
RCR1
Receive Control Register 1 (T1 Mode)
R/W
RCR1
Receive Control Register 1 (E1 Mode)
082h
T1RIBCC
Receive In-Band Code Control Regi ster ( T1 Mode)
R/W
E1RCR2
Receive Control Register 2 (E1 Mode)
083h
RCR3
Receive Control Register 3
R/W
084h
RIOCR
Receive I/O Configurat ion Regi ster
R/W
085h
RESCR
Receive Elasti c St or e Control Register
R/W
086h
ERCNT
Error-Counter Confi gur ation Register
R/W
087h
RHFC
Receive HDLC FIFO Control Regist er
R/W
088h
RIBOC
Receive Interleave Bus Operat ion Control Regi ster
R/W
089h
T1RSCC
In-Band Receiv e Spare Cont r ol Register (T1 Mode Only)
R/W
08Ah
RXPC
Receive Expansion P or t Cont r ol Register
R/W
08Bh
RBPBS
Receive BERT Port Bit Suppr ess Register
R/W
08Ch
-
Reserved
—
08Dh
RHBS
Receive HDLC-256 Bit Suppress Regi ster
R/W
08Eh-08Fh
-
Reserved
—
090h
RLS1
Receive Latched Status Register 1
R/W
091h
RLS2
Receive Latched Status Register 2 (T1 M ode)
R/W
RLS2
Receive Latched Status Register 2 ( E 1 Mode)
092h
RLS3
Receive Latched Status Register 3 (T1 M ode)
R/W
RLS3
Receive Latched Status Register 3 ( E 1 Mode)
093h
RLS4
Receive Latched Status Register 4
R/W
094h
RLS5
Receive Latched Status Register 5 (HDLC)
R/W
095h
—
Reserved
—
096h
RLS7
Receive Latc hed Status Regi ster 7 (T 1 M ode)
R/W
RLS7
Receive Latched Status Register 7 ( E 1 Mode)
097h
—
Reserved
—
098h
RSS1
Receive-Signali ng S tatus Register 1
R/W
099h
RSS2
Receive-Signali ng S tatus Register 2
R/W
09Ah
RSS3
Receive-Signali ng S tatus Register 3
R/W
09Bh
RSS4
Receive-Signali ng S tatus Register 4 (E1 Mode Only)
R/W
09Ch
T1RSCD1
Receive Spare Code Defi nition Register 1 (T1 Mode Only)
R/W
09Dh
T1RSCD2
Receive Spare Code Defi nition Register 2 (T1 Mode Only)
R/W
09Eh
—
Reserved
—
09Fh
RIIR
Receive Interrupt Inf ormation Register
R/W
0A0h
RIM1
Receive Interrupt Mask Register 1
R/W
0A1h
RIM2
Receive Interrupt Mask Register 2 (E1 Mode Only)
R/W
0A2h
RIM3
Receive Interrupt Mask Register 3 (T1 Mode)
R/W
RIM3
Receive Interrupt Mask Register 3 (E1 Mode)
0A3h
RIM4
Receive Interrupt Mask Register 4
R/W
0A4h
RIM5
Receive Interrupt Mask Register 5 (HDLC)
R/W
0A5h
—
Reserved
—
0A6h
RIM7
Receive Interrupt Mask Register 7 (BOC:FDL) (T1 Mode)
R/W
RIM7
Receive Interrupt Mask Register 7 (BOC:FDL) (E 1 Mode)
0A7h
—
Reserved
—
0A8h
RSCSE1
Receive-Signali ng Change of State Enable Regi ster 1
R/W
0A9h
RSCSE2
Receive-Signali ng Change of State Enable Regi ster 2
R/W
0AAh
RSCSE3
Receive-Signali ng Change of State Enable Regi ster 3
R/W
0ABh
RSCSE4
Receive-Signali ng Change of State Enable Regi ster 4 (E1 Mode Only )
—
0ACh
T1RUPCD1
Receive Up Code Definition Register 1 (T1 Mode Only)
R/W
0ADh
T1RUPCD2
Receive Up Code Definition Register 2 (T1 Mode Only)
R/W
0AEh
T1RDNCD1
Receive Down Code Definition Regi ster 1 (T1 Mode Only)
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 107 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
0AFh
T1RDNCD2
Receive Down Code Definition Regi ster 2 (T1 Mode Only)
R/W
0B0h
RRTS1
Receive Real-Time Status Regi ster 1
R
0B1h
—
Reserved
—
0B2h
RRTS3
Receive Real-Time Status Regi ster 3 (T1 M ode)
R
RRTS3
Receive Real-Time Status Regi ster 3 ( E 1 Mode)
0B3h
—
Reserved
—
0B4h
RRTS5
Receive Real-Time Status Regi ster 5 ( HDLC)
R
0B5h
RHPBA
Receive HDLC Packet Bytes Available Register
R
0B6h
RHF
Receive HDLC FIFO Register
R
0B7h–0BFh
—
Reserved
—
0C0h
RBCS1
Receive Blank Channel Select Register 1
R/W
0C1h
RBCS2
Receive Blank Channel Select Register 2
R/W
0C2h
RBCS3
Receive Blank Channel Select Register 3
R/W
0C3h
RBCS4
Receive Blank Channel Select Register 4 (E1 Mode On ly)
R/W
0C4h
RCBR1
Receive Channel Bl oc ki ng Register 1
R/W
0C5h
RCBR2
Receive Channel Bl oc ki ng Register 2
R/W
0C6h
RCBR3
Receive Channel Bl oc ki ng Register 3
R/W
0C7h
RCBR4
Receive Channel Bl oc ki ng Register 4 (E1 Mode Only)
R/W
0C8h
RSI1
Receive-Signali ng Reinserti on Enabl e Register 1
R/W
0C9h
RSI2
Receive-Signali ng Reinserti on Enabl e Register 2
R/W
0CAh
RSI3
Receive-Signali ng Reinserti on Enabl e Register 3
R/W
0CBh
RSI4
Receive-Signali ng Reinserti on Enabl e Register 4 (E1 Mode Only)
R/W
0CCh
RGCCS1
Receive Gapped Clock Channel S elect Regi ster 1
R/W
0CDh
RGCCS2
Receive Gapped Clock Channel S elect Register 2
R/W
0CEh
RGCCS3
Receive Gapped Clock Channel S elect Regi ster 3
R/W
0CFh
RGCCS4
Receive Gapped Clock Channel S elect Regi ster ( E 1 Mode Only)
R/W
0D0h
RCICE1
Receive Channel Idle Code Enable Register 1
R/W
0D1h
RCICE2
Receive Channel Idle Code Enable Register 2
R/W
0D2h
RCICE3
Receive Channel Idle Code Enable Register 3
R/W
0D3h
RCICE4
Receive Channel Idle Code Enable Register 4 (E1 M ode Only)
R/W
0D4h
RBPCS1
Receive BERT Port Channel Select Register 1
R/W
0D5h
RBPCS2
Receive BERT Port Channel Select Register 2
R/W
0D6h
RBPCS3
Receive BERT Port Channel Select Register 3
R/W
0D7h
RBPCS4
Receive BERT Port Channel Select Register 4 (E1 Mode Onl y)
R/W
0D8h-0DBh
-
Reserved
0DCh
RHCS1
Receive HDLC-256 Channel S elec t Register 1
R/W
0DDh
RHCS2
Receive HDLC-256 Channel S elec t Register 2
R/W
0DEh
RHCS3
Receive HDLC-256 Channel S elec t Register 3
R/W
0DFh
RHCS4
Receive HDLC-256 Channel S elec t Register 4
R/W
0E0h-0EFh
-
Reserved
-
0F0h–0FFh
Global
Registers
(Section 0)
See the Global Register list in Table 10-2. Note that t his spac e i s
“Reserved” in Fram er s 2 to 4. R/W
100h
TDMWE1
Transmit Digit al Mill iwat t Enabl e Register 1 (T1 and E1 Modes)
R/W
101h
TDMWE2
Transmit Digit al Mill iwat t Enabl e Register 2 (T1 and E1 Modes)
R/W
102h
TDMWE3
Transmit Digit al Mill iwat t Enabl e Register 3 (T1 and E1 Modes)
R/W
103h
TDMWE4
Transmit Digit al Mill iwat t Enabl e Register 4 (T1 and E1 Modes)
R/W
104h
TJBE1
Transmit Jammed Bit Eight Stuff ing Regi ster 1
R/W
105h
TJBE2
Transmit Jammed Bit Eight Stuff ing Regi ster 2
R/W
106h
TJBE3
Transmit Jammed Bit Eight Stu ffing Regi ster 3
R/W
107h
TJBE4
Transmit Jammed Bit Eight Stuff ing Regi ster 4
R/W
108h
TDDS1
Transmit DDS Zero Code Register 1
R/W
109h
TDDS2
Transmit DDS Zero Code Register 2
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 108 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
10Ah
TDDS3
Transmit DDS Zero Code Register 3
R/W
110h
THC1
Transmit HDLC Control Regist er 1
R/W
111h
THBSE
Transmit HDLC Bit Suppress Register
R/W
112h
—
Reserved
—
113h
THC2
Transmit HDLC Control Regist er 2
R/W
114h
E1TSACR
E1 Transmit Sa-Bi t Cont r ol Register (E1 Mode)
R/W
115h–117h
—
Reserved
—
118h
SSIE1
Software-Signaling Inserti on Enabl e Register 1
R/W
119h
SSIE2
Software-Signaling Inserti on Enabl e Register 2
R/W
11Ah
SSIE3
Software-Signaling Insertion Enable Register 3
R/W
11Bh
SSIE4
Software-Signaling Inserti on Enabl e Register 4 (E1 Mode O nly)
R/W
11Ch–11Fh
—
Reserved
—
120h
TIDR1
Transmit Idl e Code Defi nition Register 1
R/W
121h
TIDR2
Transmit Idl e Code Defi nition Register 2
R/W
122h
TIDR3
Transmit Idl e Code Defi nition Register 3
R/W
123h
TIDR4
Transmit Idl e Code Defi nition Register 4
R/W
124h
TIDR5
Transmit Idl e Code Defi nition Register 5
R/W
125h
TIDR6
Transmit Idl e Code Definition Regi ster 6
R/W
126h
TIDR7
Transmit Idl e Code Defi nition Register 7
R/W
127h
TIDR8
Transmit Idl e Code Defi nition Register 8
R/W
128h
TIDR9
Transmit Idl e Code Defi nition Register 9
R/W
129h
TIDR10
Transmit Idl e Code Defi nition Register 10
R/W
12Ah
TIDR11
Transmit Idl e Code Defi nition Register 11
R/W
12Bh
TIDR12
Transmit Idl e Code Defi nition Register 12
R/W
12Ch
TIDR13
Transmit Idl e Code Defi nition Register 13
R/W
12Dh
TIDR14
Transmit Idl e Code Defi nition Register 14
R/W
12Eh
TIDR15
Transmit Idle Code Defini tion Regi ster 15
R/W
12Fh
TIDR16
Transmit Idl e Code Defi nition Register 16
R/W
130h
TIDR17
Transmit Idl e Code Defi nition Register 17
R/W
131h
TIDR18
Transmit Idl e Code Defi nition Register 18
R/W
132h
TIDR19
Transmit Idl e Code Defi nition Register 19
R/W
133h
TIDR20
Transmit Idl e Code Defi nition Register 20
R/W
134h
TIDR21
Transmit Idl e Code Defi nition Register 21
R/W
135h
TIDR22
Transmit Idl e Code Defi nition Register 22
R/W
136h
TIDR23
Transmit Idl e Code Defi nition Register 23
R/W
137h
TIDR24
Transmit Idl e Code Defi nition Register 24
R/W
138h
TIDR25
Transmit Idl e Code Defi nition Register 25 ( E 1 Mode Only )
R/W
139h
TIDR26
Transmit Idl e Code Defi nition Register 26 ( E 1 Mode Only )
R/W
13Ah
TIDR27
Transmit Idl e Code Defi nition Register 27 ( E 1 Mode Only )
R/W
13Bh
TIDR28
Transmit Idl e Code Defi nition Register 28 ( E 1 Mode Only )
R/W
13Ch
TIDR29
Transmit Idl e Code Defi nition Register 29 ( E 1 Mode Only )
R/W
13Dh
TIDR30
Transmit Idl e Code Defi nition Register 30 ( E 1 Mode Only )
R/W
13Eh
TIDR31
Transmit Idl e Code Defi nition Register 31 ( E 1 Mode Only )
R/W
13Fh
TIDR32
Transmit Idl e Code Defi nition Register 32 ( E 1 Mode Only )
R/W
140h
TS1
Transmit-Signaling Register 1
R/W
141h
TS2
Transmit-Signaling Register 2
R/W
142h
TS3
Transmit-Signaling Register 3
R/W
143h
TS4
Transmit-Signaling Register 4
R/W
144h
TS5
Transmit-Signaling Register 5
R/W
145h
TS6
Transmit-Signaling Register 6
R/W
146h
TS7
Transmit-Signaling Register 7
R/W
147h
TS8
Transmit-Signaling Register 8
R/W
148h
TS9
Transmit-Signaling Register 9
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 109 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
149h
TS10
Transmit-Signaling Register 10
R/W
14Ah
TS11
Transmit-Signaling Register 11
R/W
14Bh
TS12
Transmit-Signaling Register 12
R/W
14Ch
TS13
Transmit-Signaling Register 13
R/W
14Dh
TS14
Transmit-Signaling Register 14
R/W
14Eh
TS15
Transmit-Signaling Register 15
R/W
14Fh
TS16
Transmit-Signaling Register 16
R/W
150h
TCICE1
Transmit Channel I dle Code E nable Register 1
R/W
151h
TCICE2
Transmit Channel I dle Code E nable Register 2
R/W
152h
TCICE3
Transmit Channel I dle Code E nable Register 3
R/W
153h
TCICE4
Transmit Channel I dle Code E nable Register 4 (E1 Mode Only)
R/W
154h–161h
—
Reserved
—
162h
T1TFDL
Transmit FDL Regis ter (T1 Mode Only)
R/W
163h
T1TBOC
Transmit BOC Regis ter (T1 Mode Only)
R/W
164h
T1TSLC1
Transmit SLC-96 Data Link Register 1 (T1 Mode)
R/W
E1TAF
Transmit Align Frame Register (E 1 M ode)
165h
T1TSLC2
Transmit SLC-96 Data Link Register 2 (T1 Mode)
R/W
E1TNAF
Transmit Non-Align Fram e Register (E1 Mode)
166h
T1TSLC3
Transmit SLC-96 Data Link Register 3 (T1 Mode)
R/W
E1TSiAF Transmit Si Bits of the Align Frame Regi ster ( E 1 Mode)
167h
E1TSiNAF
Transmit Si Bits of the Non-Align Fr am e Register ( E 1 Mode Only )
R/W
168h
E1TRA
Transmit Remote Alarm Register (E1 Mode)
R/W
169h
E1TSa4
Transmit Sa4 Bits Regi ster ( E 1 Mode Only )
R/W
16Ah
E1TSa5
Transmit Sa5 Bits Regi ster ( E 1 Mode Only )
R/W
16Bh
E1TSa6
Transmit Sa6 Bits Regi ster ( E 1 Mode Only )
R/W
16Ch
E1TSa7
Transmit Sa7 Bits Regi ster ( E 1 Mode Only )
R/W
16Dh
E1TSa8
Transmit Sa8 Bits Regi ster ( E 1 Mode Only )
R/W
16Eh–17Fh
—
Reserved
—
180h
TMMR
Transmit Master Mode Register
R/W
181h
TCR1
Transmit Control Regist er 1 (T1 M ode)
R/W
TCR1
Transmit Control Regist er 1 ( E 1 Mode)
182h
T1.TCR2
Transmit Control Register 2 (T1 M ode)
R/W
E1.TCR2
Transmit Control Regist er 2 ( E 1 Mode)
183h
TCR3
Transmit Control Regist er 3
R/W
184h
TIOCR
Transmit I/ O Con figurat ion Register
R/W
185h
TESCR
Transmit Elastic Stor e Control Register
R/W
186h
TCR4
Transmit Control Regist er 4 (T1 M ode Only)
R/W
187h
THFC
Transmit HDLC FIFO Contr ol Register
R/W
188h
TIBOC
Transmit Interl eave Bus O per ation Control Register
R/W
189h
TDS0SEL
Transmit DS0 Channel M onitor Select Register
R/W
18Ah
TXPC
Transmit Expansion Port Control Register
R/W
18Bh
TBPBS
Transmit BERT Port Bit Suppress Regist er
R/W
18Ch
-
Reserved
-
18Dh
THBS
Transmit HDLC-256 Bit Suppr ess Register
R/W
18Eh
TSYNCC
Transmit Synchronizer Control Register
R/W
18Fh
—
Reserved
—
190h
TLS1
Transmit Latched Status Register 1
R/W
191h
TLS2
Transmit Latched Status Register 2 (HDLC)
R/W
192h
TLS3
Transmit Latched Status Register 3 (Sync hr onizer)
R/W
193h–19Eh
—
Reserved
—
19Fh
TIIR
Transmit Inter r upt I nformation Register
R/W
1A0h
TIM1
Transmit Inter r upt Mask Regist er 1
R/W
1A1h
TIM2
Transmit Inter r upt Mask Regist er 2 ( HDLC)
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 110 of 305
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
1A2h
TIM3
Transmit Inter r upt Mask Regist er 3 ( Synchr onizer)
R/W
1A3h–1ABh
—
Reserved
—
1ACh
T1TCD1
Transmit Code Defi nition Register 1 (T1 Mode Only )
R/W
1ADh
T1TCD2
Transmit Code Defi nition Register 2 (T1 Mode Only )
R/W
1AEh–1B0h
—
Reserved
—
1B1h
TRTS2
Transmit Real-Time Status Register 2 ( HDLC)
R
1B2h
—
Reserved
—
1B3h
TFBA
Transmit HDLC FIFO Buffer Avail able Regi ster
R
1B4h
THF
Transmit HDLC FIFO Regi ster
W
1B5h–1BhA
—
Reserved
—
1BBh
TDS0M
Transmit DS0 Monitor Register
R
1BCh–1BFh
—
Reserved
—
1C0h
TBCS1
Transmit Blank Channel S elec t Regi ster 1
R/W
1C1h
TBCS2
Transmit Blank Channel S elec t Regi ster 2
R/W
1C2h
TBCS3
Transmit Blank Channel S elec t Regi ster 3
R/W
1C3h
TBCS4
Transmit Blank Channel S elec t Regi ster 4 (E1 Mode Onl y)
R/W
1C4h
TCBR1
Transmit Channel Bloc ki ng Register 1
R/W
1C5h
TCBR2
Transmit Channel Bloc ki ng Register 2
R/W
1C6h
TCBR3
Transmit Channel Bloc ki ng Register 3
R/W
1C7h
TCBR4
Transmit Channel Bloc ki ng Register 4 (E1 Mode Only)
R/W
1C8h
THSCS1
Transmit Hardware-Signaling Channel Select Regi ster 1
R/W
1C9h
THSCS2
Transmit Hardware-Signaling Channel Select Regi ster 2
R/W
1CAh
THSCS3
Transmit Hardware-Signaling Channel Select Regi ster 3
R/W
1CBh THSCS4
Transmit Hardware-Signaling Channel Select Register 4 (E1 M ode
Only)
R/W
1CCh
TGCCS1
Transmit Gapped-Clock Channel S elec t Regi ster 1
R/W
1CDh
TGCCS2
Transmit Gapped-Clock Channel S elec t Regi ster 2
R/W
1CEh
TGCCS3
Transmit Gapped-Clock Channel S elec t Regi ster 3
R/W
1CFh
TGCCS4
Transmit Gapped-Clock Channel S elec t Regi ster 4 ( E 1 Mode O nly )
R/W
1D0h
PCL1
Per-Channel Loopback E nable Register 1
R/W
1D1h
PCL2
Per-Channel Loopback Enable Register 2
R/W
1D2h
PCL3
Per-Channel Loopback Enable Register 3
R/W
1D3h
PCL4
Per-Channel Loopback Enable Register 4 (E1 Mode Only)
R/W
1D4h
TBPCS1
Transmit BERT Port Channel S elec t Regist er 1
R/W
1D5h
TBPCS2
Transmit BERT Port Channel S elec t Regist er 2
R/W
1D6h
TBPCS3
Transmit BERT Port Channel S elec t Regist er 3
R/W
1D7h
TBPCS4
Transmit BERT Port Channel S elec t Regist er 4 (E1 Mode Only)
R/W
1DCh
THCS1
Transmit HDLC-256 Channel S elec t Regist er 1
R/W
1DDh
THCS2
Transmit HDLC-256 Channel Select Register 2
R/W
1DEh
THCS3
Transmit HDLC-256 Channel Select Register 3
R/W
1DFh
THCS4
Transmit HDLC-256 Channel Select Register 4 (E1 Mode Only)
R/W
1E0h-1FFh
-
Reserved
-
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 111 of 305
10.1.3 LIU Register List
Table 10-4. LIU Register List
Note that only the LIU 1 address is presented here. The same set of registers definitions applies for LIUs 2 to 4 in accordance with the DS26514
map offsets. LIU offset is [1000+ (n - 1) x 20 hex], where n designates the LI U in question.
LIU REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
1000h LTRCR LIU T r ansmit Rec eive Control Regi ster R/W
1001h LTIPSR LIU Transmit Impedanc e and P ulse Shape Sel ection Register R/W
1002h LMCR LIU Maintenance Control Regi ster R/W
1003h LRSR LIU Real Status Regi ster R
1004h LSIMR LIU Status Interrupt Mask Register R/W
1005h LLSR LIU Latched S tatus Regi ster R/W
1006h LRSL LIU Receive Signal Lev el Register R
1007 LRISMR LIU Receive Impedance and S ensi tivity Monitor Register R/W
1008h LRCR LIU Receive Control Register R/W
1009h–
101Fh — Reserved —
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 112 of 305
10.1.4 BERT Register L ist
Table 10-5. BERT Register List
Note th at on ly the B ER T 1 addres s is pres ente d her e. Th e sa m e set of reg is t ers defin it io ns applies for B ER Ts 2 to 4 in ac c or d ance with the
DS2651 4 m ap offsets . BER T of fs e t is [110 0+ (n - 1) x 10 hex], where n designates the BERT channel in question.
BERT RE GISTER LIS T
ADDRESS NAME DESCRIPTION R/W
1100h BAWC BERT Alt er nating Word Count Rate Regist er R
1101h BRP1 BERT Repetitive Pattern Set Register 1 R/W
1102h BRP2 BERT Repetitive Pattern Set Register 2 R/W
1103h BRP3 BERT Repetitive Pattern Set Register 3 R/W
1104h BRP4 BERT Repetitive Pattern Set Register 4 R/W
1105h BC1 BERT Cont r ol Register 1 R/W
1106h BC2 BERT Cont r ol Register 2 R/W
1107h BBC1 BERT Bit Count Regi ster 1 R
1108h BBC2 BERT Bit Count Register 2 R
1109h BBC3 BERT Bit Count Regi ster 3 R
110Ah BBC4 BERT Bit Count Register 4 R
110Bh BEC1 BERT Error Count Register 1 R
110Ch BEC2 BERT Error Count Regi ster 2 R
110Dh BEC3 BERT Error Count Regi ster 3 R
110Eh BSR BERT Latched St atus Register R
110Fh BSIM BERT Status Interrupt Mask Regi ster R/W
1400h
BC3
BERT Control Register 3
R/W
1401h
BRSR
BERT Real-Time Status Register
R
1402h
BLSR1
BERT Latched S tatus Register 1
R/W
1403h
BSIM1
BERT Status Interr upt Mask Regist er 1
R/W
1404h
BLSR2
BERT Latched S tatus Register 2
R/W
1405h
BSIM2
BERT Status Interr upt Mask Regi ster 2
R/W
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 113 of 305
10.1.5 HDLC-256 Register List
Table 10-6. HDLC-256 Register List
Note that only HDLC-256 1 Address is presented here. The same set of registers definitions applies for HDLC-256s 2 to 4 in accordance with
the DS26514 map offsets. HDLC-2 56 offset is {1 50 0+ (n-1) x 20 hex}, where n designates the HDLC-256 in q ues t ion.
HDLC-256 REGISTER LIST
ADDRESS
REGISTER
REGISTER DESCRIPTION
R/W
1500h
TH256CR1
Transmit HDLC-256 Cont r ol Register 1
R/W
1501h
TH256CR2
Transmit HDLC-256 Cont r ol Register 2
R/W
1502h
TH256FDR1
Transmit HDLC-256 FIFO Data Register 1
R/W
1503h
TH256FDR2
Transmit HDLC-256 FIFO Data Register 2
R/W
1504h
TH256SR1
Transmit HDLC-256 Stat us Regi ster 1
R
1505h
TH256SR2
Transmit HDLC-256 Stat us Regi ster 2
R
1506h
TH256SRL
Transmit HDLC-256 Stat us Regi ster Latched
R/W
1507h
Unused
—
1508h
TH256SRIE
Transmit HDLC-256 Stat us Regi ster Interrupt Enable
R/W
1509h
--
Unused
—
150Ah
--
Unused
—
150Bh
--
Unused
—
150Ch
--
Unused
—
150Dh
--
Unused
—
150Eh
--
Unused
—
150Fh
--
Unused
—
1510h
RH256CR1
Receive HDLC-256 Control Register 1
R/W
1511h
RH256CR2
Receive HDLC-256 Control Register 2
R/W
1512h
--
Unused
—
1513h
--
Unused
—
1514h
RH256SR
Receive HDLC-256 Status Regi ster
R
1515h
--
Unused
—
1516h
RH256SRL
Receive HDLC-256 Status Regi ster Latched
R/W
1517h
Unused
—
1518h
RH256SRIE
Receive HDLC-256 Status Register Interrupt Enable
R/W
1519h
--
Unused
—
151Ah
--
Unused
—
151Bh
--
Unused
—
151Ch
RH256FDR1
Receive HDLC-256 FIFO Dat a Register 1
R
151Dh
RH256FDR2
Receive HDLC-256 FIFO Dat a Register 2
R
151Eh
--
Unused
—
151Fh
--
Unused
—
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 114 of 305
10.2 Register Bit Maps
10.2.1 Global Register Bit Map
Table 10-7. Global Register Bit Map
ADDR
NAME
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
00F0h GTCR1 GPSEL3 GPSEL2 GPSEL1 — 528MD GIBO GCLE GIPI
00F1h GFCR1 IBOMS1 IBOMS0 BPCLK1 BPCLK0 — RFMSS TCBCS RCBCS
00F2h GTCR3 — — — — — — TSSYNCIOSEL
TSYNCSEL
00F3h
GTCCR1
BPREFSEL3
BPREFSEL2
BPREFSEL1
BPREFSEL0
BFREQSEL
FREQSEL
MPS1
MPS0
00F4h GTCCR3 RSYSCLKSEL
TSYSCLKSEL TCLKSEL CLKOSEL3 CLKOSEL2 CLKOSEL1 CLKOSEL0
00F5h
GHISR
HIS8
HIS7
HIS6
HIS5
HIS4
HIS3
HIS2
HIS1
00F6h GSRR1 — — — — H256RST LRST BRST FRST
00F7h
GHIMR
HIM8
HIM7
HIM6
HIM5
HIM4
HIM3
HIM2
HIM1
00F8h IDR ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
00F9h GFISR1 FIS8 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1
00FAh
GBISR1
BIS8
BIS7
BIS6
BIS5
BIS4
BIS3
BIS2
BIS1
00FBh GLISR1 LIS8 LIS7 LIS6 LIS5 LIS4 LIS3 LIS2 LIS1
00FCh GFIMR1 FIM8 FIM7 FIM6 FIM5 FIM4 FIM3 FIM2 FIM1
00FDh GBIMR1 BIM8 BIM7 BIM6 BIM5 BIM4 BIM3 BIM2 BIM1
00FEh GLIMR1 LIM8 LIM7 LIM6 LIM5 LIM4 LIM3 LIM2 LIM1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 115 of 305
10.2.2 Framer Register Bit Map
Table 10-8 contains the framer registers of the DS26514. Some registers have dual functionality based on the
selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are
shown bel ow using t wo li nes of text. The fi rst line of text is the bi t functi onality for T1/ J1 mode. The second l ine is
the bit f unctionalit y in E1 m ode, in italics. Bits that are not used f or an operating mode are denoted with a single
dash “—“. When there is only one set of bit defini tions listed for a register, the bit functionality does not change with
respect to the selection of T1/J1 or E1 mode. All registers not listed are reserv ed and should be initialized with a
value of 00h for proper operation. The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be
cal c ulated using the following formula: Address for Framer n = ( Framer 1 address + (n - 1) x 200hex) .
Table 10-8. Framer Register Bit Map
Table 10-9. Framer Register Bit Map
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
000h
E1RDMWE1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
001h
E1RDMWE2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
002h
E1RDMWE3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
003h
E1RDMWE4
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
010h RHC RCRCD RHR RHMS RHCS4 RHCS3 RHCS2 RHCS1 RHCS0
011h RHBSE BSE8 BSE7 BSE6 BSE5 BSE4 BSE3 BSE2 BSE1
012h RDS0SEL — — — RCM4 RCM3 RCM2 RCM1 RCM0
013h RSIGC — — — RFSA1 — RSFF RSFE RSIE
— — — CASMS — RSFF RSFE RSEI
014h T1RCR2 — — — RSLC96 OOF2 OOF1 RAIIE RRAIS
E1RSAIMR — — — RSa4IM RSa5IM RSa6IM RSa7IM RSa8IM
015h T1RBOCC RBR — RBD1 RBD0 — RBF1 RBF0 —
020h RIDR1 C7 C6 C5 C4 C3 C2 C1 C0
021h RIDR2 C7 C6 C5 C4 C3 C2 C1 C0
022h RIDR3 C7 C6 C5 C4 C3 C2 C1 C0
023h RIDR4 C7 C6 C5 C4 C3 C2 C1 C0
024h RIDR5 C7 C6 C5 C4 C3 C2 C1 C0
025h RIDR6 C7 C6 C5 C4 C3 C2 C1 C0
026h
RIDR7
C7
C6
C5
C4
C3
C2
C1
C0
027h RIDR8 C7 C6 C5 C4 C3 C2 C1 C0
028h RIDR9 C7 C6 C5 C4 C3 C2 C1 C0
029h RIDR10 C7 C6 C5 C4 C3 C2 C1 C0
02Ah RIDR11 C7 C6 C5 C4 C3 C2 C1 C0
02Bh RIDR12 C7 C6 C5 C4 C3 C2 C1 C0
02Ch RIDR13 C7 C6 C5 C4 C3 C2 C1 C0
02Dh
RIDR14
C7
C6
C5
C4
C3
C2
C1
C0
02Eh RIDR15 C7 C6 C5 C4 C3 C2 C1 C0
02Fh RIDR16 C7 C6 C5 C4 C3 C2 C1 C0
030h RIDR17 C7 C6 C5 C4 C3 C2 C1 C0
031h RIDR18 C7 C6 C5 C4 C3 C2 C1 C0
032h RIDR19 C7 C6 C5 C4 C3 C2 C1 C0
033h
RIDR20
C7
C6
C5
C4
C3
C2
C1
C0
034h
RIDR21
C7
C6
C5
C4
C3
C2
C1
C0
035h RIDR22 C7 C6 C5 C4 C3 C2 C1 C0
036h RIDR23 C7 C6 C5 C4 C3 C2 C1 C0
037h RIDR24 C7 C6 C5 C4 C3 C2 C1 C0
038h T1RSAOI1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 116 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RIDR25 C7 C6 C5 C4 C3 C2 C1 C0
039h T1RSAOI2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RIDR26 C7 C6 C5 C4 C3 C2 C1 C0
03Ah T1RSAOI3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RIDR27 C7 C6 C5 C4 C3 C2 C1 C0
03Bh RIDR28 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
03Ch T1RDMWE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RIDR29 C7 C6 C5 C4 C3 C2 C1 C0
03Dh T1RDMWE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RIDR30 C7 C6 C5 C4 C3 C2 C1 C0
03Eh T1RDMWE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RIDR31 C7 C6 C5 C4 C3 C2 C1 C0
03Fh RIDR32 — —
—
—
—
—
—
—
C7 C6 C5 C4 C3 C2 C1 C0
040h RS1 CH1-A CH1-B CH1-C CH1-D CH13-A CH13-B CH13-C CH13-D
0 0 0 0 X Y X X
041h RS2 CH2-A CH2-B CH2-C CH2-D CH14-A CH14-B CH14-C CH14-D
CH1-A CH1-B CH1-C CH1-D CH16-A CH16-B CH16-C CH16-D
042h RS3 CH3-A CH3-B CH3-C CH3-D CH15-A CH15-B CH15-C CH15-D
CH2-A CH2-B CH2-C CH2-D CH17-A CH17-B CH17-C CH17-D
043h RS4 CH4-A CH4-B CH4-C CH4-D CH16-A CH16-B CH16-C CH16-D
CH3-A CH3-B CH3-C CH3-D CH18-A CH18-B CH18-C CH18-D
044h RS5 CH5-A CH5-B CH5-C CH5-D CH17-A CH17-B CH17-C CH17-D
CH4-A CH4-B CH4-C CH4-D CH19-A CH19-B CH19-C CH19-D
045h RS6 CH6-A CH6-B CH6-C CH6-D CH18-A CH18-B CH18-C CH18-D
CH5-A
CH5-B
CH5-C
CH5-D
CH20-A
CH20-B
CH20-C
CH20-D
046h RS7 CH7-A CH7-B CH7-C CH7-D CH19-A CH19-B CH19-C CH19-D
CH6-A CH6-B CH6-C CH6-D CH21-A CH21-B CH21-C CH21-D
047h RS8 CH8-A CH8-B CH8-C CH8-D CH20-A CH20-B CH20-C CH20-D
CH7-A CH7-B CH7-C CH7-D CH22-A CH22-B CH22-C CH22-D
048h RS9 CH9-A CH9-B CH9-C CH9-D CH21-A CH21-B CH21-C CH21-D
CH8-A CH8-B CH8-C CH8-D CH23-A CH23-B CH23-C CH23-D
049h RS10 CH10-A CH10-B CH10-C CH10-D CH22-A CH22-B CH22-C CH22-D
CH9-A CH9-B CH9-C CH9-D CH24-A CH24-B CH24-C CH24-D
04Ah RS11 CH11-A CH11-B CH11-C CH11-D CH23-A CH23-B CH23-C CH23-D
CH10-A CH10-B CH10-C CH10-D CH25-A CH25-B CH25-C CH25-D
04Bh RS12 CH12-A CH12-B CH12-C CH12-D CH24-A CH24-B CH24-C CH24-D
CH11-A CH11-B CH11-C CH11-D CH26-A CH26-B CH26-C CH26-D
04Ch RS13 — — — — — — — —
CH12-A CH12-B CH12-C CH12-D CH27-A CH27-B CH27-C CH27-D
04Dh RS14 — — — — — — — —
CH13-A CH13-B CH13-C CH13-D CH28-A CH28-B CH28-C CH28-D
04Eh RS15 — — — — — — — —
CH14-A CH14-B CH14-C CH14-D CH29-A CH29-B CH29-C CH29-D
04Fh RS16 — — — — — — — —
CH15-A
CH15-B
CH15-C
CH15-D
CH30-A
CH30-B
CH30-C
CH30-D
050h LCVCR1 LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCVC8
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 117 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
051h LCVCR2 LCVC7 LCVC6 LCVC5 LCVC4 LCVC3 LCVC2 LCVC1 LCVC0
052h PCVCR1 PCVC15 PCVC14 PCVC13 PCVC12 PCVC11 PCVC10 PCVC9 PCVC8
053h PCVCR2 PCVC7 PCVC6 PCVC5 PCVC4 PCVC3 PCVC2 PCVC1 PCVC0
054h FOSCR1 FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8
055h FOSCR2 FOS7 FOS6 FOS5 FOS4 FOS3 FOS2 FOS1 FOS0
056h E1EBCR1 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8
057h E1EBCR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
058h FEACR1 FEACR15 FEACR14 FEACR13 FEACR12 FEACR11 FEACR10 FEACR9 FEACR8
059h FEACR2 FEACR7 FEACR6 FEACR5 FEACR4 FEACR3 FEACR2 FEACR1 FEACR0
05Ah FEBCR1 FEBCR15 FEBCR14 FEBCR13 FEBCR12 FEBCR11 FEBCR10 FEBCR9 FEBCR8
05Bh FEBCR2 FEBCR7 FEBCR6 FEBCR5 FEBCR4 FEBCR3 FEBCR2 FEBCR1 FEBCR0
060h RDS0M B1 B2 B3 B4 B5 B6 B7 B8
061h — — — — — — — — —
062h T1RFDL RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
E1RRTS7 CSC5 CSC4 CSC3 CSC2 CSC0 CRC4SA CASSA FASSA
063h T1RBOC — — RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0
064h T1RSLC1 C8 C7 C6 C5 C4 C3 C2 C1
E1RAF Si 0 0 1 1 0 1 1
065h T1RSLC2 M2 M1 S=0 S=1 S=0 C11 C10 C9
E1RNAF Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
066h T1RSLC3 S=1 S4 S3 S2 S1 A2 A1 M3
E1RsiAF SiF14 SiF12 SiF10 SiF8 SiF6 SiF4 SiF2 SiF0
067h E1RSiNAF SiF15 SiF13 SiF11 SiF9 SiF7 SiF5 SiF3 SiF1
068h E1RRA RRAF15 RRAF13 RRAF11 RRAF9 RRAF7 RRAF5 RRAF3 RRAF1
069h E1RSa4 RSa4F15 RSa4F13 RSa4F11 RSa4F9 RSa4F7 RSa4F5 RSa4F3 RSa4F1
06Ah E1RSa5 RSa5F15 RSa5F13 RSa5F11 RSa5F9 RSa5F7 RSa5F5 RSa5F3 RSa5F1
06Bh E1RSa6 RSa6F15 RSa6F13 RSa6F11 RSa6F9 RSa6F7 RSa6F5 RSa6F3 RSa6F1
06Ch E1RSa7 RSa7F15 RSa7F13 RSa7F11 RSa7F9 RSa7F7 RSa7F5 RSa7F3 RSa7F1
06Dh E1RSa8 RSa8F15 RSa8F13 RSa8F11 RSa8F9 RSa8F7 RSa8F5 RSa8F3 RSa8F1
06Eh SaBITS — — — Sa4 Sa5 Sa6 Sa7 Sa8
06Fh Sa6CODE — — — — Sa6n Sa6n Sa6n Sa6n
080h RMMR FRM_EN INIT_DONE DRSS — — — SFTRST T1/E1
081h RCR1 (T1) SYNCT RB8ZS RFM ARC SYNCC RJC SYNCE RESYNC
RCR1 (E1) — RHDB3 RSIGM RG802 RCRC4 FRC SYNCE RESYNC
082h T1RIBCC — — RUP2 RUP1 RUP0 RDN2 RDN1 RDN0
E1RCR2 — — — — — — — RLOSA
083h RCR3 — uALAW RSERC BINV1 BINV0 — PLB FLB
084h RIOCR RCLKINV RSYNCINV H100EN RSCLKM RSMS RSIO RSMS2 RSMS1
RCLKINV RSYNCINV H100EN RSCLKM — RSIO RSMS2 RSMS1
085h RESCR RDATFMT RGCLKEN — RSZS RESALGN RESR RESMDM RESE
086h ERCNT 1SECS MCUS MECU ECUS EAMS FSBE MOSCRF LCVCRF
1SECS MCUS MECU ECUS EAMS — — LCVCRF
087h RHFC — — — — — — RFHWM1 RFHWM0
088h RIBOC — — — IBOSEL IBOEN — — —
089h T1RSCC — — — — — RSC2 RSC1 RSC0
08Ah RXPC
RHMS
RHEN
— — — RBPDIR RBPFUS RBPEN
RHMS RHEN — — — RBPDIR — RBPEN
08Bh RBPBS BPBSE8 BPBSE7 BPBSE6 BPBSE5 BPBSE4 BPBSE3 BPBSE2 BPBSE1
08Ch -
-
-
-
-
-
-
-
-
08Dh RHBS
RHBSE8
RHBSE7
RHBSE6
RHBSE5
RHBSE4
RHBSE3
RHBSE2
RHBSE1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 118 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
090h RLS1 RRAIC RAISC RLOSC RLOFC RRAID RAISD RLOSD RLOFD
091h RLS2 (T1) — — COFA 8ZD 16ZD SEFE B8ZS FBE
RLS2 (E1) — CRCRC CASRC FASRC RSA1 RSA0 RCMF RAF
092h RLS3 (T1) LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD
RLS3 (E1) LORCC — V52LNKC RDMAC LORCD — V52LNKD RDMAD
093h RLS4 RESF RESEM RSLIP — RSCOS 1SEC TIMER RMF
094h RLS5 — — ROVR RHOBT RPE RPS RHWMS RNES
096h RLS7 (T1) — — RRAI-CI RAIS-CI RSLC96 RFDLF BC BD
RLS7 (E1) — — — — — — Sa6CD SaXCD
097h — — — — — — — — —
098h RSS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
099h RSS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
09Ah RSS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
09Bh RSS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
09Ch T1RSCD1 C7 C6 C5 C4 C3 C2 C1 C0
—
—
—
—
—
—
—
—
09Dh T1RSCD2 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
09Fh RIIR — RLS7 RLS6* RLS5 RLS4 RLS3 RLS2** RLS1
0A0h RIM1 RRAIC RAISC RLOSC RLOFC RRAID RAISD RLOSD RLOFD
0A1h RIM2 — — — — — — — —
— — — — RSA1 RSA0 RCMF RAF
0A2h RIM3 (T1) LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD
RIM3 (E1) LORCC — V52LNKC RDMAC LORCD — V52LNKD RDMAD
0A3h RIM4 RESF RESEM RSLIP — RSCOS 1SEC TIMER RMF
0A4h RIM5 — — ROVR RHOBT RPE RPS RHWMS RNES
0A6h RIM7 (T1) — — RRAI-CI RAIS-CI RSLC96 RFDLF BC BD
RIM7 (E1) — — — — Sa6CD SaXCD
0A8h RSCSE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0A9h RSCSE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0AAh RSCSE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0ABh RSCSE4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
0ACh T1RUPCD1 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
0ADh T1RUPCD2 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
0AEh T1RDNCD1 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
0AFh T1RDNCD2 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
0B0h RRTS1 — — — — RRAI RAIS RLOS RLOF
0B2h RRTS3 (T1) — — — — LORC LSP LDN LUP
RRTS3 (E1) — — — — LORC — V52LNK RDMA
0B4h RRTS5 — PS2 PS1 PS0 — — RHWM RNE
0B5h RHPBA MS RPBA6 RPBA5 RPBA4 RPBA3 RPBA2 RPBA1 RPBA0
0B6h RHF RHD7 RHD6 RHD5 RHD4 RHD3 RHD2 RHD1 RHD0
0C0h RBCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0C1h RBCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 119 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0C2h RBCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0C3h RBCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
0C4h
RCBR1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
0C5h
RCBR2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
0C6h RCBR3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0C7h RCBR4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25(F-bit)
0C8h RSI1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0C9h RSI2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0CAh RSI3 CH24 CH23 CH22 CH21 CH200 CH19 CH18 CH17
0CBh RSI4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
0CCh RGCCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0CDh RGCCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0CEh RGCCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0CFh RGCCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25(F-bit)
0D0h RCICE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0D1h RCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0D2h RCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0D3h RCICE4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
0D4h RBPCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0D5h RBPCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0D6h RBPCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0D7h RBPCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
0DCh RHCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
0DDh RHCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
0DEh RHCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
0DFh RHCS4
-
CH32
-
CH31
-
CH30
-
CH29
-
CH28
-
CH27
-
CH26
-
CH25
100h TDMWE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
101h TDMWE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
102h TDMWE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
103h TDMWE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
104h
TJBE1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
105h TJBE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
106h TJBE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
107h TJBE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
108h TDDS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
109h TDDS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
10Ah TDDS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
110h
THC1
NOFS
TEOML
THR
THMS
TFS
TEOM
TZSD
TCRCD
111h THBSE TBSE8 TBSE7 TBSE6 TBSE5 TBSE4 TBSE3 TBSE2 TBSE1
113h THC2 TABT SBOC THCEN THCS4 THCS3 THCS2 THCS1 THCS0
TABT — THCEN THCS4 THCS3 THCS2 THCS1 THCS0
118h SSIE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
119h
SSIE2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 120 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
11Ah SSIE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
11Bh SSIE4 — — — — — — — —
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
120h TIDR1 C7 C6 C5 C4 C3 C2 C1 C0
121h TIDR2 C7 C6 C5 C4 C3 C2 C1 C0
122h TIDR3 C7 C6 C5 C4 C3 C2 C1 C0
123h TIDR4 C7 C6 C5 C4 C3 C2 C1 C0
124h TIDR5 C7 C6 C5 C4 C3 C2 C1 C0
125h TIDR6 C7 C6 C5 C4 C3 C2 C1 C0
126h
TIDR7
C7
C6
C5
C4
C3
C2
C1
C0
127h TIDR8 C7 C6 C5 C4 C3 C2 C1 C0
128h TIDR9 C7 C6 C5 C4 C3 C2 C1 C0
129h TIDR10 C7 C6 C5 C4 C3 C2 C1 C0
12Ah TIDR11 C7 C6 C5 C4 C3 C2 C1 C0
12Bh TIDR12 C7 C6 C5 C4 C3 C2 C1 C0
12Ch TIDR13 C7 C6 C5 C4 C3 C2 C1 C0
12Dh
TIDR14
C7
C6
C5
C4
C3
C2
C1
C0
12Eh TIDR15 C7 C6 C5 C4 C3 C2 C1 C0
12Fh TIDR16 C7 C6 C5 C4 C3 C2 C1 C0
130h TIDR17 C7 C6 C5 C4 C3 C2 C1 C0
131h TIDR18 C7 C6 C5 C4 C3 C2 C1 C0
132h TIDR19 C7 C6 C5 C4 C3 C2 C1 C0
133h TIDR20 C7 C6 C5 C4 C3 C2 C1 C0
134h TIDR21 C7 C6 C5 C4 C3 C2 C1 C0
135h TIDR22 C7 C6 C5 C4 C3 C2 C1 C0
136h TIDR23 C7 C6 C5 C4 C3 C2 C1 C0
137h TIDR24 C7 C6 C5 C4 C3 C2 C1 C0
138h TIDR25 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
139h TIDR26 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
13Ah TIDR27 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
13Bh TIDR28 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
13Ch TIDR29 — — — — — — — —
C7
C6
C5
C4
C3
C2
C1
C0
13Dh TIDR30 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
13Eh TIDR31 — — — — — — — —
C7
C6
C5
C4
C3
C2
C1
C0
13Fh TIDR32 — — — — — — — —
C7 C6 C5 C4 C3 C2 C1 C0
140h TS1 CH1-A CH1-B CH1-C CH1-D CH13-A CH13-B CH13-C CH13-D
0 0 0 0 X Y X X
141h TS2 CH2-A CH2-B CH2-C CH2-D CH14-A CH14-B CH14-C CH14-D
CH1-A CH1-B CH1-C CH1-D CH16-A CH16-B CH16-C CH16-D
142h TS3 CH3-A CH3-B CH3-C CH3-D CH15-A CH15-B CH15-C CH15-D
CH2-A CH2-B CH2-C CH2-D CH17-A CH17-B CH17-C CH17-D
143h TS4 CH4-A CH4-B CH4-C CH4-D CH16-A CH16-B CH16-C CH16-D
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 121 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CH3-A CH3-B CH3-C CH3-D CH18-A CH18-B CH18-C CH18-D
144h TS5 CH5-A CH5-B CH5-C CH5-D CH17-A CH17-B CH17-C CH17-D
CH4-A CH4-B CH4-C CH4-D CH19-A CH19-B CH19-C CH19-D
145h TS6 CH6-A CH6-B CH6-C CH6-D CH18-A CH18-B CH18-C CH18-D
CH5-A CH5-B CH5-C CH5-D CH20-A CH20-B CH20-C CH20-D
146h TS7 CH7-A CH7-B CH7-C CH7-D CH19-A CH19-B CH19-C CH19-D
CH6-A CH6-B CH6-C CH6-D CH21-A CH21-B CH21-C CH21-D
147h TS8 CH8-A CH8-B CH8-C CH8-D CH20-A CH20-B CH20-C CH20-D
CH7-A CH7-B CH7-C CH7-D CH22-A CH22-B CH22-C CH22-D
148h TS9 CH9-A CH9-B CH9-C CH9-D CH21-A CH21-B CH21-C CH21-D
CH8-A CH8-B CH8-C CH8-D CH23-A CH23-B CH23-C CH23-D
149h TS10 CH10-A CH10-B CH10-C CH10-D CH22-A CH22-B CH22-C CH22-D
CH9-A CH9-B CH9-C CH9-D CH24-A CH24-B CH24-C CH24-D
14Ah TS11 CH11-A CH11-B CH11-C CH11-D CH23-A CH23-B CH23-C CH23-D
CH10-A
CH10-B
CH10-C
CH10-D
CH25-A
CH25-B
CH25-C
CH25-D
14Bh TS12 CH12-A CH12-B CH12-C CH12-D CH24-A CH24-B CH24-C CH24-D
CH11-A CH11-B CH11-C CH11-D CH26-A CH26-B CH26-C CH26-D
14Ch TS13 — — — — — — — —
CH12-A CH12-B CH12-C CH12-D CH27-A CH27-B CH27-C CH27-D
14Dh TS14 — — — — — — — —
CH13-A CH13-B CH13-C CH13-D CH28-A CH28-B CH28-C CH28-D
14Eh TS15 — — — — — — — —
CH14-A CH14-B CH14-C CH14-D CH29-A CH29-B CH29-C CH29-D
14Fh TS16 — — — — — — — —
CH15-A CH15-B CH15-C CH15-D CH30-A CH30-B CH30-C CH30-D
150h TCICE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
151h TCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
152h TCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
153h TCICE4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
162h T1TFDL TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0
— — — — — — — —
163h T1TBOC — — TBOC5 TBOC4 TBOC3 TBOC2 TBOC1 TBOC0
— — — — — — — —
164h T1TSLC1 C8 C7 C6 C5 C4 C3 C2 C1
E1TAF Si 0 0 1 1 0 1 1
165h T1TSLC2 M2 M1 S=0 S=1 S=0 C11 C10 C9
E1TNAF Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
166h T1TSLC3 S=1 S4 S3 S2 S1 A2 A1 M3
E1TSiAF TSiF14 TSiF12 TSiF10 TSiF8 TSiF6 TSiF4 TSiF2 TSiF0
167h E1TSiNAF — — — — — — — —
TsiF15 TSiF13 TSiF11 TSiF9 TSiF7 TSiF5 TSiF3 TSiF1
168h E1TRA — — — — — — — —
TRAF15 TRAF13 TRAF11 TRAF9 TRAF7 TRAF5 TRAF3 TRAF1
169h E1TSa4 — — — — — — — —
TSa4F15
TSa4F13
TSa4F11
TSa4F9
TSa4F7
TSa4F5
TSa4F3
TSa4F1
16Ah E1TSa5 — — — — — — — —
TSa5F15 TSa5F13 TSa5F11 TSa5F9 TSa5F7 TSa5F5 TSa5F3 TSa5F1
16Bh E1TSa6 — — — — — — — —
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 122 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TSa6F15 TSa6F13 TSa6F11 TSa6F9 TSa6F7 TSa6F5 TSa6F3 TSa6F1
16Ch E1TSa7 — — — — — — — —
TSa7F15 TSa7F13 TSa7F11 TSa7F9 TSa7F7 TSa7F5 TSa7F3 TSa7F1
16Dh E1TSa8 — — — — — — — —
TSa8F15 TSa8F13 TSa8F11 TSa8F9 TSa8F7 TSa8F5 TSa8F3 TSa8F1
180h TMMR FRM_EN INIT_DONE — — — — SFTRST T1/E1
181h TCR1 (T1) TJC TFPT TCPT TSSE GB7S TB8ZS TAIS TRAI
TCR1 (E1) TTPT T16S TG802 TSiS TSA1 THDB3 TAIS TCRC4
182h
T1.TCR2
(T1) TFDLS TSLC96 TDDSEN FBCT2 FBCT1 TRAIS — TB7ZS
E1.TCR2
(E1) AEBE AAIS ARA — — — — —
183h TCR3
—
—
TCSS1
TCSS0
MFRS
TFM
IBPV
TLOOP
— — TCSS1 TCSS0 MFRS — IBPV CRC4R
184h TIOCR TCLKINV TSYNCINV TSSYNCINV TSCLKM TSSM TSIO TSDW TSM
TCLKINV TSYNCINV TSSYNCINV TSCLKM TSSM TSIO — TSM
185h TESCR TDATFMT TGCLKEN —— TSZS TESALGN TESR TESMDM TESE
186h TCR4 uALAW BINV1 BINV0 TJBEN TRAIM TAISM TC1 TC0
uALAW BINV1 BINV0 TJBEN — — — —
187h THFC — — — — — — TFLWM1 TFLWM0
188h TIBOC — — — IBOSEL IBOEN — — —
189h TDS0SEL — — — TCM4 TCM3 TCM2 TCM1 TCM0
18Ah
TXPC
THMS
THEN
—
—
—
TBPDIR
TBPFUS
TBPEN
18Bh
TBPBS
BPBSE8
BPBSE7
BPBSE6
BPBSE5
BPBSE4
BPBSE3
BPBSE2
BPBSE1
18Dh
THBS
THBSE8 THBSE7 THBSE6 THBSE5 THBSE4 THBSE3 THBSE2 THBSE1
18Eh TSYNCC — — — — — TSEN SYNCE RESYNC
— — — — CRC4 TSEN SYNCE RESYNC
190h TLS1 TESF TESEM TSLIP TSLC96 — TMF LOTCC LOTC
TESF TESEM TSLIP — TAF TMF LOTCC LOTC
191h TLS2 — — — TFDLE TUDR TMEND TLWMS TNFS
— — — — TUDR TMEND TLWMS TNFS
192h TLS3 — — — — — — LOF LOFD
19Fh TIIR — — — — — TLS3 TLS2 TLS1
1A0h TIM1 TESF TESEM TSLIP TSLC96 — TMF LOTCC LOTC
TESF TESEM TSLIP — TAF TMF LOTCC LOTC
1A1h TIM2 — — — TFDLE TUDR TMEND TLWMS TNFS
— — — — TUDR TMEND TLWMS TNFS
1A2h TIM3 — — — — — — — LOFD
1ACh T1TCD1 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
1ADh T1TCD2 C7 C6 C5 C4 C3 C2 C1 C0
— — — — — — — —
1B1h TRTS2 — — — — TEMPTY TFULL TLWM TNF
1B3h TFBA —— TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0
1B4h THF THD7 THD6 THD5 THD4 THD3 THD2 THD1 THD0
1BBh TDS0M B1 B2 B3 B4 B5 B6 B7 B8
1C0h TBCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
1C1h TBCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1C2h TBCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 123 of 305
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1C3h TBCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
1C4h
TCBR1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
1C5h TCBR2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1C6h TCBR3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
1C7h TCBR4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25:Fbit
1C8h THSCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
1C9h THSCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1CAh THSCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
1CBh THSCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
1CCh TGCCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
1CDh TGCCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1CEh TGCCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
1CFh TGCCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25(F-bit)
1D0h PCL1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
1D1h PCL2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1D2h PCL3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
1D3h PCL4
—
—
—
—
—
—
—
—
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
1D4h TBPCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
1D5h TBPCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
1D6h
TBPCS3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
1D7h TBPCS4 — — — — — — — —
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
1D8h –
1DBh
Reserved
1DCh
THCS1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
1DDh
THCS2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
1DEh
THCS3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
1DFh THCS4
-
CH32
-
CH31
-
CH30
-
CH29
-
CH28
-
CH27
-
CH26
-
CH25
*RLS6 is reserved for future use.
**Currently, RLS2 does not crea te an interru pt , th er e fore th is b it is no t use d in T1 m ode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 124 of 305
10.2.3 LIU Register Bit Map
Table 10-10. LIU Reg ister Bit Map
ADDR
NAME
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
1000h LTRCR — RHPM JADS1 JADS0 JAPS1 JAPS0 T1J1E1S LSC
1001h LTIPSR TG703 TIMPTON TIMPL1 TIMPL0 — L2 L1 L0
1002h LMCR TAIS ATAIS LB2 LB1 LB0 TPDE RPDE TE
1003h LRSR — — OEQ UEQ RSCS TSCS OCS LOSS
1004h LSIMR JALTCIM OCCIM SCCIM LOSCIM JALTSIM OCDIM SCDIM LOSDIM
1005h LLSR JALTC OCC SCC LOSC JALTS OCD SCD LOSD
1006h LRSL RSL3 RSL2 RLS1 RLS0 — — — —
1007h LRISMR — RIMPON — — — RIMPM2 RIMPM1 RIMPM0
1008h
LRCR
RG703
—
—
—
RTR
RMONEN
RSMS1
RSMS0
1009h–
101Fh Test
Registers — — — — — — — —
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 125 of 305
10.2.4 BERT Register Bit Map
Table 10-11. BERT Register Bit Map
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1100h
BAWC
ACNT7
ACNT6
ACNT5
ACNT4
ACNT3
ACNT2
ACNT1
ACNT0
1101h
BRP1
RPAT7
RPAT6
RPAT5
RPAT4
RPAT3
RPAT2
RPAT1
RPAT0
1102h
BRP2
RPAT15
RPAT14
RPAT13
RPAT12
RPAT11
RPAT10
RPAT9
RPAT8
1103h
BRP3
RPAT23
RPAT22
RPAT21
RPAT20
RPAT19
RPAT18
RPAT17
RPAT16
1104h
BRP4
RPAT31
RPAT30
RPAT29
RPAT28
RPAT27
RPAT26
RPAT25
RPAT24
1105h
BC1
TC
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
1106h
BC2
EIB2
EIB1
EIB0
SBE
RPL3
RPL2
RPL1
RPL0
1107h
BBC1
BBC7
BBC6
BBC5
BBC4
BBC3
BBC2
BBC1
BBC0
1108h
BBC2
BBC15
BBC14
BBC13
BBC12
BBC11
BBC10
BBC9
BBC8
1109h
BBC3
BBC23
BBC22
BBC21
BBC20
BBC19
BBC18
BBC17
BBC16
110Ah
BBC4
BBC31
BBC30
BBC29
BBC28
BBC27
BBC26
BBC25
BBC24
110Bh
BEC1
EC7
EC6
EC5
EC4
EC3
EC2
EC1
EC0
110Ch
BEC2
EC15
EC14
EC13
EC12
EC11
EC10
EC9
EC8
110Dh
BEC3
EC23
EC22
EC21
EC20
EC19
EC18
EC17
EC16
110Eh
BSR
—
BBED
RBRA01
RSYNC
BRA1
BRA0
BRLOS
BSYNC
110Fh
BSIM
—
BBED
BBCO
BECO
BRA1
BRA0
BRLOS
BSYNC
1400h
BC3
—
—
—
—
—
—
55OCT
BALIGN
1401h
BRSR
—
—
—
—
BRA1
BRA0
BRLOS
BSYNC
1402h
BLSR1
BRA1C
BRA0C
BRLOSC
BSYNCC
BRA1D
BRA0D
BRLOSD
BSYNCD
1403h
BSIM1
BRA1C
BRA0C
BRLOSC
BSYNCC
BRA1D
BRA0D
BRLOSD
BSYNCD
1404h
BLSR2
—
—
—
—
—
BED
BBCO
BECO
1405h
BSIM2
—
—
—
—
—
BED
BBCO
BECO
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 126 of 305
10.2.5 HDLC-256 Register Bit Map
Table 10-12. HDLC-256 Register Bit Map
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1500h
TH256CR1
--
TPSD
TFEI
TIFV
TBRE
TDIE
TFPD
TFRST
1501h
TH256CR2
--
--
--
TDAL4
TDAL3
TDAL2
TDAL1
TDAL0
1502h
TH256FDR1
--
--
--
--
--
--
--
TDPE
1503h
TH256FDR2
TFD7
TFD6
TFD5
TFD4
TFD3
TFD2
TFD1
TFD0
1504h
TH256SR1
--
--
--
--
--
TFF
TFE
THDA
1505h
TH256SR2
--
--
TFFL5
TFFL4
TFFL3
TFFL2
TFFL1
TFFL0
1506h
TH256SRL
--
--
TFOL
TFUL
TPEL
--
TFEL
THDAL
1507h
--
--
--
--
--
--
--
--
--
1508h
TH256SRIE
--
--
TFOIE
TFUIE
TPEIE
--
TFEIE
THDAIE
1509h-
150Fh
--
--
--
--
--
--
--
--
--
1510h
RH256CR1
--
--
--
--
RBRE
RDIE
RFPD
RFRST
1511h
RH256CR2
--
--
--
RDAL4
RDAL3
RDAL2
RDAL1
RDAL0
1512h
--
--
--
--
--
--
--
--
--
1513h
--
--
--
--
--
--
--
--
--
1514h
RH256SR
--
--
--
--
--
RFF
RFE
RHDA
1515h
--
--
--
--
--
--
--
--
--
1516h
RH256SRL
RFOL
--
--
RPEL
RPSL
RFFL
--
RHDAL
1517h
1518h
RH256SRIE
RFOIE
--
--
RPEIE
RPSIE
RFFIE
--
RHDAIE
1519h
--
--
--
--
--
--
--
--
--
151Ah
--
--
--
--
--
--
--
--
--
151Bh
--
--
--
--
--
--
--
--
--
151Ch
RH256FDR1
--
--
--
--
RPS2
RPS1
RPS0
RFDV
151Dh
RH256FDR2
RFD7
RFD6
RFD5
RFD4
RFD3
RFD2
RFD1
RFD0
151Eh
--
--
--
--
--
--
--
--
--
151Fh
--
--
--
--
--
--
--
--
--
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 127 of 305
10.3 Glob a l Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
fram er i nterr upt stat us, IBO confi guration, MCLK c onfigurat i on, and BP CLK1 conf i gurati on. The gl obal r egister s bit
descriptions are presented below.
Table 10-13. Global Register Set
ADDRESS NAME DESCRIPTION R/W
00F0h GTCR1 Global Transceiver Contr ol Register 1 R/W
00F1h GFCR1 Global Fram er Control Register 1 R/W
00F2h GTCR3 Global Transceiver Contro l Register 3 R/W
00F3h GTCCR1 Global Transceiver Cl ock Cont r ol Register 1 R/W
00F4h GTCCR3 Global Transceiver Cl ock Cont r ol Register 3 R/W
00F5h — Reserved —
00F6h GSRR1 Global S oft ware Reset Regi ster 1 R/W
00F7h — Reserved —
00F8h IDR De vice Identification Regis ter R
00F9h GFISR1 Globa l Fra mer Interrupt Status Register 1 R
00FAh GBISR1 Global B E RT Inter r upt Status Register 1 R
00FBh GLISR1 Global LIU Interrupt Status Regi ster 1 R
00FCh GFIMR1 Global Fram er s Interrupt Mask Register 1 RW
00FDh GBIMR1 Global B E RT Inter r upt Mask Register 1 RW
00FEh GLIMR1 Global LIU Interrupt Mask Regi ster 1 RW
Not e 1: Reserved registers should only be written with all zeros.
Note 2:
The global registers are located in the framer address space. The corresponding address spa ce for the other seven framers is
“Reser ved ,” an d sh ou ld be initi ali z ed w it h all z eros f or pr op er op erati on.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 128 of 305
Register Name
GTCR1
Register Desc r iptio n:
Global T ranscei ver Control Regi st er 1
Register Addr ess :
00F0h
Bit #
7
6
5
4
3
2
1
0
Name
GPSEL3
GPSEL2
GPSEL1
—
524MD
GIBO
GCLE
GIPI
Default
0
0
0
0
0
0
0
0
Bits 7 to 5: Gen eral-Purpose I/O Pins Select (GPSEL[3:1])
Table 10-14. Output Status Control
GPSEL[3:1]
RLF/LTC[4:1]
AL/RSIGF/FLOS[4:1]
000
RLF
AL
001
LTC
AL
010
RLF
RSIGF
011
LTC
RSIGF
100
RLF
FLOS
101
LTC
FLOS
110
Reserved
Reserved
111
Reserved
Reserved
Bit 3: DS 26524 Mode (524MD)
0 = Normal operation.
1 = Pi n definitions switch to DS26524 pins to obtai n pin c om patibility with the DS26524.
Normal Op erat io n
524MD
RSYSCLK[4:2]
RLF/LTC[4:2]
RSYSCLK1
RSYSCLK1
CLKO
RLF/LTC1
TSYSCLK[4:2]
AL/RSIGF/FLOS[4:2]
TSYSCLK1
TSYSCLK1
SPI_SEL
AL/RSIGF/FLOS1
TSYNC/TSSYNCIO[4:1]
TSYNC[4:1]
(Tie low—unused)
TSSYNCIO
Bit 2: Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an
ex ternal “wire-OR” oper ation. Normally this bit shoul d be set = 0 and the inter nal m ux used.
0 = Use i nternal IBO m ux.
1 = Ext er nally “wir e-OR” TSERn and RS E Rn for IBO operation.
Note: Setting GIBO disables the internal IBO mux. GFCR1 must be set to inform the framers of the IBO
configuration.
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
fram er performanc e monitor c ounters. Each framer can be i ndependently enabled to accept this input. This bit must
be cl ear ed and set again to perform anot her counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI)
0 = Normal Oper ation. Interr upt pin (INTB) will toggle low on an unmasked interrupt c ondition.
1 = Interrupt Inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 129 of 305
Register Name:
GFCR1
Description:
Global Framer Control Regi st er 1
Register Addr ess :
00F1h
Bit #
7
6
5
4
3
2
1
0
Name
IBOMS1
IBOMS0
BPCLK1
BPCLK0
—
RFMSS
TCBCS
RCBCS
Default
0
0
0
0
0
0
0
0
Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine the
configuration of the IBO (interleaved bus) multiplexer and inf orm the framers of the IBO configuration. These bits
should be used in conjuncti on with the Rx and Tx IBO cont rol registers withi n each of the framer unit s. These bit s
contr ol Channel s 1 to 4. Additi onal i nformati on concerni ng t he IBO multi plexer i s given in S ection 9.8.2. These bit s
m ust be set whether usi ng the internal I BO m ux or externally gangi ng the pi ns.
IBOMS1
IBOMS0
IBO Mode
0
0
IBO disabled.
0
1
2 devi c es on bus (4.096MHz ) .
1
0
4 devi c es on bus (8.192MHz ) .
1
1
8 devi c es on bus (16.384MHz ) .**
**The DS26514 is limited to sl ots 1-4 in this mode. The DS26514 cannot be assigned t o sl ots 5-8.
Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequenc y output on
the BP CLK 1 pin.
BPCLK1
BPCLK0
BPCLK1 Frequency
0
0
2.048MHz
0
1
4.096MHz
1
0
8.192MHz
1
1
16.384MHz
Bit 2: Receive Frame/Multiframe S ync Select ( RFMSS). This bit controls the func tion of all four
RMSYNCn/RFSYNCn pi ns.
0 = RMSYNC/RFSY NC[4:1] pi ns output RFSYNC[4: 1] (Receive Frame Sync)
1 = RMSYNC/RFSY NC[4:1] pi ns output RMSYNC[4:1] (Receive Multifram e S y nc)
Bit 1: Tran smit Channel Block/Clock S elect (T CBCS). This bit c ontrols the function of all f our
TCHBLK n/TCHCLKn pins.
0 = TCHBLK /T CHCLK [4:1] pi ns output TCHBLK[4:1] (Transmi t Channel Block)
1 = TCHBLK /T CHCLK [4:1] pi ns output TCHCLK[4:1] (Transmit Channel Cloc k )
Bit 0: Receive Chann el Block/Clock Select (RCBCS). This bit cont r ols the function of all four
RCHBLKn/ RCHCLK n pins.
0 = RCHB LK/RCHCLK [4:1] pins output RCHBLK[4:1] (Receive Channel Bloc k )
1 = RCHB LK/RCHCLK [4:1] pins output RCHCLK[4:1] (Receive Channel Clock)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 130 of 305
Register Name:
GTCR3
Register Description:
Global Transceiver Cont rol Register 3
Register Addr ess :
00F2h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
TSSYNCIOSEL
TSYNCSEL
Default
0
0
0
0
0
0
0
0
Bit 1: Tran smit System Synchronization I/O Select (TSS Y NCIO S EL)
0 = TSSYNCIO[4:1] are input s on TS Y NC/T SSYNCIO [4: 1] pi ns
1 = TSSYNCI O[ 4:1] are outputs synchronous to BP CLK 1.
Bit 0: TSYNCn/TSSYNCIOn Pin Select (TSYNCSEL)
0 = TSY NCn is selected for TSYNC/T S S Y NCIO[4:1] pins
1 = TSSYNCI On is selected for TSY NC/T S S Y NCIO[4:1] pins
Note: If TSY NCn is select ed, c ontrol of T SYNCn (I/O ) is v ia t he TIOCR register. TS SYNCIOn is norm all y selected
when transmit elastic stores are enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 131 of 305
Register Name:
GTCCR1
Register Desc r iptio n:
Global Transceiver Clock Con t rol Register 1
Register Addr ess :
00F3h
Bit #
7
6
5
4
3
2
1
0
Name
BPREFSEL3
BPREFSEL2
BPREFSEL1
BPREFSEL0
BFREQSEL
FREQSEL
MPS1
MPS0
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock
source will be used for B P CLK 1 gener ation. The BPCLK1 can be gener ated from LIU’s 1 to 4 r ec overed cl oc ks, an
external reference, or derivatives of MCLK input. This is shown in Table 10-16. See Figure 9-9 for additional
information.
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
ref erenc e clock frequenc y used by the DS26514 back pl ane cl ock generation ci rcuit . Note that t he setting of this bit
should match the T1E1 selec tion for the LIU whose recovered clock is being used to gen er ate the backplane clock.
See Figure 9-9 for additional informati on.
0 = Backplane reference cloc k i s 2.048M Hz .
1 = Backplane reference cloc k is 1.544M Hz .
Bit 2: Freq uen cy Select ion (FREQS EL). I n conj unction wi th t he MPS[ 1:0] bits, t hi s bit selec ts the ex t ernal MCLK
frequenc y of the si gnal input at the MCLK pin of the DS26514.
0 = The e xterna l master clock is 2.048MHz or m ultipl e thereof.
1 = The external m aster cl oc k is 1.544MHz or m ultipl e thereof.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequenc y of t he si gnal input at the MCLK pin of the DS26514. This is shown in Table 10-15.
Table 10-15. Master Clock Input Selection
FREQSEL MPS1 MPS0 MCLK
(MHz ± 50pp m)
0
0
0
2.048
0
0
1
4.096
0
1
0
8.192
0
1
1
16.384
1
0
0
1.544
1
0
1
3.088
1
1
0
6.176
1
1
1
12.352
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 132 of 305
Table 10-16. Backplane Reference Clock Select
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL
REFE RE NCE CLOCK
SOURCE
0
0
0
0
0
2.048MHz RCLK 1
0
0
0
0
1
1.544MHz RCLK 1
0
0
0
1
0
2.048MHz RCLK 2
0
0
0
1
1
1.544MHz RCLK 2
0
0
1
0
0
2.048MHz RCLK 3
0
0
1
0
1
1.544MHz RCLK 3
0
0
1
1
0
2.048MHz RCLK 4
0
0
1
1
1
1.544MHz RCLK 4
1 0 0 0 0
2.048MHz derived fro m
MCLK. (REFCLKI O is an
output.)
1 0 0 0 1
1.544MHz derived fro m
MCLK. ( REFCLK IO is an
output.)
1 0 0 1 0
2.048MHz ex ternal clock
input at REFCLKIO.
(REF CLK IO is an i nput. )
1 0 0 1 1
1.544MHz ex ternal clock
input at REFCLKIO.
(REF CLK IO is an i nput. )
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 133 of 305
Register Name:
GTCCR3
Register Desc r iptio n:
Global Transceiver Clock Con t rol Register 3
Register Addr ess :
00F4h
Bit #
7
6
5
4
3
2
1
0
Name
—
RSYSCLKSEL
TSYSCLKSEL
TCLKSEL
CLKOSEL3
CLKOSEL2
CLKOSEL1
CLKOSEL0
Default
0
0
0
0
0
0
0
0
Bit 6: RSYSCLKn Select (RSYSCLKSEL)
0 = Use RSYS CLK n pins for eac h r ec eiv e system cl oc k (Channels 1-4).
1 = Use BPCLK 1 as the m aster cl oc k for all four r ec eive system cl oc k s (Channels 1-4).
Bit 5: TSYSCLKn Select (TSYSCLKSEL)
0 = Use TSYSCLK n pins for eac h transmit system clock (Channe ls 1 -4).
1 = Use BPCLK 1 as the m aster cl oc k for all four transmit system clocks (Channels 1-4).
Bit 4: TCLKn Select (T CLKSEL)
0 = Use TCLK n pins for eac h of t he transmit cloc k ( Channels 1-4).
1 = Use REF CLKIO as the master cl oc k for all four tr ansmit cl oc k s (Channels 1-4).
Bits 3 to 0: Clock Out Frequency Select (CLKOSEL[3:0]. CLKO output pin will use MCLK (1.544MHz or
2.048MHz or scal ed v ersion) as its ref erence. T he following table shows how to configure for each frequency. For
best jitter performanc e use a 2.048M Hz oscillator for MCLK.
CLKOSEL[3:0] CLKO (kHz)
0000
2048
0001
4096
0010
8192
0011
16384
0100
1544
0101
3088
0110
6176
0111
12352
1000
1536
1001
3072
1010
6144
1011
12288
1100
32
1101
64
1110
128
1111
256
DS26514 4-Port T1/E1/J1 Transceiver
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Register Name:
GSRR1
Register Desc r iptio n:
Global Sof t ware Reset Register 1
Register Addr ess :
00F6h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
H256RST
LRST
BRST
FRST
Default
0
0
0
0
0
0
0
0
Bit 3 : HDL C-256 Sof tware Reset ( H256RST). HDLC-256 Channels 1-4 l ogic and registers are reset with a 0-to-1
transi tion in this bit . T he reset i s released when a zero is writ ten to t his bit.
0 = Normal Oper ation
1 = Reset HDLC-256 Ch 1-4
Note: HDLC-64 ci r c uits are reset by the Fram er Sof tware Reset.
Bit 2: LI U Softw are Reset (LRST) . LIU Channels 1-4 logic and regi ster s are reset with a 0-to-1 trans ition in this
bit. The reset is released when a zero is writ ten to this bit.
0 = Normal operat ion.
1 = Reset LIU channel s 1–4.
Bit 1: BE RT Software Reset ( BRST) . BERT Channels 1-4 logic and registers are reset with a 0-to-1 trans ition in
this bit. The reset is rel eased when a zero is written to this bi t.
0 = Normal operat ion.
1 = Reset B E RT channels 1–4.
Bit 0: Framer Software Reset (FRST). Fram ers 1-4 to l ogic and r egister s are reset wit h a 0-to-1 trans ition in t his
bit. The reset is released when a zero is writ ten to this bit.
0 = Normal operat ion.
1 = Reset fram er s 1-4.
Register Name:
IDR
Register Desc r iptio n:
Device I dentification Reg ister
Register Addr ess :
00F8h
Bit #
7
6
5
4
3
2
1
0
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default
1
1
1
0
0
0
0
0
Bits 7 to 3: Device ID (ID[ 7: 3] ) . T he upper five bits of the IDR are used to display the DS26514 I D.
Table 10-17. Device ID Codes in this Product Family
DEVICE
ID7
ID6
ID5
ID4
ID3
DS26519
1
1
0
1
1
DS26518
1
1
0
1
0
DS26514
1
1
1
0
0
DS26528
0
1
0
1
1
DS26524
0
1
1
0
0
DS26522
0
1
1
0
1
DS26521
0
1
1
1
0
Bits 2 to 0: Silicon Revision Bits (ID[2:0]). The lower three bits of the IDR are used to display a sequential
num ber denoting the di e r ev ision of the chip. The initial silic on r ev ision = “ 000” and is incr em ented wit h eac h s ilic on
revision. Thi s value is not the same as the two-charac ter dev ice rev ision on the top brand of the dev ice. This is due
to the fact that portions of the device assembly other than the silicon may change, causing the device revision
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 135 of 305
increment on the brand without having a revision of the silicon. ID0 is the LSB of a decimal code that represents
the chip rev ision.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 136 of 305
Register Name:
GFISR1
Register Desc r iptio n:
Global Framer Interrup t S t atus Regi st er 1
Register Addr ess :
00F9h
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
FIS4
FIS3
FIS2
FIS1
Default
0
0
0
0
0
0
0
0
The GFISR1 register r epor ts t he framer interrupt status for the T 1/E1 fram er s of Channels 1 to 4. A logic one in the
associated bit locat ion i ndic ates a f r am er has set its i nterrupt si gnal.
Bit 3: Framer I nterrupt Status 4 (FIS 4)
0 = Fram er 4 has not i ssued an int er r upt.
1 = Fram er 4 has issued an inter r upt.
Bit 2: Framer I nterrupt Status 3 (FIS 3)
0 = Fram er 3 has not i ssued an int er r upt.
1 = Fram er 3 has issued an inter r upt.
Bit 1: Framer I nterrupt Status 2 (FIS 2)
0 = Fram er 2 has not i ssued an int er r upt.
1 = Fram er 2 has issued an interrupt.
Bit 0: Framer I nterrupt Status 1 (FIS 1)
0 = Fram er 1 has not i ssued an int er r upt.
1 = Fram er 1 has issued an inter r upt.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 137 of 305
Register Name:
GBISR1
Register Desc r iptio n:
Global BERT In t errupt Status Regist er 1
Register Addr ess :
00FAh
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
BIS4
BIS3
BIS2
BIS1
Default
0
0
0
0
0
0
0
0
The GBISR1 register reports the interrupt status for the T1/E1 bit error rate testers (BERT) of Channels 1 to 4. A
logic one in the associated bit location indic ates a BERT has set its inter r upt si gnal.
Bit 3: BE RT Int errup t Status 4 (BIS4)
0 = BERT 4 has not i ssued an int er r upt.
1 = BERT 4 has issued an inter r upt.
Bit 2: BE RT Int errup t Status 3 (BIS3)
0 = BERT 3 has not i ssued an int er r upt.
1 = BERT 3 has issued an interrupt.
Bit 1: BE RT Int errup t Status 2 (BIS2)
0 = BERT 2 has not i ssued an int er r upt.
1 = BERT 2 has issued an inter r upt.
Bit 0: BE RT Int errup t Status 1 (BIS1)
0 = BERT 1 has not i ssued an int er r upt.
1 = BERT 1 has issued an inter r upt.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 138 of 305
Register Name:
GLISR1
Register Desc r iptio n:
Global LIU Interrupt Status Regi st er 1
Register Addr ess :
00FBh
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
LIS4
LIS3
LIS2
LIS1
Default
0
0
0
0
0
0
0
0
The GLISR1 register reports the LIU interrupt status for the T1/E1 LIUs of Channels 1 to 4. A logic one in the
associated bit locat ion i ndic ates a LIU has set it s i nterrupt signal .
Bit 3: LI U Interru pt Status 4 (LIS4)
0 = LIU 4 has not issued an inter r upt.
1 = LIU 4 has issued an int er r upt.
Bit 2: LI U Interru pt Status 3 (LIS3)
0 = LIU 3 has not issued an inter r upt.
1 = LIU 3 has issued an int er r upt.
Bit 1: LI U Interru pt Status 2 (LIS2)
0 = LIU 2 has not issued an inter r upt.
1 = LIU 2 has issued an int er r upt.
Bit 0: LI U Interru pt Status 1 (LIS1)
0 = LIU 1 has not issued an interrupt.
1 = LIU 1 has issued an int er r upt.
Register Name:
GHISR
Register Desc r iptio n:
Global HDLC-256 Interrupt Status Register
Register Addr ess :
00F5h
Read/Write Function
R
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
HIS4
HIS3
HIS2
HIS1
Default
0
0
0
0
0
0
0
0
The G LISR r egister r epor ts the HDLC-256 interrupt status for Channels 1 through 8. A logic one in the associated
bit locat ion indicates a HDLC-256 has set its i nterrupt signal.
Bit 3 : HDL C-256 In t errup t Status 4
0 = HDLC-256 4 has not issued an int er r upt.
1 = HDLC-256 4 has i ssued an int er r upt.
Bit 2 : HDL C-256 In t errup t Status 3
0 = HDLC-256 3 has not issued an int er r upt.
1 = HDLC-256 3 has i ssued an int er r upt.
Bit 1 : HDL C-256 In t errup t Status 2
0 = HDLC-256 2 has not issued an inter r upt.
1 = HDLC-256 2 has i ssued an int er r upt.
Bit 0 : HDL C-256 In t errup t Status 1
0 = HDLC-256 1 has not issued an int er r upt.
1 = HDLC-256 1 has i ssued an int er r upt.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 139 of 305
Register Name:
GFIMR1
Register Desc r iptio n:
Global Framer Interrup t M ask Regi st er 1
Register Addr ess :
00FCh
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
FIM4
FIM3
FIM2
FIM1
Default
0
0
0
0
0
0
0
0
Bit 3: Framer 4 Int errupt Mask (FIM 4)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Framer 3 Int errupt Mask (FIM 3)
0 = Interrupt masked.
1 = Int er r upt enabled.
Bit 1: Framer 2 Int errupt Mask (FIM 2)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Framer 1 Int errupt Mask (FIM 1)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 140 of 305
Register Name:
GBIMR1
Register Desc ription:
Global BERT In t errupt Mask Register 1
Register Addr ess :
00FDh
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
BIM4
BIM3
BIM2
BIM1
Default
0
0
0
0
0
0
0
0
Bit 3: BE RT Int errup t Mask 4 (BIM4)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: BE RT In t errup t Mask 3 (BIM3)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: BE RT Int errup t Mask 2 (BIM2)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: BE RT Int errup t Mask 1 (BIM1)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 141 of 305
Register Name:
GLIMR1
Register Desc r iptio n:
Global LIU Interrupt Mask Register 1
Register Addr ess :
00FEh
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
LIM4
LIM3
LIM2
LIM1
Default
0
0
0
0
0
0
0
0
Bit 3: LI U Interru pt Mask 4 (LIM4)
0 = Interrupt mas ked.
1 = Interrupt enabled.
Bit 2: LI U Interru pt Mask 3 (LIM3)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: LI U Interru pt Mask 2 (LIM2)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: LI U Interru pt Mask 1 (LIM1)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Register Name:
GHIMR
Register Desc r iptio n:
Global HDLC-256 Interrupt Mask Register
Register Addr ess :
00F7h
Read/Write Function
R/W
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
HIM4
HIM3
HIM2
HIM1
Default
0
0
0
0
0
0
0
0
Bit 3 : HDL C-256 In t errup t Mask 4
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2 : HDL C-256 In t errup t Mask 3
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1 : HDL C-256 In t errup t Mask 2
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0 : HDL C-256 In t errup t Mask 1
0 = Interrupt masked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 142 of 305
10.4 Framer Register Descriptions
10.4.1 Receive Register Descriptions
See Table 10-3 for the complete framer register lis t.
Register Name:
RHC
Register Desc r iptio n:
Receive HDL C Con t rol Regi st er
Register Addr ess :
010h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RCRCD
RHR
RHMS
RHCS4
RHCS3
RHCS2
RHCS1
RHCS0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive CRC-16 Dis play (RCRCD)
0 = Do not write received CRC-16 code to FIFO (de fault).
1 = Write received CRC-16 code to FIFO after last oct et of packet.
Bit 6: Receive HDLC Reset ( RHR) . Will reset the receive HDLC cont r oller and flush t he r ec eive FIFO. Note that
this bit i s a acknowledged r eset. The host should set this bit and the DS26514 wi ll clear it onc e the reset oper ation
is complete. The DS26514 will compl ete the HDLC r eset within 2 frames.
0 = Normal operat ion.
1 = Reset r ec eiv e HDLC c ontroll er and flush the receive FIFO.
Bit 5: Receive HDLC M apping S elect ( RHM S)
0 = Rec eiv e HDLC assigned t o c hannels.
1 = Rec eiv e HDLC assigned t o FDL (T1 mode), S a bits (E1 mode) .
Bits 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to
the HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s
select s channel 32 ( E 1) . A ch ange to t he r ec eive HDLC channel select is ackno wledged only aft er a r ec eive HDLC
reset (RHR).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 143 of 305
Register Name:
RHBSE
Register Desc r iptio n:
Receive HDL C-64 Bit Suppress Regist er
Register Addr ess :
011h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BSE8
BSE7
BSE6
BSE5
BSE4
BSE3
BSE2
BSE1
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Chann el Bit 8 Supp ress ( BS E 8). MSB of the channel. Set to one to stop this bit from bei ng used.
Bit 6: Receive Chann el Bit 7 Supp ress ( BS E 7). S et to one to stop this bit fr om bei ng used.
Bit 5: Receive Chann el Bit 6 Supp ress ( BS E 6). S et to one to stop this bit fr om bei ng used.
Bit 4: Receive Chann el Bit 5 Supp ress ( BS E 5). Set to one to stop thi s bi t f r om bei ng used.
Bit 3: Receive Chann el Bit 4 Supp ress ( BS E 4). S et to one to stop this bit fr om bei ng used.
Bit 2: Receive Chann el Bit 3 Supp ress ( BS E 3). S et to one to stop this bit fr om bei ng used.
Bit 1: Receive Channel Bit 2 Suppress ( BS E 2). Set to one to stop this bit f r om bei ng used.
Bit 0: Receive Chann el Bit 1 Supp ress ( BS E 1). LSB of the c hannel. Set to one to stop t his bit from being used.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 144 of 305
Register Name:
RDS0SEL
Register Desc r iptio n:
Receive Ch annel Monitor Sel ect Regi st er
Register Addr ess :
012h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
RCM4
RCM3
RCM2
RCM1
RCM0
Default
0
0
0
0
0
0
0
0
Bits 4 to 0: Receive Chann el Monito r Bits ( RCM [ 4: 0]). RCM 0 is the LS B of a 5-bit channel sel ect that
determ ines whic h r ec eive DS0 channel data will appear in the RDS0M register.
Register Name:
RSIGC
Register Desc r iptio n:
Receive-Signaling Control Register
Register Addr ess :
013h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
RFSA1
—
RSFF
RSFE
RSIE
—
—
—
CASMS
—
RSFF
RSFE
RSIE
Default
0
0
0
0
0
0
0
0
Bit 4 (T 1 Mode): Recei ve Fo rce Sign aling All Ones (RFSA1)
0 = Do not f orce robbed bit si gnaling to all ones.
1 = Forc e si gnaling bi ts to all ones on a per-channel basis according to t he T1RSAOI1–3 registers.
Bit 4 (E1 Mode): CAS Mode Select (CASMS)
0 = The DS26514 will i nitiate a resync when two conse c utive multif r am e alignm ent si gnals have been
received with an er r or.
1 = The DS26514 will i nitiate a resync when two conse c utive multif r am e alignm ent si gnals have been
received with an er r or, or 1 multifr am e has been receiv ed with all the bits i n time sl ot 16 in state 0.
Ali gnm ent criteria i s met when at least one bit in state 1 i s present in the time slot 16 preceding t he
m ultif r am e alignment signal fir st detected (G. 732 alternate criteri a) .
Bit 2: Receive-Signalin g Force Freeze (RSFF). Freezes receive-side si gnaling at RSIGn (and RSERn if receive-
signal ing reinsertion is enabl ed) ; will overri de receive freeze enable (RFE ).
0 = Do not f orce a freeze ev ent.
1 = Forc e a freeze event.
Bit 1: Receive-Signalin g F reez e Enabl e ( RSFE )
0 = No freezing of receive signali ng data will occur.
1 = All ow freezing of r ec eiv e si gnaling data at RSIGn (and RSERn if rec eiv e-signaling reinsertion is
enabled).
Bit 0: Receive-Signaling Integration Enable (RSIE)
0 = Si gnaling changes of state repor ted on any change in select ed c hannels.
1 = Si gnaling must be stable for three multif r am es i n order for a c hange of stat e to be reported.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 145 of 305
Register Name:
T1RCR2 (T1 Mo de)
Register Desc r iptio n:
Receive Co ntrol Regist er 2
Register Addr ess :
014h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
RSLC96
OOF2
OOF1
RAIIE
RRAIS
Default
0
0
0
0
0
0
0
0
Bit 4: Receive SLC-96 Synchronizer E nable (RSL C96). S ee S ection 9.9.4.4 for SLC-96 det ails.
0 = The SLC-96 synchr onizer is disabl ed.
1 = The SLC-96 synchr onizer is enabled.
Bits 3 and 2: Out Of Fra me Selec t Bi ts (O OF [2 :1 ])
OOF2
OOF1
OU T OF FR AME CRI TER IA
0
0
2/4 frame bits in error
0
1
2/5 frame bits in error
1
0
2/6 frame bits in error
1
1
2/6 frame bits in error
Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to
ex ceed 100ms per interrupti on (T1.403). In ESF mode, setti ng RAIIE wil l cause the RAI status f rom the DS26514
to be integrated for 200ms.
0 = RAI detects when 16 consecutive patterns of 00FF appear i n the F DL.
RAI cl ear s when 14 or f ewer patterns of 00FF hex out of 16 possi ble appear i n the FDL.
1 = RAI detects when the c ondition has been present for greater than 200ms.
RAI cl ear s when the condi tion has been absent for greater t han 200m s.
Bit 0: Receive-Side Remote Alarm Sel ect ( RRAIS)
0 = Rec eiv e fram er detects T1 r em ote alarm .
D4—Zeros i n bit 2 of all c hannels.
ESF—00FF pattern in FDL.
1 = Rec eiv e Fram er detects J1 Remote Alarm .
D4—A one i n the S-bit position of fr am e 12.
ESF—all ones in FDL.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 146 of 305
Register Name:
E1RSAIMR (E1 Mode Only )
Register Desc r iptio n:
Receive Sa Bit Interrup t Mask Register
Register Addr ess :
014h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
RSa4IM
RSa5IM
RSa6IM
RSa7IM
RSa8IM
Default
0
0
0
0
0
0
0
0
Bit 4: S a4 Change Det ect Interru pt Mask (RSa4IM). This bit will enable the change detect i nterrupt for the Sa4
bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS 7.0 t o indic ate the c hange of st ate.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: S a5 Change Det ect In t errup t Mask (RSa5IM). This bit will enable the change detec t i nterrupt for the Sa5
bits. Any change of state of the Sa5 bit will then generate an interrupt in RLS 7.0 t o indic ate the c hange of st ate.
0 = Interrupt mas ked.
1 = Interrupt enabled.
Bit 2: S a6 Change Det ect In t errup t Mask (RSa6IM). This bit will enable the change detec t i nterrupt for the Sa6
bits. Any change of state of the Sa6 bit will then generate an interrupt in RLS 7.0 t o indic ate the c hange of st ate.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: S a7 Change Det ect In t errup t Mask (RSa7IM). This bit will enable the change detec t i nterrupt for the Sa7
bits. Any change of state of the Sa7 bit will then generate an interrupt in RLS 7.0 t o indic ate the c hange of state.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: S a8 Change Det ect In t errup t Mask (RSa8IM). This bit will enable the change detec t i nterrupt for the Sa8
bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS 7.0 t o indicat e the change of st ate.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 147 of 305
Register Name:
T1RBOCC (T1 Mode Onl y)
Register Desc r iptio n:
Receive BO C Con t rol Regi st er
Register Addr ess :
015h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RBR
—
RBD1
RBD0
—
RBF1
RBF0
—
Default
0
0
0
0
0
0
0
0
Bit 7: Receive BOC Reset ( RBR) . T he host shoul d set this bit to f orce a reset of t he BOC ci r c uitry. Note t hat thi s i s
an acknowledged reset—that is, the host needs only to set the bit and the DS26514 will clear it once the reset
operati on is compl ete (l ess than 250µs). Modificati ons to t he RBF[1:0] and RBD[1:0] bi ts will not be applied to the
BOC c ontroller until a BOC reset has been com plet ed.
Bits 5 and 4: Receive BOC Disintegration Bits (RBD[1:0]). The BOC disintegration filter sets the number of
m essage bits that must be receiv ed without a v alid BOC t o set the B C bi t indicating that a vali d BOC is no longer
being r ec eived.
RBD1 RBD0
CONSECUTIVE MESSAGE BITS
FOR BOC CLEAR IDENTIFICATION
0
0
16
0
1
32
1
0
48
1
1
64 (See Not e 1)
Bits 2 and 1: Receive BOC Fil t er Bits ( RBF[1:0). The BO C filter sets the num ber of consecut ive patterns that
m ust be r ec eiv ed without error prior to an indicat ion of a valid m essage.
RBF1 RBF0
CONSE CUTI V E BOC CODES FOR
VALID SEQUENCE IDENTIFICATION
0
0
None
0
1
3
1
0
5
1
1
7 (See Note 1)
Note 1: The DS26514’s BOC controller does not integrate and disintegrate concurrently. Therefore, if t he maximum integrat ion
time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be
detected.
Register Name:
RIDR1 to RI DR32
Register Desc r iptio n:
Receive I dle Code Defini tion Regi st ers 1 to 32
Register Addr ess :
020h to 03F h + (200h x (n - 1)) : wh ere n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bits 7 t o 0: P er-Chan nel Id le Code Bi ts (C[ 7:0]). C0 i s the LSB of the c ode (thi s bit i s tran smit ted l ast). Address
20h is for channel 1. Addr ess 37h is for c hannel 24. Address 3Fh is f or c hannel 32. RIDR25–RIDR32 are E1 mode
only.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 148 of 305
Register Name:
T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only)
Register Desc r iptio n:
Receive-Signaling All-Ones In sert ion Registers 1 to 3
Register Addr ess :
038h, 039h, 03Ah + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
T1RSAOI1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
T1RSAOI2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
T1RSAOI3
Setting any of the CH[ 1:24] bits in t he T1RSAOI1 to T1RSAO I3 register s wil l c ause signaling data to be replaced
with logic ones as reported on RSERn. The RSIGn signal will conti nue to repor t rec eived signali ng data. Note that
this f eature must be enabled with c ontrol bit RSIGC.4.
Register Name:
T1RD MWE1, T1RDMWE2, T1RDMWE3
Register Desc r iptio n:
T1 Receive Dig ital Milliwatt Enable Regi st ers 1 t o 3
Register Addr ess :
03Ch, 03Dh, 03E h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
T1RDMWE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
T1RDMWE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
T1RDMWE3
Bits 7 to 0: Receive Digi t al Mil li watt Enable for Channels 1 to 24 (CH[1:24] )
0 = Does not aff ec t t he r ec eiv e data associated with this channel.
1 = Replac e the receive data associ ated wi th this channel with di gital milliwatt c ode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 149 of 305
Register Name:
RS1 to RS16
Register Desc r iptio n:
Receive-Sign aling Reg isters 1 to 16
Register Addr ess :
040h to 04F h + (200h x (n - 1)) : wh ere n = 1 to 4
T1 Mode:
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH1-A
CH1-B
CH1-C
CH1-D
CH13-A
CH13-B
CH13-C
CH13-D
RS1
CH2-A
CH2-B
CH2-C
CH2-D
CH14-A
CH14-B
CH14-C
CH14-D
RS2
CH3-A
CH3-B
CH3-C
CH3-D
CH15-A
CH15-B
CH15-C
CH15-D
RS3
CH4-A
CH4-B
CH4-C
CH4-D
CH16-A
CH16-B
CH16-C
CH16-D
RS4
CH5-A
CH5-B
CH5-C
CH5-D
CH17-A
CH17-B
CH17-C
CH17-D
RS5
CH6-A
CH6-B
CH6-C
CH6-D
CH18-A
CH18-B
CH18-C
CH18-D
RS6
CH7-A
CH7-B
CH7-C
CH7-D
CH19-A
CH19-B
CH19-C
CH19-D
RS7
CH8-A
CH8-B
CH8-C
CH8-D
CH20-A
CH20-B
CH20-C
CH20-D
RS8
CH9-A
CH9-B
CH9-C
CH9-D
CH21-A
CH21-B
CH21-C
CH21-D
RS9
CH10-A
CH10-B
CH10-C
CH10-D
CH22-A
CH22-B
CH22-C
CH22-D
RS10
CH11-A
CH11-B
CH11-C
CH11-D
CH23-A
CH23-B
CH23-C
CH23-D
RS11
CH12-A
CH12-B
CH12-C
CH12-D
CH24-A
CH24-B
CH24-C
CH24-D
RS12
E1 Mode:
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
0
X
Y
X
X
RS1
CH1-A
CH1-B
CH1-C
CH1-D
CH16-A
CH16-B
CH16-C
CH16-D
RS2
CH2-A
CH2-B
CH2-C
CH2-D
CH17-A
CH17-B
CH17-C
CH17-D
RS3
CH3-A
CH3-B
CH3-C
CH3-D
CH18-A
CH18-B
CH18-C
CH18-D
RS4
CH4-A
CH4-B
CH4-C
CH4-D
CH19-A
CH19-B
CH19-C
CH19-D
RS5
CH5-A
CH5-B
CH5-C
CH5-D
CH20-A
CH20-B
CH20-C
CH20-D
RS6
CH6-A
CH6-B
CH6-C
CH6-D
CH21-A
CH21-B
CH21-C
CH21-D
RS7
CH7-A
CH7-B
CH7-C
CH7-D
CH22-A
CH22-B
CH22-C
CH22-D
RS8
CH8-A
CH8-B
CH8-C
CH8-D
CH23-A
CH23-B
CH23-C
CH23-D
RS9
CH9-A
CH9-B
CH9-C
CH9-D
CH24-A
CH24-B
CH24-C
CH24-D
RS10
CH10-A
CH10-B
CH10-C
CH10-D
CH25-A
CH25-B
CH25-C
CH25-D
RS11
CH11-A
CH11-B
CH11-C
CH11-D
CH26-A
CH26-B
CH26-C
CH26-D
RS12
CH12-A
CH12-B
CH12-C
CH12-D
CH27-A
CH27-B
CH27-C
CH27-D
RS13
CH13-A
CH13-B
CH13-C
CH13-D
CH28-A
CH28-B
CH28-C
CH28-D
RS14
CH14-A
CH14-B
CH14-C
CH14-D
CH29-A
CH29-B
CH29-C
CH29-D
RS15
CH15-A
CH15-B
CH15-C
CH15-D
CH30-A
CH30-B
CH30-C
CH30-D
RS16
In the ESF framing m ode, there can be up to f our signaling bits per channel (A, B, C, and D). In the D4 framing
m ode, there ar e only two si gnaling bits per channel (A and B) . In t he D4 fram ing mode, the framer will repeat the A
and B signal ing dat a i n the C and D bi t l ocati ons. Ther ef ore, when the f r am er i s operated i n D4 f rami ng m ode, t he
user will need to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The receive-signaling
registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling
informati on before the “OOF ” occ ur r ed.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 150 of 305
Register Name:
LCVCR1
Register Desc r iptio n:
Line Cod e Viol at io n Count Register 1
Register Addr ess :
050h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LCVC15
LCVC14
LCVC13
LCVC12
LCVC11
LCVC10
LCVC9
LCVC8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Line Cod e Viol ation Count er Bits 15 to 8 (LCVC[ 15: 8] ). LCV 15 is the M SB of the 16-bit code
v iolation count.
Register Name:
LCVCR2
Register Description:
Line Cod e Viol at io n Count Register 2
Register A ddr es s:
051h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LCVC7
LCVC6
LCVC5
LCVC4
LCVC3
LCVC2
LCVC1
LCVC0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Line Code Violation Counter Bits 7 to 0 (LCVC[7: 0] ) . LCV0 is the LS B of t he 16-bit code violatio n
count.
Register Name:
PCVCR1
Register Desc r iptio n:
Path Cod e Viol at ion Count Regi st er 1
Register Addr ess :
052h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
PCVC15
PCVC14
PCVC13
PCVC12
PCVC11
PCVC10
PCVC9
PCVC8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Path Code Violat ion Counter Bits 15 to 8 (PCVC[15: 8] ) . PCVC15 is the M SB of the 16-bit path code
v iolation count.
Register Name:
PCVCR2
Register Desc r iptio n:
Path Code Violat ion Count Regi st er 2
Register Addr ess :
053h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
PCVC7
PCVC6
PCVC5
PCVC4
PCVC3
PCVC2
PCVC1
PCVC0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Path Code Violat ion Counter Bits 7 to 0 (PCVC[7:0]). PCVC0 is the LSB of the 16-bi t pat h c ode
v iolation count.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 151 of 305
Register Name:
FOSCR1
Register Desc r iptio n:
Frames O ut of Sync Count Regi st er 1
Register Addr ess :
054h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FOS15
FOS14
FOS13
FOS12
FOS11
FOS10
FOS9
FOS8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Frames Out of Sync Count er Bits 15 to 8 (FOS[ 15: 8] ) . FOS 15 is the MSB of t he 16-bit frames out of
sync count.
Register Name:
FOSCR2
Register Desc r iptio n:
Frames O ut of Sync Count Regi st er 2
Register Addr ess :
055h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FOS7
FOS6
FOS5
FOS4
FOS3
FOS2
FOS1
FOS0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Frames Out of Sync Count er Bits 7 to 0 (FOS[7:0] ) . FOS 0 is the LS B of the 16-bit fram es out of
sync count.
Register Name:
E1EBCR1 (E 1 Mode Onl y)
Register Description:
E-Bit Count Regi st er 1
Register A ddr es s:
056h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EB15
EB14
EB13
EB12
EB11
EB10
EB9
EB8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: E-Bit Coun t er Bits 15 to 8 (EB[15: 8] ) . EB15 i s the M SB of the 16-bit E-bit c ount.
Register Name:
E1EBCR2 (E 1 Mode Onl y)
Register Description:
E-Bit Count Regi st er 2
Register A ddr es s:
057h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: E-Bit Coun t er Bits 7 to 0 (EB[7: 0] ). E B 0 is the LSB of the 16-bit E-bit count.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 152 of 305
Register Name:
FEACR1
Register Description:
Error Cou nt A Regist er 1
Register A ddr es s:
058h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FEACR15
FEACR14
FEACR13
FEACR12
FEACR11
FEACR10
FEACR9
FEACR8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Error Count A Regi st er 1 Bits 15 to 8 (FEACR[15:8]). FEACR15 is the MSB of the 16-bit Far End A
Counter.
Register Name:
FEACR2
Register Description:
Error Cou nt A Regist er 2
Register A ddr es s:
059h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FEACR7
FEACR6
FEACR5
FEACR4
FEACR3
FEACR2
FEACR1
FEACR0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Error Count A Regi st er 2 Bits 7 to 0 (FEACR[7:0]) . FEACR0 is the LSB of t he 16-bit F ar End A
Counter.
Register Name:
FEBCR1
Register Description:
Error Cou nt B Regist er 1
Register A ddr es s:
05Ah + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FEBCR15
FEBCR14
FEBCR13
FEBCR12
FEBCR11
FEBCR10
FEBCR9
FEBCR8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Erro r Count B Regi st er 1 Bits 15 to 8 (FEBCR[15:8] ) . FEBCR15 is the MSB of the 16-bit Far E nd
Error B Counter.
Register Name:
FEBCR2
Register Description:
Error Cou nt B Regist er 2
Register A ddr es s:
05Bh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FEBCR7
FEBCR6
FEBCR5
FEBCR4
FEBCR3
FEBCR2
FEBCR1
FEBCR0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Erro r Count B Regi st er 2 Bits 7 to 0 (FEBCR[7:0]). FEB CR0 is the LS B of t he 16-bit F ar End Error B
Counter.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 153 of 305
Register Name:
RDS0M
Register Desc r iptio n:
Receive DS0 M on itor Register
Register Addr ess :
060h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
B1
B2
B3
B4
B5
B6
B7
B8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Receive DS0 Ch ann el Bi t s (B[1:8] ) . Receive channel dat a that has been selected by the Receiv e
Channel M onitor Select Regi ster (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be r ec eiv ed) .
Register Name:
T1RFDL (T1 Mode)
Register Desc r iptio n:
Receive F DL Register
Register Addr ess :
062h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin ition for E1 mode. See E1RRTS7.
Bit 7: Receive FDL Bi t 7 (RF DL7). MS B of the rec eiv ed FDL code.
Bit 6: Receive FDL Bi t 6 (RF DL6).
Bit 5: Receive FDL Bi t 5 (RF DL5).
Bit 4: Receive FDL Bi t 4 (RF DL4).
Bit 3: Receive FDL Bi t 3 (RF DL3).
Bit 2: Receive FDL Bi t 2 (RF DL2).
Bit 1: Receive FDL Bi t 1 (RF DL1).
Bit 0: Receive FDL Bi t 0 (RF DL0). LSB of t he received FDL code.
Register Name:
E1RRTS7 (E1 Mode)
Register Desc r iptio n:
Receive Real -Time Status Regi st er 7
Register Addr ess :
062h + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
CSC5
CSC4
CSC3
CSC2
CSC0
CRC4SA
CASSA
FASSA
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin it ion for T1 mode. See T1RFDL. All bits in this register are real-time (not latched).
Bits 7 to 3: CRC-4 Sync Count er Bits ( CS C[ 5: 2] an d CSC0). T he CRC-4 sync counter inc r em ents each time the
8m s CRC-4 multiframe search times out. The counter is cl ear ed when the framer has successfull y obtained
synchroni z ation at t he CRC-4 lev el. The c ounter can also be cl ear ed by disabling t he CRC-4 mode (RCR1.3 = 0).
This counter is useful for determining the amount of time the framer has been searching f or synchr onizati on at the
CRC-4 level. ITU-T G.706 suggests that if synchroni z ation at the CRC-4 lev el c annot be obtained wit hin 400 ms,
then t he search shoul d be abandoned and proper ac tion taken. The CRC-4 sync counter will saturate ( not rollover).
CSC0 i s the LS B of the 6–bit c ounter. ( Note: CS C1 is omitted to allow resolution to > 400ms using 5 bits.)
Bit 2: CRC-4 MF Sync Active (CRC4SA). Set whi le the synchroniz er is searching for the CRC-4 MF alignment
word.
Bit 1: CAS MF Sync Active (CASSA). Set while the synchroni z er is searchi ng for the CAS MF alignment word.
Bit 0: FAS Sync Active (FASSA). Set while the synchronizer is searchi ng for alignm ent at the FAS level.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 154 of 305
Register Name:
T1RBOC (T1 Mode)
Register Desc r iptio n:
Receive BO C Register
Register Addr ess :
63h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
RBOC5
RBOC4
RBOC3
RBOC2
RBOC1
RBOC0
Default
0
0
0
0
0
0
0
0
Bit 5: BOC Bit 5 (RBOC5)
Bit 4: BOC Bit 4 (RBOC4)
Bit 3: BOC Bit 3 (RBOC3)
Bit 2: BOC Bit 2 (RBOC2)
Bit 1: BOC Bit 1 (RBOC1)
Bit 0: BOC Bit 0 (RBOC0)
The T 1RBOC r egister always cont ains the l ast v alid BOC received. The Receive FDL Register (T1RFDL) reports
the incoming Facility Data Link (FDL) or the inc omi ng Fs bits. T he LSB is received first. In D4 frami ng m ode, RFDL
updates on m ultifram e boundar ies and reports the six Fs bits in RFDL[5:0].
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 155 of 305
Register Name:
T1R SLC1, T1RSLC2, T1RSLC3 (T1 Mode)
Register Desc r iptio n:
Receive SLC96 Data Lin k Regi st ers
Register Addr ess :
064h, 065h, 066h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
C8
C7
C6
C5
C4
C3
C2
C1
T1RSLC1
M2
M1
S=0
S=1
S=0
C11
C10
C9
T1RSLC2
S=1
S4
S3
S2
S1
A2
A1
M3
T1RSLC3
Note: These registers have an alternate definit ion for E1 mode. See E1RAF, E1RNAF, and E1RsiAF.
Regis ter Name:
E1RAF (E1 Mod e)
Register Desc r iptio n:
E1 Receive Alig n F rame Regi st er
Register Addr ess :
064h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
Si
0
0
1
1
0
1
1
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin ition for T1 mode. See T1RSLC1.
Bit 7: International Bit (Si)
Bit 6: Frame Align ment Signal Bit (0)
Bit 5: Frame Align ment Signal Bit (0)
Bit 4: Frame Align ment Signal Bit (1)
Bit 3: Frame Align ment Signal Bit (1)
Bit 2: Frame Align ment Signal Bit (0)
Bit 1: Frame Align ment Signal Bit (1)
Bit 0: Frame Align ment Signal Bit (1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 156 of 305
Register Name:
E1RNAF (E1 Mod e)
Register Desc r iptio n:
E1 Receive Non-Ali gn Frame Reg ister
Register Addr ess :
065h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin ition for T1 mode. See T1RSLC2.
Bit 7: International Bit (Si)
Bit 6: Frame Non-Alignment Signal Bit (1)
Bit 5: Remote Alarm (A)
Bit 4: Addit io nal Bit 4 (Sa4)
Bit 3: Addit io nal Bit 5 (Sa5)
Bit 2: Addit io nal Bit 6 (Sa6)
Bit 1: Addit io nal Bit 7 (Sa7)
Bit 0: Addit io nal Bit 8 (Sa8)
Register Name:
E1RsiAF (E 1 Mode)
Register Desc r iptio n:
Received S i Bi t s of the Align F rame
Register Addr ess :
066h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
SiF14
SiF12
SiF10
SiF8
SiF6
SiF4
SiF2
SiF0
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin ition for T1 mode. See T1RSLC3.
Bit 7: Si Bit of Frame 14 (SiF14)
Bit 6: Si Bit of Frame 12 (SiF12)
Bit 5: Si Bit of Frame 10 (SiF10)
Bit 4: Si Bit of Frame 8 (SiF8)
Bit 3: Si Bit of Frame 6 (SiF6)
Bit 2: Si Bit of Frame 4 (SiF4)
Bit 1: Si Bit of Frame 2 (S iF2)
Bit 0: Si Bit of Frame 0 (SiF0)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 157 of 305
Register Name:
E1RSiNAF (E1 Mode Only)
Register Desc r iptio n:
Receive Si Bits of the Non-Align Frame Register
Register Addr ess :
067h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
SiF15
SiF13
SiF11
SiF9
SiF7
SiF5
SiF3
SiF1
Default
0
0
0
0
0
0
0
0
Bit 7: Si Bit of Frame 15 (SiF15)
Bit 6: Si Bit of Frame 13 (SiF13)
Bit 5: Si Bit of Frame 11 (SiF11)
Bit 4: Si Bit of Frame 9 (SiF9)
Bit 3: Si Bit of Frame 7 (SiF7)
Bit 2: Si Bit of Frame 5 (SiF5)
Bit 1: Si Bit of Frame 3 (SiF3)
Bit 0: Si Bit of Frame 1 (SiF1)
Register Name:
E1RRA (E1 Mode Onl y)
Register Desc r iptio n:
Receive Remo t e Alarm Reg ister
Register Addr ess :
068h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RRAF15
RRAF13
RRAF11
RRAF9
RRAF7
RRAF5
RRAF3
RRAF1
Default
0
0
0
0
0
0
0
0
Bit 7: Remote Alarm Bi t of Frame 15 (RRAF15)
Bit 6: Remote Alarm Bi t of Frame 13 (RRAF13)
Bit 5: Remote Alarm Bi t of Frame 11 (RRAF11)
Bit 4: Remote Alarm Bi t of Frame 9 (RRAF9)
Bit 3: Remote Alarm Bi t of Frame 7 (RRAF7)
Bit 2: Remote Alarm Bi t of Frame 5 (RRAF5)
Bit 1: Remote Alarm Bi t of Frame 3 (RRAF3)
Bit 0: Remote Alarm Bi t of Frame 1 (RRAF1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 158 of 305
Register Name:
E1RSa4 (E 1 Mode Onl y)
Register Desc r iptio n:
Received S a4 Bits Register
Register Addr ess :
069h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSa4F15
RSa4F13
RSa4F11
RSa4F9
RSa4F7
RSa4F5
RSa4F3
RSa4F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a4 Bit of Frame 15 (RS a4F15)
Bit 6: S a4 Bit of Frame 13 (RS a4F13)
Bit 5: S a4 Bit of Frame 11 (RS a4F11)
Bit 4: S a4 Bit of Frame 9 (RS a4F9)
Bit 3: S a4 Bit of Frame 7 (RS a4F7)
Bit 2: S a4 Bit of Frame 5 (RS a4F5)
Bit 1: S a4 Bit of Frame 3 (RS a4F3)
Bit 0: S a4 Bit of Frame 1 (RS a4F1)
Register Name:
E1RSa5 (E 1 Mode Onl y)
Register Desc r iptio n:
Received S a5 Bits Register
Register Addr ess :
06Ah + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSa5F15
RSa5F13
RSa5F11
RSa5F9
RSa5F7
RSa5F5
RSa5F3
RSa5F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a5 Bit of Frame 15 (RSa5F15)
Bit 6: S a5 Bit of Frame 13 (RS a5F13)
Bit 5: S a5 Bit of Frame 11 (RS a5F11)
Bit 4: S a5 Bit of Frame 9 (RS a5F9)
Bit 3: S a5 Bit of Frame 7 (RS a5F7)
Bit 2: S a5 Bit of Frame 5 (RS a5F5)
Bit 1: S a5 Bit of Frame 3 (RS a5F3)
Bit 0: S a5 Bit of Frame 1 (RS a5F1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 159 of 305
Register Name:
E1RSa6 (E 1 Mode Onl y)
Register Desc r iptio n:
Received S a6 Bits Register
Register Addr ess :
06Bh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSa6F15
RSa6F13
RSa6F11
RSa6F9
RSa6F7
RSa6F5
RSa6F3
RSa6F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a6 Bit of Frame 15 (RS a6F15)
Bit 6: S a6 Bit of Frame 13 (RS a6F13)
Bit 5: S a6 Bit of Frame 11 (RS a6F11)
Bit 4: S a6 Bit of Frame 9 (RS a6F9)
Bit 3: S a6 Bit of Frame 7 (RS a6F7)
Bit 2: S a6 Bit of Frame 5 (RS a6F5)
Bit 1: S a6 Bit of Frame 3 (RSa6F3)
Bit 0: S a6 Bit of Frame 1 (RS a6F1)
Register Name:
E1RSa7 (E 1 Mode Onl y)
Register Desc r iptio n:
Received S a7 Bits Register
Register Addr ess :
06Ch + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSa7F15
RSa7F13
RSa7F11
RSa7F9
RSa7F7
RSa7F5
RSa7F3
RSa7F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a7 Bit of Frame 15 (RS a4F15)
Bit 6: S a7 Bit of Frame 13 (RS a7F13)
Bit 5: S a7 Bit of Frame 11 (RS a7F11)
Bit 4: S a7 Bit of Frame 9 (RS a7F9)
Bit 3: S a7 Bit of Frame 7 (RS a7F7)
Bit 2: S a7 Bit of Frame 5 (RS a7F5)
Bit 1: S a7 Bit of Frame 3 (RS a7F3)
Bit 0: S a7 Bit of Frame 1 (RS a7F1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 160 of 305
Register Name:
E1RSa8 (E 1 Mode Onl y)
Register Desc r iptio n:
Received S a8 Bits Register
Register Addr ess :
06Dh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSa8F15
RSa8F13
RSa8F11
RSa8F9
RSa8F7
RSa8F5
RSa8F3
RSa8F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a8 Bit of Frame 15 (RS a8F15)
Bit 6: S a8 Bit of Frame 13 (RS a8F13)
Bit 5: S a8 Bit of Frame 11 (RS a8F11)
Bit 4: S a8 Bit of Frame 9 (RS a8F9)
Bit 3: S a8 Bit of Frame 7 (RS a8F7)
Bit 2: S a8 Bit of Frame 5 (RS a8F5)
Bit 1: S a8 Bit of Frame 3 (RS a8F3)
Bit 0: S a8 Bit of Frame 1 (RS a8F1)
Register Name:
SaBITS
Register Desc r iptio n:
Received S aX Bits Regi st er
Register Addr ess :
06Eh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
Sa4
Sa5
Sa6
Sa7
Sa8
Default
0
0
0
0
0
0
0
0
This register indicates the last received SaX bit. This can be used in conjunction with the RLS7 register to
determ ine which SaX bi ts h ave changed. The user c an program which Sa bit positions should be monitored v ia the
E1RSAIMR regi ster, and when a change i s detect ed th rough an i nt errupt in RLS7. 0, the user can deter mi ne whi ch
bit has changed by readi ng this register and compari ng it wit h pr ev ious known values.
Bit 4: Last Received Sa4 Bit (Sa4)
Bit 3: Last Received Sa5 Bit (Sa4)
Bit 2: Last Received Sa6 Bit (Sa5)
Bit 1: Last Received Sa7 Bit (Sa7)
Bit 0: Last Recei ved Sa8 Bit (Sa8)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 161 of 305
Register Name:
Sa6CODE
Register Desc r iptio n:
Received S a6 Cod ewo rd Reg ister
Register Addr ess :
06Fh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
Sa6n
Sa6n
Sa6n
Sa6n
Default
0
0
0
0
0
0
0
0
This register will report the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe
asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid
codeword. The table below indicates which patterns reported in this register correspond to a given valid Sa6
codeword.
Bits 3 to 0: Sa6 Codeword Bi t (Sa6n )
VALID Sa6 CODE
POSSIBLE REPORTED
PATTERNS
Sa6_8
1000, 0100, 0010, 0001
Sa6_A
1010, 0101
Sa6_C
110, 0110, 0011, 1001
Sa6_E
1110, 0111, 1011, 1101
Sa6_F
1111
Register Name:
RMMR
Register Desc r iptio n:
Receive Mast er M ode Regist er
Register Addr ess :
080h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FRM_EN
INIT_DONE
DRSS
—
—
—
SFTRST
T1/E1
Default
0
0
0
0
0
0
0
0
Bit 7: Framer Enable (FRM_EN). Thi s bit m ust be set to the desired state before writi ng INIT_DONE .
0 = Fram er di sabl ed—held in low -power state.
1 = Fram er enabl ed—all features active.
Bit 6: Initialization Done (INIT _DONE). The user m ust set thi s bit once he has writ ten t he configur ati on regi sters.
The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the
DS26514 wil l check the FRM_E N bit and, if enabled, will begi n oper ation based on the initial c onfiguration.
Bit 5: Disab le Receive-S ide Synchroni z er ( DRS S). This bi t must be set to the desi r ed state before writi ng
INIT_DONE.
0 = Synchr onizer enabled.
1 = Synchr onizer disabled.
Bit 1: Sof t Reset (SFTRST). Level sensitive “ soft” rese t. Should be t ak en high, t hen low to reset the receiver .
0 = Normal operat ion.
1 = Reset the receiver.
Note: This reset does not cl ear the registers.
Bit 0: Receiver T1/E1 Mode Select (T 1/E1) . Sets operat ing mode for rec eiv er only! This bit m ust be set to the
desired stat e before writing INIT_DONE.
0 = T1 operation.
1 = E1 operat ion.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 162 of 305
Register Name:
RCR1 (T1 Mo de)
Register Desc r iptio n:
Receive Co ntrol Regist er 1
Register Addr ess :
081h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
SYNCT
RB8ZS
RFM
ARC
SYNCC
RJC
SYNCE
RESYNC
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin it ion for E1 mode. See RCR1.
Bit 7: S ync Time (SYNCT)
0 = Qualif y 10 bits.
1 = Qualif y 24 bits.
Bit 6: Receive B8ZS Enable (RB8ZS)
0 = B8ZS di sabl ed.
1 = B8ZS enabl ed.
Bit 5: Receive Frame M od e S elect ( RFM)
0 = ESF framing mode.
1 = D4 framing mode.
Bit 4: Auto Resyn c Criteria (ARC)
0 = Resync on OOF or LOS event.
1 = Resync on OOF only .
Bit 3: S ync Cri t eria (SY NCC)
In D4 Framing Mode:
0 = Search for Ft patter n, then search for Fs patt er n.
1 = Cr oss couple Ft and Fs patt er n.
In ESF Framing Mode:
0 = Search for FPS patter n only.
1 = Search for FPS and verify with CRC-6.
Bit 2: Receive Japanese CRC-6 Enable (RJC)
0 = Use ANSI: AT& T:ITU-T CRC-6 calc ulation (normal operat ion).
1 = Use Japanese standar d J T –G 704 CRC-6 calculation .
Bit 1: S ync Enable ( SYNCE)
0 = Auto r esync enabled.
1 = Auto r esync disabled.
Bit 0: Resynchron ize (RESYNC). When toggled fr om low to high, a r esynchr onization of t he r ec eiv e-side framer is
initiated. Must be cleared and set again for a subsequent resync.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 163 of 305
Register Name:
RCR1 (E1 Mod e)
Register Desc r iptio n:
Receive Co ntrol Regist er 1
Register Addr ess :
081h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
RHDB3
RSIGM
RG802
RCRC4
FRC
SYNCE
RESYNC
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin it ion for T1 mode. See RCR1.
Bit 6: Receive HDB3 Enable (RHDB3)
0 = HDB 3 disabl ed.
1 = HDB 3 enabled ( dec oded per O. 162) .
Bit 5: Receive Signaling Mode Select (RS IG M )
0 = CAS signaling mode.
1 = CCS signaling m ode.
Bit 4: Receive G.802 Enable (RG802). See Figure 11-30 for details.
0 = Do not f orce RCHBLK n high dur ing bi t 1 of tim e sl ot 26.
1 = Forc e RCHB LK n high duri ng bit 1 of time slot 26.
Bit 3: Receive CRC-4 Enable (RCRC4)
0 = CRC-4 disabl ed.
1 = CRC-4 enabled.
Bit 2: Frame Resyn c Criteria (FRC)
0 = Resync if FAS receiv ed in er r or three c onsecut ive times.
1 = Resync if FAS or bit 2 of non-FAS i s receiv ed in er ror t hr ee c onsecut ive times.
Bit 1: S ync Enable ( SYNCE)
0 = Auto r esync enabled.
1 = Auto r esync disabled.
Bit 0: Resynchron ize (RESYNC). When toggled fr om low to high, a r esynchr onization of the r ec eiv e-side framer is
initiated. Must be cleared and set again for a subsequent resync.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 164 of 305
Register Name:
T1RIBCC (T1 Mod e)
Register Desc r iptio n:
Receive I n-Band Code Control Register
Register Addr ess :
082h + (200h x (n - 1)) : where n = 1 to 4
Bi t #
7
6
5
4
3
2
1
0
Name
—
—
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin ition for E1 mode. See E1RCR2.
Bits 5 to 3: Receive Up Cod e Length Def in itio n Bi t s (RUP[2: 0])
RUP2
RUP1
RUP0
LENGTH SELECTED
0
0
0
1 bits
0
0
1
2 bits
0
1
0
3 bits
0
1
1
4 bits
1
0
0
5 bits
1
0
1
6 bits
1
1
0
7 bits
1
1
1
8 : 16 bit s
Bits 2 to 0: Receive Down Cod e Length Defini t io n Bits (RDN[ 2: 0] )
RDN2
RDN1
RDN0
LENGTH SELECTED
0
0
0
1 bits
0
0
1
2 bits
0
1
0
3 bits
0
1
1
4 bits
1
0
0
5 bits
1
0
1
6 bits
1
1
0
7 bits
1
1
1
8 : 16 bit s
Register Name:
E1RCR2 (E1 M od e)
Register Desc r iptio n:
Receive Co ntrol Regist er 2
Register Addr ess :
082h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
RLOSA
Default
0
0
0
0
0
0
0
0
Note: This register has an alternate defin it ion for T1 mode. See T1RIBCC.
Bit 0: Receive Loss of Sign al Altern at e Criteria (RLOSA). Defines the c r iteria for a loss of si gnal conditi on.
0 = LOS decl ar ed upon 255 c onsecut ive zeros (125µs).
1 = LOS decl ar ed upon 2048 c onsecut ive zeros (1ms).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 165 of 305
Register Name:
RCR3
Register Desc r iptio n:
Receive Co ntrol Regist er 3
Register Addr ess :
083h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
uALAW
RSERC
BINV1
BINV0
—
PLB
FLB
Default
0
0
0
0
0
0
0
0
Bit 6: u-Law or A -Law Digital Milliwatt Code Select (uALAW)
0 = u-law code i s i nsert ed based on T1RDMWE1–3 or E1RDMWE1–4 registers.
1 = A-l aw code i s inserted based on T1RDMWE1–3 or E1RDMWE1–4 registers.
Bit 5: RSERn Control (RSERC)
0 = Allow RSERn t o output data as received under all conditions (normal operat ion).
1 = Forc e RSERn t o one under loss of fram e alignm ent conditions.
Bits 4 and 3: Receive Bit Inversion (BI NV [ 1: 0])
00 = No inv er si on.
01 = Invert framing.
10 = Invert si gnaling.
11 = Invert payl oad.
Bit 1: P aylo ad Loopback ( PLB)
0 = Loopbac k disabl ed.
1 = Loopbac k enabled.
When PLB is enabl ed, the following will occur :
1) Data will be transmitted on TT IPn and TRINGn synchr onous with RCLKn instead of TCLK n.
2) All of the receive-side signals will continue to operate normally.
3) The TCHCLKn and TCHBLKn signals are forced low.
4) Data at the TSERn, TDATAn, and TSIG n pins i s i gnor ed.
In a PLB si tuat ion, t he DS26514 wi ll l oop the 192 bi t s (248 f or E 1) of payload dat a ( with B PVs correct ed) f r om th e
receive section back to the transmit section. The transmitter will follow the frame alignment provided by the
receiver. The receive frame boundary is automatically fed into the transmit section, such that the transmit frame
position is locked to the receiver (i.e., TSYNCn is sourced from RSYNCn). The FPS framing pattern, CRC-6
cal c ulation, and t he FDL bit s (F A S word, S i, S a, E bits, and CRC-4 for E 1) ar e not looped back , they are r einserted
by the DS 26514 (i .e., the transmit sect ion wil l m odify the payload as if it was input at TS E Rn).
Bit 0: Framer Loop back (FLB)
0 = loopbac k disabl ed
1 = loopbac k enabled
This loopback is usef ul in testing and debugging appl ications. In FLB, the DS 26514 will loop data from the transmit
side back to the r ec eive side. When FLB is enabled, the f ollowing will oc c ur:
1) (T 1 m ode) an unfr am ed all-ones code will be transmit ted at TTIPn and TRINGn.
(E1 mode) normal data will be transmitted at TTIPn and TRI NGn.
2) Data at RTIPn and RRINGn will be ignored.
3) All rec eive-side si gnals will take on timi ng synchr onous with TCLKn instead of RCLKn.
Note t hat it is not ac c eptable to have RCLK n tied t o TCLKn duri ng this l oopbac k bec ause this will cause an
unstable c ondition.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 166 of 305
Register Name:
E1RDMWE1, E 1RDM WE 2, E1RDMWE3, E 1RDM WE4
Register Desc r iptio n:
E1 Receive Digital Milli watt Enable Regist ers 1 to 4
Register Addr ess :
000h, 001h, 002h, 003h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
E1RDMWE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
E1RDMWE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
E1RDMWE3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
E1RDMWE4
Bits 7 to 0: E1 Receive Dig ital Milliwatt Enabl e for Chan nels 1 to 32 (CH[1:32] )
0 = Do not affec t t he r ec eive data associated wit h this channel.
1 = Replac e the receive data associ ated wi th this channel with di gital milliwatt c ode.
Register Name:
T DMWE1, TDMWE2, TDMWE3, TDMWE4 (T1 and E1 Modes)
Register Desc r iptio n:
Transmit Digital Milliwatt Enable Registers 1 to 4
Register Addr ess :
100h, 101h, 102h, 103h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TDMWE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TDMWE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TDMWE3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TDMWE4
Bits 7 to 0: Tran smit Dig ital Milliwatt Enabl e for Channels 1 to 32 (CH[ 1: 32] )
0 = Do not affec t t he transmit data associ ated wi th this channel.
1 = Replac e the transmit data associated wit h this channel wi th di gital milliwatt c ode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 167 of 305
Register Name:
RIOCR
Register Desc r iptio n:
Receive I /O Configu ration Regi st er
Register Addr ess :
084h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RCLKINV
RSYNCINV
H100EN
RSCLKM
RSMS
RSIO
RSMS2
RSMS1
RCLKINV
RSYNCINV
H100EN
RSCLKM
—
RSIO
RSMS2
RSMS1
Default
0
0
0
0
0
1
0
0
Bit 7: RCLKn Invert ( RCLKINV)
0 = No inv er si on.
1 = Inver t RCLKn.
Bit 6: RS YNCn Invert (RSYNCINV)
0 = No inv er si on.
1 = Inver t RSY NCn as ei ther input or output.
Bit 5: H.100 Sync Mode ( H100E N) . See S ection 0 for more in for mation.
0 = Normal operat ion.
1 = RSYNCn and T SSYNCIO n si gnals are shifted.
Bit 4: RSYSCLKn Mode Select (RSCLKM)
0 = If RSYS CLK n is 1.544MHz.
1 = If RSYS CLK n is 2.048M Hz or IBO enabled.
Bit 3: RSYNCn Multiframe Skip Control ( RSMS) (T1 Mode Onl y). Usefu l in framing forma t convers ions fro m D4
to ESF. T his func tion is not available when the receive-side elast ic store is enabled. RSYNCn must be set to output
m ultif r am e pulses.
0 = RSYNCn will output a pul se at ev er y m ultif r am e.
1 = RSYNCn will output a pul se at ev er y other m ultifram e.
Bit 2: RSYNCn I/O Select ( RSIO). (Note: This bit must be set to z er o when elastic stor e is disabled. ) The default
v alue for thi s bi t is a logic 1 so that t he default state of RSYNCn is as an input.
0 = RSYNCn is an output .
1 = RSYNCn is an input (onl y v alid if elasti c stor e enabled) .
Bit 1: RSYNCn Mode Select 2 ( RSMS2)
T1: RSY NCn pin m ust be pr ogr ammed i n the output frame mode.
0 = do not pulse doubl e wide in si gnaling fr am es.
1 = do pulse doubl e wide in signali ng fram es.
E1: RSYNCn pin must be programmed in the output multifra me mode.
0 = RSYNCn out puts CAS m ultif r am e boundar ies.
1 = RSYNCn out puts CRC-4 multiframe boundaries.
In E1 m ode, RSM S 2 also selects which m ultifram e si gnal is available at the RMSYNCn pin, regardless of the
configurati on for RSY NCn. W hen RSMS2 = 0, RMSY NCn output s CAS m ultiframe boundari es; when RSMS2 = 1,
RMSYNCn outputs CRC-4 mult ifra me boundaries.
Bit 0: RSYNC Mode Select 1 (RSMS 1). S elec ts f r am e or multifram e pulse when RSYNCn pin is in output mode. I n
input mode (elasti c store must be enabled) multifr am e m ode is onl y usef ul when receive signali ng r einsertion is
enabled.
0 = Frame mode.
1 = Multiframe mode .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 168 of 305
Register Name:
RESCR
Register Desc r iptio n:
Receive Elastic S tore Con t rol Regi st er
Register Addr ess :
085h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RDATFMT
RGCLKEN
—
RSZS
RESALGN
RESR
RESMDM
RESE
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Chann el Data Format ( RDATF MT)
0 = 64k bps (dat a c ontained in all 8 bits).
1 = 56k bps (dat a c ontained in 7 out of the 8 bit s).
Bit 6: Receive Gapp ed Cl ock En abl e ( RGCL KEN)
0 = RCHCLK n functions normally.
1 = Enabl e gapped bit cl oc k output on RCHCLK n.
Note: RGPCKEN and RDATFMT are not associated w ith the elast ic st or e and will be ex plained in the fractional
support s ec tion.
Bit 4: Receive Slip Zone Select (RSZS ) . T his bit determines the minimum distance allowed between the elastic
store read and write pointers bef or e forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1
conversion applications.
0 = Forc e a sli p at 9 bytes or l ess of separation (used for clustered bl ank channels).
1 = Forc e a sli p at 2 bytes or l ess of separation (used for di str ibuted blank channel s and minim um delay
mode).
Bit 3: Receive Elastic Sto re Align (RE S ALG N). S etting this bit f r om a zero t o a one wi ll f or c e the rec eive elastic
store’ s writ e/read poi nters to a minimum separation of half a frame. No action wil l be taken if the poi nter separ ation
is al r eady gr eater or equal to half a frame. If point er separat ion is less than half a fram e, t he c ommand will be
ex ec uted and the data wil l be disrupted. S hould be toggl ed after RSYSCLKn has been applied and i s stabl e. Must
be cl ear ed and set again for a subseque nt align.
Bit 2: Receive Elastic Sto re Reset ( RESR). Setting this bi t f r om a zero to a one will f or c e the read pointer into the
same frame that the write pointer is exiting, mi nimi zi ng the delay thr ough the el astic store. If this comm and shoul d
plac e the poi nters within the slip zone ( see bi t 4), t hen an immedi ate slip will occur and the pointers will move back
to opposite frames. Should be toggl ed after RSYSCLKn has been applied and is stable. Do not leave thi s bi t set
HIGH.
Bit 1: Receive Elastic Sto re Mini mum Delay Mode (RESMDM)
0 = El astic stor es operat e at full two-fram e depth.
1 = El astic stor es operat e at 32-bit depth.
Bit 0: Receive Elastic Sto re Enabl e ( RESE)
0 = Elastic stor e is bypassed.
1 = El astic stor e is enabl ed.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 169 of 305
Register Name:
ERCNT
Register Desc r iptio n:
Error Cou nter Configurat io n Reg ister
Register Addr ess :
086h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
1SECS
MCUS
MECU
ECUS
EAMS
FSBE
MOSCRF
LCVCRF
1SECS
MCUS
MECU
ECUS
EAMS
—
—
LCVCRF
Default
0
0
0
0
0
0
0
0
Bit 7: One-Second Selec t (1SEC S). This bit all ows for synchronization of the error c ounter updates between
m ultipl e por ts. When E RCNT. 3 = 0, setting this bit (on a speci fic fram er) will updat e the fr am er ’s error c ounters on
the t r ansi tion of the one-second timer fr om fr am er 1. Note t hat this bit should always be clear for framer 1.
0 = Use the one-second t imer that is inter nal to the framer.
1 = Use the one-second t imer fro m fra mer 1 to latch updates.
Bit 6 : Manu al Counter Update Select (MCUS). When manual update mode i s enabl ed with EAM S, this bit c an be
used to allow the i nc om ing LATCH_CNT signal to lat c h all c ounters. Usef ul for synchronously latc hing counters of
m ultipl e DS 26514 c or es l oc ated on the same di e.
0 = MECU is used to manually latch counters .
1 = Counters are latched on the rising edge of the LATCH_CNT signal.
Bit 5: Manual E rror Counter Updat e ( M E CU). When enabled by ERCNT. 3, the c hanging of thi s bi t f r om a 0 to a 1
allows the next clock cycle to load the err or c ounter registers with the latest count s and reset t he c ounters. The
user must wait a minimum of 250µs before reading the error count r egister s to allow for proper update.
Bit 4: E rror Counter Upd at e S elect (ECUS)
T1 mode:
0 = Update error c ounters once a second.
1 = Update error c ounters every 42ms (333 fram es).
E1 mode:
0 = Update error c ounters once a second.
1 = Update error c ounters every 62.5m s (500 frames).
Bit 3: E rror Accumulation Mode Select ( E AMS)
0 = Autom atic updating of error c ounters enabled. The state of ERCNT. 4 determines accumulati on time
(timed update).
1 = User t oggling of E RCNT. 5 determines accumulation time (m anual update).
Bit 2: P CVCR Fs-Bit E rror Report Enabl e (FS BE ) (T1 Mode Only)
0 = Do not repor t bit er r or s i n Fs-bit positi on; onl y Ft -bit position.
1 = Repor t bit er r or s in Fs-bit posi tion as well as Ft-bit position.
Bit 1: Multiframe Out of Sync Count Register Fu nction Select (MOSCRF) (T1 Mode Onl y)
0 = Count err or s i n the f r ami ng bit position.
1 = Count t he num ber of multif r am es out of sync.
Bit 0: T1 Line Code Viol at io n Count Regist er Fu nction Select (LCVCRF)
0 = Do not count exc essive zeros.
1 = Count exc essive zeros.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 170 of 305
Register Name:
RHFC
Register Desc r iptio n:
Receive HDL C-64 FIFO Control Regi st er
Register Addr ess :
087h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
RFHWM1
RFHWM0
Default
0
0
0
0
0
0
0
0
Bits 1 and 0 : Receive FIFO High Watermark Select (RFHWM[ 1: 0]
RFHWM1
RFHWM0
Receive F IFO Watermark
0
0
4 bytes
0
1
16 bytes
1
0
32 bytes
1
1
48 bytes
Register Name:
RIBOC
Register Desc r iptio n:
Receive I nterleave Bus Operation Control Regist er
Register Addr ess :
088h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
IBOSEL
IBOEN
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 4: In t erleave Bus Op erat io n Select (IBOSEL ). This bit sel ec ts channel or frame interleave mode.
0 = Channel Interleave
1 = Frame Interleave
Bit 3: In t erleave Bus Op erat io n Enable (I BOEN)
0 = Int erl eave Bus Oper ation di sabl ed.
1 = Int erl eave Bus Oper ation enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 171 of 305
Register Name:
T1RSCC (T1 Mode Only)
Register Desc r iptio n:
In-Band Receive Spare Con t rol Regi st er
Register Addr ess :
089h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
RSC2
RSC1
RSC0
Default
0
0
0
0
0
0
0
0
Bits 2 to 0: Receive Sp are Cod e Lengt h Defin ition Bits (RSC[ 2: 0] )
RSC2
RSC1
RSC0
LENGTH SELECTED
0
0
0
1 bits
0
0
1
2 bits
0
1
0
3 bits
0
1
1
4 bits
1
0
0
5 bits
1
0
1
6 bits
1
1
0
7 bits
1
1
1
8 : 16 bit s
Register Name:
RXPC
Register Desc r iptio n:
Receive Expansion Port Cont rol Regi st er
Register Addr ess :
08Ah + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RHMS
RHEN
—
—
—
RBPDIR
RBPFUS
RBPEN
RHMS
—
—
—
—
RBPDIR
—
RBPEN
Default
0
0
0
0
0
0
0
0
Bit 7 : Recei ve HDLC-256 Mode Sel ect ( RHMS). T 1 Mo de
0 = Rec eiv e HDLC-256 assigned t o timeslots
1 = Rec eiv e HDLC-256 assigned t o FDL Bits
Bit 7 : Recei ve HDLC-256 Mode Sel ect ( RHMS). E1 Mode
0 = Rec eiv e HDLC-256 assigned t o timeslots
1 = Rec eiv e HDLC-256 assigned t o the Sa Bits
Bit 6 : Recei ve HDLC-256 Enable (RHEN).
0 = Rec eiv e HDLC-256 i s not ac tive.
1 = Rec eiv e HDLC-256 is active.
Bit 2: Receive BERT Port Direction Con t rol (RBPDIR)
0 = Normal (line) operation. Rx BE RT port rec eiv es data from the r ec eiv e fram er .
1 = System ( bac k plane) oper ation. Rx BERT port r ec eiv es data from the transmit pat h. T he transmit path
enters the r ec eive BERT on the line side of the elastic store ( if enabled) .
Bit 1: Receive BERT Port Framed/ Unframed Sel ect (RBPF US ) (T1 Mode Only)
0 = The DS26514’s receive BERT will not clock data from the F-bit posi tion (framed).
1 = The DS26514’s receive BERT will clock data fr om the F-bit posi tion (unframed).
Bit 0: Receive BERT Port Enable (RBPEN)
0 = Rec eiv e BERT port is not active.
1 = Rec eiv e BERT port is active.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 172 of 305
Register Name:
RBPBS
Register Desc r iptio n:
Receive BERT Port Bit Suppress Reg ister
Register Address:
08Bh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BPBSE8
BPBSE7
BPBSE6
BPBSE5
BPBSE4
BPBSE3
BPBSE2
BPBSE1
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Chann el Bit 8 Supp ress ( BP BSE8). MSB of the channel. Set to one to stop this bit fro m being
used.
Bit 6: Receive Chann el Bit 7 Supp ress ( BP BSE7). Set to one to stop t his bi t f r om bei ng used.
Bit 5: Receive Chann el Bit 6 Supp ress ( BP BSE6). Set to one to stop t his bi t f r om bei ng used.
Bit 4: Receive Chann el Bit 5 Supp ress ( BP BSE5). Set to one to stop t his bi t fr om bei ng used.
Bit 3: Receive Chann el Bit 4 Supp ress ( BP BSE4). Set to one to stop t his bi t f r om bei ng used.
Bit 2: Receive Chann el Bit 3 Supp ress ( BP BSE3). Set to one to stop t his bi t f r om bei ng used.
Bit 1: Receive Channel Bit 2 Supp ress ( BP BSE2). Set to one to stop t his bi t f r om bei ng used.
Bit 0: Receive Chann el Bit 1 Supp ress ( BP BSE1). LSB of the c hannel. Set to one to stop this bi t f r om bei ng
used.
Register Name:
RHCS1, RHCS 2, RHCS3, RHCS4
Register Desc r iptio n:
Receive HDLC-256 Channel Select Regi st ers
Register Addr ess :
0DCh, 0DDh, 0DEh, 0DFH
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RHCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RHCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RHCS3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RHCS4
Setting any of the CH1 through CH32 bits i n the RHCS1 thr ough RHCS 4 r egisters wi ll enable the Receive HDLC
cl oc k for the associat ed c hannel tim e, and allow m apping of t he sel ec ted channel data int o the HDLC-256 Port.
Multiple, or all channel s may be selec ted simul taneously.
Register Name:
RHBS
Register Desc r iptio n:
Receive HDL C-256 Bit Suppress Reg ister
Register Addr ess :
08DH
Bit #
7
6
5
4
3
2
1
0
Name
RHBSE
8
RHBSE
7
RHBSE
6
RHBSE
5
RHBSE
4
RHBSE
3
RHBSE
2
RHBSE1
Default
0
0
0
0
0
0
0
0
Bit 7 : Recei ve Channel Bit 8 Supp ress ( BS E 8) . MSB of the c hannel. Set to one to stop this bit f r om bei ng used.
Bit 6 : Recei ve Channel Bit 7 Supp ress ( BS E 7) . Set to one to stop thi s bit from being used.
Bit 5 : Recei ve Channel Bit 6 Supp ress ( BS E 6) . Set to one to stop thi s bit from being used.
Bit 4 : Recei ve Channel Bit 5 Supp ress / Sa4 Bit Suppress (BS E 5). Set to one to stop this bit from being used
Bit 3 : Recei ve Channel Bit 4 Supp ress / Sa5 Bit Suppress (BS E 4). Set to one to stop this bit from being us ed
Bit 2 : Recei ve Channel Bit 3 Supp ress / Sa6 Bit Suppress (BS E 3). Set to one to stop this bit from being used
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 173 of 305
Bit 1 : Recei ve Channel Bit 2 Supp ress/ Sa7 Bit Suppress (BS E 2) . Set to one to stop t his bi t f r om bei ng used
Bit 0 : Receive Channel Bit 1 Suppress / S a8 Bit Supp ress ( BS E 1). LSB of the channel . Set to one t o stop this
bit fr om bei ng used.
Register Name:
RLS1
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 1
Register Addr ess :
090h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RRAIC
RAISC
RLOSC
RLOFC
RRAID
RAISD
RLOSD
RLOFD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Remote Alarm Indicat io n Condi t ion Clear (RRAIC). Fal ling edge detect of RRAI . Set when a
RRAI c ondition has cleared.
Bit 6: Receive Alarm In dication Sign al Condi t io n Clear (RAISC). Falling edge det ec t of RAIS. S et when a RAIS
condi tion has cleared.
Bit 5: Receive Loss of Sign al Condi t ion Clear (RL OSC) . Falling edge detec t of RLOS. Set when an RLOS
condi tion has cleared.
Bit 4: Receive Loss of Frame Condi t ion Clear (RL OF C) . Falling edge detec t of RLOF. S et when an RLOF
condi tion has cleared.
Bit 3: Receive Remote Alarm Indicat io n Condi t ion Detect (RRAID). Rising edge detec t of RRAI. Set when a
remote alarm i s received at RRINGn and RTIPn.
Bit 2: Receive Alarm In dication Sign al Condi t io n Detect ( RAISD) . Rising edge detect of RAIS.Set when an
unframed all-ones code i s received at RRINGn and RTIPn.
Bit 1: Receive Loss of Signal Conditio n Detect (R L OSD). Ri si ng edge detect of RLOS. Set when 192
consecutive zeros have been det ec ted at RRINGn and RTI P n.
Bit 0: Receive Loss of Frame Condi t ion Det ect ( RLOFD). Risi ng edge detect of RLOF. Set when the DS26514
has lost synchronized to the received dat a str eam .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 174 of 305
Register Name:
RLS2 (T1 Mod e)
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 2
Register Addr ess :
091h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—-
—
COFA
8ZD
16ZD
SEFE
B8ZS
FBE
Default
0
0
0
0
0
0
0
0
Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 Mode.
Bit 5: Change of Frame Alignment Event (COFA). Set when the last r esync r esul ted in a change of fram e or
m ultif r am e alignment.
Bit 4: Eigh t Zero Detect E vent (8ZD). Set when a string of at least ei ght consecut ive zeros (regardless of the
length of the string) have been received at RRINGn and RTIP n.
Bit 3: Sixt een Z ero Detect E vent (16ZD). Set when a string of at l east si x teen consecutive zeros (regardless of
the length of the stri ng) hav e been r ec eiv ed at RRI NGn and RT IPn.
Bit 2: S everely Errored Framing Event (SEFE) . Set whe n 2 out of 6 f r ami ng bits (Ft or FPS) ar e r ec eiv ed in error.
Bit 1: B8ZS Cod ewo rd Detect E vent ( B8ZS) . Set when a B8ZS codeword i s detec ted at RRINGn and RTIP n
independent of whether t he B 8ZS mode is selected or not. Useful for autom atically setti ng the line c oding.
Bit 0: Frame Bi t Erro r E vent (F BE ) . Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Register Name:
RLS2 (E1 Mode)
Register Desc r iptio n:
E1 Receive Latched St atus Regi st er 2
Register Addr ess :
091h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
CRCRC
CASRC
FASRC
RSA1
RSA0
RCMF
RAF
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched. Bits 0 to 3 can cause inter r upts. There is no associated real-time register. See RLS2
for T1 Mode.
Bit 6: CRC Resync Crit eria Met E vent (CRCRC). Set when 915:1000 c odewords are received in error.
Bit 5: CAS Resync Criteria Met Event ( CASRC). S et when 2 c onsecut ive CAS MF alignment words are received
in er r or .
Bit 4: FAS Resync Cri t eria Met Event (FASRC). Set whe n 3 c onsecut ive FAS words are rec eived in er r or.
Bit 3: Receive Signaling All On es Event (RSA1). Set when the cont ents of time slot 16 contai ns fewer than three
zeros ov er 16 c onsecut ive frames. This alarm is not disabled in the CCS si gnaling mode.
Bit 2: Receive Signalin g A ll Ze r os Ev e nt (R S A0). Set when ov er a full MF, time slot 16 contains all z er os.
Bit 1: Receive CRC-4 Mult iframe Event (RCMF) . Set on CRC-4 m ultifram e boundar ies; wi ll conti nue to be set
ev er y 2ms on an arbi trar y boundar y if CRC-4 i s di sabl ed.
Bit 0: Receive Align Frame Event (RAF). Set appr oximately ev er y 250µs to alert the host t hat Si and S a bits are
av ailable in the RAF and RNAF regi ster s.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 175 of 305
Register Name:
RLS3 (T1 Mod e)
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 3
Register Addr ess :
092h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LORCC
LSPC
LDNC
LUPC
LORCD
LSPD
LDND
LUPD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create interrupts. See RLS3 for E1 Mode.
Bit 7: Lo ss of Receive Cl ock Cond itio n Cl ear ( LO RCC). Falling edge detect of LO RC. Set when an LORC
condi tion was detect ed and then remov ed.
Bit 6: Spare Cod e Det ect ed Condi t io n Cl ear (L S P C). Falling edge detect of LSP. Set when a spare-code m atch
condi tion was detect ed and then remov ed.
Bit 5: Loop Down Code Det ect ed Condi t io n Cl ear (LDNC). Falling edge detect of LDN. Set when a loop-down
condi tion was detect ed and then remov ed
Bit 4: Loop Up Code Detect ed Condi t io n Cl ear (L UPC). Falling edge detect of LUP. Set when a loop-up
condi tion was detect ed and then remov ed.
Bit 3: Lo ss of Receive Cl ock Cond itio n Detect ( LO RCD). Rising edge detect of LO RC. Set when the RCLKn pin
has not transi tioned for one channel time.
Bit 2: Spare Cod e Det ect ed Condi t io n Detect (L S P D). Risi ng edge detect of LSP. Set when the spare code as
defined in the T1RSCD1:T1RSCD2 registers is being received.
Bit 1: Loop Down Code Det ect ed Condi t io n Detect (LDND) . Ri si ng edge detect of LDN. Set when the loop down
code as defined in the T1RDNCD1:T1RDNCD2 register is being received.
Bit 0: Loop Up Code Detect ed Condi t io n Detect ( LUPD). Risi ng edge detect of LUP. Set when the l oop up code
as defined in the T1RUPCD1:T1RUPCD2 register is bei ng r ec eiv ed.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 176 of 305
Register Name:
RLS3 (E1 Mode)
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 3
Register Addr ess :
092h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LORCC
—
V52LNKC
RDMAC
LORCD
—
V52LNKD
RDMAD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create inter rupts. See RLS3 for T1 Mode.
Bit 7: Lo ss of Receive Cl ock Clear ( LO RCC) . Change of state indicati on. Set when an LORC condition has
cl ear ed (falli ng edge detect of LO RC).
Bit 5: V 5.2 Link Detect ed Clear ( V 52LNKC). Change of state indication. Set when a V52LNK conditi on has
cl ear ed (falli ng edge detect of V52LNK ) .
Bit 4: Receive Dist ant MF Alarm Clear ( RDM AC). Change of stat e indic ation. Set when an RDMA condition has
cl ear ed (falli ng edge detect of RDMA ).
Bit 3: Loss of Receive Clock Det ect (LORCD) . Change of state i ndication. Set when the RCLKn pin has not
transi tioned for one channel tim e ( ri si ng edge detect of LO RC) .
Bit 1: V 5.2 Link Detect ( V 52LNKD). Change of state indic ation. Set on detection of a V5. 2 link identification signal.
(G.965). This is the ri si ng edge detect of V52LNK.
Bit 0: Receive Dist ant MF Alarm Detect ( RDM AD). Change of stat e indic ation. Set when bit-6 of tim e slot 16 in
fram e 0 has been set for two consecut ive mul tifram es. This al arm is not disabled in the CCS signaling m ode. Thi s
is the ri si ng edge detect of RDMA.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 177 of 305
Register Name:
RLS4
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 4
Register Addr ess :
093h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RESF
RESEM
RSLIP
—
RSCOS
1SEC
TIMER
RMF
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create inter rupts.
Bit 7: Receive Elastic Sto re Full Event (RE SF) . Set whe n the receive elastic stor e buffer fills and a fr am e i s
deleted.
Bit 6: Receive E lastic Store Empty Ev ent (RESEM). Set when the receive el astic stor e buffer empties and a
frame is repeated.
Bit 5: Receive Elastic Sto re Slip Occu rrence Even t (RSL IP). Set when the rec eive elastic stor e has ei ther
repeated or deleted a fram e.
Bit 3: Receive Signaling Change Of S t at e Event (RSCOS). Set when any channel sel ec ted by the Rec eiv e
Si gnaling Change Of Stat e Int er r upt Enable regi ster s (RSCSE1 through RSCSE 3) changes signal ing state.
Bit 2: One-Second Timer (1SEC). Set on every one-second i nterval based on RCLKn.
Bit 1: Ti mer E vent (TIME R) . T his status bi t i ndicates that the perf ormance monitor counter s have been updated
and are avai lable to be read by the host. The err or c ounter update interval as determined by the setti ngs i n the
Error Counter Configur ation Register ( ERCNT).
T1: S et on incr em ents of 1 second or 42ms based on RCLKn, or a m anual latch event.
E1: S et on incr em ents of 1 second or 62.5ms based on RCLKn, or a manual latch event.
Bit 0: Receive Multiframe E vent ( RMF)
T1 Mode: Set ev ery 1. 5m s on D4 MF boundaries or every 3m s on ESF MF boundaries.
E1 Mode: Set ever y 2.0m s on receive CAS multiframe boundaries to alert host the si gnaling data is
av ailable. Continues t o set on an ar bitrary 2.0ms boundary when CAS signaling is not enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 178 of 305
Register Name:
RLS5
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 5 (HDLC-64)
Register Addr ess :
094h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
ROVR
RHOBT
RPE
RPS
RHWMS
RNES
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can cause interrupts.
Bit 5: Receive FIF O O verrun ( ROVR) . Set when the receive HDLC cont r oller has terminated pack et rec eption
because t he FIFO buffer is full.
Bit 4: Receive HDLC Op eni ng Byt e Event (RHO BT). Set when the next byte available i n the rec eiv e FIFO is the
first byte of a message.
Bit 3: Receive Packet End Event (RP E). Set when the HDLC controll er detects ei ther the finish of a v alid
message ( i.e. , CRC chec k complete) or when the cont rol ler has ex per ienced a m essage f ault such as a CRC
checking error , or an ov er r un condi tion, or an abort has been seen. This is a latched bit and wi ll be cleared when
read.
Bit 2: Receive Packet Start Event (RPS). Set when the HDLC cont r oller det ects an openi ng by te. Thi s i s a
latched bit and wi ll be cleared when read.
Bit 1: Receive FIF O Above Hig h Watermark Set E vent (RHWMS). S et when the receive 64-byte FIFO crosses
the high watermark as defined by the Rec eiv e HDLC FIFO Cont r ol Register (RHFC). Risi ng edge detect of RHWM.
Bit 0: Receive FIF O No t Empty Set Event (RNES) . Set when the receive FIFO has transitioned from “ em pty” to
“not em pty” (at least one byte has been put i nto the FIFO ) . Rising edge detec t of RNE.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 179 of 305
Register Name:
RLS7 (T1 Mod e)
Register Desc r iptio n:
Receive L at ched Statu s Regi st er 7
Register Addr ess :
096h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
RRAI-CI
RAIS-CI
RSLC96
RFDLF
BC
BD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create inter rupts. See RLS7 for E1 Mode.
Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI patt er n has been detec ted by the receiver. This bit is
activ e in E SF frami ng mode onl y, and wi ll set onl y if an RAI condi tion is being det ect ed (RRTS1.3). When the host
reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1
seconds).
Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit
will set onl y if an AI S conditi on is bei ng detect ed (RRTS1.2). Thi s is a l atched bit that must be c lear ed by the host,
and will set again each time the AIS-CI pat tern i s detected ( appr ox imatel y every 1.2 seconds).
Bit 3: Receive SLC-96 Alignment Even t (RSLC96). Set when a valid SLC-96 alignment patt er n is detec ted i n the
Fs bi t stream , and the T1RSLC1–3 regi ster s have data availabl e for ret ri ev al. See Sec tion 9.9.4.4 for more
information.
Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit T1RFDL regi ster is full. Usef ul f or SLC-96
operation, or manual ext r ac tion of F DL data bit s. S ee Sect ion 9.9.5.4 for more in formation.
Bit 1: BOC Cl ear Event ( BC). Set when a vali d BOC is no l onger detected (with the di si ntegration filt er applied).
Bit 0: BOC Detect E vent ( BD). S et when a valid BOC has been detec ted (with the BOC filter applied).
Register Name:
RLS7 (E1 Mode)
Register Desc r iptio n:
Receive L at ched Status Regi st er 7
Register Addr ess :
096h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
Sa6CD
SaXCD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create inter rupts. See RLS7 for T1 Mode.
Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit
positions.
Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled
SaX bit s are selec ted by theE1RSAIMR register.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 180 of 305
Register Name:
RSS1, RSS2, RSS3, RSS4
Register Desc r iptio n:
Receive-Sign aling St at us Regi st ers 1 to 4
Register Addr ess :
098h, 099h, 09Ah, 09Bh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1*
RSS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RSS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17*
RSS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RSS4 (E1
Mode Only)
Note: Status bits in this register are latched.
When a channel ’s si gnaling data changes state, the respective bit in regi ster s RSS1–4 will be set and latched. The
RSCOS bi t (RLS4.3) will be set i f t he channel was also enabled by setting the appropriate bit i n RSCSE1–4. The
INTB si gnal will go low if enabled by the interr upt mask bit RIM4.3. The bit wi ll r em ain set unt il r ead.
*Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3
represents reserved bits and the distant multiframe alarm.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 181 of 305
Register Name:
T1RSCD1 (T1 Mode Only)
Register Desc r iptio n:
Receive Spare Code Defini tion Regi st er 1
Register Addr ess :
09Ch + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Spare Code Definition Bi t 7 (C7). Fir st bit of the repeating pat tern.
Bit 6: Receive Spare Code Definition Bi t 6 (C6). A Don’t Care if a 1-bit length is selected.
Bit 5: Receive Spare Code Definition Bi t 5 (C5). A Don’t Care if a 1- or 2-bit length is selected.
Bit 4: Receive Spare Code Definition Bi t 4 (C4). A Don’t Care if a 1- to 3-bit length is sel ec ted.
Bit 3: Receive Spare Code Definition Bi t 3 (C3). A Don’t Care if a 1- to 4-bit length is sel ec ted.
Bit 2: Receive Spare Code Definition Bi t 2 (C2). A Don’t Car e if a 1- t o 5-bit length is selected.
Bit 1: Receive Spare Code Definition Bi t 1 (C1). A Don’t Care if a 1- to 6-bit length is sel ec ted.
Bit 0: Receive Spare Code Definition Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is sel ec ted.
Register Name:
T1RSCD2 (T1 Mode Only)
Register Desc r iptio n:
Receive Spare Code Definiti on Regi st er 2
Register Addr ess :
09Dh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Spare Code Definition Bi t 7 (C7). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 6: Receive Spare Code Definition Bi t 6 (C6). A Don’t Care if a 1- to 7-bit length is sel ec ted.
Bit 5: Receive Spare Code Definition Bi t 5 (C5). A Don’t Care if a 1- to 7-bit length is selected.
Bit 4: Receive Spare Code Definition Bi t 4 (C4). A Don’t Care if a 1- to 7-bit length is sel ec ted.
Bit 3: Receive Spare Code Definition Bi t 3 (C3). A Don’t Care if a 1- to 7-bit length is sel ec ted.
Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don’t Car e if a 1- t o 7-bit length is sel ec ted.
Bit 1: Receive Spare Code Definition Bi t 1 (C1). A Don’t Care if a 1- to 7-bit length is sel ec ted.
Bit 0: Receive Spare Code Definition Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 182 of 305
Register Name:
RIIR
Register Desc r iptio n:
Receive I nterrupt In format ion Reg ister
Register Addr ess :
9Fh + (200h x ( n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
RLS7
RLS6*
RLS5
RLS4
RLS3
RLS2**
RLS1
Default
0
0
0
0
0
0
0
0
* RLS6 is reserved for future use.
** Curr ently RLS 2 does not cr ea t e an interru pt , th er e fore th is b it is not use d in T1 m od e.
The Receive Interrupt Information Register indicates which of the DS26514 status registers are generating an
int errupt. W hen an int errupt occurs, the host can read RIIR t o quickly identif y which of the receiv e status register s
is (are) causing the interrupt(s). The Receive Interrupt Information Register bits will clear once the appropriate
interrupt has been serviced and cleared, as long as no additional, unmasked interrupt condition is present in the
associat ed stat us register. Stat us bit s that hav e been masked vi a the Receive Interrupt Mask (RIMx ) registers wil l
also be masked from the RIIR register.
Register Name:
RIM1
Register Description:
Receive I nterrupt M ask Regi st er 1
Register Addr ess :
0A0h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RRAIC
RAISC
RLOSC
RLOFC
RRAID
RAISD
RLOSD
RLOFD
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Remote Alarm Indicat io n Condi tion Clear (RRAIC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 6: Receive Alarm In dication Sign al Condi t io n Clear (RAISC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: Receive Loss of Sign al Condi t ion Clear (RL OSC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 4: Receive Loss of Frame Condi t ion Clear (RL OF C)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3 : Recei ve Remote Alarm In di cat ion Condition Detect (RRAID)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Receive Alarm In dication Sign al Condi t io n Detect ( RAISD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Receive Loss of Sign al Condi t ion Det ect ( RLOSD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Receive Loss of Frame Condi t ion Det ect ( RLOFD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 183 of 305
Register Name:
RIM2 (E1 Mo de Only)
Register Desc r iptio n:
E1 Receive Interrup t Mask Reg ister 2
Register Addr ess :
0A1h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSA1
RSA0
RCMF
RAF
Default
0
0
0
0
0
0
0
0
Bit 3: Receive-Signaling All Ones Event (RSA1)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Receive-Signalin g All Zero s E vent ( RS A0)
0 = Interrupt mas ked.
1 = interrupt enabled.
Bit 1: Receive CRC-4 Mult iframe Event (RCMF)
0 = Interrupt masked.
1 = Int er r upt enabled.
Bit 0: Receive Alig n Frame E vent (RAF)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 184 of 305
Register Name:
RIM3 (T1 Mod e)
Register Desc r iptio n:
Receive I nterrupt M ask Regi st er 3
Register Addr ess :
0A2h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LORCC
LSPC
LDNC
LUPC
LORCD
LSPD
LDND
LUPD
Default
0
0
0
0
0
0
0
0
Note: See RIM3 for E1 Mode.
Bit 7: Lo ss of Receive Cl ock Cond itio n Cl ear ( LO RCC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 6: Spare Cod e Det ect ed Condi t io n Cl ear (L S P C)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: Loop Down Code Det ect ed Condi t io n Cl ear (LDNC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 4: Loop Up Code Detect ed Condi t io n Cl ear (LUPC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Lo ss of Receive Cl ock Cond itio n Detect ( LO RCD)
0 = Interrupt mas ked
1 = Int er r upt enabled
Bit 2: Spare Cod e Det ect ed Condi t io n Detect (L S P D)
0 = Interrupt mas ked.
1 = Int er r upt enabl ed.
Bit 1 : Loop Down Cod e Detected Condition Det ect (LDND)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Loop Up Code Detect ed Condi t io n Detect ( LUPD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 185 of 305
Register Name:
RIM3 (E1 Mo de)
Register Desc r iption:
E1 Receive Interrup t Mask Reg ister 3
Register Addr ess :
0A2h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
LORCC
—
V52LNKC
RDMAC
LORCD
—
V52LNKD
RDMAD
Default
0
0
0
0
0
0
0
0
Note: See RIM3 for T1 Mode.
Bit 7: Lo ss of Receive Cl ock Clear ( LO RCC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: V 5.2 Link Detect ed Clear ( V 52LNKC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 4: Receive Dist ant MF Alarm Clear ( RDM AC)
0 = Interrupt mas ked.
1 = Interrupt enabled.
Bit 3: Lo ss of Receive Cl ock Detect (LORCD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: V 5.2 Link Detect ( V 52LNKD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Receive Dist ant MF Alarm Detect ( RDM AD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 186 of 305
Register Name:
RIM4
Register Desc r iptio n:
Receive I nterrupt M ask Regi st er 4
Register Addr ess :
0A3h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RESF
RESEM
RSLIP
—
RSCOS
1SEC
TIMER
RMF
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Elastic Sto re Full Event (RE SF)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 6: Receive Elastic Sto re E mpty Event ( RESEM )
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: Receive Elastic Sto re Slip Occu rrence Even t (RSL I P)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Receive Signaling Change Of S t at e Event (RSCOS)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: One-Second Timer (1SEC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Ti mer E vent (TIME R)
0 = Interrupt masked.
1 = Int er r upt enabled.
Bit 0: Receive Multiframe E vent ( RMF)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 187 of 305
Register Name:
RIM5
Register Desc r iptio n:
Receive I nterrupt M ask 5 (HDLC-64)
Register Addr ess :
0A4h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
ROVR
RHOBT
RPE
RPS
RHWMS
RNES
Default
0
0
0
0
0
0
0
0
Bit 5: Receive FIF O O verrun ( ROVR)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 4: Receive HDLC Op eni ng Byt e Event (RHO BT)
0 = Interrupt mas ked.
1 = Interrupt enabled.
Bit 3: Receive Packet End Event (RP E)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Receive Packet Start Event (RP S )
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Receive FIF O Above Hig h Watermark Set E vent (RHWMS)
0 = Interrupt masked.
1 = Int er r upt enabled.
Bit 0: Receive FIF O No t Empty Set Event (RNES)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 188 of 305
Register Name:
RIM7 (T1 Mod e)
Register Desc r iptio n:
Receive I nterrupt M ask Regi st er 7 ( BOC:FDL )
Register Addr ess :
0A6h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
RRAI-CI
RAIS-CI
RSLC96
RFDLF
BC
BD
Default
0
0
0
0
0
0
0
0
Note: See RIM7 for E1 Mode.
Bit 5: Receive RAI-CI (RRAI -CI)
0 = Interrupt mas ked.
1 = Interrupt enabled.
Bit 4: Receive AIS -CI (RAIS-CI)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Receive SLC-96 (RSLC96)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Receive FDL Reg ister Full (RFDLF )
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: BOC Cl ear Event ( BC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: BOC Detect E vent ( BD)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Register Name:
RIM7 (E1 Mo de)
Register Desc r iptio n:
Receive I nterrupt M ask Regi st er 7 ( BOC:FDL )
Register Addr ess :
0A6h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
Sa6CD
SaXCD
Default
0
0
0
0
0
0
0
0
Note: See RIM7 for T1 Mode.
Bit 1: S a6 Codeword Det ect (Sa6CD). This bit will enable the i nterrupt generated when a v alid codeword (per
ETS 300 233) is detec ted i n the Sa6 bits.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: S aX Chang e Detect (S aX CD) . T his bit will enable the i nterrupt gener ated when a change of state i s
detected in any of the unmasked SaX bi t positions. The masked or unm asked SaX bi ts are selec ted by the
E1RSAIMR register.
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 189 of 305
Register Name:
RSCSE1, RSCSE2, RSCSE3, RSCSE4
Register Description:
Receive-Signaling Change of State Enable Registers 1 to 4
Register Addr ess :
0A8h, 0A9h, 0AAh, 0ABh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RSCSE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RSCSE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RSCSE3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RSCSE4 (E1
Mode Only)
Setting any of the CH[ 1:32] bits in t he RS CSE1 t o RSCSE4 regi ster s will c ause RSCO S (RLS4.3) to be set when
that c hannel’s si gnali ng data changes st ate.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 190 of 305
Register Name:
T1RUPCD1 (T1 Mode Only)
Register Desc r iptio n:
Receive Up Cod e Def in ition Register 1
Register Addr ess :
0ACh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Up Cod e Defini t io n Bi t 7 (C7). Fi r st bit of the repeating patter n.
Bit 6: Receive Up Cod e Defini t io n Bi t 6 (C6). A Don’t Care if a 1-bi t lengt h is selec ted.
Bit 5: Receive Up Cod e Defini t io n Bi t 5 (C5). A Don’t Care if a 1- or 2-bit l ength i s selected.
Bit 4: Receive Up Cod e Defini t io n Bi t 4 (C4). A Don’t Care if a 1- to 3-bit length is selected.
Bit 3: Receive Up Cod e Defini t io n Bi t 3 (C3). A Don’t Care if a 1- to 4-bit length is selected.
Bit 2: Receive Up Cod e Defini t io n Bi t 2 (C2). A Don’t Care if a 1- to 5-bit length is selected.
Bit 1: Receive Up Cod e Defini t io n Bi t 1 (C1). A Don’t Care if a 1- to 6-bit length is selected.
Bit 0: Receive Up Cod e Defini t io n Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
Register Name:
T1RUPCD2 (T1 Mode Only)
Register Desc r iptio n:
Receive Up Cod e Def in ition Register 2
Register Addr ess :
0ADh + (200h x (n - 1)) : wh ere n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Up Cod e Defini t io n Bi t 7 (C7). A Don’t Care if a 1- to 7-bit length is selected.
Bit 6: Receive Up Cod e Defini t io n Bi t 6 (C6). A Don’t Care if a 1- to 7-bit length is selected.
Bit 5: Receive Up Cod e Defini t io n Bi t 5 (C5). A Don’t Care if a 1- to 7-bit length is selected.
Bit 4: Receive Up Cod e Defini t io n Bi t 4 (C4). A Don’t Care if a 1- to 7-bit length is selected.
Bit 3: Receive Up Cod e Defini t io n Bi t 3 (C3). A Don’t Care if a 1- to 7-bit length is selected.
Bit 2: Receive Up Cod e Defini t io n Bi t 2 (C2). A Don’t Care if a 1- to 7-bit length is selected.
Bit 1: Receive Up Cod e Defini t io n Bi t 1 (C1). A Don’t Care if a 1- to 7-bit length is selected.
Bit 0: Receive Up Cod e Defini t io n Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is selected.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 191 of 305
Register Name:
T1RDNCD1 (T1 Mode On ly)
Register Desc r iptio n:
Receive Do wn Cod e Defini t io n Reg ister 1
Register Addr ess :
0AEh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Note: Writing this register resets the detector’s integration period.
Bit 7: Receive Down Cod e Defini t io n Bi t 7 (C7). Fi r st bit of the r epeating patter n.
Bit 6: Receive Down Cod e Defini t io n Bi t 6 (C6). A Don’t Care if a 1-bi t length is sel ec ted.
Bit 5: Receive Down Cod e Defini t io n Bi t 5 (C5). A Don’t Care if a 1- or 2-bit length is selected.
Bit 4: Receive Down Cod e Defini t io n Bi t 4 (C4). A Don’t Care if a 1- to 3-bit length is select ed.
Bit 3: Receive Down Cod e Defini t io n Bi t 3 (C3). A Don’t Care if a 1- to 4-bit length is select ed.
Bit 2: Receive Down Cod e Defini t io n Bi t 2 (C2). A Don’t Care if a 1- to 5-bit length is select ed.
Bit 1: Receive Down Cod e Defini t io n Bi t 1 (C1). A Don’t Care if a 1- to 6-bit length is select ed.
Bit 0: Receive Down Cod e Defini t io n Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is select ed.
Register Name:
T1RDNCD2 (T1 Mode On ly)
Register Desc r iptio n:
Receive Do wn Cod e Defini t io n Reg ister 2
Register Addr ess :
0AFh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive Down Cod e Defini t io n Bi t 7 (C7). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 6: Receive Down Cod e Defini t io n Bi t 6 (C6). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 5: Receive Down Cod e Defini t io n Bi t 5 (C5). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 4: Receive Down Cod e Defini t io n Bi t 4 (C4). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 3: Receive Down Cod e Defini t io n Bi t 3 (C3). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 2: Receive Down Cod e Defini t io n Bi t 2 (C2). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 1: Receive Down Cod e Defini t io n Bi t 1 (C1). A Don’t Care if a 1- to 7-bit length is select ed.
Bit 0: Receive Down Cod e Defini t io n Bi t 0 (C0). A Don’t Care if a 1- to 7-bit length is select ed.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 192 of 305
Register Name:
RRTS1
Register Desc r iptio n:
Receive Real -Time Status Regi st er 1
Register Addr ess :
0B0h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
RRAI
RAIS
RLOS
RLOF
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are real-time (not latched).
Bit 3: Receive Remote Alarm Indicat io n Condition (RRAI ). S et when a remot e alarm is received at RRINGn and
RTIPn.
Bit 2: Receive Alarm In dication Sign al Condi t io n (RAIS ) . S et when an unfr am ed all-ones code is received at
RRING n and RTI P n.
Bit 1: Receive Loss of Sign al Condi t ion ( RLO S). Set when 192 consecutive zeros have been detected at
RRING n and RTI P n.
Bit 0: Receive Loss of Frame Condi t ion ( RLOF) . Set when the DS26514 is not synchr onized t o the received
data stream.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 193 of 305
Register Name:
RRTS3 (T1 Mod e)
Register Desc r iptio n:
Receive Real -Time Status Regi st er 3
Register Addr ess :
0B2h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
LORC
LSP
LDN
LUP
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are real-time (not latched). See RRTS3 fo r E1 Mode .
Bit 3: Lo ss of Receive Cl ock Cond itio n (LO RC) . Set when the RCLKn pin has not transi tioned for one channel
time.
Bit 2: Spare Cod e Det ect ed Condi t io n (LSP ) . Set when t he spare code as defi ned in the T1RSCD1:T1RSCD2
regi ster s i s bei ng r ec eived.
Bit 1: Loop -Down Code Det ect ed Cond ition (L DN). Set when the loop-down code as def ined i n the
T1RDNCD1:T1RDNCD2 register is bei ng r ec eived.
Bit 0: Loop -Up Code Detect ed Cond ition (LUP ). S et when the loop-up code as defined in the
T1RUPCD1:T1RUPCD2 register is being receiv ed.
Register Name:
RRTS3 (E1 Mo de)
Register Desc r iptio n:
Receive Real -Time Status Regi st er 3
Register Addr ess :
0B2h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
LORC
—
V52LNK
RDMA
Default
0
0
0
0
0
0
0
0
Note: Al l bits in this register are real-time (not latched). See RRTS3 fo r T1 Mod e.
Bit 3: Lo ss of Receive Cl ock Cond itio n (LO RC) . Set when the RCLKn pin has not transi tioned for one channel
time.
Bit 1: V 5.2 Link Detect ed Cond ition (V52LNK). Set on det ec tion of a V5. 2 link identif ication
signal ( G. 965) .
Bit 0: Receive Dist ant MF Alarm Cond iti on ( RDM A). Set when bit -6 of time slot 16 in fram e 0 has been set for
two consecut ive multif r am es. Thi s al arm is not disabl ed in the CCS signaling mode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 194 of 305
Register Name:
RRTS5
Register Desc r iptio n:
Receive Real -Time Status Regi st er 5 ( HDLC-64)
Register Addr ess :
0B4h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
PS2
PS1
PS0
—
—
RHWM
RNE
Default
0
0
0
0
0
0
0
0
Note: Al l bits in t his register are real time.
Bits 6 to 4: Receive Packet S t at us (PS [ 2: 0] ). These are real -time bit s i ndic ating the status as of the last r ead of
the rec eive FIFO.
PS2
PS1
PS0
PACKET STATUS
0 0 0 In Progress: End of m essage has not y et been reached.
0 0 1 Packet OK: Packet ended with correct CRC codeword.
0 1 0 CRC Error: A closi ng flag was detected, preceded by a corrupt CRC codeword.
0 1 1 Abort: Packet ended because an abort signal wa s detec ted (7 or more ones in a row).
1 0 0 Overrun: HDLC controller t erminated reception of pac ket bec ause receive FIFO is full.
Bit 1: Receive FIF O Above Hig h Watermark Co ndition (RHWM) . Set when the rec eive 64-byte FI FO fills beyond
the high watermark as defined by the Rec eiv e HDLC FIFO Cont r ol Register (RHFC). This is a real -time bi t.
Bit 0: Receive FIF O No t Empty Condi t ion ( RNE ). S et when the rec eive 64-byte FIFO has at least one byte
av ailable for a read. This i s a real -time bi t.
Register Name:
RHPBA
Register Desc r iptio n:
Receive HDL C-64 P acket Byt es Avail able Register
Register Addr ess :
0B5h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
MS
RPBA6
RPBA5
RPBA4
RPBA3
RPBA2
RPBA1
RPBA0
Default
0
0
0
0
0
0
0
0
Bit 7: Message S t atus ( M S)
0 = Byt es i ndic ated by RPBA 0 through RP B A 6 ar e the end of a message. Host m ust c hec k the HDLC
Status register for details.
1 = Byt es i ndic ated by RPBA 0 through RP B A 6 ar e the beginning or conti nuation of a m essage. The host
does not need to chec k the HDLC Status. T he MS bit will ret ur n to a value of ‘1’ when the Rx HDLC FIFO
is empty .
Bits 6 to 0: Receive FIFO P acket Byt es Avail able Count (RPBA[6:0]). RP B A 0 is the LSB.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 195 of 305
Register Name:
RHF
Register Desc r iptio n:
Receive HDL C-64 FIFO Register
Register Addr ess :
0B6h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RHD7
RHD6
RHD5
RHD4
RHD3
RHD2
RHD1
RHD0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive HDLC Dat a Bit 7 ( RHD7) . MSB of a HDLC packet dat a byte.
Bit 6: Receive HDLC Dat a Bit 6 ( RHD6)
Bit 5: Receive HDLC Dat a Bit 5 ( RHD5)
Bit 4: Receive HDLC Dat a Bit 4 ( RHD4)
Bit 3: Receive HDLC Dat a Bit 3 ( RHD3)
Bit 2: Receive HDLC Dat a Bit 2 ( RHD2)
Bit 1: Receive HDLC Dat a Bit 1 ( RHD1)
Bit 0: Receive HDLC Dat a Bit 0 ( RHD0) . LSB of a HDLC packet data byte.
Register Name:
RBCS1, RBCS 2, RBCS3, RBCS4
Register Desc r iptio n:
Receive Bl ank Channel Select Reg isters 1 to 4
Register Addr ess :
0C0h, 0C1h, 0C2h, 0C3h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RBCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RBCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RBCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RBCS4 (E1
Mode Only)
Bits 7 to 0: Receive Blank Chann el Sel ect for Channels 1 to 32 (CH[1:32] )
0 = Do not blank this channel (channel dat a is available on RSERn).
1 = Data on RSE Rn is for c ed to all ones for this channel.
Note t hat when two or more sequential channels are chosen to be blanked, t he r ec eiv e-sli p z one sel ec t bit shoul d
be set to zer o. If t he blank c hannels are di str ibuted (such as 1, 5, 9, 13, 17, 21, 25, 29), t hen the RSZ S bit c an be
set to one, whic h m ay provide a lower occurrenc e of slips in cer tai n applicati ons.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 196 of 305
Register Name:
RCBR1, RCBR2, RCBR3, RCBR4
Register Desc r iptio n:
Receive Ch annel Blocking Reg isters 1 to 4
Regis ter Address:
0C4h, 0C5h, 0C6h, 0C7h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
RCBR4 (E1
Mode Only)*
Bits 7 to 0: Channel Bl ocking Con t rol Bits for Receive Ch annels 1 to 32 (CH[1:32])
0 = Forc e the RCHBLK n pin to remain l ow duri ng this channel time.
1 = Forc e the RCHBLK n pin high during this channel time .
*Note t hat RCBR4 has two functions:
When 2.048M Hz bac k plane m ode is selected, t his register allows the user to enabl e the channel bloc ki ng
signal for any of the 32 possible backpl ane c hannels.
When 1.544MHz backp lane mode is select ed, the LSB of this regi ster determines whether or not the
RCHBLKn signal will pulse hi gh dur ing t he F-bit time. In thi s mode RCBR4.1 to RCB R4.7 should be set to
0.
RCBR4.0 = 0, do not pulse RCHBLKn during the F-bit.
RCBR4.0 = 1, pulse RCHBLKn dur ing the F-bit.
Register Name:
RSI1, RSI2, RSI3, RSI 4
Register Desc r iptio n:
Receive-Signaling Reinsertion Enable Registers 1 to 4
Register Addr ess :
0C8h, 0C9h, 0CAh, 0CBh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RSI1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RSI2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RSI3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RSI4 ( E 1
Mode Only)
Setting any of t he CH[1:24] bits in the RSI1 through RSI4 r egisters will cause signaling data to be reinserted for the
associated channel . RSI 4 is used for 2.048MHz backplane operat ion.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 197 of 305
Register Name:
RGCCS1, RGCCS 2, RGCCS 3, RG CCS 4
Register Desc r iptio n:
Receive G apped Clock Channel Select Regi st ers 1 to 4
Register Addr ess :
0CCh, 0CDh, 0CEh, 0CFh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RGCCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RGCCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RGCCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
RGCCS4 ( E 1
Mode Only)*
Bits 7 to 0: Gapped Clock Channel Select Bits for Receive Ch annels 1 to 32(CH[1:32] )
0 = No cl ock is present on RCHCLKn during this channel time.
1 = Forc e a cl ock on RCHCLKn duri ng this channel time. T he cl oc k will be synchr onous with RCLK n if the
elastic store is di sabl ed, and sync hr onous with RSYSCLKn if the el astic store is enabled.
* Note that RGCCS4 has two functions:
When 2.048M Hz bac k plane m ode is selected, t his register allows the user t o enable the gapped c lock on
RCHCLKn for any of the 32 possible backplane channels.
When 1.544M Hz bac k plane m ode is selected, t he LSB of this register determines whether or not a clock is
generated on RCHCLK n dur ing the F-bit time:
RGCCS4.0 = 0, do not gener ate a clock duri ng the F-bit.
RGCCS4.0 = 1, generate a clock duri ng the F-bit.
In t his mode RG CCS 4.1 to RGCCS4.7 should be set to 0.
Register Name:
RCICE1, RCICE2, RCI CE3, RCICE4
Register Desc r iptio n:
Receive Ch annel Idle Code Enable Reg isters 1 to 4
Register Addr ess :
0D0h, 0D1h, 0D2h, 0D3h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCICE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCICE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCICE3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RCICE4 ( E 1
Mode Only)
Bits 7 to 0: Receive Chann els 1 to 32 Code Insert ion Con t rol Bits ( CH[ 1: 32] )
0 = Do not insert data from the Idl e Code A r r ay i nto t he receive data stream.
1 = Insert data from the Idl e Code A r r ay i nto t he r ec eive data str eam .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 198 of 305
Register Name:
RBPCS1, RBP CS 2, RBPCS 3, RBPCS 4
Register Desc r iptio n:
Receive BERT Port Chann el Select Regi st ers 1 t o 4
Register Addr ess :
0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RBPCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RBPCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RBPCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
RBPCS4 (E1
Mode Only)
Bits 7 to 0: BERT Port Chann el Select Receive Channels 1 to 32 (CH[1: 32] )
0 = Do not enable the rec eiv e B E RT cloc k for the associated c hannel time, or map the sel ec ted channel
data out of t he r ec eiv e BERT port.
1 = Enabl e r ec eiv e BERT cl ock f or the associated channel time, and allow mapping of the selected
channel data out of the receive BE RT port. M ultiple or all c hannels m ay be sel ec ted simultaneousl y .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 199 of 305
10.4.2 Transmit Register Descriptions
10.4.2.1 Tran smit HDLC-64 Regi st er Def in itions
Register Name:
THC1
Register Desc r iptio n:
Transmit HDLC-64 Control Regi st er 1
Register Addr ess :
110h + (200h x (n-1) ) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
NOFS
TEOML
THR
THMS
TFS
TEOM
TZSD
TCRCD
Default
0
0
0
0
0
0
0
0
Bit 7 : Nu mber O f Flag s Select (NOFS).
0 = send one flag between consecutiv e m essages
1 = send two flags between con secut ive messages
Bit 6 : T ran smit End o f Messag e and Loop (TE OML). T o l oop on a m essage, shoul d be set to a one j ust befor e
the last data byte of an HDLC pac k et is written into the transmit FIFO. The message will repeat until the user clears
this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will
com plete t hen fl ags wi ll be t ransmit ted unti l new m essage is wri tt en to t he FI FO. If the host t erm i nates the l oop by
writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new
m essage will start. If not disabl ed v ia TCRCD, the transmitt er will autom atically append a t wo-byte CRC c ode to t he
end of all messages.
Bit 5 : T ransmit HDLC-64 Reset ( THR). Will reset the transm it HDLC-64 contr oller and flush the transmit FIFO. An
abort followed by 7Eh or FFh flags/idle will be tr ansmitted until a new packet is ini tiated by writing new data into the
FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26514 will clear it once
the reset oper ation is complete. Total time for the r eset is l ess than 250µs.
0 = Normal operat ion
1 = Reset transmit HDLC-64 contr oller and flush the transmi t FIFO
Bit 4 : T ransmit HDLC-64 Mapp in g Select (THMS).
0 = Transmit HDLC-64 assigned to c hannels
1 = Transmit HDLC-64 assigned to FDL(T1 m ode) , Sa Bi ts(E1 mode). This m ode m ust be enabled with
TCR2.7.
Bit 3 : T ransmit Flag/Idle Select (TFS). Thi s bi t selec ts the inter-message fi ll c har ac ter after the closing and
before the opening flags (7Eh).
0 = 7E h
1 = FFh
Bit 2 : T ransmit End of Message (T EOM ). S hould be set to a one just before the l ast data byte of an HDLC
packet is wri tt en into the transmit FIFO at THF. If not disabled v ia TCRCD, t he transmitter will autom atically append
a two byte CRC code to the end of t he m essage.
Bit 1 : T ransmit Zero Stu f f er Defeat (TZ S D). The Zero Stuffer function automatically inserts a zero in the
m essage fi eld (between the flags) af ter 5 consecut ive ones to pr event the emulation of a fl ag or abor t sequenc e by
the dat a pattern. The receiver automati c ally r em ov es (de-st uff s) any z er o after 5 ones in the message fiel d.
0 = enable the z er o stuff er ( normal oper ation)
1 = disabl e the zero stuffer
Bit 0 : T ransmit CRC Def eat (TCRCD) . A two-by te CRC code is autom atically appended t o the outbound
m essage. This bit can be used to disable the CRC function.
0 = enable CRC generat ion (normal operation)
1 = disabl e CRC gener ation
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 200 of 305
Register Name:
THBSE
Register Desc r iptio n:
Transmit HDLC-64 Bit Suppress
Register Addr ess :
111h + (200h x (n-1) ) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TBSE8
TBSE7
TBSE6
TBSE5
TBSE4
TBSE3
TBSE2
TBSE1
Default
0
0
0
0
0
0
0
0
Bit 7 : T ransmit Bit 8 Supp ress (TBS E 8) . MS B of the channel. Set to one to stop this bi t f r om bei ng used.
Bit 6 : T ransmit Bit 7 Supp ress (TBS E 7) . Set t o one to st op this bit from being used.
Bit 5 : T ransmit Bit 6 Supp ress (TBS E 6) . Set to one to stop t his bit from bei ng used.
Bit 4 : T ransmit Bit 5 Supp ress (TBS E 5) . Set t o one to stop this bit from being used
Bit 3 : T ransmit Bit 4 Supp ress (TBS E 4) . Set t o one to st op this bit from being used
Bit 2 : T ransmit Bit 3 Supp ress (TBS E 3) . Set to one to stop t his bit from bei ng used
Bit 1 : T ransmit Bit 2 Supp ress (TBS E 2) . Set t o one to st op this bit from being used
Bit 0 : Transmit Bit 1 Suppress (TBSE 1) . LSB of the channel. S et t o one to stop t his bi t f r om bei ng used.
Register Name:
THC2
Register Desc r iptio n:
Transmit HDLC-64 Control Regi st er 2
Register Addr ess :
113h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TABT
SBOC
THCEN
THCS4
THCS3
THCS2
THCS1
THCS0
TABT
—
THCEN
THCS4
THCS3
THCS2
THCS1
THCS0
Default
0
0
0
0
0
0
0
0
Bit 7: Tran smit Abort (TABT ). A 0-to-1 transition will cause the FI FO c ontents to be dum ped and one FEh abort to
be sent foll owed by 7Eh or FF h flags/idle unti l a new packet is i nitiated by writing new data i nto the FIFO . Must be
cl ear ed and set again for a subsequent abort to be sent.
Bit 6: Send BOC (SBOC) (T1 Mode Only). Set = 1 to transm it the BOC code placed in bits 0 to 5 of the T1TBOC
register.
Bit 5: Tran smit HDLC-64 Controller En abl e (THCE N)
0 = Transmit HDLC-64 Controller i s not enabled
1 = Transmit HDLC-64 Controll er is enabl ed
Bits 4 to 0: Tran smit HDLC-64 Chann el Select (THCS[4:0]). Determines which DSO channel will carry the HDLC
m essage if enabled. Changes to this val ue ar e acknowledged only upon a tr ansmit HDLC-64 controller reset (THR
at THC1.5).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 201 of 305
Register Name:
E1TSACR
Register Desc r iptio n:
E1 Transmit Sa-Bit Control Regi st er
Register Addr ess :
114h + (200h x (n - 1)) : where n = 1 to 4, for Ports 1 to 8
Bit #
7
6
5
4
3
2
1
0
Name
SiAF
SiNAF
RA
Sa4
Sa5
Sa6
Sa7
Sa8
Default
0
0
0
0
0
0
0
0
Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF)
0 = Do not insert data from the E1TSiAF r egister into the transmit dat a str eam .
1 = Insert data from the E1TSiAF regi ster into the transmit dat a str eam .
Bit 6: International Bit in Non-Align Frame Insert ion Control Bit (SiNAF)
0 = Do not insert data from the E1TSiNAF regi ster into the transmit data str eam .
1 = Insert data from the E1TSiNAF regi ster into the transmit dat a str eam.
Bit 5: Remote Alarm I nsertion Control Bit ( RA)
0 = Do not insert data from the E1TRA register into the transmit data stream.
1 = Insert data from the E1TRA register into the transmi t dat a str eam .
Bit 4: Addit io nal Bit 4 In sert io n Cont rol Bit ( S a4)
0 = Do not insert data fro m the E1TSa4 register into the transmit dat a str eam .
1 = Insert data from the E1TSa4 register into the t r ansmit data stream.
Bit 3: Addit io nal Bit 5 In sert io n Cont rol Bit ( S a5)
0 = Do not insert data from the E1TSa5 register into the t r ansmit data stream.
1 = Insert data from the E1TSa5 register into the t r ansmit data stream.
Bit 2: Additional Bit 6 Insertion Control Bit ( S a6)
0 = Do not insert data from the E1TSa6 register int o the t r ansmit data stream.
1 = Insert data from the E1TSa6 register into the t r ansmit data stream.
Bit 1: Additional Bit 7 In sert io n Cont rol Bit ( S a7)
0 = Do not insert data from the E1TSa7 register into the t r ansmit data stream.
1 = Insert data from the E1TSa7 register into the t r ansmit data stream.
Bit 0: Addit io nal Bit 8 In sert io n Cont rol Bit ( S a8)
0 = Do not insert data from the E1TSa8 register into the t r ansmit data stream.
1 = Insert data from the E1TSa8 register into the transmit data stream.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 202 of 305
Register Name:
SSIE1, SSIE2, SSIE3, SSIE4
Register Description:
Software-Signaling Insertion Enable Registers 1 to 4
Register A ddr es s:
118h, 119h, 11Ah, 11Bh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
SSIE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
SSIE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
SSIE3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
SSIE4 (E1
Mode Only)
Bits 7 to 0: Sof tware-Signaling Insertion Enabl e for Chan nels 1 to 32 ( CH[ 1: 32] ). These bit s determine wh ich
channel s are t o have si gnaling i nsert ed f orm t he Transmit Si gnaling register s.
0 = Do not source signaling data fr om the TS regi ster s for this channel.
1 = Source signaling data from the TS registers for this channel.
Register Name:
TIDR1 to TIDR32
Register Desc r iptio n:
Transmit Idle Code Definit io n Regist ers 1 t o 32
Register Addr ess :
120h to 13F h + (200h x (n - 1)) : wh ere n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Per-Chann el I dl e Cod e Bits ( C[ 7: 0] ). C0 is the LSB of the code (this bit is transmi tt ed last) . Address
120h is for c hannel 1, address 13Fh is for channel 32. TIDR25:TIDR32 are E1 mode.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 203 of 305
Register Name:
TS1 t o TS16
Register Desc r iptio n:
Transmit-Signaling Regi st ers
Register Addr ess :
140h to 14F h + (200h x (n - 1)) : wh ere n = 1 to 4
T1 Mode:
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH1-A
CH1-B
CH1-C
CH1-D
CH13-A
CH13-B
CH13-C
CH13-D
TS1
CH2-A
CH2-B
CH2-C
CH2-D
CH14-A
CH14-B
CH14-C
CH14-D
TS2
CH3-A
CH3-B
CH3-C
CH3-D
CH15-A
CH15-B
CH15-C
CH15-D
TS3
CH4-A
CH4-B
CH4-C
CH4-D
CH16-A
CH16-B
CH16-C
CH16-D
TS4
CH5-A
CH5-B
CH5-C
CH5-D
CH17-A
CH17-B
CH17-C
CH17-D
TS5
CH6-A
CH6-B
CH6-C
CH6-D
CH18-A
CH18-B
CH18-C
CH18-D
TS6
CH7-A
CH7-B
CH7-C
CH7-D
CH19-A
CH19-B
CH19-C
CH19-D
TS7
CH8-A
CH8-B
CH8-C
CH8-D
CH20-A
CH20-B
CH20-C
CH20-D
TS8
CH9-A
CH9-B
CH9-C
CH9-D
CH21-A
CH21-B
CH21-C
CH21-D
TS9
CH10-A
CH10-B
CH10-C
CH10-D
CH22-A
CH22-B
CH22-C
CH22-D
TS10
CH11-A
CH11-B
CH11-C
CH11-D
CH23-A
CH23-B
CH23-C
CH23-D
TS11
CH12-A
CH12-B
CH12-C
CH12-D
CH24-A
CH24-B
CH24-C
CH24-D
TS12
Note: In D4 framing mode, the C and D bits are not used.
E1 Mode:
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
0
X
Y
X
X
TS1
CH1-A
CH1-B
CH1-C
CH1-D
CH16-A
CH16-B
CH16-C
CH16-D
TS2
CH2-A
CH2-B
CH2-C
CH2-D
CH17-A
CH17-B
CH17-C
CH17-D
TS3
CH3-A
CH3-B
CH3-C
CH3-D
CH18-A
CH18-B
CH18-C
CH18-D
TS4
CH4-A
CH4-B
CH4-C
CH4-D
CH19-A
CH19-B
CH19-C
CH19-D
TS5
CH5-A
CH5-B
CH5-C
CH5-D
CH20-A
CH20-B
CH20-C
CH20-D
TS6
CH6-A
CH6-B
CH6-C
CH6-D
CH21-A
CH21-B
CH21-C
CH21-D
TS7
CH7-A
CH7-B
CH7-C
CH7-D
CH22-A
CH22-B
CH22-C
CH22-D
TS8
CH8-A
CH8-B
CH8-C
CH8-D
CH23-A
CH23-B
CH23-C
CH23-D
TS9
CH9-A
CH9-B
CH9-C
CH9-D
CH24-A
CH24-B
CH24-C
CH24-D
TS10
CH10-A
CH10-B
CH10-C
CH10-D
CH25-A
CH25-B
CH25-C
CH25-D
TS11
CH11-A
CH11-B
CH11-C
CH11-D
CH26-A
CH26-B
CH26-C
CH26-D
TS12
CH12-A
CH12-B
CH12-C
CH12-D
CH27-A
CH27-B
CH27-C
CH27-D
TS13
CH13-A
CH13-B
CH13-C
CH13-D
CH28-A
CH28-B
CH28-C
CH28-D
TS14
CH14-A
CH14-B
CH14-C
CH14-D
CH29-A
CH29-B
CH29-C
CH29-D
TS15
CH15-A
CH15-B
CH15-C
CH15-D
CH30-A
CH30-B
CH30-C
CH30-D
TS16
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 204 of 305
Register Name:
TC ICE1, TC ICE2, TCICE3, TCICE4
Register Desc r iptio n:
Transmit Channel Idle Code Enable Registers 1 to 4
Register Addr ess :
150h, 151h, 152h, 153h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCICE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCICE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCICE3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
TCICE 4 (E1
Mode Only)
The T r ansmit Channel Idle Code Enabl e Registers (TCICE1–4) ar e used to determi ne whic h of t he 24 T1 channels
(or 32 E1 c hannels) from the backplane shoul d be ov erwrit ten with the code plac ed in the Transm it Idle Code
Definition Regist er (TIDR1–32).
Bits 7 to 0: Tran smit Channels 1 to 32 Cod e Inserti on Con t rol Bits ( CH[ 1: 32] )
0 = Do not insert data from the Idl e Code Ar r ay i nto t he transmit data stream.
1 = Insert data from the Idl e Code A r r ay i nto t he transmit data stream.
Register Name:
TJB E1, TJBE2, TJBE3, TJBE4
Register Desc r iptio n:
Transmit Jammed Bit Eight Stuf fing Regi st ers 1 to 4
Register Addr ess :
104h, 105h, 106h, 107h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TJBE1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TJBE2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TJBE3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TJBE4
The T r ansmit J ammed Bit Eight Stuff ing Register s (T JBE1–4) select whic h of the 24 T1 channels (or 32 E1
Channels) t o insert jamm ed bit ei ght stuf fing. These registers are enabled by TCR4.TJBEN.
Bits 7 to 0: Tran smit Channels 1 to 32 Jammed Bi t Eight Stu f fing Contro l Bi t s (CH[1:32] )
0 = Do not affec t dat a in this channel.
1 = Replac e the channel with TJ B ES if the c hannel is all z er os.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 205 of 305
Register Name:
TDD S1, TDDS2, TDDS3
Register Desc r iptio n:
Transmit DDS Zero Cod e Regi st ers 1 to 3
Register Addr ess :
108h, 109h, 10Ah + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TDDS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TDDS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TDDS3
The T r ansmit DDS Zer o Code Registers (TDDS 1–3) selec t which of the 24 T1 channel s to insert DDS z er o code
stuff ing. These regi ster s are enabled by T1.TCR2.TDDSEN.
Bits 7 to 0: Tran smit Channels 1 to 24 DDS Zero Code Con t rol Bits ( CH[ 1: 32] )
0 = Do not affec t dat a in this channel.
1 = Replac e the channel with DDS Zero Code stuf fing if the channel is all zeros.
Register Name:
T1TFDL
Register Desc r iptio n:
Tra nsmit FD L Register
Register Addr ess :
162h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
Default
0
0
0
0
0
0
0
0
Note: Also used to insert Fs framing pattern in D4 framing mode.
The T r ansmit FDL Register (T1TFDL) c ontai ns the Facil ity Data Li nk (FDL) information that is to be insert ed on a
byte basi s i nto the outgoing T1 dat a str eam . T he LSB is tr ansmitted first. In D4 m ode, onl y the lower six bits are
used.
Bit 7: Tran smit FDL Bit 7 (TFDL 7) . MSB of the Transmit FDL Code.
Bit 6: Transmit FDL Bit 6 (TFDL6)
Bit 5: Tran smit FDL Bit 5 (TFDL 5)
Bit 4: Tran smit FDL Bit 4 (TFDL 4)
Bit 3: Tran smit FDL Bit 3 (TFDL 3)
Bit 2: Tran smit FDL Bit 2 (TFDL 2)
Bit 1: Tran smit FDL Bit 1 (TFDL 1)
Bit 0: Tran smit FDL Bit 0 (TFDL 0) . LSB of the T r ansmit FDL Code.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 206 of 305
Register Name:
T1TBOC
Register Desc r iptio n:
Transmit BOC Register
Register Addr ess :
163h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
TBOC5
TBOC4
TBOC3
TBOC2
TBOC1
TBOC0
Default
0
0
0
0
0
0
0
0
Bit 5: Tran smit BOC Bit 5 (T BOC5). MS B of the transm it BOC code.
Bit 4: Tran smit BOC Bit 4 (T BOC4)
Bit 3: Tran smit BOC Bit 3 (T BOC3)
Bit 2: Tran smit BOC Bit 2 (T BOC2)
Bit 1: Tran smit BOC Bit 1 (T BOC1)
Bit 0: Tran smit BOC Bit 0 (T BOC0). LSB of t he transmit BOC code.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 207 of 305
Register Name:
T1 TSLC1, T1 TSLC2, T1TSLC3 ( T1 Mode)
Register Desc r iptio n:
Tra nsmit SLC-96 Data Link Regist ers 1 to 3
Register Addr ess :
164h, 165h, 166h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
C8
C7
C6
C5
C4
C3
C2
C1
T1TSLC1
M2
M1
S=0
S=1
S=0
C11
C10
C9
T1TSLC2
S=1
S4
S3
S2
S1
A2
A1
M3
T1TSLC3
Note: See E1TAF, E1TNAF, and E1TSiAF for E1 Mode.
Register Name:
E1TAF (E1 Mode)
Register Desc r iptio n:
Transmit Align Frame Regist er
Register Addr ess :
164h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
Si
0
0
1
1
0
1
1
Default
0
0
0
1
1
0
1
1
Bit 7: International Bit (Si)
Bit 6: Frame Align ment Signal Bit (0)
Bit 5: Frame Align ment Signal Bit (0)
Bit 4: Frame Align ment Signal Bit (1)
Bit 3: Frame Align ment Signal Bit (1)
Bit 2: Frame Align ment Signal Bit (0)
Bit 1: Frame Align ment Signal Bit (1)
Bit 0: Frame Align ment Signal Bit (1)
Register Name:
E1TNAF (E 1 Mode)
Register Desc r iptio n:
Transmit Non-Ali gn Frame Register
Register Addr ess :
165h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
Default
0
1
0
0
0
0
0
0
Bit 7: International Bit (Si)
Bit 6: Frame Non-Alignment Signal Bit (1)
Bit 5: Remote Alarm (Used to Transmit the Alarm) (A)
Bit 4: Addit io nal Bit 4 (Sa4)
Bit 3: Addit io nal Bit 5 (Sa5)
Bit 2: Addit io nal Bit 6 (Sa6)
Bit 1: Addit io nal Bit 7 (Sa7)
Bit 0: Addit io nal Bit 8 (Sa8)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 208 of 305
Register Name:
E1TSiAF (E1 Mode)
Register Desc r iptio n:
Transmit Si Bits of the Align Frame Regist er
Register Addr ess :
166h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSiF14
TSiF12
TSiF10
TSiF8
TSiF6
TSiF4
TSiF2
TSiF0
Default
0
0
0
0
0
0
0
0
Bit 7: Si Bit of Frame 14 (TSiF 14)
Bit 6: Si Bit of Frame 12 (TSiF 12)
Bit 5: Si Bit of Frame 10 (TSiF 10)
Bit 4: Si Bit of Frame 8 (TSiF 8)
Bit 3: Si Bit of Frame 6 (TSiF 6)
Bit 2: Si Bit of Frame 4 (TSiF 4)
Bit 1: Si Bit of Frame 2 (TSiF 2)
Bit 0: Si Bit of Frame 0 (TSiF0)
Register Name:
E1TSiNAF (E1 Mode Only)
Register Desc r iptio n:
Tra nsmit Si Bits of the Non-Align F rame Regi st er
Register Addr ess :
167h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSiF15
TSiF13
TSiF11
TSiF9
TSiF7
TSiF5
TSiF3
TSiF1
Default
0
0
0
0
0
0
0
0
Bit 7: Si Bit of Frame 15 (TSiF 15)
Bit 6: Si Bit of Frame 13 (TSiF 13)
Bit 5: Si Bit of Frame 11 (TSiF 11)
Bit 4: Si Bit of Frame 9 (TSiF 9)
Bit 3: Si Bit of Frame 7 (TSiF 7)
Bit 2: Si Bit of Frame 5 (TSiF 5)
Bit 1: Si Bit of Frame 3 (TSiF 3)
Bit 0: Si Bit of Frame 1 (TSiF 1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 209 of 305
Register Name:
E1TRA (E1 Mod e Only)
Register Desc r iptio n:
Transmit Remote Alarm Regi st er
Register Addr ess :
168h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TRAF15
TRAF13
TRAF11
TRAF9
TRAF7
TRAF5
TRAF3
TRAF1
Default
0
0
0
0
0
0
0
0
Bit 7: Remote Alarm Bi t of Frame 15 (TRAF15)
Bit 6: Remote Alarm Bi t of Frame 13 (TRAF13)
Bit 5: Remote Alarm Bi t of Frame 11 (TRAF11)
Bit 4: Remote Alarm Bi t of Frame 9 (TRAF9)
Bit 3: Remote Alarm Bi t of Frame 7 (TRAF7)
Bit 2: Remote Alarm Bi t of Frame 5 (TRAF5)
Bit 1: Remote Alarm Bi t of Frame 3 (TRAF3)
Bit 0: Remote Alarm Bi t of Frame 1 (TRAF1)
Register Name:
E1TSa4 (E1 Mode Only)
Register Desc r iptio n:
Transmit Sa4 Bits Regist er
Register Addr ess :
169h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSa4F15
TSa4F13
TSa4F11
TSa4F9
TSa4F7
TSa4F5
TSa4F3
TSa4F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a4 Bit of Frame 15 (TS a4F15)
Bit 6: S a4 Bit of Frame 13 (TS a4F13)
Bit 5: S a4 Bit of Frame 11 (TS a4F11)
Bit 4: S a4 Bit of Frame 9 (TSa4F9)
Bit 3: S a4 Bit of Frame 7 (TSa4F7)
Bit 2: S a4 Bit of Frame 5 (TSa4F5)
Bit 1: S a4 Bit of Frame 3 (TSa4F3)
Bit 0: S a4 Bit of Frame 1 (TSa4F1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 210 of 305
Register Name:
E1TSa5 (E1 Mode Only)
Register Description:
Transmit Sa5 Bits Regist er
Register Addr ess :
16Ah + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSa5F15
TSa5F13
TSa5F11
TSa5F9
TSa5F7
TSa5F5
TSa5F3
TSa5F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a5 Bit of Frame 15 (TS a5F15)
Bit 6: S a5 Bit of Frame 13 (TS a5F13)
Bit 5: S a5 Bit of Frame 11 (TS a5F11)
Bit 4: S a5 Bit of Frame 9 (TSa5F9)
Bit 3: S a5 Bit of Frame 7 (TSa5F7)
Bit 2: S a5 Bit of Frame 5 (TSa5F5)
Bit 1: S a5 Bit of Frame 3 (TSa5F3)
Bit 0: S a5 Bit of Frame 1 (TSa5F1)
Register Name:
E1TSa6 (E1 Mode Only)
Register Desc r iptio n:
Transmit Sa6 Bits Regist er
Register Addr ess :
16Bh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSa6F15
TSa6F13
TSa6F11
TSa6F9
TSa6F7
TSa6F5
TSa6F3
TSa6F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a6 Bit of Frame 15 (TS a6F15)
Bit 6: S a6 Bit of Frame 13 (TS a6F13)
Bit 5: S a6 Bit of Frame 11 (TS a6F11)
Bit 4: S a6 Bit of Frame 9 (TSa6F9)
Bit 3: S a6 Bit of Frame 7 (TSa6F7)
Bit 2: S a6 Bit of Frame 5 (TSa6F5)
Bit 1: S a6 Bit of Frame 3 (TSa6F3)
Bit 0: S a6 Bit of Frame 1 (TSa6F1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 211 of 305
Register Name:
E1TSa7 (E1 Mode Only)
Register Desc r iptio n:
Transmit Sa7 Bits Regist er
Register Addr ess :
16Ch + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSa7F15
TSa7F13
TSa7F11
TSa7F9
TSa7F7
TSa7F5
TSa7F3
TSa7F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a7 Bit of Frame 15 (TS a4F15)
Bit 6: S a7 Bit of Frame 13 (TS a7F13)
Bit 5: S a7 Bit of Frame 11 (TS a7F11)
Bit 4: S a7 Bit of Frame 9 (TSa7F9)
Bit 3: S a7 Bit of Frame 7 (TSa7F7)
Bit 2: S a7 Bit of Frame 5 (TSa7F5)
Bit 1: S a7 Bit of Frame 3 (TSa7F3)
Bit 0: S a7 Bit of Frame 1 (TSa7F1)
Register Name:
E1TSa8 (E1 Mode Only)
Register Desc r iptio n:
Transmit Sa8 Bits Regist er
Register Addr ess :
16Dh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TSa8F15
TSa8F13
TSa8F11
TSa8F9
TSa8F7
TSa8F5
TSa8F3
TSa8F1
Default
0
0
0
0
0
0
0
0
Bit 7: S a8 Bit of Frame 15 (TS a8F15)
Bit 6: S a8 Bit of Frame 13 (TS a8F13)
Bit 5: S a8 Bit of Frame 11 (TS a8F11)
Bit 4: S a8 Bit of Frame 9 (TSa8F9)
Bit 3: S a8 Bit of Frame 7 (TSa8F7)
Bit 2: S a8 Bit of Frame 5 (TSa8F5)
Bit 1: S a8 Bit of Frame 3 (TSa8F3)
Bit 0: S a8 Bit of Frame 1 (TSa8F1)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 212 of 305
Register Name:
TMMR
Register Desc r iptio n:
Transmit Master Mode Regist er
Register Addr ess :
180h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
FRM_EN
INIT_DONE
—
—
—
—
SFTRST
T1/E1
Default
0
0
0
0
0
0
0
0
Bit 7: Framer Enable (FRM_EN). Thi s bit m ust be set to the desired state before writi ng INIT_DONE .
0 = Fram er di sabl ed—held in low -power state.
1 = Fram er enabled—all features acti ve .
Bit 6: Initialization Done (INIT _DONE). The user m ust set thi s bit once he has writ ten t he configur ati on regi ster s.
The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the
DS26514 wil l check the FRM_E N bit and, if enabled, will begi n oper ation based on the initial c onfiguration.
Bit 1: Sof t Reset (SFTRST). Level sensitive “ soft” rese t. Should be t ak en high, t hen low to reset the transceiver .
0 = Normal operat ion.
1 = Reset the transceiver.
Note: This reset does not cl ear the registers.
Bit 0: Transmi tter T1/ E1 Mod e S elect (T 1/E1). Set s operati ng m ode f or tr ansmitter only! T hi s bi t must be writ ten
with t he desi r ed v alue prior to setti ng INIT_DONE.
0 = T1 operation.
1 = E1 operation.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 213 of 305
Register Name:
TCR1 (T 1 Mode)
Register Desc r iptio n:
Transmit Cont rol Regi st er 1
Register Addr ess :
181h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TJC
TFPT
TCPT
TSSE
GB7S
TB8ZS
TAIS
TRAI
Default
0
0
0
0
0
0
0
0
Note: See TCR1 for E1 Mode.
Bit 7: Tran smit Japanese CRC-6 Ena ble (TJC)
0 = Use ANSI/ AT& T: IT U-T CRC-6 calc ulation (normal operat ion).
1 = Use Japanese standar d J T –G 704 CRC-6 calculation .
Bit 6: Tran smit F-Bit P a s s Thr ou gh (TFPT)
0 = F bit s sourced i nternal ly.
1 = F bit s sampled at T SERn (T1.TCR2.7 TFDLS must be programmed to 0).
Bit 5: Tran smit CRC Pass Th rough (TCPT)
0 = Source CRC-6 bits i nternally.
1 = CRC-6 bits sampled at T SERn during F-bit time.
Bit 4: Transmit Software Signaling Enable (TSSE). This function is enabl ed by TB 7ZS (T1.TCR2.0).
0 = Do not source signaling data fr om the TS1–16 register s regardless of t he SSIE1–4 register s. The
SSIE1–4 register s sti ll define whic h c hannels are to have B7 stuffing performed.
1 = Source si gnaling data as enabled by the SSIE1–4 registers.
Bit 3: Global Bit 7 Stuffing (GB7S). Thi s func tion i s enabl ed by TB7ZS (T1.TCR2.0).
0 = All ow the SSIE1–4 registers to determine whi c h c hannels cont aining all z er os are t o be bit 7 stuffed.
1 = Forc e bit 7 stuffing i n all z er o byte c hannels of that port , regardl ess of how the SSIE1–4 registers are
programmed.
Bit 2: Tran smit B8ZS Enable (TB8ZS)
0 = B8ZS di sabl ed.
1 = B8ZS enabl ed.
Bit 1: Tran smit Alarm Indication Signal (T AIS)
0 = Transmit data normally.
1 = Transmit an unf r am ed all-ones code at TT IPn and TRING n.
Bit 0: Tran smit Remote Alarm Indication (TRAI)
0 = Do not transm it remote alarm.
1 = Transmit rem ote al arm.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 214 of 305
Register Name:
TCR1 (E1 Mode)
Register Desc r iptio n:
Transmit Cont rol Regi st er 1
Register Addr ess :
181h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TTPT
T16S
TG802
TSiS
TSA1
THDB3
TAIS
TCRC4
Default
0
0
0
0
0
0
0
0
Note: See TCR1 for T1 Mode.
Bit 7: Transmit Time Slot 0 Pass Through (TTPT)
0 = FAS bits/S a bits/Remote Alarm sourced i nternally from t he E1TAF and E1TNAF registers.
1 = FAS bits/S a bits/Remote Alarm sourced from TSERn.
Bit 6: Tran smit Time Slot 16 Data Select (T16S ). S ee Secti on 9.9.4 on software signaling.
0 = Time sl ot 16 det ermined by the SSIE1–4 and THSCS1–4 registers.
1 = Source time slot 16 from TS1–16 register s.
Bit 5: Tran smit G.802 E nable (TG802) . See Section 11.4.
0 = Do not f orce T CHB LK n high duri ng bit 1 of time slot 26.
1 = Forc e TCHBLK n high dur ing bi t 1 of tim e slot 26.
Bit 4: Tran smit Int ernational Bit S elect (TS iS)
0 = Sample Si bits at TSE Rn pin.
1 = Source Si bits f rom E1TAF and E1TNAF registers (in t his m ode, TCR1. 7 must be set to 0).
Bit 3: Transmit Signaling All Ones (TSA1)
0 = Normal operat ion.
1 = Forc e time sl ot 16 in every fram e to all ones.
Bit 2: Tran smit HDB3 Enab le (T HDB3)
0 = HDB 3 disabl ed.
1 = HDB 3 enabled.
Bit 1: Tran smit AIS (TAIS )
0 = Transmit data normally.
1 = Transmit an unf r am ed all-ones code at TT IPn and TRING n.
Bit 0: Tran smit CRC-4 Enab le (T CRC4)
0 = CRC-4 disabl ed.
1 = CRC-4 enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 215 of 305
Register Name:
T1 .TCR2 (T1 Mode)
Register Desc r iptio n:
Transmit Cont rol Regi st er 2
Register Addr ess :
182h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TFDLS
TSLC96
TDDSEN
FBCT2
FBCT1
TRAIS
—
TB7ZS
Default
0
0
0
0
0
0
0
0
Note: See E1.TCR2 for E1 Mode.
Bit 7: TF DL Regist er S elect (TF DLS)
0 = Source FDL or Fs bits fr om the internal TFDL register or the SLC-96 data formatter (T1.TCR2.6).
1 = Source FDL or Fs bits fr om the internal HDLC-64 controller.
Bit 6: Tran smit SLC-96 (TSLC96). Set this bit to a one in SLC-96 fr ami ng applicati ons. M ust be set to source the
SLC-96 al ignment pattern and dat a f r om the T1TSLC1–3 regi ster s. S ee S ec tion 9.9.4.3 for det ails.
0 = SLC-96 i nsert ion disabled.
1 = SLC-96 i nsert ion enabled.
Bit 5: Transmit DDS Zero Su ppression Enable (TDDSEN)
0 = No DDS stuffing.
1 = DDS stuffing enabled. For c e zero code 10011000 in all zero byte c hannels based on the channel
select r egisters TDDS1–3.
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit hi gh enables the corruption of one Ft (D4 fr ami ng m ode)
or FP S (ESF frami ng m ode) bit in every 128 Ft or FPS bit s as long as the bit r em ains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-hi gh transiti on of this bit causes the nex t thr ee c onsecut ive Ft
(D4 fr ami ng m ode) or FPS (E SF frami ng m ode) bits to be corrupted c ausi ng the remot e end to experi enc e a loss of
synchronization.
Bit 2: Tran smit RAI Sel ect (TRAIS)
0 = Transmit RAI is T1.
D4—Zeros i n bit 2 of all c hannels.
ESF—00FF pattern in the FDL.
1 = Transmit RAI is J1.
D4—A one i n the S-bit position of fr am e 12.
ESF—All ones in FDL.
Note: This bit only selects the ty pe of rem ote al arm t o send. To enable tr ansmission of r em ote al arm, set
TCR1.TRAI.
Bit 0: Transmit-Side Bit 7 Zero S uppression Enable (TB7ZS)
0 = No stuff ing occur s.
1 = Forc e bit 7 t o a one as determined by the GB7S bit at TCR1.3.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 216 of 305
Register Name:
E1.TCR2 (E1 Mode)
Register Desc r iptio n:
Transmit Cont rol Regi st er 2
Register Addr ess :
182h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
AEBE
AAIS
ARA
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Note: See T1.TCR2 for T1 Mode.
Bit 7: Automatic E-Bit Enable (AEBE)
0 = E-bits not automatically set in the tr ansmit direction.
1 = E-bits autom atically set i n the transm it di r ec tion.
Bit 6: Automatic AIS Generat io n (AAIS)
0 = Disabl ed
1 = Enabled
Bit 5: Automatic Remote Alarm Generatio n (ARA)
0 = Disabl ed
1 = Enabled
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 217 of 305
Register Name:
TCR3
Register Desc r iptio n:
Transmit Cont rol Regi st er 3
Register Addr ess :
183h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
TCSS1
TCSS0
MFRS
TFM
IBPV
TLOOP
—
—
TCSS1
TCSS0
MFRS
—
IBPV
CRC4
Default
0
0
0
0
0
0
0
0
Bits 5 and 4 : Transmi t Clock Sou rce S elect 1 and 0 (TCS S[1:0] )
TCSS1
TCSS0
Tra nsmit Clock Source
0
0
The T CLK n pin is al ways the source of transmit clock.
0 1
Switc h to the cl oc k pr esent at RCLKn when the signal at the TCLKn pin fails to transiti on aft er
1 channel time.
1
0
Reserved.
1
1
Use the signal pr esent at RCLKn as the tr ansmit cl oc k . The TCLK n pin is i gnor ed (loop time).
Bit 3: Multiframe Referen ce S elect (MFRS ) . This bit sel ec ts the source for the transmit formatter multiframe
boundary.
0 = Normal Oper ation. Transmit multiframe boundary is determined by 'l ine-side' counters referenced to
TSY NCn when TSY NCn is an i nput. Free-running when T S Y NCn is an output.
1 = Pass -Forward O per ation. Tx multif r am e boundary det ermined by 'system-si de' c ounters referenced t o
TSS Y NCIO n (i nput mode3) , whi c h is then passed forward to t he line si de cl oc k dom ain. T his mode can
only be used when the tr ansmit el astic stor e is enabl ed with a synchronous backpl ane ( i.e., no fram e sli ps
allowed). This mode must be used to allow Tx hardware signali ng insert ion whi le the Tx elastic stor e is
enabled.
Bit 2: Tran smit Frame Mode S elect (TF M ) ( T1 Mode Only )
0 = ESF framing mode.
1 = D4 framing mode.
Bit 1: In sert BPV (IBPV ) . A 0 -to-1 transit ion on thi s bi t will cause a single Bi polar Violation (BPV) to be insert ed
into the transmit dat a str eam . Once t his bi t has been toggled from a 0 to a 1, the device waits f or the nex t
occurr enc e of three consecutive ones to insert the BP V. Thi s bit m ust be cl ear ed and set again for a subseque nt
error to be i nsert ed.
Bit 0 (T1 Mode): T ransmit Loop Code Enable (TLOOP). See Section 9.9.15 for detail s.
0 = Transmit data normally.
1 = Replac e normal transmitt ed data with r epeating code as defi ned in registers T1TCD1 and T1TCD2.
Bit 0 ( E 1 Mode): CRC-4 Recalculate (CRC4R)
0 = Transmit CRC-4 generati on and insert ion operat es in normal m ode.
1 = Transmit CRC-4 generati on oper ates accordi ng to G.706 Interm ediate Path Recal c ulation m ethod.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 218 of 305
Register Name:
TIOCR
Register Desc r iptio n:
Tra ns m it I/O C on f ig ur a t i on Regist er
Register Addr ess :
184h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TCLKINV
TSYNCINV
TSSYNCINV
TSCLKM
TSSM
TSIO
TSDW
TSM
TCLKINV
TSYNCINV
TSSYNCINV
TSCLKM
TSSM
TSIO
—
TSM
Default
0
0
0
0
0
0
0
0
Bit 7: TCLK n Invert (TCLKINV)
0 = No inv er si on.
1 = Invert.
Bit 6: TSY NCn Invert (TS Y NCINV)
0 = No inv er si on.
1 = Invert.
Bit 5: TSSYNCIOn (Input Mode Only) Invert (TSSYNCINV)
0 = No inv er si on.
1 = Invert.
Bit 4: TSYSCLKn Mode Select (TSCLKM)
0 = If TSYSCLK n is 1.544M Hz .
1 = If TSYSCLK n is 2.048/4.096/8.192/16. 384M Hz or IBO enabled (see Sect ion 9.8.2 for details on IBO
function).
Bit 3: TSSYNCIOn Mode Select (TSSM). Selects fra m e or multifra me mode for the TSSYNC IOn p in.
0 = Frame mode.
1 = Multiframe mode .
Bit 2: TSYNCn I/O Select (TSIO)
0 = TSYNCn is an input.
1 = TSY NCn is an output.
Bit 1: TSYNCn Double-Wide (TSDW) (T 1 Mode Only) (Note: This bi t must be set to zero when TSM = 1 or when
TSI O = 0 .)
0 = Do not pulse doubl e-wide in signaling frames.
1 = Do pulse doubl e-wide in signali ng fram es.
Bit 0: TSYNCn Mode Select (TSM). Selects frame or multifra me mode fo r the TSYNCn pin.
0 = Frame mode.
1 = Multiframe mode .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 219 of 305
Register Name:
TESCR
Register Desc r iptio n:
Tra nsmit Elasti c Sto re Contro l Regist er
Register Addr ess :
185h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TDATFMT
TGCLKEN
—
TSZS
TESALGN
TESR
TESMDM
TESE
Default
0
0
0
0
0
0
0
0
Note: Bits 6 and 7 are used for fractional backplane support. See Section 9.8.5.
Bit 7: Tran smit Channel Data Format (TDAT FMT)
0 = 64k bps (dat a c ontained in all 8 bits).
1 = 56k bps (dat a c ontained in 7 out of the 8 bit s).
Bit 6: Transmit Gapped Clock Enable (TGCLKEN)
0 = TCHCLK functions normally.
1 = Enabl e gapped bit cl oc k output on TCHCLKn.
Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the mi nimum distance all owed between the elastic
store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1
conversion applications.
0 = Forc e a sli p at 9 bytes or l ess of separation (used for clustered bl ank channels).
1 = Forc e a sli p at 2 bytes or l ess of separation (used for di str ibuted blank channel s).
Bit 3: Transmi t Elast ic Store Ali gn (TESALGN). Setting this bit from a zer o to a one will f orce t he transmit elastic
store’ s wri te/read pointers to a mi nimum separat ion of half a fram e. No action wi ll be tak en if t he pointer sepa r ation
is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be
ex ecuted and t he data will be disrupt ed. Sho ul d be tog gl ed af ter TSYSCLKn has b een appl i ed and is stabl e. Must
be cl ear ed and set again for a subseque nt align.
Bit 2: Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one will force the read pointer into
the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command
should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will
move back to opposite frames. Should be toggled after TSYSCLKn has been applied and is stable. Do not leave
this bit set high.
Bit 1: Tran smit Elastic Store Minimum Delay Mode (TESMD M)
0 = El astic stor es operat e at full two-fram e depth.
1 = El astic stor es operat e at 32-bit depth.
Bit 0: Tran smit Elastic Store Enab le (TESE )
0 = El astic stor e is bypassed.
1 = El astic stor e is enabl ed.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 220 of 305
Register Name:
TCR4
Register Desc r iption:
Transmit Cont rol Regi st er 4
Register Addr ess :
186h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
uALAW
BINV1
BINV0
TJBEN
TRAIM
TAISM
TC1
TC0
uALAW
BINV1
BINV0
TJBEN
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 7: u-Law or A -Law Digital Milliwatt Code Select (uALAW)
0 = u-law code i s i nsert ed based on TDMWEx regi ster s .
1 = A-l aw code i s inserted based on TDMWEx registers.
Bits 6 and 5: Transmit Bit In version (BINV[1: 0] )
00 = No inv er si on.
01 = Invert framing.
10 = Invert si gnaling.
11 = Invert payl oad.
Bit 4: Tran smit Jammed Bit 8 Suppression Enabl e (TJBEN)
0 = No stuff ing enabl ed.
1 = Jammed Bi t 8 Suppr ession enabled. This for c es bi t 8 to a one as determined by TJBE1–4 register s
and bit 7 to a one in T1 signaling frames.
Bits 3: Transmit RAI Mode (TRAIM) (T1 Mod e Only) . Det ermines the pattern sent when TRAI (TCR1.0) is
activated i n ESF frame mode only .
0 = Transmit norm al RA I when TCR1.RAI = 1
1 = If T1 ESF mode, transmit RAI-CI (T1.403) when TCR1.RAI = 1
Bits 2 : Transmit AIS Mode (TAISM) (T1 Mode Only). Determines the patt er n sent when TAIS (TCR1.1 ) is
activated.
0 = Transmit norm al A IS ( unframed all ones) upon activat ion wi th TCR1.1.
1 = Transmit AIS-CI (T1.403) upon activation with TCR1.1.
Bits 1 and 0 : Transmi t Code L ength Defi ni t io n Bi t s (T C[ 1: 0] ) (T1 Mode Only)
TC1
TC0
Len gth Selected
0
0
5 bits
0
1
6 bits : 3 bits
1
0
7 bits
1
1
16 bits : 8 bits : 4 bits : 2 bits : 1 bit
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 221 of 305
Register Name:
THFC
Register Desc r iptio n:
Transmit HDLC-64 FIF O Cont rol Regi st er
Register Addr ess :
187h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
TFLWM1
TFLWM0
Default
0
0
0
0
0
0
0
0
Bits 1 and 0: Transmit HDLC-64 FIFO Low Watermark S elect (TFLWM[1: 0] )
TFLWM1
TFLWM0
Tra nsmit FIFO Watermark
0
0
4 bytes
0
1
16 bytes
1
0
32 bytes
1
1
48 bytes
Register Name:
TIBOC
Register Desc r iptio n:
Transmit Interleave Bu s Op erat io n Cont rol Regi st er
Register Addr ess :
188h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
IBOSEL
IBOEN
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 4: In t erleave Bus Op erat io n Select (IBOSEL ). This bit sel ec ts channel or frame interleave mode.
0 = Channel Interleave.
1 = Fra me Interleave .
Bit 3: In t erleave Bus Op erat io n Enable (I BOEN)
0 = Int erl eave Bus Oper ation di sabl ed.
1 = Int erl eave Bus Operation enabled.
Register Name:
TDS0SEL
Register Desc r iptio n:
Transmit DS0 Channel Monitor Select Register
Register Addr ess :
189h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
TCM4
TCM3
TCM2
TCM1
TCM0
Default
0
0
0
0
0
0
0
0
Bits 4 to 0: Transmit Channel Monitor Bits (TCM[4:0]). TCM0 is the LSB of a 5-bit channel select that
determ ines which transmit c hannel data will appear in the TDS0M regi ster . Channels 1 through 32 ar e represented
by a 5-bit B CD code fr om 0 to 31. TCM[ 0:4] = all 0s selects channel 1, TCM[ 0:4] = 11111 selec ts channel 32.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 222 of 305
Register Name:
TXPC
Register Desc r iptio n:
Transmit Expansion Port Contro l Reg ister
Register Addr ess :
18Ah + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
THMS
THEN
—
—
—
TBPDIR
TBPFUS
TBPEN
Default
0
0
0
0
0
0
0
0
Bit 7 : T ransmit HDLC-256 Mod e S elect (THMS). T1 Mod e
0 = Transmit HDLC-256 assigned to tim esl ots
1 = Transmit HDLC-256 assigned to FDL Bits
Bit 7 : Transmit HDLC-256 Mod e S elect (THMS). E1 Mode
0 = Transmit HDLC-256 assigned to tim esl ots
1 = Transmit HDLC-256 assigned to the Sa Bit s
Bit 6 : T ransmi t HDLC-256 Enabl e (THEN).
0 = Transmit HDLC-256 is not active.
1 = Transmit HDLC-256 is active.
Bit 2: Transmit BERT Port Direct io n Cont rol (TBP DIR)
0 = Normal (line) operation. Tr ansmit BERT por t sources data into the tr ansmit path.
1 = S y stem (back plane) oper ation. Transmit BE RT port sources data into the receive path (RSERn). In this
m ode, t he data from the B ERT is muxed into the rece ive path.
Bit 1: Tran smit BERT Port Framed/Unf ramed Select (T BPFUS ) . T 1 mode only
0 = The DS26514’s tr ansmit BERT will not clock data into the F-bit positi on (fr am ed) .
1 = The DS26514’s tr ansmit BERT will cloc k data i nto the F-bit posi tion (unfr am ed).
Bit 0: Tran smit BERT Port Enable (TBPE N)
0 = Transmit BERT por t is not active.
1 = Transmit BERT por t is active.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 223 of 305
Register Name:
TBPBS
Register Desc r iptio n:
Transmit BERT Port Bi t Suppress Register
Register Addr ess :
18Bh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BPBSE8
BPBSE7
BPBSE6
BPBSE5
BPBSE4
BPBSE3
BPBSE2
BPBSE1
Default
0
0
0
0
0
0
0
0
Bit 7: Transmit Channel Bi t 8 Suppress (BP BS E 8). MSB of t he channel . Set to one t o stop this bit from being
used.
Bit 6: Transmit Channel Bi t 7 Suppress (BP BS E 7). Set to one to stop this bi t f r om bei ng used.
Bit 5: Transmit Channel Bi t 6 Suppress (BP BS E 6). Set to one to stop this bi t f r om bei ng used.
Bit 4: Transmit Channel Bi t 5 Suppress (BP BS E 5). Set to one to stop this bi t f r om bei ng used.
Bit 3: Transmit Channel Bi t 4 Suppress (BP BS E 4). Set to one to stop this bi t f r om bei ng used.
Bit 2: Transmit Channel Bi t 3 Suppress (BP BS E 3). Set to one to stop this bi t f r om bei ng used.
Bit 1: Transmit Channel Bi t 2 Suppress (BP BS E 2). Set to one to stop this bi t f r om bei ng used.
Bit 0: Transmit Channel Bi t 1 Suppress (BP BS E 1). LSB of the channel. Set to one to stop this bi t f r om bei ng
used.
Register Name:
THC S1, THCS2, THCS3, THCS4
Register Desc r iptio n:
Transmit HDLC-256 Channel Select Reg isters
Register Addr ess :
1DCh, 1DDh, 1DEh, 1DEFH
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
THCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
THCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
THCS3
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
THCS4
Setting any of the CH1 through CH32 bits i n the THCS1 through THCS4 registers wil l enabl e the Tr ansmit HDLC
cl oc k for the associat ed c hannel tim e, and allow m apping of t he sel ec ted channel data out of the HDLC-25 6 FIFO.
Mul tipl e, or all channels m ay be selected simul taneously.
Register Name:
THBS
Register Desc r iptio n:
Transmit HDLC-256 Bit Suppress Register
Register Addr ess :
18DH
Bit #
7
6
5
4
3
2
1
0
Name
THBSE
8
THBSE
7
THBSE
6
THBSE
5
THBSE
4
THBSE
3
THBSE2 THBSE1
Default
0
0
0
0
0
0
0
0
Bit 7 : T ransmit Channel Bit 8 Supp ress ( BS E 8). MSB of the channel. S et t o one to stop t his bi t fr om bei ng
used.
Bit 6 : T ransmit Channel Bit 7 Supp ress ( BS E 7). Set to one to stop this bi t f r om bei ng used.
Bit 5 : T ransmit Channel Bit 6 Supp ress (BSE6). Set t o one to stop t his bi t f r om bei ng used.
Bit 4 : T ransmit Channel Bit 5 Supp ress / Sa4 Bit Supp ress ( BS E 5). Set to one to stop this bit from being used
Bit 3 : T ransmit Channel Bit 4 Supp ress / Sa5 Bit Supp ress ( BS E 4). Set to one to stop this bit from being us ed
Bit 2 : T ransmit Channel Bit 3 Supp ress / Sa6 Bit Supp ress ( BS E 3). Set to one to stop this bit from being used
Bit 1 : T ransmit Channel Bit 2 Supp ress/ Sa7 Bit Suppress (BSE2). Set to one t o stop this bit from being used
Bit 0 : Transmit Channel Bit 1 Supp ress / Sa8 Bit Supp ress ( BS E 1). LSB of the channel . Set to one t o stop this
bit fr om bei ng used.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 224 of 305
Register Name:
TSYNCC
Register Desc r iptio n:
Transmit Synchroniz er Con t rol Regi st er
Register Addr ess :
18Eh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
TSEN
SYNCE
RESYNC
—
—
—
—
CRC4
TSEN
SYNCE
RESYNC
Default
0
0
0
0
0
0
0
0
Bit 3: CRC-4 Enabl e ( CRC4) (E1 Mod e Only)
0 = Do not search f or the CRC-4 multiframe word.
1 = Search for the CRC-4 multifr am e word.
Bit 2: Tran smit Synchroniz er Enabl e (TS E N)
0 = Transmit synchronizer disabl ed.
1 = Transmit synchronizer enabled.
Bit 1: S ync Enable ( SYNCE)
0 = Auto r esync enabled.
1 = Auto r esync disabled.
Bit 0: Resynchron ize (RESYNC). When toggled from low to high, a resynchroni z ation of the transmit-side fra mer
is i nitiated. Must be clear ed and set again for a subsequent r esync.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 225 of 305
Register Name:
TLS1
Register Desc r iptio n:
Transmit Latched Statu s Regi st er 1
Register Addr ess :
190h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TESF
TESEM
TSLIP
TSLC96
—
TMF
LOTCC
LOTC
TESF
TESEM
TSLIP
—
TAF
TMF
LOTCC
LOTC
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can cause interrupts.
Bit 7: Tran smit Elastic Store Full Event (TESF). Set when the transmit el astic stor e buffer fills and a frame is
deleted.
Bit 6: Tran smit Elastic Store Empty E vent (TES EM). Set when the t r ansmit elastic store buffer em pties and a
frame is repeated.
Bit 5: Tran smit Elastic Store Slip O ccurren ce E vent (TSLIP ). Set when the tr ansmit elastic store has either
repeated or deleted a fram e.
Bit 4: Tran smit SLC-96 Mul t iframe E vent (TSL C96) (T1 Mode Only) . When enabled by T1.TCR2.6, this bit will
set once per SLC-96 m ultifram e ( 72 frames) to aler t t he host that new data may be wri tt en to the T1TSLC1–3
regi ster s. S ee S ec tion 9.9.4.3 for more informa tion.
Bit 3: Transmit Align Frame Eve nt ( TAF) (E1 Mode Only). Set every 250µs to alert the host that the E1TAF and
E1TNAF registers need to be updated.
Bit 2: Tran smit Mul tif rame E vent (TMF). In T1 mode, this bit is set every 1.5m s on D4 MF boundaries or ev ery
3m s on ESF MF boundaries. In E1 operati on, this but is set every 2ms (regar dless if CRC-4 is enabled) on transmit
m ultif r am e boundar ies. Used to al er t t he host that si gnaling data needs t o be updated.
Bit 1: Loss of Transmit Clo ck Conditi on Clear (LOTCC). S et when the LOTC condition has clear ed ( a cl ock has
been sensed at the TCLK n pin).
Bit 0: Loss of Transmit Clock Condition (LOTC). Set when the TCLK n pin has not transitioned for approximately
3 cl oc k periods. Will force the LOTC pin high if enabled. Thi s bit c an be cl ear ed by the host ev en if the condition is
still present. The LOTC pin will r em ain high while the condition exists, even if the host has cleared the stat us bit. If
enabled by TIM1.0, the INTB pin will transiti on low wh en this bit i s set, and transition high when this bit is cleared (if
no other unm asked interr upt conditions exist) .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 226 of 305
Register Name:
TLS2
Register Desc r iptio n:
Transmit Latched Statu s Regi st er 2 ( HDLC-64)
Register Addr ess :
191h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
TFDLE
TUDR
TMEND
TLWMS
TNFS
—
—
—
—
TUDR
TMEND
TLWMS
TNFS
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create inter rupts.
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL regi ster has shif ted out all 8
bits. Useful if t he user wants to manually use the TFDL register to send messages, instead of usi ng the HDLC or
BOC c ontroller cir c uits.
Bit 3: Transmit FIFO Underrun E vent (TUDR) . Set when t he transmit FIFO em pties out without hav ing seen the
TME ND bit set. A n abort is autom atically sent.
Bit 2: Tran smit Message End Event (TMEND) . Set when the tr ansmit HDLC-64 controller has finished sending a
message.
Bit 1: Tran smit FIFO Below Low Watermark S et Condition (TLWMS). Set when the t r ansmit 64-byte FI FO
em pties beyond the low watermark as defined by the transmit low watermark bits (TLWM), risi ng edge detect of
TLWM.
Bit 0: Transmit FIFO Not Full Set C onditio n (TN FS) . Set when the t r ansmit 64-byte FIFO has at least one em pty
byte av ailabl e for write. Risi ng edge detect of TNF. Indicates change of state from full t o not f ull.
Register Name:
TLS3
Register Desc r iptio n:
Transmit Latched Statu s Regist er 3 (Syn chroni z er)
Register Addr ess :
192h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
LOF
LOFD
Default
0
0
0
0
0
0
0
0
Note: Some bits in this register are latched and can create interrupts.
Bit 1: Lo ss of Frame (LOF). A real-time bit that indicates that the transmit synchr onizer is searchi ng for the sync
patt er n in the i nc omi ng data stream.
Bit 0: Lo ss Of Frame Synch ron ization Detect (LOF D). This latched bit is set when the transmit synchronizer is
searching for the sync pattern in the incoming data stream.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 227 of 305
Register Name:
TIIR
Register Desc r iptio n:
Transmit Interrup t Information Register
Register Addr ess :
19Fh + ( 200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
TLS3
TLS2
TLS1
Default
0
0
0
0
0
0
0
0
The inter r upt i nformation register pr ov ides an i ndication of which stat us register s are generating an interrupt. When
an interrupt occur s, the host c an r ead TIIR to quic kl y identify which of the transm it status registers are causi ng the
interrupt ( s). These are real -time registers i n that the bits will cl ear onc e the appropr iate interrupt has been ser viced
and cl ear ed.
Bit 2: Tran smit Latched Statu s Regi st er 3 Interru pt Statu s (TLS3)
0 = No interr upt pending.
1 = Int er r upt pending.
Bit 1: Transmit Latched Status Regi st er 2 Interru pt Statu s (TLS2)
0 = No interr upt pending.
1 = Int er r upt pending.
Bit 0: Tran smit Latched Statu s Regi st er 1 Interru pt Statu s (TLS1)
0 = No interr upt pending.
1 = Int er r upt pending.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 228 of 305
Register Name:
TIM1
Register Desc r iptio n:
Transmit Interrup t Mask Regist er 1
Register Addr ess :
1A0h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TESF
TESEM
TSLIP
TSLC96
—
TMF
LOTCC
LOTC
TESF
TESEM
TSLIP
—
TAF
TMF
LOTCC
LOTC
Default
0
0
0
0
0
0
0
0
Bit 7: Transmit Elastic S tore Fu ll E vent (TE SF)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 6: Tran smit Elastic Store Empty E vent (TES EM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: Tran smit Elastic Store Sli p O ccurren ce E vent (TSLIP)
0 = Interrupt masked.
1 = Int er r upt enabled.
Bit 4: Tran smit SLC96 Mul t iframe Event (TSLC96) (T1 Mode Only)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Tran smit Align Frame Event (TAF) ( E 1 Mode Only)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Transmit Multiframe E vent (TMF)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Lo ss of Tran smit Clo ck Clear Cond ition (LOTCC)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Loss of Transmit Clock Condition (LOTC)
0 = Interrupt mas ked.
1 = Interrupt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 229 of 305
Register Name:
TIM2
Register Desc r iptio n:
Transmit Interrup t Mask Regist er 2 ( HDLC-64)
Register Addr ess :
1A1h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
TFDLE
TUDR
TMEND
TLWMS
TNFS
—
—
—
—
TUDR
TMEND
TLWMS
TNFS
Default
0
0
0
0
0
0
0
0
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Tran smit FIFO Und errun E vent (TUDR)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Tran smit Message End Event (TMEND)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Tran smit FIFO Below Low Watermark S et Condition (TLWMS)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0: Transmit FIFO Not Full Set Condition (TNFS)
0 = Interrupt mas ked.
1 = Interrupt enabled.
Register Name:
TIM3
Register Desc r iptio n:
Transmit Interrup t Mask Regist er 3 ( S ynch ron izer)
Register Addr ess :
1A2h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
LOFD
Default
0
0
0
0
0
0
0
0
Bit 0: Loss Of Frame Synch ron ization Detect (LOF D)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 230 of 305
Register Name:
T1TCD1 (T1 Mode Only)
Register Desc r iptio n:
Transmit Code Def in iti on Regi st er 1
Register Addr ess :
1ACh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bit 7: Tran smit Code Def in ition Bit 7 (C7). First bit of the repeat ing pattern.
Bit 6: Tran smit Code Def in ition Bit 6 (C6)
Bit 5: Tran smit Code Def in ition Bit 5 (C5)
Bit 4: Tran smit Code Definition Bit 4 (C4)
Bit 3: Tran smit Code Def in ition Bit 3 (C3)
Bit 2: Tran smit Code Def in ition Bit 2 (C2). A Don’t Care if a 5-bit length is selected.
Bit 1: Tran smit Code Def in ition Bit 1 (C1). A Don’t Care if a 5- or 6-bit length is selected.
Bit 0: Tran smit Code Def in ition Bit 0 (C0). A Don’t Care if a 5-, 6-, or 7-bit length is selected.
Register Name:
T1TCD2 (T1 Mode Only)
Register Desc r iptio n:
Transmit Code Def in iti on Regi st er 2
Register Addr ess :
1ADh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Bit 7: Tran smit Code Def in ition Bit 7 (C7). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 6: Tran smit Code Def in ition Bit 6 (C6). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 5: Tran smit Code Def in ition Bit 5 (C5). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 4: Tran smit Code Def in ition Bit 4 (C4). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 3: Tran smit Code Def in ition Bit 3 (C3). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 2: Tran smit Code Def in ition Bit 2 (C2). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 1: Tran smit Code Def in ition Bit 1 (C1). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
Bit 0: Tran smit Code Def in ition Bit 0 (C0). A Don’t Care if a 5-, 6-, o r 7-bit length is selected.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 231 of 305
Register Name:
TRTS2
Register Desc r iptio n:
Transmit Real-Time Status Register 2 ( HDLC-64)
Register Addr ess :
1B1h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
TEMPTY
TFULL
TLWM
TNF
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty ( TEMPTY). A real-time bit t hat is set high when the F IF O is empty.
Bit 2: Tr a ns m it FIFO Fu ll (TFULL). A real-time bit that i s set hi gh when the FIFO is full.
Bit 1: Tran smit FIFO Below Low Watermark Condition (TLWM) . Set when the tr ansmit 64-byte FIFO empties
beyond the low watermark as defined by the tr ansmit low watermark bits (TLW M).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the t r ansmit 64-byte FIFO has at least one by te
available.
Register Name:
TFBA
Register Desc r iptio n:
Transmit HDLC-64 FIF O Bu f f er Avail abl e Regi st er
Register Addr ess :
1B3h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
Name—
TFBA6
TFBA5
TFBA4
TFBA3
TFBA2
TFBA1
TFBA0
Default
0
0
0
0
0
0
0
0
Bits 6 to 0: Tran smit FI FO Bytes Available (TFB A6 t o TFB A0 ). TFB A 0 is the LSB.
Register Name:
THF
Register Description:
Transmit HDLC-64 FIFO
Register Addr ess :
1B4 + ( 200h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
THD7
THD6
THD5
THD4
THD3
THD2
THD1
THD0
Default
0
0
0
0
0
0
0
0
Bit 7 : T ransmit HDLC-64 Data Bit 7 (THD7). MSB of a HDLC-64 packet data byte.
Bit 6 : T ransmit HDLC-64 Dat a Bit 6 (THD6).
Bit 5 : T ransmit HDLC-64 Data Bit 5 (THD5).
Bit 4 : T ransmit HDLC-64 Data Bit 4 (THD4).
Bit 3 : T ransmit HDLC-64 Data Bit 3 (THD3).
Bit 2 : T ransmit HDLC-64 Data Bit 2 (THD2).
Bit 1 : T ransmit HDLC-64 Data Bit 1 (THD1).
Bit 0 : Transmit HDLC-64 Data Bit 0 (THD0). LSB of a HDLC-64 packet dat a by te.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 232 of 305
Register Name:
TDS0M
Register Desc r iptio n:
Transmit DS0 Moni t or Register
Register Addr ess :
1BBh + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
B1
B2
B3
B4
B5
B6
B7
B8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Tran smit DS 0 Channel Bit s ( B[ 1: 8] ). Transmit channel dat a that has been sel ec ted by the TDS0SEL
regi ster . B8 is the LSB of the DS0 channel (last bit to be transmi tt ed) .
Register Name:
TBC S1, TBCS2, TBCS3, TBCS4
Register Desc r iptio n:
Transmit Blank Channel Sel ect Regi st ers 1 to 4
Register Addr ess :
1C0h, 1C1h, 1C2h, 1C3h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Named
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TBCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TBCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TBCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
TBCS4
(E1 Mode
Only)
Bits 7 to 0: Tran smit Blank Channel S elect fo r Channels 1 to 32 (CH[1:32])
0 = Transmit TSERn data fr om this channel.
1 = Ignore TSERn dat a from this channel.
Note t hat when two or more sequential channels are chosen to be ignored, t he r ec eiv e sli p z one sel ect bit should
be set to zer o. If t he ignor e c hannels are distri buted (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be
set to one, whic h m ay provide a lower occurrenc e of slips in cer tai n applicati ons.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 233 of 305
Register Name:
TCBR1 , TCBR2 , TCBR3, TCBR4
Register Desc r iptio n:
Transmit Channel Blo cking Regi st ers 1 to 4
Register Addr ess :
1C4h, 1C5h, 1C6h, 1C7h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
TCBR4 (E1
Mode Only)*
Bits 7 to 0: Tran smit Channels 1 to 32 Channel Blockin g Cont rol Bits ( CH[ 1: 32] ) .
0 = Forc e the T CHB LK n pin to rem ain low duri ng this channel t im e.
1 = Force the TCHBLKn pin high during this channel time.
* Note that TCBR4 h as two fun ction s:
When 2.048M Hz bac k plane m ode is selected, t his register allows the user to enabl e the channel bloc ki ng
signal for any of the 32 possible backpl ane c hannels.
When 1.544M Hz bac k plane m ode is selected, t he LSB of this register determi nes whether or not the
TCHBLK n si gnal will pul se hi gh duri ng the F-bit time:
TCBR4.0 = 0, do not pulse TCHB LK n duri ng the F-bit.
TCBR4.0 = 1, pulse TCHBLKn during the F-bit.
In t his mode T CB R4.1 to TCBR4.7 should be set to 0.
Register Name:
TH SCS1, THSCS2, TH SCS3, THSCS4
Register Description:
Transmit Hardware-Signaling Channel Select Registers 1 to 4
Register A ddr es s:
1C8h, 1C9h, 1CAh, 1CBh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
THSCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
THSCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
THSCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
THSCS4
(E1 Mode
Only)*
Bits 7 to 0: Tran smit Hardware-Signali ng Channel Select f or Chann els 1 to 32 (CH[1: 32] ) . T hese bi ts
determ ine which channels have signaling data insert ed from t he TSIG n pin into the TSERn PCM data.
0 = Do not source signaling data fr om the TSIG n pin for this channel.
1 = Source si gnaling data from the T SIGn pin for this channel.
* Not e that THSCS 4 is only used in 2.048MHz backplane app li cat io ns.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 234 of 305
Register Name:
TGCCS1, TGCCS2, TGCCS3, TGCCS4
Register Desc r iptio n:
Transmit Gapped Clock Chann el Select Registers 1 to 4
Register Address:
1CCh, 1CDh, 1CEh, 1CFh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TGCCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TGCCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TGCCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
TGCCS4 (E1
Mode Only)*
Bits 7 to 0: Tran smit Channels 1 to 32 Gapped Clock Channel Select Bits (CH[1:32])
0 = no cl ock is present on TCHCLK dur ing this channel time
1 = force a clock on TCHCLK during this channel time. The clock will be synchr onous with TCLKn if t he
elastic store is di sabl ed, and sync hr onous with TSYSCLKn if t he elastic stor e is enabled.
* Note that TG CCS 4 has two fun ction s:
When 2.048M Hz bac k plane m ode is selected, t his register allows the user to enabl e the gapped clock on
TCHCLK for any of t he 32 possible backplane channels.
When 1.544M Hz bac k plane m ode is selected, t he LSB of this register determines whether or not a clock is
generated on TCHCLK during the F -bit ti me:
TG CCS 4.0 = 0, do not generat e a cl oc k during the F-bit.
TG CCS 4.0 = 1, generate a clock duri ng the F-bit.
In t his mode TGCCS 4.1 to TG CCS 4.7 should be set t o 0.
Register Name:
PCL1, PCL2, PCL3, PCL4
Register Desc r iptio n:
Per-Channel Loopback Enable Registers 1 to 4
Register Addr ess :
1D0h, 1D1h, 1D2h, 1D3h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
PCL1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
PCL2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
PCL3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
PCL4 (E1
Mode Only)
Bits 7 to 0: Per-Chann el Loop back Enable for Channels 1 to 32 (CH[1:32] )
0 = Loopbac k disabl ed.
1 = Enabl e loopbac k . Source data fr om the correspondi ng r ec eive channel.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 235 of 305
Register Name:
TB PCS1, TBPCS2, TB PCS3, TBPCS4
Register Desc r iptio n:
Transmit BERT Port Ch ann el Select Registers
Register Addr ess :
1D4h, 1D5h, 1D6h, 1D7h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TBPCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TBPCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TBPCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
TBPCS4
(E1 Mode
Only)
Setting any of the CH[ 1:32] bits in t he TBP CS 1 to TBPCS4 register s wil l enable the transmit BERT clock for th e
associated channel time, and allow mapping of the sel ected c hannel data out of the rec eiv e BERT port . Multiple or
all c hannels m ay be sel ec ted simultaneously.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 236 of 305
10.5 LIU Register Definitions
Table 10-18. LIU Register Set
ADDRESS NAME DESCRIPTION R/W
1000h LTRCR LIU T r ansmit Rec eive Control Regi ster R/W
1001h LTIPSR LIU T r ansmit Impedanc e and P ulse Shape Sel ection Register R/W
1002h LMCR LIU Maintenance Control Regi ster R/W
1003h LRSR LIU Real Status Regi ster R
1004h LSIMR LIU Status Interrupt M ask Register R/W
1005h LLSR LIU Latched S tatus Regi ster R/W
1006h LRSL LIU Receive Signal Lev el Register R
1007h LRISMR LIU Receive Im pedanc e and S ensi tivity Monit or Register R/W
1008h LRCR LIU Receive Control Register R/W
1009h–101Fh — Reserved —
Note: Reserved registers should only be written with all zeros.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 237 of 305
Register Name:
LTRCR
Register Desc r iptio n:
LI U Tran smit Receive Control Regi st er
Register Addr ess es:
1000h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
RHPM
JADS1
JADS0
JAPS1
JAPS0
T1J1E1S
LSC
Default
0
0
0
0
0
0
0
0
Bit 6: Receive Hit less Protecti on Mode (RHPM).
0 = Normal operat ion using software for hitless prot ec tion (RIMPON) .
1 = Hitless protection switc hing mode usi ng TXENAB LE pi n.
If the TXENABLE pin is low and this bit is set to one, the receive LIU will present a high impedance to the line,
ov er ri ding the receive im pedanc e sel ec tion register bits LRISMR.RIMPM [2 :0].
Bits 5 and 4 : Jitter Attenuator Depth Select (JADS[1:0] )
JADS1 JADS0 FUNCTION
0
0
Ji tt er att enuator FIFO depth 128 bit s.
0
1
Ji tt er att enuator FIFO depth 64 bit s.
1
0
Ji tt er att enuator FIFO depth 32 bits.
1
1
Ji tt er att enuator FIFO depth 16 bit s (used for del ay sensit ive applications).
Bits 3 and 2: Jitt er Atten uator Posi t io n Sel ect ( JAPS[1: 0] ) . These bit s are used to select the posi tion of the jitt er
attenuator.
JAPS1
JAPS0
FUNCTION
0
0
Jitter att enuator in the receive pat h.
0
1
Ji tt er att enuator in the transmit path.
1
0
Ji tt er att enuator disabled.
1
1
Ji tt er att enuator disabled.
Bit 1: T1J1E1 S election (T1J1E1S) . This bi t configures the LIU for E1 or T1/ J 1 operation.
0 = E1
1 = T1 or J1
Bit 0: LOS Selection Criteria (LS C) . T his bi t is used for LIU LOS sel ec tion criteri a.
E1 Mode
0 = G.775
1 = ETS 300 233
T1/J1 Mode
0 = T1.231
1 = T1.231
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 238 of 305
Register Name:
LTIPSR
Register Desc r iptio n:
LIU Transmit Impedance and Pulse Shape Selection Register
Register Addr ess :
1001h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TG703
TIMPTON
TIMPL1
TIMPL0
—
L2
L1
L0
Default
0
0
0
0
0
0
0
0
Bit 7: Transmit G.703 S ynchronization Clock (TG703)
0 = Normal tr ansmitter mode.
1 = G.703 2.048MHz cl oc k transmitted on TTIPn and TRING n.
Bit 6: Transmit Impedance On (TIMPTON)
0 = Disabl e transmit terminating im pedanc e.
1 = Enabl e transmit terminati ng im pedanc e.
Bits 5 and 4: T ransmit Load Impedance 1 and 0 (TIMPL[1:0]). These bits are used to select the transmit load
im pedanc e. These must be set to match the c able im pedance. Even if the Inter nal load impedance is turned off (v ia
TIMPTOFF); the external cable impedance has to be specified for optimum operation. For J1 applications, use
110Ω. See Table 10-19.
Bits 2 to 0: Line Build-Out Select 2 to 0 (L[2:0] ). Used to select t he transmit waveshape. The waveshape ha s a
v oltage l ev el and load impedance associated with it once the T 1/J1 or E1 selec tion is made by settings in the
LTRCR register. See Table 10-20.
Table 10-19. Transmit Load Impedance Selection
TIMPL1
TIMPLO
IMPEDANCE SELECTIO N
0
0
75
Ω
0
1
100
Ω
1
0
110Ω
1
1
120
Ω
Table 10-20. Transmit Pulse Shape Selection
L2 L1 L0 MODE IMPEDANCE
NOMINAL
VOLTAGE
0
0
0
E1
75Ω
2.37V
0
0
1
E1
120
Ω
3.0V
L2 L1 L0 MODE CABLE LENGTH
MAX
ALLOWED
CABLE LOSS
0
0
0
T1/J1
DSX-1/0dB CS U, 0ft –133f t ABAM 100
Ω
0.6dB
0
0
1
T1/J1
DSX-1, 133ft–266ft ABAM 100
Ω
1.2dB
0 1 0 T1/J1
DSX-1, 266ft–399ft ABAM 100
Ω
1.8dB
0
1
1
T1/J1
DSX-1, 399ft–533ft ABAM 100
Ω
2.4dB
1
0
0
T1/J1
DSX-1, 533ft–655ft ABAM 100
Ω
3.0dB
1
0
1
T1/J1
-7.5dB CS U
—
1
1
0
T1/J1
-15dB CSU
—
1
1
1
T1/J1
-22.5dB CS U
—
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 239 of 305
Register Name:
LMCR
Register Desc r iptio n:
LI U Maintenance Control Reg ister
Register Addr ess :
1002h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TAIS
ATAIS
LB2
LB1
LB0
TPDE
RPDE
TE
Default
0
0
0
0
0
0
0
0
Bit 7: Manual Tran smit AIS (TAIS ) . Alarm I ndic ation Signal (AIS) is sent using MCLK as the reference cloc k . The
transmit data coming from the framer is ignored.
0 = TAIS is dis abled.
1 = Out put an unf r am ed all-ones patt er n ( A IS) at TTIPn and TRINGn.
Bit : Automatic Transmit AIS (AT AIS)
0 = ATAIS is disabled.
1 = Autom atical ly transmit AIS on the occ ur r enc e of an LIU LOS.
Bits 5 to 3: Loopb ack S election (LB[2:0] . See Figure 9-28 for more details on each loopbac k .
LB2 LB1 LB0 Loo pb ack S election
0
0
0
No loopbac k sel ec ted
0
0
1
Rem ote Loopback 2 ( includes jitt er att enuator)
0
1
0
Anal og Loopbac k
0
1
1
Rem ote Loopback 1 ( no jitter att enuator)
1
0
0
Local Loopbac k ( includes jitt er attenuator)
1 0 1
Dual Loopbac k —Remote Loopback 1 and Local Loopbac k ( jitter
att enuator is included in Local Loopback)
1
1
0
Reserved
1
1
1
Reserved
Bit 2: Tran smit Pow er-Down Enable (TPDE)
0 = Transmitter power enabled.
1 = Transmitter powered down. TTI P n/T RINGn outputs are hi gh im pedanc e.
Bit 1: Receiver Power-Down Enable (RPDE)
0 = Rec eiv er power enabl ed.
1 = Rec eiv er powered down.
Bit 0: Transmit Enable (TE). Thi s func tion is overri dden by the TXENABLE pin.
0 = TTIP n/T RINGn out puts are high im pedance.
1 = TTIP n/T RINGn out puts enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 240 of 305
Register Name:
LRSR
Register Desc r iptio n:
LI U Real St atu s Regi st er
Register Addr ess :
1003h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
OEQ
UEQ
RSCS
TSCS
OCS
LOSS
Default
0
0
0
0
0
0
0
0
Bit 5: Over Equali z ed (OEQ). The equalizer is over equali z ed. T his can happen if there very large unexpected
resistive loss. This could result if monitor mode is used and t he dev ice is not placed in monitor mode. This indicator
provides more qualitative in forma tion to the receive loss indicators.
Bit 4: Under Equalized (UEQ). The equalizer is under equal ized. A signal wit h a v ery high resi stive gain is being
applied. This indic ator provides m or e qualitative inf ormati on to t he r ec eiv e loss indicator s.
Bit 3: Recei ve Short-Circuit Status (RSCS). A real-time bit set when the LIU det ec ts that the RTIPn and RRING n
inputs are short -c ircuit ed. T he load r esi stanc e has to be 25Ω (ty pic ally) or less for short cir c uit det ec tion.
Bit 2: Tran smit Sho rt -Circuit Status (TSCS). A real-time bit set when the LI U detects that the TTIP n and
TRI NGn outputs are short-c ircuited. The l oad r esi stanc e has to be 25Ω (ty pic ally) or less for short ci r c uit det ection.
Bit 1: Open-Circuit Status (OCS). A real-time bit t hat is set when the LI U detects that the TTIPn and TRINGn
output s are open-circuited.
Bit 0: Loss of Signal Status (LOSS). A real-tim e bit that is set when the LIU detects an LOS conditi on at RTIPn
and RRING n.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 241 of 305
Register Name:
LSIMR
Register Desc r iptio n:
LIU Status Interrup t Mask Regist er
Register Addr ess :
1004h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
JALTCIM
OCCIM
SCCIM
LOSCIM
JALTSIM
OCDIM
SCDIM
LOSDIM
Default
0
0
0
0
0
0
0
0
B it 7: Ji t t er Atten uato r Li mit Trip Clear In t errup t M ask (JALTCIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 6: Open-Ci rcui t Clear Int errupt Mask (OCCIM )
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 5: Short-Circuit Cl ear In t errup t Mask (S CCIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 4: Loss of Signal Clear Interrupt Mask (LOSCIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: Jitt er Atten uator Limit Trip Set Int errup t M ask (JALTSIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 2: Open-Ci rcui t Det ect Interrupt Mask (OCDIM )
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 1: Short-Circuit Detect Interrupt Mask (SCDIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 0 : Loss of Sign al Detect Interrup t Mask (LO S DIM)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 242 of 305
Register Name:
LLSR
Register Desc r iptio n:
LI U Latched S t atus Regi st er
Register Addr ess :
1005h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
JALTC
OCC
SCC
LOSC
JALTS
OCD
SCD
LOSD
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are latched and can create interrupts.
Bit 7: Jitt er Atten uator Limit Trip Clear (JALTC). This l atched bit is set when a JA lim it trip c ondition was
detected and then rem ov ed.
Bit 6: Open-Ci rcui t Clear (OCC). This latched bit i s set when an open circ uit condition was detected at TT IPn and
TRI NGn and then r em ov ed.
Bit 5: Short-Circuit Cl ear (SCC). This latched bit is set when a short circuit condi tion was detected at TTIP n and
TRI NGn and then r em ov ed.
Bit 4: Lo ss of Sign al Cl ear (LOSC) . T his l atched bit i s set when a loss of signal conditi on was detected at RTIPn
and RRING n and then removed.
Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator tri p condi tion is
detected.
Bit 2: Open-Ci rcui t Det ect (O CD). This latched bit is set when open-ci r c uit condition i s detec ted at TT IPn and
TRI NGn. This bit i s not functional in T1 CSU operati ng m odes (T 1 LBO 5, LBO 6, and LBO 7).
Bit 1: Short-Circuit Detect (SCD). This latched bit i s set when shor t-cir c uit condition is detec ted at TT IPn and
TRI NGn. This bit i s not functional in T1 CSU operati ng m odes (T 1 LBO 5, LBO 6, and LBO 7).
Bit 0: Lo ss of Sign al Detect (LOSD) . This latched bi t is set when an LOS c ondition is detected at RTIPn and
RRINGn.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 243 of 305
Register Name:
LRSL
Register Desc r iption:
LI U Receive Signal Level Register
Register Addr ess :
1006h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RSL3
RSL2
RLS1
RLS0
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 10-21.
Note t hat t he range of si gnal lev els report ed the RS L[3:0] is l imited by the Equali zer Gai n Limit (EGL) in short-haul
applications.
Table 10-21. Receive Level Indication
RSL3 RSL2 RSL1 RSL0 RECEIVE LEVEL
DS1/E 1 (d B)
0
0
0
0
> -2.5
0
0
0
1
-2.5 t o -5
0
0
1
0
-5 to -7.5
0
0
1
1
-7.5 t o -10
0
1
0
0
-10 to -12.5
0
1
0
1
-12.5 t o -15
0
1
1
0
-15 to -17.5
0
1
1
1
-17.5 t o -20
1
0
0
0
-20 to -22.5
1
0
0
1
-22.5 t o 25
1
0
1
0
-25 to -27.5
1
0
1
1
-27.5 t o -30
1
1
0
0
-30 to -32.5
1
1
0
1
-32.5 t o -35
1
1
1
0
-35 to -37.5
1
1
1
1
< -37.5
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 244 of 305
Register Name:
LRISMR
Register Desc r iptio n:
LIU Receive Impedance and Sensitivity Monitor Regist er
Register Addr ess :
1007h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
RIMPON
—
—
—
RIMPM2
RIMPM1
RIMPM0
Default
0
0
0
0
0
0
0
0
Bit 6: Recei ve In t ernal Imp edance Mat ch On (RIMPON)
0 = Receive internal impedance termination is disabled (high impedance).
1 = Receive internal impedance termination is enabled.
Bits 2 to 0: Receive Impedance Selection (RIMPM[2:0]). These bits are used to select the receive impedance
termination. They must be set accor ding t o the c abl e i m pedance ev en if int ernal termi nation resi stance i s di sabl ed
(RIM PON = 0) . See Table 10-22.
Table 10-22. Receive Impedance Selection
RIMPON RIMPRM[2:0] RECEIVE IMPEDANCE SELECTED (
Ω
)
0
x00
75Ω external termination (no internal impedance match)
0
x01
100Ω e xternal termination (no internal impedanc e m atch)
0
x10
110
Ω
externa l termination (no internal impedanc e m atch)
0
x11
120
Ω
externa l termination (no internal impedanc e m atch)
1
000
75
Ω
, wi th ex ternal 120
Ω
resistor
1
001
100
Ω
, wit h exter nal 120
Ω
resistor
1
010
110
Ω
, wit h exter nal 120
Ω
resistor
1
011
120
Ω
, wit h exter nal 120
Ω
resistor
1
100
75
Ω
inter nal terminati on
1
101
100Ω inter nal terminati on
1
110
110Ω internal termination
1
111
120
Ω
inter nal terminati on
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 245 of 305
Register Name:
LRCR
Register Desc r iptio n:
LI U Receive Control Regist er
Register Addr ess :
1008h + (20h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RG703
—
—
—
RTR
RMONEN
RSMS1
RSMS0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive G.703 Clock (RG703). If this bit is set, the rec eiver expects a 2.048M Hz or 1.544MHz cl oc k from
the RT IPn/RRINGn, based on the sel ec tion of T1 (1.544) or E 1 ( 2.048) m ode in the LTRCR register.
Bit 3: Receiver Turns Ratio (RT R)
0 = Rec eiv e transformer turns rati o is 1:1.
1 = Rec eiv e transformer turns rati o is 2:1. This opti on shoul d only be used i n short-haul applic ations.
Note: Internal impedance match is not available for this mode.
Bit 2: Receiver Monito r Mode Enable ( RMONE N)
0 = Disabl e r ec eiv e m onitor mode.
1 = Enabl e r ec eiv e m onitor mode. Resi stive gain is added wi th the maximum sensitivity. The rec eiver
sensit ivit y is determined by RSMS1 and RSMS0.
Bits 1 and 0: Receiver Sensitivity/Monitor Gain Select (RSMS[1:0]). These bits are used to select the receiver
sensit iv ity l ev el and additional gai n in m onitori ng applicati ons. The monitor m ode (RMONEN) adds resi stiv e gai n to
compensate for the signal loss caused by t he isolati on resistors. See Table 10-23 and Table 10-24.
Table 10-23. Receiver Sensitivity Selection with Monitor Mode Disabled
RMONEN RSMS[1:0] RECEIVER
MONITOR MODE
GAIN (dB)
RECEIVER SENSI TI VI TY
(MAX CABLE LOSS
ALLOWED) (dB)
0
00
0
12
0
01
0
20
0
10
0
30
0
11
0
36 for T1; 43 for E1
Table 10-24. Receiver Sensitivity Selection with Monitor Mode Enabled
RMONEN RSMS[1:0]
RECEIVER
MONITOR MODE
GAIN (dB)
RECEIVER SENSI TI VI TY
(MAX CABLE LOSS
ALLOWED) (dB)
1
00
14
30
1
01
20
22.5
1
10
26
17.5
1
11
32
12
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 246 of 305
10.6 BERT Register Definitions
Table 10-25. BERT Register Set
ADDRESS NAME DESCRIPTION R/W
1100h BAWC BERT Alt er nating Word Count Rate Regist er R
1101h BRP1 BERT Repetitive Patt er n Set Register 1 R/W
1102h BRP2 BERT Repetitive Patt er n Set Register 2 R/W
1103h BRP3 BERT Repetitive Patt er n Set Register 3 R/W
1104h BRP4 BERT Repetitive Patt er n Set Register 4 R/W
1105h BC1 BERT Cont r ol Register 1 R/W
1106h BC2 BERT Cont r ol Register 2 R/W
1107h BBC1 BERT Bit Count Regi ster 1 R
1108h BBC2 BERT Bit Count Regi ster 2 R
1109h BBC3 BERT Bit Count Regi ster 3 R
110Ah BBC4 BERT Bit Count Register 4 R
110Bh BEC1 BERT Error Count Regi ster 1 R
110Ch BEC2 BERT Error Count Regi ster 2 R
110Dh BEC3 BERT Error Count Regi ster 3 R
110Eh BSR BERT Latched Stat us Regi ster R
110Fh BSIM BER T Sta tu s Inte rrupt Mask Register R/W
Register Name:
BAWC
Register Desc r iptio n:
BERT Alternating Word Coun t Rate Regist er
Register Addr ess :
1100h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
ACNT7
ACNT6
ACNT5
ACNT4
ACNT3
ACNT2
ACNT1
ACNT0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the
alternating word mode, the words will repeat for the count loaded into this register then flip to the other word and
again repeat for the number of times loaded i nto this register. ACNT0 is the LSB of the 8-bit alt ernati ng word count
rate c ounter.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 247 of 305
Register Name:
BRP1
Register Desc r iptio n:
BERT Repetitive Pattern Set Register 1
Register Addr ess :
1101h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RPAT7
RPAT6
RPAT5
RPAT4
RPAT3
RPAT2
RPAT1
RPAT0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]) . RPAT0 is the LSB of t he 32-bit repetitive
pattern.
Register Name:
BRP2
Register Desc r iptio n:
BERT Repetitive Pattern Set Register 2
Register Addr ess :
1102h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RPAT15
RPAT14
RPAT13
RPAT12
RPAT11
RPAT10
RPAT9
RPAT8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 15 to 8 (RPAT [ 15: 8] )
Register Name:
BRP3
Register Desc r iptio n:
BERT Repetitive Pattern Set Register 3
Register Addr ess :
1103h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RPAT23
RPAT22
RPAT21
RPAT20
RPAT19
RPAT18
RPAT17
RPAT16
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 23 to 16 (RPAT [ 23: 16] )
Register Name:
BRP4
Register Desc r iptio n:
BERT Repetitive Pattern Set Register 4
Register Addr ess :
1104h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RPAT31
RPAT30
RPAT29
RPAT28
RPAT27
RPAT26
RPAT25
RPAT24
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 31 to 24 (RPAT [ 31: 24] ) . RPAT31 is the MSB of the 32-bit
repetitiv e patt er n.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 248 of 305
Register Name:
BC1
Register Description:
BERT Con t rol Regi st er 1
Register A ddr es s:
1105h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TC
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
Default
0
0
0
0
0
0
0
0
Bit 7: T ransmit Pattern Load (T C). A l ow-to-high transiti on loads the pattern generator wit h the patter n that is to
be generated. This bit should be t oggled from low to high whenever the host wi sh es to load a new p attern. Must b e
cl ear ed and set again for a subsequ ent loads.
Bit 6:Transmit In vert Dat a Enable (TINV)
0 = Do not inver t t he outgoing data stream.
1 = Inver t t he outgoing data stream.
Bit 5: Receive Invert Data Enable (RINV).
0 = Do not inver t t he inc omi ng data str eam .
1 = Inver t t he inc omi ng data str eam .
Bits 4 to 2: Pattern Sel ect Bits 2 to 0 (PS[2:0]) . These bits select data pat tern used by the transmit and receiv e
circuits. See Table 10-26.
Table 10-26. BERT Pattern Select
PS2 PS1 PS0 PATTERN DEFINITION
0 0 0 P seudorandom 2E 7–1.
0 0 1
Pseudorandom 2E11–1.
0 1 0 P seudorandom 2E 15–1.
0 1 1 P seudorandom P att er n QRSS . A 2
20
- 1 pattern with 14 consecutive zero restric tion.
1 0 0
Repetitive P att er n.
1 0 1 Alternating Word Pattern.
1 1 0
Modified 55 Octet (Daly ) P att er n. T he Daly pattern is a repeati ng 55 oc tet patter n that i s
byte-aligned i nto the active DS0 time slots. The pattern is defined i n an ATIS (Alliance
for Tel ec ommuni c ations I ndustr y S olutions) Committ ee T1 T ec hnic al Repor t Number 25
(November 1993) .
1 1 1 P seudorandom 2E -9-1.
Bit 1: Lo ad Bit and Error Count ers ( LC). A low-to-high tr ansi tion latches the c ur r ent bit and err or c ounts int o the
regi ster s BBC1, BBC2, BBC3, BB C4 and BEC1, BEC2, BEC3 and cl ear s the int er nal c ount. Thi s bi t should be
toggled from l ow to high whenev er the host wi shes to begi n a new acqui si tion peri od. Must be cl ear ed and set
again for a subsequent loads.
Bit 0: Fo rce Resynchronization ( RE SYNC). A low -to-hi gh transition will force the receiv e B E RT synchronizer to
resynchronize to the i nc omi ng data str eam . T his bit shoul d be toggl ed from low to high whenever the host wishes
to acquire synchronization on a new pat tern. Must be cleared and set again for a subseque nt resynchronization.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 249 of 305
Register Name:
BC2
Register Description:
BERT Con t rol Regi st er 2
Register Addr ess :
1106h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EIB2
EIB1
EIB0
SBE
RPL3
RPL2
RPL1
RPL0
Default
0
0
0
0
0
0
0
0
Bits 7 to 5: Error In sert Bits 2 to 0 (EIB[ 2: 0] ). Will automatically insert bit er r or s at the prescribed rat e into t he
generated data patt er n. Can be used for v erify ing error detection f eatures. See Table 10-27.
Table 10-27. BERT Error Insertion Rate
EIB2 EIB1 EIB0 ERROR RATE INSERTED
0
0
0
No errors automati c ally insert ed
0
0
1
10E-1
0
1
0
10E-2
0
1
1
10E-3
1
0
0
10E-4
1
0
1
10E-5
1
1
0
10E-6
1
1
1
10E-7
Bit 4: Sing le Bit Erro r In sert ( S BE). A low -to-hi gh transit ion will create a singl e bit err or . Must be cl ear ed and set
again for a subsequent bit err or to be inserted.
Bits 3 to 0: Repetitive Pattern Length Select 3 to 0 (RPL[3:0]). RPL0 is the LSB and RPL3 is the MSB of a
nibble that describes the how long the repetitiv e pattern is. The valid range is 17 (0000) to 32 (1111). These bits
are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns fewer
than 17 bits in length, the user m ust set t he length t o an integer number of the desired length that i s less th an or
equal to 32. F or exampl e, to create a 6-bit patter n, the user ca n set the length t o 18 (00 01) or to 24 ( 0111) or t o 30
(1101). S ee Table 10-28.
Table 10-28. BERT Repetitive Pattern Length Select
LENGTH
(BITS)
RPL3 RPL2 RPL1 RPL0
17
0
0
0
0
18
0
0
0
1
19
0
0
1
0
20
0
0
1
1
21
0
1
0
0
22
0
1
0
1
23
0
1
1
0
24
0
1
1
1
25
1
0
0
0
26
1
0
0
1
27
1
0
1
0
28
1
0
1
1
29
1
1
0
0
30
1
1
0
1
31
1
1
1
0
32
1
1
1
1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 250 of 305
Register Name:
BBC1
Register Desc r iptio n:
BERT Bit Count Regi st er 1
Register Addr ess :
1107h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BBC7
BBC6
BBC5
BBC4
BBC3
BBC2
BBC1
BBC0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Bit Count er Bits 7 to 0 (BBC[7:0] ) . BB C0 is the LS B of the 32-bit c ounter.
Register Name:
BBC2
Register Desc r iptio n:
BERT Bit Count Regi st er 2
Register Addr ess :
1108h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BBC15
BBC14
BBC13
BBC12
BBC11
BBC10
BBC9
BBC8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Bit Count er Bits 15 to 8 ( BBC[ 15: 8]).
Register Name:
BBC3
Register Desc r iptio n:
BERT Bit Count Regi st er 3
Register Addr ess :
1109h + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BBC23
BBC22
BBC21
BBC20
BBC19
BBC18
BBC17
BBC16
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Bit Count er Bits 23 to 16 ( BBC[ 23:16]).
Register Name:
BBC4
Register Desc r iptio n:
BERT Bit Count Regi st er 4
Register Addr ess :
110Ah + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BBC31
BBC30
BBC29
BBC28
BBC27
BBC26
BBC25
BBC24
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: BERT Bit Count er Bits 31 to 24 ( BBC[ 31:24]). BBC31 is the MSB of the 32-bit counter.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 251 of 305
Register Name:
BEC1
Register Desc r iptio n:
BERT E rror Coun t Register 1
Register Addr ess :
110Bh + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EC7
EC6
EC5
EC4
EC3
EC2
EC1
EC0
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Error Count er Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit c ounter.
Register Name:
BEC2
Register Desc r iptio n:
BERT E rror Coun t Register 2
Register Addr ess :
110Ch + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EC15
EC14
EC13
EC12
EC11
EC10
EC9
EC8
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Error Count er Bits 15 to 8 (EC[15:8])
Register Name:
BEC3
Register Desc r iptio n:
BERT E rror Coun t Register 3
Register Addr ess :
110Dh + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
EC23
EC22
EC21
EC20
EC19
EC18
EC17
EC16
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Error Count er Bits 23 to 16 (EC[23:16]) . EC23 is the MSB of the 24-bit counter.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 252 of 305
Register Name:
BSR
Register Desc r iptio n:
BERT S t atus Regi st er
Register Addr ess :
110Eh + ( 10 h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
BBED
RBRA01
RSYNC
BRA1
BRA0
BRLOS
BSYNC
Default
0
0
0
0
0
0
0
0
Note: All latched bits in this register can create interrupts.
Bit 6: BE RT Bit Error Det ect ed (BED) E vent (BBED). A latched bit, which is set when a bit error is detected. T he
receive BERT must be in synchroni z ation for it to detect bit er r or s.
Bit 5: Real-time BERT All Zeros or Ones (RBA01). Or’d real time status of all zero detection and all ones
detection.
Bit 4: Real-time Sync (RSYNC). Real time sync status. A zero indicates not synchronized and a one indicates
synchroni z ation state.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit, which is set when 32 consecutive ones are
received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit, which is set when 32 consecutive zeros are
received.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). A latched bit which is set whenever the
receive BERT begins searching for a patt er n.
Bit 0: BERT in Synchronization Condition (BSYNC). A lat c hed bit that is set when the incomi ng pattern matches
for 32 consecut ive bit posit ions.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 253 of 305
Register Name:
BSIM
Register Desc r iptio n:
BERT Status Interrupt Mask Register
Register Addr ess :
110Fh + ( 10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
BBED
—
—
BRA1
BRA0
BRLOS
BSYNC
Default
0
0
0
0
0
0
0
0
Bit 6: BE RT Bit Error Detect ed Event (BBED)
0 = Interrupt mas ked.
1 = Int er r upt enabled.
Bit 3: BE RT Recei ve All Ones Condit io n (BRA1)
0 = Interrupt masked.
1 = Int er r upt enabled—interrupts on rising and falling edges.
Bit 2: BE RT Recei ve All Zero s Condition (BRA0)
0 = Interrupt mas ked.
1 = Int er r upt enabled—interrupts on rising and falling edges.
Bit 1: BE RT Recei ve Lo ss Of Synchro ni z at ion C ondition (BR LOS)
0 = Interrupt mas ked.
1 = Int er r upt enabled—interrupts on rising and falling edges.
Bit 0: BERT in Synchronization Condition (BSYNC)
0 = Interrupt mas ked.
1 = Int er r upt enabled—interrupts on rising and falling edges.
10.7 Extended BERT Register Definitions
Table 10-29. Extended BERT Register Set
ADDR ABBR DESCRIPTION R/W
1400
BERT Control Register 3
R/W
1401
BERT Real-Time Status Register
R
1402
BERT Latched S tatus Register 1
R/W
1403
BERT Status Interrupt Mask 1
R/W
1404
BERT Latched S tatus Register 1
R/W
1405
BERT Status Interr upt Mask 2
R/W
Register Name:
BC3
Register Description:
BERT Con t rol Regi st er 3
Register A ddr es s:
1400h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
- - - - - - 55OCT BALIGN
Default
0
0
0
0
0
0
0
0
Bit 1: 55 Octet Pattern (55OCT). This bit sel ec ts data pattern used by the tr ansmit and r ec eiv e ci r c uits.
0 = 55 Octet Pattern di sabl ed.
1 = 55 Octet patt er n enabled, when Modifi ed 55 Octet (Daly ) P att er n is selected by BC1.PSn register bits.
Bit 0: Byt e Alignment to DS 0 bound ary( BALI GN).
A low-to-high trans ition c auses the Tr ansmit BE RT pattern to be by te-ali gned to the DS0 boundar y . This
bit should be toggled from low to hi gh when a patt er n load is executed (BC1.TC)
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 254 of 305
Register Name:
BRSR
Register Desc r iptio n:
Bert Real-Time Status Register
Register Addr ess :
1401h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
- - - - BRA1 BRA0 BRLOS BSYNC
Default
0
0
0
0
0
0
0
0
Bit 3: BERT Receive All-Ones Condition (BRA1). This bit is set when 32 consecutive ones are received and
cl ear s when at least one z er o is received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). This bit is set when 32 consecutive zeros are received and
cl ear s when at least one “ one” is received.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). This bit i s set whenev er the receiv e BERT
begins searc hing for a patt er n and cl ear s when BERT enter SY NC c ondition.
Bit 0: BERT in Synchronization Condition (BSYNC). This bit is set when the incoming pattern matches for 32
consecutive bit positions and remains set until t he BERT enter s Loss of Sy nc hr oniz ation condition.
Register Name:
BLSR1
Register Desc r iptio n:
BERT Latched Status Register 1
Register Addr ess :
1402h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BRA1C BRA0C BRLOSC BSYNCC BRA1D BRA0D
BRLOS
D
BSYNCD
Default
0
0
0
0
0
0
0
0
All latched bits in this register c an c r eate int er r upts.
Bit 7: BERT Receive All-Ones Condition Cl ear (BRA1C). A latc hed bit, which i s set when the BERT trans itions
out of All -Ones Condition.
Bit 6: BERT Recei ve All-Zeros Condi tion Clear (BRA0C). A latched bit, which is set when the BERT transitions
out of All -Zeros Condi tion.
Bit 5: BERT Recei ve Lo ss Of Syn chronizat ion Condi tion Cl ear (BRLOSC) . A lat ched bi t whic h is set when the
BERT transi tions out of Loss Of Synchroniz ation Condition.
Bit 4: BERT in Synchronization Condition Clear (BSYNCC) . A l atched bi t that is set when the B ERT t ransit i ons
out of Synchr onizati on Condition.
Bit 3: BERT Receive All-O nes Condi tion Detect (BRA1D). A l at ched bit, which is set when 32 con secutive ones
are received.
Bit 2: BE RT Recei ve All -Zero s Con di t ion Det ect ( BRA0D). A latched bit, which is set when 32 consecutive zeros
are received.
Bit 1: BERT Receive Loss Of Synchronization Condition Detect (BRLOSD). A latched bit which is set
whenever the rec eiv e BERT begi ns searchi ng for a pattern.
Bit 0: BE RT in Syn chronization Condit io n Detect (BSYNCD). A l atched bit that is set when the inc omi ng patt er n
m atches for 32 consecutive bit positions.
Register Name:
BSIM1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 255 of 305
Register Desc r iptio n:
BERT S t atus In t errup t Mask Register 1
Register Addr ess :
1403h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
BRA1C BRA0C BRLOSC BSYNCC BRA1D BRA0D
BRLOS
D
BSYNCD
Default
0
0
0
0
0
0
0
0
Bit 7 : Recei ve All On es Condition Clear (BRA1C).
0 = interrupt mas ked
1 = interrupt enabled
Bit 6 : Recei ve All Zeros Condi t io n Cl ear ( BRA0C).
0 = interrupt mas ked
1 = interrupt enabled
Bit 5 : Recei ve Lo ss Of S ynch ron ization Condition Clear (BRLOSC)
0 = interrupt mas ked
1 = interrupt enabled
Bit 4 : BERT in S ynch ron izat io n Condition Clear (BSYNCC).
0 = interrupt mas ked
1 = interrupt enabled
Bit 3 : Recei ve All On es Condition Det ect ( BRA1D).
0 = interrupt mas ked
1 = interrupt enabled
Bit 2 : Recei ve All Zeros Condi t io n Detect ( BRA0D).
0 = interrupt mas ked
1 = interrupt enabled
Bit 1 : Recei ve Lo ss Of S ynchronization Condition Detect (BRLOSD)
0 = interrupt mas ked
1 = interrupt enabled
Bit 0 : BERT in S ynch ron izat io n Condition Detect (BSYNCD).
0 = interrupt mas ked
1 = interrupt enabled
Register Name:
BLSR2
Register Desc r iptio n:
BERT Latched Status Register 2
Register Addr ess :
1404h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
BED
BBCO
BECO
Default
0
0
0
0
0
0
0
0
All latched bits in this regist er c an c r eate int er r upts.
Bit 2: BERT Bit E rror Detect ed Event ( BED). A latched bit , which is set when a bi t err or i s detected. The receiv e
BERT m ust be in synchroni z ation for it to detect bit er r ors.
Bit 1: BERT Bit Counter O verflow Even t (BBCO). A lat ched bit, which i s set when t he 32-bit BE RT Bit Counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit, which is set when the 24-bit BERT Error
Counter ( B E C) ov erflows.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 256 of 305
Register Name:
BSIM2
Register Desc r iptio n:
BERT S t atus In t errup t Mask Register 2
Register Addr ess :
1405h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
BED
BBCO
BECO
Default
0
0
0
0
0
0
0
0
Bit 2 : Bi t Erro r Det ect ed Event (BED) .
0 = interrupt mas ked
1 = interrupt enabled
Bit 1 : BERT Bi t Coun t er Overflo w Event (BBCO ).
0 = interrupt mas ked
1 = interrup t enabled
Bit 0 : BERT Error Count er Overflow Event (BE CO).
0 = interrupt mas ked
1 = interrupt enabled
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 257 of 305
10.8 HDLC-256 Register Definitions
10.8.1 Transmit HDL C-256 Register Definitions
Table 10-30. Transmit Side HDLC-256 Register Map
ADDRESS
REGISTER
REGISTER DESCRIPTION
1500h
TH256CR1
Transmit HDLC-256 Cont r ol Register 1
1501h
TH256CR2
Transmit HDLC-256 Cont r ol Register 2
1502h
TH256FDR1
Transmit HDLC-256 FIFO Data Register 1
1503h
TH256FDR2
Transmit HDLC-256 FIFO Data Register 2
1504h
TH256SR1
Transmit HDLC-256 Stat us Register 1
1505h
TH256SR2
Transmit HDLC-256 Stat us Regi ster 2
1506h
TH256SRL
Transmit HDLC-256 Stat us Regi ster Latched
1507h
--
Unused
1508h
TH256SRIE
Transmit HDLC-256 Stat us Regi ster Interrupt Enable
1509h
--
Unused
150Ah
--
Unused
150Bh
--
Unused
150Ch
--
Unused
150Dh
--
Unused
150Eh
--
Unused
150Fh
--
Unused
Register Name:
TH256CR1
Register Description:
Transmit HDLC-256 Tra nsmit Con t rol Register 1
Register A ddr es s:
1500h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
TPSD
TFEI
TIFV
TBRE
TDIE
TFPD
TFRST
Default
0
0
0
0
0
0
0
0
Bit 6: Transmit Packet Start Disable (TPSD) – When 0, the Transmit Packet Processor will continue sending
packets after the current packet end. When 1, the Transmit Packet Processor will stop sending packets after the
current packet end.
Bit 5: T ransmit FCS Error Insertion (TFEI ) – W hen 0, the calc ulated FCS (inv ert ed CRC-16) is appended to the
packet. When 1, the inverse of the calculated FCS (non-inverted CRC-16) is appended to the packet causing a
FCS er r or. This bit i s i gnor ed if t r ansmit FCS processi ng is disabled (TF P D = 1).
Bit 4: Transmit Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag sequence (7Eh).
When 1, inter-fram e fill i s done with all ‘1’s.
Bit 3: Transmit Bit Reorderi ng Enabl e (TBRE) – When 0, bit reor der ing i s di sabl ed ( The first bit transmitted is the
LSB of the Transmit FI FO Data byte TFD[0]). When 1, bit r eor deri ng is enabled (T he first bi t transmitted i s the M S B
of the Transmit FIFO Data byte TFD[7]).
Bit 2: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data is directly output from packet
processi ng. When 1, the out going data is i nv erted before being output from pac k et proc essing.
Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not a FCS is calculated and
appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet.
When 1, the pack et i s tr ansmit ted wi thout a FCS.
Bit 0: T ran smit FIF O Reset (TF RST) – W hen 0, t he Transmi t FIF O will resum e norm al operati ons, ho wever, dat a
is discarded until a start of packet is received after RAM power-up is completed. When 1, the Transmit FIFO is
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 258 of 305
em ptied, any transfer in pr ogr es s i s halted, the FI FO RA M is powered down, and all inc omi ng data is di scarded (al l
TF DR r egister wri tes are ignored) .
Register Name:
TH256CR2
Register Description:
Transmit HDLC-256 Tra nsmit Control Regist er 2
Register A ddr es s:
1501h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
TDAL4
TDAL3
TDAL2
TDAL1
TDAL0
Default
0
0
0
0
1
0
0
0
Bits 4 to 0: Transmit HDLC Data Storage Available Level (TDAL[4:0]) – These five bits i ndicate the minimum
number of bytes ([TDAL*8]+1) that must be available for storage (do not contain data) in the Transmit FIFO for
HDLC data storage t o be avail able. F or ex ampl e, a value of 21 (15h) resul ts in HDLC dat a storage bei ng av ailabl e
(THDA = 1) when the Transmit FIFO has 169 (A9h) bytes or more available for storage, and HDLC data storage
not bei ng av ail able (THDA = 0) when the T ran smit FIFO has 168 ( A8h) byt es or l ess av ail abl e for storage. Default
v alue ( aft er r eset) is 128 byt es minimum available.
Register Name:
TH256FDR1
Register Description:
Transmit HDLC-256 FIFO Data Regi st er 1
Register A ddr es s:
1502h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
--
--
TDPE
Default
0
0
0
0
0
0
0
0
Bit 0: Tran smit FIFO Data Packet En d (TDP E) – W hen 0, the Transmit FIFO dat a is not a packet end. W hen 1,
the Transmit FIFO data i s a packet end. Thi s bit should be writ ten bef ore the l ast byt e of t he packet is wri tt en int o
TH256FDR2.
Register Name:
TH256FDR2
Register Description:
Transmit HDLC-256 FIFO Data Regi st er 2
Register A ddr es s:
1503h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TFD7
TFD6
TFD5
TFD4
TFD3
TFD2
TFD1
TFD0
Default
0
0
0
0
0
0
0
0
When read, the value of these bits i s al ways zero.
Bits 7 to 0: Transmit FIFO Data (TFD[7:0]) – These eight bits are the packet data to be stored in the Transmit
FIFO. TFD[7] is the MSB, and TF D[0] is the LS B . If bit reordering is di sabl ed, TFD[0] is the first bit tr ansmit ted, and
TFD[7] is the last bit transmitted. If bit reordering is enabled, TFD[7] is the first bit transmitted, and TFD[0] is the
last bit transmit ted.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 259 of 305
Register Name:
TH256SR1
Register Description:
Transmit HDLC-256 Status Regist er 1
Register A ddr es s:
1504h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
TFF
TFE
THDA
Bit 2: Transmit FIFO Full (TFF) – When 0, the Transmit FIFO contains 255 or less bytes of data. W hen 1, the
Transmit FIFO is full.
Bit 1: T ransmit FIFO Empty (TFE) – W hen 0, the Transmit FIFO cont ains at l east one byt e of data. When 1, the
Transmit FI F O is emp ty.
Bit 0: Transmit HDLC Data Storage Available (THDA) – When 0, the Transmit FIFO has less storage space
available in the Transmit FIFO than the Transmit HDLC data storage available level (TDAL[4:0]). When 1, the
Transmit FIFO has the same or m or e stor age space available than the Transmit FIFO HDLC data stor age availabl e
level.
Register Name:
TH256SR2
Register Description:
Transmit HDLC-256 Status Regist er 2
Register A ddr es s:
1505h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFFL5
TFFL4
TFFL3
TFFL2
TFFL1
TFFL0
Bits 5 to 0: Transmit FIFO Fill Level (TFFL[5:0]) – These six bits indicate the number of eight byte groups
available for storage (do not contain data) in the Transmit FIFO. E.g., a v alue of 21 (15h) indicates the FIFO has
168 (A8h) to 175 (AFh) bytes are avail able for stor age.
Register Name:
TH256SRL
Register Description:
Transmit HDLC-256 Status Regist er Latched
Register A ddr es s:
1506h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFOL
TFUL
TPEL
--
TFEL
THDAL
Bit 5: Tr a ns m it FIFO Ov e r flow Lat c hed ( TF OL) – This bit is set when a Transmit FIFO ov erflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL) – This bit is set when a Transmit FIFO underflow condition
occurs. An under flow condition result s in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL) – This bit is set when an end of packet is read from the Transmit
FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL) – Thi s bit is set when the TFE bi t t r ansi tions fr om 0 to 1.
Note: Thi s bit is al so set when TH256CR1.T FRST is deasserted.
Bit 0: T ran smit HDLC Dat a Avail abl e Lat ched (T HDAL) – Thi s bit is set when the T HDA bi t transi ti ons f rom 0 to
1. Note: T his bi t is also set wh en TH256CR1.T FRST is deasserted.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 260 of 305
Register Name:
TH256SRIE
Register Description:
Transmit HDLC-256 Status Regist er In t errupt En able
Register A ddr es s:
1508h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
TFOIE
TFUIE
TPEIE
--
TFEIE
THDAIE
Default
0
0
0
0
0
0
0
0
Bit 5: Tr a ns m it FIFO Ov e r flow In te r r upt Enable (TF OIE) – This bit enables an int er r upt if the TFO L bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE) – This bit enables an inter r upt if the TFUL bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 3: Tran smit Packet End Interrupt Enab le (TPEI E ) – This bit enabl es an i nterrupt if the TP E L bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – Thi s bit enables an interrupt if t he TFFL bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 1: Tr a ns m it FIFO Em pt y In t e r r upt Ena ble (TFEIE) – This bit enables an interrupt if the TFEL bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 0: T ransmi t HDLC Data Availab le Interru pt Enable (T HDAIE ) – T his bit enabl es an interrupt if t he THDAL bit
is set.
0 = interrupt di sabl ed
1 = interrupt enabled
10.8.2 Receive HDLC-256 Register Definitions
Table 10-31. Receive Side HDLC-256 Register Map
ADDRESS
REGISTER
REGISTER DESCRIPTION
1510h
RH256CR1
Receive HDLC-256 Control Register 1
1511h
RH256CR2
Receive HDLC-256 Control Register 2
1512h
--
Unused
1513h
--
Unused
1514h
RH256SR
Receive HDLC-256 Status Regi ster
1515h
--
Unused
1516h
RH256SRL
Receive HDLC-256 Status Regi ster Latched
1517h
Unused
1518h
RH256SRIE
Receive HDLC-256 Status Register Interrupt Enable
1519h
--
Unused
151Ah
--
Unused
151Bh
--
Unused
151Ch
RH256FDR1
Receive HDLC-256 FIFO Dat a Register 1
151Dh
RH256FDR2
Receive HDLC-256 FIFO Dat a Register 2
151Eh
--
Unused
151Fh
--
Unused
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 261 of 305
Register Name:
RH256CR1
Register Description:
Receive HDL C-256 Control Register 1
Register A ddr es s:
1510 + ( 20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
RBRE
RDIE
RFPD
RFRST
Default
0
0
0
0
0
0
0
0
Bit 3: Receive Bi t Reordering Enable ( RBRE) – When 0, bit r eordering i s disabled (The fi rst bit r ec eived is in the
LSB of t he Rec eive FIF O Data byte RFD[0]). When 1, bit reor der ing is enabl ed ( The f irst bit received is i n the MSB
of t he Rec eiv e FIFO Dat a byte RFD[7]).
Bit 2: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for packet
processi ng. When 1, the incomi ng data is i nv erted before being passed on for packet processing.
Bit 1: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have a
FCS appended) . When 1, FCS processing is disabled (the packets do not have a FCS appended) .
Bit 0: Receive FI FO Reset ( RFRST) – When 0, the Rec eive FIFO will resum e normal operations, however, data is
discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the RHDA bit is forced low, and all
inc omi ng data i s di scarded.
Register Name:
RH256CR2
Register Description:
Receive HDL C-256 Control Register 2
Register A ddress:
1511h+ (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
RDAL4
RDAL3
RDAL2
RDAL1
RDAL0
Default
0
0
0
0
1
0
0
0
Bits 4 to 0: Receive HDLC Data Avail able Level (RDAL[4:0]) – These fiv e bit s indicate the minimum number of
eight byte groups that must be stored (contain data) in the Receive FIFO before HDLC data is considered to be
available (RHDA=1). For example, a value of 21 (15h) results in HDLC data being available when the Receive
FIFO contains 168 (A8h) bytes or mor e.
Register Name:
RH256SR
Register Description:
Receive HDL C-256 S t at us Register
Register A ddr es s:
1514h+ (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
RFF
RFE
RHDA
Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When 1, the
Receive FIFO is fu ll.
Bit 1: Receive FIFO Empty (RFE) – When 0, the Receive FIFO contains at least one byte of data. W hen 1, the
Receive FIFO is e mpty.
Bit 0: Receive HDLC Data Available (RHDA) – When 0, the Receive FIFO contains less data than the Receiv e
HDLC data available level (RDAL[4:0]). When 1, the Receive FIFO contains the same or more data than the
Receive HDLC data available lev el.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 262 of 305
Register Name:
RH256SRL
Register Description:
Receive HDL C-256 S t at us Re gister Latched
Register A ddr es s:
1516h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RFOL
--
--
RPEL
RPSL
RFFL
--
RHDAL
Bit 7: Receive FIFO Overflow Latched (RFOL) – T his bit i s set when a Receiv e FIFO overfl ow conditi on occurs.
An overflow condition result s i n a loss of data.
Bit 4: Receive Packet End Latched (RP EL) – This bit is set when an end of packet is stored in the Rec eive FIFO.
Bit 3: Receive Packet Start L at ched (RPSL) – This bit is set when a star t of packet is st or ed in the Receive FIFO.
Bit 2: Receive FIF O Full Latched (RFFL) – This bit is set when t he RFF bit transit ions f r om 0 to 1.
Bit 0: Receive HDLC Data Available Latched (RHDAL) – This bit is set when the RHDA bit transitions from
0 to 1.
Register Name:
RH256SRIE
Register Description:
Receive HDL C-256 S t at us Register Interrupt Enabl e
Register A ddr es s:
1518h + (20h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RFOIE
--
--
RPEIE
RPSIE
RFFIE
--
RHDAIE
Default
0
0
0
0
0
0
0
0
Bit 7: Receive FIF O O verflow Interrupt Enable (RFOIE) – This bi t enables an interrupt if the RFOL bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 4: Receive Packet End Interrup t Enabl e ( RP EIE ) – T his bit enables an inter r upt if the RPE L bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Receive Packet Start Int errupt En abl e ( RP SIE ) – Thi s bi t enables an inter r upt if the RP S L bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 2: Receive FIF O Full In t errup t Enabl e ( RFFIE ) – This bit enables an i nterr upt if the RFFL bit is set.
0 = interrupt di sabl ed
1 = interrupt enabled
Bit 0: Receive HDL C Data Avail abl e Interru pt Enable (RHDAIE) – Thi s bit enabl es an int errupt if the RHDAL bi t
is set and.
0 = interrupt di sabl ed
1 = interrupt enabled
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 263 of 305
Register Name:
RH256FDR1
Register Description:
Receive HDL C-256 FIFO Data Register 1
Register A ddr es s:
151Ch + (20h x (n-1) ) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
RPS2
RPS1
RPS0
RFDV
Default
0
0
0
0
X
X
X
0
Note: The FIFO data and status are updated when the Receive FIFO Data (RH256F DR2.RFD[7:0] ) is read.
Reading this regist er will r eflect the status of the next read of RH256F DR2.
Bits 3 to 1: Receive Packet St atus (RPS[2:0]) – These three bits indicat e the status of t he receiv ed packet and
packet data.
000 = pac k et middle
001 = pac k et start.
010 = r eserved
011 = r eserved
100 = pac k et end: good pac k et
101 = pac k et end: FCS er r or ed pac k et.
110 = pac k et end: inv alid packet (a non-integer num ber of bytes).
111 = pac k et end: abor ted packet.
Bit 0: Receive FI FO Data Valid ( RFDV) – W hen 0, the Receive FIFO data (RFD[7:0]) i s i nv alid (the Rec eive FIFO
is empty ). When 1 , the Receive FIFO data (RFD[7:0]) is valid.
Register Name:
RH256FDR2
Register Description:
Receive HDL C-256 FIFO Data Register 2
Register A ddr es s:
151Dh + (20h x (n-1) ) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
RFD7
RFD6
RFD5
RFD4
RFD3
RFD2
RFD1
RFD0
Default
X
X
X
X
X
X
X
X
Note: Reading this regist er when RH256FDR1. RFDV=0 may result i n a l oss of data.
Bits 7 to 0: Receive FIFO Data (RFD[7:0]) – These eight bits are the packet data stored in the Receive FIFO.
RFD[ 7] is the MSB, and RFD[ 0] is the LS B. If bit reorderi ng i s disabled, RFD[0] is the fir st bit receiv ed, and RFD[7]
is the last bit received. If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit
received.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 264 of 305
11. FUNCTION AL TIMING
11.1 T1 Receiver Functional Timing Diagrams
Figure 11-1. T1 Receiv e-S ide D4 Timin g
Figure 11-2. T1 Re ceiv e-S ide ESF Ti m in g
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
RSYNCn3
RSYNCn
1
RFSYNCn
RSYNCn2
NOTE 1: RSYNCn IN THE FRAME MODE ( RIOCR. 0 = 0 ) AND DOUBLE-WIDE FRAME SY NC IS NOT ENA BLED ( RIOCR.1 = 0).
NOTE 2: RSYNCn IN THE FRAME MODE ( RIOCR. 0 = 0 ) AND DOUBLE-WIDE FRAME SY NC IS E NAB LED (RIOCR.1 = 1 ).
NOTE 3: RSYNCn IN THE MULTIFRAME MODE (RIOCR.0 = 1).
1
2
3
4
5
6
7
8
9
10
11
12
RFSYNCn
FRAME#
RSYNCn1
RSYNCn2
RSYNCn3
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
NOTE 1: RSYNCn IN THE FRAME MODE ( RIOCR. 0 = 0 ) AND DOUBLE-WIDE F RAME SY NC IS NOT ENA BLED ( RIOCR.1 = 0).
NOTE 2: RSYNCn IN THE FRAME MODE ( RIOCR. 0 = 0 ) AND DOUBLE-WIDE FRAME SY NC IS E NAB LED (RIOCR.1 = 1 ).
NOTE 3: RSYNCn IN THE MULTIFRAME MODE (RIOCR.0 = 1).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 265 of 305
Figure 11-3. T1 Receiv e-Side Boundary Timing (Elastic Store Disabled)
Figure 11-4. T1 Receiv e-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
CHANNEL 23
CHANNEL 24
CHANNEL 1
CHANNEL 23
CHANNEL 24
CHANNEL 1
RCLKn
RSERn
RSYNCn
RFSYNCn
RSIGn
RCHCLKn
RCHBLKn1
B
A
C/A
D/B
A
C/A
D/B
LSB
F
MSB
MSB
LSB
A
B
N OTE 1:
RCHBLKn I S P RO G RAMME D T O BL OCK CHANNEL 24.
RSERn
CHANNEL 23
CHANNEL 24
CHANNEL 1
RCHCLKn
RCHBLK3
RSYSCLKn
RSYNCn2
RSYNCn1
RMSYNCn
RSIGn
LSB
F MSB
MSB
LSB
CHANNEL 23
CHANNEL 24
CHANNEL 1
B
A
C/A
D/B
A
C/A
D/B
A
B
NOTE 1: RSYNCn IS IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 2: RSYNCn IS IN THE INPUT MODE (RIO CR.2 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNE L 24 .
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 266 of 305
Figure 11-5. T1 Receiv e-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSERn1
CHANNEL 1
RCHCLKn
RCHBLKn4
RSYSCLKn
RSYNCn3
CHANNEL 31
CHANNEL 32
RSYNCn2
RMSYNCn
RSIGn
CHANNEL 31
CHANNEL 32
B
A
C/A
D/B
C/A
D/B
A
B
CHANNEL 1
LSB
MSB
LSB
NOTE 1: RSERn DATA IN CHANNELS 1, 5, 9, 13, 1 7, 21 , 25, AND 2 9 ARE FORCED TO ONE.
NOT E 2: RSYNCn IS IN THE OUT PUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIO CR.2 = 1).
NOTE 4: RCHBLK n IS P RO GRAM ME D T O BL OCK CHANNEL 1.
NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-S IDE EL ASTIC STO R E.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 267 of 305
Figure 11-6. T1 Receiv e-Side Interleave Bus Operation—BYTE Mode
RSERn
LSB
RSYSCLKn
RSYNCn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
RSERn1
RSYNCn
RSIGn1
RSERn2
RSIGn
2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
A
B
C
D
A
B
C
D
A
B
C
D
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIO CR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, RCHCLKn CONTINUES TO MARK THE CHANNE L LSB F O R THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, RCH
BLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 268 of 305
Figure 11-7. T1 Receiv e-Side Interleave Bus Operation—FRAME Mode
Figure 11-8. T1 Receiv e-Side RCHCLKn Gapped Mode During F-Bit
RCLKn
RCHCLKn
RSYNCn
RSERn
LSB
F-BIT
MSB
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
RSERn
LSB
RSYSCLKn
RSYNCn
3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
RSERn
1
RSYNCn
RSIGn1
RSERn2
RSIGn2
BIT DETAIL
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, RCHCLKn CONTINUES TO MARK THE CHANNE L LSB F O R THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, RCHBLKn CONTI NUES TO MARK THE BL O CKE D CHANNE L S FO R T HE F RAM ER’S ACTIVE PERI OD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 269 of 305
11.2 T1 Tran sm itter Function al Tim in g D iagram s
Figure 11-9. T1 Transmit-S ide D4 Tim ing
Figure 11-10. T1 Tr an sm it-Side ESF Timing
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5
TSSYNCIOn
FRAME#
TSYNCn1
TSYNCn2
TSYNCn3
NOTE 1: TS YNCn IN THE FRAME MODE (T IOCR.0 = 0) AND DOUB L E-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0).
NOTE 2: TSYNCn IN THE FRAM E MO DE (T IOCR.0 = 0) AND DOUB L E-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1).
NOTE 3: TS YNCn IN THE MULTIF RAME MODE (TIO CR.0 = 1).
1
2
3
4
5
6
7
8
9
10
11
12
TSSYNCIOn
FRAME#
TSYNCn1
TSYNCn2
TSYNCn3
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
NOTE 1: TS YNCn IN THE FRAME MODE (T IOCR.0 = 0) AND DOUB L E-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0).
NOTE 2: TSYNCn IN THE FRAME MODE (TIOCR. 0 = 0) AND DOUB LE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1).
NOTE 3: TS YNCn IN THE MULTIF RAME MODE (TIO CR.0 = 1).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 270 of 305
Figure 11-11. T1 Tr an sm it-Side Boundary Timing (Elastic Store Disabled)
Figure 11-12. T1 Tr an sm it-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
LSB
F
MSB
LSB
MSB
LSB
MSB
CHANNEL 1
CHANNEL 2
CHANNEL 1
CHANNEL 2
A
B
C/A
D/B
A
B
C/A
D/B
TCLKn
TSERn
TSYNCn1
TSYNCn2
TSIGn
TCHCLKn
TCHBLKn3
D/B
NOTE 1: TSYNCn IS IN THE O UTPUT MODE (TIOCR. 2 = 1).
NOTE 2: TS YNCn IS IN THE INPUT MODE (TIOCR. 2 = 0).
NOTE 3: TCHBLKn IS PROG RAMMED TO BLOCK CHANNEL 2.
LSB
F
MSB
LSB
MSB
CHANNEL 1
CHANNEL 24
A
B
C/A
D/B
A
B
C/A
D/B
TSYSCLKn
TSERn
TSSYNCIOn
TSIGn
TCHCLKn
TCHBLKn1
CHANNEL 23
A
CHANNEL 23
CHANNEL 24
CHANNEL 1
NOTE 1: TCHBLKn IS PROG RAMMED TO BLOCK CHANNEL 24.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 271 of 305
Figure 11-13. T1 Tr an sm it-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
LSB
F3
LSB
MSB
CHANNEL 1
CHANNEL 32
A
B
C/A
D/B
A
B
C/A
D/B
TSYSCLKn
TSERn1
TSSYNCIOn
TSIGn
TCHCLKn
TCHBLKn2
CHANNEL 31
A
CHANNEL 31
CHANNEL 32
CHANNEL 1
NOTE 1: TSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.
NOTE 2: TCHBLKn IS PROG RAMMED TO BLOCK CHANNELS 31 AND 1.
NOTE 3: THE F-BIT POS IT ION FOR TH E T1 FRAME IS SAMPLED AND PASSED THROUGH T HE T RANSM IT -SIDE
ELASTIC STO RE I NTO THE MSB BIT POSITION OF CHANNEL 1. (NORMA L LY THE T RANSMIT -SIDE FORMATTER
OVERWRITES T HE F-BIT POSITION UNLE SS THE FORM ATTER IS PROGRAM ME D T O PASS T HRO UGH THE F -BIT
POSITION).
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 272 of 305
Figure 11-14. T1 Tr an sm it-Side Interleave Bus Operation—BYTE Mode
TSERn
LSB
TSYSCLKn
TSSYNCIOn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
TSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
TSERn1
TSSYNCIOn
TSIGn1
TSERn2
TSIGn2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NO TE 3: TS SYNCIOn IS IN T HE INP UT MODE (T IOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, T CHCLKn CONTINUES TO MA RK THE CHANNEL LSB FOR THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, T CHBLKn CONTI NUES TO MARK T HE B L OCKED CHANNELS FOR THE FRAM ER’S A CT IVE PE RIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 273 of 305
Figure 11-15. T1 Tr an sm it-Side Interleave Bus Operation—FRAME Mode
Figure 11-16. T1 Tr an sm it-Side TCHCLKn Gapped Mode During F-Bit
TCLKn
TCHCLKn
TSYNCn
TSERn
LSB
MSB
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
TSERn
LSB
TSYSCLKn
TSSYNCIOn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
TSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
TSERn1
TSSYNCIOn
TSIGn1
TSERn
2
TSIGn2
BIT DETAIL
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: TS SY NCIOn IS IN T HE INPUT MODE (T IOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, T CHCLKn CONTINUES TO MA RK THE CHA NNEL LSB FOR THE FRAMER' S ACTIVE PERIOD.
NOTE 5: THOUGH NOT SHO WN, T CHBLKn CONTI NUES TO MARK T HE B L OCKED CHANNELS FOR THE FRAM ER’S A CT IVE PE RIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 274 of 305
11.3 E1 Receiver Functional Timing Diagrams
Figure 11-17. E1 Receive-S ide Timing
Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled)
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
RSYNCn2
RSYNCn1
RFSYNCn
NOTE 1: RSYNCn IN FRA ME MODE (RIOCR.0 = 0).
NOTE 2: RSYNCn IN MULT IFRAME MODE (RIOCR.0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
CHANNEL 32
CHANNEL 1
CHANNEL 2
CHANNEL 32
CHANNEL 1
CHANNEL 2
RCLKn
RSERn
RSYNCn
RFSYNCn
RSIGn
RCHCLKn1
RCHBLKn1
C
D
A
LSB
MSB
A
B
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
B
Note 3
NOTE 1: RCHBLK n IS P RO GRAM ME D T O BL OCK CHANNEL 1.
NOTE 2: SHOWN IS AN RNAF FRA ME BOUNDA RY.
NOTE 3. RSIGn NORMAL LY CONTAI NS THE CAS MULT IFRAME ALIG NME NT NIBB LE (0000) IN CHANNEL 1.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 275 of 305
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RSERn1
CHANNEL 23/31
CHANNEL 24/32
CHANNEL 1/2
RCHCLKn
RCHBLKn4
RSYSCLKn
RSYNCn3
RSYNCn2
RMSYNCn
LSB
F
MSB
MSB
LSB
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FRO M THE E 1 LI NK IS
MA PP ED TO CHANNE L 1 OF T HE T1 LI NK, ET C.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE).
NOTE 2: RSYNCn IN THE OUTP UT MODE (RIOCR.2 = 0).
NOTE 3: RSYNCn IN THE INP UT MO DE (RIOCR.2 = 1).
NOTE 4: RCHBLK n IS PROGRAMMED TO BLOCK CHANNEL 24.
RSERn
CHANNEL 1
RCHCLKn
RCHBLKn3
RSYSCLKn
RSYNCn2
CHANNEL 31
CHANNEL 32
RSYNCn1
RMSYNCn
RSIGn
CHANNEL 31
CHANNEL 32
C
D
A
B
CHANNEL 1
LSB
MSB
LSB
MSB
C
D
B
A
Note 4
NOTE 1: RSYNCn IN THE OUTP UT MODE (RIOCR.2 = 0).
NOTE 2: RSYNCn IN THE INP UT MO DE (RIOCR.2 = 1).
NOTE 3: RCHBLK n IS P RO GRAM ME D T O BL OCK CHANNEL 1.
NOTE 4: RSIGn NORMAL LY CONTAI NS THE CAS MULT IFRAME ALIG NME NT NIBB LE (0000) IN CHANNEL 1.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 276 of 305
Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode
RSERn
LSB
RSYSCLKn
RSYNCn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
RSERn1
RSYNCn
RSIGn1
RSERn2
RSIGn
2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
A
B
C
D
A
B
C
D
A
B
C
D
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: RSYNCn IS IN THE INPUT MODE (RIO CR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, RCHCLKn CONTINUES TO MARK THE CHANNE L LSB F O R THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, RCHBLKn CONTI NUES TO MARK THE BL O CKE D CHANNE L S FOR THE FRAMER’S ACTIVE PERIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 277 of 305
Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode
Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1
RCLKn
RSYNCn
RCHCLKn
RSERn
LSB
F
F
F
F
F
F
F
F
MSB
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
RSERn
LSB
RSYSCLKn
RSYNCn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
RSERn
1
RSYNCn
RSIGn1
RSERn2
RSIGn2
BIT DETAIL
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: RSYNC IS IN THE I NPUT M O DE (RIOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, RCHCLK CONTI NUES TO MARK T HE CHANNEL LSB FOR THE FRAMER' S A CTI VE PERIOD.
NOTE 5: THOUGH NOT SHO WN, RCHBLK CONTINUES TO MARK THE BLO CKED CHANNELS F OR THE F RAMER’S ACTIVE PE RIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 278 of 305
11.4 E1 Tran smi tter Fun ction al Timing Diagrams
Figure 11-24. E1 Tr an smi t-Side Timing
Figure 11-25. E1 Tr an smi t-Side Boundary Timing (Elastic Store Disabled)
1
2
3
4
5
6
7
8
9
10
11
12
TSSYNCIOn
FRAME#
TSYNCn1
TSYNCn2
13
14
15
16
1
2
3
4
5
14
15
16
6
7
8
9
10
NO TE 1: TS YNCn IN FRAME MO DE (TIOCR.0 = 0).
NOTE 2: TS YNCn IN MULTIF RAME MO DE (TIOCR. 0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME.
LSB
MSB
LSB
MSB
CHANNEL 1
CHANNEL 2
CHANNEL 1
CHANNEL 2
A
B
C
D
TCLKn
TSERn
TSYNCn1
TSYNCn2
TSIGn
TCHCLKn
TCHBLKn3
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
D
NOTE 1: TS YNCn IN THE OUTP UT MO DE (T IOCR.2 = 1).
NOTE 2: TS YNCn IN THE INP UT MO DE (TIO CR.2 = 0).
NOTE 3: TCHBLKn IS PROG RAMMED TO BLOCK CHANNEL 2.
NOTE 4: THE SIGNA LING DATA AT TSIGn DURING CHANNE L 1 IS NORMA L LY OVERWRITTEN IN THE TRANSM IT
FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 5: SHOWN IS A TNAF FRAM E B O UNDARY.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 279 of 305
Figure 11-26. E1 Tr an smi t-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 11-27. E1 Tr an smi t-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
LSB
F
MSB
LSB
MSB
CHANNEL 1
CHANNEL 24
TSYSCLKn
TSERn1
TSSYNCIOn
TCHCLKn
TCHBLKn2
CHANNEL 23
NOTE 1: THE F-BIT P OSITION IN THE TSERn D ATA IS IGNORED.
NOTE 2: TCHBLKn IS PROG RAMMED TO BLOCK CHANNEL 24.
TSERn
CHANNEL 1
TCHCLKn
TCHBLKn2
TSYSCLKn
TSYNCn1
CHANNEL 31
CHANNEL 32
TSIGn
CHANNEL 31
CHANNEL 32
C
D
A
B
CHANNEL 1
LSB
MSB
LSB
MSB
C
D
B
A
NOTE 1: TS YNCn IN THE INP UT MO DE (TI OCR.2 = 0).
NOTE 2: TCHBLKn IS PROG RAMMED TO BLOCK CHANNEL 1.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 280 of 305
Figure 11-28. E1 Tr an smi t-Side Interleave Bus Operation—BYTE Mode
TSERn
LSB
TSYSCLKn
TSSYNCIOn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
TSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
TSERn1
TSSYNCIOn
TSIGn1
TSERn2
TSIGn2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
NOTE 1: 4.096MHz BUS CONFIGURA TI ON.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: TS SY NCIOn IS IN T HE INPUT MODE (T IOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, T CHCLKn CONTINUES TO MA RK THE CHANNEL LSB FOR THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, T CHBLKn CONTI NUES TO MARK T HE B L OCKED CHANNELS FOR THE FRAM ER’S A CT IV E PE RIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 281 of 305
Figure 11-29. E1 Tr an smi t-Side Interleave Bus Operation—FRAME Mode
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
TSERn
LSB
TSYSCLKn
TSSYNCIOn3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
TSIGn
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
TSERn1
TSSYNCIOn
TSIGn1
TSERn2
TSIGn2
BIT DETAIL
A
B
C/A
D/B
A
B
C/A
D/B
A
B
C/A
D/B
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
NOTE 1: 4. 096MH z BUS CONF IGURAT ION.
NOTE 2: 8.192MHz BUS CONFIGURA TI ON.
NOTE 3: TS SY NCIOn IS IN T HE INPUT MODE (T IOCR.2 = 0).
NOTE 4: THOUGH NOT SHO WN, T CHCLKn CONTINUES TO MA RK THE CHANNEL LSB FOR THE FRAME R'S ACTIVE PE RIOD.
NOTE 5: THOUGH NOT SHO WN, T CHBLKn CONTI NUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 282 of 305
Figure 11-30. E1 G.802 Timing
Figure 11-31. E1 Tr an smi t-Side TCHCLKn Gapped Mode During Channel 1
TCLKn
TSYNCn
TCHCLKn
TSERn
LSB
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
31
32
TS#
RSYNCn
TSYNCn
RCHCLKn
TCHCLKn
RCHBLKn
TCHBLKn
CHANNEL 26
CHANNEL 25
LSB
MSB
RCLKn/RSYSCLKn
TCLKn/TSYSCLKn
RSERn/TSERn
RCHCLKn/TCHCLKn
RCHBLKn/TCHBLKn
1
2
0
NOTE: RCHBLKn O R TCHB LKn P ROG RAM ME D T O PULSE HIG H DURING T IME SLOTS 1 THROUGH 15, 17
THROUGH 2 5, AND BI T 1 OF TIME SLOT 2 6.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 283 of 305
12. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Vol tage Range on Any Lead with Respect to VSS ( except V DD)…………………………………………….-0.3V to +5.5V
Suppl y V oltage (VDD) Range with Respect to VSS…………………………………………………………..-0.3V to +3.63V
Operating Te mperature Range…..………………………………………………………………...-40°C t o +85° C (Note 1)
Storage Temperature Range...………………………………………………………………………………-55°C to +125°C
Soldering Tem per ature (reflow)
CSBG A l ead( P b) -free ............................................................................................................................ +260°C
CSBGA containing lead(Pb)................................................................................................................... +240°C
This i s a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operation
sec tions of this specif icat ion is not im p l ie d. Expos ur e to a bs olut e maxim um rating conditions for extended periods of time may affect reliability.
Not e 1: Specifications to -40° C are guar ant eed b y des ig n (GBD ) and not product i on tested .
Table 12-1. Recommended DC Operating Conditions
(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Logic 1 VIH
2.0 5.5 V
Logic 0 VIL
-0.3 +0.8 V
I/ O Supply VDD
3.135 3.3 3.465 V
Core Supply VDD-CORE
1.71 1.8 1.89 V
Table 12-2. Capacitance
(TA = +25°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capac itance CIN
7 pF
Out put Capacitanc e COUT
7 pF
Table 12-3. Recommended DC Operating Conditions
(VDD = 3.135V to 3.465V, TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
3.3V S upply Current IDD (Notes 1, 2) 215 250 mA
1.8V Cor e S upply Current IDD-CORE (Notes 1, 2) 45 60 mA
Input Leak age IIL -10.0 +10.0 µA
Pull up Pi n Input Leakage IILP (Note 3) -85.0 +10.0 µA
Pull down Pi n Input Leakage IILP (Note 3) -10.0 +85.0 µA
Three-State Output Leakage IOL -10.0 +10.0 µA
Output Voltage (IOH = -4mA) VOH 2.4 V
Output Voltage (IOL = +4mA) VOL 0.4 V
Not e 1: RCLK1-n = TCLK1-n = 2.048MHz, digital outputs without load.
Not e 2: M ax p ow er consumed is measured with all p orts trans m ittin g an al l-ones dat a p attern wi th a tr ans m itter l oad of 1 00Ω.
Not e 3: Pullup/pulldown pins include SPI_SEL, TSY SCLK[2:8 ], RSYSCLK[2:8], DIGIOEN, JTRST, JTMS, and JTDI.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 284 of 305
12.1 Thermal Characteristics
Table 12-4. Therm al Char acter istics
PARAMETER CONDITIONS MIN TYP MAX UNITS
Ambient Temperature (Not e 1) -40 +85 °C
Junction Temperature +125 °C
Theta-JA (θJA) in Still Ai r for 256-Pin TE-CSBGA (Not e 2) +17.5 °C/W
Not e 1: The package is mounted on a four-layer JEDEC standard test board.
Not e 2:
Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer J EDEC standard test
board.
12.2 Line Interface Characteristics
Table 12-5. Transm itter Character istic s
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Mark Amplitude Vm
E1 75
Ω
2.13
2.37
2.61
V
E1 120
Ω
2.70
3.00
3.30
T1 100
Ω
2.40
3.00
3.60
J1 110
Ω
2.40
3.00
3.60
Output Zero Amplitude Vs (Note 1) -0.3 +0.3 V
Transmit Amplitude Var iation wit h
Supply -1 +1 %
Table 12-6. Receiver Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Cable A tt enuation Attn 43 dB
All owable Zeros Before Loss
(Note 1)
192
192
2048
All owable Ones Bef or e Loss
(Note 2) 24
192
192
Not e 1:
192 zeros for T1 and T1.231 Specifica tion Compliance. 192 zeros for E1 and G.775 Spe cification Compliance. 2048 zeros for
ETS 300 233 compliance.
Not e 2:
24 ones in 19 2-bit pe riod fo r T1.231; 192 ones for G.775; 192 ones for ETS 300 233.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 285 of 305
13. AC TIMING CHARACTERISTICS
Unless otherwi se noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
13.1 Microprocessor Bus AC Characteristics
13.1.1 SPI Bus Mode
Table 13-1. SPI Bus Mode Timing
(See Figure 13-1.)
SYMBOL
(Not e 1)
CHARACTERISTIC (Note 2) SYMBOL MIN MAX UNITS
Operating Frequency
Slave
fBUS(S) 5 MHz
t1 Cycle Time: Slave tCYC(S) 200 ns
t2 Enable Lead Time tLEAD(S) 15 ns
t3 Enable Lag Time tLAG(S) 15 ns
t4, t5
Cloc k ( CLK ) Duty Cycle
Slave (t4/t1 or t5/t1)
tCLKH(S) 80 ns
t6
Data Setup Time (Input s)
Slave
tSU(S) 5 ns
t7
Data Hold Tim e (Inputs)
Slave tH(S) 15 ns
t8 Disable Time, Sl av e ( Note 3) tDIS(S) 25 ns
t9
Data Valid Time, After Enabl e Edge
Sl av e ( Note 4)
tV(S) 40 ns
t10
Data Hold Time, Outputs, After Enable Edge
Slave
tHD(S) 5 ns
Not e 1: Symbols refer to dimensions in Figure 13-1.
Not e 2: 100pF load on all SPI pins.
Not e 3: Hold time to high-impedance state.
Not e 4: With 100pF on all SPI pins.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 286 of 305
Figure 13-1. SPI Interface Timing Diagram
NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AND CPOL SETTIN GS. SEE THE FUNCTIONAL
TIMING DIAGRAMS.
NOTE 2: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED.
CSB
INPUT
SPI_SCLK
SPI_SCLK
1
MOSI
INPUT
MISO
OUTPUT
MSB
BITS
13:0
SLAVE
MSB
BITS 6:1
NOTE 2
BIT 14
t1
t4
t5
t2
t3
SLAVE
LSB
t8
t6
t7
t9
t10
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 287 of 305
Table 13-2. AC Characteristics—M icr oproc essor Bus Timing
(VDD = 3.3V ±5% , TA = -40°C to +85°C.) (See Figure 13-2, Figure 13-3, Figure 13-4, and Figure 13-5.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for A[12:0] Valid t o CSB
Active t1 0 ns
Setup Time for CSB Active to E ither RDB,
or WRB Active t2 0 ns
Delay Time f r om Eit her RDB or DSB
A ct ive t o D[7:0] Valid t3 (Note 1) 175 ns
Hold Time f r om Eit her RDB or WRB
Inac tive to CSB Inactive t4 0 ns
Hold Time fro m CSB or RDB or DSB
Inactive to D[7:0] Three-State t5 5 20 ns
Wa it Time from WRB Active to Latch Data t6 40 ns
Data Setup Time to WRB Inactive t7 10 ns
Data Hold Time from WRB Inactive t8 2 ns
Address Hold from WRB Inactive t9 0 ns
Write Access to Subsequ ent Write/Read
Access Delay Tim e t10 (Note 1) 30 ns
Not e 1: If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 288 of 305
Figure 13-2. Intel Bus Read Timing (BTS = 0)
Figure 13-3. Intel Bus Write Timing (BTS = 0)
t2
t3
Address Valid
Data Valid
t4
t9
t5
t10
A[12:0]
D[7:0]
CSB
RDB
WRB
t1
t2
t6
Address Valid
t4
t9
t10
A[12:0]
D[7:0]
CSB
RDB
WRB
t7
t8
t1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 289 of 305
t2
t6
Address Valid
t4
t9
t10
A[12:0]
D[7:0]
CSB
RWB
DSB
t7
t8
t1
Figure 13-4. Motorola Bus Read Timing (BTS = 1)
Figure 13-5 Motorola Bus Write Timing (BTS = 1)
t2
t3
Address Valid
Data Valid
t4
t9
t5
t10
A[12:0]
D[7:0]
CSB
DSB
RWB
t1
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 290 of 305
Table 13-3. Receiver AC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-6, Figure 13-7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RCLKn Period tCP (Note 1) 648 ns
(Note 2) 488
RCLKn Pulse Width tCH 125 ns
t
CL
125
RSYSCLK n P eri od tSP (Note 3) 60 ns
(Note 4) 60
RSYSCLKn Pulse Width tSH 30 ns
tSL 30
RSYNCn Setup to RSYSCLKn Falling tSU 10 ns
RSYNCn Puls e Width tPW 50 ns
Delay RCLK n to RSERn, RSIG n V alid tD1 10 ns
Delay RCLK n to RCHCLKn,
RSYNCn, RCHB LK n, RF S Y NCn tD2 20 ns
Delay RS Y S CLK n to RSERn, RSIGn
Valid tD3 20 ns
Delay RS Y S CLK n to RCHCLKn,
RCHBLKn, RM S Y NCn, RSY NCn tD4 20 ns
Not e 1:
T1 Mode.
Not e 2:
E1 M od e.
Not e 3:
RSYSCL Kn = 1. 5 4 4MHz.
Not e 4: R SYSCL Kn = 2. 0 4 8MHz.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 291 of 305
Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)
t
D1
t
D2
RSERn/RSIGn
RCHCLKn
RCHBLKn
RSYNCn1
RCLKn
RFSYNCn/RMSYNCn
F-BIT
t
D2
t
D2
t
D2
NOTE 1: RSYNCn IS IN THE OUTPUT MODE.
NOTE 2: NO RELATIONSHIP BETWEEN RCHCLKn AND RCHBLKn AND OTHER SIGNALS IS IMPLIED.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 292 of 305
Figure 13-7. Receive-Side Timin g—Elastic Store Enabled (T1 Mode)
NOTE 1: RSYNCn IS IN THE OUTPUT MODE.
NOTE 2: RSYNCn IS IN THE INPUT MODE.
NOT E 3: F-BIT W HEN RI O CR.4 = 0, MSB OF TS0 WHE N RIOCR.4 = 1.
t
D3
t
D4
t
D4
t
D4
t
t
SU
HD
RSERn/RSIGn
RCHCLKn
RCHBLKn
RSYNCn1
RSYNCn2
RSYSCLKn
SL
t
t
SP
SH
t
t
D4
RMSYNCn
SEE NOTE 3
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 293 of 305
Table 13-4. T ransmit AC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-8, Figure 13-9, and Figure 13-10.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TCLKn P eri od tCP
(Note 1)
648
ns
(Note 2)
488
TCLKn Pulse Width
tCH
125
ns
tCL
125
TSYSCLKn Period tSP
(Note 3)
60
ns
(Note 4)
60
TSYSCLKn Puls e Width
tSH
30
ns
t
SL
30
TSYNCn or TSSYNCIOn Setup to
TCLKn or TSY S CLK n Falling
tSU 10 ns
TSYNCn or TSSYNCIOn Pu lse Width tPW ( Note 5) 50 ns
TSSYNCIOn Puls e Width (Notes 6, 7) tPW
488
ns
244
122
61
TSE Rn, T SIGn Set up to T CLK n,
TSYSCLKn Falling tSU 10 ns
TSERn, TSIGn Hold from TCLKn,
TSYSCLKn Falling tHD 10 ns
Delay TCLKn to TCHB LK n, T CHCLK n,
TSYNCn tD2 20 ns
Delay TSYSCLKn to TCHCLKn,
TCHBLKn tD3 20 ns
Delay B P CLK 1 to TSSYNCIOn tD5 (Note 6) 5 ns
Not e 1: T1 Mode.
Not e 2:
E1 M od e.
Not e 3:
RSYSCL Kn = 1. 5 4 4MHz.
Not e 4:
RSYSCL Kn = 2. 0 4 8MHz.
Not e 5: TSSYNCIOn configured as an input (GTCR3.1 = 0).
Not e 6:
T SS YNCIOn c onfig ur ed as an output (GTCR3.1 = 1).
Not e 7:
Varies depending on the frequency of BPCLK1.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 294 of 305
Figure 13-8. Transmit Formatter Timing—Backplane
TCLKn
TSERn/TSIGn
TCHCLKn
t
t
CL
t
CH
CP
TSYNCn1
TSYNCn
2
TCHBLKn
t
D2
t
D2
t
D2
t
t
t
SU
HD
D1
t
HD
TESO
t
SU
NOTE 1: TS YNCn IS IN THE OUTPUT MODE .
NOTE 2: TS YNCn IS IN THE INPUT MODE.
NOTE 3: TSERn IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 4: TCHCLKn AND T CHBLKn ARE SY NCHRO NO US WIT H TCLK WHEN T HE TRANSMIT -SIDE ELASTIC STORE IS DISABLED.
NOTE 5: NO RELATIONSHIP BETWEEN TCHCLKn AND TCHBLKn AND THE OTHER SIGNALS IS IMPLIED.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 295 of 305
Figure 13-9. Transmit Formatter Timing—Elastic Store Enabled
Figure 13-10. BPCLK1 Tim ing
BPCLK1
TSSYNCIOn1
t
D5
NOTE 1: TSSYNCIOn IS CONFIGURED AS AN OUTPUT (GTCR3.TSSYNCIOSEL = 1).
TSYSCLKn
TSERn
TCHCLKn
t
t
SL
t
SH
SP
TSSYNCIOn
TCHBLKn
t
D3
t
D3
t
t
t
SU
HD
SU
t
HD
NOTE 1: TSERn IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLKn WHEN THE TRANSMIT-S ID E EL ASTIC STO R E IS ENA BLED.
NOTE 2: TCHCLKn AND T CHBLKn ARE SY NCHRO NO US WITH TSYSCLKn WHEN THE T RANSMIT-SIDE ELASTIC STORE IS ENABLED.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 296 of 305
13.2 JTAG Interface Timin g
Table 13-5. JTAG Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-11.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTCLK Clock Period t1 1000 ns
JTCLK Cloc k High:Low Time t2:t3 ( Note 1) 50 500 ns
JTCLK to JTDI , JTMS Setup Time t4 5 ns
JTCLK to JTDI , JTMS Hold Time t5 2 ns
JTCLK to JTDO Delay t6 2 50 ns
JTCLK to JTDO High-Impedance Delay t7 2 50 ns
JTRST W idth Low Time t8 100 ns
Not e 1:
Clock can be stopped high or low.
Figure 13-11. JT AG Interface Timing Diagram
JTCLK
t1
JTD0
t4
t5
t2
t3
t7
JTDI, JTMS, JTRST
t6
JTRST
t8
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 297 of 305
14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT
The DS26514 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and
EXTEST . Optional publ ic instructi ons included are HI GHZ , CLAMP, and IDCO DE. See Table 14-1. T he DS26514
contains the following as required by IE EE 1149. 1 Standar d Test Access Port and Boundar y S c an A rchit ec ture.
Test Access Port (TAP)
TAP Controller
Instruc tion Register
Bypass Regi ster
Boundary S c an Register
Device Identification Regis ter
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details.
Figure 14-1. JTAG Functio nal Block Diagram
JTDI
JTMS
JTCLK
JTRST
JTDO
TEST ACCESS PORT
CONTROLLER
V
DD
V
DD
V
DD
BOUNDRY S CA N
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
IDENTIFICATION
REGISTER
MUX
SELECT
OUTPUT ENABLE
10kΩ
10kΩ
10kΩ
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 298 of 305
14.1 TAP Controller State Machine
The TAP controll er is a fi nit e state machine t hat responds to t he logic lev el at JTMS on t he rising edge of JTCLK.
See Figure 14-2.
14.1.1 Test-Logic-Reset
Upon power-up, the TAP Controller will be in the Test-Logic-Reset state. The instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
14.1.2 Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register and test
registers will remain idle.
14.1.3 Select-DR-Scan
All test regi sters ret ain t hei r previ ous stat e. W ith J TMS LOW , a ri sing edge of JT CLK moves the control ler i nto the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the
contr oller to the S elec t-IR-Scan state.
14.1.4 Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the Test Register remains at its
current v alue. On the rising edge of JTCLK, the controll er goes to the Shif t-DR state if JTMS is LOW or it goes to
the Exi t1-DR state if JTMS is HIGH.
14.1.5 Shift-DR
The test dat a register selected by the current i nstructi on is connected bet ween JTDI and JTDO and wil l shift data
one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instr uc tion is not plac ed in the serial path, i t maintai ns i ts previous state.
14.1.6 Exit1-DR
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the
scanning process if JTMS i s HIGH. A ri sing edge on JTCLK wit h JTMS LOW puts the cont roll er in t he Pause-DR
state.
14.1.7 Pause-DR
Shift ing of t he test registers i s hal ted whil e in thi s state. All test registers selected by the current instr uction r etain
their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS
HIG H puts the cont r oller in the Exit2-DR stat e.
14.1.8 Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and
terminates the scanning pr oc es s. A ri si ng edge on J TCLK wit h JTM S LOW enters the Shift-DR stat e.
14.1.9 Update-DR
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
14.1.10 Select-IR-Scan
All test registers retain their previous state. The instruction register remains unchanged during this state. With
JTM S LOW , a rising edge on JTCLK moves the controll er into the Capture-IR stat e and initiat es a scan sequence
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 299 of 305
f or the instruct i on register. JTMS HIGH duri ng a rising edge on JTCLK put s the contr oller back int o the T est-Logic-
Reset state.
14.1.11 Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on t he ri sing edge of JT CLK. If JTMS is HIG H on the ri sing e dge of JT CLK, t he contr oll er ent ers the Exit 1-
IR stat e. If JTMS is LOW on the rising edge of JTCLK , the cont r oller enter s the Shift-IR state.
14.1.12 Shift-IR
In this state, the shift register in the instructi on regi ster is connect ed between JTDI and JTDO and shif ts data one
stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers,
remains at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the Exit1-IR
state. A rising edge on JTCLK with JTMS LOW keeps the controller in the Shift-IR state while moving data one
stage through the instr uc tion shift regi ster .
14.1.13 Exit1-IR
A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-IR state. If JTMS is HIGH on the rising
edge of JT CLK, the cont r oller enters the Update-IR state and terminates the scanning process.
14.1.14 Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK puts the
contr oller in t he Exit 2-IR st ate. The controll er r em ains in the P ause-IR state if JTMS is LOW during a rising edge on
JTCLK.
14.1.15 Exit2-IR
A rising edge on JTCLK with JTMS LOW puts the controller in the Update-IR state. The controller loops back to
Shift-IR if JTMS i s HIGH during a rising edge of JT CLK in this state.
14.1.16 Update-IR
The i nstructi on code shift ed i nto the instruct i on shift register is latc hed i nto the parall el output on t he falli ng edge of
JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising
edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller
enters the S elect-DR-Scan state.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 300 of 305
Figure 14-2. TAP Controller State Diagram
1
0
01
1 1
1
1
1
11
1 1
11 0 0
00
0
1
00
00
11
00
00
Select
DR-Scan
Capture DR
Shift DR
Exit DR
Pause DR
Exit2 DR
Update DR
Select
IR-Scan
Capture IR
Shi ft IR
Ex i t IR
Pause IR
Ex i t2 IR
Update IR
Test Logic
Reset
Run Test/
Idle
0
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 301 of 305
14.2 Instruction Register
The instructi on r egister cont ains a shift r egister as well as a latched paral lel output and is 3 bits in length. When the
TAP controller enter s the S hift-IR state, the instr uc tion shif t register is connected between JTDI and J TDO. Whi le in
the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage towards the serial output at
JTDO. A risi ng edge on JTCLK in the Exit1-IR state or the Exit2-IR stat e with JTMS HIGH moves the controller to
the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS26514 and its respective operational binary codes are
shown in Table 14-1.
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SELECTED REGIST ER INST RUCTI ON CODES
SAMPLE:PRELOAD
Boundary S c an
010
BYPASS
Bypass
111
EXTEST
Boundary S c an
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
14.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the Boundary Scan Register without interfering with the normal
operation of the dev ic e by usi ng the Capture-DR state. SAMPLE:PRE LOAD also allows the dev ic e to shift data i nto
the boundary scan register via JTDI using the Shift-DR state.
14.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit Bypass Test Register. This allows data to pass from JTDI to JTDO without affecting the device’s normal
operation.
14.2.3 EXTEST
Thi s allows testi ng of all int erconnections to t he devi ce. W hen the EXTEST i nstruction is latched in the i nstructi on
regi ster, t he f ollowing act i ons occur. O nce enabl ed v ia the Updat e-IR state, the par all el output s of all di git al output
pins will be driven. The Boundary Scan Register will be connect ed between JTDI and JTDO . The Capt ure-DR wi l l
sample al l digital inputs i nto t he Boundary S c an Register.
14.2.4 CLAMP
All digital outputs of the device will output data from t he boundary scan paral lel output whil e c onnec ting the By pas s
Register between JT DI and JTDO. The outputs will not change during the CLAMP instruction.
14.2.5 HIGHZ
All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected
between JTDI and JTDO.
14.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a “1” in the LSB posi tion. The next 11 bits identify the manufacturer’s JEDE C number and
num ber of continuation bytes f ollowed by 16 bit s for the device and 4 bit s for the versi on.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 302 of 305
14.3 JTAG ID Codes
Table 14-2. ID Code Structure
DEVICE REVISION
ID[31:28] DEVI CE CODE
ID[27:12] MANUFACTURER’S CODE
ID[11:1] REQUIRED
ID[0]
DS26519
Consult factory
0000000010001011
00010100001
1
DS26518
Consult factory
0000000010001010
00010100001
1
DS26514
Consult factory
0000000010001100
00010100001
1
14.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register, the Identification Register, has been included with the DS26514 design. The Identification
Register is used i n c onjuncti on with the IDCODE i nstr uction and the Test-Logic-Reset state of the TAP cont r oller .
14.4.1 Boundary Scan Register
This register c ontains both a shift register path and a latc hed par allel output for all c ontrol c ells and digi tal I/O cell s,
and is n bits i n length.
14.4.2 Bypass Register
This register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instr uc tions, pr ov iding a short path between JTDI and JTDO.
14.4.3 Identification Register
The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset stat e.
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 303 of 305
15. PIN CONFIGURATION
15.1 Pin Configuration—256-B all TE-CSBGA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A TTIP1 TTIP1 TRING1 RSYNC1 TCHBLK1/
TCHCLK1 TSIG2 REFCLKIO A11 A7 A1 A
B ATVDD1 ATVSS1 TRING1 TSYNC1/
TSSYNCIO1 RCHBLK2/
RCHCLK2 RSYNC2 MCLK A10 A8 A2 ATVSS ATVDD B
C RTIP1 RRING1 SPI_SEL/
AL/RSIGF/
FLOS1
RMSYNC1/
RFSYNC1 TCLK1 RMSYNC2/
RFSYNC2 TCHBLK2/
TCHCLK2 A12 A6 A0 C
D ARVDD1 ARVSS1 CLKO/
RLF/LTC1 RSIG1 TSIG1 RSER2 TCLK2 DIGIOEN A5 ARVSS ARVDD D
E ARVDD2 ARVSS2 RSYSCLK2/
RLF/LTC2 RCHBLK1/
RCHCLK1 RSER1 RSIG2 TSER2 BPCLK1 A4 ARVSS ARVDD E
F RTIP2 RRING2 TSYSCLK2/
AL/RSIGF/
FLOS2 RCLK1 JTCLK TSER1 TSYNC2/
TSSYNCIO2
A9 A3 F
G ATVDD2 ATVSS2 TRING2 RCLK2 DVDD33 DVDD33 DVDD18 DVDD18 DVDD18 DVDD18 DVDD33 DVDD33 ATVSS ATVDD G
H TTIP2 TTIP2 TRING2 JTDI DVDD33 DVDD33 ACVDD DVDD33 DVDD33 DVDD33 DVDD33 DVSS SCANMODE
H
J TTIP3 TTIP3 TRING3 JTDO RESREF DVSS ACVSS DVSS DVSS DVSS DVSS RESETB J
K ATVDD3 ATVSS3 TRING3 JTMS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS ATVSS ATVDD K
L RTIP3 RRING3 TSYSCLK3/
AL/RSIGF/
FLOS3 RCLK3 JTRST RCHBLK3/
RCHCLK3 TCHBLK3/
TCHCLK3 TCLK4 D1/
SPI_MOSI RSYSCLK1 TXENABLE/
SCAN_EN L
M ARVDD3 ARVSS3 RSYSCLK3/
RLF/LTC3 RCLK4 RSIG3 TSYNC3/
TSSYNCIO3
TSYNC4/
TSSYNCIO4
RDB/
DSB D5/
SPI_SWAP BTS ARVSS ARVDD M
N ARVDD4 ARVSS4 RSYSCLK4/
RLF/LTC4 RSER3 RSYNC3 RSER4 TSER4 D0/
SPI_MISO D6/
SPI_CPHA TSSYNCIO ARVSS ARVDD N
P RTIP4 RRING4 TSYSCLK4/
AL/RSIGF/
FLOS4
RMSYNC3/
RFSYNC3 TCLK3 RMSYNC4/
RFSYNC4 TCHBLK4/
TCHCLK4 D2/
SPI_SCLK TSYSCLK1 P
R ATVDD4 ATVSS4 TRING4 TSER3 RSIG4 TSIG4 WRB/
RWB D4 INTB ATVSS ATVDD R
T TTIP4 TTIP4 TRING4 TSIG3 RCHBLK4/
RCHCLK4 RSYNC4 CSB D3 D7/
SPI_CPOL T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 304 of 305
16. PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note t hat a “+” , “#”, or “-” in the pac k age c ode indic at es Ro HS status only . Package dr awi ngs may sho w a different
suffix character , but the drawing pert ains to the package regardl ess of RoHS status.
PA CKA GE TYPE PACKAGE CODE OUTLINE NO. L AND PATTERN NO.
256 CSBG A X256T-1 21-0315 90-0291
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 305 of 305
Max im c a nnot as s u me responsib ility for use o f a ny circ u itr y ot her th a n circ u itr y e nt ir e ly em bod ied in a M axi m pr oduct . No circu it p atent licens es
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integra ted Products Maxim is a regis ter ed trad em ark of Ma xi m Int egrat ed P r oduc t s .
17. DOCUMENT REVISION HISTORY
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
022007
New Product Release.
1 041307
Updated dat a sheet to reflec t new feat ur es with B 1 die revision:
HDLC-256 Controll er – introduc ed in Section 9.10 and described in S ec tion
9.10.3
Ext ended B E RT Registers – introduced in Section 9.13 and defined in S ection
10.6.1
2
103007
Added more content to T CLK n pin description in Section 8.1.
3 101608
Final iz ed the specifi c ations i n this document and removed “pr elimi nar y”
designation.
Rem ov ed c ommerci al temperatur e range product option fr om Orderi ng
Inf ormation t able ( page 1) and Operating Paramet er s (Section 12).
In t he A bsol ute Maxim um Ratings portion of Section 12, added Note 1 stati ng
that specif icati ons to -40°C ar e guaranteed by desi gn ( GBD) and not product ion
tested.
Reduced the maxim um supply c ur r ent f or the 1.8v supply from 70m A to 60mA.
Incr eased the typi c al suppl y c urrent s for the 3.3v and 1.8v suppl ies to 215mA
and 45m A, r espect ively.
Added definition for Receive Master Mode Register bit 5 (RMMR. 5) which, when
set, disables the receive-side synchronizer in the framer. This feature is new with
revision B1.
Added i nstr uc tion in Step 5 of the Exam ple Dev ic e Init ializ ation and Sequence
(Section 9.4. 1) to incr ease the frequency of the internally generat ed cl oc k which
is s upplied to the framers.
Replac ed pac k age dr awing with link to pack age dr awing ( S ec tion 16).
4 5/11
Correct TTIP and TRING pi n identif ication in Figure 15.1 FROM: TTI P 3 pins J3,
K3, TRING3 pi ns J1, J2 TO: TTIP3 pins J1, J2, T RING3 pins J3, K 3. Remov ed
reference to TSYS CLK 8 at C14. Changed table format to improv e r eadability.
Sect ion 12 Operating P ar am eters added l ead and lead-free r eflow temperatures.
Table 8-1 Pin Func tion Descr iptions the f ollowing note was added to pin names
RDB/DSB and WRB/RWB: Note: If SPI mode is select ed by the S PI_S E L pin, t his
pin m ust be c onnec ted thr ough a 10K ohm r esi stor to the I/O S upply .
