1 of 12
FEATURES
Int egr at es NV SRAM, Rea l-Time C lo ck,
Crystal, Power-Fail Con trol Circuit an d
Lithium Energy Source
Clock Register s ar e Accessed I dentica l ly to
t he Static RAM. T hese Regist er s ar e
Re sid ent in the Eight Top RAM L oc a tions
T otally Nonvolatile with Over 10 Year s of
Operatio n in the Absence of Po wer
BCD-Co ded Year , Month, Dat e, Day, Hours,
Minutes, and Seconds wit h Leap Year
Compensation Valid Up to 2100
Power-F ail Write Protection Allows f or
±10% VCC Power S u pply T oleran ce
DS1646 only (DIP Mo dule)
St andard JEDEC Bytewide 128k x 8 RAM
Pinout
DS1646P Only (P owerCap Module Bo ard)
Sur face Mo unt ab le Package for Direct
Connection to PowerCap Containing
Ba tte ry and C rys tal
Rep laceab le Battery ( P owerCap)
Power-Fail Output
Pin-for-Pin C ompa tible with Other Densities
of DS164xP Timekeeping RAM
Underwrit er s La bo r at or ies (UL) Recogn ized
PIN CONFIGURATIONS
ORDERING INFORMATION
PART
VOLTAGE
RANGE (V)
TEMP RANGE PIN-PACKAGE TO P MARK
DS1646-120+
5.0
0°C to +70°C
32 EDIP (0. 740a)
DS1646+120
DS1646P-120+
5.0
0°C to +70°C
34 PowerCap*
DS1646P+120
+Denotes a lead(Pb)-free/RoHS-com p lia nt pac ka ge.
*DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
A “+" indicates a lead(Pb)-f r ee produc t . Th e t op m ark w ill includ e a “+ " sy mbo l on le ad (Pb)-free devices.
1
N.C.
2
3
A15
A16
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
N.C.
A14
33
32
31
30
29
28
27
26
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
N.C.
X1 GND VBAT X2
34-Pin P owerC ap Mod ule Boa rd
(Us es DS9034PCX+ or DS9034I-PCX+ PowerCap)
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
32-Pin Encapsulated Package
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
N.C.
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
N.C.
DQ2
GND
15
16
18
17
DQ4
DQ3
DS1646/DS1646P
Nonvolatile Timekeeping RAM
www.maxim-ic.com
19-5595; Rev 10/10
DS1646/DS1646P
2 of 12
PIN DESCRIPTION
PIN
NAME FUNCTION
PDIP
PowerCap
1, 30
1, 33, 34
N.C.
No Connect ion
2
3
A16
Address Input
3
32
A14
4
30
A12
5
25
A7
6
24
A6
7
23
A5
8
22
A4
9
21
A3
10
20
A2
11
19
A1
12
18
A0
25
29
A11
26
27
A9
27
26
A8
28
31
A13
13
16
DQ0
Data Input/O utput
14
15
DQ1
15
14
DQ2
17
13
DQ3
18
12
DQ4
19
11
DQ5
20
10
DQ6
21
9
DQ7
16
17
GND
Ground
22
8
CE
Active-Low Chip Enable
23
28
A10
Address Input
24
7
OE
Active-Low Output Enable
29
6
WE
Active-Low Write Enabl e
31
2
A15
Address Input
32
5
VCC
Power-Supply I nput
— 4 PFO
Active-Low Power-Fail Output, Open Drain. Requires a pullup
resistor for proper operatio n.
—
X1, X2,
VBAT
Crys tal C onnection, VBAT Batt er y Co nnection
DS1646/DS1646P
3 of 12
DESCRIPTION
The DS1646 is a 128k x 8 nonvolatile static RAM wit h a full-function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
mont h, date, day, hour s, minutes, and seconds dat a in 24-hour BCD format. Correct ions for the day of the
month and leap year ar e made automat ically. The RT C c lock r egist er s ar e dou ble-buffered to avo id acces s
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time lo ss as the timekeep ing countdown continues unabated by access to t ime register dat a. T he DS1646
also contains its own power-fail c ircuit ry, whic h deselect s the device when t he VCC supply is in an out-of-
to lerance cond ition. Th is featur e pr eve nt s loss of data from unpredict able s yst em o per atio n brought o n by
low VCC as err ant access a nd update cycles are avoided.
PACKAGES
The DS1646 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
Power Cap Modu le Board is desig ned w it h co nt acts for connection t o a separ ate Power Cap ( DS 90 34PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1646P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process preve nt s damage t o t he cr yst al and bat tery du e to t he h ig h t emperatures required for s older
r eflow. T he Pow e rCa p is k eyed to prevent reve rse inser tion. The Power Cap Modu le Bo ar d and Power Cap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered r egist er str u ctu r e r edu ces the cha nce of reading inco r r ect dat a, inter nal updates
to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
co unt, that is da y, dat e, and time that was present at t he mo me nt the ha lt co mmand was issu ed. Ho wever ,
t he int er na l clock reg ist ers o f t he doub le-buffer ed syste m co nt inue t o update so that clo ck accur acy i s no t
affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock
st atu s is reset. Upd ating is wit h in a seco nd after t he read bit is wr it ten to 0.
DS1646/DS1646P
4 of 12
BLOCK DIAGRAM DS1646 Figure 1
TRUTH TABLE DS1646 Table 1
VCC
CE
OE
WE
MODE DQ POWER
5V ± 10%
VIH
X
X
DESELECT
HIGH-Z
STANDBY
X
X
X
DESELECT
HIGH-Z
STANDBY
VIL
X
VIL
WRITE
DATA I N
ACTIVE
V
IL
V
IL
V
IH
READ
DATA OUT
ACTIVE
VIL
VIH
VIH
READ
HIGH-Z
ACTIVE
<4.5 V >VBAT
X
X
X
DESELECT
HIGH-Z
CMOS STANDBY
<VBAT X X X DESELECT HIGH-Z
DAT A RETENTION
MODE
SETTING THE CLOCK
The MSB Bit, B7 , of the cont rol r eg ist er is t he writ e bit . Sett ing t he wr it e bit to a 1, like t he read bit halt s
updat es to t he DS1646 reg ister s. The user can then lo ad them wit h the correct day, dat e and t ime dat a in
24-hour BCD for mat . Resetting the write bit t o a 0 then transfers those values t o the act u al clock cou nt er s
and allows nor mal operation to resu me.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock osc illat or may be stopp ed at any t ime. To increase the sh elf life, the o scillator can be t ur ne d off
to minimize current drain fro m t he batt ery. T he
OSC
bit is the MSB for t he second’s reg ist ers. Setting it
to a 1 stops the o sc illator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and
the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds
register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as condit ions for access
remain valid (i.e., CE low,
OE
low, and addr ess for seconds reg ist er r emain val id and stable).
DS1646/DS1646P
5 of 12
CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibr ated at the factor y by Dallas Se miconducto r using nonvolatile tuning elements, a nd does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information refer to
Appl icat ion Note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional informat ion refer to Application Note 58.
1646 REGISTER MAP—BANK1 Table 2
ADDRESS
DATA
FUNCTION
B7
B6
B5
B4
B3
B2
B1
B0
1FFFF
—
—
—
—
—
—
—
—
Year
00–99
1FFFE
X
X
X
—
—
—
—
—
Month
01–12
1FFFD
X
X
-
—
—
—
—
—
Date
01–31
1FFFC
X
FT
X
X
X
—
—
—
Day
01–07
1FFFB
X
X
—
—
—
—
—
—
Hour
00–23
1FFFA
X
—
—
—
—
—
—
—
Minutes
00–59
1FFF9 OSC
— — — — — — — Seconds 00–59
1FFF8
W
R
X
X
X
X
X
X
Control
A
OSC
= Sto p Bit
R = Read Bit
FT = Frequ ency Test
W = Wri t e Bit X = U nused
Note: All indicated “ X” bits are unused but must be set to “0” during writ e cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever
WE
(write enable) is high;
CE
(chip enable) is low. The
device architecture allow s ripp le-through access to any of the address locat ions in the NVSRAM. Valid
data will b e ava ilable a t t he DQ pins within tAA after the last address input is st able, pro viding t hat the CE
and
OE
access times and states are satisfied. If CE or
OE
access times are not met, valid data will be
available at the latt er o f chip-enable access (tCEA) or at output enable access t ime (tOEA). The state of the
data input /output pin s (D Q) is co nt rolled by
CE
and
OE
. If t he out put s are activat ed befo re t AA, the dat a
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
re ma in valid , o ut put dat a w ill re main va lid for o utp ut dat a ho ld time ( t OH) but will t he n go ind et er mina te
until the ne xt address access.
DS1646/DS1646P
6 of 12
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever
WE
and CE are in their act ive state. The start of a write is
refere nced to t he latt er occu rring high to lo w tr ansit io n o f
WE
and CE . T he add resse s mu st be he ld va lid
throughout the cycle. CE or
WE
must return inactive for a minimum of tWR prior to the initiation o f
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical applicat ion, t he OE sig na l will be hig h dur ing a wr it e cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to
WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on
WE
will then disable the outp uts tWEZ after
WE
go es active.
DATA RETENTION MODE
When V CC is within nominal lim its (VCC > 4. 5 vo lts) the DS164 6 can be accessed as described above wit h
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
inter nally by inhibit ing acce ss via t he CE s ig na l. At th is t ime t he p ow er-fail o ut p ut s ig na l (
PFO
) w ill be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
leve l of the int ernal bat tery supp ly, po wer input is switched fro m the VCC pin to the int ernal batt ery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
DS1646/DS1646P
7 of 12
ABSOLUTE MAXIMUM RATINGS
Voltage Range o n Any Pin Relat ive to Ground……………………………………………..-0.3V to +6.0V
Stor ag e T emperat ur e Range
EDIP..........………………………………….........................................……………-40°C to +85°C
PowerCap......…………………………………....................................……………-55°C to +125°C
Lead Temperature ( soldering, 10s) ……............................ ...................... ...................... ................... +2 6 0 °C
Note: EDIP is w ave or hand soldered only.
So ldering Te mperatur e (reflow, P ower Ca p ) .... ...................... ...................... ...................... ............... +260°C
This is a stre ss ra t i n g on l y and functional ope ration of the device at t hese or any other condi tions above those indicated in the
operation sec tions of thi s specific ation is not i mplied. Exposure to absolute maxi mum rat ing condit i ons for extended periods of
time may affect reliability.
OPERATING RANGE
RANGE
TEMPERATURE
VCC
Commercial
0°C to +70°C, Noncondensing
5V ±10%
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supp ly Volt age
VCC
4.5
5.0
5.5
V
1
Logic 1 Voltage A ll Inputs
V
IH
2.2
V
CC
+0.3
V
Logic 0 Voltage All Inputs
VIL
-0.3
0.8
V
DC ELECTRICAL CHARACTERISTICS (Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Average VCC Po wer S upply Curr ent
ICC1
85
mA
2, 3
TTL Standby Curr ent (
CE
=VIH)
ICC2 3 6 mA 2, 3
CM OS Sta ndby C urr e nt
(
CE
=VCC-0.2V) ICC3 2 4.0 mA 2, 3
Input Leakage Cur r ent (Any I nput)
I
IL
-1
+1
µA
Output Leakage Curr ent
I
OL
-1
+1
µ
A
Output Logic 1 Voltage
(IOUT = -1.0 mA)
VOH 2.4 V
Output Logic 0 Voltage
(IOUT = +2. 1 mA)
VOL 0.4 V
Power-Fail Volta g e
VPF
4.0
4.25
4.5
V
DS1646/DS1646P
8 of 12
AC ELECTRICAL CHARACTERISTICS (Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Re a d Cyc le Time
tRC
120
ns
Address Acces s Time
tAA
120
ns
CE Acc ess Time
t
CEA
120
ns
CE
Dat a Off Time
t
CEZ
40
ns
Output Enable Access Time
tOEA
100
ns
Output Enable Data O ff Time
t
OEZ
40
ns
Output Enable to DQ Low-Z
tOEL
5
ns
CE
to DQ Low-Z
t
CEL
5
ns
Output Ho ld from Address
t
OH
5
ns
Write Cycle Time
tWC
120
ns
A ddress Setup Time
tAS
0
ns
CE Pulse Widt h
t
CEW
100
ns
Address Ho ld from E nd of Wr ite
tAH1
5
ns
5
tAH2
30
ns
6
Write Pulse Width
tWEW
75
ns
WE
Dat a Off Time
t
WEZ
40
ns
WE
or
CE
I na ctive Time
t
WR
10
ns
Da ta Setup Time
tDS
85
ns
Dat a Ho ld Time Hig h
tDH1
0
ns
5
tDH2
25
ns
6
AC TEST CONDITIONS
I nput Levels: 0V to 3V
Tra nsition Ti mes: 5 ns
CAPACITANCE (TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Capac it ance o n All Pins (except DQ )
CI
7
pF
Capac it ance o n DQ P ins
CDQ
10
pF
AC ELECTRICAL CHARACTERISTICS
(POWER-UP/DOWN TIMING) (Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or
WE
at V
IH
before Power -Down tPD 0 µs
V
PF
(Max) to V
PF
(Min) V
CC
Fall Time
tF 300 µ
s
V
PF
(Min) to V
SO
V
CC
Fall Time
tFB
10
µs
V
SO
to V
PF
(Min) V
CC
Rise Time
tRB
1
µ
s
V
PF
(Min) to V
PF
(Max) V
CC
Rise Time
t
R
0
µs
Power-Up
tREC
15
35
ms
Expect ed Data Ret ent io n T ime
( Oscil la tor On)
tDR 10 years 4
DS1646/DS1646P
9 of 12
DS1646 READ CY CLE TIMING
DS1646 WRITE CYCLE TIMING
DS1646/DS1646P
10 of 12
POWER-DOWN/POWER-UP TIMING
OUTP UT LOAD
DS1646/DS1646P
11 of 12
NOTES:
1) All vo ltages ar e r eferenced to ground.
2) Typical value s ar e at 2 5°C and nomina l supp l ies.
3) Outputs are open.
4) Data retention time is at 25°C and is calculated from the date code on the device package. The date
co de XXYY is t he year followed by the week of the year in whic h t he de vice was manu factur ed. For
example, 9225 wo uld mean the 25th week o f 1992.
5) tAH1, tDH1 are me asur ed from
WE
going high.
6) tAH2, tDH2 are me asur ed from
CE
going high.
7) Real-Time Clock Modules (EDIP) can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source co nt ained wit hin do es no t exceed +85°C. Po st-solder c leaning with wat er washing techniques
is acc eptable, provided t hat ult raso nic vibr ation is not used.
I n addition, for the P ow e rCa p ve rs ion:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow or iented wit h t he la bel side up ( “l ive -bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder , apply flux to the pad, heat the lead fra me p ad and apply so lder. To remo ve
the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to
remov e solder.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
d ifferent suffix c haracter , but the drawing pertains to the package r egar dless of RoHS stat us.
PACKAGE TYPE PACK AG E CODE OU TLINE NO .
LAND
PATTERN NO.
32 EDIP MDF32+1 21-0245 —
34 PCAP PC2+6 21-0246 —
DS1646/DS1646P
12 of 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim and the Dallas logo are a registered trademark of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
10/10
Updated the Ordering Information table; updated the st or ag e, lead,
and soldering info rmatio n in the Absolute Maximum R atings section
1, 7