User's Manual 32 V850ES/JC3-H, V850ES/JE3-H User's Manual: Hardware RENESAS MCU V850ES/Jx3-H Microcontrollers V850ES/JC3-H PD70F3809 PD70F3810 PD70F3811 PD70F3812 PD70F3813 PD70F3814 PD70F3815 PD70F3816 PD70F3817 PD70F3818 PD70F3819 V850ES/JE3-H PD70F3820 PD70F3821 PD70F3822 PD70F3823 PD70F3824 PD70F3825 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.00 Sep, 2011 Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850ES/JC3-H and V850ES/JE3-H and design application systems using the V850ES/JC3-H and V850ES/JE3-H. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JC3-H and V850ES/JE3-H shown in the Organization below. Organization The manual of these products is divided into two volumes: Hardware (this volume) and Architecture (V850ES Architecture User's Manual). Hardware Architecture * Pin functions * Data types * CPU function * Register set * On-chip peripheral functions * Instruction format and instruction set * Flash memory programming * Interrupts and exceptions * Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/JC3-H and V850ES/JE3-H Read this manual according to the CONTENTS. To find the details of a register where the name is known Use APPENDIX B REGISTER INDEX. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual available separately. The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what: " field. Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the Note: Footnote for item marked with Note in the text bottom Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JC3-H and V850ES/JE3-H Document Name Document No. V850ES Architecture User's Manual U15943E V850ES/JC3-H, V850ES/JE3-H Hardware User's Manual This manual Documents related to development tools Document Name Document No. QB-V850ESJX3H In-Circuit Emulator U19170J QB-V850MINI, QB-V850MINIL On-Chip Debug Emulator U17638E QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E CA850 Ver. 3.20 C Compiler Package Operation U18512E C Language U18513E Assembly Language U18514E Link Directives U18515E PM+ Ver. 6.30 Project Manager U18416E ID850QB Ver. 3.40 Integrated Debugger Operation U18604E SM850 Ver. 2.50 System Simulator Operation U16218E SM850 Ver. 2.00 or Later System Simulator External Part User Open U14873E Interface Specification SM+ System Simulator RX850 Ver. 3.20 Real-Time OS RX850 Pro Ver. 3.21 Real-Time OS Operation U18601E User Open Interface U18212E Basics U13430E Installation U17419E Technical U13431E Task Debugger U17420E Basics U18165E Installation U17421E Task Debugger U17422E AZ850 Ver. 3.30 System Performance Analyzer U17423E PG-FP5 Flash Memory Programmer U18865E Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. EEPROM is a trademark of Renesas Electronics Corporation. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries, including the United States and Japan. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON is an abbreviation of The Real-Time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. CONTENTS CHAPTER 1 INTRODUCTION................................................................................................................. 21 1.1 General ...................................................................................................................................... 21 1.2 Features .................................................................................................................................... 25 1.3 Application Fields .................................................................................................................... 27 1.4 Ordering Information ............................................................................................................... 27 1.5 Pin Configuration (Top View).................................................................................................. 29 1.6 Function Block Configuration................................................................................................. 36 1.6.1 Internal block diagram.....................................................................................................................36 1.6.2 Internal units ...................................................................................................................................39 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 43 2.1 List of Pin Functions................................................................................................................ 43 2.2 Pin States .................................................................................................................................. 50 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins.......... 51 2.4 Cautions .................................................................................................................................... 55 CHAPTER 3 CPU FUNCTION ................................................................................................................ 56 3.1 Features .................................................................................................................................... 56 3.2 CPU Register Set...................................................................................................................... 57 3.2.1 Program register set .......................................................................................................................58 3.2.2 System register set .........................................................................................................................59 3.3 Operation Modes ...................................................................................................................... 65 3.3.1 Specifying operation mode..............................................................................................................65 3.4 Address Space ......................................................................................................................... 66 3.4.1 CPU address space ........................................................................................................................66 3.4.2 Wraparound of CPU address space ...............................................................................................67 3.4.3 Memory map ...................................................................................................................................68 3.4.4 Areas ..............................................................................................................................................70 3.4.5 Recommended use of address space.............................................................................................76 3.4.6 Peripheral I/O registers ...................................................................................................................79 3.4.7 Programmable peripheral I/O registers ...........................................................................................90 3.4.8 Special registers .............................................................................................................................91 3.4.9 Cautions..........................................................................................................................................95 CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 99 4.1 Features .................................................................................................................................... 99 4.2 Basic Port Configuration......................................................................................................... 99 4.3 Port Configuration ................................................................................................................. 102 4.3.1 Port 0 ............................................................................................................................................108 4.3.2 Port 1 ............................................................................................................................................113 4.3.3 Port 3 ............................................................................................................................................114 4.3.4 Port 4 ............................................................................................................................................121 4.3.5 Port 5 ............................................................................................................................................124 4.3.6 Port 6 (V850ES/JE3-H only) .........................................................................................................130 4.3.7 Port 7 ............................................................................................................................................133 4.3.8 Port 9 ............................................................................................................................................135 4.3.9 Port DL..........................................................................................................................................142 4.4 4.5 Port Register Settings When Alternate Function Is Used.................................................. 144 Cautions .................................................................................................................................. 149 4.5.1 Cautions on setting port pins.........................................................................................................149 4.5.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................152 4.5.3 Cautions on on-chip debug pins (V850ES/JC3-H only).................................................................152 4.5.4 Cautions on P56/INTP05/DRST pin..............................................................................................152 4.5.5 Cautions on P10 and P53 pins when power is turned on..............................................................152 4.5.6 Hysteresis characteristics .............................................................................................................152 CHAPTER 5 CLOCK GENERATION FUNCTION .............................................................................. 153 5.1 Overview ................................................................................................................................. 153 5.2 Configuration.......................................................................................................................... 154 5.3 Registers ................................................................................................................................. 156 5.4 Operation ................................................................................................................................ 161 5.4.1 Operation of each clock ................................................................................................................161 5.4.2 Clock output function ....................................................................................................................161 5.5 PLL Function .......................................................................................................................... 162 5.5.1 Overview .......................................................................................................................................162 5.5.2 Registers.......................................................................................................................................162 5.5.3 Usage ...........................................................................................................................................165 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA).............................................................. 166 6.1 Overview ................................................................................................................................. 166 6.2 Functions ................................................................................................................................ 166 6.3 Configuration.......................................................................................................................... 167 6.3.1 Pin configuration ...........................................................................................................................170 6.4 6.5 Registers ................................................................................................................................. 171 Operation ................................................................................................................................ 188 6.5.1 Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) ...........................................................194 6.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001)..................................................204 6.5.3 External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) .....................................212 6.5.4 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) ...............................................224 6.5.5 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) ..............................................................231 6.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101).....................................................240 6.5.7 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) .........................................257 6.5.8 Timer output operations ................................................................................................................262 6.6 Timer-Tuned Operation Function ......................................................................................... 263 6.6.1 Free-running timer mode (during timer-tuned operation) ..............................................................265 6.7 Simultaneous-Start Function ................................................................................................ 272 6.7.1 PWM output mode (simultaneous-start operation) ........................................................................273 6.8 Cascade Connection.............................................................................................................. 275 6.9 Selector Function ................................................................................................................... 280 6.10 Cautions .................................................................................................................................. 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB).............................................................. 282 7.1 Overview ................................................................................................................................. 282 7.2 Functions ................................................................................................................................ 282 7.3 Configuration.......................................................................................................................... 283 7.4 Registers ................................................................................................................................. 286 7.5 Operation ................................................................................................................................ 303 7.5.1 Interval timer mode (TAB1MD2 to TAB1MD0 bits = 000) .............................................................304 7.5.2 External event count mode (TAB1MD2 to TAB1MD0 bits = 001)..................................................313 7.5.3 External trigger pulse output mode (TAB1MD2 to TAB1MD0 bits = 010) .....................................322 7.5.4 One-shot pulse output mode (TAB1MD2 to TAB1MD0 bits = 011) ...............................................335 7.5.5 PWM output mode (TAB1MD2 to TAB1MD0 bits = 100) ..............................................................344 7.5.6 Free-running timer mode (TAB1MD2 to TAB1MD0 bits = 101).....................................................355 7.5.7 Pulse width measurement mode (TAB1MD2 to TAB1MD0 bits = 110) .........................................375 7.5.8 Triangular wave PWM mode (TAB1MD2 to TAB1MD0 bits = 111) ...............................................381 7.5.9 Timer output operations ................................................................................................................383 7.6 7.7 Timer-Tuned Operation Function/Simultaneous-Start Function ...................................... 384 Cautions .................................................................................................................................. 385 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) ................................................................. 386 8.1 Overview ................................................................................................................................. 386 8.2 Functions ................................................................................................................................ 386 8.3 Configuration.......................................................................................................................... 387 8.3.1 Pin configuration ...........................................................................................................................390 8.4 8.5 8.6 Registers ................................................................................................................................. 391 Timer Output Operations....................................................................................................... 412 Operation ................................................................................................................................ 413 8.6.1 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000).................................................................421 8.6.2 External event count mode (TT0MD3 to TT0MD0 bits = 0001).....................................................431 8.6.3 External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010).........................................441 8.6.4 One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) ..................................................454 8.6.5 PWM output mode (TT0MD3 to TT0MD0 bits = 0100)..................................................................461 8.6.6 Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) ........................................................470 8.6.7 Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) ............................................486 8.6.8 Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) .......................................492 8.6.9 Encoder count function .................................................................................................................494 8.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) .........................................................510 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) ............................................................................ 518 9.1 Overview ................................................................................................................................. 518 9.2 Configuration.......................................................................................................................... 519 9.3 Registers ................................................................................................................................. 521 9.4 Operation ................................................................................................................................ 523 9.4.1 Interval timer mode .......................................................................................................................523 9.4.2 Cautions........................................................................................................................................527 CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only)............................................. 528 10.1 Functional Overview .............................................................................................................. 528 10.2 Configuration.......................................................................................................................... 529 10.3 Control Registers ................................................................................................................... 533 10.4 Operation ................................................................................................................................ 543 10.4.1 System outline ..............................................................................................................................543 10.4.2 Dead-time control (generation of negative-phase wave signal).....................................................548 10.4.3 Interrupt culling function ................................................................................................................555 10.4.4 Operation to rewrite register with transfer function........................................................................562 10.4.5 TAA4 tuning operation for A/D conversion start trigger signal output............................................580 10.4.6 A/D conversion start trigger output function ..................................................................................583 CHAPTER 11 REAL-TIME COUNTER................................................................................................. 588 11.1 Functions ................................................................................................................................ 588 11.2 Configuration.......................................................................................................................... 589 11.2.1 Pin configuration ...........................................................................................................................591 11.2.2 Interrupt functions .........................................................................................................................591 11.3 Registers ................................................................................................................................. 592 11.4 Operation ................................................................................................................................ 607 11.4.1 Initial settings ................................................................................................................................607 11.4.2 Rewriting each counter during real-time counter operation...........................................................608 11.4.3 Reading each counter during real-time counter operation ............................................................609 11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation ......................................610 11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation ......................................611 11.4.6 Initial INTRTC2 interrupt settings ..................................................................................................612 11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation ......................................613 11.4.8 Initializing real-time counter ..........................................................................................................614 11.4.9 Watch error correction example of real-time counter ....................................................................615 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 619 12.1 Functions ................................................................................................................................ 619 12.2 Configuration.......................................................................................................................... 620 12.3 Registers ................................................................................................................................. 621 12.4 Operation ................................................................................................................................ 623 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 624 13.1 Function .................................................................................................................................. 624 13.2 Configuration.......................................................................................................................... 625 13.3 Registers ................................................................................................................................. 627 13.4 Operation ................................................................................................................................ 629 13.5 Usage....................................................................................................................................... 630 13.6 Cautions .................................................................................................................................. 630 CHAPTER 14 A/D CONVERTER ......................................................................................................... 631 14.1 Overview ................................................................................................................................. 631 14.2 Functions ................................................................................................................................ 631 14.3 Configuration.......................................................................................................................... 632 14.4 Registers ................................................................................................................................. 635 14.5 Operation ................................................................................................................................ 646 14.5.1 Basic operation .............................................................................................................................646 14.5.2 Conversion operation timing .........................................................................................................647 14.5.3 Trigger mode.................................................................................................................................648 14.5.4 Operation mode ............................................................................................................................650 14.5.5 Power-fail compare mode .............................................................................................................654 14.6 Cautions .................................................................................................................................. 659 14.7 How to Read A/D Converter Characteristics Table ............................................................ 663 CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) ............................ 667 15.1 Functions ................................................................................................................................ 667 15.2 Configuration.......................................................................................................................... 667 15.3 Registers ................................................................................................................................. 668 15.4 Operation ................................................................................................................................ 670 15.4.1 Operation in normal mode.............................................................................................................670 15.4.2 Operation in real-time output mode...............................................................................................670 15.4.3 Cautions........................................................................................................................................671 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 672 16.1 Features .................................................................................................................................. 672 16.2 Configuration.......................................................................................................................... 673 16.3 Mode Switching Between UARTC and Other Serial Interfaces ......................................... 675 16.3.1 Mode switching between UARTC0 and CSIF4 .............................................................................675 16.3.2 Mode switching between UARTC2 and CSIF3 .............................................................................676 16.3.3 Mode switching between UARTC3, I2C00 and CAN0....................................................................677 16.3.4 Mode switching between UARTC4, CSIF0, and I2C01 ..................................................................678 16.4 Registers ................................................................................................................................. 679 16.5 Interrupt Request Signals ..................................................................................................... 689 16.6 Operation ................................................................................................................................ 690 16.6.1 Data format ...................................................................................................................................690 16.6.2 SBF transmission/reception format ...............................................................................................692 16.6.3 SBF transmission..........................................................................................................................694 16.6.4 SBF reception ...............................................................................................................................695 16.6.5 UART transmission .......................................................................................................................696 16.6.6 Continuous transmission procedure..............................................................................................697 16.6.7 UART reception ............................................................................................................................699 16.6.8 Reception errors ...........................................................................................................................700 16.6.9 Parity types and operations...........................................................................................................702 16.6.10 Receive data noise filter ...........................................................................................................703 16.7 Dedicated Baud Rate Generator........................................................................................... 704 16.8 Cautions .................................................................................................................................. 712 CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) .................................................... 713 17.1 Mode Switching of CSIF and Other Serial Interfaces ......................................................... 713 17.1.1 CSIF4 and UARTC0 mode switching ............................................................................................713 17.1.2 CSIF0, UARTC4, and I2C01 mode switching ................................................................................714 17.1.3 CSIF3 and UARTC2 mode switching ............................................................................................715 17.2 Features .................................................................................................................................. 716 17.3 17.4 17.5 17.6 Configuration.......................................................................................................................... 717 Registers ................................................................................................................................. 720 Interrupt Request Signals ..................................................................................................... 727 Operation ................................................................................................................................ 728 17.6.1 Single transfer mode (master mode, transmission mode).............................................................728 17.6.2 Single transfer mode (master mode, reception mode) ..................................................................730 17.6.3 Single transfer mode (master mode, transmission/reception mode) .............................................732 17.6.4 Single transfer mode (slave mode, transmission mode) ...............................................................734 17.6.5 Single transfer mode (slave mode, reception mode).....................................................................736 17.6.6 Single transfer mode (slave mode, transmission/reception mode)................................................738 17.6.7 Continuous transfer mode (master mode, transmission mode).....................................................740 17.6.8 Continuous transfer mode (master mode, reception mode) ..........................................................742 17.6.9 Continuous transfer mode (master mode, transmission/reception mode) .....................................745 17.6.10 Continuous transfer mode (slave mode, transmission mode) ..................................................749 17.6.11 Continuous transfer mode (slave mode, reception mode)........................................................751 17.6.12 Continuous transfer mode (slave mode, transmission/reception mode)...................................754 17.6.13 Reception error ........................................................................................................................758 17.6.14 Clock timing..............................................................................................................................759 17.7 Output Pins ............................................................................................................................. 761 17.8 Baud Rate Generator ............................................................................................................. 762 17.8.1 Baud rate generation ....................................................................................................................763 17.9 Cautions .................................................................................................................................. 764 CHAPTER 18 I2C BUS .......................................................................................................................... 765 18.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 766 18.1.1 UARTC3 and I2C00 mode switching .............................................................................................766 18.1.2 UARTC4, CSIF0, and I2C01 mode switching ................................................................................767 18.2 18.3 18.4 18.5 Features .................................................................................................................................. 768 Configuration.......................................................................................................................... 769 Registers ................................................................................................................................. 773 I2C Bus Mode Functions ........................................................................................................ 788 18.5.1 Pin configuration ...........................................................................................................................788 18.6 I2C Bus Definitions and Control Methods ............................................................................ 789 18.6.1 Start condition ...............................................................................................................................789 18.6.2 Addresses .....................................................................................................................................790 18.6.3 Transfer direction specification .....................................................................................................791 18.6.4 ACK ..............................................................................................................................................792 18.6.5 Stop condition ...............................................................................................................................793 18.6.6 Wait state......................................................................................................................................794 18.6.7 Wait state cancellation method .....................................................................................................796 18.7 I2C Interrupt Request Signals (INTIICn)................................................................................ 797 18.7.1 Master device operation................................................................................................................797 18.7.2 Slave device operation (when receiving slave address data (address match)) .............................800 18.7.3 Slave device operation (when receiving extension code)..............................................................804 18.7.4 Operation without communication.................................................................................................808 18.7.5 Arbitration loss operation (operation as slave after arbitration loss)..............................................808 18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ........................810 18.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ........................ 817 18.9 Address Match Detection Method ........................................................................................ 819 18.10 Error Detection ....................................................................................................................... 819 18.11 Extension Code ...................................................................................................................... 819 18.12 Arbitration ............................................................................................................................... 820 18.13 Wakeup Function ................................................................................................................... 821 18.14 Communication Reservation ................................................................................................ 822 18.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)........................822 18.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .......................826 18.15 Cautions .................................................................................................................................. 827 18.16 Communication Operations .................................................................................................. 828 18.16.1 Master operation in single master system ................................................................................829 18.16.2 Master operation in multimaster system...................................................................................830 18.16.3 Slave operation ........................................................................................................................833 18.17 Timing of Data Communication ............................................................................................ 836 CHAPTER 19 CAN CONTROLLER ..................................................................................................... 843 19.1 Overview ................................................................................................................................. 843 19.1.1 Features........................................................................................................................................843 19.1.2 Overview of functions....................................................................................................................844 19.1.3 Configuration.................................................................................................................................845 19.2 CAN Protocol .......................................................................................................................... 846 19.2.1 Frame format ................................................................................................................................846 19.2.2 Frame types ..................................................................................................................................847 19.2.3 Data frame and remote frame .......................................................................................................847 19.2.4 Error frame....................................................................................................................................855 19.2.5 Overload frame .............................................................................................................................856 19.3 Functions ................................................................................................................................ 857 19.3.1 Determining bus priority ................................................................................................................857 19.3.2 Bit stuffing .....................................................................................................................................857 19.3.3 Multi masters.................................................................................................................................857 19.3.4 Multi cast.......................................................................................................................................857 19.3.5 CAN sleep mode/CAN stop mode function ...................................................................................858 19.3.6 Error control function.....................................................................................................................858 19.3.7 Baud rate control function .............................................................................................................865 19.4 Connection with Target System ........................................................................................... 869 19.5 Internal Registers of CAN Controller ................................................................................... 870 19.5.1 CAN controller configuration .........................................................................................................870 19.5.2 Register access type.....................................................................................................................871 19.5.3 Register bit configuration ..............................................................................................................888 19.6 Registers ................................................................................................................................. 892 19.7 Bit Set/Clear Function............................................................................................................ 928 19.8 CAN Controller Initialization ................................................................................................. 930 19.8.1 Initialization of CAN module ..........................................................................................................930 19.8.2 Initialization of message buffer......................................................................................................930 19.8.3 Redefinition of message buffer .....................................................................................................930 19.8.4 Transition from initialization mode to operation mode ...................................................................931 19.8.5 Resetting error counter C0ERC of CAN module ...........................................................................932 19.9 Message Reception................................................................................................................ 933 19.9.1 Message reception........................................................................................................................933 19.9.2 Reading reception data .................................................................................................................934 19.9.3 Receive history list function...........................................................................................................935 19.9.4 Mask function................................................................................................................................937 19.9.5 Multi buffer receive block function.................................................................................................939 19.9.6 Remote frame reception................................................................................................................940 19.10 Message Transmission.......................................................................................................... 941 19.10.1 Message transmission..............................................................................................................941 19.10.2 Transmit history list function.....................................................................................................943 19.10.3 Automatic block transmission (ABT) ........................................................................................945 19.10.4 Transmission abort process .....................................................................................................947 19.10.5 Remote frame transmission .....................................................................................................948 19.11 Power Saving Modes ............................................................................................................. 949 19.11.1 CAN sleep mode ......................................................................................................................949 19.11.2 CAN stop mode........................................................................................................................951 19.11.3 Example of using power saving modes ....................................................................................952 19.12 Interrupt Function .................................................................................................................. 953 19.13 Diagnosis Functions and Special Operational Modes ....................................................... 954 19.13.1 Receive-only mode ..................................................................................................................954 19.13.2 Single-shot mode .....................................................................................................................955 19.13.3 Self-test mode ..........................................................................................................................956 19.13.4 Transmission/reception operation in each operation mode ......................................................957 19.14 Time Stamp Function............................................................................................................. 958 19.14.1 Time stamp function.................................................................................................................958 19.15 Baud Rate Settings ................................................................................................................ 960 19.15.1 Bit rate setting conditions .........................................................................................................960 19.15.2 Representative examples of baud rate settings .......................................................................964 19.16 Operation of CAN Controller................................................................................................. 968 CHAPTER 20 USB FUNCTION CONTROLLER (USBF) .................................................................. 994 20.1 Overview ................................................................................................................................. 994 20.2 Configuration.......................................................................................................................... 995 20.2.1 Block diagram ...............................................................................................................................995 20.2.2 USB memory map.........................................................................................................................996 20.3 External Circuit Configuration .............................................................................................. 997 20.3.1 Outline ..........................................................................................................................................997 20.3.2 Connection configuration ..............................................................................................................998 20.4 Cautions ................................................................................................................................ 1000 20.5 Requests ............................................................................................................................... 1001 20.5.1 Automatic requests .....................................................................................................................1001 20.5.2 Other requests ............................................................................................................................1008 20.6 Register Configuration ........................................................................................................ 1009 20.6.1 USB control registers ..................................................................................................................1009 20.6.2 External bus control registers......................................................................................................1011 20.6.3 USB function controller register list .............................................................................................1014 20.6.4 EPC control registers ..................................................................................................................1030 20.6.4 Data hold registers......................................................................................................................1082 20.6.5 EPC request data registers .........................................................................................................1105 20.6.6 Bridge register.............................................................................................................................1120 20.6.7 DMA register ...............................................................................................................................1124 20.6.8 Bulk-in register ............................................................................................................................1128 20.6.9 Bulk-out register..........................................................................................................................1129 20.6.10 Peripheral control registers ....................................................................................................1131 20.7 STALL Handshake or No Handshake................................................................................. 1135 20.8 Register Values in Specific Status ..................................................................................... 1136 20.9 FW Processing ..................................................................................................................... 1138 20.9.1 Initialization processing ...............................................................................................................1140 20.9.2 Interrupt servicing .......................................................................................................................1143 20.9.3 USB main processing .................................................................................................................1144 20.9.4 Suspend/Resume processing .....................................................................................................1170 20.9.5 Processing after power application .............................................................................................1173 20.9.6 Receiving data for bulk transfer (OUT) in DMA mode .................................................................1176 20.9.7 Transmitting data for bulk transfer (IN) in DMA mode.................................................................1181 CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) ................................................................. 1186 21.1 Features ................................................................................................................................ 1186 21.2 Configuration........................................................................................................................ 1187 21.3 Registers ............................................................................................................................... 1188 21.4 Transfer Targets................................................................................................................... 1197 21.5 Transfer Modes .................................................................................................................... 1197 21.6 Transfer Types ..................................................................................................................... 1198 21.7 DMA Channel Priorities ....................................................................................................... 1199 21.8 Time Related to DMA Transfer............................................................................................ 1199 21.9 DMA Transfer Start Factors ................................................................................................ 1200 21.10 DMA Abort Factors .............................................................................................................. 1201 21.11 End of DMA Transfer ........................................................................................................... 1201 21.12 Cautions ................................................................................................................................ 1201 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................. 1205 22.1 Features ................................................................................................................................ 1205 22.2 Non-Maskable Interrupts ..................................................................................................... 1210 22.2.1 Operation ....................................................................................................................................1212 22.2.2 Restore .......................................................................................................................................1213 22.2.3 NP flag ........................................................................................................................................1214 22.3 Maskable Interrupts ............................................................................................................. 1215 22.3.1 Operation ....................................................................................................................................1215 22.3.2 Restore .......................................................................................................................................1217 22.3.3 Priorities of maskable interrupts..................................................................................................1218 22.3.4 Interrupt control register (xxICn) .................................................................................................1222 22.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) ...........................................................................1225 22.3.6 In-service priority register (ISPR) ................................................................................................1227 22.3.7 ID flag .........................................................................................................................................1228 22.3.8 Watchdog timer mode register 2 (WDTM2).................................................................................1228 22.4 Software Exception.............................................................................................................. 1229 22.4.1 Operation ....................................................................................................................................1229 22.4.2 Restore .......................................................................................................................................1230 22.4.3 EP flag ........................................................................................................................................1231 22.5 Exception Trap ..................................................................................................................... 1232 22.5.1 Illegal opcode..............................................................................................................................1232 22.5.2 Debug trap ..................................................................................................................................1234 22.6 External Interrupt Request Input Pins (NMI and INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP18) .................................................................................................................................. 1236 22.6.1 Noise elimination.........................................................................................................................1236 22.6.2 Edge detection ............................................................................................................................1236 22.7 Interrupt Acknowledge Time of CPU.................................................................................. 1243 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1244 22.9 Cautions ................................................................................................................................ 1244 CHAPTER 23 KEY INTERRUPT FUNCTION ................................................................................... 1245 23.1 Function ................................................................................................................................ 1245 23.2 Register ................................................................................................................................. 1246 23.3 Cautions ................................................................................................................................ 1246 CHAPTER 24 STANDBY FUNCTION ................................................................................................ 1247 24.1 Overview ............................................................................................................................... 1247 24.2 Registers ............................................................................................................................... 1249 24.3 HALT Mode ........................................................................................................................... 1252 24.3.1 Setting and operation status .......................................................................................................1252 24.3.2 Releasing HALT mode ................................................................................................................1252 24.4 IDLE1 Mode........................................................................................................................... 1254 24.4.1 Setting and operation status .......................................................................................................1254 24.4.2 Releasing IDLE1 mode ...............................................................................................................1255 24.5 IDLE2 Mode........................................................................................................................... 1257 24.5.1 Setting and operation status .......................................................................................................1257 24.5.2 Releasing IDLE2 mode ...............................................................................................................1258 24.5.3 Securing setup time when releasing IDLE2 mode.......................................................................1260 24.6 STOP Mode ........................................................................................................................... 1261 24.6.1 Setting and operation status .......................................................................................................1261 24.6.2 Releasing STOP mode ...............................................................................................................1261 24.6.3 Securing oscillation stabilization time when releasing STOP mode ............................................1264 24.7 Subclock Operation Mode................................................................................................... 1265 24.7.1 Setting and operation status .......................................................................................................1265 24.7.2 Releasing subclock operation mode ...........................................................................................1265 24.8 Sub-IDLE Mode..................................................................................................................... 1267 24.8.1 Setting and operation status .......................................................................................................1267 24.8.2 Releasing sub-IDLE mode ..........................................................................................................1267 CHAPTER 25 RESET FUNCTIONS ................................................................................................... 1269 25.1 Overview ............................................................................................................................... 1269 25.2 Registers to Check Reset Source ...................................................................................... 1270 25.3 Operation .............................................................................................................................. 1271 25.3.1 Reset operation via RESET pin ..................................................................................................1271 25.3.2 Reset operation by watchdog timer 2..........................................................................................1273 25.3.3 Reset operation by low-voltage detector .....................................................................................1275 25.3.4 Operation after reset release ......................................................................................................1276 25.3.5 Reset function operation flow......................................................................................................1277 CHAPTER 26 CLOCK MONITOR ...................................................................................................... 1278 26.1 Functions .............................................................................................................................. 1278 26.2 Configuration........................................................................................................................ 1278 26.3 Register ................................................................................................................................. 1279 26.4 Operation .............................................................................................................................. 1280 CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) ........................................................................... 1283 27.1 Functions .............................................................................................................................. 1283 27.2 Configuration........................................................................................................................ 1283 27.3 Registers ............................................................................................................................... 1284 27.4 Operation .............................................................................................................................. 1286 27.4.1 To use for internal reset signal....................................................................................................1286 27.4.2 To use for interrupt......................................................................................................................1287 27.5 RAM Retention Voltage Detection Operation.................................................................... 1288 CHAPTER 28 CRC FUNCTION.......................................................................................................... 1289 28.1 Functions .............................................................................................................................. 1289 28.2 Configuration........................................................................................................................ 1289 28.3 Registers ............................................................................................................................... 1290 28.4 Operation .............................................................................................................................. 1291 28.5 Usage Method....................................................................................................................... 1292 CHAPTER 29 REGULATOR ............................................................................................................... 1294 29.1 Overview ............................................................................................................................... 1294 29.2 Operation .............................................................................................................................. 1295 CHAPTER 30 FLASH MEMORY ........................................................................................................ 1296 30.1 Features ................................................................................................................................ 1296 30.2 Memory Configuration......................................................................................................... 1297 30.3 Functional Overview ............................................................................................................ 1299 30.4 Rewriting by Dedicated Flash Programmer ...................................................................... 1302 30.4.1 Programming environment..........................................................................................................1302 30.4.2 Communication mode .................................................................................................................1303 30.4.3 Flash memory control .................................................................................................................1319 30.4.4 Selection of communication mode ..............................................................................................1320 30.4.5 Communication commands.........................................................................................................1321 30.4.6 Pin connection ............................................................................................................................1322 30.5 Rewriting by Self Programming.......................................................................................... 1326 30.5.1 Overview .....................................................................................................................................1326 30.5.2 Features......................................................................................................................................1327 30.5.3 Standard self programming flow .................................................................................................1328 30.5.4 Flash functions............................................................................................................................1329 30.5.5 Pin processing ............................................................................................................................1329 30.5.6 Internal resources used...............................................................................................................1330 30.6 Creating ROM code to place order for previously written product ................................ 1331 30.6.1 Procedure for using ROM code to place an order .......................................................................1331 CHAPTER 31 ON-CHIP DEBUG FUNCTION ................................................................................... 1332 31.1 Debugging with DCU ........................................................................................................... 1333 31.1.1 Connection circuit example ........................................................................................................1333 31.1.2 Interface signals .........................................................................................................................1333 31.1.3 Maskable functions.....................................................................................................................1335 31.1.4 Register......................................................................................................................................1335 31.1.5 Operation ...................................................................................................................................1337 31.1.6 Cautions .....................................................................................................................................1337 31.2 Debugging Without Using DCU .......................................................................................... 1338 31.2.1 Circuit connection examples.......................................................................................................1338 31.2.2 Maskable functions.....................................................................................................................1342 31.2.3 Securement of user resources ...................................................................................................1343 31.2.4 Cautions .....................................................................................................................................1350 31.3 ROM Security Function........................................................................................................ 1351 31.3.1 Security ID..................................................................................................................................1351 31.3.2 Setting ........................................................................................................................................1352 CHAPTER 32 ELECTRICAL SPECIFICATIONS ............................................................................... 1354 32.1 Absolute Maximum Ratings ................................................................................................ 1354 32.2 Capacitance .......................................................................................................................... 1356 32.3 Operating Conditions .......................................................................................................... 1356 32.4 Oscillator Characteristics.................................................................................................... 1357 32.4.1 Main clock oscillator characteristics ............................................................................................1357 32.4.2 Subclock oscillator characteristics ..............................................................................................1359 32.4.3 PLL characteristics......................................................................................................................1361 32.4.4 Internal oscillator characteristics .................................................................................................1361 32.5 DC Characteristics ............................................................................................................... 1362 32.5.1 I/O level.......................................................................................................................................1362 32.5.2 Supply current.............................................................................................................................1364 32.6 32.7 32.8 32.9 Data Retention Characteristics........................................................................................... 1365 AC Characteristics ............................................................................................................... 1366 Basic Operation.................................................................................................................... 1367 Flash Memory Programming Characteristics ................................................................... 1380 CHAPTER 33 PACKAGE DRAWINGS .............................................................................................. 1381 APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1386 A.1 Software Package ................................................................................................................ 1388 A.2 Language Processing Software ......................................................................................... 1388 A.3 Control Software .................................................................................................................. 1388 A.4 Debugging Tools (Hardware) .............................................................................................. 1389 A.4.1 When using IECUBE QB-V850ESJX3H......................................................................................1389 A.4.2 When using MINICUBE QB-V850MINI .......................................................................................1392 A.4.3 When using MINICUBE2 QB-MINI2............................................................................................1393 A.5 Debugging Tools (Software) ............................................................................................... 1393 A.6 Embedded Software............................................................................................................. 1394 A.7 Flash Memory Writing Tools ............................................................................................... 1394 APPENDIX B REGISTER INDEX ....................................................................................................... 1395 APPENDIX C INSTRUCTION SET LIST ........................................................................................... 1429 C.1 Conventions.......................................................................................................................... 1429 C.2 Instruction Set (in Alphabetical Order) .............................................................................. 1432 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 V850ES/JC3-H, V850ES/JE3-H RENESAS MCU CHAPTER 1 INTRODUCTION The V850ES/JC3-H and V850ES/JE3-H are products in the low-power series of Renesas Electronics' V850 single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/JC3-H and V850ES/JE3-H are 32-bit single-chip microcontrollers that use the V850ES CPU core and incorporate peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, a D/A converter, a DMA controller, CAN, and a USB function controller. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JC3-H and V850ES/JE3-H feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit manipulation instructions. Table 1-1 lists the products of the V850ES/JC3-H (40 pin), Table 1-2 lists the products of the V850ES/JC3-H (48 pin), and Table 1-3 lists the products of the V850ES/JE3-H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 21 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JC3-H (40 pin) Product List Generic Name V850ES/JC3-H (40 pin) PD70F3809 Part Number PD70F3810 PD70F3811 PD70F3812 PD70F3813 Internal memory Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB RAM 8 KB 16 KB 24 KB 24 KB 24 KB Memory space Logical space 64 MB General-purpose register 32 bits x 32 registers Clock (PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8) Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz) Main clock Subclock fXT = 32.768 kHz Internal oscillator fR = 220 kHz (TYP.) Minimum instruction execution time 20.8 ns (main clock (fXX) = 48 MHz) I/O port (5 V tolerant) I/O: 25 (15) Timer 16-bit TAA 4 channels (including 1 channel used only for interval function) 16-bit TAB 1 channel (only for interval function) 16-bit TMM 4 channels 16-bit TMT 1 channel (only for interval function) Watch timer 1 channel (RTC) WDT 1 channel Real-time output function 4 bits x 1 channel Key interrupt function 4 bits x 1 channel 10-bit A/D converter 5 channels USB controller USB2.0 Full-speed function: 1channel Serial interface CSIF/UARTC 2 channels CSIF 1 channel 2 CSIF/UARTC/I C DMA controller Interrupt source 1 channel 4 channels (transfer target: on-chip peripheral I/O, internal RAM) External Note Internal 10 52 Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) On-chip debugging MINICUBE(R), MINICUBE2 supported Operating power supply voltage 2.85 to 3.6 V Operating ambient temperature -40 to +85C Package 40-pin plastic WQFN (6 x 6 mm) Note The figures in parentheses indicate the number of external interrupts that can release STOP mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 22 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION Table 1-2. V850ES/JC3-H (48 pin) Product List Generic Name V850ES/JC3-H (48 pin) PD70F3814 Part Number <R> PD70F3815 PD70F3816 PD70F3817 PD70F3818 PD70F3819 Internal memory Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB 256 KB RAM 8 KB 16 KB 24 KB 24 KB 24 KB 24 KB Memory space Logical space 64 MB General-purpose register 32 bits x 32 registers Clock (PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8) Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz) Main clock Subclock fXT = 32.768 kHz Internal oscillator fR = 220 kHz (TYP.) Minimum instruction execution time 20.8 ns (main clock (fXX) = 48 MHz) I/O port (5 V tolerant) I/O: 32 (17) Timer 16-bit TAA 4 channels (including 1 channel used only for interval function) 16-bit TAB 1 channel (only for interval function) 16-bit TMM 4 channels 16-bit TMT 1 channel Watch timer 1 channel (RTC) WDT 1 channel 4 bits x 1 channel Real-time output function Key interrupt function 4 bits x 1 channel 10-bit A/D converter 6 channels 8-bit D/A converter 1 channel USB controller USB2.0 Full-speed function: 1channel Serial interface 2 channels CSIF/UARTC 2 CSIF/UARTC/I C 1 channel CSIF 1 channel 2 UARTC/I C DMA controller Interrupt source - 1 channel - 2 UARTC/I C/CAN 1 channel 4 channels (transfer target: on-chip peripheral I/O, internal RAM) External Note Internal 10 53 57 Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) On-chip debugging MINICUBE, MINICUBE2 supported Operating power supply voltage 2.85 to 3.6 V Operating ambient temperature -40 to +85C Package 48-pin plastic LQFP (fine pitch) (7 x 7 mm) 48 pin plastic WQFN (7 x 7 mm) Note The figures in parentheses indicate the number of external interrupts that can release STOP mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 23 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION Table 1-3. V850ES/JE3-H Product List Generic Name V850ES/JE3-H PD70F3820 Part Number <R> PD70F3821 PD70F3822 PD70F3823 PD70F3824 PD70F3825 Internal memory Flash memory 16 KB 32 KB 64 KB 128 KB 256 KB 256 KB RAM 8 KB 16 KB 24 KB 24 KB 24 KB 24 KB Memory space Logical space 64 MB General-purpose register 32 bits x 32 registers Clock (PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8) Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz) Main clock Subclock fXT = 32.768 kHz Internal oscillator fR = 220 kHz (TYP.) Minimum instruction execution time 20.8 ns (main clock (fXX) = 48 MHz) I/O port (5 V tolerant) I/O: 45 (19) Timer 4 channels (including 1 channel used only for interval function) 16-bit TAA 16-bit TAB 1 channel 16-bit TMM 4 channels 16-bit TMT 1 channel Motor control 1 channel (functions with combination of TAA and TAB; includes Hi-Z output control function) Watch timer 1 channel (RTC) WDT 1 channel Real-time output function 4 bits x 1 channel Key interrupt function 6 bits x 1 channel 10-bit A/D converter 10 channels 8-bit D/A converter 1 channel USB controller USB2.0 Full-speed Function: 1channel Serial interface 2 channels CSIF/UARTC 2 CSIF/UARTC/I C CSIF 1 channel 1 channel 2 UARTC/I C - 1 channel - 2 UARTC/I C/CAN DMA controller Interrupt source 1 channel 4 channels (transfer target: on-chip peripheral I/O, internal RAM) External Notes1, 2 Internal 11 53 57 Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) On-chip debugging MINICUBE, MINICUBE2 supported Operating power supply voltage 2.85 to 3.6 V Operating ambient temperature -40 to +85C Package 64-pin plastic LQFP (fine pitch) (10 x 10 mm) 64-pin plastic WQFN (9 x 9 mm) 64-pin plastic FBGA (6 x 6 mm) Note3 Notes 1. The figures in parentheses indicate the number of external interrupts that can release STOP mode. 2. Including NMI. 3. PD70F3824 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 24 of 1442 V850ES/JC3-H, V850ES/JE3-H 1.2 CHAPTER 1 INTRODUCTION Features { Minimum instruction execution time: 20.8 ns (main clock (fXX) = 48 MHz: VDD = 2.85 to 3.6 V) 30.5 s (subclock (fXT) = 32.768 kHz) { General-purpose registers: 32 bits x 32 registers { CPU features: Signed multiplication (16 x 16 32): 1 or 2 clocks Signed multiplication (32 x 32 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format { Memory space: 64 MB of linear address space (for programs and data) * Internal memory: RAM: 8/16/24 KB (see Table 1-1, Table 1-2 and Table 1-3) Flash memory: 16/32/64/128/256 KB (see Table 1-1, Table 1-2 and Table 1-3) { Interrupts and exceptions: Internal External Non-maskable Maskable Total Non-maskable Maskable Total V850ES/JC3-H PD70F3809 1 51 52 - 10 10 (40 pin) PD70F3810 1 51 52 - 10 10 PD70F3811 1 51 52 - 10 10 PD70F3812 1 51 52 - 10 10 PD70F3813 1 51 52 - 10 10 V850ES/JC3-H PD70F3814 1 52 53 - 10 10 (48 pin) PD70F3815 1 52 53 - 10 10 PD70F3816 1 52 53 - 10 10 PD70F3817 1 52 53 - 10 10 PD70F3818 1 52 53 - 10 10 PD70F3819 1 56 57 - 10 10 PD70F3820 1 52 53 1 11 11 PD70F3821 1 52 53 1 11 11 PD70F3822 1 52 53 1 11 11 PD70F3823 1 52 53 1 11 11 PD70F3824 1 52 53 1 11 11 PD70F3825 1 56 57 1 11 11 V850ES/JE3-H Software exceptions: 32 sources Exception trap: 2 sources { I/O lines: I/O ports: 25 (V850ES/JC3-H (40 pin)) 32 (V850ES/JC3-H (48 pin)) 45 (V850ES/JE3-H) { Timer function: R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 16-bit interval timer M (TMM): 4 channels 16-bit timer/event counter AA (TAA): 4 channels 16-bit timer/event counter AB (TAB): 1 channel Page 25 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION Motor control function (timers used: TAB1, TAA4) (V850ES/JE3-H only) 6-phase PWM function with dead-time function of 16-bit accuracy High-impedance output control function A/D trigger generation by timer-tuned operation function Arbitrary cycle setting function Arbitrary dead-time setting function 16-bit timer/event counter T (TMT): 1 channel Real-time counter (RTC): 1 channel Watchdog timer: 1 channel { Real-time output port: 4 bits x 1 channel { Key interrupt: 4 bits x 1 channel { USB controller: USB2.0 Full-speed Function: 1channel { Serial interface: Asynchronous serial interface C (UARTC) 3-wire variable-length serial interface F (CSIF) I2C bus interface (I2C) CAN interface Note1 USB function interface UARTC/CSIF: 2 channels UARTC/CSIF/I2C: 1 channel CSIF: 1 channel UARTC/I2C: 2 UARTC/I C/CAN 1/2 channel (see Table 1-1, Table 1-2 and Table 1-3) Note2 : USB function: 1 channel 1 channel { A/D converter: 10-bit resolution: 5/6/10 channels { D/A converter Note3: 8-bit resolution: 1 channel { DMA controller: 4 channels { DCU (debug control unit): JTAG interface { Clock generator: Main clock or subclock operation: 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable { Internal oscillation clock: 220 kHz (TYP.) { Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode { Package: 40-pin plastic WQFN (6 x 6 mm) (V850ES/JC3-H) 48-pin plastic LQFP (fine pitch) (7 x 7 mm) (V850ES/JC3-H) 48-pin plastic WQFN (7 x 7 mm) (V850ES/JC3-H) 64-pin plastic LQFP (fine pitch) (10 x 10 mm) (V850ES/JE3-H) 64-pin plastic WQFN (9 x 9 mm) (V850ES/JE3-H) 64-pin plastic FBGA (6 x 6 mm) ( PD70F3824 only) Notes1. In the PD70F3819 and 70F3825, one channel is shared with CAN. 2. PD70F3819, 70F3825 only 3. V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 26 of 1442 V850ES/JC3-H, V850ES/JE3-H 1.3 CHAPTER 1 INTRODUCTION Application Fields Equipment requiring a USB interface such as PC peripheral, Healthcare, OA, Consumer, USB interface. 1.4 Ordering Information * V850ES/JC3-H (40 pin) Part Number PD70F3809K8-4B4-AX PD70F3810K8-4B4-AX PD70F3811K8-4B4-AX PD70F3812K8-4B4-AX PD70F3813K8-4B4-AX Package Internal Flash Memory 40-pin plastic WQFN (6 x 6) 16 KB 40-pin plastic WQFN (6 x 6) 32 KB 40-pin plastic WQFN (6 x 6) 64 KB 40-pin plastic WQFN (6 x 6) 128 KB 40-pin plastic WQFN (6 x 6) 256 KB * V850ES/JC3-H (48 pin) Part Number PD70F3814GA-GAM-AX PD70F3815GA-GAM-AX PD70F3816GA-GAM-AX PD70F3817GA-GAM-AX PD70F3818GA-GAM-AX PD70F3819GA-GAM-AX PD70F3814K8-5B4-AX PD70F3815K8-5B4-AX PD70F3816K8-5B4-AX PD70F3817K8-5B4-AX PD70F3818K8-5B4-AX PD70F3819K8-5B4-AX Package Internal Flash Memory 48-pin plastic LQFP (fine pitch) (7 x 7) 16 KB 48-pin plastic LQFP (fine pitch) (7 x 7) 32 KB 48-pin plastic LQFP (fine pitch) (7 x 7) 64 KB 48-pin plastic LQFP (fine pitch) (7 x 7) 128 KB 48-pin plastic LQFP (fine pitch) (7 x 7) 256 KB 48-pin plastic LQFP (fine pitch) (7 x 7) 256 KB 48-pin plastic WQFN (7 x 7) 16 KB 48-pin plastic WQFN (7 x 7) 32 KB 48-pin plastic WQFN (7 x 7) 64 KB 48-pin plastic WQFN (7 x 7) 128 KB 48-pin plastic WQFN (7 x 7) 256 KB 48-pin plastic WQFN (7 x 7) 256 KB Remark The V850ES/JC3-H is lead-free products. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 27 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H Part Number PD70F3820GB-GAH-AX PD70F3821GB-GAH-AX PD70F3822GB-GAH-AX PD70F3823GB-GAH-AX PD70F3824GB-GAH-AX PD70F3825GB-GAH-AX PD70F3820K8-6B4-AX PD70F3821K8-6B4-AX PD70F3822K8-6B4-AX PD70F3823K8-6B4-AX PD70F3824K8-6B4-AX PD70F3825K8-6B4-AX PD70F3824F1-BA3-A Remark Package Internal Flash Memory 64-pin plastic LQFP (fine pitch) (10 x 10) 16 KB 64-pin plastic LQFP (fine pitch) (10 x 10) 32 KB 64-pin plastic LQFP (fine pitch) (10 x 10) 64 KB 64-pin plastic LQFP (fine pitch) (10 x 10) 128 KB 64-pin plastic LQFP (fine pitch) (10 x 10) 256 KB 64-pin plastic LQFP (fine pitch) (10 x 10) 256 KB 64-pin plastic WQFN (9 x 9) 16 KB 64-pin plastic WQFN (9 x 9) 32 KB 64-pin plastic WQFN (9 x 9) 64 KB 64-pin plastic WQFN (9 x 9) 128 KB 64-pin plastic WQFN (9 x 9) 256 KB 64-pin plastic WQFN (9 x 9) 256 KB 64-pin plastic FBGA (6 x 6) 256 KB The V850ES/JE3-H is lead-free products. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 28 of 1442 V850ES/JC3-H, V850ES/JE3-H 1.5 CHAPTER 1 INTRODUCTION Pin Configuration (Top View) * V850ES/JC3-H (40 pin) 40-pin plastic WQFN (6 x 6) P910/SIF3/TXDC2/INTP14 PDL5/FLMD1 31 P913/INTP16 35 32 P74/ANI4 36 P911/SOF3/RXDC2/INTP15 P73/ANI3 37 33 P72/ANI2 38 P912/SCKF3 P71/ANI1 39 PD70F3811K8-4B4-AX 34 P70/ANI0 PD70F3810K8-4B4-AX 40 PD70F3809K8-4B4-AX PD70F3813K8-4B4-AX PD70F3812K8-4B4-AX 30 P97/TIAA20/TOAA20 2 29 P96/TIAA21/TOAA21/INTP11 AVREF0 1 AVSS exposed die pad 8 23 P52/KR2/RTP02/DDI XT1 9 22 P42/SCKF0/INTP10 XT2 10 21 P41/SOF0/RXDC4/SCL01 20 RESET P40/SIF0/TXDC4/SDA01 P53/SIF2/KR3/RTP03/DDO 19 24 P32/ASCKC0/SCKF4/TIAA00/TOAA00 7 18 X2 P31/RXDC0/SIF4/INTP08 P54/SOF2/KR4/RTP04/DCK 17 25 P30/TXDC0/SOF4/INTP07 6 16 X1 P34/TIAA10/TOAA10/INTP09 P55/SCKF2/KR5/RTP05/DMS 15 26 VSS 5 14 VSS EVDD P56/INTP05/DRST 13 27 UDPF 4 REGC 12 FLMD0Note2 UDMF 28 11 3 P03/INTP02/ADTRG/UCLK VDD Note1 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (recommend value) capacitor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 29 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JC3-H (48 pin) 48-pin plastic LQFP (fine pitch) (7 x 7) AVREF0 1 AVSS 2 4 VDD 5 REGCNote2 6 VSS 7 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P913/INTP16 P912/SCKF3 P911/SOF3/RXDC2/INTP15 P910/SIF3/TXDC2/INTP14 P94/TENC00/EVTT0 PDL5/FLMD1 46 45 44 43 42 41 40 39 38 37 11 16 17 18 19 20 21 22 23 24 EVDD VSS P34/TIAA10/TOAA10/INTP09 Note3 P37/RXDC3/SDA00/CRXD0Note3 P30/TXDC0/SOF4/INTP07 P31/RXDC0/SIF4/INTP08 P32/ASCKC0/SCKF4/TIAA00/TOAA00 P40/SIF0/TXDC4/SDA01 P36/TXDC3/SCL00/CTXD0 15 12 UDPF XT2 10 14 XT1 9 13 RESET 8 UDMF X2 47 3 AVREF1 X1 PD70F3816GA-GAM-AX PD70F3819GA-GAM-AX P03/INTP02/ADTRG/UCLK P10/ANO0 PD70F3815GA-GAM-AX PD70F3818GA-GAM-AX 48 PD70F3814GA-GAM-AX PD70F3817GA-GAM-AX 36 P93/TECR0/TIT00/TOT01 35 P92/TENC01/TIT01/TOT01 34 P97/TIAA20/TOAA20 33 P96/TIAA21/TOAA21/INTP11 32 FLMD0Note1 31 P56/INTP05/DRST 30 P55/SCKF2/KR5/RTP05/DMS 29 P54/SOF2/KR4/RTP04/DCK 28 P53/SIF2/KR3/RTP03/DDO 27 P52/KR2/RTP02/DDI 26 P42/SCKF0/INTP10 25 P41/SOF0/RXDC4/SCL01 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (recommend value) capacitor. 3. PD70F3819 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 30 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JC3-H (48 pin) 48-pin plastic WQFN (7 x 7) AVREF0 1 AVSS 2 P10/ANO0 3 AVREF1 4 VDD 5 REGCNote2 6 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P913/INTP16 P912/SCKF3 P911/SOF3/RXDC2/INTP15 P910/SIF3/TXDC2/INTP14 P94/TENC00/EVTT0 PDL5/FLMD1 47 46 45 44 43 42 41 40 39 38 37 exposed die pad 7 X1 8 X2 9 RESET 10 XT1 11 15 16 17 18 19 20 21 22 23 24 UDPF EVDD VSS P34/TIAA10/TOAA10/INTP09 P36/TXDC3/SCL00/CTXD0Note3 Note3 P30/TXDC0/SOF4/INTP07 P31/RXDC0/SIF4/INTP08 P32/ASCKC0/SCKF4/TIAA00/TOAA00 P40/SIF0/TXDC4/SDA01 P37/RXDC3/SDA00/CRXD0 14 UDMF 12 13 XT2 PD70F3816K8-5B4-AX P03/INTP02/ADTRG/UCLK VSS PD70F3815K8-5B4-AX PD70F3819K8-5B4-AX 48 PD70F3814K8-5B4-AX PD70F3818K8-5B4-AX PD70F3817K8-5B4-AX 36 P93/TECR0/TIT00/TOT01 35 P92/TENC01/TIT01/TOT01 34 P97/TIAA20/TOAA20 33 P96/TIAA21/TOAA21/INTP11 32 FLMD0Note1 31 P56/INTP05/DRST 30 P55/SCKF2/KR5/RTP05/DMS 29 P54/SOF2/KR4/RTP04/DCK 28 P53/SIF2/KR3/RTP03/DDO 27 P52/KR2/RTP02/DDI 26 P42/SCKF0/INTP10 25 P41/SOF0/RXDC4/SCL01 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (recommend value) capacitor. 3. PD70F3819 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 31 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H 64-pin plastic LQFP (fine pitch) (10 x 10) P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P913/TOAB1OFF/INTP16 P912/SCKF3 P911/SOF3/RXDC2/INTP15 P910/SIF3/TXDC2/INTP14 P94/TENC00/EVTT0 PDL5/FLMD1 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 P70/ANI0 63 P40/SIF0/TXDC4/SDA01 16 31 P63/TOAB1B2/TRGAB1 P32/ASCKC0/SCKF4/TIAA00/TOAA00 15 30 P62/TOAB1T2/TOAB12/TIAB12 P31/RXDC0/SIF4/INTP08 14 29 P61/TOAB1B1/TIAB10/TOAB10 P30/TXDC0/SOF4/INTP07 13 28 P60/TOAB1T1/TIAB11/TOAB11 P37/RXDC3/SDA00/CRXD0Note3 12 27 XT2 P36/TXDC3/SCL00/CTXD0Note3 11 26 XT1 P34/TIAA10/TOAA10/TOAA1OFF/INTP09 10 25 RESET VSS 9 24 X2 EVDD 8 23 7 X1 UVDD VSS 22 6 UDPF REGCNote2 21 5 UDMF VDD 20 4 P03/INTP02/ADTRG/UCLK AVREF1 19 3 P02/NMI P10/ANO0 18 2 17 1 AVSS P65/TOAB1B3/EVTAB1 AVREF0 PD70F3822GB-GAH-AX PD70F3825GB-GAH-AX 64 PD70F3821GB-GAH-AX PD70F3824GB-GAH-AX P64/TOAB1T3/TOAB13/TIAB13 PD70F3820GB-GAH-AX PD70F3823GB-GAH-AX 48 P93/TECR0/TIT00/TOT01 47 P92/TENC01/TIT01/TOT01 46 P97/TIAA20/TOAA20 45 P96/TIAA21/TOAA21/INTP11 44 EVDD 43 VSS 42 FLMD0Note1 41 P56/INTP05/DRST 40 P55/SCKF2/KR5/RTP05/DMS 39 P54/SOF2/KR4/RTP04/DCK 38 P53/SIF2/KR3/RTP03/DDO 37 P52/KR2/RTP02/DDI 36 P35/TIAA11/TOAA11/RTC1HZ 35 P33/TIAA01/TOAA01/RTCDIV/RTCCL 34 P42/SCKF0/INTP10 33 P41/SOF0/RXDC4/SCL01 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (recommend value) capacitor. 3. PD70F3825 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 32 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H 64-pin plastic WQFN (9 x 9) P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P913/TOAB1OFF/INTP16 P912/SCKF3 P911/SOF3/RXDC2/INTP15 P910/SIF3/TXDC2/INTP14 P94/TENC00/EVTT0 PDL5/FLMD1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 P40/SIF0/TXDC4/SDA01 16 31 P63/TOAB1B2/TRGAB1 P32/ASCKC0/SCKF4/TIAA00/TOAA00 15 30 P62/TOAB1T2/TOAB12/TIAB12 P31/RXDC0/SIF4/INTP08 14 29 P61/TOAB1B1/TIAB10/TOAB10 P30/TXDC0/SOF4/INTP07 13 28 P60/TOAB1T1/TIAB11/TOAB11 P37/RXDC3/SDA00/CRXD0Note3 12 27 XT2 P36/TXDC3/SCL00/CTXD0Note3 11 26 10 XT1 P34/TIAA10/TOAA10/TOAA1OFF/INTP09 RESET 25 9 VSS X2 24 8 EVDD X1 23 7 UVDD VSS 22 6 UDPF REGCNote2 21 5 UDMF VDD 20 4 P03/INTP02/ADTRG/UCLK AVREF1 19 3 P02/NMI P10/ANO0 exposed die pad 18 2 17 1 AVSS P65/TOAB1B3/EVTAB1 AVREF0 PD70F3822K8-6B4-AX PD70F3825K8-6B4-AX 64 PD70F3821K8-6B4-AX PD70F3824K8-6B4-AX P64/TOAB1T3/TOAB13/TIAB13 PD70F3820K8-6B4-AX PD70F3823K8-6B4-AX 48 P93/TECR0/TIT00/TOT01 47 P92/TENC01/TIT01/TOT01 46 P97/TIAA20/TOAA20 45 P96/TIAA21/TOAA21/INTP11 44 EVDD 43 VSS 42 FLMD0Note1 41 P56/INTP05/DRST 40 P55/SCKF2/KR5/RTP05/DMS 39 P54/SOF2/KR4/RTP04/DCK 38 P53/SIF2/KR3/RTP03/DDO 37 P52/KR2/RTP02/DDI 36 P35/TIAA11/TOAA11/RTC1HZ 35 P33/TIAA01/TOAA01/RTCDIV/RTCCL 34 P42/SCKF0/INTP10 33 P41/SOF0/RXDC4/SCL01 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 F (recommend value) capacitor. 3. PD70F3825 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 33 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H ( PD70F3824 only) 64-pin plastic FBGA (6 x 6) PD70F3824F1-BA34-AX Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H Index mark H G F E D C B A Index mark Pin configuration is undefinded. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 34 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION Pin names ADTRG: ANI0 to ANI09: ANO0: ASCKC0:: AVREF0, AVREF1: AVSS: CRXD0: CTXD0: DCK: DDI: DDO: DMS: DRST: EVDD: EVTT0, EVTAB1: FLMD0, FLMD1: INTP02, INTP05 INTP07 to INTP011, INTP14 to INTP16: KR2 to KR5: NMI: P02, P03: P10: P30 to P37: P40 to P42: P52 to P56: P60 to P65 P70 to P77: P92 to P94, P910 to P913 : PDL5: REGC: RESET: RTC1HZ, RTCCL, RTCDIV: RTP00 to RTP05: A/D trigger input Analog input Analog output Asynchronous serial clock Analog reference voltage Grand for analog pin CAN receive data CAN transmit data Debug clock Debug data input Debug data output Debug mode select Debug reset Power supply for external pin Timer event count input Flash programming mode External interrupt input Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port DL Regulator control Reset Real-time counter clock output Real-time output port R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 RXDC0, RXDC2 to RXDC4: SCKF0 to SCKF4: SCL00, SCL01: SDA00, SDA01: SIF0, SIF2 to SIF4: SOF0, SOF2 to SOF4: TECR0: TENC00, TENC01: TIAA00, TIAA01, TIAA10, TIAA11, TIAA20, TIAA21, TIAB10 to TIAB13, TIT00, TIT01: TOAA00, TOAA01, TOAA10, TOAA11, TOAA20, TOAA21, TOAB10 to TOAB13, TOAB1B1 to TOAB1B3, TOAB1T1 to TOAB1T3, TOT00, TOT01: TOAA1OFF, TOAB1OFF: TRGAB1: TXDC0, TXDC2 to TXDC4: UCLK: UDMF: UDPF: UVDD: VDD: VSS: X1, X2: XT1, XT2: Receive data Serial clock Serial clock Serial data Serial input Serial output Timer encoder clear input Timer encoder input Timer input Timer output Timer output off Timer trigger input Transmit data USB clock USB data I/O (-) function USB data I/O (+) function Power supply for external USB Power supply Grand Crystal for main clock Crystal for subclock Page 35 of 1442 V850ES/JC3-H, V850ES/JE3-H 1.6 1.6.1 CHAPTER 1 INTRODUCTION Function Block Configuration Internal block diagram * V850ES/JC3-H (40 pin) Flash memory INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 INTC 16-bit timer/ counter AB: 1 ch TIAA00, TIAA10, TIAA20, TIAA21 TOAA00, TOAA10 TOAA20, TOAA21 CPU Instruction queue Note 1 PC RAM 32-bit barrel shifter Note 2 System register 16-bit timer/ counter AA: 4 ch Multiplier 16 x 16 32 BCU ALU General-purpose registers 32 bits x 32 DMAC: 4 ch 16-bit interval timer M: 4 ch Internal oscillator Ports PDL5 P96 , P97 ,P910 to P913 P70 to P74 P52 to P56 P40 to P42 P30 to P32, P34 P03 WDT RTC RTP02 to RTP05 RTO SIF0, SIF2 to SIF4 SOF0, SOF2 to SOF4 SCKF0, SCKF2 to SCKF4 CSIF: 4 ch RXDC0, RXDC2, RXDC4 TXDC0, TXDC2, TXDC4 ASCKC0 UARTC: 3 ch SDA01 SCL01 I2C: 1 ch UDMF UDPF USB function A/D converter CG CG PLL XT1 XT2 X1 X2 RESET LVI VDD Regulator VSS REGC FLMD0 FLMD1 ANI0 to ANI4 ADTRG AVREF0 AVSS EVDD DRST DMS DCU Key return function Notes 1. PD70F3809: PD70F3810: PD70F3811: PD70F3812: PD70F3813: 2. PD70F3809: PD70F3810: PD70F3811, 70F3812, 70F3813: R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 CLKOUT CRC 16-bit timer/ counter T: 1 ch KR2 to KR5 DDI DCK DDO 16 KB 32 KB 64 KB 128 KB 256 KB 8KB 16 KB 24 KB Page 36 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JC3-H (48 pin) INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 Flash memory INTC 16-bit timer/ counter AB: 1 ch TIAA00, TIAA10, TIAA20, TIAA21 TOAA00, TOAA10 TOAA20, TOAA21 CPU Instruction queue Note 1 PC RAM 32-bit barrel shifter Note 2 System register 16-bit timer/ counter AA: 4 ch Multiplier 16 x 16 32 BCU ALU General-purpose registers 32 bits x 32 DMAC: 4 ch 16-bit interval timer M: 4 ch TOT00, TOT01 16-bit timer/ counter T: 1 ch Internal oscillator Ports PDL5 P92 to P94,P96, P97,P910 to P913 P70 to P75 P52 to P56 P40 to P42 P30 to P33, P34, P36, P37 P10 P03 WDT RTC RTP02 to RTP05 RTO SIF0, SIF2 to SIF4 SOF0, SOF2 to SOF4 SCKF0, SCKF2 to SCKF4 CSIF: 4 ch CRC TECR0, TENC00, TENC01, EVTT0, TIT00, TIT01 CG CG PLL UARTC: 4 ch SDA00, SDA01 SCL00, SCL01 I2C: 2 ch UDMF UDPF CRXD0 CTXD0 A/D converter RESET VDD Regulator VSS REGC FLMD0 FLMD1 EVDD ANI0 to ANI5 ADTRG AVREF0 AVSS DRST DMS USB function CANNote 3: 1 ch D/A converter Key return function Notes 1. PD70F3814: PD70F3815: PD70F3816: PD70F3817: PD70F3818, 70F3819: 2. PD70F3814: PD70F3815: PD70F3816, 70F3817, 70F3818, 70F3819: 3. PD70F3819 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 XT2 X1 X2 LVI CLM RXDC0, RXDC2 to RXDC4 TXDC0, TXDC2 to TXDC4 ASCKC0 XT1 AVREF1 ANO0 DCU DDI DCK DDO KR2 to KR5 16 KB 32 KB 64 KB 128 KB 256 KB 8KB 16 KB 24 KB Page 37 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H NMI INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 16-bit timer/ counter AB: 1 ch PC RAM 32-bit barrel shifter Note 2 System register TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 TIAA00, TIAA10, TIAA20 TIAA01,TIAA11, TIAA21 TOAA1OFF TOAA00, TOAA10, TOAA20 TOAA01, TOAA11, TOAA21 BCU ALU 16-bit timer/ counter AA: 4 ch DMAC: 4 ch 16-bit timer/ counter T: 1 ch WDT RTC1HZ RTCCL RTCDIV RTC RTP02 to RTP05 RTO Ports CG CG PDL5 P92 to P94, P96, P97, P910 to P913 P70 to P79 P60 to P65 P52 to P56 P40 to P42 P30 to P37 P10 P02, P03 TOT00, TOT01 Multiplier 16 x 16 32 General-purpose registers 32 bits x 32 16-bit interval timer M: 4 ch TECR0, TENC00, TENC01, EVTT0, TIT00, TIT01 Instruction queue Note 1 CRC TOAB10 to TOAB13 CPU Internal oscillator TIAB10 to TIAB13, EVTAB1, TRGAB1, TOAB1OFF Flash memory INTC PLL XT1 XT2 X1 X2 RESET LVI VDD Regulator VSS REGC FLMD0 FLMD1 SIF0, SIF2 to SIF4 SOF0, SOF2 to SOF4 SCKF0, SCKF2 to SCKF4 CSIF: 4 ch RXDC0, RXDC2 to RXDC4 TXDC0, TXDC2 to TXDC4 ASCKC0 UARTC: 4 ch SDA00, SDA01 SCL00, SCL01 I2C: 2 ch UDMF UDPF CRXD0 CTXD0 USB function CAN Note 3 : 1 ch EVDD, UVDD CLM A/D converter DRST DMS D/A converter Key return function Notes 1. PD70F3820: PD70F3821: PD70F3822: PD70F3823: PD70F3824, 70F3825: 2. PD70F3820: PD70F3821: PD70F3822, 70F3823, 70F3824, 70F3825: 3. PD70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 ANI0 to ANI9 ADTRG AVREF0 AVSS AVREF1 ANO0 DCU DDI DCK DDO KR2 to KR5 16 KB 32 KB 64 KB 128 KB 256 KB 8KB 16 KB 24 KB Page 38 of 1442 V850ES/JC3-H, V850ES/JE3-H 1.6.2 CHAPTER 1 INTRODUCTION Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue. (3) Flash memory (ROM) This is a 256/128/64/32/16 KB flash memory mapped to addresses 0000000H to 003FFFFH/0000000H to 001FFFFH/0000000H to 000FFFFH/0000000H to 0007FFFH/0000000H to 0003FFFH/. It can be accessed from the CPU in one clock during instruction fetch. (4) RAM This is a 24/16/8 KB RAM mapped to addresses 3FF9000H to 3FFEFFFH/3FFB000H to 3FFEFFFH/ 3FFD000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access. (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 8. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (7) Internal oscillator An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator supplies the clock for watchdog timer 2 and timer M. (8) Timer/counter Four-channel 16-bit timer/event counter AA (TAA), one-channel 16-bit timer/event counter AB (TAB) Note, one-channel 16-bit timer/event counter T (TMT), and four-channel 16-bit interval timer M (TMM) are provided on chip. The motor control function can be realized using TAB1 and TAA4 in combination. Note V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 39 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION (9) Real-time counter (for watch) The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to 99 years. (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JC3-H and V850ES/JE3-H include three kinds of serial interfaces (asynchronous serial interface C (UARTC), 3-wire variable-length serial interface F (CSIF), and an I2C bus interface (I2C)), a CAN controller (CAN)Note1, and a USB function controller (USBF). UARTC transfers data via the TXDC0, TXDC2 to TXDC4 pins and RXDC0, RXDC2 to RXDC4 pins. CSIF transfers data via the SOF0, SOF2 to SOF4 pins, SIF0, SIF2 to SIF4 pins, and SCKF0, SCKF2 to SCKF4 pins. In the case of I2C, data is transferred via the (SDA00)Note2 , SDA01 and (SCL00)Note2 , SCL01 pins. CANNote1 transfers data via the CRXDNote1 and CTXD0Note1 pins. USBF transfers data via the UDMF and UDPF pins. Notes1. PD70F3819, 70F3825 only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only (12) A/D converter This 10-bit A/D converter includes 10/6/5 analog input pins. Conversion is performed using the successive approximation method. (13) D/A converter (V850ES/JC3-H (48 pin), JE3-H only) A one-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip. (14) DMA controller A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM, on-chip peripheral I/O devices, and external memory in response to interrupt requests sent by on-chip peripheral I/O devices. (15) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (4 channels). (16) Real-time output function The real-time output function transfers preset 4-bit data to output latches upon the occurrence of a timer compare register match signal. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 40 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION (17) CRC function A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on-chip. (18) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the OCDM register. (19) Ports The following general-purpose port functions and control pin functions are available. * V850ES/JC3-H (40 pin) Port I/O Alternate Function P0 1-bit I/O External interrupt, A/D converter trigger, serial interface P3 4-bit I/O Serial interface, timer I/O P4 3-bit I/O Serial interface, external interrupt P5 5-bit I/O Timer I/O, serial interface, real-time output, key interrupt input, debug I/O P7 5-bit I/O A/D converter analog input P9 6-bit I/O External interrupt PDL 1-bit I/O External address/data bus * V850ES/JC3-H (48 pin) Port I/O Alternate Function P0 1-bit I/O External interrupt, A/D converter trigger, serial interface P1 1-bit I/O D/A converter analog output P3 6-bit I/O Serial interface, timer I/O P4 3-bit I/O Serial interface, external interrupt P5 5-bit I/O Timer I/O, serial interface, real-time output, key interrupt input, debug I/O P7 6-bit I/O A/D converter analog input P9 9-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt PDL 1-bit I/O External address/data bus R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 41 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 1 INTRODUCTION * V850ES/JE3-H Port I/O Alternate Function P0 2-bit I/O NMI, external interrupt, A/D converter trigger, serial interface P1 1-bit I/O D/A converter analog output P3 8-bit I/O External interrupt, real-time counter, serial interface, timer I/O P4 3-bit I/O Serial interface, external interrupt P5 5-bit I/O Timer I/O, real-time output, key interrupt input P6 6-bit I/O Timer I/O P7 10it I/O A/D converter analog input P9 9-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt PDL 1bit I/O External address/data bus R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 42 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins of the V850ES/JC3-H and V850ES/JE3-H are described below. There are four types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD and UVDD. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins V850ES/JC3-H (40 pin) AVREF0 Port 7 V850ES/JE3-H (64 pin) Port 7 Port 7 Port 1 Port 1 RESET, ports 0, 3 to 6, 9, RESET, ports 0, 3 to 6, 9, RESET, ports 0, 3 to 7, 9, DL DL, UDPF, UDMF DL, UDPF, UDMF - AVREF1 EVDD V850ES/JC3-H (48 pin) UVDD R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - - UDPF, UDMF Page 43 of 1442 V850ES/JC3-H, V850ES/JE3-H <R> CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/2) Pin Name I/O Function Pin No. Alternate Function JE3-H JC3-H 40 pin 48 pin P02 I/O Port 3 1-bit I/O port (JC3-H (40 pin)) P03 NMI - - 19 INTP02/ADTRG/UCLK 11 13 20 ANO0 - 3 3 TXDC0/SOF4/INTP07 17 21 29 1-bit I/O port (JC3-H (48 pin)) 2-bit I/O port (JE3-H ) Input/output can be specified in 1-bit units. 5 V tolerant. P10 I/O Port 1 1-bit I/O port Input/output can be specified in 1-bit units. I/O P30 Port 3 P31 4-bit I/O port (JC3-H (40 pin)) RXDC0/SIF4/INTP08 18 22 30 P32 6-bit I/O port (JC3-H (48 pin)) ASCKC0/SCKF4/TIAA00/TOAA00 19 23 31 TIAA01/TOAA01/RTCDIV/RTCCL - - 35 TIAA10/TOAA10/TOAA1OFF/INTP09 - - 26 TIAA10/TOAA10/ INTP09 16 18 - TIAA11/TOAA11/RTC1HZ - - 36 - 19 27 - 20 28 8-bit I/O port (JE3-H ) P33 Input/output can be specified in 1-bit units. P34 5 V tolerant. P35 P36 TXDC3/SCL00/CTXD0 P37 Note RXDC3/SDA00/CRXD0 I/O P40 Port 4 Note SIF0/TXDC4/SDA01 20 24 32 SOF0/RXDC4/SCL01 21 25 33 SCKF0/INTP10 22 26 34 KR2/RTP02/DDI 23 27 37 SIF2/KR3/RTP03/DDO 24 28 38 SOF2/KR4/RTP04/DCK 25 29 39 P55 SCKF2/KR5/RTP05/DMS 26 30 40 P56 INTP05/DRST 27 31 41 TOAB1T1/TOAB11/TIAB11 - - 13 3-bit I/O port P41 Input/output can be specified in 1-bit units. P42 5 V tolerant. I/O P52 Port 5 5-bit I/O port P53 Input/output can be specified in 1-bit units. P54 5 V tolerant. P60 I/O Port 6 6-bit I/O port TOAB1B1/TIAB10/TOAB10 - - 14 TOAB1T2/TOAB12/TIAB12 - - 15 P63 TOAB1B2/TRGAB1 - - 16 P64 TOAB1T3/TOAB13/TIAB13 - - 17 P65 TOAB1B3/EVTAB1 - - 18 P61 Input/output can be specified in 1-bit units. P62 Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 44 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name I/O Function Alternate Function Pin No. JE3-H JC3-H 40 pin 48 pin ANI0 40 48 64 ANI1 39 47 63 ANI2 38 46 62 ANI3 37 45 61 P74 ANI4 36 44 60 P75 ANI5 - 43 59 P76 ANI6 - - 58 P77 ANI7 - - 57 P78 ANI8 - - 56 P70 I/O Port 7 5-bit I/O port (JC3-H (40 pin )) P71 6-bit I/O port (JC3-H (48 pin) ) P72 10-bit I/O port (JE3-H) P73 Input/output can be specified in 1-bit units. P79 ANI9 - - 55 TENC01/TIT01/TOT01 - 35 47 P93 6-bit I/O port (JC3-H (40 pin)) TECR0/TIT00/TOT00 - 36 48 P94 9-bit I/O port (JE3-H, JC3-H (48 pin)) TENC00/EVTT0 - 38 50 P96 TIAA21/TOAA21/INTP11 29 33 45 P97 TIAA20/TOAA20 30 34 46 P910 SIF3/TXDC2/INTP14 32 39 51 P911 SOF3/RXDC2/INTP15 33 40 52 P912 SCKF3 34 41 53 P913 TOAB1OFF/INTP16 - - 54 P92 I/O Port 9 Input/output can be specified in 1-bit units. PDL5 I/O Port DL INTP16 35 42 - FLMD1 31 37 49 1-bit I/O port Input/output can be specified in 1-bit units. Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 45 of 1442 V850ES/JC3-H, V850ES/JE3-H <R> CHAPTER 2 PIN FUNCTIONS (2) Non-port Pins (1/4) Pin Name I/O Function Alternate Function Pin No. JC3-H JE3-H 40 pin 48 pin ADTRG Input External trigger input for A/D converter 5 V tolerant. P03/INTP02/UCLK 11 13 20 ANI0 Input Analog voltage input for A/D converter P70 40 48 64 ANI1 P71 39 47 63 ANI2 P72 38 46 62 ANI3 P73 37 45 61 ANI4 P74 36 44 60 ANI5 P75 - 43 59 ANI6 P76 - - 58 ANI7 P77 - - 57 ANI8 P78 - - 56 ANI9 P79 - - 55 ANO0 Output ASCKC0 Input Analog voltage output for D/A converter P10 - 3 3 UARTC0 baud rate clock input, 5 V tolerant. P32/SCKF4/TIAA00/TOAA00 19 23 31 AVREF0 - Reference voltage input for A/D converter/positive power supply for port 7 - 1 1 1 AVREF1 - Reference voltage input for D/A converter/positive power supply for port 1 - - 4 4 - Ground potential for A/D and D/A converters - AVSS Note Input Note Output CRXD0 CTXD0 2 2 2 CAN receive data input P37/RXDC3/SDA00 - 20 28 CAN transmit data output P36/TXDC3/SCL00 - 19 27 DCK Input Clock input for on-chip debugging, 5 V tolerant. P54/SOF2/KR4/RTP04 25 29 39 DDI Input Data input for on-chip debugging, 5 V tolerant. P52/KR2/RTP02 23 27 37 DDO Output Data output for on-chip debugging In the on-chip debug mode, high-level output is forcibly set. 5 V tolerant. P53/SIF2/KR3/RTP03 24 28 38 DMS Input Mode select signal input for on-chip debugging, 5 V tolerant. P55/SCKF2/KR5/RTP05 26 30 40 DRST Input Reset signal input for on-chip debugging, 5 V tolerant. P56/INTP05 27 31 41 EVDD - 14 16 24, 44 P94/ TENC00 - 38 50 P65/TOAB1B3 - - 18 28 32 42 31 37 49 - Positive power supply for external devices (same potential as VDD) EVTT0 Input External event count input of TMT0 EVTAB1 Input External event count input of TAB1 FLMD0 Input Flash memory programming mode setting pin FLMD1 Input - PDL5 Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 46 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name I/O Function Pin No. Alternate Function JE3-H JC3-H INTP02 Input INTP05 INTP07 INTP08 External interrupt request input (maskable, analog noise elimination) Analog noise elimination or digital noise elimination selectable for INTP02 pin. 5 V tolerant (INTP02, INTP05, INTP07, INTP08 to INTP10) . 40 pin 48 pin P03/ADTRG/UCLK 11 13 20 P56/DRST 27 31 41 P30/TXDC0/SOF4 17 21 29 P31/RXDC0/SIF4 18 22 30 P34/TIAA10/TOAA10/TOAA1OFF - - 26 P34/TIAA10/TOAA10 16 18 - INTP10 P42/SCKF0 22 26 34 INTP11 P96/TIAA21/TOAA21 29 33 45 INTP14 P910/SIF3/TXDC2 32 39 51 INTP15 P911/SOF3/RXDC2 33 40 52 INTP16 P913/TOAB1OFF - - 54 P913 35 42 - INTP09 KR2 Input KR3 Key interrupt input (on-chip analog noise eliminator) 5 V tolerant. KR4 KR5 NMI REGC Input - External interrupt input (non-maskable, analog noise elimination), 5 V tolerant. P52/RTP02/DDI 23 27 37 P53/SIF2/ RTP03/DDO 24 28 38 P54/SOF2/RTP04/DCK 25 29 39 P55/SCKF2/RTP05/DMS 26 30 40 P02 - - 19 4 6 6 - Connection of regulator output stabilization capacitance (4.7 F: Recommend value) - RESET Input 8 10 10 RTC1HZ Output Real-time counter correction clock (1 Hz) output, 5 V tolerant. P35/TIAA11/TOAA11 - - 36 RTCCL Output Real-time counter clock (32 kHz primary oscillation) output, 5 V tolerant. P33/TIAA01/TOAA01/RTCDIV - - 35 RTCDIV Output Real-time counter clock (32 kHz division) output, 5 V tolerant. P33/TIAA01/TOAA01/RTCCL - - 35 Real-time counter clock (32 kHz division) output, 5 V tolerant. P52/KR2/DDI 23 27 37 P53/SIF2/KR3/DDO 24 28 38 RTP02 RTP03 System reset input RTP04 P54/SOF2/KR4/DCK 25 29 39 RTP05 P55/SCKF2/KR5/DMS 26 30 40 P31/SIF4/INTP08 18 22 30 33 40 52 RXDC0 RXDC2 RXDC3 Input Serial receive data input (UARTC0, UARTC2 to UARTC4) 5 V tolerant (RXDC0, RXDC3, RXDC4). RXDC4 P911/SOF3/INTP15 P37/SDA00/CRXD0 - 20 28 P41/SOF0/SCL01 21 25 33 Note Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 47 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name I/O Function Alternate Function Pin No. JC3-H 48 pin P42/INTP10 22 26 34 SCKF2 Serial clock I/O (CSIF0, CSIF2 to CSIF4) N-ch open-drain output selectable P55/KR5/RTP05/DMS 26 30 40 SCKF3 5 V tolerant (SCKF0, SCKF2, SCKF4). P912 34 41 53 P32/ASCKC0/TIAA00/TOAA00 19 23 31 - 19 27 21 25 33 - 20 28 SCKF0 I/O JE3-H 40 pin SCKF4 SCL00 I/O SCL01 2 2 Serial clock I/O (I C00 to I C01) N-ch open-drain output selectable, P36/TXDC3/CTXD0 Note P41/SOF0/RXDC4 5 V tolerant. SDA00 I/O SDA01 SIF0 Input SIF2 SIF3 2 P37/RXDC3/CRXD0 P40/SIF0/TXDC4 20 24 32 Serial receive data input (CSIF0, CSIF2 to CSIF4) 5 V tolerant (SIF0, SIF3, SIF4). P40/TXDC4/SDA01 20 24 32 P53/KR3/RTP03/DDO 24 28 38 P910/TXDC2/INTP14 32 39 51 P31/RXDC0/INTP08 18 22 30 SIF4 SOF0 Output SOF2 SOF3 P41/RXDC4/SCL01 21 25 33 P54/KR4/RTP04/DCK 25 29 39 P911/RXDC2/INTP15 33 40 52 P30/TXDC0/INTP07 17 21 29 TMT0 encoder clear input P93/TIT00/TOT00 - 36 48 TMT0 encoder input P94/ EVTT0 - 38 50 Serial transmit data output (CSIF0, CSIF2 to CSIF4) 5 V tolerant (SOF0, SOF3, SOF4). SOF4 TECR0 Input TENC00 TENC01 External event count input/capture trigger TIAA00 Note Serial transmit/receive data I/O (I C00 to 2 I C01) N-ch open-drain output selectable, 5 V tolerant P92/TIT01/TOT01 - 35 47 P32/ASCKC0/SCKF4/TOAA00 19 23 31 input/external trigger input (TAA0), 5 V tolerant TIAA01 Capture trigger input (TAA0), 5 V tolerant P33/TOAA01/RTCDIV/RTCCL - - 35 TIAA10 External event count input/capture trigger P34/TOAA10/TOAA1OFF/INTP09 - - 26 input/external trigger input (TAA1), 5 V P34/TOAA10/INTP09 16 18 - tolerant TIAA11 Capture trigger input (TAA1), 5 V tolerant P35/TOAA11/RTC1HZ - - 36 TIAA20 External event count input/capture trigger P97/TOAA20 30 34 46 input/external trigger input (TAA2) TIAA21 Capture trigger input (TAA2) P96/TOAA21/INTP11 29 33 45 TIAB10 Capture trigger input (TAB1) P61/TOAB1B1/TOAB10 - - 14 P60/TOAB1T1/TOAB11 - - 13 TIAB12 P62/TOAB1T2/TOAB12 - - 15 TIAB13 P64/TOAB1T3/TOAB13 - - 17 P93/TECR0/TOT00 - 36 48 TMT0 capture trigger input P92/TENC01/TOT01 - 35 47 Timer output (TAA0) P32/ASCKC0/SCKF4/TIAA00 19 23 31 N-ch open-drain output selectable, 5 V P33/TIAA01/RTCDIV/RTCCL - - 35 TIAB11 TMT0 external trigger input/capture TIT00 trigger input TIT01 TOAA00 TOAA01 Output tolerant Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 48 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name I/O Function Alternate Function Pin No. JE3-H JC3-H TOAA10 Output Timer output (TAA1) N-ch open-drain output selectable 40 pin 48 pin P34/TIAA10/TOAA1OFF/INTP09 - - 26 P34/TIAA10/INTP09 16 18 - P35/TIAA11/RTC1HZ - - 36 P34/TIAA10/TOAA10/INTP09 - - 26 5 V tolerant TOAA11 TAA1 high-impedance output control TOAA1OFF signal input, 5 V tolerant TOAA20 Timer output (TAA2) P97/TIAA20 30 34 46 TOAA21 N-ch open-drain output selectable P96/TIAA21/INTP11 29 33 45 TOAB10 Timer output (TAB1) P61/TOAB1B1/TIAB10 - - 14 TOAB11 P60/TOAB1T1/TIAB11 - - 13 TOAB12 P62/TOAB1T2/TIAB12 - - 15 P64/TOAB1T3/TIAB13 - - 17 Pulse signal output for 6-phase PWM P61/TIAB10/TOAB10 - - 14 low-arm of TAB1 P63/TRGAB1 - - 16 P65/EVTAB1 - - 18 P913/INTP16 - - 54 Pulse signal output for 6-phase PWM P60/TOAB11/TIAB11 - - 13 high-arm of TAB1 P62/TIAB12/TOAB12 - - 15 P64/TOAB13/TIAB13 - - 17 TOAB13 Output TOAB1B1 TOAB1B2 TOAB1B3 TAB1 high-impedance output control TOAB1OFF signal input TOAB1T1 Output TOAB1T2 TOAB1T3 TOT00 Output P93/TECR0/TIT00 - 36 48 P92/TENC01/TIT01 - 35 47 External trigger input of TAB1 P63/TOAB1B2 - - 16 Serial transmit data output (UARTC0, P30/SOF4/INTP07 17 21 29 UARTC2 to UARTC4) P910/SIF3/INTP14 32 39 51 - 19 27 P40/SIF0/SDA01 20 24 32 P03/INTP02/ADTRG 11 13 20 TMT0 timer output TOT01 TRGAB1 TXDC0 Input Output TXDC2 N-ch open-drain output selectable TXDC3 5 V tolerant (TXDC0, TXDC3, TXDC4) . TXDC4 UCLK Input UDMF I/O UDPF USB clock signal input, 5 V tolerant. P36/SCL00/CTXD0 Note USB data I/O (-) function - 12 14 21 USB data I/O (+) function - 13 15 22 UVDD - 3.3 V Positive power supply for USB - - - 23 VDD - Positive power supply pin for internal unit - 3 5 5 VSS - Ground potential for internal unit/ - 5, 15 7, 17 7, 25, 43 Ground potential for external (same potential as VSS) X1 X2 Input Connection of resonator for main clock - XT1 Input XT2 - Connection of resonator for subclock - 6 - 7 9 9 - 9 11 11 - 10 12 12 8 8 Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 49 of 1442 V850ES/JC3-H, V850ES/JE3-H 2.2 CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various operation modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power Is During Reset Turned On Note 1 (Other than HALT Note 2 Mode When Power Is STOP IDLE1, IDLE2, Sub-IDLE Mode Mode Idle State Note 3 Bus Hold Note 2 Note 2 Turned On) DRST Pull down DDO Pull down Undefined P10/ANO0 Note 6 Other port pins Note 4 Note 5 Hi-Z Held Held Held Held Held Held Held Held Held Held Undefined Hi-Z Held Held Held Held Held Hi-Z Hi-Z Held Held Held Held Held Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit) when the power is turned on. 2. Operates while alternate functions are operating. 3. The state of the pins in the idle state inserted after the T3 state is shown. 4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the state of this pin differs according to the OCDM.OCDM0 bit setting. 5. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 6. V850ES/JC3-H (48 pin), V850ES/JE3-H only Remark Hi-Z: High impedance Held: The state during the immediately preceding external bus cycle is held. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 50 of 1442 V850ES/JC3-H, V850ES/JE3-H 2.3 CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/3) Pin Alternate Function I/O Circuit Recommended Connection Type Name Pin No. JC3-H JE3-H 40 pin 48 pin P02 NMI 10-D - - Output: Leave open. Input: - Independently connect to EVDD or VSS via a resistor. Input: Independently connect to EVDD or VSS via a resistor. P03 INTP02/ADTRG/UCLK 10-D P10 ANO0 12-D Independently connect to AVREF1 or AVSS via a resistor. Output: Leave open. P30 P31 10-D TXDC0/SOF4/INTP07 Input: RXDC0/SIF4/INTP08 Output: Leave open. P32 ASCKC0/SCKF4/TIAA00/TOAA00 P33 TIAA01/TOAA01/RTCDIV/RTCCL - - P34 TIAA10/TOAA10/TOAA1OFF/INTP09 - - TIAA10/TOAA10/ INTP09 - P35 TIAA11/TOAA11/RTC1HZ - - - - Independently connect to EVDD or VSS via a resistor. Independently connect to EVDD or VSS via a resistor. P36 TXDC3/SCL00/CTXD0 Note P37 RXDC3/SDA00/CRXD0 P40 SIF0/TXDC4/SDA01 P41 Note 10-D Input: SOF0/RXDC4/SCL01 P42 SCKF0/INTP10 P52 KR2/RTP02/DDI Output: Leave open. 10-D Input: P53 SIF2/KR3/RTP03/DDO P54 SOF2/KR4/RTP04/DCK P55 SCKF2/KR5/RTP05/DMS P56 INTP05/DRST P60 TOAB1T1/TIAB11/TOAB11 - - P61 TOAB1B1/TIAB10/TOAB10 - - P62 TOAB1T2/TIAB12/TOAB12 - - P63 TOAB1B2/TRGAB1 - - P64 TOAB1T3/TIAB13/TOAB13 - - P70 to P74 ANI0 to ANI4 P75 ANI5 P76 to P79 ANI6 to ANI9 Output: Leave open. 5 11-G Independently connect to EVDD or VSS via a resistor. Output: Leave open. Input: Input: Independently connect to AVREF1 or AVSS via a resistor. Output: Leave open. - - - Note PD70F3819, 70F3825 only Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 51 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (2/3) Pin Name Alternate Function I/O Circuit Type Recommended Connection Pin No. JC3-H JE3-H 40 pin 48 pin P92 TENC01/TIT01/TOT01 5 Input: Independently connect to EVDD or - VSS via a resistor. - - P93 TECR0/TIT00/TOT00 P94 TENC00/EVTT0 P96 TIAA21/TOAA21/INTP11 P97 SIF1/TIAA20/TOAA20 P910 SIF3/TXDC2/INTP14 P911 SOF3/RXDC2/INTP15 P912 SCKF3 P913 TOAB1OFF/INTP16 - - INTP16 - PDL5 Output: Leave open. AD5/FLMD1 5 Input: Independently connect to EVDD or VSS via a resistor. Output: Leave open. - AVREF0 - Always connect to power supply. (The same - AVREF1 - - applies during standby.) AVSS - - Always directly connect to ground. (The same applies during standby.) - DCK - Always connect to power supply. (The same DDI - - applies during standby.) DDO - - Leave open. DMS - - Always connect to power supply. (The same - - applies during standby.) - DRST - Always directly connect to ground. (The same applies during standby.) - EVDD - Always connect to power supply. (The same applies during standby.) - FLMD0 - Directly connect to VSS in other than flash mode. FLMD1 - PDL5 Directly connect to VSS in other than flash mode. REGC - - Connect to regulator output stabilization capacitor. RESET - 2 UDMF - - - Always directly connect to ground via a resistor. UDPF - - Always directly connect to ground. (The same applies during standby.) UVDD - - Always connect to power supply. (The same applies during standby.) VDD - - Always connect to power supply. (The same applies during standby.) Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 52 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (3/3) Pin Alternate Function Name I/O Circuit Pin No. Recommended Connection Type JC3-H JE3-H 40 pin 48 pin 64 pin VSS - - Always directly connect to ground. (The same applies during standby.) X1 - - - X2 - - - XT1 - 16-C Connect to VSS via a resistor. XT2 - 16-C Leave open. Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 53 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 11-G Type 2 AVREF0 Data IN P-ch IN/OUT Output disable N-ch Schmitt-triggered input with hysteresis characteristics AVSS EVDD Data P-ch VREF0 (Threshold voltage) IN/OUT Output disable P-ch Comparator + _ Type 5 N-ch N-ch AVSS Input enable Type 12-D VSS AVREF1 Input enable Type 10-D EVDD Data P-ch Output disable N-ch IN/OUT AVSS Data P-ch Input enable IN/OUT Open drain P-ch Analog output N-ch Output disable Note VSS N-ch Type 16-C Feedback cut-off Input enable P-ch XT1 XT2 Note Hysteresis characteristics are not available in port mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 54 of 1442 V850ES/JC3-H, V850ES/JE3-H 2.4 CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. * P10/ANO0 pin * P53/SIF2/KR3/RTP03/DDO pin R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 55 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JC3-H and V850ES/JE3-H is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 20.8 ns (operating with main clock (fXX) of 48 MHz: VDD = 2.85 to 3.6 V) 30.5 s (operating with subclock (fXT) of 32.768 kHz) Memory space Program (physical address) space: 64 MB linear Data (logical address) space: 4 GB linear General-purpose registers: 32 bits x 32 registers Internal 32-bit architecture 5-stage pipeline control Multiplication/division instruction Saturation operation instruction 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 56 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.2 CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JC3-H and V850ES/JE3-H can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User's Manual. (1) Program register set 31 r0 (2) System register set 0 31 0 (Zero register) EIPC (Interrupt status saving register) (Assembler-reserved register) EIPSW (Interrupt status saving register) r3 (Stack pointer (SP)) FEPC (NMI status saving register) r4 (Global pointer (GP)) FEPSW (NMI status saving register) r5 (Text pointer (TP)) r1 r2 r6 ECR (Interrupt source register) PSW (Program status word) CTPC (CALLT execution status saving register) r7 r8 r9 r10 r11 CTPSW (CALLT execution status saving register) r12 r13 DBPC r14 (Exception/debug trap status saving register) DBPSW (Exception/debug trap status saving register) r15 r16 CTBP r17 (CALLT base pointer) r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (Element pointer (EP)) r31 (Link pointer (LP)) 31 PC 0 (Program counter) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 57 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.2.1 CHAPTER 3 CPU FUNCTION Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. When using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does not use r2, it can be used as a register for variables. Table 3-1. Program Registers Name Usage Operation r0 Zero register Always holds 0. r1 Assembler-reserved register Used as working register to create 32-bit immediate data r2 Register for address/data variable (if real-time OS does not use r2) r3 Stack pointer Used to create a stack frame when a function is called r4 Global pointer Used to access a global variable in the data area r5 Text pointer Used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 Register for address/data variable r30 Element pointer Used as base pointer to access memory r31 Link pointer Used when the compiler calls a function PC Program counter Holds the instruction address during program execution Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the CA850 (C Compiler Package) Assembly Language User's Manual. (2) Program counter (PC) The program counter holds the instruction address during program execution. The lower 32 bits of this register are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs. Bit 0 is fixed to 0. This means that execution cannot branch to an odd address. 31 PC 26 25 Fixed to 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 1 0 Instruction address during program execution 0 Default value 00000000H Page 58 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.2.2 CHAPTER 3 CPU FUNCTION System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2. System Register Numbers System System Register Name Register Operand Specification LDSR Instruction STSR Instruction Number Note 1 0 Interrupt status saving register (EIPC) 1 Interrupt status saving register (EIPSW) Note 1 Note 1 2 NMI status saving register (FEPC) 3 NMI status saving register (FEPSW) 4 Interrupt source register (ECR) x 5 Program status word (PSW) Reserved for future function expansion (operation is not guaranteed if these x x 6 to 15 Note 1 registers are accessed) 16 CALLT execution status saving register (CTPC) 17 CALLT execution status saving register (CTPSW) Exception/debug trap status saving register (DBPC) 19 Exception/debug trap status saving register (DBPSW) 20 CALLT base pointer (CTBP) Reserved for future function expansion (operation is not guaranteed if these x x 18 21 to 31 Note 2 Note 2 Note 2 Note 2 registers are accessed) Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction or illegal opcode and DBRET instruction execution. Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when execution is returned to the main routine by the RETI instruction after interrupt servicing (this is because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0). Remark : Can be accessed x: Access prohibited R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 59 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs). The address of the instruction next to the instruction under execution, except some instructions (see 23.8 Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable interrupt occurs. The current contents of the PSW are saved to EIPSW. Because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always fixed to 0). The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction. 31 EIPC 0 0 0 0 0 0 31 EIPSW 26 25 0 Default value 0xxxxxxxH (x: Undefined) (Contents of saved PC) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 (Contents of saved PSW) Default value 000000xxH (x: Undefined) Page 60 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs. The current contents of the PSW are saved to FEPSW. Because only one set of NMI status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always fixed to 0). The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction. 31 FEPC 26 25 0 0 0 0 0 0 0 31 FEPSW Default value 0xxxxxxxH (x: Undefined) (Contents of saved PC) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value 000000xxH (x: Undefined) (Contents of saved PSW) (3) Interrupt source register (ECR) The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs. This register holds the exception code of each interrupt source. Because this register is a read-only register, data cannot be written to this register using the LDSR instruction. 31 16 15 ECR Bit position FECC Bit name 0 EICC Meaning 31 to 16 FECC Exception code of non-maskable interrupt (NMI) 15 to 0 EICC Exception code of exception or maskable interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Default value 00000000H Page 61 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will not be acknowledged while the LDSR instruction is being executed. Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 8 7 6 5 4 3 2 1 0 PSW NP EP ID SAT CY OV S Z RFU Bit position Flag name Default value 00000020H Meaning 31 to 8 RFU Reserved field. Fixed to 0. 7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an NMI request is acknowledged, disabling multiple interrupts. 0: NMI is not being serviced. 1: NMI is being serviced. 6 Indicates that an exception is being processed. This bit is set to 1 when an exception occurs. EP Even if this bit is set, interrupt requests are acknowledged. 0: Exception is not being processed. 1: Exception is being processed. 5 Indicates whether a maskable interrupt can be acknowledged. ID 0: Interrupt enabled 1: Interrupt disabled 4 Note SAT Indicates that the result of a saturation operation has overflowed and is saturated. Because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: Not saturated 1: Saturated 3 Indicates whether a carry or a borrow occurs as a result of an operation. CY 0: Carry or borrow does not occur. 1: Carry or borrow occurs. 2 OV Note Indicates whether an overflow occurs during operation. 0: Overflow does not occur. 1: Overflow occurs. 1 S Note Indicates whether the result of an operation is negative. 0: The result is positive or 0. 1: The result is negative. 0 Z Indicates whether the result of an operation is 0. 0: The result is not 0. 1: The result is 0. Remark Also read Note on the next page. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 62 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed. Status of Operation Result Result of Operation of Flag Status SAT OV S Saturation Processing Maximum positive value is exceeded 1 1 0 7FFFFFFFH Maximum negative value is exceeded 1 1 1 80000000H Positive (maximum value is not exceeded) Holds value 0 0 Operation result itself Negative (maximum value is not exceeded) before operation 1 (5) CALLT execution status saving registers (CTPC and CTPSW) CTPC and CTPSW are CALLT execution status saving registers. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those of the program status word (PSW) are saved to CTPSW. The contents saved to CTPC are the address of the instruction next to CALLT. The current contents of the PSW are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0). 31 CTPC 0 0 0 0 0 0 31 CTPSW 26 25 0 Default value 0xxxxxxxH (x: Undefined) (Saved PC contents) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 (Saved PSW contents) Default value 000000xxH (x: Undefined) Page 63 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. The current contents of the PSW are saved to DBPSW. This register can be read or written only during the interval between the execution of the DBTRAP instruction or illegal opcode and the DBRET instruction. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0). The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction. 31 DBPC 26 25 0 0 0 0 0 0 0 31 DBPSW Default value 0xxxxxxxH (x: Undefined) (Saved PC contents) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value 000000xxH (x: Undefined) (Saved PSW contents) (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0). Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 CTBP 26 25 0 0 0 0 0 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 (Base address) 0 Default value 0xxxxxxxH (x: Undefined) Page 64 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.3 CHAPTER 3 CPU FUNCTION Operation Modes The V850ES/JC3-H and V850ES/JE3-H have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started. (2) Flash memory programming mode In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/JC3-H and V850ES/JE3-H are provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications. For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION. 3.3.1 Specifying operation mode Specify the operation mode by using the FLMD0 and FLMD1 pins. In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released. In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. Operation When Reset Is Released Operation Mode After Reset FLMD0 FLMD1 L x Normal operation mode H L Flash memory programming mode H H Setting prohibited Remark L: Low-level input H: High-level input x: Don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 65 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4 3.4.1 CHAPTER 3 CPU FUNCTION Address Space CPU address space For instruction addressing, up to a combined total of 16 MB of internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Image on Address Space Image 63 4 GB Data space Peripheral I/O area Program space Image 1 Use-prohibited area Internal RAM area Internal RAM area Use-prohibited area 64 MB Use-prohibited area 64 MB Image 0 Internal ROM area (user flash area) Internal ROM area (user flash area) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 66 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.2 CHAPTER 3 CPU FUNCTION Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses. That the highest address and the lowest address of the program space are contiguous in this way is called wraparound. Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O area, instructions cannot be fetched from this area. Therefore, do not execute an operation in which the result of a branch address calculation affects this area. 00000001H Program space 00000000H (+) direction (-) direction 03FFFFFFH 03FFFFFEH Program space (2) Data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous, and wraparound occurs at the boundary of these addresses. 00000001H Data space 00000000H (+) direction (-) direction FFFFFFFFH FFFFFFFEH Data space R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 67 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.3 CHAPTER 3 CPU FUNCTION Memory map The areas shown below are reserved in the V850ES/JC3-H and V850ES/JE3-H. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH On-chip peripheral I/O area (4 KB) (80 KB) 03FFFFFFH 03FFF000H 03FFEFFFH 03FEC000H 03FEBFFFH Internal RAM area (60 KB) Note 1 Use prohibited 03FE0000H 03FEFFFFH 03FEF000H 03FEEFFFH Programmable peripheral I/O areaNote 2 or use prohibitedNote 3 03FEC000H 003FFFFFH Use prohibited Use prohibited USB function area (Use prohibited) 00280000H 0027FFFFH 00240000H 0023FFFFH USB function area (Peripheral I/O area) 00200000H 00400000H 003FFFFFH 001FFFFFH (2 MB) Use prohibited 00200000H 001FFFFFH 00100000H 000FFFFFH (2 MB) 00000000H Internal ROM area (1 MB) 00000000H Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because they overlap an on-chip peripheral I/O area. 2. The programmable peripheral I/O area is seen as 256 MB areas in the 4 GB address space. 3. In on-chip CAN controller products, addresses 03FEC000H to 03FEEFFFH are assigned to addresses 03FEC000H to 03FECBFFH as a programmable peripheral I/O area. In other products, use of this area is prohibited. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 68 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Use prohibited (program fetch prohibited area) Internal RAM area (60 KB) 03FFE000H 03FEFFFFH Use prohibited 00100000H 000FFFFFH 00000000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Internal ROM area (1 MB) Page 69 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.4 CHAPTER 3 CPU FUNCTION Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (16 KB) 16 KB are allocated to addresses 00000000H to 00003FFFH in the following products. Accessing addresses 00004000H to 000FFFFFH is prohibited. * PD70F3809, 70F3814, 70F3820 Figure 3-4. Internal ROM Area (16 KB) 000FFFFFH Access-prohibited area 00004000H 00003FFFH 00000000H Internal ROM (16 KB) (b) Internal ROM (32 KB) 32 KB are allocated to addresses 00000000H to 00007FFFH in the following products. Accessing addresses 00008000H to 000FFFFFH is prohibited. * PD70F3810, 70F3815, 70F3821 Figure 3-5. Internal ROM Area (32 KB) 000FFFFFH Access-prohibited area 00008000H 00007FFFH 00000000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Internal ROM (32 KB) Page 70 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (c) Internal ROM (64 KB) 64 KB are allocated to addresses 00000000H to 0000FFFFH in the following products. Accessing addresses 00010000H to 000FFFFFH is prohibited. * PD70F3811, 70F3816, 70F3822 Figure 3-6. Internal ROM Area (64 KB) 000FFFFFH Access-prohibited area 00010000H 0000FFFFH Internal ROM (64 KB) 00000000H (d) Internal ROM (128 KB) 128 KB are allocated to addresses 00000000H to 0001FFFFH in the following products. Accessing addresses 00020000H to 000FFFFFH is prohibited. * PD70F3812, 70F3817, 70F3823 Figure 3-7. Internal ROM Area (128 KB) 000FFFFFH Access-prohibited area 00020000H 0001FFFFH Internal ROM (128 KB) 00000000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 71 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (e) Internal ROM (256 KB) 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products. Accessing addresses 00040000H to 000FFFFFH is prohibited. * PD70F3813, 70F3818, 70F3819, 70F3824, 70F3825 Figure 3-8. Internal ROM Area (256 KB) 000FFFFFH Access-prohibited area 00040000H 0003FFFFH Internal ROM (256 KB) 00000000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 72 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. The RAM capacity of V850ES/JC3-H and V850ES/JE3-H is as follows. Table 3-3 RAM area Generic Name V850ES/JC3-H (40 pin) V850ES/JC3-H (48 pin) V850ES/JE3-H Product Name Internal RAM PD70F3809 8 KB PD70F3810 16 KB PD70F3711, 70F3712, 70F3713 24 KB PD70F3814 8 KB PD70F3815 16 KB PD70F3816, 70F3817, 70F3818, 70F3819 24 KB PD70F3820 8 KB PD70F3821 16 KB PD70F3822, 70F3823, 70F3824, 70F3825 24 KB (a) Internal RAM (8 KB) 8 KB are allocated to addresses 03FFD000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FFCFFFH is prohibited. * PD70F3809, 70F3814, 70F3820 Figure 3-9. Internal RAM Area (8 KB) Physical address space 03FFEFFFH 03FFD000H 03FFCFFFH Logical address space Internal RAM (8 KB) FFFFEFFFH FFFFD000H FFFFCFFFH Access-prohibited area 03FF0000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 FFFF0000H Page 73 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (b) Internal RAM (16 KB) 16 KB are allocated to addresses 03FFB000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FFAFFFH is prohibited. * PD70F3810, 70F3815, 70F3821 Figure 3-10. Internal RAM Area (16 KB) Physical address space Logical address space FFFFEFFFH 03FFEFFFH Internal RAM (16 KB) 03FFB000H 03FFAFFFH FFFFB000H FFFFAFFFH Access-prohibited area 03FF0000H FFFF0000H (c) Internal RAM (24 KB) 24 KB are allocated to addresses 03FF9000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FF8FFFH is prohibited. * PD70F3816, 70F3817, 70F3818, 70F3819, 70F3822, 70F3823, 70F3824, 70F3825 Figure 3-11. Internal RAM Area (24 KB) Physical address space Logical address space FFFFEFFFH 03FFEFFFH Internal RAM (24 KB) 03FF9000H 03FF8FFFH FFFF9000H FFFF8FFFH Access-prohibited area 03FF0000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 FFFF0000H Page 74 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-13. On-Chip Peripheral I/O Area Physical address space Logical address space 03FFFFFFH FFFFFFFFH On-chip peripheral I/O area (4 KB) 03FFF000H FFFFF000H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area. Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. 3. Addresses not defined as registers are reserved for future expansion. The operation is undefined and not guaranteed when these addresses are accessed. 4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive addresses. When accessing the internal ROM/RAM area by incrementing or decrementing addresses using a pointer operation or such, be careful not to access the on-chip peripheral I/O area by mistakenly extending over the internal ROM/RAM area boundary. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 75 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.5 CHAPTER 3 CPU FUNCTION Recommended use of address space The architecture of the V850ES/JC3-H and V850ES/JE3-H requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer 32 KB can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access the following addresses. Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid fetch) straddling the on-chip peripheral I/O area does not occur. RAM Size Access Address 24 KB 03FF9000H to 03FFEFFFH 16 KB 03FFB000H to 03FFEFFFH 8 KB 03FFD000H to 03FFEFFFH R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 76 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2) Data space With the V850ES/JC3-H and V850ES/JE3-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H 32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers. Example: PD70F3822 0007FFFFH 00007FFFH Internal ROM area 32 KB On-chip peripheral I/O area 4 KB Internal RAM area 24 KB (R = ) 0 0 0 0 0 0 0 0 H FFFFF000H FFFFEFFFH FFFF9000H 4 KB FFFF8000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 77 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION Figure 3-14. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFFFFFFH FFFEC000H FFFEBFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFF9000H FFFEFFFFH FFFEC000H FFFEBFFFH 04000000H 03FFFFFFH Use prohibited 03FFF000H 03FFEFFFH Internal RAM 03FF9000H 03FEFFFFH 03FEC000H 03FEBFFFH Use prohibited Program space 64 MB Use prohibited 00100000H 000FFFFFH Internal ROM 00000000H 00100000H 000FFFFFH 00080000H 0007FFFFH 00000000H Remarks 1. Internal ROM Internal ROM indicates the recommended area. 2. This figure is the recommended memory map of the PD70F3822. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 78 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.6 CHAPTER 3 CPU FUNCTION Peripheral I/O registers (1/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF004H FFFFF004H FFFFF024H FFFFF024H FFFFF044H FFFFF044H FFFFF064H Port DL register PDL Port DL register L PDLL Port DL mode register PMDL Port DL mode register L PMDLL Port DL mode control register PMCDL Port DL mode control register L PMCDLL Peripheral I/O area select control register BPC 8 16 R/W Note 00H Note 0000H FFFFH FFH 0000H 0000H 00H FFFFF06EH System wait control register VSWC FFFFF080H DMA source address register 0L DSA0L Undefined 77H FFFFF082H DMA source address register 0H DSA0H Undefined FFFFF084H DMA destination address register 0L DDA0L Undefined FFFFF086H DMA destination address register 0H DDA0H Undefined FFFFF088H DMA source address register 1L DSA1L Undefined FFFFF08AH DMA source address register 1H DSA1H Undefined FFFFF08CH DMA destination address register 1L DDA1L Undefined FFFFF08EH DMA destination address register 1H DDA1H Undefined FFFFF090H DMA source address register 2L DSA2L Undefined FFFFF092H DMA source address register 2H DSA2H Undefined FFFFF094H DMA destination address register 2L DDA2L Undefined FFFFF096H DMA destination address register 2H DDA2H Undefined FFFFF098H DMA source address register 3L DSA3L Undefined FFFFF09AH DMA source address register 3H DSA3H Undefined FFFFF09CH DMA destination address register 3L DDA3L Undefined FFFFF09EH DMA destination address register 3H DDA3H Undefined FFFFF0C0H DMA transfer count register 0 DBC0 Undefined FFFFF0C2H DMA transfer count register 1 DBC1 Undefined FFFFF0C4H DMA transfer count register 2 DBC2 Undefined FFFFF0C6H DMA transfer count register 3 DBC3 Undefined FFFFF0D0H DMA addressing control register 0 DADC0 0000H FFFFF0D2H DMA addressing control register 1 DADC1 0000H FFFFF0D4H DMA addressing control register 2 DADC2 0000H FFFFF0D6H DMA addressing control register 3 DADC3 0000H FFFFF0E0H DMA channel control register 0 DCHC0 00H FFFFF0E2H DMA channel control register 1 DCHC1 00H FFFFF0E4H DMA channel control register 2 DCHC2 00H FFFFF0E6H DMA channel control register 3 DCHC3 00H FFFFF100H Interrupt mask register 0 IMR0 FFFFF100H Interrupt mask register 0L IMR0L FFH FFFFF101H Interrupt mask register 0H IMR0H FFH Note FFFFH The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 79 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF102H 8 IMR1 FFFFF102H Interrupt mask register 1L IMR1L FFFFF103H Interrupt mask register 1H IMR1H Interrupt mask register 2 IMR2 FFFFF104H 16 R/W Interrupt mask register 1 FFFFH FFH FFH FFFFH FFFFF104H Interrupt mask register 2L IMR2L FFH FFFFF105H Interrupt mask register 2H IMR2H FFH Interrupt mask register 3 IMR3 FFFFF106H FFFFH FFFFF106H Interrupt mask register 3L IMR3L FFH FFFFF107H Interrupt mask register 3H IMR3H FFH Interrupt mask register 4 IMR4 FFFFF108H FFFFH FFFFF108H Interrupt mask register 4L IMR4L FFH FFFFF109H Interrupt mask register 4H IMR4H FFH FFFFF10AH Interrupt mask register 5 IMR5 FFFFF10AH Interrupt mask register 5L IMR5L FFH FFFFH FFFFF10BH Interrupt mask register 5H IMR5H FFH FFFFF110H Interrupt control register LVIIC 47H FFFFF116H Interrupt control register PIC02 47H FFFFF11CH Interrupt control register PIC05 47H FFFFF120H Interrupt control register PIC07 47H FFFFF122H Interrupt control register PIC08 47H FFFFF124H Interrupt control register PIC09 47H FFFFF126H Interrupt control register PIC10 47H FFFFF128H Interrupt control register PIC11 47H FFFFF12EH Interrupt control register PIC14 47H FFFFF130H Interrupt control register PIC15 47H FFFFF132H Interrupt control register PIC16 47H FFFFF142H Interrupt control register TAB1OVIC 47H FFFFF144H Interrupt control register TAB1CCIC0 47H FFFFF146H Interrupt control register TAB1CCIC1 47H FFFFF148H Interrupt control register TAB1CCIC2 47H FFFFF14AH Interrupt control register TAB1CCIC3 47H FFFFF14CH Interrupt control register TT0OVIC 47H FFFFF14EH Interrupt control register TT0CCIC0 47H FFFFF150H Interrupt control register TT0CCIC1 47H FFFFF152H Interrupt control register TT0IECIC 47H FFFFF154H Interrupt control register TAA0OVIC 47H FFFFF156H Interrupt control register TAA0CCIC0 47H FFFFF158H Interrupt control register TAA0CCIC1 47H FFFFF15AH Interrupt control register TAA1OVIC 47H FFFFF15CH Interrupt control register TAA1CCIC0 47H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 80 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (3/12) Address Function Register Name Symbol R/W R/W TAA1CCIC1 Manipulatable Bits Default Value 1 8 16 47H FFFFF15EH Interrupt control register FFFFF160H Interrupt control register TAA2OVIC 47H FFFFF162H Interrupt control register TAA2CCIC0 47H FFFFF164H Interrupt control register TAA2CCIC1 47H FFFFF16CH Interrupt control register TAA4OVIC 47H FFFFF16EH Interrupt control register TAA4CCIC0 47H FFFFF170H Interrupt control register TAA4CCIC1 47H FFFFF178H Interrupt control register TM0EQIC0 47H FFFFF17AH Interrupt control register TM1EQIC0 47H FFFFF17CH Interrupt control register TM2EQIC0 47H FFFFF17EH Interrupt control register TM3EQIC0 47H FFFFF180H Interrupt control register CF0RIC/IICIC1 47H FFFFF182H Interrupt control register CF0TIC 47H FFFFF188H Interrupt control register CF2RIC 47H FFFFF18AH Interrupt control register CF2TIC 47H FFFFF18CH Interrupt control register CF3RIC 47H FFFFF18EH Interrupt control register CF3TIC 47H FFFFF190H Interrupt control register CF4RIC 47H FFFFF192H Interrupt control register CF4TIC 47H FFFFF194H Interrupt control register UC0RIC 47H FFFFF196H Interrupt control register UC0TIC 47H FFFFF19CH Interrupt control register UC2RIC 47H FFFFF19EH Interrupt control register UC2TIC 47H 47H 47H UC4RIC 47H Interrupt control register UC4TIC 47H Interrupt control register ADIC 47H Interrupt control register DMAIC0 47H Interrupt control register DMAIC1 47H Interrupt control register DMAIC2 47H Interrupt control register DMAIC3 47H FFFFF1B2H Interrupt control register KRIC 47H FFFFF1B4H Interrupt control register RTC0IC 47H FFFFF1B6H Interrupt control register RTC1IC 47H FFFFF1B8H Interrupt control register RTC2IC 47H FFFFF1BAH Interrupt control register ERRIC0 47H FFFFF1BCH Interrupt control register WUPIC0 47H FFFFF1BEH Interrupt control register RECIC0 47H FFFFF1C0H Interrupt control register TRXIC0 47H FFFFF1C8H Interrupt control register UFIC0 47H FFFFF1CAH Interrupt control register UFIC1 47H FFFFF1A0H Interrupt control register UC3RIC/IICIC0 FFFFF1A2H Interrupt control register UC3TIC FFFFF1A4H Interrupt control register FFFFF1A6H FFFFF1A8H FFFFF1AAH FFFFF1ACH FFFFF1AEH FFFFF1B0H Note Note Note V850ES/JC3-H (48 pin), V850ES/JE3-H only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 81 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (4/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 00H Undefined FFFFF1FAH In-service priority register ISPR R FFFFF1FCH Command register PRCMD W FFFFF1FEH Power save control register PSC 00H FFFFF200H A/D converter mode register 0 ADA0M0 00H FFFFF201H A/D converter mode register 1 ADA0M1 00H FFFFF202H A/D converter channel specification register ADA0S 00H FFFFF203H A/D converter mode register 2 ADA0M2 00H R/W FFFFF204H Power-fail compare mode register ADA0PFM 00H FFFFF205H Power-fail compare threshold value register ADA0PFT 00H FFFFF210H A/D conversion result register 0 ADA0CR0 A/D conversion result register 0H ADA0CR0H A/D conversion result register 1 ADA0CR1 A/D conversion result register 1H ADA0CR1H A/D conversion result register 2 ADA0CR2 FFFFF211H FFFFF212H FFFFF213H FFFFF214H FFFFF215H FFFFF216H FFFFF217H FFFFF218H FFFFF219H FFFFF21AH FFFFF21BH FFFFF21CH FFFFF21DH FFFFF21EH FFFFF21FH FFFFF220H FFFFF221H FFFFF222H FFFFF223H A/D conversion result register 2H ADA0CR2H A/D conversion result register 3 ADA0CR3 A/D conversion result register 3H ADA0CR3H A/D conversion result register 4 ADA0CR4 A/D conversion result register 4H ADA0CR4H A/D conversion result register 5 ADA0CR5 A/D conversion result register 5H ADA0CR5H A/D conversion result register 6 ADA0CR6 A/D conversion result register 6H ADA0CR6H A/D conversion result register 7 ADA0CR7 A/D conversion result register 7H ADA0CR7H A/D conversion result register 8 ADA0CR8 A/D conversion result register 8H ADA0CR8H A/D conversion result register 9 ADA0CR9 A/D conversion result register 9H ADA0CR9H R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFFFF280H D/A conversion value setting register 0 DA0CS0 00H FFFFF282H D/A converter mode register DA0M 00H FFFFF300H Key return mode register KRM 00H 00H 00H R/W FFFFF308H Selector operation control register 0 SELCNT0 FFFFF310H CRC input register CRCIN FFFFF312H CRC data register CRCD FFFFF320H Prescaler mode register 1 PRSM1 00H FFFFF321H Prescaler compare register 1 PRSCM1 00H FFFFF324H Prescaler mode register 2 PRSM2 00H FFFFF325H Prescaler compare register 2 PRSCM2 00H FFFFF328H Prescaler mode register 3 PRSM3 00H FFFFF329H Prescaler compare register 3 PRSCM3 00H FFFFF340H IIC division clock select register 0 OCKS0 00H FFFFF344H IIC division clock select register 1 OCKS1 00H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0000H Page 82 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (5/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 00H Note 1 00H Note 2 FFFFF400H Port 0 register P0 FFFFF402H Port 1 register P1 R/W 16 FFFFF406H Port 3 register P3 00H FFFFF408H Port 4 register P4 00H FFFFF40AH Port 5 register P5 00H FFFFF40CH Port 6 register P6 00H FFFFF40EH Port 7 register L P7L 00H FFFFF40FH Port 7 register H P7H 00H FFFFF412H Port 9 register P9 FFFFF412H Port 9 register L P9L 00H Note 2 FFFFF413H Port 9 register H P9H 00H Note 2 FFFFF420H Port 0 mode register PM0 FFH FFFFF422H Port 1 mode register PM1 FFH FFFFF426H Port 3 mode register PM3 FFH FFFFF428H Port 4 mode register PM4 FFH FFFFF42AH Port 5 mode register PM5 FFH Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 0000H FFFFF42CH Port 6 mode register PM6 FFH FFFFF42EH Port 7 mode register L PM7L FFH FFFFF42FH Port 7 mode register H PM7H FFFFF432H Note 1 FFH FFFFH Port 9 mode register PM9 FFFFF432H Port 9 mode register L PM9L FFH FFFFF433H Port 9 mode register H PM9H FFH FFFFF440H Port 0 mode control register PMC0 00H FFFFF446H Port 3 mode control register PMC3 00H FFFFF448H Port 4 mode control register PMC4 00H FFFFF44AH Port 5 mode control register PMC5 FFFFF44CH Port 6 mode control register PMC6 FFFFF452H Port 9 mode control register PMC9 Note 1 00H 00H 0000H FFFFF452H Port 9 mode control register L PMC9L 00H FFFFF453H Port 9 mode control register H PMC9H 00H FFFFF460H Port 0 function control register PFC0 00H FFFFF466H Port 3 function control register PFC3 00H FFFFF468H Port 4 function control register PFC4 00H FFFFF46AH Port 5 function control register PFC5 00H FFFFF46CH FFFFF472H Port 6 function control register PFC6 Note 1 Note 2 00H 0000H Port 9 function control register PFC9 FFFFF472H Port 9 function control register L PFC9L FFFFF473H Port 9 function control register H PFC9H Data wait control register 0 DWC0 7777H FFFFF488H Address wait control register AWC FFFFH FFFFF48AH Bus cycle control register BCC AAAAH FFFFF484H 00H 00H Notes 1. V850ES/JE3-H only 2. The output latch is 00H or 0000H. When these registers are input, the pin statuses are read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 83 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (6/12) Address FFFFF560H Function Register Name TAB1 control register 0 Symbol R/W TAB1CTL0 Note R/W Manipulatable Bits Default Value 1 8 16 00H FFFFF561H TAB1 control register 1 TAB1CTL1 Note 00H FFFFF562H TAB1 I/O control register 0 TAB1IOC0 Note 00H FFFFF563H TAB1 I/O control register 1 TAB1IOC1 Note 00H FFFFF564H TAB1 I/O control register 2 TAB1IOC2 Note 00H FFFFF565H TAB1 option register 0 TAB1OPT0 Note FFFFF566H TAB1 capture/compare register 0 TAB1CCR0 Note 0000H FFFFF568H TAB1 capture/compare register 1 TAB1CCR1 Note 0000H FFFFF56AH TAB1 capture/compare register 2 TAB1CCR2 Note 0000H TAB1CCR3 Note 0000H 0000H FFFFF56CH TAB1 capture/compare register 3 Note FFFFF56EH TAB1 counter read buffer register TAB1CNT FFFFF570H TAB1 I/O control register 4 TAB1IOC4 Note FFFFF580H TAB1 option register 1 TAB1OPT1 Note FFFFF581H TAB1 option register 2 TAB1OPT2 Note R R/W Note FFFFF582H TAB1 I/O control register 3 TAB1IOC3 FFFFF584H TAB1 dead time compare register 1 TAB1DTC Note FFFFF590H High impedance output control register 0 HZACTL0 Note Note 00H 00H 00H 00H A8H 0000H 00H FFFFF591H High impedance output control register 1 HZACTL1 00H FFFFF600H TMT0 control register 0 TT0CTL0 00H FFFFF601H TMT0 control register 1 TT0CTL1 00H FFFFF602H TMT0 control register 2 TT0CTL2 00H FFFFF603H TMT0I/O control register 0 TT0IOC0 00H FFFFF604H TMT0I/O control register 1 TT0IOC1 00H FFFFF605H TMT0I/O control register 2 TT0IOC2 00H FFFFF606H TMT0I/O control register 3 TT0IOC3 00H FFFFF607H TMT0 option register 0 TT0OPT0 00H FFFFF608H TMT0 option register 1 TT0OPT1 00H FFFFF609H TMT0 option register 2 TT0OPT2 00H FFFFF60AH TMT0 capture/compare register 0 TT0CCR0 0000H FFFFF60CH TMT0 capture/compare register 1 TT0CCR1 0000H FFFFF60EH TMT0 counter read buffer register TT0CNT R 0000H FFFFF610H TMT0 counter write register TT0TCW R/W 0000H FFFFF630H TAA0 control register 0 TAA0CTL0 00H FFFFF631H TAA0 control register 1 TAA0CTL1 00H FFFFF632H TAA0 I/O control register 0 TAA0IOC0 00H FFFFF633H TAA0 I/O control register 1 TAA0IOC1 00H FFFFF634H TAA0 I/O control register 2 TAA0IOC2 00H FFFFF635H TAA0 option register 0 TAA0OPT0 FFFFF636H TAA0 capture/compare register 0 TAA0CCR0 FFFFF638H TAA0 capture/compare register 1 TAA0CCR1 FFFFF63AH TAA0 counter read buffer register TAA0CNT 00H R 0000H 0000H 0000H Note V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 84 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (7/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 00H TAA0OPT1 00H TAA1 control register 0 TAA1CTL0 00H TAA1 control register 1 TAA1CTL1 00H FFFFF642H TAA1 I/O control register 0 TAA1IOC0 00H FFFFF643H TAA1 I/O control register 1 TAA1IOC1 00H FFFFF644H TAA1 I/O control register 2 TAA1IOC2 00H FFFFF645H TAA1 option register 0 TAA1OPT0 00H FFFFF646H TAA1 capture/compare register 0 TAA1CCR0 0000H FFFFF648H TAA1 capture/compare register 1 TAA1CCR1 0000H FFFFF64AH TAA1 counter read buffer register TAA1CNT R 0000H R/W FFFFF63CH TAA0 I/O control register 4 TAA0IOC4 FFFFF63DH TAA0 option register 1 FFFFF640H FFFFF641H R/W 16 FFFFF64CH TAA1 I/O control register 4 TAA1IOC4 00H FFFFF650H TAA2 control register 0 TAA2CTL0 00H FFFFF651H TAA2 control register 1 TAA2CTL1 00H FFFFF652H TAA2 I/O control register 0 TAA2IOC0 00H FFFFF653H TAA2 I/O control register 1 TAA2IOC1 00H FFFFF654H TAA2 I/O control register 2 TAA2IOC2 00H FFFFF655H TAA2 option register 0 TAA2OPT0 00H FFFFF656H TAA2 capture/compare register 0 TAA2CCR0 0000H FFFFF658H TAA2 capture/compare register 1 TAA2CCR1 0000H FFFFF65AH TAA2 counter read buffer register TAA2CNT R 0000H FFFFF65CH TAA2 I/O control register 4 TAA2IOC4 R/W FFFFF65DH TAA2 option register 1 FFFFF670H TAA4 control register 0 00H TAA2OPT1 00H TAA4CTL0 00H FFFFF671H TAA4 control register 1 TAA4CTL1 FFFFF676H TAA4 capture compare register 0 TAA4CCR0 0000H 00H FFFFF678H TAA4 capture compare register 1 TAA4CCR1 0000H FFFFF67AH TAA4 counter read buffer register TAA4CNT FFFFF6C0H Oscillation stabilization time select register OSTS R R/W 0000H 06H FFFFF6C1H PLL lockup time specification register PLLS 03H FFFFF6D0H Watchdog timer mode register 2 WDTM2 67H FFFFF6D1H Watchdog timer enable register WDTE 9AH FFFFF6E0H Real-time output buffer register 0L RTBL0 00H FFFFF6E2H Real-time output buffer register 0H RTBH0 00H FFFFF6E4H Real-time output port mode register 0 RTPM0 00H FFFFF6E5H Real-time output port control register 0 RTPC0 00H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 85 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (8/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 00H PFCE3 00H PFCE4 00H 00H FFFFF700H Port 0 function control expansion register PFCE0 FFFFF706H Port 3 function control expansion register FFFFF708H Port 4 function control expansion register FFFFF70AH Port 5 function control expansion register PFCE5 R/W Note 16 FFFFF70CH Port 6 function control expansion register PFCE6 FFFFF712H Port 9 function control expansion register PFCE9 00H FFFFF712H Port 9 function control expansion register L PFCE9L 00H FFFFF713H Port 2 function control expansion register H PFCE9H 00H 0000H FFFFF724H TAA noise elimination control register TANFC 00H FFFFF726H TMT noise elimination control register TTNFC 00H FFFFF728H Noise elimination control register INTNFC 00H FFFFF802H System status register SYS 00H FFFFF80CH Internal oscillation mode register RCM 00H FFFFF810H DMA trigger factor register 0 DTFR0 00H FFFFF812H DMA trigger factor register 1 DTFR1 00H FFFFF814H DMA trigger factor register 2 DTFR2 00H FFFFF816-H DMA trigger factor register 3 DTFR3 00H FFFFF820H Power save mode register PSMR 00H FFFFF822H Clock control register CKC 0AH FFFFF824H Lock register LOCKR R 00H FFFFF828H Processor clock control register PCC R/W 03H FFFFF82CH PLL control register PLLCTL 01H FFFFF82EH CPU operation clock status register CCLS R 00H FFFFF870H Clock monitor mode register CLM R/W 00H FFFFF888H Reset source flag register RESF 00H FFFFF892H Internal RAM data status register RAMS 01H FFFFF8B0H Prescaler mode register 0 PRSM0 00H FFFFF8B1H Prescaler compare register 0 PRSCM0 00H FFFFFA00H UARTC0 control register 0 UC0CTL0 10H FFFFFA01H UARTC0 control register 1 UC0CTL1 FFFFFA03H UARTC0 option control register 0 UC0OPT0 FFFFFA04H UARTC0 status register UC0STR FFFFFA06H UARTC0 receive data register UC0RX FFFFFA06H UARTC0 receive data register L UC0RXL UARTC0 transmit data register UC0TX UARTC0 transmit data register L UC0TXL FFFFFA0AH UARTC0 option control register 1 UC0OPT1 FFFFFA20H UARTC2 control register 0 UC2CTL0 FFFFFA21H UARTC2 control register 1 FFFFFA22H UARTC2 control register 2 FFFFFA23H UARTC2 option control register 0 UC2OPT0 FFFFFA24H UARTC2 status register UC2STR FFFFFA08H FFFFFA08H 00H 14H R 00H 01FFH 01FFH R/W FFH FFH 00H 10H UC2CTL1 00H UC2CTL2 FFH 14H 00H Note V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 86 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (10/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFFA26H UC2RX UARTC2 receive data register L UC2RXL UARTC2 transmit data register UC2TX UARTC2 transmit data register L UC2TXL FFFFFA2AH UARTC2 option control register 1 UC2OPT1 FFFFFA30H UARTC3 control register 0 UC3CTL0 Note FFFFFA26H FFFFFA28H FFFFFA28H FFFFFA31H UARTC3 control register 1 UC3CTL1 FFFFFA32H UARTC3 control register 2 UC3CTL2 Note FFFFFA33H UARTC3 option control register 0 UC3OPT0 FFFFFA34H UARTC3 status register UC3STR FFFFFA36H UARTC3 receive data register UC3RX UARTC3 receive data register L UC3RXL UARTC3 transmit data register UC3TX FFFFFA38H FFFFFA38H 16 Note Note Note FFH 00H 10H 00H FFH 14H 00H R UARTC3 transmit data register L UC3TXL UARTC3 option control register 1 UC3OPT1 FFFFFA40H UARTC4 control register 0 UC4CTL0 FFFFFA41H UARTC4 control register 1 UC4CTL1 Note 01FFH FFH R/W Note FFFFFA3AH 01FFH Note Note 01FFH FFH R/W Note FFFFFA36H 8 R UARTC2 receive data register 01FFH FFH 00H 10H 00H FFFFFA42H UARTC4 control register 2 UC4CTL2 FFH FFFFFA43H UARTC4 option control register 0 UC4OPT0 14H FFFFFA44H UARTC4 status register UC4STR 00H FFFFFA46H FFFFFA46H FFFFFA48H UARTC4 receive data register UC4RX UARTC4 receive data register L UC4RXL UARTC4 transmit data register UC4TX UARTC4 transmit data register L UC4TXL FFFFFA4AH UARTC4 option control register 1 UC4OPT1 FFFFFA80H TMM0 control register 0 TM0CTL0 FFFFFA84H TMM0 compare register 0 TM0CMP0 FFFFFA90H TMM1 control register 0 TM1CTL0 FFFFFA94H TMM1 compare register 0 TM1CMP0 FFFFFAA0H TMM2 control register 0 TM2CTL0 FFFFFAA4H TMM2 compare register 0 TM2CMP0 FFFFFAB0H TMM3 control register 0 TM3CTL0 FFFFFAB4H TMM3 compare register 0 TM3CMP0 FFFFFAD0H Sub-count register RC1SUBC FFFFFAD2H Second count register RC1SEC FFFFFAD3H Minute count register FFFFFAD4H FFFFFAD5H FFFFFA48H R R/W 01FFH FFH 01FFH FFH 00H 00H 00H 0000H 0000H 0000H 0000H 00H R 0000H 00H 00H RC1MIN 00H Hour count register RC1HOUR 12H Week count register RC1WEEK 00H FFFFFAD6H Day count register RC1DAY 01H FFFFFAD7H Month count register RC1MONTH 01H FFFFFAD8H Year count register RC1YEAR 00H FFFFFAD9H Time error correction register RC1SUBU 00H FFFFFADAH Alarm minute set register RC1ALM 00H Note R/W V850ES/JC3-H (48 pin), V850ES/JE3-H only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 87 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (11/12) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFFADBH Alarm time set register RC1ALH R/W 8 16 12H FFFFFADCH Alarm week set register RC1ALW 00H FFFFFADDH RTC control register 0 RC1CC0 00H FFFFFADEH RTC control register 1 RC1CC1 00H FFFFFADFH RTC control register 2 RC1CC2 00H FFFFFAE0H RTC control register 3 RC1CC3 00H FFFFFC00H External interrupt falling edge specification register 0 INTF0 00H FFFFFC06H External interrupt falling edge specification register 3 INTF3 00H FFFFFC08H External interrupt falling edge specification register 4 INTF4 00H FFFFFC0AH External interrupt falling edge specification register 5 INTF5 00H FFFFFC12H External interrupt falling edge specification register 9 INTF9 FFFFFC12H External interrupt falling edge specification register 9H INTF9H 00H FFFFFC13H External interrupt falling edge specification register 9L INTF9L 00H FFFFFC20H External interrupt rising edge specification register 0 INTR0 00H FFFFFC26H External interrupt rising edge specification register 3 INTR3 00H FFFFFC28H External interrupt rising edge specification register 4 INTR4 00H FFFFFC2AH External interrupt rising edge specification register 5 INTR5 00H External interrupt rising edge specification register 9 INTR9 FFFFFC32H 0000H 0000H FFFFFC32H External interrupt rising edge specification register 9H INTR9H 00H FFFFFC33H External interrupt rising edge specification register 9L INTR9L 00H FFFFFC60H Port 0 function register PF0 00H FFFFFC66H Port 3 function register PF3 00H FFFFFC68H Port 4 function register PF4 00H FFFFFC6AH Port 5 function register PF5 00H FFFFFD00H CSIF0 control register 0 CF0CTL0 01H FFFFFD01H CSIF0 control register 1 CF0CTL1 00H FFFFFD02H CSIF0 control register 2 CF0CTL2 FFFFFD03H CSIF0 status register CF0STR FFFFFD04H CSIF0 receive data register CF0RX FFFFFD04H FFFFFD06H CSIF0 receive data register L CF0RXL CSIF0 transmit data register CF0TX 00H 00H R 0000H 0000H R/W 00H CSIF0 transmit data register L CF0TXL 00H FFFFFD20H CSIF2 control register 0 CF2CTL0 01H FFFFFD21H CSIF2 control register 1 CF2CTL1 00H FFFFFD22H CSIF2 control register 2 CF2CTL2 00H FFFFFD23H CSIF2 status register CF2STR 00H FFFFFD06H FFFFFD24H FFFFFD24H FFFFFD26H FFFFFD26H CSIF2 receive data register CF2RX CSIF2 receive data register L CF2RXL CSIF2 transmit data register CF2TX CSIF2 transmit data register L CF2TXL R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 R 00H R/W 0000H 0000H 00H Page 88 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (12/12) Address Function Register Name Symbol FFFFFD30H CSIF3 control register 0 CF3CTL0 FFFFFD31H CSIF3 control register 1 CF3CTL1 FFFFFD32H CSIF3 control register 2 CF3CTL2 FFFFFD33H CSIF3 status register CF3STR FFFFFD34H CSIF3 receive data register CF3RX CSIF3 receive data register L CF3RXL FFFFFD34H FFFFFD36H CSIF3 transmit data register CF3TX CSIF3 transmit data register L CF3TXL FFFFFD40H CSIF4 control register 0 CF4CTL0 FFFFFD41H CSIF4 control register 1 CF4CTL1 FFFFFD42H CSIF4 control register 2 CF4CTL2 FFFFFD43H CSIF4 status register CF4STR FFFFFD44H CSIF4 receive data register CF4RX FFFFFD36H FFFFFD44H FFFFFD46H FFFFFD46H R/W Manipulatable Bits Default Value R/W 1 8 CF4RXL CSIF4 transmit data register CF4TX CSIF4 transmit data register L CF4TXL IIC shift register 0 IIC0 FFFFFD82H IIC control register 0 IICC0 Note Note Slave address register 0 SVA0 FFFFFD84H IIC clock select register 0 IICCL0 00H 00H 00H R 0000H 00H 01H 00H 00H 00H R 0000H 00H Note 0000H 00H Note FFFFFD83H R/W FFFFFD80H 01H R/W CSIF4 receive data register L 16 0000H 00H 00H 00H 00H 00H FFFFFD85H IIC function expansion register 0 IICX0 Note 00H FFFFFD86H IIC status register 0 IICS0 Note R 00H FFFFFD8AH IIC flag register 0 IICF0 Note R/W 00H FFFFFD90H IIC shift register 1 IIC1 00H FFFFFD92H IIC control register 1 IICC1 00H FFFFFD93H Slave address register 1 SVA1 00H FFFFFD94H IIC clock select register 1 IICCL1 00H FFFFFF40H USB clock selection register UCKSEL 00H FFFFFF41H USB function control register UFCKMSK 03H FFFFFF44H USB function selection register EPRMK 03H FFFFFD95H IIC function expansion register 1 IICX1 00H FFFFFD96H IIC status register 1 IICS1 R 00H FFFFFD9AH IIC flag register 1 IICF1 R/W 00H Note V850ES/JC3-H (48 pin), V850ES/JE3-H only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 89 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.7 CHAPTER 3 CPU FUNCTION Programmable peripheral I/O registers The BPC register is used to select the programmable peripheral I/O register area. The BPC register is valid only in the PD70F3819 and 70F3825. (1) Peripheral I/O area select control register (BPC) This register can be read or written in 16-bit units. Reset sets this register to 0000H. After reset: 0000H BPC 15 14 PA15 0 PA15 13 Address: FFFFF064H 12 11 10 9 8 7 6 5 4 3 2 1 0 PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 Allows/does not allow use of programmable peripheral I/O area. 0 Do not allow use of programmable peripheral I/O area. 1 Allow use of programmable peripheral I/O area. PA13 to PA00 Caution R/W Set address of programmable peripheral I/O area. (correspond to A27 to A14) If the PA15 bit is set to 1, be sure to set the BPC register to 8FFBH. If the PA15 bit is set to 0, be sure to set the BPC register to 0000H. For the list of programmable peripheral I/O registers, refer to Table 19-16 Register Access Types. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 90 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.8 CHAPTER 3 CPU FUNCTION Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850ES/JC3-H and V850ES/JE3-H have the following eight special registers. * Power save control register (PSC) * Clock control register (CKC) * Processor clock control register (PCC) * Clock monitor mode register (CLM) * Reset source flag register (RESF) * Low-voltage detection register (LVIM) * Internal RAM data status register (RAMS) * On-chip debug mode register (OCDM) In addition, the PRCDM register is provided to protect against a write access to the special registers so that the application system does not inadvertently stop due to a program loop. A write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the SYS register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 91 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4> Write the setting data to the special register (by using the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) (<5> to <9> Insert NOP instructions (5 instructions).)Note <10> Enable DMA operation if necessary. [Example] With PSC register (setting standby mode) ST.B r11, PSMR[r0] <1>CLR1 0, DCHCn[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes). ; Disable DMA operation. n = 0 to 3 <2>MOV0x02, r10 <3>ST.B r10, PRCMD[r0] ; Write PRCMD register. <4>ST.B r10, PSC[r0] ; Set PSC register. Note <5>NOP ; Dummy instruction <6>NOPNote ; Dummy instruction Note <7>NOP ; Dummy instruction <8>NOPNote ; Dummy instruction Note <9>NOP ; Dummy instruction <10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3 (next instruction) There is no special sequence to read a special register. Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not acknowledged. This is because it is assumed that steps <3> and <4> above are performed by successive store instructions. If another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. Although dummy data is written to the PRCMD register, use the same general-purpose register used to set the special register (<4> in Example) to write data to the PRCMD register (<3> in Example). The same applies when a general-purpose register is used for addressing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 92 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read). After reset: Undefined PRCMD W Address: FFFFF1FCH 7 6 5 4 3 2 1 0 REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 93 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF802H < > SYS 0 0 0 PRERR 0 0 0 0 PRERR Detects protection error 0 Protection error did not occur 1 Protection error occurred The PRERR flag operates under the following conditions. (a) Set condition (PRERR flag = 1) (i) When data is written to a special register without writing anything to the PRCMD register (when <4> is executed without executing <3> in 3.4.8 (1) Setting data to special registers) (ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.8 (1) Setting data to special registers is not the setting of a special register) Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between an operation to write the PRCMD register and an operation to write a special register, the PRERR flag is not set, and the set data can be written to the special register. (b) Clear condition (PRERR flag = 0) (i) When 0 is written to the PRERR flag (ii) When the system is reset Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes precedence). 2. If data is written to the PRCMD register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 94 of 1442 V850ES/JC3-H, V850ES/JE3-H 3.4.9 CHAPTER 3 CPU FUNCTION Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JC3-H and V850ES/JE3-H. * System wait control register (VSWC) * On-chip debug mode register (OCDM) * Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary. When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related registers after setting the above registers. (a) System wait control register (VSWC) The VSWC register controls wait of bus access to the on-chip peripheral I/O registers. Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JC3H and V850ES/JE3-H require wait cycles according to the operating frequency. Set the following value to the VSWC register in accordance with the frequency used. The VSWC register can be read or written in 8-bit units. Reset sets this register to 77H. After reset: 77H R/W Address: FFFFF06EH VSWC Operating Frequency (fCPU) Set Value of VSWC Number of Waits fCPU < 16.6 MHz 00H 0 (no waits) 16.6 MHz fCPU < 25 MHz 01H 1 25 MHz fCPU < 33.3 MHz 11H 2 33.3 MHz fCPU 48 MHz 12H 3 (b) On-chip debug mode register (OCDM) (V850ES/JC3-H only) For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION. (c) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2. Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to activate this operation. For details, see CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 95 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. This must be taken into consideration if real-time processing is required. When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the wait states set by the VSWC register. The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this time are shown below. (1/2) Peripheral Function Register Name Access k 16-bit timer/event counter AA (TAA) TAAnCNT Read 1 or 2 (n = 0 to 2, 4, m = 0 to 2) TAAnCCR0, TAAnCCR1 Write * 1st access: No wait * Continuous write: 0 to 3 TAAmIOC4 Read 1 or 2 Write * 1st access: No wait * Continuous write: 0 to 3 16-bit timer/event counter AB (TAB) Read 1 or 2 TAB1CNT Read 1 or 2 TAB1CCR0 to TAB1CCR3 Write * 1st access: No wait * Continuous write: 0 to 3 TAB1IOC4 Read 1 or 2 Write * 1st access: No wait * Continuous write: 0 to 3 Motor control TAB1OPT1 Read 1 or 2 Write * 1st access: No wait * Continuous write: 0 to 3 TAB1DTC Write * 1st access: No wait * Continuous write: 0 to 3 TMT TT0CNT Read 1 or 2 TT0TCR0, TT0TCR1 Write * 1st access: No wait * Continuous write: 0 to 3 Watchdog timer 2 (WDT2) WDTM2 Read 1 or 2 Write 3 (when WDT2 operating) Real-time output function (RTO) RTBL0, RTBH0 Write 1 (RTPC0.RTPOE0 bit = 0) A/D converter R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 ADA0M0 Read 1 or 2 ADA0CR0 to ADA0CR9 Read 1 or 2 ADA0CR0H to ADA0CR9H Read 1 or 2 Page 96 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (2/2) Peripheral Function 2 2 Register Name Access k I C00 to I C01 IICS0 to IICS1 Read 1 CRC CRCD Write 1 CAN controller C0GMABT, Read/Write fXX/fCANMOD + 1) / (2 + j) (MIN.) (m = 0 to 31, a = 1 to 4) C0GMABTD, Note Note (2 x fXX/fCANMOD + 1) / (2 + j) (MAX.) C0MASKaL, C0MASKaH, C0LEC, C0INFO, C0ERC, C0IE, C0INTS, C0BRP, C0BTR, C0TS C0GMCTRL, Read/Write Note (fXX/fCAN + 1) / (2 + j) (MIN.) (2 x fXX/fCAN + 1) / (2 + j) (MAX.) C0GMCS, Note C0CTRL C0RGPT, Write Note (fXX/fCANMOD + 1) / (2 + j) (MIN.) Note C0TGPT (2 x fXX/fCANMOD + 1) / (2 + j) (MAX.) Read (3 x fXX/fCANMOD + 1) / (2 + j) (MIN.) Note Note (4 x fXX/fCANMOD + 1) / (2 + j) (MAX.) C0LIPT, Read Note Write Note (4 x fXX/fCAN + 1) / (2 + j) (MIN.) (5 x fXX/fCAN + 1) / (2 + j) (MAX.) Read Write (8 bits) Note Note (4 x fXX/fCANMOD + 1) / (2 + j) (MIN.) Note Note C0MDATA1m, C0MDATA23m, C0MDATA2m, C0MDATA3m, Note (3 x fXX/fCAN + 1) / (2 + j) (MIN.) (4 x fXX/fCAN + 1) / (2 + j) (MAX.) C0MDATA01m, C0MDATA0m, Note (4 x fXX/fCANMOD + 1) / (2 + j) (MAX.) C0LOPT C0MCTRLm (3 x fXX/fCANMOD + 1) / (2 + j) (MIN.) (5 x fXX/fCANMOD + 1) / (2 + j) (MAX.) Write (16 bits) C0MDATA45m, C0MDATA4m, (2 x fXX/fCANMOD + 1) / (2 + j) (MIN.) Note Note (3 x fXX/fCANMOD + 1) / (2 + j) (MAX.) C0MDATA5m, C0MDATA67m, C0MDATA6m, C0MDATA7m, Read (8/16 bits) C0MDLCm, (3 x fXX/fCANMOD + 1) / (2 + j) (MIN.) Note Note (4 x fXX/fCANMOD + 1) / (2 + j) (MAX.) C0MCONFm, C0MIDLm, C0MIDHm Number of clocks necessary for access = 3 + i + j + (2 + j) x k Note Digits below the decimal point are rounded up. Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated, it can only be cleared by a reset. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock Remark i: Values (0) of higher 4 bits of VSWC register j: Values (0 or 1) of lower 4 bits of VSWC register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 97 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu * sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu * Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 not reg1, reg2 satsubr reg1, reg2 satsub reg1, reg2 satadd reg1, reg2 satadd imm5, reg2 or reg1, reg2 xor reg1, reg2 and reg1, reg2 tst reg1, reg2 subr reg1, reg2 sub reg1, reg2 add reg1, reg2 add imm5, reg2 cmp reg1, reg2 cmp imm5, reg2 mulh reg1, reg2 shr imm5, reg2 sar imm5, reg2 shl imm5, reg2 <Example> <i> ld.w [r11], r10 * * * If the decode operation of the mov instruction <ii> immediately before the sld instruction <iii> and an interrupt request conflict before execution of the ld instruction <i> is complete, the execution result of instruction <i> may not be stored in a register. <ii> mov r10, r28 <iii> sld.w 0x28, r10 (b) Countermeasure <1> When compiler (CA850) is used Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> For assembler When executing the sld instruction immediately after instruction <ii>, avoid the above operation using either of the following methods. * Insert a nop instruction immediately before the sld instruction. * Do not use the same register as the sld instruction destination register in the above instruction <ii> executed immediately before the sld instruction. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 98 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Features { I/O ports * V850ES/JC3-H (40 pin): 25 5 V tolerant/N-ch open-drain output selectable: 15 * V850ES/JC3-H (48 pin): 32 5 V tolerant/N-ch open-drain output selectable: 17 * V850ES/JE3-H: 45 5 V tolerant/N-ch open-drain output selectable: 19 { Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JC3-H (40 pin) features a total of 25 I/O ports consisting of ports 0, 3 to 5, 7, 9, and DL. The V850ES/JC3-H (48 pin) features a total of 32 I/O ports consisting of ports 0, 1, 3 to 5, 7, 9, and DL. The V850ES/JE3-H features a total of 45 I/O ports consisting of ports 0, 1, 3 to 7, 9, and DL. The port configuration is shown below. Table 4-1. I/O Buffer Power Supplies for Pins (V850ES/JC3-H (40 pin)) Power Supply Corresponding Pins AVREF0 Port 7 EVDD RESET, ports 0, 3 to 5, 9, CM, CT, and DL Table 4-2. I/O Buffer Power Supplies for Pins (V850ES/JC3-H (48 pin)) Power Supply Corresponding Pins AVREF0 Port 7 AVREF1 Port 1 EVDD RESET, ports 0, 3 to 5, 9, and DL Table 4-3. I/O Buffer Power Supplies for Pins (V850ES/JE3-H) Power Supply Corresponding Pins AVREF0 Port 7 AVREF1 Port 1 EVDD RESET, ports 0, 3 to 6, 9, and DL R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 99 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS Figure 4-1. Port Configuration Diagram (V850ES/JC3-H (40 pin)) Port 0 P03 P70 Port 7 P30 P74 Port 3 P32 P34 P40 Port 4 P96 P97 P910 Port 9 P42 P50 P913 P56 PDL5 Port 5 Port DL Figure 4-2. Port Configuration Diagram (V850ES/JC3-H (48 pin)) Port 0 P03 P70 Port 1 P10 P75 P30 P92 P32 P34 P36 P37 P94 P96 P97 P40 P910 P42 P913 Port 7 Port 3 Port 9 Port 4 P50 Port 5 P56 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PDL5 Port DL Page 100 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS Figure 4-3. Port Configuration Diagram (V850ES/JE3-H) Port 0 P02 P03 P70 Port 1 P10 P79 P30 P92 P37 P94 P96 P97 Port 3 P40 Port 4 P42 Port 7 Port 9 P910 P50 P913 Port 5 P56 P60 PDL5 Port DL Port 6 P65 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 101 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3 CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-4. Port Configuration (V850ES/JC3-H (40 pin)) Item Control register Configuration Port n mode register (PMn: n = 0, 3 to 5, 7, 9, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, DL) Port n function control register (PFCn: n = 0, 3 to 5, 9) Port n function control expansion register (PFCEn: n = 0, 3 to 5, 9) Port n function register (PFn: n = 0, 3 to 5) Ports I/O: 25 Table 4-5. Port Configuration (V850ES/JC3-H (48 pin)) Item Control register Configuration Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, DL) Port n function control register (PFCn: n = 0, 3 to 5, 9) Port n function control expansion register (PFCEn: n = 0, 3 to 5, 9) Port n function register (PFn: n = 0, 3 to 5, 9) Ports I/O: 32 Table 4-6. Port Configuration (V850ES/JE3-H) Item Control register Configuration Port n mode register (PMn: n = 0, 1, 3 to 7, 9, DL) Port n mode control register (PMCn: n = 0, 3 to 6, 9, DL) Port n function control register (PFCn: n = 0, 2 to 6, 9) Port n function control expansion register (PFCEn: n = 0, 3 to 6, 9) Port n function register (PFn: n = 0, 3 to 6, 9) Ports I/O: 45 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 102 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins. Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units. After reset: 00H (output latch) Pn R/W 7 6 5 7 3 2 1 0 Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 Pnm Control of output data (in output mode) 0 Outputs 0. 1 Outputs 1. Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register. Table 4-7. Writing/Reading Pn Register Setting of PMn Register Writing to Pn Register Note Output mode Data is written to the output latch (PMnm = 0) In the port mode (PMCn = 0), the contents of the output . Reading from Pn Register The value of the output latch is read. latch are output from the pins. Input mode Data is written to the output latch. (PMnm = 1) The pin status is not affected The pin status is read. Note . Note The value written to the output latch is retained until a new value is written to the output latch. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 103 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. After reset: FFH PMn PMn7 R/W PMn6 PMn5 PMnm PMn4 PMn3 PMn2 PMn1 PMn0 Control of input/output mode 0 Output mode 1 Input mode (3) Port n mode control register (PMCn) The PMCn register specifies the port mode or alternate function. Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. After reset: 00H PMCn PMCn7 R/W PMCn6 PMCnm PMCn5 PMCn4 PMCn2 PMCn1 PMCn0 Specification of operation mode 0 Port mode 1 Alternate-function mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PMCn3 Page 104 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. After reset: 00H PFCn PFCn7 R/W PFCn6 PFCn5 PFCnm PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 Specification of alternate function 0 Alternate function 1 1 Alternate function 2 (5) Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. After reset: 00H PFCEn PFCn R/W PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0 PFCn7 PFCn6 PFCn5 PFCn3 PFCn1 PFCn0 PFCEnm PFCnm 0 0 Alternate function 1 0 1 Alternate function 2 1 0 Alternate function 3 1 1 Alternate function 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PFCn4 PFCn2 Specification of alternate function Page 105 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1bit units. After reset: 00H PFn PFn7 PFnmNote PFn6 R/W PFn5 PFn4 PFn3 PFn2 PFn1 PFn0 Control of normal output/N-ch open-drain output 0 Normal output (CMOS output) 1 N-ch open-drain output Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode is specified), the set value of the PFn register is invalid. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 106 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-4. Setting of Each Register and Pin Function Port mode Output mode "0" PMn register Input mode "1" Alternate function (when two alternate functions are available) "0" Alternate function 1 "0" PFCn register Alternate function 2 PMCn register "1" Alternate function (when three or more alternate functions are available) "1" Alternate function 1 (a) Alternate function 2 (b) PFCn register (c) PFCEn register Alternate function 3 (d) Alternate function 4 Remark (a) (b) (c) (d) PFCEnm PFCnm 0 0 1 1 0 1 0 1 Set the alternate functions in the following sequence. <1> Set the PFCn and PFCEn registers. <2> Set the PMCn register. <3> Set the INTRn or INTFn register (to specify an external interrupt pin). If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn registers are being set. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 107 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.1 CHAPTER 4 PORT FUNCTIONS Port 0 Port 0 witch I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each part. Generic name Number of I/O Ports V850ES/JC3-H (40 pin) 1-bit I/O port V850ES/JC3-H (48pin) 1-bit I/O port V850ES/JE3-H 2-bit I/O port Port 0 includes the following alternate-function pins. Table 4-8. Port 0 Alternate-Function Pins Pin Pin No. Name Alternate-Function Pin Name V850ES/ V850ES/ V850ES/ JC3-H JC3-H JE3-H (40 pin) (48 pin) I/O Remark Selectable as N-ch open-drain output P02 - - 19 NMI Input P03 11 13 20 INTP02/ADTRG/UCLK Input Caution The P02 and P03 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) Port 0 register (P0) (a) V850ES/JC3-H After reset: 00H (output latch) P0 R/W Address: FFFFF400H 7 6 5 4 3 2 1 0 0 0 0 0 P03 0 0 0 P03 Output data control (in output mode) 0 Outputs 0. 1 Outputs 1. (b) V850ES/JE3-H After reset: 00H (output latch) P0 R/W Address: FFFFF400H 7 6 5 4 3 2 1 0 0 0 0 0 P03 P02 0 0 P0n Output data control (in output mode) (n = 2, 3) 0 Outputs 0. 1 Outputs 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 108 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) (a) V850ES/JC3-H After reset: FFH PM0 R/W Address: FFFFF420H 7 6 5 4 3 2 1 0 1 1 1 1 PM03 1 1 1 PM03 I/O mode control 0 Output mode 1 Input mode (b) V850ES/JE3-H After reset: FFH PM0 R/W Address: FFFFF420H 7 6 5 4 3 2 1 0 1 1 1 1 PM03 PM02 1 1 PM0n I/O mode control (n = 2, 3) 0 Output mode 1 Input mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 109 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) (a) V850ES/JC3-H After reset: 00H PMC0 R/W Address: FFFFF440H 7 6 5 4 3 2 1 0 0 0 0 0 PMC03 0 0 0 PMC03 Specification of P03 pin operation mode 0 I/O port 1 INTP02 input/ADTRG input/UCLK input (b) V850ES/JE3-H After reset: 00H PMC0 R/W Address: FFFFF440H 7 6 5 4 3 2 1 0 0 0 0 0 PMC03 PMC02 0 0 PMC03 Specification of P03 pin operation mode 0 I/O port 1 INTP02 input/ADTRG input/UCLK input PMC02 Specification of P02 pin operation mode 0 I/O port 1 NMI input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 110 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H PFC0 Remark R/W Address: FFFFF460H 7 6 5 4 3 2 1 0 0 0 0 0 PFC03 0 0 0 For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. (5) Port 0 function control expansion register (PFCE0) After reset: 00H PFCE0 Remark R/W Address: FFFFF700H 7 6 5 4 3 2 1 0 0 0 0 0 PFCE03 0 0 0 For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 111 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port 0 alternate function specifications PFCE03 PFC03 Specification of P03 pin alternate function 0 0 INTP02 input 0 1 ADTRG input 1 0 UCLK input 1 1 Setting prohibited (7) Port 0 function register (PF0) (a) V850ES/JC3-H After reset: 00H PF0 R/W Address: FFFFFC60H 7 6 5 4 3 2 1 0 0 0 0 0 PF03 0 0 0 PF03 Control of normal output or N-ch open-drain output 0 Normal output 1 N-ch open-drain output (b) V850ES/JE3-H After reset: 00H PF0 Address: FFFFFC60H 7 6 5 4 3 2 1 0 0 0 0 0 PF03 PF02 0 0 PF0n Caution R/W Control of normal output or N-ch open-drain output (n = 2, 3) 0 Normal output 1 N-ch open-drain output When an output pin is pulled up to EVDD or higher, be sure to set the PF0n bit to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 112 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.2 CHAPTER 4 PORT FUNCTIONS Port 1 Port 1 is a 1-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-9. Port 1 Alternate-Function Pins Pin Name P10 Caution Pin No. Alternate- V850ES/JC3-H V850ES/JC3-H V850ES/ Function Pin (40 pin) (48pin) JE3-H Name - 3 3 I/O ANO0 Remark - Output When the power is turned on, the P10 pin may output an undefined level temporarily even during reset. (1) Port 1 register (P1) After reset: 00H (output latch) P1 R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 P10 P10 Caution Address: FFFFF402H Output data control (in output mode) 0 Outputs 0. 1 Outputs 1. Do not read or write the P1 register during D/A conversion (see 15.4.3 Cautions). (2) Port 1 mode register (PM1) After reset: 00H PM1 R/W Address: FFFFF422H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PM10 PM10 I/O mode control 0 Output mode 1 Input mode Cautions 1. When using P10 as the alternate function (ANO0 pin output), set the PM10 bit to 1. 2. When using one of the PM10 pin as an I/O port and the other as a D/A output pin, do so in an application where the port I/O level does not change during D/A output. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 113 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.3 CHAPTER 4 PORT FUNCTIONS Port 3 Port 3 witch I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each part. Generic name Number of I/O Ports V850ES/JC3-H (40 pin) 4-bit I/O port V850ES/JC3-H(48pin 6-bit I/O port V850ES/JE3-H 8-bit I/O port Port 3 includes the following alternate-function pins. Table 4-10. Port 3 Alternate-Function Pins Pin Alternate-Function Pin Pin No. Name V850ES/JC3-H V850ES/JC3-H (40 pin) I/O Remark Name V850ES/JE3-H (48 pin) P30 17 21 29 TXDC0/SOF4/INTP07 I/O Selectable as N-ch open-drain P31 18 22 30 RXDC0/SIF4/INTP08 Input output P32 19 23 31 ASCKC0/SCKF4/ I/O TIAA00/TOAA00 P33 Note1 - - 35 TIAA01/TOAA01/ I/O RTCDIV/RTCCL P34 16 18 26 TIAA10/TOAA10/ I/O TOAA1OFF/INTP09 P35 Note1 - - 36 TIAA11/TOAA11/ I/O RTC1HZ P36 Note2 - 19 27 TXDC3/SCL00/ CTXD0 P37 Note2 - 20 27 RXDC3/SDA00/ CRXD0 Notes1. I/O Note3 V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only 3. PD70F3819, 70F3825 only Caution I/O Note3 The P30 to P37 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 114 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 00H (output latch) P3 R/W Address: FFFFF406H 7 6 5 4 3 2 1 0 P37Note1 P36Note1 P35Note2 P34 P33Note2 P32 P31 P30 P3n Output data control (in output mode) (n = 0 to 7) 0 Outputs 0. 1 Outputs 1. Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only (2) Port 3 mode register (PM3) After reset: FFH 7 PM3 PM37 R/W Address: FFFFF426H 6 Note1 PM36 5 Note1 PM35 PM3n 4 Note2 PM34 3 Note2 PM33 2 1 0 PM32 PM31 PM30 I/O mode control (n = 0 to 7) 0 Output mode 1 Input mode Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 115 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 00H PMC3 R/W Address: FFFFF446H PMC37Note1 PMC36Note1 PMC35Note2 PMC34 PMC33Note2 PMC32 PMC37 PMC31 PMC30 Specification of P37 pin operation mode 0 I/O port 1 RXDC3 input/SDA00 I/O/CRXD inputNote3 PMC36 Specification of P36 pin operation mode 0 I/O port 1 TXDC3 output/SCL00 I/O/CTXD0 outputNote3 PMC35 Specification of P35 pin operation mode 0 I/O port 1 TIAA11 input/TOAA11 output/RTC1HZ output PMC34 Specification of P34 pin operation mode 0 I/O port 1 TIAA10 input/TOAA10 output/TOAA1OFF input/INTP09 input PMC33 Specification of P33 pin operation mode 0 I/O port 1 TIAA01 input/TOAA01 output/RTCDIV output/RTCCL output PMC32 Specification of P32 pin operation mode 0 I/O port 1 ASCKA0 input/SCKF4 I/O/TIAA00 input/TOAA00 output PMC31 Specification of P31 pin operation mode 0 I/O port 1 RXDC0 input/SIF4 input/INTP08 input PMC30 Specification of P30 pin operation mode 0 I/O port 1 TXDC0 output/SOF4 output/INTP07 input Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only 3. PD70F3819, 70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 116 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 00H R/W Address: FFFFF466H PFC3 PFC37Note1 PFC36Note1 PFC35Note2 PFC34 PFC33Note2 PFC32 PFC31 PFC30 Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only Remark For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function specifications. (5) Port 3 function control expansion register (PFCE3) After reset: 00H PFCE3 R/W Address: FFFFF706H PFCE37Note1 PFCE36Note1 PFCE35Note2 PFCE34 PFCE33Note2 PFCE32 PFCE31 PFCE30 Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only Remark For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function specifications. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 117 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specifications PFCE37 Note1 PFC37 Note1 Specification of P37 pin alternate function 0 0 RXDC3 input 0 1 SDA00 I/O 1 0 CRXD0 input 1 1 Setting prohibit Note2 Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. PD70F3819, 70F3825 only PFCE36 Note1 PFC36 Note1 Specification of P36 pin alternate function 0 0 TXDC3 output 0 1 SCL00 I/O 1 0 CTXD0 output 1 1 Setting prohibit Note2 Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. PD70F3819, 70F3825 only PFCE35 Note PFC35 Note Specification of P35 pin alternate function 0 0 TIAA11 input 0 1 TOAA11 output 1 0 RTC1HZ output 1 1 Setting prohibited Note V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 118 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS PFCE34 PFC34 0 0 TIAA10 input 0 1 TOAA10 output 1 0 TOAA1OFF input/INTP09 input 1 1 Setting prohibited PFCE33 Note PFC33 Specification of P34 pin alternate function Note Specification of P33 pin alternate function 0 0 TIAA01 input 0 1 TOAA01 output 1 0 RTCDIV output 1 1 RTCCL output Note V850ES/JE3-H only PFCE32 PFC32 Specification of P32 pin alternate function 0 0 ASCKC0 input 0 1 SCKF4 I/O 1 0 TIAA00 input 1 1 TOAA00 output PFCE31 PFC31 Specification of P31 pin alternate function 0 0 RXDC0 input 0 1 SIF4 input 1 0 INTP08 input 1 1 Setting prohibited PFCE30 PFC30 0 0 TXDC0 output 0 1 SOF4 output 1 0 INTP07 input 1 1 Setting prohibited R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Specification of P30 pin alternate function Page 119 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 00H PF3 R/W Address: PF37Note1 PF36Note1 PF35Note2 PF3n FFFFFC66H PF34 PF33Note2 PF32 PF31 PF30 Control of normal output or N-ch open-drain output (n = 0 to 7) 0 Normal output (CMOS output) 1 N-ch open-drain output Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. PD70F3819, 70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 120 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.4 CHAPTER 4 PORT FUNCTIONS Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-11. Port 4 Alternate-Function Pins Pin Name Alternate-Function Pin Pin No. V850ES/JC3-H V850ES/JC3-H (40 pin) I/O Remark Name V850ES/JE3-H (48 pin) P40 20 24 32 SIF0/TXDC4/SDA01 I/O Selectable as N-ch open-drain P41 21 25 33 SOF0/RXDC4/SCL01 I/O output P42 22 26 34 SCKF0/INTP10 I/O Caution The P40 to P42 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) Port 4 register (P4) After reset: 00H (output latch) P4 0 0 R/W 0 P4n Address: FFFFF408H 0 0 P42 P41 P40 Output data control (in output mode) (n = 0 to 2) 0 Outputs 0. 1 Outputs 1. (2) Port 4 mode register (PM4) After reset: FFH PM4 1 R/W Address: FFFFF428H 1 PM4n 1 1 PM42 PM41 PM40 I/O mode control (n = 0 to 2) 0 Output mode 1 Input mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 1 Page 121 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 R/W Address: FFFFF448H 0 0 PMC42 0 0 PMC42 PMC41 PMC40 Specification of P42 pin operation mode 0 I/O port 1 SCKF0 I/O/INTP10 input PMC41 Specification of P41 pin operation mode 0 I/O port 1 SOF0 output/RXDC4 input/SCL01 I/O PMC40 Specification of P40 pin operation mode 0 I/O port 1 SIF0 input/TXDC4 output/SDA01 I/O (4) Port 4 function control register (PFC4) After reset: 00H PFC4 Remark 0 R/W 0 Address: FFFFF468H 0 0 0 PFC42 PFC41 PFC40 For details of alternate function specification, see 4.3.5 (6) Port 4 alternate function specifications. (5) Port 4 function control expansion register (PFCE4) After reset: 00H PFCE4 Remark 0 R/W 0 Address: FFFFF708H 0 0 0 0 PFCE41 PFCE40 For details of alternate function specification, see 4.3.5 (6) Port 4 alternate function specifications. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 122 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port 4 alternate function specifications PFC42 Specification of P42 pin alternate function 0 SCKF0 I/O 1 INTP10 input PFCE41 PFC41 Specification of P41 pin alternate function 0 0 SOF0 output 0 1 RXDC4 input 1 0 SCL01 I/O 1 1 Setting prohibited PFCE40 PFC40 0 0 SIF0 input 0 1 TXDC4 output 1 0 SDA01 I/O 1 1 Setting prohibited Specification of P40 pin alternate function (7) Port 4 function register (PF4) After reset: 00H PF4 0 PF4n R/W 0 Address: FFFFFC68H 0 0 PF42 PF41 PF40 Control of normal output or N-ch open-drain output (n = 0 to 2) 0 Normal output (CMOS output) 1 N-ch open-drain output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 Page 123 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.5 CHAPTER 4 PORT FUNCTIONS Port 5 Port 5 is 5-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-12. Port 5 Alternate-Function Pins Pin Name V850ES/JC3-H V850ES/JC3-H (40 pin) P52 Alternate-Function Pin Pin No. 23 27 24 Remark V850ES/JE3-H (48 pin) 37 KR2/TOAB13/RTP02/ DDI P53 I/O Name 28 38 I/O Note Selectable as N-ch open-drain output SIF2/KR3/TOAB10/ I/O Note RTP03/DDO P54 25 29 39 SOF2/KR4/RTP04 /DCK P55 26 30 40 SCKF2/KR5/RTP05 /DMS P56 27 31 41 I/O Note I/O Note Note INTP05/DRST Input Note The DDI, DDO, DCK, DMS, and DRST pins are used for on-chip debugging. If on-chip debugging is not used, fix the P05/INTP02/DRST pin to low level between when the reset by the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). For details, see 4.5.3 Cautions on on-chip debug pins. Cautions 1. When the power is turned on, the P53 pin may output an undefined level temporarily even during reset. 2. The P52 to P56 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 124 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (1) Port 5 register (P5) After reset: 00H (output latch) P5 0 R/W P56 P55 P5n Address: FFFFF40AH P54 P53 P52 0 0 Output data control (in output mode) (n = 2 to 6) 0 Outputs 0. 1 Outputs 1. (2) Port 5 mode register (PM5) After reset: FFH R/W PM5 PM56 1 Address: FFFFF42AH PM55 PM5n PM53 PM52 0 0 I/O mode control (n = 2 to 6) 0 Output mode 1 Input mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PM54 Page 125 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H PMC5 0 R/W PMC56 Address: FFFFF44AH PMC55 PMC56 PMC54 PMC53 0 0 Specification of P56 pin operation mode 0 I/O port 1 INTP05 input PMC55 Specification of P55 pin operation mode 0 I/O port 1 SCKF2 I/O/KR5 input/RTP05 output PMC54 Specification of P54 pin operation mode 0 I/O port 1 SOF2 output/KR4 input/RTP04 output PMC53 Specification of P53 pin operation mode 0 I/O port 1 SIF2 input/KR3 input/RTP03 output PMC52 Specification of P52 pin operation mode 0 I/O port 1 KR2 input/RTP02 output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PMC52 Page 126 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H PFC5 Remark 0 R/W 0 Address: FFFFF46AH PFC55 PFC54 PFC53 PFC52 0 0 For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H PFCE5 Remark 0 R/W 0 Address: FFFFF70AH PFCE55 PFCE54 PFCE53 PFCE52 0 0 For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function specifications. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 127 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port 5 alternate function specifications PFCE55 PFC55 0 0 SCKF2 I/O 0 1 KR5 input 1 0 RTP05 output 1 1 Setting prohibited PFCE54 PFC54 0 0 SOF2 output 0 1 KR4 input 1 0 RTP04 output 1 1 Setting prohibited PFCE53 PFC53 0 0 SIF2 input 0 1 KR3 input 1 0 Setting prohibited 1 1 RTP03 output PFCE52 PFC52 0 0 KR2 input 0 1 Setting prohibited 1 0 RTP02 output 1 1 Setting prohibited R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Specification of P55 pin alternate function Specification of P54 pin alternate function Specification of P53 pin alternate function Specification of P52 pin alternate function Page 128 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (7) Port 5 function register (PF5) After reset: 00H PF5 0 PF5n R/W Address: FFFFFC6AH PF56 PF55 PF54 PF52 0 0 Control of normal output or N-ch open-drain output (n = 2 to 6) 0 Normal output (CMOS output) 1 N-ch open-drain output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PF53 Page 129 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.6 CHAPTER 4 PORT FUNCTIONS Port 6 (V850ES/JE3-H only) Port 6 is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Table 4-13. Port 6 Alternate-Function Pins Pin Name Caution Pin No. Alternate-Function Pin V850ES/JE3-H Name I/O P60 13 TOAB1T1/TOAB11/TIAB11 I/O P61 14 TOAB1B1/TOAB10/TIAB10 I/O P62 15 TOAB1T2/TOAB12/TIAB12 I/O P63 16 TOAB1B2/TRGAB1/CS0 I/O P64 17 TOAB1T3/TOAB13/TIAB13 I/O P65 18 TOAB1B3/EVTAB1 I/O Remark - The P60 to P65 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) Port 6 register (P6) After reset: 00H (output latch) P6 0 0 P6n P65 Address: FFFFF40CH P64 P63 P62 P61 P60 Output data control (in output mode) (n = 0 to 5) 0 Outputs 0. 1 Outputs 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 R/W Page 130 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (2) Port 6 mode register (PM6) After reset: FFH PM6 R/W 1 Address: FFFFF42CH 1 PM65 PM5n PM64 PM63 PM62 PM61 PM60 Output data control (in output mode) (n = 0 to 5) 0 Output mode 1 Input mode (3) Port 6 mode control register (PMC6) After reset: 00H PMC6 0 R/W 0 PMC65 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 Specification of P65 pin operation mode 0 I/O port 1 TOAB1B3 output/EVTAB1 input PMC64 Specification of P64 pin operation mode 0 I/O port 1 TOAB1T3 output/TOAB13 output/TIAB13 input PMC63 Specification of P63 pin operation mode 0 I/O port 1 TOAB1B2 output/TRGAB1 input PMC62 Specification of P62 pin operation mode 0 I/O port 1 TOAB1T2 output/TOAB12 output/TIAB12 output PMC61 Specification of P61 pin operation mode 0 I/O port 1 TOAB1B1 output/TIAB10 input/TOAB10 output PMC60 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Address: FFFFF44CH Specification of P60 pin operation mode 0 I/O port 1 TOAB1T1 output/TOAB11 output/TIAB11 input Page 131 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port 6 function control register (PFC6) After reset: 00H PFC6 Remark 0 R/W Address: FFFFF46CH 0 PFC65 PFC64 PFC63 PFC62 PFC61 PFC60 For details of alternate function specification, see 4.3.7 (6) Port 6 alternate function specifications. (5) Port 6 function control expansion register (PFCE6) After reset: 00H PFCE6 0 R/W Address: FFFF70CH 0 PFCE65 PFCE64 PFCE63 PFCE62 PFCE61 PFCE60 (6) Port 6 alternate function specifications PFCE65 PFC65 0 0 TOAB1B3 output 0 1 EVTAB1 input 1 0 Setting prohibited 1 1 Setting prohibited PFCE64 PFC64 0 0 TOAB1T3 output/TOAB13 output 0 1 TIAB13 input 1 0 Setting prohibited 1 1 Setting prohibited PFCE61 PFC61 0 0 TOAB1B1 output 0 1 TIAB10 input 1 0 TOAB10 output 1 1 Setting prohibited PFCE60 PFC60 0 0 TOAB1T1 output/TOAB11 output 0 1 TIAB11 input 1 0 Setting prohibited 1 1 Setting prohibited R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Specification of P65 pin alternate function Specification of P64 pin alternate function Specification of P61 pin alternate function Specification of P60 pin alternate function Page 132 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.7 CHAPTER 4 PORT FUNCTIONS Port 7 Port 5 witch I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each part. Generic name Number of I/O Ports V850ES/JC3-H (40 pin) 5-bit I/O port V850ES/JC3-H (48 pin) 6-bit I/O port V850ES/JE3-H 10-bit I/O port Port 7 includes the following alternate-function pins. Table 4-14. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name I/O V850ES/JC3-H V850ES/JC3-H (40 pin) (48 pin) V850ES/JE3-H P70 40 48 64 ANI0 Input P71 39 47 63 ANI1 Input P72 38 46 62 ANI2 Input P73 37 45 61 ANI3 Input P74 36 44 60 ANI4 Input P75 Note1 - 43 59 ANI5 Input P76 Note2 - - 58 ANI6 Input P77 Note2 - - 57 ANI7 Input P78 Note2 - - 56 ANI8 Input P79 Note2 - - 55 ANI9 Input Notes1. 2. Remark - V850ES/JC3-H (48 pin), V850ES/JE3-H only V850ES/JE3-H only (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) R/W Address: P7L FFFFF40EH, P7H FFFFF40FH P7H 0 0 0 0 0 0 P79Note1 P78Note1 P7L P77Note1 P76Note1 P75Note2 P74 P73 P72 P71 P70 P7n Output data control (in output mode) (n = 0 to 9) 0 Outputs 0. 1 Outputs 1. Notes1. 2. V850ES/JE3-H only V850ES/JC3-H (48 pin), V850ES/JE3-H only Caution Do not read or write the P7H and P7L registers during A/D conversion (see 14.6 (4) Alternate I/O). Remark These registers cannot be accessed in 16-bit units as the P7 register. They can be read or written in 8-bit or 1-bit units as the P7H and P7L registers. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 133 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) After reset: FFH PM7H PM7L 1 R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH 1 1 PM77Note1 PM76Note1 PM75Note2 PM7n 1 1 1 PM74 PM73 PM72 PM79Note1 PM78Note1 PM71 PM70 I/O mode control (n = 0 to 9) 0 Output mode 1 Input mode Notes1. 2. V850ES/JE3-H only V850ES/JC3-H (48 pin), V850ES/JE3-H only Caution When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1. Remark These registers cannot be accessed in 16-bit units as the PM7 register. They can be read or written in 8-bit or 1-bit units as the PM7H and PM7L registers. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 134 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.8 CHAPTER 4 PORT FUNCTIONS Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-15. Port 9 Alternate-Function Pins Pin Name Alternate-Function Pin Pin No. V850ES/JC3- V850ES/JC3-H H (40 pin) (48 pin) I/O Remark Name V850ES/JE3-H P92 Note - 35 47 TENC01/TIT01/TOT01 I/O Selectable as N-ch open-drain P93 Note - 36 48 TECR0/TIT00/TOT00 I/O output P94 Note - 38 50 TENC00/EVTT0 I/O 29 33 45 TIAA21/TOAA21 I/O P96 /INTP11 P97 30 34 46 SIF1/TIAA20/TOAA20 I/O P910 32 39 51 SIF3/TXDC2/INTP14 I/O P911 33 40 52 SOF3/RXDC2/INTP15 I/O P912 34 41 53 SCKF3 I/O P913 35 42 54 TOAB1OFF/INTP16 I/O Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Caution The P92 to P94, P96, P97, P910 to P913 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 135 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) P9 (P9H) (P9L) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 15 14 13 12 11 10 9 8 0 0 P913 P912 P911 P910 0 0 P97 P96 0 P94Note P93Note P92Note 0 0 P9n Output data control (in output mode) (n = 2 to 4, 6, 7, 10 to 13) 0 Outputs 0. 1 Outputs 1. Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P9 register as the P9H register and the lower 8 bits as the P9L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P9H register. (2) Port 9 mode register (PM9) After reset: FFFFH Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H 15 14 13 12 11 10 9 8 0 0 PM913 PM912 PM911 PM910 0 0 PM97 PM96 0 0 0 PM9 (PM9H) (PM9L) R/W PM9n PM94Note PM93Note PM92Note I/O mode control (in output mode) (n = 2 to 4, 6, 7 10 to 13) 0 Output mode 1 Input mode Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. The PM9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM9 register as the PM9H register and the lower 8 bits as the PM9L register, they can be read or written in 8-bit and 1-bit units. 2. To read/write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PM9H register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 136 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) After reset: 0000H PMC9 (PMC9H) (PMC9L) R/W 15 14 0 0 PMC97 PMC96 PMC913 Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 9 8 PMC913 PMC912 PMC911 PMC910 13 0 0 PMC94Note PMC93Note PMC92Note 0 0 0 12 11 10 Specification of P913 pin operation mode 0 I/O port 1 TOAB1OFF input/INTP16 input PMC912 Specification of P912 pin operation mode 0 I/O port 1 SCKF3 I/O PMC911 Specification of P911 pin operation mode 0 I/O port 1 SOF3 output/RXDC2 input/INTP15 input PMC910 Specification of P910 pin operation mode 0 I/O port 1 SIF3 input/TXDC2 output/INTP14 input PMC97 Specification of P97 pin operation mode 0 I/O port 1 SIF1 input/TIAA20 input/TOAA20 output PMC96 Specification of P96 pin operation mode 0 I/O port 1 TIAA21 input/TOAA21 output/INTP11 input PMC94 Specification of P94 pin operation mode 0 I/O port 1 TENC00 input/EVTT0 input PMC93 Specification of P93 pin operation mode 0 I/O port 1 TECR0 input/TIT00 input/TOT00 output PMC92 Specification of P92 pin operation mode 0 I/O port 1 TENC01 input/TIT01 input/TOT01 output Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. The PMC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC9 register as the PMC9H register and the lower 8 bits as the PMC9L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMC9H register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 137 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) After reset: 0000H Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H 15 14 13 12 11 10 9 8 0 0 PFC913 PFC912 PFC911 PFC910 0 0 PFC97 PFC96 0 PFC94Note PFC93Note PFC92Note 0 0 PFC9 (PFC9H) (PFC9L) R/W Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. For details of alternate function specification, see 4.3.9 (6) Port 9 alternate function specifications. 2. The PFC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC9 register as the PFC9H register and the lower 8 bits as the PFC9L register, they can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC9H register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 138 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (5) Port 9 function control expansion register (PFCE9) After reset: 0000H PFCE9 (PFCE9H) (PFCE9L) R/W 15 14 0 0 PFCE97 PFCE96 Address: PFCE9 FFFFF712H, PFCE9L FFFFF712H, PFCE9H FFFFF713H 9 8 PFCE913 PFCE912 PFCE911 PFCE910 13 0 0 PFCE94Note PFCE93Note PFCE92Note 0 0 0 12 11 10 Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. For details of alternate function specification, see 4.3.9 (6) Port 9 alternate function specifications. 2. The PFCE9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFCE9 register as the PFCE9H register and the lower 8 bits as the PFCE9L register, they can be read or written in 8-bit or 1bit units. 3. To read/write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFCE9H register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 139 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFC913 Specification of P913 pin alternate function 0 TOAB1OFF input/INTP16 input 1 Setting prohibited PFC912 Specification of P912 pin alternate function 0 SCKF3 I/O 1 Setting prohibited PFCE911 PFC911 Specification of P911 pin alternate function 0 0 SOF3 output 0 1 RXDC2 input 1 0 INTP15 input 1 1 Setting prohibited PFCE910 PFC910 Specification of P910 pin alternate function 0 0 SIF3 input 0 1 TXDC2 output 1 0 INTP14 input 1 1 Setting prohibited PFCE97 PFC97 0 0 SIF1 input 0 1 TIAA20 input 1 0 TOAA20 output 1 1 Setting prohibited PFCE96 PFC96 0 0 TIAA21 input 0 1 TOAA21 output 1 0 INTP11 input 1 1 Setting prohibited PFCE94 Note PFC94 0 0 Note Specification of P97 pin alternate function Specification of P96 pin alternate function Specification of P94 pin alternate function Setting prohibited 0 1 Setting prohibited 1 0 TENC00 input/EVTT0 input 1 1 Setting prohibited Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 140 of 1442 V850ES/JC3-H, V850ES/JE3-H PFCE93 Note PFC93 CHAPTER 4 PORT FUNCTIONS Note Specification of P93 pin alternate function 0 0 TECR0 input 0 1 TIT00 input 1 0 TOT00 output 1 1 Setting prohibited PFCE92 Note PFC92 Note Specification of P92 pin alternate function 0 0 TENC01 input 0 1 TIT01 input 1 0 TOT01 output 1 1 Setting prohibited Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 141 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.3.9 CHAPTER 4 PORT FUNCTIONS Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-16. Port DL Alternate-Function Pins Pin Name V850ES/JC3-H V850ES/JC3-H (40 pin) PDL5 Alternate-Function Pin No. 31 V850ES/JE3-H I/O Remark Pin Name (48 pin) 37 49 Note FLMD1 I/O - Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated with the port control register. For details, see CHAPTER 30 FLASH MEMORY. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 142 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) R/W Address: PDL 03FFF004H, PDLL 03FFF004H, PDLH 03FFF005H 15 14 13 12 11 10 9 8 PDL (PDLH) 0 0 0 0 0 0 0 0 (PDLL) 0 0 PDL5 0 0 0 0 0 PDL5 Output data control (in output mode) 0 Outputs 0. 1 Outputs 1. Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PDL register as the PDLH register and the lower 8 bits as the PDLL register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PDLH register. (2) Port DL mode register (PMDL) After reset: FFFFH R/W Address: PMDL 03FFF024H, PMDLL 03FFF024H, PMDLH 03FFF025H 15 14 13 12 11 10 9 8 PMDL (PMDLH) 0 0 0 0 0 0 0 0 (PMDLL) 0 0 PMDL5 0 0 0 0 0 PMDL5 I/O mode control 0 Output mode 1 Input mode Remarks 1. The PMDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMDLH register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 143 of 1442 V850ES/JC3-H, V850ES/JE3-H 4.4 CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-17 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 144 of 1442 Pin Name Alternate Function Name I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) P02 Note 1 NMI Input P02 = Setting not required PM02 = Setting not required PMC02 = 1 - P03 INTP02 Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 0 PFC03 = 0 ADTRG Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 0 PFC03 = 1 UCLK Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 1 PFC03 = 0 P10 Note 2 ANO0 Output P10 = Setting not required PM10 = 1 P30 TXDC0 Output P30 = Setting not required PM30 = Setting not required PMC30 = 1 PFCE30 = 0 PFC30 = 0 SOF4 Output P30 = Setting not required PM30 = Setting not required PMC30 = 1 PFCE30 = 0 PFC30 = 1 P31 P32 P33 Note 1 INTP07 Input P30 = Setting not required PM30 = Setting not required PMC30 = 1 PFCE30 = 1 PFC30 = 0 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 PFCE31 = 0 PFC31 = 0 SIF4 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 PFCE31 = 0 PFC31 = 1 INTP08 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 PFCE31 = 1 PFC31 = 0 ASCKC0 Input P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 0 PFC32 = 0 SCKF4 I/O P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 0 PFC32 = 1 TIAA00 Input P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 1 PFC32 = 0 TOAA00 Output P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 1 PFC32 = 1 TIAA01 Input P33 = Setting not required PM33 = Setting not required PMC33 = 1 PFCE33 = 0 PFC33 = 0 TOAA01 Output P33 = Setting not required PM33 = Setting not required PMC33 = 1 PFCE33 = 0 PFC33 = 1 RTCDIV Output P33 = Setting not required PM33 = Setting not required PMC33 = 1 PFCE33 = 1 PFC33 = 0 RTCCL Output P33 = Setting not required PM33 = Setting not required PMC33 = 1 PFCE33 = 1 PFC33 = 1 TIAA10 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 0 TOAA10 Output P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 1 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 0 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 0 TIAA11 Input P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 0 PFC35 = 0 TOAA11 Output P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 0 PFC35 = 1 RTC1HZ Output P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 1 PFC35 = 0 INTP09 P35 - RXDC0 TOAA1OFF Note 1 - Note 3 Page 145 of 1442 Notes 1. V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only CHAPTER 4 PORT FUNCTIONS P34 - - V850ES/JC3-H, V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Table 4-17. Using Port Pin as Alternate-Function Pin (1/4) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits I/O Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) TXDC3 Output P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 0 PFC36 = 0 SCL00 I/O P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 0 PFC36 = 1 CTXD0 Output P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 1 PFC36 = 0 RXDC3 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 0 PFC37 = 0 SDA00 I/O P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 0 PFC37 = 1 CRXD0Note 2 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 1 PFC37 = 0 SIF0 Input P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 0 PFC40 = 0 TXDC4 Output P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 0 PFC40 = 1 SDA01 I/O P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 1 PFC40 = 0 SOF0 Output P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 0 PFC41 = 0 RXDC4 Input P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 0 PFC41 = 1 Name P36 Note 1 Note 2 P37 Note 1 P40 P41 P42 SCL01 I/O P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 1 PFC41 = 0 SCKF0 I/O P42 = Setting not required PM42 = Setting not required PMC42 = 1 - PFC42 = 0 INTP10 Input P42 = Setting not required PM42 = Setting not required PMC42 = 1 - PFC42 = 1 Input P52 = Setting not required PM52 = Setting not required PMC52 = 1 PFCE52 = 0 PFC52 = 0 SIF2 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 0 PFC53 = 0 RTP03 Output P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 1 PFC53 = 1 P54 SOF2 Output P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 0 PFC54 = 0 KR4 Input P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 0 PFC54 = 1 RTP04 Output P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 1 PFC54 = 0 SCKF2 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 KR5 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 1 RTP05 Output P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 1 PFC55 = 0 TOAB1T1 Output P60 = Setting not required PM60 = Setting not required PMC60 = 1 PFCE60 = 0 PFC60 = 0 TOAB11 Output P60 = Setting not required PM60 = Setting not required PMC60 = 1 PFCE60 = 0 PFC60 = 0 TIAB11 Input P60 = Setting not required PM60 = Setting not required PMC60 = 1 PFCE60 = 0 PFC60 = 1 P55 P60 Note1 Page 146 of 1442 Notes1. 2. V850ES/JE3-H only PD70F3819, 70F3825 only PF37 (PF3) = 1 PF40 (PF4) = 0 PF41 (PF4) = 0 CHAPTER 4 PORT FUNCTIONS KR2 P53 PF36 (PF3) = 1 V850ES/JC3-H, V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Table 4-17. Using Port Pin as Alternate-Function Pin (2/4) Pin Name Alternate Function Name P61 Note1 P62 Note1 P63 Note1 P64 Note1 P65 Note1 I/O Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) TIAB10 Input P61 = Setting not required PM61 = Setting not required PMC61 = 1 PFCE61 = 0 PFC61 = 1 TOAB10 Output P61 = Setting not required PM61 = Setting not required PMC61 = 1 PFCE61 = 1 PFC61 = 0 TOAB1T2 Output P62 = Setting not required PM62 = Setting not required PMC62 = 1 PFCE62 = 0 PFC62 = 0 TOAB12 Output P62 = Setting not required PM62 = Setting not required PMC62 = 1 PFCE62 = 0 PFC62 = 0 TIAB12 Input P62 = Setting not required PM62 = Setting not required PMC62 = 1 PFCE62 = 0 PFC62 = 1 TOAB1B2 Output P63 = Setting not required PM63 = Setting not required PMC63 = 1 PFCE63 = 0 PFC63 = 0 TRGAB1 Input P63 = Setting not required PM63 = Setting not required PMC63 = 1 PFCE63 = 0 PFC63 = 1 TOAB1T3 Output P64 = Setting not required PM64 = Setting not required PMC64 = 1 PFCE64 = 0 PFC64 = 0 TOAB13 Output P64 = Setting not required PM64 = Setting not required PMC64 = 1 PFCE64 = 0 PFC64 = 0 TIAB13 Input P64 = Setting not required PM64 = Setting not required PMC64 = 1 PFCE64 = 0 PFC64 = 1 TOAB1B3 Output P65 = Setting not required PM65 = Setting not required PMC65 = 1 PFCE65 = 0 PFC63 = 0 PFCE65 = 0 PFC65 = 1 EVTAB1 Input P65 = Setting not required PM65 = Setting not required PMC65 = 1 P70 ANI0 Input P70 = Setting not required PM70 = 1 - - - P71 ANI1 Input P71 = Setting not required PM71 = 1 - - - P72 ANI2 Input P72 = Setting not required PM72 = 1 - - - P73 ANI3 Input P73 = Setting not required PM73 = 1 - - - ANI4 Input P74 = Setting not required PM74 = 1 - - - P75 Note2 ANI5 Input P75 = Setting not required PM75 = 1 - - - Note1 ANI6 Input P76 = Setting not required PM76 = 1 - - - P77 Note1 ANI7 Input P77 = Setting not required PM77 = 1 - - - P78 Note1 ANI8 Input P78 = Setting not required PM78 = 1 - - - Note1 ANI9 Input P79 = Setting not required PM79 = 1 - - - P76 P79 Notes 1. V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only Page 147 of 1442 CHAPTER 4 PORT FUNCTIONS P74 V850ES/JC3-H, V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Table 4-17. Using Port Pin as Alternate-Function Pin (3/4) Pin Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Name P92 Note1 TENC01 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 0 TIT01 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 1 TOT01 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 1 PFC92 = 0 TECR0 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 0 P93 Note1 P94 Note1 P96 P910 P911 I/O TIT00 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 1 TOT00 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 1 PFC93 = 0 TENC00 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 1 PFC94 = 0 EVTT0 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 1 PFC94 = 0 TIAA21 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 0 PFC96 = 0 TOAA21 Output P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 INTP11 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 TIAA20 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 1 TOAA20 Output P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 1 PFC97 = 0 SIF3 Input P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 0 PFC910 = 0 TXDC2 Output P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 0 PFC910 = 1 INTP14 Input P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 1 PFC910 = 0 SOF3 Output P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 0 PFC911 = 0 RXDC2 Input P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 0 PFC911 = 1 Input P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 1 PFC911 = 0 SCKF3 I/O P912 = Setting not required PM912 = Setting not required PMC912 = 1 - PFC912 = 0 P913 TOAB1OFF Input P913 = Setting not required PM913 = Setting not required PMC913 = 1 - PFC913 = 0 INTP16 Input P913 = Setting not required PM913 = Setting not required PMC913 = 1 - PFC913 = 0 FLMD1Note2 Input PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = Setting not required - PDL5 - Notes 1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. Since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register. FLASH MEMORY. For details, see CHAPTER 30 Page 148 of 1442 CHAPTER 4 PORT FUNCTIONS INTP15 P912 V850ES/JC3-H, V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Table 4-17. Using Port Pin as Alternate-Function Pin (4/4) V850ES/JC3-H, V850ES/JE3-H 4.5 4.5.1 CHAPTER 4 PORT FUNCTIONS Cautions Cautions on setting port pins (1) In the V850ES/JC3-H and V850ES/JE3-H, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode) by setting the PMCn register. Note the following cautions with regards to this register setting sequence. (a) Cautions on switching from port mode to alternate-function mode Switch from the port mode to alternate-function mode in the following order. <1> Set the PFn registerNote 1: N-ch open-drain setting <2> Set the PFCn and PFCEn registers: Alternate-function selection <3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode <4> Set the INTRn and INTFn registersNote 2: External interrupt setting If the PMCn register is set first, note that unexpected operations may occur at that moment or depending on the change of the pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers. A concrete example is shown in [Example] below. Notes 1. N-ch open-drain output pin only 2. Only when the external interrupt function is selected Caution Regardless of the port mode/alternate-function mode, the Pn register is read and written as follows. * Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read the pin states (PMn.PMnm bit = 1). * Pn register write: Write to the port output latch [Example] SCL01 pin setting example The SCL01 pin is used alternately as the P41/SOF0 pin. Select the valid pin function using the PMC4, PFC4, and PF4 registers. PMC41 Bit PFC41 Bit PF41 Bit Valid Pin Function 0 don't care 1 P41 (in output port mode, N-ch open-drain output) 1 0 1 SOF0 output (N-ch open-drain output) 1 1 SCL01 I/O (N-ch open-drain output) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 149 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin is shown below. Setting Procedure <1> Setting Contents Initial value Pin State Pin Level Port mode (input) Hi-Z SOF0 output Low level (high level depending on the (PMC41 bit = 0, PFC41 bit = 0, PF41 bit = 0) <2> PMC41 bit 1 CSIF0 setting) <3> PFC41 bit 1 SCL01 I/O High level (CMOS output) <4> PF41 bit 1 SCL01 I/O Hi-Z (N-ch open-drain output) In <2>, I2C communication may be affected since the alternate-function SOF0 output is output to the pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated. (b) Cautions on alternate-function mode (input) The signal input to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternatefunction operation enable timing, unexpected operations may occur. Therefore, switch between the port mode and alternate-function mode in the following sequence. * To switch from port mode to alternate-function mode (input) Set the pins to the alternate-function mode using the PMCn register and then enable the alternate-function operation. * To switch from alternate-function mode (input) to port mode Stop the alternate-function operation and then switch the pins to the port mode. Concrete examples are shown in [Example 1] and [Example 2]. [Example 1] Switching from general-purpose port (P02) to external interrupt pin (NMI) When the P02/NMI pin is pulled up as shown in Figure 4-4 and the rising edge is specified by the NMI pin edge detection setting, even though a high level is input continuously to the NMI pin when switching from the P02 pin to the an NMI pin (PMC02 bit = 0 1), this is detected as a rising edge as if a low level changed to a high level, and an NMI interrupt occurs. To avoid this, set the NMI pin's valid edge after switching from the P02 pin to the NMI pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 150 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS Figure 4-4. Example of Switching from P02 to NMI (Incorrect) 7 6 5 4 3 2 1 0 01 PMC0 3V PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Rising edge detector P02/NMI PMC02 bit = 0: Low level PMC02 bit = 1: High level Remark m = 2, 3 [Example 2] Switching from external pin (NMI) to general-purpose port (P02) When the P02/NMI pin is pulled up as shown in Figure 4-5 and the falling edge is specified by the NMI pin edge detection setting, even though a high level is input continuously to the NMI pin when switching from the NMI pin to the P02 pin (PMC02 bit = 1 0), this is detected as a falling edge as if a high level changed to a low level, and an NMI interrupt occurs. To avoid this, set the NMI pin edge detection as "No edge detected" before switching to the P02 pin. Figure 4-5. Example of Switching from NMI to P02 (Incorrect) 7 6 5 4 3 2 1 0 10 PMC0 3V PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Falling edge detector P02/NMI PMC02 bit = 1: High level PMC02 bit = 0: Low level Remark m = 2, 3 (2) In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit = 0). In the input mode (PMnm bit = 1), the value of the PFnm bit is not reflected in the buffer. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 151 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 4 PORT FUNCTIONS 4.5.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. 4.5.3 Cautions on on-chip debug pins (V850ES/JC3-H only) The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used. The following action must be taken if on-chip debugging is not used. * Clear the OCDM0 bit of the OCDM register (special register) (0) At this time, fix the P56/INTP05/DRST pin to low level from when reset by the RESET pin is released until the above action is taken. If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock). Handle the P56 pin with the utmost care. Caution 4.5.4 After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the P56/INTP05/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM register holds the current value. Cautions on P56/INTP05/DRST pin The P56/INTP05/DRST pin has an internal pull-down resistor (30 k TYP.). After a reset by the RESET pin, a pulldown resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0). 4.5.5 Cautions on P10 and P53 pins when power is turned on When the power is turned on, the following pins may output an undefined level temporarily even during reset. * P10/ANO0 pin * P53/SIF2/KR3/RTP03/DDO pin (V850ES/JC3-H (48 pin), V850ES/JE3-H only) 4.5.6 Hysteresis characteristics In port mode, the following port pins do not have hysteresis characteristics. P02, P03 P30 to P37 P40 to P42 P52 to P56 P60 to P65 P92 to P94, P96, P97, P910 to P913 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 152 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION CHAPTER 5 CLOCK GENERATION FUNCTION 5.1 Overview The following clock generation functions are available. Main clock oscillator * In clock-through mode fX = 3.0 to 6.0 MHz (fXX = 3.0 to 6.0 MHz) * In PLL mode fX = 3.0 to 6.0 MHz (x8: fXX = 24 to 48 MHz) Subclock oscillator * fXT = 32.768 kHz Multiply (x8) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable Internal oscillator * fR = 220 kHz (TYP.) Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function Remark fX: Main clock oscillation frequency fXX: Main clock frequency fXT: Subclock frequency fR: Internal oscillation clock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 153 of 1442 V850ES/JC3-H, V850ES/JE3-H 5.2 CHAPTER 5 CLOCK GENERATION FUNCTION Configuration Figure 5-1. Clock Generator FRC bit XT1 Subclock oscillator XT2 fXT fXT RTC clock, WDT clock Prescaler 3 PLL Main clock oscillator stop control IDLE mode IDLE fXX control CK2 to CK0 bits Prescaler 2 fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX STOP mode SELPLL bit Internal oscillator fR HALT mode Selector Main clock oscillator fX CLS, CK3 bits Selector X2 PLLON bit Selector X1 IDLE control Selector MFRC bit RTC clock HALT fCPU control 1/8 divider fCLK CPU clock Internal system clock WDT clock, TMM clock RSTOP bit Port CM CLKOUT UCLK Remark Prescaler 1 Selector UCKSEL bit fX: Main clock oscillation frequency fXX: Main clock frequency Peripheral clock USB clock fCLK: Internal system clock frequency fXT: Subclock frequency fCPU: CPU clock frequency fR: Internal oscillation clock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 154 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (fX). * In clock-through mode fX = 3.0 to 6.0 MHz * In PLL mode fX = 3.0 to 6.0 MHz (x8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Internal oscillator Oscillates a frequency (fR) of 220 kHz (TYP.). (5) Prescaler 1 This prescaler generates the clock (fXX to fXX/1,024) to be supplied to the following on-chip peripheral functions: TAA, TAB, TMM, TMT, CSIF, UARTC, I2C, CAN, ADC, DAC, WDT2 (6) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin. (7) Prescaler 3 This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz) and supplies that clock to the real-time counter (RTC) block. (8) PLL This circuit multiplies the clock generated by the main clock oscillator (fX) by 8. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 155 of 1442 V850ES/JC3-H, V850ES/JE3-H 5.3 CHAPTER 5 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 156 of 1442 V850ES/JC3-H, V850ES/JE3-H After reset: 03H CHAPTER 5 CLOCK GENERATION FUNCTION R/W Address: FFFFF828H < > < > PCC FRC MCK MFRC FRC Note CLS < > CK3 CK2 CK1 CK0 Use of subclock on-chip feedback resistor 0 Used 1 Not used MCK Main clock oscillator control 0 Oscillation enabled 1 Oscillation stopped * Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. * When the main clock is stopped and the device is operating with the subclock, clear (0) the MCK bit and secure the oscillation stabilization time by software before switching the CPU clock to the main clock or operating the on-chip peripheral functions. MFRC Use of main clock on-chip feedback resistor 0 Used 1 Not used CLSNote Status of CPU clock (fCPU) 0 Main clock operation 1 Subclock operation CK3 CK2 CK1 CK0 Clock selection (fCLK/fCPU) 0 0 0 0 fXX 0 0 0 1 fXX/2 0 0 1 0 fXX/4 0 0 1 1 fXX/8 0 1 0 0 fXX/16 0 1 0 1 fXX/32 0 1 1 x Setting prohibited 1 x x x fXT Note The CLS bit is a read-only bit. Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. Remark x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 157 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation subclock operation <1> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit 1: Set the MCK bit to 1 only when stopping the main clock. Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip peripheral functions operating with the main clock. 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting the CK2 to CK0 bits [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 <1> _SET_SUB_RUN : st.b r0, PRCMD[r0] set1 3, PCC[r0] -- CK3 bit 1 <2> _CHECK_CLS : tst1 4, PCC[r0] bz _CHECK_CLS -- Wait until subclock operation starts. <3> _STOP_MAIN_CLOCK : st.b r0, PRCMD[r0] set1 6, PCC[r0] -- MCK bit 1, main clock is stopped. _DMA_ENABLE: setl Remark 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed loop. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 158 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation main clock operation <1> MCK bit 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit 0: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <4> Main clock operation: It takes the following time after the CK3 bit is set until main clock operation is started. Max.: 1/fXT (1/subclock frequency) Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. Caution Enable operation of the on-chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. If their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 <1> _START_MAIN_OSC : st.b r0, PRCMD[r0] -- Release of protection of special registers clr1 6, PCC[r0] -- Main clock starts oscillating. 0x55, r0, r11 -- Wait for oscillation stabilization time. <2> movea _WAIT_OST : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _WAIT_OST <3> st.b clr1 r0, PRCMD[r0] 3, PCC[r0] -- CK3 0 <4> _CHECK_CLS : tst1 4, PCC[r0] bnz _CHECK_CLS -- Wait until main clock operation starts. _DMA_ENABLE: setl Remark 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 The description above is simply an example. Note that in <4> above, the CLS bit is read in a closed loop. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 159 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF80CH < > RCM 0 0 0 RSTOP 0 0 0 0 RSTOP Oscillation/stop of internal oscillator 0 Internal oscillator oscillation 1 Internal oscillator stopped Cautions 1. The internal oscillator cannot be stopped while the CPU is operating on the internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1. 2. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time, the RSTOP bit remains being set to 1. (3) CPU operation clock status register (CCLS) The CCLS register indicates the status of the CPU operation clock. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00HNote CCLS 0 R Address: FFFFF82EH 0 CCLSF 0 0 0 0 0 CCLSF CPU operation clock status 0 Operating on main clock (fX) or subclock (fXT). 1 Operating on internal oscillation clock (fR). Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set to 1 and the reset value is 01H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 160 of 1442 V850ES/JC3-H, V850ES/JE3-H 5.4 5.4.1 CHAPTER 5 CLOCK GENERATION FUNCTION Operation Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLK Bit = 0, MCK Bit = 0 During Reset During Oscillation Stabilization Main clock oscillator (fX) CLS Bit = 1, MCK Bit = 0 MCK Bit = 1 HALT IDLE1, STOP Subclock Sub-IDLE Subclock Sub- Mode IDLE2 Mode Mode Mode Mode IDLE Mode Time Count Target Clock CLS Bit = 1, Mode x x x x Subclock oscillator (fXT) x x x x x x x Note x x x x x CPU clock (fCPU) x x Internal system clock (fCLK) x Main clock (in PLL mode, fXX) x Peripheral clock (fXX to x x x x x x x x x x x x x fXX/1,024) WT clock (main) x x WT clock (sub) WDT2 clock (internal oscillation) x WDT2 clock (main) x x x x x WDT2 clock (sub) Note Lockup time Remark : Operable x: Stopped 5.4.2 Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 5-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 161 of 1442 V850ES/JC3-H, V850ES/JE3-H 5.5 5.5.1 CHAPTER 5 CLOCK GENERATION FUNCTION PLL Function Overview In the V850ES/JC3-H and V850ES/JE3-H, an operating clock that is 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions. When PLL function is used (x8): Input clock = 3.0 to 6.0 MHz (output: 24 to 48 MHz) Clock-through mode: 5.5.2 Input clock = 3.0 to 6.0 MHz (output: 3.0 to 6.0 MHz) Registers (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the PLL function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. After reset: 01H PLLCTL 0 R/W Address: FFFFF82CH 0 0 0 PLLON 0 0 < > < > SELPLL PLLON PLL operation stop register 0 PLL stopped 1 PLL operating (After PLL operation starts, a lockup time is required for frequency stabilization) SELPLL CPU operation clock selection register 0 Clock-through mode 1 PLL mode Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clockthrough mode). 2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not (unlocked), "0" is written to the SELPLL bit if data is written to it. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 162 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 0AH. After reset: 0AH CKC 0 R/W 0 CKDIV0 Address: FFFFF822H 0 0 1 0 1 CKDIV0 Internal system clock (fXX) in PLL mode 0 Setting prohibited 1 fXX = 8 x fX (fX = 3.0 to 6.0 MHz) Caution 1. Be sure to set the CKC register to 0BH. When setting this register to a value other than 0BH or leaving it set to its initial value without setting it to 0BH, enabling PLL operation (PLLCTL.SELPLL = 1) is prohibited. 2. Be sure to set bits 3 and 1 to ``1'' and clear bits 7 to 4 and 2 to ``0''. Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is divided by the PCC register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 163 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R Address: FFFFF824H < > LOCKR 0 0 0 LOCK 0 0 0 0 LOCK PLL lock status check 0 Locked status 1 Unlocked status Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear conditions are as follows. [Set conditions] * Upon system resetNote * In IDLE2 or STOP mode * Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0) * Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of PCC.MCK bit to 1) Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the oscillation stabilization time has elapsed. [Clear conditions] * Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 24.2 (3) Oscillation stabilization time select register (OSTS))) * Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release, when the STOP mode was set in the PLL operating status * Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed from 0 to 1 * After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register) when the IDLE2 mode is set during PLL operation. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 164 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 5 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H. After reset: 03H R/W Address: FFFFF6C1H 0 0 PLLS1 PLLS0 0 0 210/fX 0 1 211/fX 1 0 212/fX 1 1 213/fX (default value) PLLS 0 0 0 0 PLLS1 PLLS0 Selection of PLL lockup time Cautions 1. Set so that the lockup time is 800 s or longer. 2. Do not change the PLLS register setting during the lockup period. 5.5.3 Usage (1) When PLL is used * After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). * To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0). * The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from the IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows. (a) When transiting to the IDLE2 or STOP mode from the clock through mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer. * IDLE2 mode: Set the OSTS register so that the setup time is 350 s (min.) or longer. (b) When transiting to the IDLE 2 or STOP mode while remaining in the PLL operation mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer. * IDLE2 mode: Set the OSTS register so that the setup time is 800 s (min.) or longer. When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary. (2) When PLL is not used * The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 165 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.1 Overview An overview of TAAn is shown below. * 16 bit timer/counter (TAAn) * Clock selection: 8 ways * Capture/trigger input pins (TIAAm0, TIAAk1): 2 * External event count input pinsNote: 1 * External trigger input pinNote: 1 * Timer/counter: 1 * Capture/compare registers: 2 (32-bit capture timer function available by using a cascade connection with TAA.) * Capture/compare match interrupt request signals: 2 * Timer output pins (TOAAm0, TOAAm1): 2 Note External event count input pins and external trigger input pins are alternately used as capture/trigger input pins (TIAAm0). Remark n = 0 to 2, 4 m = 0 to 2 k = 2 (V850ES/JC3-H) k =0 to 2 (V850ES/JE3-H) 6.2 Functions TAAn has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement * Timer-tuned function * Simultaneous-start function R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 166 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.3 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Configuration TAAn includes the following hardware. Table 6-1. Configuration of TAAn Item Configuration 16-bit counter Registers TAAn capture/compare registers 0, 1 (TAAnCCR0, TAAnCCR1) TAAn counter read buffer register (TAAnCNT) CCR0, CCR1 buffer registers TAAn control registers 0, 1 (TAAnCTL0, TAAnCTL1) TAAm I/O control registers 0 to 2, 4 (TAAmIOC0 to TAAmIOC2, TAAmIOC4) TAAm option registers 0, 1 (TAAmOPT0, TAAmOPT1) TAA noise elimination control register (TANFC) Timer inputs Note 1 Note 1 Timer outputs Note 2 2 (TIAAm0 , TIAAk1 pins) 2 (TOAAm0, TOAAm1 pins) Notes 1. When using the functions of the TIAAm0, TIAAm1, TOAAm0, and TOAAm1 pins, see Table 4-17 Using Port Pin as Alternate-Function Pin. 2. The TIAAm0 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. Remark n = 0 to 2, 4 m = 0 to 2 k = 2 (V850ES/JC3-H) k =0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 167 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-1. Block Diagram of TAAn Internal bus Selector TAAnCNT Clear TIAAk1 Edge detector CCR0 buffer register TIAAm0 INTTAAnOV 16-bit counter Output controller Selector Note fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 CCR1 buffer register TOAAm0 TOAAm1 INTTAAnCC0 INTTAAnCC1 TAAnCCR0 TAAnCCR1 Internal bus Note TAA2: fXX/2, fXX/4, fXX/8, fXX/16, fXX/64, fXX/256, fXX/512, fXX/1024. Remark fXX: Main clock frequency n = 0 to 2, 4 m = 0 to 2 k = 2 (V850ES/JC3-H) k =0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 168 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TAAnCNT register is read at this time, 0000H is read. Reset sets the TAAnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAAnCCR0 register is used as a compare register, the value written to the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated. The CCR0 buffer register cannot be read or written directly. Reset clears the TAAnCCR0 register to 0000H. Therefore, the CCR0 buffer register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAAnCCR1 register is used as a compare register, the value written to the TAAnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. The CCR1 buffer register cannot be read or written directly. Reset clears the TAAnCCR1 register to 0000H. Therefore, the CCR1 buffer register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIAAm0 and TIAAm1 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TAAmIOC1 and TAAmIOC2 registers. (5) Output controller This circuit controls the output of the TOAAm0 and TOAAm1 pins. The outputs of the TOAAm0 and TOAAm1 pins are controlled by the TAAmIOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 169 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.3.1 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Pin configuration The timer inputs and outputs that configure TAAn are shared with the following ports. The port functions must be set when using each pin (see Table 4-17 When Using Port Pins as Alternate-Function Pins). Table 6-2 Pin Configuration Channel TAA0 Port P32 P33 TAA1 TAA2 TAA4 TIAA00 Note 2 P34 P35 Timer AA Input TIAA01 TIAA10 Note 2 Timer AA Output Note 1 Note 1 TIAA11 P97 TIAA20 P96 TIAA21 Note 1 Other Alternate Function TOAA00 ASCK0/SCKF4 TOAA01 RTCDIV/RTCCL TOAA10 TOAA1OFF TOAA11 RTC1HZ TOAA20 SIF1 TOAA21 INTP11 Note 2 /INTP09 - - - - - - - - Notes 1. The TAAm0 pin functions alternately as a capture trigger input function, external event input function, and external trigger input function. 2. The V850ES/JE3-H only Cautions1. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TAAnCTL1.TAAnEEE bit to 0). 2. To use the external event count mode, specify that the valid edge of the TIAAn0 pin capture trigger input is not detected (by setting the TAAnCTL1.TAAnEEE bit to 1). Remarks1. TAA4 has no timer input pin and output pin functions. When TAA4 is used solely, therefore, only the interval timer function can be used. The 6-phase PWM output function is available by using TAA4 in combination with TAB1. 2. n = 0 to 2, 4 m = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 170 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.4 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Registers The registers that control TAAn are as follows. * TAAn control register 0 (TAAnCTL0) * TAAn control register 1 (TAAnCTL1) * TAAn I/O control register 0 (TAAmIOC0) * TAAn I/O control register 1 (TAAmIOC1) * TAAn I/O control register 2 (TAAmIOC2) * TAAn I/O control register 4 (TAAmIOC4) * TAAn option register 0 (TAAmOPT0) * TAAn option register 1 (TAAmOPT1) * TAAn capture/compare register 0 (TAAnCCR0) * TAAn capture/compare register 1 (TAAnCCR1) * TAAn counter read buffer register (TAAnCNT) * TAA noise elimination control register (TANFC) Remarks 1. When using the functions of the TIAAm0, TIAAm1, TOAAm0, and TOAAm1 pins, see Table 4-17 Using Port Pin as Alternate-Function Pin. 2. n = 0 to 2, 4 m = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 171 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) TAAn control register 0 (TAAnCTL0) The TAAnCTL0 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TAAnCTL0 register by software. After reset: 00H R/W Address: TAA0CTL0 FFFFF630H, TAA1CTL0 FFFFF640H, TAA2CTL0 FFFFF650H, TAA4CTL0 FFFFF670H TAAnCTL0 7 6 5 4 3 TAAnCE 0 0 0 0 2 1 0 TAAnCKS2 TAAnCKS1 TAAnCKS0 (n = 0 to 2, 4) TAAnCE TAAn operation control 0 TAAn operation disabled (TAAn reset asynchronouslyNote ). 1 TAAn operation enabled. TAAn operation started. TAAnCKS2 TAAnCKS1 TAAnCKS0 Internal count clock selection n = 0, 1, 4 n=2 0 0 0 fXX (20.8 ns) fXX/2 (41.7 ns) 0 0 1 fXX/2 (41.7 ns) fXX/4 (83.3 ns) 0 1 0 fXX/4 (83.3 ns) fXX/8 (166.7 ns) 0 1 1 fXX/8 (166.7 ns) fXX/16 (333.3 ns) 1 0 0 fXX/16 (333.3 ns) fXX/64 (1.3333 s) 1 0 1 fXX/32 (666.7 ns) fXX/256 (5.3333 s) 1 1 0 fXX/64 (1.3333 s) fXX/512 (10.6667 s) 1 1 1 fXX/128 (2.6667 s) fXX/1024 (21.3333 s) Note TAAnOPT0.TAAnOVF bit, 16-bit counter, timer output (TOAAn0, TOAAn1 pins) Cautions 1. Set the TAAnCKS2 to TAAnCKS0 bits when the TAAnCE bit = 0. When the value of the TAAnCE bit is changed from 0 to 1, the TAAnCKS2 to TAAnCKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to "0". Remark fXX: Main clock frequency The values in parentheses indicate the cycles when fXX = 48 MHz. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 172 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) TAAn control register 1 (TAAnCTL1) The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H R/W Address: TAA0CTL1 FFFFF631H, TAA1CTL1 FFFFF641H, TAA2CTL1 FFFFF651H, TAA4CTL1 FFFFF671H 7 TAA0CTL1 6 5 4 TAA0SYE TAA0EST TAA0EEETAA0SYM TAA1CTL1 0 3 2 1 0 0 TAA0MD2 TAA0MD1 TAA0MD0 TAA1EST TAA1EEE 0 0 TAA1MD2 TAA1MD1 TAA1MD0 TAA2CTL1 TAA2SYE TAA2EST TAA2EEE 0 0 TAA2MD2 TAA2MD1 TAA2MD0 TAA4CTL1 TAA4SYE TAA4SYM 0 TAA4MD2 TAA4MD1 TAA4MD0 0 0 TAAmSYETAAmSYM Tuned operation mode enable control (m = 0, 4) 0 0 Independent operation mode (asynchronous operation mode) 0 1 Setting prohibited 1 0 Tuned-operation function (specification of slave operation) 1 1 Simultaneous-start function (specification of slave timer) These bits can be set only for the slave timer (setting them for the master timer is prohibited). The relationship between the master timer and slave timer is as follows. Master timer Slave timer TAA1 TAA0 TAB1 TAA4 For the tuned-operation function, see 6.6 Timer-Tuned Operation Function. For the simultaneous-start function, see 6.7 Simultaneous-Start Function. TAAnEST Software trigger control (n = 0 to 2) 0 - 1 Generates a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TAAnEST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TAAnEST bit as the trigger. Cautions 1. The TAAnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. Be sure to clear the sections of the TAAnCTL1 register of each channel, where 0 is specified, to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 173 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) TAAmEEE Count clock selection 0 Disables operation with external event count input. (Performs counting with the count clock selected by the TAAmCTL0.TAAmCK0 to TAAmCK2 bits.) 1 Enables operation with external event count input. (Performs counting at every valid edge of the external event count input signal.) The TAAmEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TAAnMD2 TAAnMD1 TAAnMD0 Timer mode selection 0 0 0 Interval timer mode 0 0 1 External event count mode 0 1 0 External trigger pulse output mode 0 1 1 One-shot pulse output mode 1 0 0 PWM output mode 1 0 1 Free-running timer mode 1 1 0 Pulse width measurement mode 1 1 1 Setting prohibited Cautions 1. External event count input is selected in the external event count mode regardless of the value of the TAAmEEE bit. 2. Set the TAAmEEE and TAAmMD2 to TAAmMD0 bits when the TAAmCTL0.TAAmCE bit = 0. (The same value can be written when the TAAmCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TAAmCE bit = 1. If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again (m = 0 to 3, 5). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 174 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) TAAn I/O control register 0 (TAAnIOC0) The TAAnIOC0 register is an 8-bit register that controls the timer output (TOAAn0, TOAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TAA0IOC0 FFFFF632H, TAA1IOC0 FFFFF642H, TAA2IOC0 FFFFF652H, TAAnIOC0 7 6 5 4 0 0 0 0 3 2 1 0 TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 (n = 0 to 2) TOAAn1 pin output level settingNote TAAnOL1 0 TOAAn1 pin output starts at high level 1 TOAAn1 pin output starts at low level TAAnOE1 TOAAn1 pin output setting 0 Timer output disabled * When TAAnOL1 bit = 0: Low level is output from the TOAAn1 pin * When TAAnOL1 bit = 1: High level is output from the TOAAn1 pin 1 Timer output enabled (a square wave is output from the TOAAn1 pin). TOAAn0 pin output level settingNote TAAnOL0 0 TOAAn0 pin output starts at high level 1 TOAAn0 pin output starts at low level TAAnOE0 TOAAn0 pin output setting 0 Timer output disabled * When TAAnOL0 bit = 0: Low level is output from the TOAAn0 pin * When TAAnOL0 bit = 1: High level is output from the TOAAn0 pin 1 Timer output enabled (a square wave is output from the TOAAn0 pin). Note The output level of the timer output pin (TOAAnm) specified by the TAAnOLm bit is shown below. * When TAAnOLm bit = 0 16-bit counter * When TAAnOLm bit = 1 16-bit counter TAAnCE bit TAAnCE bit TOAAnm pin output TOAAnm pin output Cautions 1. Rewrite the TAAnOL1, TAAnOE1, TAAnOL0, and TAAnOE0 bits when the TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. Even if the TAAnOLm bit is manipulated when the TAAnCE and TAAnOEm bits are 0, the TOAAnm pin output level varies. Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 m = 0, 1 Page 175 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (4) TAAn I/O control register 1 (TAAnIOC1) The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAAn0, TIAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TAA0IOC1 FFFFF633H, TAA1IOC1 FFFFF643H, TAA2IOC1 FFFFF653H TAAnIOC1 7 6 5 4 0 0 0 0 3 2 0 1 TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0 (n = 0 to 2) TAAnIS3 TAAnIS2 Capture trigger input signal (TIAAn1 pin)Note valid edge setting 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAAnIS1 TAAnIS0 Capture trigger input signal (TIAAn0 pin) valid edge setting 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Note n = 2 (V850ES/JC3-H) n = 0 to 2 (V850ES/JE3-H) Cautions 1. Rewrite the TAAnIS3 to TAAnCTL0.TAAnCE bit = 0. TAAnIS0 bits when the (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. The TAAnIS3 to TAAnIS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 176 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (5) TAAn I/O control register 2 (TAAnIOC2) The TAAnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIAAn0 pin) and external trigger input signal (TIAAn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TAAnIOC2 (n = 0 to 2) R/W Address: TAA0IOC2 FFFFF634H, TAA1IOC2 FFFFF644H, TAA2IOC2 FFFFF654H 7 6 5 4 0 0 0 0 3 2 1 0 TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnEES1 TAAnEES0 External event count input signal (TIAAn0 pin) valid edge setting 0 0 No edge detection (external event count invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAAnETS1 TAAnETS0 External trigger input signal (TIAAn0 pin) valid edge setting 0 0 No edge detection (external trigger invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TAAnEES1, TAAnEES0, TAAnETS1, and TAAnETS0 bits when the TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. The TAAnEES1 and TAAnEES0 bits are valid only when the TAAnCTL1.TAAnEEE bit = 1 or when the external event count mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 001) has been set. 3. The TAAnETS1 and TAAnETS0 bits are valid only when the external trigger pulse output mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 010) or the one-shot pulse output mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 = 011) is set. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 177 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (6) TAAn I/O control register 4 (TAAnIOC4) The TAAnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TAAnCTL0.TAAnCE = 0). Cautions 1. Accessing the TAAnIOC4 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock 2. The TAAnIOC4 register can be set only in the interval timer mode and free-running timer mode. Be sure to set the TAAnIOC4 register to 00H in all other modes (for details of the mode setting, see 6.4 (2) TAAn control register 1 (TAAnCTL1)). The TAAnIOC4 register setting is invalid if the TAAnCCR0 and TAAnCCR1 registers are set to the capture function, even if the free-running timer mode is set. After reset: 00H R/W Address: TAA0IOC4 FFFFF63CH, TAA1IOC4 FFFFF64CH, TAA2IOC4 FFFFF65CH TAAnIOC4 7 6 5 4 0 0 0 0 3 2 1 0 TAAnOS1 TAAnOR1 TAAnOS0 TAAnOR0 (n = 0 to 2) Toggle control of TIAAn1 pin TAAnOS1 TAAnOR1 0 0 No request. Normal toggle operation. 0 1 Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCR1 register. 1 0 Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCR1 register. 1 1 Keep request Keep current output level. TAAnOS0 TAAnOR0 Toggle control of TIAAn0 0 0 No request. Normal toggle operation. 0 1 Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCR0 register. 1 0 Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCR0 register. 1 1 Keep request Keep current output level. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 178 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (7) TAAn option register 0 (TAAnOPT0) The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TAA0OPT0 FFFFF635H, TAA1OPT0 FFFFF645H, TAA2OPT0 FFFFF655H TAAnOPT0 7 6 0 0 5 4 TAAnCCS1TAAnCCS0 3 2 1 0 0 0 0 TAAnOVF (n = 0 to 2) TAAnCCS1 TAAnCCR1 register capture/compare selection 0 Compare register selected 1 Capture register selected The TAAnCCS1 bit setting is valid only in the free-running timer mode. TAAnCCS0 TAAnCCR0 register capture/compare selection 0 Compare register selected 1 Capture register selected The TAAnCCS0 bit setting is valid only in the free-running timer mode. TAAnOVF TAAn overflow detection flag Set (1) Overflow occurred Reset (0) 0 written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0 * The TAAnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTAAnOV) is generated at the same time that the TAAnOVF bit is set to 1. The INTTAAnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TAAnOVF bit is not cleared even when the TAAnOVF bit or the TAAnOPT0 register are read when the TAAnOVF bit = 1. * The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TAAn. Cautions 1. Rewrite the TAAnCCS1 and TAAnCCS0 bits when the TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. Be sure to set bits 1 to 3, 6, and 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 179 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (8) TAAn option register 1 (TAAnOPT1) The TAAnOPT1 register is an 8-bit register that controls the 32-bit capture function realized by a cascade connection. Rewriting this register is prohibited while the timer is operating (TAAnCTL0.TAAnCE = 1). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TAAnOPT1 R/W Address: TAA0OPT1 FFFFF63DH, TAA2OPT1 FFFFF65DH 7 6 5 4 3 2 1 0 TAAnCSE 0 0 0 0 0 0 0 (n = 0, 2) TAAnCSE Cascade control 0 Individual operation or operation as lower side of cascade function 1 Operation as higher side of cascade function Cautions 1. Cascade connection and timer-tuned operation cannot be used together. Be sure to set TAAnCTL1.TAAnSYE to 0 for a cascade connection. 2. For a cascade connection, set the free-running timer mode and use the TAAnCCR0 and TAAnCCR1 registers as capture registers. For details of cascade connection, see 6.8 Cascade Connection. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 180 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (9) TAAn capture/compare register 0 (TAAnCCR0) The TAAnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS0 bit. In the pulse width measurement mode, the TAAnCCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAAnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAAnCCR0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TAA0CCR0 FFFFF636H, TAA1CCR0 FFFFF646H, TAA2CCR0 FFFFF656H, TAA4CCR0 FFFFF676H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAAnCCR0 (n = 0 to 2, 4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 181 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated. If TOAAn0 pin output is enabled at this time, the output of the TOAAn0 pin is inverted. When the TAAnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TAAnCCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAAnCCR0 register if the valid edge of the capture trigger input pin (TIAAn0 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAAnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAAn0) is detected. Even if the capture operation and reading the TAAnCCR0 register conflict, the correct value of the TAAnCCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Page 182 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (10) TAAn capture/compare register 1 (TAAnCCR1) The TAAnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS1 bit. In the pulse width measurement mode, the TAAnCCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAAnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAAnCCR1 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TAA0CCR1 FFFFF638H, TAA1CCR1 FFFFF648H, TAA2CCR1 FFFFF658H, TAA4CCR1 FFFFF678H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAAnCCR1 (n = 0 to 2, 4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 183 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR1 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. If TOAAn1 pin output is enabled at this time, the output of the TOAAn1 pin is inverted. (b) Function as capture register When the TAAnCCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAAnCCR1 register if the valid edge of the capture trigger input pin (TIAAn1 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAAnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAAn1) is detected. Even if the capture operation and reading the TAAnCCR1 register conflict, the correct value of the TAAnCCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Page 184 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (11) TAAn counter read buffer register (TAAnCNT) The TAAnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAAnCTL0.TAAnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TAAnCNT register is cleared to 0000H when the TAAnCE bit = 0. If the TAAnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. Reset clears the TAAnCE bit to 0. Therefore, the value of the TAAnCNT register is cleared to 0000H. Caution Accessing the TAAnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R Address: TAA0CNT FFFFF63AH, TAA1CNT FFFFF64AH, TAA2CNT FFFFF65AH, TAA4CNT FFFFF67AH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAAnCNT (n = 0 to 2, 4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 185 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (12) Noise elimination control register (TANFC) Digital noise elimination can be selected for the TIAAn0 and TIAAm1 pins. The noise elimination setting is selected using the TANFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX and fXX/4. Sampling is performed 3 times. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Time equal to the sampling clock x 3 clocks is required until the digital noise eliminator is initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and TIAAn1 is input after the sampling clock has been changed and before the time of the sampling clock x 3 clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using the external trigger function, the external event function, and the capture trigger function of TAA, enable TAA operation after the time of the sampling clock x 3 clocks has elapsed. Remark n = 0 to 2 m = 2 (V850ES/JC3-H) 0 to 2 (V850ES/JE3-H) After reset: 00H TANFC R/W TANFEN 0 TANFEN Address: FFFFF724H 0 0 0 0 0 TANFC0 Setting of digital noise elimination 0 Does not perform digital noise elimination 1 Performs digital noise elimination TANFC0 Digital sampling clock 0 fXX 1 fXX/4 Remarks 1. Since sampling is performed 3 times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 186 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) A timing example of noise elimination performed by the timer AA input pin digital filter is shown Figure 6-2. Figure 6-2. Example of Digital Noise Elimination Timing Noise elimination clock Input signal Sampling 3 times Sampling 3 times 1 clock 1 clock 2 clocks 2 clocks 3 clocks 3 clocks Internal signal Remarks1. If there are two or fewer noise elimination clocks while the TIAAn0 or TIAAm1 input signal is high level (or low level), that input signal is eliminated as noise. If it is sampled three times or more, the edge is detected as a valid input. 2. n = 0 to 2 m = 2 (V850ES/JC3-H) m = 0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 187 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.5 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Operation TAAn can perform the following operations. Operation Interval timer mode External event count mode Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 TAAnCTL1.TAAmEST Bit TIAAn0 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input) Register Setting Write Invalid Invalid Compare only Anytime write Invalid Invalid Compare only Anytime write Valid Valid Compare only Batch write Valid Valid Compare only Anytime write Invalid Invalid Compare only Batch write Invalid Invalid Switching enabled Anytime write Invalid Invalid Capture only Not applicable Notes 1. To use the external event count mode, specify that the valid edge of the TIAAn0 pin capture trigger input is not detected (by clearing the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TAAnCTL1.TAAnEEE bit to 0). Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 188 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Anytime write and batch write With TAAn, the TAAnCCR0 and TAAnCCR1 registers can be rewritten during timer operation (TAAnCTL0.TAAnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. Figure 6-3. Example of Basic Anytime Write Operation Flowchart (Interval Timer Mode of TAA0) START Initial settings * Set values to TAACCRn register * Timer operation enable (TAA0CE bit = 1) Transfer values of TAA0CCRn register to CCRn buffer register TAA0CCRn register rewrite Transfer to CCRn buffer register Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start INTTAA0CC1 signal output INTTAA0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 n = 0, 1 Page 189 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-4. Example of Anytime Write Timing (Interval Timer Mode of TAA0) TAA0CE bit = 1 D01 FFFFH D01 D02 16-bit counter D11 D11 D12 D12 0000H D01 TAA0CCR0 register CCR0 buffer register 0000H D01 D11 TAA0CCR1 register CCR1 buffer register D02 0000H D02 D12 D11 D12 INTTAA0C0 signal INTTAA0CC1 signal Remark D01, D02: Set values of TAA0CCR0 register D11, D12: Set values of TAA0CCR1 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 190 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Batch write In this mode, data is transferred all at once from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TAAnCCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TAAnCCR1 register. In order for the set value when the TAAnCCR0 and TAAnCCR1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1 buffer registers), it is necessary to rewrite the TAAnCCR0 register and then write to the TAAnCCR1 register before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TAAnCCR0 and TAAnCCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite the value of the TAAnCCR0 register, also write the same value (same as preset value of the TAAnCCR1 register) to the TAAnCCR1 register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 191 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-5. Example of Basic Batch Write Operation Flowchart (PWM Output Mode of TAA0) START Initial settings * Set values to TAA0CCRn register * Enable timer operation (TAA0CE bit = 1) Transfer values of TAA0CCRn register to CCRn buffer register TAA0CCR0 register rewrite TAA0CCR1 register rewrite Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start * Transfer of values of TAA0CCRn register to CCRn buffer register Batch write enable INTTAA0CC1 signal output INTTAA0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TAA0CCR1 register includes enabling of batch write. Thus, rewrite the TAA0CCR1 register after rewriting the TAA0CCR0 register. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 192 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-6. Timing of Batch Write (Interval Timer Mode of TAA0) TAA0CE bit = 1 D01 FFFFH D02 D11 D12 16-bit counter D03 D02 D12 D12 D12 0000H D01 TAA0CCR0 register CCR0 buffer register 0000H TAA0CCR1 register CCR1 buffer register D02 D01 D11 0000H D03 D02 Note 1 Note 2 D12 D11 D12 Note 1 Note 1 Same value write D12 Note 3 D03 D12 Note 1 INTTAA0CC0 signal INTTAA0CC1 signal TOAA00 pin output TOAA01 pin output Notes 1. Because the TAA0CCR1 register was not rewritten, D03 is not transferred. 2. Because the TAA0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TAA0CCR0 register (D01). 3. Because the TAA0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TAA0CCR0 register (D02). Remark D01, D02, D03: Set values of TAA0CCR0 register D11, D12: R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Set values of TAA0CCR1 register Page 193 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.5.1 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0 pin. Usually, the TAAnCCR1 register is not used in the interval timer mode. Figure 6-7. Configuration of Interval Timer Clear Count clock selection Output controller 16-bit counter Match signal TAAnCE bit TOAAm0 pin INTTAAnCC0 signal CCR0 buffer register TAAnCCR0 register Remark m = 0 to 2 n = 0 to 2, 4 Figure 6-8. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 0000H TAAnCE bit TAAnCCR0 register D0 TOAAm0 pin output INTTAAnCC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Remark m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 194 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOAAn0 pin is inverted, and a compare match interrupt request signal (INTTAAnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TAAnCCR0 register + 1) x Count clock cycle Remark m = 0 to 2 n = 0 to 2, 4 Figure 6-9. Register Settings for Interval Timer Mode Operation (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 TAAnCKS2 TAAnCKS1 TAAnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAmEST TAAmEEE TAAnCTL1 0 0 0/1Note TAAnMD2 TAAnMD1 TAAnMD0 0 0 0 0 0 0, 0, 0: Interval timer mode 0: Operates on count clock selected by TAAmCKS0 to TAAmCKS2 bits 1: Counts with external event count input signal Note This bit can be set to 1 only when the interrupt request signals (INTTAAmCC0 and INTTAAmCC1) are masked by the interrupt mask flags (TAAmCCMK0 and TAAmCCMK1) and timer output (TOAAm1) is performed. However, set the TAAmCCR0 and TAAmCCR1 registers to the same value (see 6.5.1 (2) (d) Operation of TAAnCCR1 register). Remark m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 195 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-9. Register Settings for Interval Timer Mode Operation (2/2) (c) TAAm I/O control register 0 (TAAmIOC0) TAAmOL1 TAAmOE1TAAmOL0 TAAmOE0 TAAmIOC0 0 0 0 0 0/1 0/1 0/1 0/1 0: Disables TOAAm0 pin output 1: Enables TOAAm0 pin output Setting of output level with operation of TOAAm0 pin disabled 0: Low level 1: High level 0: Disables TOAAm1 pin output 1: Enables TOAAm1 pin output Setting of output level with operation of TOAAm1 pin disabled 0: Low level 1: High level (d) TAAn counter read buffer register (TAAnCNT) By reading the TAAnCNT register, the count value of the 16-bit counter can be read. (e) TAAn capture/compare register 0 (TAAnCCR0) If the TAAnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TAAn capture/compare register 1 (TAAnCCR1) Usually, the TAAnCCR1 register is not used in the interval timer mode. However, the set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal (INTTAAnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TAAnCCMK1). Remarks 1. TAAm I/O control register 1 (TAAmIOC1), TAAm I/O control register 2 (TAAmIOC2), and TAAm option register 0 (TAAmOPT0) are not used in the interval timer mode. 2. m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 196 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Interval timer mode operation flow Figure 6-10. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TAAnCE bit TAAnCCR0 register D0 TOAAm0 pin output INTTAAnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAmIOC0 register, TAAnCCR0 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). <2> Count operation stop flow TAAnCE bit = 0 The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. STOP Remark m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 197 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Interval timer mode operation timing (a) Operation if TAAnCCR0 register is set to 0000H If the TAAnCCR0 register is set to 0000H, the INTTAAnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAAm0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TAAnCE bit TAAnCCR0 register 0000H TOAAm0 pin output INTTAAnCC0 signal Interval time Count clock cycle Remark Interval time Count clock cycle m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 198 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTAAnCC0 signal is generated and the output of the TOAAm0 pin is inverted. At this time, an overflow interrupt request signal (INTTAAnOV) is not generated, nor is the overflow flag (TAAmOPT0.TAAmOVF bit) set to 1. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register FFFFH TOAAm0 pin output INTTAAnCC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle Remark m = 0 to 2 n = 0 to 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 199 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Notes on rewriting TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 D1 16-bit counter D2 D2 D2 0000H TAAnCE bit D1 TAAnCCR0 register TAAnOL0 bit D2 L TOAAm0 pin output INTTAAnCC0 signal Interval time (1) Remarks 1. Interval time (1): Interval time (NG) Interval time (2) (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle 2. m = 0 to 2 n = 0 to 2, 4 If the value of the TAAnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTAAnCC0 signal is generated and the output of the TOAAm0 pin is inverted. Therefore, the INTTAAnCC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" as originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 200 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Operation of TAAnCCR1 register Figure 6-11. Configuration of TAAnCCR1 Register TAAnCCR1 register CCR1 buffer register Output controller Match signal TOAAn1 pinNote INTTAAnCC1 signal Clear Count clock selection 16-bit counter Output controller Match signal TAAnCE bit TOAAn0 pin INTTAAnCC0 signal CCR0 buffer register TAAnCCR0 register Note The TOAA01 pin and TOAA11 pin are only in The V850ES/JE3-H. Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 201 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is less than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is generated once per cycle. At the same time, the output of the TOAAn1 pin is inverted. The TOAAn1 pin outputs a square wave with the same cycle as that output by the TOAAn0 pin. Figure 6-12. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TAAnCE bit TAAnCCR0 register D01 TOAAn0 pin output INTTAAnCC0 signal TAAnCCR1 register D11 TOAAn1 pin output INTTAAnCC1 signal Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 202 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the count value of the 16-bit counter does not match the value of the TAAnCCR1 register. Consequently, the INTTAAnCC1 signal is not generated, nor is the output of the TOAAn1 pin changed. Figure 6-13. Timing Chart When D01 < D11 FFFFH D01 D01 D01 D01 16-bit counter 0000H TAAnCE bit TAAnCCR0 register D01 TOAAn0 pin output INTTAAnCC0 signal D11 TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal Remark L n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 203 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.5.2 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) External event count mode (TAAnMD2 to TAAnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified number of edges have been counted. The TOAAn0 pin cannot be used. Usually, the TAAnCCR1 register is not used in the external event count mode. Figure 6-14. Configuration in External Event Count Mode Clear TIAAn0 pin (external event count input) Edge detector 16-bit counter Match signal TAAnCE bit INTTAAnCC0 signal CCR0 buffer register TAAnCCR0 register Remark n = 0 to 2 Figure 6-15. Basic Timing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H 16-bit counter TAAnCE bit External event count input (TIAAn0 pin input) TAAnCCR0 register TAAnCCR0 register D0 D0 - 1 D0 0000 0001 D0 INTTAAnCC0 signal INTTAAnCC0 signal External event count interval (D0 + 1) External event count interval (D0 + 1) External event count interval (D0 + 1) Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 204 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated. The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TAAnCCR0 register + 1) times. Figure 6-16. Register Setting for Operation in External Event Count Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0 0 0 0 0 0 0 0 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0 0 TAAnMD2 TAAnMD1 TAAnMD0 0 0 0 0 1 0, 0, 1: External event count mode (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0 0 0 0 0 0 0 0 0: Disables TOAAn0 pin output 0: Disables TOAAn1 pin output (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 205 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-16. Register Setting for Operation in External Event Count Mode (2/2) (e) TAAn counter read buffer register (TAAnCNT) The count value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare register 0 (TAAnCCR0) If D0 is set to the TAAnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTAAnCC0) is generated when the number of external event counts reaches (D0 + 1). (g) TAAn capture/compare register 1 (TAAnCCR1) Usually, the TAAnCCR1 register is not used in the external event count mode. However, the set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. Therefore, mask the interrupt signal by using the interrupt mask flag (TAAnCCMK1). Caution When an external clock is used as the count clock, the external clock can be input only from the TIAAn0 pin. At this time, set the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture trigger input (TIAAn0 pin): no edge detection). Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the external event count mode. 2. n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 206 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) External event count mode operation flow Figure 6-17. Flow of Software Processing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TAAnCE bit TAAnCCR0 register D0 INTTAAnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). <2> Count operation stop flow TAAnCE bit = 0 The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. STOP Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 207 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TAAnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation of the count clock to be enabled by the external event count input (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 000, TAAnCTL1.TAAnEEE bit = 1). (a) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTAAnCC0 signal is generated. At this time, the TAAnOPT0.TAAnOVF bit is not set. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register FFFFH INTTAAnCC0 signal External event count signal interval Remark External event count signal interval External event count signal interval n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 208 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Notes on rewriting the TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter D1 D2 D2 D2 0000H TAAnCE bit D1 TAAnCCR0 register D2 INTTAAnCC0 signal External event count signal interval (1) (D1 + 1) Remark External event count signal interval (NG) (10000H + D2 + 1) External event count signal interval (2) (D2 + 1) n = 0 to 2 If the value of the TAAnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTAAnCC0 signal is generated. Therefore, the INTTAAnCC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" as originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 209 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Operation of TAAnCCR1 register Figure 6-18. Configuration of TAAnCCR1 Register TAAnCCR1 register CCR1 buffer register Match signal INTTAAnCC1 signal Clear Edge detector TIAAn0 pin 16-bit counter Match signal TAAnCE bit INTTAAnCC0 signal CCR0 buffer register TAAnCCR0 register Remark n = 0 to 2 If the set value of the TAAnCCR1 register is smaller than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is generated once per cycle. Figure 6-19. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TAAnCE bit TAAnCCR0 register D01 INTTAAnCC0 signal TAAnCCR1 register D11 INTTAAnCC1 signal Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 210 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TAAnCCR1 register do not match. Figure 6-20. Timing Chart When D01 < D11 FFFFH D01 D01 D01 D01 16-bit counter 0000H TAAnCE bit TAAnCCR0 register D01 INTTAAnCC0 signal D11 TAAnCCR1 register INTTAAnCC1 signal Remark L n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 211 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.5.3 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter AA starts counting, and outputs a PWM waveform from the TOAAn1 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOAAn0 pin. Figure 6-21. Configuration in External Trigger Pulse Output Mode TAAnCCR1 register Edge detector TIAAn0 pin Transfer CCR1 buffer register Software trigger generation Output S controller R (RS-FF) Match signal TOAAn1 pin INTTAAnCC1 signal Clear Count clock selection Count start control 16-bit counter Output controller Match signal TAAnCE bit TOAAn0 pin INTTAAnCC0 signal CCR0 buffer register Transfer TAAnCCR0 register Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 212 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-22. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 D1 16-bit counter D0 D0 D1 D1 D0 D1 0000H TAAnCE bit External trigger input (TIAAn0 pin input) D0 TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output (only when software trigger is used) D1 TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) 16-bit timer/event counter AA waits for a trigger when the TAAnCE bit is set to 1. When the trigger is generated, the 16bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOAAn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOAAn0 pin is inverted. The TOAAn1 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAAnCCR1 register) x Count clock cycle Cycle = (Set value of TAAnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1) The compare match request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H at the same time. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the trigger. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 213 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 TAAnCKS2 TAAnCKS1 TAAnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0/1 TAAnMD2 TAAnMD1 TAAnMD0 0 0 0 0 1 0 0, 1, 0: External trigger pulse output mode Generates software trigger when 1 is written (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0 0 0 0 0/1 0/1 0/1Note 0/1Note 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low * When TAAnOL1 bit = 0 * When TAAnOL1 bit = 1 16-bit counter 16-bit counter TOAAn1 pin output TOAAn1 pin output Note Clear this bit to 0 when the TOAAn0 pin is not used in the external trigger pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 214 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the external trigger pulse output mode. 2. n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 215 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in external trigger pulse output mode Figure 6-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter D00 D10 D00 D10 D01 D01 D11 D10 D11 D00 D10 0000H TAAnCE bit External trigger input (TIAAn0 pin input) TAAnCCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTAAnCC0 signal TOAAn0 pin output (only when software trigger is used) D10 TAAnCCR1 register D10 D11 D10 CCR1 buffer register D10 D10 D11 D10 INTTAAnCC1 signal TOAAn1 pin output <1> Remark <2> <3> <4> <5> n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 216 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TAAnCCR0, TAAnCCR1 register setting change flow START Setting of TAAnCCR1 register Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. Only writing of the TAAnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TAAnCCRm register is transferred to the CCRm buffer register. <4> TAAnCCR0, TAAnCCR1 register setting change flow The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting is enabled (TAAnCE bit = 1). Trigger wait status Setting of TAAnCCR0 register When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. Setting of TAAnCCR1 register <2> TAAnCCR0 and TAAnCCR1 register setting change flow Setting of TAAnCCR0 register Setting of TAAnCCR1 register Remark <5> Count operation stop flow TAAnCCR1 register write processing is necessary only when the set cycle is changed. TAAnCE bit = 0 When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. STOP Counting is stopped. n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 217 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC0 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TAAnCE bit External trigger input (TIAAn0 pin input) TAAnCCR0 register CCR0 buffer register D00 D01 D00 D01 INTTAAnCC0 signal TOAAn0 pin output (only when software trigger is used) TAAnCCR1 register CCR1 buffer register D10 D10 D11 D11 INTTAAnCC1 signal TOAAn1 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 218 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) In order to transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level width to the TAAnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write the same value to the TAAnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to be set. After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with writing the TAAnCCRm register. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 219 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAAnCE bit TAAnCCR0 register D0 D0 D0 TAAnCCR1 register 0000H 0000H 0000H INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output Remark n = 0 to 2 To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAAnCE bit TAAnCCR0 register D0 D0 D0 TAAnCCR1 register D0 + 1 D0 + 1 D0 + 1 INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 220 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Conflict between trigger detection and match with TAAnCCR1 register If the trigger is detected immediately after the INTTAAnCC1 signal is generated, the 16-bit counter is cleared to 0000H at the same time, the output signal of the TOAAn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF D1 - 1 0000 0000 External trigger input (TIAAn0 pin input) D1 TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output Shortened Remark n = 0 to 2 If the trigger is detected immediately before the INTTAAnCC1 signal is generated, the INTTAAnCC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOAAn1 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter FFFF 0000 D1 - 2 0000 0001 D1 - 1 D1 External trigger input (TIAAn0 pin input) TAAnCCR1 register D1 INTTAAnCC1 signal TOAAn1 pin output Extended Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 221 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Conflict between trigger detection and match with TAAnCCR0 register If the trigger is detected immediately after the INTTAAnCC0 signal is generated, the 16-bit counter is cleared to 0000H again and continues counting up. Therefore, the active period of the TOAAn1 pin is extended by the time from generation of the INTTAAnCC0 signal to trigger detection. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0000 External trigger input (TIAAn0 pin input) D0 TAAnCCR0 register INTTAAnCC0 signal TOAAn1 pin output Extended Remark n = 0 to 2 If the trigger is detected immediately before the INTTAAnCC0 signal is generated, the INTTAAnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOAAn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 External trigger input (TIAAn0 pin input) TAAnCCR0 register D0 INTTAAnCC0 signal TOAAn1 pin output Shortened Remark n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 222 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the external trigger pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter TAAnCCR1 register D1 - 2 D1 - 1 D1 D1 + 1 D1 + 2 D1 TOAAn1 pin output INTTAAnCC1 signal Remark n = 0 to 2 Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up, after the count value of the 16-bit counter matches the value of the TAAnCCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOAAn1 pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 223 of 1442 V850ES/JC3-H, V850ES/JE3-H 6.5.4 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter AA starts counting, and outputs a one-shot pulse from the TOAAn1 pin. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOAAn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 6-25. Configuration in One-Shot Pulse Output Mode TAAnCCR1 register Edge detector TIAAn0 pin Transfer Output S controller R (RS-FF) CCR1 buffer register Software trigger generation Match signal TOAAn1 pin INTTAAnCC1 signal Clear Count clock selection Count start control Output S controller R (RS-FF) 16-bit counter Match signal TAAnCE bit TOAAn0 pin INTTAAnCC0 signal CCR0 buffer register Transfer TAAnCCR0 register Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 224 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-26. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 16-bit counter D1 D0 D1 D0 D1 0000H TAAnCE bit External trigger input (TIAAn0 pin input) D0 TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output (only when software trigger is used) TAAnCCR1 register D1 INTTAAnCC1 signal TOAAn1 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Active Delay level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) When the TAAnCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAAn1 pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TAAnCCR1 register) x Count clock cycle Active level width = (Set value of TAAnCCR0 register - Set value of TAAnCCR1 register + 1) x Count clock cycle The compare match interrupt request signal INTTAAnCC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the trigger. Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 225 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-27. Register Setting for Operation in One-Shot Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 TAAnCKS2 TAAnCKS1 TAAnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0/1 0 TAAnMD2 TAAnMD1 TAAnMD0 0 0 0 1 1 0, 1, 1: One-shot pulse output mode Generates software trigger when 1 is written (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0 0 0 0 0/1 0/1 0/1Note 0/1Note 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low * When TAAnOL1 bit = 0 * When TAAnOL1 bit = 1 16-bit counter 16-bit counter TOAAn1 pin output TOAAn1 pin output Note Clear this bit to 0 when the TOAAn0 pin is not used in the one-shot pulse output mode. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 226 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 - D1 + 1) x Count clock cycle Output delay period = (D1) x Count clock cycle Caution One-shot pulses are not output even in the one-shot pulse output mode, if the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register. Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the one-shot pulse output mode. 2. n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 227 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in one-shot pulse output mode Figure 6-28. Software Processing Flow in One-Shot Pulse Output Mode FFFFH D00 D01 16-bit counter D10 D11 0000H TAAnCE bit External trigger input (TIAAn0 pin input) TAAnCCR0 register D00 D01 D10 D11 INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output <1> <2> <1> Count operation start flow <3> <2> TAAnCCR0, TAAnCCR1 register setting change flow START Setting of TAAnCCR0, TAAnCCR1 registers Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register TAAnCE bit = 1 Remark Initial setting of these registers is performed before setting the TAAnCE bit to 1. As rewriting the TAAnCCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTAAnCCR0 signal is recommended. <3> Count operation stop flow The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). Trigger wait status TAAnCE bit = 0 Count operation is stopped STOP n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 228 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TAAnCCRm register To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D00 16-bit counter D00 D10 D10 D00 D10 D01 D11 0000H TAAnCE bit External trigger input (TIAAn0 pin input) D00 TAAnCCR0 register D01 INTTAAnCC0 signal TOAAn0 pin output (only when software trigger is used) TAAnCCR1 register D10 D11 INTTAAnCC1 signal TOAAn1 pin output Delay (D10) Active level width (D00 - D10 + 1) Delay (D10) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) When the TAAnCCR0 register is rewritten from D00 to D01 and the TAAnCCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TAAnCCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TAAnCCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1 pin. When the count value matches D01, the counter generates the INTTAAnCC0 signal, deasserts the TOAAn1 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 229 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Generation timing of compare match interrupt request signal (INTTAAnCC1) The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter D1 - 2 D1 - 1 TAAnCCR1 register D1 D1 + 1 D1 + 2 D1 TOAAn1 pin output INTTAAnCC1 signal Remark n = 0 to 2 Usually, the INTTAAnCC1 signal is generated the next time the 16-bit counter counts after its count value matches the value of the TAAnCCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOAAn1 pin. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 230 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.5.5 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAAn0 pin. Figure 6-29. Configuration in PWM Output Mode TAAnCCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOAAn1 pin INTTAAnCC1 signal Clear Count clock selection 16-bit counter Output controller Match signal TAAnCE bit TOAAn0 pin INTTAAnCC0 signal CCR0 buffer register Transfer TAAnCCR0 register Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 231 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-30. Basic Timing in PWM Output Mode FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TAAnCE bit TAAnCCR0 register D00 CCR0 buffer register D01 D00 D01 INTTAAnCC0 signal TOAAn0 pin output D10 TAAnCCR1 register D11 D10 CCR1 buffer register D11 INTTAAnCC1 signal TOAAn1 pin output Active period (D10) Cycle (D00 + 1) Inactive period (D00 - D10 + 1) When the TAAnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOAAn1 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAAnCCR1 register) x Count clock cycle Cycle = (Set value of TAAnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1) The PWM waveform can be changed by rewriting the TAAnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 232 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-31. Setting of Registers in PWM Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 TAAnCKS2 TAAnCKS1 TAAnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 1 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0 TAAnMD2 TAAnMD1 TAAnMD0 0/1 0 0 1 0 0 1, 0, 0: PWM output mode 0: Operates on count clock selected by TAAnCKS0 to TAAnCKS2 bits 1: Counts external event input signal (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0 0 0 0 0/1 0/1 0/1Note 2 0/1Note 2 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low * When TAAnOL1 bit = 0 * When TAAnOL1 bit = 1 16-bit counter 16-bit counter TOAAn1 pin output TOAAn1 pin output Notes 1. The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1. 2. Clear this bit to 0 when the TOAAn0 pin is not used in the PWM output mode. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 233 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-31. Setting of Registers in PWM Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the PWM output mode. 2. n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 234 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in PWM output mode Figure 6-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D00 D01 D00 D10 D10 D01 D11 D11 D10 D00 D10 0000H TAAnCE bit TAAnCCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTAAnCC0 signal TOAAn0 pin output D10 TAAnCCR1 register D10 D10 CCR1 buffer register D11 D10 D10 D11 D10 INTTAAnCC1 signal TOAAn1 pin output <1> Remark <2> <3> <4> <5> n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 235 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-32. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TAAnCCR0, TAAnCCR1 register setting change flow START Setting of TAAnCCR1 register Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. Only writing of the TAAnCCR1 register must be performed when only the set duty factor is changed. When the counter is cleared after setting, the value of compare register m is transferred to the CCRm buffer register. <4> TAAnCCR0, TAAnCCR1 register setting change flow The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting is enabled (TAAnCE bit = 1). Setting of TAAnCCR0 register When the counter is cleared after setting, the values of compare register m are transferred to the CCRm buffer register in a batch. Setting of TAAnCCR1 register <2> TAAnCCR0, TAAnCCR1 register setting change flow Setting of TAAnCCR0 register Setting of TAAnCCR1 register Remark <5> Count operation stop flow TAAnCCR1 write processing is necessary even if only the set cycle is changed. When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. TAAnCE bit = 0 Counting is stopped. STOP n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 236 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D01 D11 D11 0000H TAAnCE bit TAAnCCR0 register D00 D01 CCR0 buffer register TAAnCCR1 register CCR1 buffer register D00 D10 D01 D11 D10 D11 TOAAn1 pin output INTTAAnCC0 signal To transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level to the TAAnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write the same value to the TAAnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to be set. After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with writing the TAAnCCRm register. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 237 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TAAnCE bit TAAnCCR0 register D00 D00 D00 TAAnCCR1 register 0000H 0000H 0000H INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output Remark n = 0 to 2 To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TAAnCE bit TAAnCCR0 register D00 D00 D00 TAAnCCR1 register D00 + 1 D00 + 1 D00 + 1 INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 238 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter TAAnCCR1 register D1 - 2 D1 - 1 D1 D1 + 1 D1 + 2 D1 TOAAn1 pin output INTTAAnCC1 signal Remark n = 0 to 2 Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the TAAnCCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOAAn1 pin. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 239 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.5.6 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits. Figure 6-33. Configuration in Free-Running Timer Mode TAAnCCR1 register (compare) TAAnCCR0 register (compare) Output controller TOAAn1 pin output Output controller TOAAn0 pin output TAAnCCS0, TAAnCCS1 bits (capture/compare selection) Internal count clock TIAAn0 pin (external event count input/ capture trigger input) Edge detector Count clock selection 0 TAAnCE bit Remark INTTAAnCC1 signal 1 Edge detector 0 TAAnCCR0 register (capture) TIAAn1 pin (capture trigger input) INTTAAnOV signal 16-bit counter INTTAAnCC0 signal 1 Edge detector TAAnCCR1 register (capture) n = 0 to 2 m = 2 (V850ES/JC3-H) m = 0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 240 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0 and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TAAnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Figure 6-34. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH D00 D00 D01 16-bit counter D10 D10 D11 D01 D11 D11 0000H TAAnCE bit TAAnCCR0 register D00 D01 INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register D10 D11 INTTAAnCC1 signal TOAAn1 pin output INTTAAnOV signal TAAnOVF bit Cleared to 0 by CLR instruction Remark Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 241 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal (INTTAAnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 6-35. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH D10 D00 16-bit counter D11 D12 D13 D01 D02 D03 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register D00 D01 D02 D03 INTTAAnCC0 signal TIAAm1 pin input TAAnCCR1 register D10 D11 D12 D13 INTTAAnCC1 signal INTTAAnOV signal TAAnOVF bit Cleared to 0 by CLR instruction Remark Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction n = 0 to 2 m = 2 (V850ES/JC3-H) m = 0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 242 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-36. Register Setting in Free-Running Timer Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1 (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0 0/1 TAAnMD2 TAAnMD1 TAAnMD0 0 0 1 0 1 1, 0, 1: Free-running mode 0: Operates with count clock selected by TAAnCKS0 to TAAnCKS2 bits 1: Counts on external event count input signal (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0 0 0 0 0/1 0/1 0/1 0/1 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level with operation of TOAAn0 pin disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Sets output level with operation of TOAAn1 pin disabled 0: Low level 1: High level R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 243 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-36. Register Setting in Free-Running Timer Mode (2/2) (d) TAAn I/O control register 1 (TAAnIOC1) TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0 TAAnIOC1 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of TIAAn0 pin input Select valid edge of TIAAn1 pin input (e) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (f) TAAn option register 0 (TAAnOPT0) TAAnCCS1 TAAnCCS0 TAAnOPT0 0 0 0/1 0/1 TAAnOVF 0 0 0 0/1 Overflow flag Specifies if TAAnCCR0 register functions as capture or compare register Specifies if TAAnCCR1 register functions as capture or compare register (g) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (h) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) These registers function as capture registers or compare registers depending on the setting of the TAAnOPT0.TAAnCCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIAAnm pin is detected. When the registers function as compare registers and when Dm is set to the TAAnCCRm register, the INTTAAnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOAAnm pin is inverted. Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 244 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 D00 D01 16-bit counter D10 D10 D01 D11 D11 D11 0000H TAAnCE bit TAAnCCR0 register D00 D01 Set value changed INTTAAnCC0 signal TOAAn0 pin output D10 TAAnCCR1 register D11 Set value changed INTTAAnCC1 signal TOAAn1 pin output INTTAAnOV signal TAAnOVF bit <1> Cleared to 0 by CLR instruction <2> Remark Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <3> <2> n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 245 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnOPT0 register, TAAnCCR0 register, TAAnCCR1 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). <2> Overflow flag clear flow Read TAAnOPT0 register (check overflow flag). TAAnOVF bit = 1 NO YES Execute instruction to clear TAAnOVF bit (CLR TAAnOVF). <3> Count operation stop flow TAAnCE bit = 0 Counter is initialized and counting is stopped by clearing TAAnCE bit to 0. STOP Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 246 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) When using capture/compare register as capture register Figure 6-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input D01 D00 TAAnCCR0 register TAAnOVF1 flagNote TIAAm1 pin input <1> Remark D11 D10 TAAnCCR1 register <2> <3> <4> <5> <6> n = 0 to 2 m = 2 (V850ES/JC3-H) m = 0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 247 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC1 register, TAAnOPT0 register TAAnCE bit = 1 Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). <2> Overflow flag clear flow Read TAAnOPT0 register (check overflow flag). TAAnOVF bit = 1 NO YES Execute instruction to clear TAAnOVF bit (CLR TAAnOVF). <3> Count operation stop flow TAAnCE bit = 0 Counter is initialized and counting is stopped by clearing TAAnCE bit to 0. STOP Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 248 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in free-running timer mode (a) Interval operation with TAAnCCRm register used as compare register When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAAnCCm signal has been detected. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TAAnCE bit TAAnCCR0 register D00 D01 D02 D03 D04 D05 INTTAAnCC0 signal TOAAn0 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TAAnCCR1 register D10 D11 D12 D13 D14 INTTAAnCC1 signal TOAAn1 pin output Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TAAnCCRm register must be re-set in the interrupt servicing that is executed when the INTTAAnCCm signal is detected. The set value for re-setting the TAAnCCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent times: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark m = 0, 1 n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 249 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Pulse width measurement with TAAnCCRm used as capture register When pulse width measurement is performed with the TAAnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAAnCCm signal has been detected and for calculating the interval. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TAAnCE bit TIAAn0 pin input TAAnCCR0 register 0000H D00 D01 D02 D03 D04 INTTAAnCC0 signal Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TIAAn1 pin input TAAnCCR1 register 0000H D10 D11 D12 D13 INTTAAnCC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) INTTAAnOV signal TAAnOVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TAAnCCRm register in synchronization with the INTTAAnCCm signal, and calculating the difference between the read value and the previously read value. Remark m = 0, 1 n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 250 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register D01 D00 TIAAn1 pin input D11 D10 TAAnCCR1 register INTTAAnOV signal TAAnOVF bit <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input). <3> Read the TAAnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TAAnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 251 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input D01 D00 TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input D11 D10 TAAnCCR1 register <1> <2> <3> <4> <5> <6> Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software. <1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of the default value of the TIAAm1 pin input). <3> An overflow occurs. Set the TAAnOVF0 and TAAnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TAAnCCR0 register. Read the TAAnOVF0 flag. If the TAAnOVF0 flag is 1, clear it to 0. Because the TAAnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TAAnCCR1 register. Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0 (the TAAnOVF0 flag is cleared in <4>, and the TAAnOVF1 flag remains 1). Because the TAAnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 252 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input D01 D00 TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input D11 D10 TAAnCCR1 register <1> <2> <3> <4> <5> <6> Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software. <1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of the default value of the TIAAm1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TAAnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TAAnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TAAnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0. Because the TAAnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 253 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register Dm0 Dm1 INTTAAnOV signal TAAnOVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> The following problem may occur when a long pulse width is measured in the free-running timer mode. <1> Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TAAnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. Remark m = 0, 1 n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 254 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register Dm0 Dm1 INTTAAnOV signal TAAnOVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TAAnCCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark m = 0, 1 n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 255 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) Overflow set signal (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal L L 0 write signal 0 write signal Register access signal Overflow flag (TAAnOVF bit) Read Write Overflow flag (TAAnOVF bit) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal Overflow set signal 0 write signal 0 write signal Register access signal Overflow flag (TAAnOVF bit) Overflow flag (TAAnOVF bit) Remark Read Write H n = 0 to 2 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 256 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.5.7 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TAAnCCRm register after a capture interrupt request signal (INTTAAnCCm) occurs. Select either the TIAAn0 or TIAAk1 pin as the capture trigger input pin. Specify "No edge detection" for the unused pins by using the TAAnIOC1 register. When an external clock is used as the count clock, measure the pulse width of the TIAAn1 pin because the external clock is fixed to the TIAAn0 pin. At this time, clear the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture trigger input (TIAAn0 pin): No edge detection). Figure 6-39. Configuration in Pulse Width Measurement Mode Clear Count clock selection 16-bit counter INTTAAnOV signal INTTAAnCC0 signal TAAnCE bit TIAAn0 pin (capture trigger input) Edge detector TIAAk1 pin (capture trigger input) Edge detector Remark INTTAAnCC1 signal TAAnCCR0 register (capture) TAAnCCR1 register (capture) n = 0 to 2 m = 0, 1 k = 2 (V850ES/JC3-H) k = 0 to 2 (V850ES/JE3-H) R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 257 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register 0000H D0 D1 D2 D3 INTTAAnCCm signal INTTAAnOV signal TAAnOVF bit Remark Cleared to 0 by CLR instruction n = 0 to 2 m = 0, 1 When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is later detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTAAnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIAAnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTAAnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TAAnOVF bit set (1) count + Captured value) x Count clock cycle Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 258 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-41. Register Setting in Pulse Width Measurement Mode (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCTL0 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1) TAAnEST TAAnEEE TAAnCTL1 0 0 0 TAAnMD2 TAAnMD1 TAAnMD0 0 0 1 1 0 1, 1, 0: Pulse width measurement mode (c) TAAn I/O control register 1 (TAAnIOC1) TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0 TAAnIOC1 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of TIAAn0 pin input Select valid edge of TIAAn1 pin input (d) TAAn option register 0 (TAAnOPT0) TAAnOVF TAAnCCS1 TAAnCCS0 TAAnOPT0 0 0 0 0 0 0 0 0/1 Overflow flag (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIAAnm pin is detected. Remarks 1. TAAn I/O control register 0 (TAAnIOC0), and TAAn I/O control register 2 (TAAnIOC2) are not used in the pulse width measurement mode. 2. m = 0, 1 n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 259 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in pulse width measurement mode Figure 6-42. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input 0000H TAAnCCR0 register D0 D1 D2 0000H INTTAAnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC1 register, TAAnOPT0 register Set TAAnCTL0 register (TAAnCE bit = 1) Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). <2> Count operation stop flow TAAnCE bit = 0 The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. STOP Remark n = 0 to 2 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 260 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) Overflow set signal (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal L L 0 write signal 0 write signal Register access signal Overflow flag (TAAnOVF bit) Read Write Overflow flag (TAAnOVF bit) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal Overflow set signal 0 write signal 0 write signal Register access signal Overflow flag (TAAnOVF bit) Overflow flag (TAAnOVF bit) Remark Read Write H n = 0 to 2 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 261 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.5.8 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer output operations The following table shows the operations and output levels of the TOAAn0 and TOAAn1 pins. Table 6-5. Timer Output Control in Each Mode Operation Mode TOAAn1 Pin TOAAn0 Pin Interval timer mode Square wave output External event count mode Square wave output External trigger pulse output mode External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Free-running timer mode Square wave output (only when compare function is used) Square wave output - Pulse width measurement mode Remark - n = 0 to 2 Table 6-6. Truth Table of TOAAn0 and TOAAn1 Pins Under Control of Timer Output Control Bits TAAnIOC0.TAAnOLm Bit TAAnIOC0.TAAnOEm Bit 0 TAAnCTL0.TAAnCE Bit Level of TOAAnm Pin 0 x Low-level output 1 0 Low-level output 1 Low level immediately before counting, high level after counting is started 1 0 1 x High-level output 0 High-level output 1 High level immediately before counting, low level after counting is started Remark n = 0 to 2 m = 0, 1 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 262 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.6 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer-Tuned Operation Function Timer AA and timer AB have a timer-tuned operation function. The timer-tuned operation function is used to tune the internal timers of the V850ES/JE3-H, so that the number of capture or compare registers of the slave timer (the number of timer outputs and the number of compare match interrupts of the slave timer) can be added to the master timer. The timers that can be tuned are listed in Table 6-7. Table 6-7. Tuned-Operation Mode of Timers Master Timer Slave Timer TAA1 TAA0 TAB1 TAA4 The tuned-operation function has the following modes. * PWM output mode * Free-running timer mode Figure 6-43 shows an example where individual operation and tuned operation of TAA0 (as the master timer) and TAA1 (as the slave timer) are performed in PWM output mode. Figure 6-43. Differences Between Individual Operation and Tuned Operation Using TAA0 and TAA1 Individual operation Tuned operation TAA1 (master) + TAA0 (slave) TAA1 16-bit timer/counter 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOAA10 (square waveform output) TOAA11 (PWM output) TAA0 16-bit capture/compare TOAA10 (square waveform output) TOAA11 (PWM output) 16-bit capture/compare TOAA01 (PWM output) 16-bit capture/compare TOAA01 (PWM output) 16-bit capture/compare 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOAA00 (squarewaveform output) TOAA01 (PWM output) Two PWM outputs are available when PWM is operated separately with each timer. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Three PWM outputs are available when PWM is operated in tuned-operation mode. Page 263 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Table 6-8 show the timer modes that can be used in the tuned-operation mode and Table 6-9 shows the differences of the timer output functions between individual operation and tuned operation (: Settable, x: Not settable). Table 6-8. Timer Modes Usable in Tuned-Operation Mode Master Timer Slave Timer Free-Running Timer Mode PWM Mode TAA1 TAA0 TAB1 TAA4 Table 6-9. Timer Output Functions Tuned Channel Ch0 Timer TAA1 (master) Ch2 Free-Running Timer Mode PWM Mode Individual Operation Tuned Operation Individual Operation Tuned Operation TOAA10 PPG Toggle TOAA11 PPG PWM TAA0 (slave) TOAA00 PGP Toggle PWM TOAA01 PPG PWM TAB1 TOAB10 PPG Toggle TOAB11 to TOAB13 PPG PWM TAA4 TOAA40 PPG Toggle PWM (slave) TOAA41 PPG PWM (master) Remark Pin The timing of transmitting data from the compare register of the buffer register is as follows. * PPG: CPU write timing * Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOAAn0 and TOABm0 R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 264 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.6.1 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Free-running timer mode (during timer-tuned operation) This section explains the free-running timer mode of the timer-tuned operation. For the combination of timer-tuned operations, see Table 6-7. In this section, an example of timer-tuned operation using TAA1 and TAA0 is shown. (i) Selecting capture/compare registers When the free-running timer mode of the timer-tuned operation is used with TAA1 and TAA0 connected to each other, the two capture/compare registers of TAA1 and two capture/compare registers of TAA0 can be used in combination. How the capture and compare registers are combined is not restricted and can be selected by using the TAAnCCSn bit of the master or slave timer. When the compare register is selected, the set value of the compare register can be rewritten during operation and the rewriting method is anytime write (n = 0, 1). (ii) Overflow If the counter overflows, an overflow interrupt (INTTAA1OV) of the master timer is generated and the overflow flag (TAA1OVF) is set to "1". The overflow interrupt (INTTAA0OV) and overflow flag (TAA0OVF) of the slave timer do not operate and are always at the low level. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 265 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Settings in free-running timer mode (compare function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] * TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) * TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 00 (setting of capture/compare select bit to "compare".) * TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any)) * TAA1CCR1 and TAA1CCR0 registers are set. [Initial settings of slave timer (TAA0)] * TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation) * TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode) * TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to "compare".) * TAA0CCR0 and TAA0CCR1 registers are set. Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. <3> Changing the setting of the register during operation * The compare register can be rewritten (anytime write). [End condition] * Set TAA1CTL0.TAA1CE of the master timer to 0. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 266 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-44. Example of Timing in Free-Running Mode (Compare Function) FFFFH D01 D01 D00 D00 TAA1 16-bit counter D11 D11 D10 D10 0000H TAA1CE TAA1CCR0 D10 TAA1CCR1 D11 TAA0CCR0 D00 TAA0CCR1 D01 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF TAA1OVF write clear (0) TOAA10 TOAA11 TOAA00 TOAA01 INTTAA0OV L TAA0OVF L R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 267 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Settings in free-running timer mode (capture function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] * TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) * TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to "capture".) * TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any)) * TAA1IOC1.TAA1IS3 to TAA1IOC1.TAA1IS0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)] * TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation) * TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode) * TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 11 (setting of capture/compare select bit to "capture".) * TAA0IOC1.TAA0IS3 to TAA0IOC1.TAA0IS0 (specification of valid edge of capture trigger) Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. [End condition] * Set TAA1CTL0.TAA1CE of the master timer to 0. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 268 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-45. Example of Timing in Free-Running Mode (Capture Function) FFFFH D011 D110 D001 D000 TAA1 16-bit counter D111 D110 D100 D101 0000H TAA1CE TIAA10 TIAA11 TIAA00 TIAA01 TAA1CCR0 TAA1CCR1 0000 0000 TAA0CCR0 D110 0000 TAA0CCR1 D101 D100 0000 D101 D110 D111 D000 D001 D010 D011 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF INTTAA0OV L TAA0OVF L R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 TAA1OVF write clear (0) Page 269 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) Settings in free-running timer mode (capture/compare used together) An example of using TAA0 as a capture register and TAA1 as a compare register is shown below. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] * TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode) * TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to "capture".) * TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any)) * TAA1.TAA0IS3 to TAA1.TAA1IS0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)] * TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation) * TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode) * TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to "compare".) * TAA0CCR0 and TAA0CCR1 registers are set. Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. [End condition] * Set TAA1CTL0.TAA1CE of the master timer to 0. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 270 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-46. Example of Timing in Free-Running Mode (Capture/Compare Used Together) FFFFH D100 D010 D010 TAA1 16-bit counter D000 D000 D111 D110 0000H TAA1CE TIAA10 TIAA11 0000 TAA1CCR0 TAA1CCR1 0000 D000 D111 D110 TAA0CCR0 0000 D000 TAA0CCR1 0000 D010 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF TAA1OVF write clear (0) TOAA00 TOAA01 INTTAA0OV L TAA0OVF L R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 271 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.7 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function. By using the simultaneous-start function, a timer operation in which the operation start timing and count up timing of the master timer and slave timer are synchronized can be performed. Only the PWM output mode can be used in the simultaneous-start function. The combinations of timers that can use the simultaneous-start function are listed in Table 6-10. Table 6-10. Timer Simultaneous-Start Function Master Timer Slave Timer TAA1 TAA0 TAB1 TAA4 Figure 6-48 shows an example where individual operation and simultaneous-start operation of TAA0 (as the master timer) and TAA1 (as the slave timer) are performed in PWM output mode. Figure 6-48. Differences Between Individual Operation and Simultaneous-Start Operation Using TAA1 and TAA0 Individual operation Simultaneous-start operation TAA1 (master) TAA1 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare 16-bit timer/counter TOAA10 (square waveform output) TOAA11 (PWM output) TAA0 16-bit capture/compare 16-bit capture/compare TAA0 (slave) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare Simultaneous-start signal 16-bit timer/counter TOAA00 (square waveform output) TOAA01 (PWM output) If PWM operates separately with each timer, the 16-bit counter starts and the PWM output starts at a different timing for each timer. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 TOAA10 (square waveform output) TOAA11 (PWM output) 16-bit capture/compare 16-bit capture/compare TOAA00 (square waveform output) TOAA01 (PWM output) With the simultaneous-start function, PWM output operates with the count start timing and the count clock of both timers being synchronized. Page 272 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.7.1 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) PWM output mode (simultaneous-start operation) In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and TAA0 is used as the slave timer. The master timer (TAA1) and slave timer (TAA0) start operating at the same time when the TAA1CTL0.TAA0CE bit of master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1). After the slave timer starts operating, however, the 16-bit counter of the slave timer (TAA0) is not cleared even if the 16-bit counter of the master timer (TAA1) is cleared to 0000H upon a match between the 16-bit counter value of the master timer (TAA1) and the TAA1CCR0 register value, because each timer operates individually. In the same manner, if the compare register value of the master timer (TAA1) is rewritten by batch writing, the compare register of the slave timer is not affected. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] * TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 100 (setting of PMW output mode) * TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any)) * TAA1CCR1, TAA1CCR0 (specification of valid edge of capture trigger) * TAA1IOC0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)] * TAA0CTL1.TAA0SYE = 1, TAA0SYM = 1 (simultaneous-start operation) * TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 100 (setting of PMW output mode) * TAA0CCR0, TAA1CCR1 (specification of valid edge of capture trigger) * TAA0IOC0 (specification of valid edge of capture trigger) Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. <3> Changing the setting of the register during operation * The compare register can be rewritten (anytime write). [End condition] * Set TAA1CTL0.TAA0CE of the master timer to 0. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 273 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-49. Timing Example of Simultaneous-Start Function (TAA1: Master, TAA0: Slave) FFFFH D11 TAA1 16-bit counter D11 D10 D10 0000H FFFFH TAA0 16-bit counter D01 D00 D01 D00 D01 D00 0000H TAA1CE bit TAA1CCR0 register D10 TAA1CCR1 register D11 INTTAA1CC0 interrupt INTTAA1CC1 interrupt TOAA10 pin output TOAA11 pin output TAA0CCR0 register D00 TAA0CCR1 register D01 INTTAA0CC0 interrupt INTTAA0CC1 interrupt TOAA00 pin output TOAA01 pin output R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 274 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.8 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Cascade Connection This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer. For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as capture registers (TAA0CCSn = 1). Combinations of TAA channels that can be connected in cascade are shown in the following table. Table 6-11. Cascade Connection of TAA Lower Timer (Master Timer) Higher Timer (Slave Timer) TAA1 TAA0 In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave timer) to use them as a 32-bit capture timer by cascade connection. Figure 6-50. Cascade Connection Example [Lower timer TAA1] Capture signal 1 (TIAA11) [Higher timer TAA0] Lower capture interrupt 1 (INTTAA1CC1) Edge detection Higher capture register 1 (TAA0CCR1) Lower capture register 1 (TAA1CCR1) Count clock selection Lower timer counter Operation enable bit (TAA1CE) FFFFH detection signal Lower capture register 0 (TAA1CCR0) Capture signal 0 (TIAA10) Higher timer counter Higher capture register 0 (TAA0CCR0) Edge detection Lower capture interrupt 0 (INTTAA1CC0) R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Lower overflow interrupt (INTTAA1OV) Higher overflow interrupt (INTTAA0OV) Page 275 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) The operation of each pin and signal when TAA1 and TAA0 are connected in cascade is shown below. Table 6-12. Status in Cascade Connection Name TIAA10 pin input Higher/Lower Lower Function Capture input 0 Operation The value of the lower timer counter is stored in the TAA1CCR0 register and the value of the higher timer counter is stored in the TAA0CCR0 register when the valid edge of this input is detected. TIAA11 pin input Note Lower Capture input 1 The value of the lower timer counter is stored in the TAA1CCR1 register and the value of the higher timer counter is stored in the TAA0CCR1 register when the valid edge of this input is detected. INTTAA1CCR0 interrupt signal Lower Capture interrupt 0 This interrupt is generated when the valid edge of the TIAA10 pin is detected. INTTAA1CCR1 interrupt signal Lower Capture interrupt 1 This interrupt is generated when the valid edge of the TIAA11 pin is detected. INTTAA1OV interrupt signal Lower Overflow interrupt This interrupt is generated when an overflow of the lower timer counter is detected. TIAA00 pin input Higher Capture input 0 Does not operate. Higher Capture input 1 Does not operate. INTTAA0CCR0 interrupt signal Higher Capture interrupt 0 Does not operate. INTTAA0CCR1 interrupt signal Higher Capture interrupt 1 Does not operate. INTTAA0OV interrupt signal Higher Overflow interrupt This interrupt is generated when an overflow of the TIAA01 pin input Note higher timer counter is detected. Note V850ES/JE3-H only R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 276 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (1/2) FFFFFFFFH D1a1b D0e0f D1c1d D0a0b 32-bit counter D0g0h D1e1f D0c0d 00000000H Operation enable bit (TAA1CE) TIAA10 input Lower capture register 0 (TAA1CCR0) 0000 D 0b D 0d D 0f D 0h 0000H Higher capture register 0 (TAA0CCR0) 0000 D 0a D 0c D 0e D 0g 0000H Lower capture interrupt 0 (INTTAA1CC0) Pulse interval Pulse interval Pulse interval D0c0d - D0a0b D0e0f - D0c0d D0g0h - D0c0d TIAA11 input Lower capture register 1 (TAA1CCR1) 0000 D 1b D1d D 1f 0000H Higher capture register 1 (TAA0CCR1) 0000 D 1a D1c D 1e 0000H Lower capture interrupt 1 (INTTAA1CC1) Pulse interval Pulse interval D1c1d - D1a1b D1e1f - D1c1d Overflow interrupt (INTTAA0OV) Overflow flag (TAA0OVF) Cleared to 0 by CLR instruction <1> R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 <2> <3> <4> Cleared to 0 by CLR instruction <5> Page 277 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (2/2) <2> Capture 1 read flow <1> Count operation start flow START INTTAA0CCR1 generated? Register initial setting [Lower timer: TAA1] TAA1CTL0 register (TAA1CKS0 to TAA1CKS2 bits), TAA1CTL1 register, TAA1IOC1 register, TAA1IOC2 register, TAA1OPT0 register [Higher timer: TAA0] TAA0CTL1 register, TAA0IOC1 register, TAA0OPT0 register, TAA0OPT1 register TAA1CE bit = 1 Perform initial setting of these registers before TAA1CE bit = 1. NO YES Executing instruction that clears TAA0CCIC1.TAA0CCIF1 bit (CLR TAA0CCIF1) Reading TAA1CCR1 and TAA0CCR1 registers (reading capture register 0) TAA1CKS0 to TAA1CKS2 bits can be set as soon as counting operation starts (TAA1CE bit = 1). TAA0CCIF1 = 0? NO YES Calculating pulse interval (Captured value - Previously captured value) <2> Capture 0 read flow <4> Overflow flag clear flow INTTAA0CCR0 generated? NO YES Reading TAA0OPT0 register (checking overflow flag) Executing instruction that clears TAA0CCIC0.TAA0CCIF0 bit (CLR TAA0CCIF0) Reading TAA1CCR0 and TAA0CCR0 registers (reading capture register 0) TAA0OVF bit = 1 NO YES TAA1CCIF0 = 0? NO Executing instruction that clears TAA0OVF bit (CLR TAA0OVF) YES Calculating pulse interval (Captured value - Previously captured value) <5> Count operation stop flow TAA1CE bit = 0 Counter is initialized by stopping counting operation (TAA1CE bit = 0). STOP R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 278 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade FFFFFFFFH D1a1b D0e0f D1c1d D0a0b 32-bit counter D0g0h D1e1f D0c0d D0i0j D1g1h 00000000H Operation enable bit (TAA1CE) TIAA10 input Lower capture register 0 (TAA1CCR0) 0000 D 0b D 0d D 0f D 0h D 0j Higher capture register 0 (TAA0CCR0) 0000 D 0a D 0c D 0e D 0g D 0i Lower capture interrupt 0 (INTTAA1CC0) Pulse interval Pulse interval Pulse interval Pulse interval D0c0d - D0a0b D0e0f - D0c0d D0g0h - D0c0d D0i0j - D0g0h TIAA11 input Lower capture register 1 (TAA1CCR1) 0000 D 1b D1d D 1f D 1h Higher capture register 1 (TAA0CCR1) 0000 D 1a D1c D 1e D 1g Capture interrupt 1 (INTTAA1CC1) Pulse interval Pulse interval Pulse interval D1c1d - D1a1b D1e1f - D1c1d D1g1h - D1c1d Overflow interrupt (INTTAA0OV) Overflow flag (TAA0OVF) Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction The counting operation is started when the TAA1CTL.TAA1CE bit is set to 1 and the count clock is supplied. When the valid edge input to the TIAA10 pin is detected, the count value is stored in the capture register 0 (TAA1CCR0 and TAA0CCR0), and capture interrupt 0 signal (INTTAA1CC0) is issued. The timer counter continues the counting operation in synchronization with the count clock. When it counts up to FFFFFFFFH, the overflow interrupt (INTTAA0OV) is generated at the next clock and the overflow flag (TAA0OVF) is set to 1. The timer counter is cleared to 00000000H and continues counting up. The overflow flag (TAA0OVF) is cleared by an instruction issued from the CPU that writes "0" to it. Because the free-running timer mode is set, the timer counter cannot be cleared by detection of the valid edge input to the TIAA10 pin. Using TOAA10 output is prohibited because it alternately functions as the TIAA10 input. Capture register 1 (TAA1CCR1 and TAA0CCR1) also operates in the same manner. If the lower timer counter (TAA1) overflows, an overflow interrupt (TAA1OVF) is generated. However, it is recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter. R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 279 of 1438 V850ES/JC3-H, V850ES/JE3-H 6.9 CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Selector Function In the V850ES/JC3-H and V850ES/JE3-H, the alternate-function pins of ports or peripheral I/O (TAA1, TAB0, UARTC0, or UARTC1) signals can be selected as the capture trigger input of TAA1 and TAB0. If the signal input from the UARTCn pin is selected by the selector function when RXDCn is used, baud rate errors of the LIN reception transfer rate of UARTCn can be calculated (n = 0, 1). (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for CAN0, TAA1, and TAB0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H SELCNT0 R/W Address: FFFFF308H 7 6 5 4 3 2 1 0 0 0 0 0 ISEL3 0 0 ISEL0Note ISEL3 Selection of TIAA10 capture trigger input signal 0 TIAA10 (alternately functions as P34) pin 1 RXDC0 (alternately functions as P31) pin ISEL0Note Selection of TIAA00 capture trigger input signal 0 TIA00 (alternately functions as P32) pin 1 CAN0 TSOUT signal Note PD70F3819 and 70F3825 only Cautions 1. To set the ISEL4, ISEL3, and ISEL0 bits to 1, set the corresponding function pin to the capture input mode. 2. Set the ISEL3, and ISEL0 bits when the operation of TAA1, UARTC0, and CAN0 are stopped. 3. Be sure to set bits 7 to 5, 2, and 1 to "0". R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Page 280 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.10 Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TAAnCCR0 and TAAnCCR1 registers if the capture trigger is input immediately after the TAAnCE bit is set to 1. (a) Free-running timer mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TAAnCCR0 register 0000H FFFFH 0001H TAAnCE bit TIAAn0 pin input Capture trigger input Capture trigger input (b) Pulse width measurement mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TAAnCCR0 register 0000H FFFFH 0002H TAAnCE bit TIAAn0 pin input Capture trigger input R01UH0288EJ0100 Rev.2.00 Sep 20, 2011 Capture trigger input Page 281 of 1438 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer AB (TAB) is a 16-bit timer/event counter. The following table shows the function of TAB can be used. Timer mode V850ES/JC3-H (40 pin) V850ES/JC3-H (48 pin) V850ES/JE3-H Interval timer mode External event count mode - - External trigger pulse output mode - - One-shot pulse output mode - - PWM output mode - - Free-running timer mode - - Pulse width measurement mode - - Triangular wave PWM mode - - 7.1 Overview An outline of TAB1 is shown below. * 16-bit timer/counter (TAB1) * Clock selection: 8 ways * Capture/trigger input pins (TIAB10 to TIAB13): 4 * External event count input pins (EVTAB1): 1 * External trigger input pins (TRGAB1): 1 * Timer counters: 1 * Capture/compare registers: 2 * Capture/compare match interrupt request signals: 4 * Timer output pins (TOAB10 to TOAB13): 4 7.2 Functions TAB1 has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement * Triangular wave PWM output * Timer-tuned operation function * Simultaneous-start function R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 282 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Configuration TAB1 includes the following hardware. Table 7-1. Configuration of TAB1 Item Configuration 16-bit counter Registers TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) TAB1 counter read buffer register (TAB1CNT) CCR0 to CCR3 buffer registers TAB1 control registers 0, 1 (TAB1CTL0, TAB1CTL1) TAB1 I/O control registers 0 to 2 (TAB1IOC0 to TAB1IOC2, TAB1IOC4) TAB1 option register 0 (TAB1OPT0) Timer inputs Note Timer outputs Note 4 (TIAB10 to TIAB13 pins) Note 4 (TOAB10 to TOAB13 pins) When using the functions of the TIAB10 to TIAB13 and TOAB10 to TOAB13 pins, see Table 4-17 Using Port Pin as Alternate-Function Pin. Cautions1. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TAB1CTL1.TAB1EEE bit to 0). 2. To use the external event count mode, specify that the valid edge of the TIAA10 pin capture trigger input is not detected (by setting the TAB1CTL1.TABEEE0 bits to 1). Figure 7-1. Block Diagram of TAB1 Internal bus TIAB10 TIAB11 TIAB12 TIAB13 INTTAB1OV 16-bit counter Clear Output controller Counter control Selector Edge detector TRGAB EVTAB TAB1CNT Edge detector fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 CCR0 buffer register CCR1 buffer register CCR2 buffer register TAB1CCR0 CCR3 buffer register TAB1CCR1 TOAB10 TOAB11 TOAB12 TOAB13 INTTAB1CC0 INTTAB1CC1 INTTAB1CC2 INTTAB1CC3 TAB1CCR2 TAB1CCR3 Internal bus Remark fXX: Main clock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 283 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAB1CNT register. When the TAB1CTL0.TAB1CE bit = 0, the value of the 16-bit counter is FFFFH. If the TAB1CNT register is read at this time, 0000H is read. Reset sets the TAB1CE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAB1CCR0 register is used as a compare register, the value written to the TAB1CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAB1CC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TAB1CCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAB1CCR1 register is used as a compare register, the value written to the TAB1CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAB1CC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TAB1CCR1 register is cleared to 0000H. (4) CCR2 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAB1CCR2 register is used as a compare register, the value written to the TAB1CCR2 register is transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTAB1CC2) is generated. The CCR2 buffer register cannot be read or written directly. The CCR2 buffer register is cleared to 0000H after reset, as the TAB1CCR2 register is cleared to 0000H. (5) CCR3 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAB1CCR3 register is used as a compare register, the value written to the TAB1CCR3 register is transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTAB1CC3) is generated. The CCR3 buffer register cannot be read or written directly. The CCR3 buffer register is cleared to 0000H after reset, as the TAB1CCR3 register is cleared to 0000H. (6) Edge detector This circuit detects the valid edges input to the TIAB10 to TIAB13 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TAB1IOC1 and TAB1IOC2 registers. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 284 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) Output controller This circuit controls the output of the TOAB10 to TOAB13 pins. The output controller is controlled by the TAB1IOC0 register. (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 285 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.4 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Registers The registers that control TAB1 are as follows. * TAB1 control register 0 (TAB1CTL0) * TAB1 control register 1 (TAB1CTL1) * TAB1 I/O control register 0 (TAB1IOC0) * TAB1 I/O control register 1 (TAB1IOC1) * TAB1 I/O control register 2 (TAB1IOC2) * TAB1 I/O control register 4 (TAB1IOC4) * TAB1 option register 0 (TAB1OPT0) * TAB1 capture/compare register 0 (TAB1CCR0) * TAB1 capture/compare register 1 (TAB1CCR1) * TAB1 capture/compare register 2 (TAB1CCR2) * TAB1 capture/compare register 3 (TAB1CCR3) * TAB1 counter read buffer register (TAB1CNT) Remark When using the functions of the TIAB10 to TIAB13 and TOAB10 to TOAB13 pins, see Table 4-17 Using Port Pin as Alternate-Function Pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 286 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) TAB1 control register 0 (TAB1CTL0) The TAB1CTL0 register is an 8-bit register that controls the operation of TAB1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TAB1CTL0 register. After reset: 00H TAB1CTL0 R/W Address: TAB1CTL0 FFFFF560H 7 6 5 4 3 TAB1CE 0 0 0 0 TAB1CE 2 1 0 TAB1CKS2 TAB1CKS1 TAB1CKS0 TAB1 operation control 0 TAB1 operation disabled (TAB1 reset asynchronouslyNote). 1 TAB1 operation enabled. TAB1 operation started. Internal count clock selection TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 fXX 0 0 1 fXX/2 0 1 0 fXX/4 0 1 1 fXX/8 1 0 0 fXX/16 1 0 1 fXX/32 1 1 0 fXX/64 1 1 1 fXX/128 Note TAB1OPT0.TAB1OVF bit, 16-bit counter, timer output (TOAB10 to TOAB13 pins) Cautions 1. Set the TAB1CKS2 to TAB1CKS0 bits when the TAB1CE bit = 0. When the value of the TAB1CE bit is changed from 0 to 1, the TAB1CKS2 to TAB1CKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to "0". Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 fXX: Main clock frequency Page 287 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) TAB1 control register 1 (TAB1CTL1) The TAB1CTL1 register is an 8-bit register that controls the operation of TAB1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 TAB1CTL1 0 R/W 6 Address: TAB1CTL1 FFFFF561H 5 TAB1EST TAB1EEE 4 3 0 0 2 TAB1EST Software trigger control 0 - 1 1 0 TAB1MD2 TAB1MD1 TAB1MD0 Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TAB1EST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TAB1EST bit as the trigger. Count clock selection TAB1EEE 0 Disable operation with external event count input. (Perform counting with the count clock selected by the TAB1CTL0.TAB1CK0 to TAB1CTL0.TAB1CK2 bits.) 1 Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.) The TAB1EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TAB1MD2 TAB1MD1 TAB1MD0 Timer mode selection 0 0 0 Interval timer mode 0 0 1 External event count mode 0 1 0 External trigger pulse output mode 0 1 1 One-shot pulse output mode 1 0 0 PWM output mode 1 0 1 Free-running timer mode 1 1 0 Pulse width measurement mode 1 1 1 Triangular wave PWM mode Cautions 1. The TAB1EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. Be sure to set bits 3, 4, and 7 to "0". 3. External event count input is selected in the external event count mode regardless of the value of the TAB1EEE bit. 4. Set the TAB1EEE and TAB1MD2 to TAB1MD0 bits when the TAB1CTL0.TAB1CE bit = 0. (The same value can be written when the TAB1CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TAB1CE bit = 1. If rewriting was mistakenly performed, clear the TAB1CE bit to 0 and then set the bits again. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 288 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (3) TAB1 I/O control register 0 (TAB1IOC0) The TAB1IOC0 register is an 8-bit register that controls the timer output (TOAB10 to TOAB13 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 6 7 TAB1IOC0 Address: TAB1IOC0 FFFFF562H 5 4 3 2 1 0 TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TOAB1m pin output level setting (m = 0 to 3)Note TAB1OLm 0 TOAB1m pin high level start 1 TOAB1m pin low level start TOAB1m pin output setting (m = 0 to 3) TAB1OEm 0 Timer output disabled * When TAB1OLm bit = 0: Low level is output from the TOAB1m pin * When TAB1OLm bit = 1: High level is output from the TOAB1m pin 1 Timer output enabled (a square wave is output from the TOAB1m pin). Note The output level of the timer output pin (TOAB1m) specified by the TAB1OLm bit is shown below. * When TAB1OLm bit = 0 * When TAB1OLm bit = 1 16-bit counter 16-bit counter TAB1CE bit TAB1CE bit TOAB1m output pin TOAB1m output pin Cautions 1. Rewrite the TAB1OLm and TAB1OEm bits when the TAB1CTL0.TAB1CE bit = 0. (The same value can be written when the TAB1CE bit = 1.) If rewriting was mistakenly performed, clear the TAB1CE bit to 0 and then set the bits again. 2. Even if the TAB1OLm bit is manipulated when the TAB1CE and TAB1OEm bits are 0, the TOAB1m pin output level varies. Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 m = 0 to 3 Page 289 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (4) TAB1 I/O control register 1 (TAB1IOC1) The TAB1IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAB10 to TIAB13 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 R/W Address: 6 5 TAB1IOC1 FFFFF563H 4 3 2 1 0 TAB1IOC1 TAB1IS7 TAB1IS6 TAB1IS5 TAB1IS4 TAB1IS3 TAB1IS2 TAB1IS1 TAB1IS0 TAB1IS7 TAB1IS6 Capture trigger input signal (TIAB13 pin) valid edge setting 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAB1IS5 TAB1IS4 Capture trigger input signal (TIAB12 pin) valid edge detection 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAB1IS3 TAB1IS2 Capture trigger input signal (TIAB11 pin) valid edge setting 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAB1IS1 TAB1IS0 Capture trigger input signal (TIAB10 pin) valid edge setting 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TAB1IS7 to TAB1CTL0.TAB1CE bit = 0. TAB1IS0 bits when the (The same value can be written when the TAB1CE bit = 1.) If rewriting was mistakenly performed, clear the TAB1CE bit to 0 and then set the bits again. 2. The TAB1IS7 to TAB1IS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 290 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (5) TAB1 I/O control register 2 (TAB1IOC2) The TAB1IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (EVTAB1 pin) and external trigger input signal (TRGAB1 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TAB1IOC2 R/W Address: TAB1IOC2 FFFFF564H 7 6 5 4 0 0 0 0 TAB1EES1 TAB1EES0 3 2 1 0 TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 External event count input signal (EVTAB1 pin) valid edge setting 0 0 No edge detection (external event count invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TAB1ETS1 TAB1ETS0 External trigger input signal (TRGAB1 pin) valid edge setting 0 0 No edge detection (external trigger invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TAB1EES1, TAB1EES0, TAB1ETS1, and TAB1ETS0 bits when the TAB1CTL0.TAB1CE bit = 0. (The same value can be written when the TAB1CE bit = 1.) If rewriting was mistakenly performed, clear the TAB1CE bit to 0 and then set the bits again. 2. The TAB1EES1 and TAB1EES0 bits are valid only when the TAB1CTL1.TAB1EEE bit = 1 or when the external event count mode (TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits = 001) has been set. 3. The TAB1ETS1 and TAB1ETS0 bits are valid only when the external trigger pulse output mode (TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits = 010) or the one-shot pulse output mode (TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 = 011) is set. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 291 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (6) TAB1 I/O control register 4 (TAB1IOC4) The TAB1IOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TAB1CTL0.TAB1CE = 0). Cautions 1. Accessing the TAB1IOC4 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock 2. The TAB1IOC4 register can be set only in the interval timer mode and free-running timer mode. Be sure to set the TAB1IOC4 register to 00H in all other modes (for details of the mode setting, see 7.4 (2) TAB1 control register 1 (TAB1CTL1)). Even in free-running timer mode, if the TAB1CCR0 to TAB1CCR3 registers are set to the capture function, the setting of the TAB1IOC4 register becomes invalid. After reset: 00H 7 TAB1IOC4 R/W 6 Address: TAB1IOC4 FFFFF570H 5 4 3 2 1 0 TAB1OS3 TAB1OR3 TAB1OS2 TAB1OR2 TAB1OS1 TAB1OR1 TAB1OS0 TAB1OR0 TAB1OSm TAB1ORm Toggle control of TOAB1m pin (m = 0 to 3) 0 0 No request. Normal toggle operation. 0 1 Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCRm register. 1 0 Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCRm register. 1 1 Keep request Keep the current output level. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 292 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) TAB1 option register 0 (TAB1OPT0) The TAB1OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: 6 7 5 AB1OPT0 FFFFF565H 4 TAB1OPT0 TAB1CCS3 TAB1CCS2 TAB1CCS1 TAB1CCS0 TAB1CCSm 3 0 2 1 Note TAB1CMS 0 TAB1CUF TAB1OVF TAB1CCRm register capture/compare selection 0 Compare register selected 1 Capture register selected The TAB1CCSm bit setting is valid only in the free-running timer mode. TAB1OVF TAB1 overflow detection Set (1) Overflow occurred Reset (0) TAB1OVF bit 0 written or TAB1CTL0.TAB1CE bit = 0 * The TAB1OVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTAB1OV) is generated at the same time that the TAB1OVF bit is set to 1. The INTTAB1OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TAB1OVF bit is not cleared even when the TAB1OVF bit or the TAB1OPT0 register are read when the TAB1OVF bit = 1. * The TAB1OVF bit can be both read and written, but the TAB1OVF bit cannot be set to 1 by software. Writing 1 has no effect on the operation of TAB1. Note The TAB1CMS bit is used for the motor control function. For details, see CHAPTER 10 MOTOR CONTROL FUNCTION. Cautions 1. Rewrite the TAB1CCS3 to TAB1CCS0 bits when the TAB1CTL0.TAB1CE bit = 0. (The same value can be written when the TAB1CE bit = 1.) If rewriting was mistakenly performed, clear the TAB1CE bit to 0 and then set the bits again. 2. Be sure to set bit 3 to "0". When the motor control function is not used, be sure to also set bit 2 to "0". Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 m = 0 to 3 Page 293 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (8) TAB1 capture/compare register 0 (TAB1CCR0) The TAB1CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS0 bit. In the pulse width measurement mode, the TAB1CCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAB1CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAB1CCR0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 TAB1CCR0 FFFFF566H 9 8 7 6 5 4 3 2 1 0 TAB1CCR0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 294 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR0 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAB1CC0) is generated. If TOAB10 pin output is enabled at this time, the output of the TOAB10 pin is inverted. When the TAB1CCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, or triangular wave PWM mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TAB1CCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAB1CCR0 register if the valid edge of the capture trigger input pin (TIAB10 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAB1CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAB10 pin) is detected. Even if the capture operation and reading the TAB1CCR0 register conflict, the correct value of the TAB1CCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register Triangular wave PWM mode Compare register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Batch write Page 295 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (9) TAB1 capture/compare register 1 (TAB1CCR1) The TAB1CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS1 bit. In the pulse width measurement mode, the TAB1CCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAB1CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAB1CCR1 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 TAB1CCR1 FFFFF568H 9 8 7 6 5 4 3 2 1 0 TAB1CCR1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 296 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR1 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAB1CC1) is generated. If TOAB11 pin output is enabled at this time, the output of the TOAB11 pin is inverted. (b) Function as capture register When the TAB1CCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAB1CCR1 register if the valid edge of the capture trigger input pin (TIAB11 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAB1CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAB11 pin) is detected. Even if the capture operation and reading the TAB1CCR1 register conflict, the correct value of the TAB1CCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register Triangular wave PWM mode Compare register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Batch write Page 297 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (10) TAB1 capture/compare register 2 (TAB1CCR2) The TAB1CCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS2 bit. In the pulse width measurement mode, the TAB1CCR2 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAB1CCR2 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAB1CCR2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 TAB1CCR2 FFFFF56AH 9 8 7 6 5 4 3 2 1 0 TAB1CCR2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 298 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR2 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR2 register is transferred to the CCR2 buffer register. When the value of the 16bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTAB1CC2) is generated. If TOAB12 pin output is enabled at this time, the output of the TOAB12 pin is inverted. (b) Function as capture register When the TAB1CCR2 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAB1CCR2 register if the valid edge of the capture trigger input pin (TIAB12 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAB1CCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAB12 pin) is detected. Even if the capture operation and reading the TAB1CCR2 register conflict, the correct value of the TAB1CCR2 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register Triangular wave PWM mode Compare register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Batch write Page 299 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (11) TAB1 capture/compare register 3 (TAB1CCR3) The TAB1CCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS3 bit. In the pulse width measurement mode, the TAB1CCR3 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAB1CCR3 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAB1CCR3 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 TAB1CCR3 FFFFF56CH 9 8 7 6 5 4 3 2 1 0 TAB1CCR3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 300 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR3 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR3 register is transferred to the CCR3 buffer register. When the value of the 16bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTAB1CC3) is generated. If TOAB13 pin output is enabled at this time, the output of the TOAB13 pin is inverted. (b) Function as capture register When the TAB1CCR3 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TAB1CCR3 register if the valid edge of the capture trigger input pin (TIAB13 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAB1CCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIAB13 pin) is detected. Even if the capture operation and reading the TAB1CCR3 register conflict, the correct value of the TAB1CCR3 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register Triangular wave PWM mode Compare register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - Batch write Page 301 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (12) TAB1 counter read buffer register (TAB1CNT) The TAB1CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAB1CTL0.TAB1CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only in 16-bit units. The value of the TAB1CNT register is cleared to 0000H when the TAB1CE bit = 0. If the TAB1CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TAB1CNT register is cleared to 0000H after reset, as the TAB1CE bit is cleared to 0. Caution Accessing the TAB1CNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R 13 Address: 12 11 10 TAB1CNT FFFFF56EH 9 8 7 6 5 4 3 2 1 0 TAB1CNT R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 302 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Operation TAB1 can perform the following operations. Operation Interval timer mode External event count mode Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Triangular wave PWM mode TAB1CTL1.TAB1EST Bit TIAB10 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input) Register Setting Write Invalid Invalid Compare only Anytime write Invalid Invalid Compare only Anytime write Valid Valid Compare only Batch write Valid Valid Compare only Anytime write Invalid Invalid Compare only Batch write Invalid Invalid Switching enabled Anytime write Invalid Invalid Capture only Not applicable Invalid Invalid Compare only Batch write Notes 1. To use the external event count mode, specify that the valid edge of the TIAB10 pin capture trigger input is not detected (by clearing the TAB1IOC1.TAB1IS1 and TAB1IOC1.TAB1IS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TAB1CTL1.TAB1EEE bit to 0). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 303 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Interval timer mode (TAB1MD2 to TAB1MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTAB1CC0) is generated at the specified interval if the TAB1CTL0.TAB1CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAB10 pin. Usually, the TAB1CCR1 to TAB1CCR3 registers are not used in the interval timer mode. Figure 7-2. Configuration of Interval Timer Clear Count clock selection Output controller 16-bit counter Match signal TAB1CE bit TOAB10 pin INTTAB1CC0 signal CCR0 buffer register TAB1CCR0 register Figure 7-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 0000H TAB1CE bit TAB1CCR0 register D0 TOAB10 pin output INTTAB1CC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 304 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOAB10 pin is inverted. Additionally, the set value of the TAB1CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOAB10 pin is inverted, and a compare match interrupt request signal (INTTAB1CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TAB1CCR0 register + 1) x Count clock cycle Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0 Note 0/1 TAB1MD2 TAB1MD1 TAB1MD0 0 0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by bits TAB1CKS0 to TAB1CKS2 1: Count with external event count input signal Note This bit can be set to 1 only when the interrupt request signals (INTTAB1CC0 and INTTAB1CCk) are masked by the interrupt mask flags (TAB1CCMK0 to TAB1CCMKk) and the timer output (TOAB1k) is performed at the same time. However, the TAB1CCR0 and TAB1CCRk registers must be set to the same value (see 7.5.1 (2) (d) Operation of TAB1CCR1 to TAB1CCR3 registers) (k = 1 to 3). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 305 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output Setting of output level with operation of TOABn0 pin disabled 0: Low level 1: High level 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Setting of output level with operation of TOABn1 pin disabled 0: Low level 1: High level 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Setting of output level with operation of TOABn2 pin disabled 0: Low level 1: High level 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output Setting of output level with operation of TOABn3 pin disabled 0: Low level 1: High level (d) TAB1 counter read buffer register (TAB1CNT) By reading the TAB1CNT register, the count value of the 16-bit counter can be read. (e) TAB1 capture/compare register 0 (TAB1CCR0) If the TAB1CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TAB1 capture/compare registers 1 to 3 (TAB1CCR1 to TAB1CCR3) Usually, the TAB1CCR1 to TAB1CCR3 registers are not used in the interval timer mode. However, the set value of the TAB1CCR1 to TAB1CCR3 registers is transferred to the CCR1 to CCR3 buffer registers. The compare match interrupt request signals (INTTAB1CCR1 to INTTAB1CCR3) are generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers. Therefore, mask the interrupt requests by using the corresponding interrupt mask flags (TAB1CCMK1 to TAB1CCMK3). Remark TAB1 I/O control register 1 (TAB1IOC1), TAB1 I/O control register 2 (TAB1IOC2), and TAB1 option register 0 (TAB1OPT0) are not used in the interval timer mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 306 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TAB1CE bit TAB1CCR0 register D0 TOAB10 pin output INTTAB1CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits) TAB1CTL1 register, TAB1IOC0 register, TAB1CCR0 register TAB1CE bit = 1 The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). <2> Count operation stop flow TAB1CE bit = 0 The counter is initialized and counting is stopped by clearing the TAB1CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 307 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Interval timer mode operation timing (a) Operation if TAB1CCR0 register is set to 0000H If the TAB1CCR0 register is set to 0000H, the INTTAB1CC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAB10 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TAB1CE bit TAB1CCR0 register 0000H TOAB10 pin output INTTAB1CC0 signal Interval time Count clock cycle Interval time Count clock cycle (b) Operation if TAB1CCR0 register is set to FFFFH If the TAB1CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTAB1CC0 signal is generated and the output of the TOAB10 pin is inverted. At this time, an overflow interrupt request signal (INTTAB1OV) is not generated, nor is the overflow flag (TAB1OPT0.TAB1OVF bit) set to 1. FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register FFFFH TOAB10 pin output INTTAB1CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 308 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Notes on rewriting TAB1CCR0 register To change the value of the TAB1CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAB1CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register FFFFH TOAB10 pin output INTTAB1CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle Remark Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle If the value of the TAB1CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAB1CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTAB1CC0 signal is generated and the output of the TOAB10 pin is inverted. Therefore, the INTTAB1CC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 309 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Operation of TAB1CCR1 to TAB1CCR3 registers Figure 7-6. Configuration of TAB1CCR1 to TAB1CCR3 Registers TAB1CCR1 register CCR1 buffer register Output controller Match signal TOAB11 pin INTTAB1CC1 signal TAB1CCR2 register Output controller CCR2 buffer register Match signal TOAB12 pin INTTAB1CC2 signal TAB1CCR3 register CCR3 buffer register Output controller Match signal TOAB13 pin INTTAB1CC3 signal Clear Count clock selection 16-bit counter Match signal TAB1CE bit Output controller TOAB10 pin INTTAB1CC0 signal CCR0 buffer register TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 310 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is less than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is generated once per cycle. At the same time, the output of the TOAB1k pin is inverted. The TOAB1k pin outputs a square wave with the same cycle as that output by the TOAB10 pin. Remark k = 1 to 3, Figure 7-7. Timing Chart When D01 Dk1 FFFFH 16-bit counter D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 0000H TAB1CE bit TAB1CCR0 register D01 TOAB10 pin output INTTAB1CC0 signal TAB1CCR1 register D11 TOAB11 pin output INTTAB1CC1 signal TAB1CCR2 register D21 TOAB12 pin output INTTAB1CC2 signal TAB1CCR3 register D31 TOAB13 pin output INTTAB1CC3 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 311 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is greater than the set value of the TAB1CCR0 register, the count value of the 16-bit counter does not match the value of the TAB1CCRk register. Consequently, the INTTAB1CCk signal is not generated, nor is the output of the TOAB1k pin changed. Remark k = 1 to 3, Figure 7-8. Timing Chart When D01 < Dk1 FFFFH D01 D01 D01 D01 16-bit counter 0000H TAB1CE bit D01 TAB1CCR0 register TOAB10 pin output INTTAB1CC0 signal TAB1CCR1 register D11 TOAB11 pin output INTTAB1CC1 signal L D21 TAB1CCR2 register TOAB12 pin output INTTAB1CC2 signal L D31 TAB1CCR3 register TOAB13 pin output INTTAB1CC3 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 L Page 312 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.2 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) External event count mode (TAB1MD2 to TAB1MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TAB1CTL0.TAB1CE bit is set to 1, and an interrupt request signal (INTTAB1CC0) is generated each time the specified number of edges have been counted. The TOAB10 pin cannot be used. Usually, the TAB1CCR1 to TAB1CCR3 registers are not used in the external event count mode. Figure 7-9. Configuration in External Event Count Mode Clear External event count input (EVTAB1 pin input) Edge detector 16-bit counter Match signal TAB1CE bit INTTAB1CC0 signal CCR0 buffer register TAB1CCR0 register Figure 7-10. Basic Timing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H 16-bit counter TAB1CE bit External event count input (EVTAB1 pin input) TAB1CCR0 register CCR0 register D0 D0 0000 0001 D0 INTTAB1CC0 signal INTTAB1CC0 signal External event count interval (D0 + 1) Remark D0 - 1 External event count interval (D0 + 1) External event count interval (D0 + 1) This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 313 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of the external event count input is detected. Additionally, the set value of the TAB1CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTAB1CC0) is generated. The INTTAB1CC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TAB1CCR0 register + 1) times. Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0 0 0 0: Stop counting 1: Enable counting (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0 0 TAB1MD2 TAB1MD1 TAB1MD0 0 0 0 0 1 0, 0, 1: External event count mode (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0 0 0 0 0 0 0 0 0: Disable TOAB10 pin output 0: Disable TOAB11 pin output 0: Disable TOAB12 pin output 0: Disable TOAB13 pin output (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 314 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TAB1 counter read buffer register (TAB1CNT) The count value of the 16-bit counter can be read by reading the TAB1CNT register. (f) TAB1 capture/compare register 0 (TAB1CCR0) If D0 is set to the TAB1CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTAB1CC0) is generated when the number of external event counts reaches (D0 + 1). (g) TAB1 capture/compare registers 1 to 3 (TAB1CCR1 to TAB1CCR3) Usually, the TAB1CCR1 to TAB1CCR3 registers are not used in the external event count mode. However, the set value of the TAB1CCR1 to TAB1CCR3 registers are transferred to the CCR1 to CCR3 buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTAB1CC1 to INTTAB1CC3) are generated. Therefore, mask the interrupt signals by using the interrupt mask flags (TAB1CCMK1 to TAB1CCMK3). Remark TAB1 I/O control register 1 (TAB1IOC1) and TAB1 option register 0 (TAB1OPT0) are not used in the external event count mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 315 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TAB1CE bit TAB1CCR0 register D0 INTTAB1CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits) TAB1CTL1 register, TAB1IOC0 register, TAB1IOC2 register, TAB1CCR0 register TAB1CE bit = 1 The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). <2> Count operation stop flow TAB1CE bit = 0 The counter is initialized and counting is stopped by clearing the TAB1CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 316 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TAB1CCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits = 000, TAB1CTL1.TAB1EEE bit = 1). (a) Operation if TAB1CCR0 register is set to FFFFH If the TAB1CCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTAB1CC0 signal is generated. At this time, the TAB1OPT0.TAB1OVF bit is not set. FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register FFFFH INTTAB1CC0 signal External event count signal interval R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 External event count signal interval External event count signal interval Page 317 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Notes on rewriting the TAB1CCR0 register To change the value of the TAB1CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAB1CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter D1 D2 D2 D2 0000H TAB1CE bit D1 TAB1CCR0 register D2 INTTAB1CC0 signal External event count signal interval (1) (D1 + 1) External event count signal interval (NG) (10000H + D2 + 1) External event count signal interval (2) (D2 + 1) If the value of the TAB1CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAB1CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTAB1CC0 signal is generated. Therefore, the INTTAB1CC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 318 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Operation of TAB1CCR1 to TAB1CCR3 registers Figure 7-13. Configuration of TAB1CCR1 to TAB1CCR3 Registers TAB1CCR1 register CCR1 buffer register Match signal INTTAB1CC1 signal TAB1CCR2 register CCR2 buffer register Match signal INTTAB1CC2 signal TAB1CCR3 register CCR3 buffer register Match signal INTTAB1CC3 signal Clear EVTAB1 Edge detector 16-bit counter Match signal TAB1CE bit INTTAB1CC0 signal CCR0 buffer register TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 319 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is smaller than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is generated once per cycle. Remark k = 1 to 3, Figure 7-14. Timing Chart When D01 Dk1 FFFFH 16-bit counter D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 D01 D31 D11 D21 0000H TAB1CE bit TAB1CCR0 register D01 INTTAB1CC0 signal TAB1CCR1 register D11 INTTAB1CC1 signal TAB1CCR2 register D21 INTTAB1CC2 signal TAB1CCR3 register D31 INTTAB1CC3 signal If the set value of the TAB1CCRk register is greater than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is not generated because the count value of the 16-bit counter and the value of the TAB1CCRk register do not match. Remark k = 1 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 320 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-15. Timing Chart When D01 < Dk1 FFFFH D01 D01 D01 D01 16-bit counter 0000H TAB1CE bit D01 TAB1CCR0 register INTTAB1CC0 signal TAB1CCR1 register INTTAB1CC1 signal D11 L TAB1CCR2 register INTTAB1CC2 signal D21 L TAB1CCR3 register INTTAB1CC3 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 D31 L Page 321 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) External trigger pulse output mode (TAB1MD2 to TAB1MD0 bits = 010) In the external trigger pulse output mode, TAB1 waits for a trigger when the TAB1CTL0.TAB1CE bit is set to 1. When the valid edge of the external trigger input signal is detected, TAB1 starts counting, and outputs a PWM waveform from the TOAB11 to TOAB13 pins. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOAB10 pin. Figure 7-16. Configuration in External Trigger Pulse Output Mode TAB1CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOAB11 pin INTTAB1CC1 signal TAB1CCR2 register Transfer S Output R controller CCR2 buffer register Match signal TOAB12 pin INTTAB1CC2 signal TAB1CCR3 register Transfer Edge detector EVTAB1 pin CCR3 buffer register Software trigger generation Output S controller R (RS-FF) Match signal TOAB13 pin INTTAB1CC3 signal Clear Count clock selection Count start control 16-bit counter Output controller Match signal TAB1CE bit TOAB10 pin INTTAB1CC0 signal CCR0 buffer register Transfer TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 322 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 D3 D3 D2 16-bit counter D0 D3 D2 D1 D0 D3 D2 D1 D1 D1 D0 D2 D1 0000H TAB1CE bit External trigger input (TRGAB1 pin input) TAB1CCR0 register D0 INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) D1 TAB1CCR1 register INTTAB1CC1 signal TOAB11 pin output Active level width (D1) Active level width (D1) Active level Active level width width (D1) (D1) TAB1CCR2 register Active level width (D1) D2 INTTAB1CC2 signal TOAB12 pin output Active level width (D2) Active level width (D2) TAB1CCR3 register Active level width (D2) D3 INTTAB1CC3 signal TOAB13 pin output Active level width (D3) Wait Cycle (D0 + 1) for trigger R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Page 323 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) TAB1 waits for a trigger when the TAB1CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOAB1k pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOAB10 pin is inverted. The TOAB1k pin outputs a high level regardless of the status (high/low) when a trigger is generated.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAB1CCRk register) x Count clock cycle Cycle = (Set value of TAB1CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TAB1CCRk register)/(Set value of TAB1CCR0 register + 1) The compare match request signal (INTTAB1CC0) is generated when the 16-bit counter counts up next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTAB1CCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The value set to the TAB1CCRm register is transferred to the CCRm buffer register when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The valid edge of the external trigger input signal or setting the software trigger (TAB1CTL1.TAB1EST bit) to 1 is used as the trigger. Remark k = 1 to 3, m = 0 to 3, Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/3) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TAB1CTL1.TAB1EEE bit = 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 324 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0/1 0/1 TAB1MD2 TAB1MD1 TAB1MD0 0 0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TAB1CKS0 to TAB1CKS2 bits 1: Count by external event input signal Generate software trigger when 1 is written (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0/1Note 0: Disable TOAB10 pin output 1: Enable TOAB10 pin output Setting of output level while operation of TOAB10 pin is disabled 0: Low level 1: High level 0: Disable TOAB11 pin output 1: Enable TOAB11 pin output Specification of active level of TOAB11 pin output 0: Active-high 1: Active-low 0: Disable TOAB12 pin output 1: Enable TOAB12 pin output Specification of active level of TOAB12 pin output 0: Active-high 1: Active-low 0: Disable TOAB13 pin output 1: Enable TOAB13 pin output Specification of active level of TOAB13 pin output 0: Active-high 1: Active-low * When TAB1OLk bit = 0 * When TAB1OLk bit = 1 16-bit counter 16-bit counter TOAB1k pin output TOAB1k pin output Note Clear this bit to 0 when the TOAB10 pin is not used in the external trigger pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 325 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register. (f) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) If D0 is set to the TAB1CCR0 register, D1 to the TAB1CCR1 register, D2 to the TAB1CCR2 register, and D3 to the TAB1CCR3 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle TOAB11 pin PWM waveform active level width = D1 x Count clock cycle TOAB12 pin PWM waveform active level width = D2 x Count clock cycle TOAB13 pin PWM waveform active level width = D3 x Count clock cycle Remarks 1. TAB1 I/O control register 1 (TAB1IOC1) and TAB1 option register 0 (TAB1OPT0) are not used in the external trigger pulse output mode. 2. Updating TAB1 capture/compare register 2 (TAB1CCR2) and TAB1 capture/compare register 3 (TAB1CCR3) is enabled by writing TAB1 capture/compare register 1 (TAB1CCR1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 326 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 D00 16-bit counter D30 D10 D20 D00 D31 D21 D31 D21 D11 D11 D00 D00 D31 D21 D30 D20 D10 D10 D00 D31 D21 D11 0000H TAB1CE bit External trigger input (TRGAB1 pin input) TAB1CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) D10 TAB1CCR1 register D11 D10 CCR1 buffer register D11 D10 D11 D11 D10 D10 D11 D10 D11 INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D20 CCR2 buffer register D20 D21 D20 D21 D21 D20 D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register D30 CCR3 buffer register D30 D31 D30 D31 D31 D30 D31 INTTAB1CC3 signal TOAB13 pin output <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <3> <4> <5> <6> <7> Page 327 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC0 register, TAB1IOC2 register, TAB1CCR0 to TAB1CCR3 registers TAB1CE bit = 1 <4> TAB1CCR1 to TAB1CCR3 register setting change flow Setting of TAB1CCR2, TAB1CCR3 registers The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting is enabled (TAB1CE bit = 1). Trigger wait status Setting of TAB1CCR1 register <5> TAB1CCR2, TAB1CCR3 register setting change flow Setting of TAB1CCR2, TAB1CCR3 registers Setting of TAB1CCR1 register <2> TAB1CCR0 to TAB1CCR3 register setting change flow Setting of TAB1CCR0, TAB1CCR2, and TAB1CCR3 registers Setting of TAB1CCR1 register Writing the TAB1CCR1 register must be performed after writing the TAB1CCR0, TAB1CCR2, and TAB1CCR3 registers. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer registers. Setting of TAB1CCR0 register Setting of TAB1CCR1 register Remark When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. Writing the same value to the TAB1CCR1 register is necessary only when the set duty factor of the TOAB12 and TOAB13 pin outputs is changed. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. <6> TAB1CCR1 register setting change flow Setting of TAB1CCR1 register <3> TAB1CCR0 register setting change flow Writing the same value to the TAB1CCR1 register is necessary only when the set cycle is changed. Writing the TAB1CCR1 register must be performed only when the set duty factor is changed after writing the TAB1CCR2 and TAB1CCR3 registers. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. The TAB1CCR1 register only needs to be written, only when the set duty factor of the TOAB11 pin output is changed. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. <7> Count operation stop flow TAB1CE bit = 0 Counting is stopped. STOP m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 328 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAB1CCR1 register last. Rewrite the TAB1CCRk register after writing the TAB1CCR1 register after the INTTAB1CC0 signal is detected. FFFFH 16-bit counter 0000H D01 D00 D30 D20 D10 D00 D30 D20 D10 D00 D30 D20 D10 D01 D31 D21 D31 D21 D11 D11 TAB1CE bit External trigger input (TRGAB1 pin input)Note TAB1CCR0 register D00 D01 D00 CCR0 buffer register D01 INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) D10 TAB1CCR1 register D11 D10 CCR1 buffer register D11 INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D20 D21 D20 CCR2 buffer register D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register CCR3 buffer register D30 D31 D30 D31 INTTAB1CC3 signal TOAB13 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 329 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TAB1CCRm register to the CCRm buffer register, the TAB1CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TAB1CCR0 register, set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then set the active level to the TAB1CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAB1CCR0 register, and then write the same value to the TAB1CCR1 register. To change only the active level width (duty factor) of the PWM waveform, first set the active level to the TAB1CCR2 and TAB1CCR3 registers and then set the active level to the TAB1CCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOAB11 pin, only the TAB1CCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOAB12 and TOAB13 pins, first set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then write the same value to the TAB1CCR1 register. After data is written to the TAB1CCR1 register, the value written to the TAB1CCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value to be compared with the 16-bit counter. To write the TAB1CCR0 to TAB1CCR3 registers again after writing the TAB1CCR1 register once, do so after the INTTAB1CC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAB1CCRm register to the CCRm buffer register conflicts with writing the TAB1CCRm register. Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 330 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAB1CCRk register to 0000H. If the set value of the TAB1CCR0 register is FFFFH, the INTTAB1CCk signal is generated periodically. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAB1CE bit TAB1CCR0 register D0 D0 D0 TAB1CCRk register 0000H 0000H 0000H INTTAB1CC0 signal INTTAB1CCk signal TOAB1k pin output Remark L k = 1 to 3, To output a 100% waveform, set a value of "set value of TAB1CCR0 register + 1" to the TAB1CCRk register. If the set value of the TAB1CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAB1CE bit TAB1CCR0 register D0 D0 D0 TAB1CCRk register D0 + 1 D0 + 1 D0 + 1 INTTAB1CC0 signal INTTAB1CCk signal TOAB1k pin output Remark k = 1 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 331 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTAB1CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOAB1k pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF Dk - 1 0000 Dk 0000 External trigger input (TRGAB1 pin input) Dk CCRk buffer register INTTAB1CCk signal TOAB1k pin output Shortened Remark k = 1 to 3, If the trigger is detected immediately before the INTTAB1CCk signal is generated, the INTTAB1CCk signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOAB1k pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter FFFF 0000 Dk - 2 0000 0001 Dk - 1 Dk External trigger input (TRGAB1 pin input) CCRk buffer register Dk INTTAB1CCk signal TOAB1k pin output Extended Remark k = 1 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 332 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTAB1CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOAB1k pin is extended by time from generation of the INTTAB1CC0 signal to trigger detection. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0000 External trigger input (TRGAB1 pin input) D0 CCR0 buffer register INTTAB1CC0 signal TOAB1k pin output Extended Remark k = 1 to 3, If the trigger is detected immediately before the INTTAB1CC0 signal is generated, the INTTAB1CC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOAB1k pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 External trigger input (TRGAB1 pin input) CCR0 buffer register D0 INTTAB1CC0 signal TOAB1k pin output Shortened Remark k = 1 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 333 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Generation timing of compare match interrupt request signal (INTTAB1CCk) The timing of generation of the INTTAB1CCk signal in the external trigger pulse output mode differs from the timing of other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Count clock 16-bit counter CCRk buffer register Dk - 2 Dk - 1 Dk Dk + 1 Dk + 2 Dk TOAB1k pin output INTTAB1CCk signal Remark k = 1 to 3, Usually, the INTTAB1CCk signal is generated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the CCRk buffer register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOAB1k pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 334 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.4 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) One-shot pulse output mode (TAB1MD2 to TAB1MD0 bits = 011) In the one-shot pulse output mode, TAB1 waits for a trigger when the TAB1CTL0.TAB1CE bit is set to 1. When the valid edge of the external trigger input is detected, TAB1 starts counting, and outputs a one-shot pulse from the TOAB11 to TOAB13 pins. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOAB10 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 7-20. Configuration in One-Shot Pulse Output Mode TAB1CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOAB11 pin INTTAB1CC1 signal TAB1CCR2 register Transfer Output S controller R (RS-FF) CCR2 buffer register Match signal TOAB12 pin INTTAB1CC2 signal TAB1CCR3 register TRGAB1 pin Transfer Edge detector S Output controller R (RS-FF) CCR3 buffer register Software trigger generation Match signal TOAB13 pin INTTAB1CC3 signal Clear Count clock selection Count start control S Output controller R (RS-FF) 16-bit counter Match signal TAB1CE bit TOAB10 pin INTTAB1CC0 signal CCR0 buffer register Transfer TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 335 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 D0 D3 16-bit counter D0 D3 D2 D3 D2 D1 D2 D1 D1 0000H TAB1CE bit External trigger input (TRGAB1 pin input) D0 TAB1CCR0 register INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) TAB1CCR1 register D1 INTTAB1CC1 signal TOAB11 pin output Delay (D1) Active level width (D0 - D1 + 1) TAB1CCR2 register Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Active level width (D0 - D1 + 1) D2 INTTAB1CC2 signal TOAB12 pin output Delay (D2) TAB1CCR3 register Active level width (D0 - D2 + 1) Delay (D2) Active level width (D0 - D2 + 1) Delay (D2) Active level width (D0 - D2 + 1) D3 INTTAB1CC3 signal TOAB13 pin output Delay (D3) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Active level width (D0 - D3 + 1) Delay (D3) Active level width (D0 - D3 + 1) Delay (D3) Active level width (D0 - D3 + 1) Page 336 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, TAB1 waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAB1k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TAB1CCRk register) x Count clock cycle Active level width = (Set value of TAB1CCR0 register - Set value of TAB1CCRk register + 1) x Count clock cycle The compare match interrupt request signal INTTAB1CC0 is generated when the 16-bit counter counts up after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTAB1CCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The valid edge of the external trigger input or setting the software trigger (TAB1CTL1.TAB1EST bit) to 1 is used as the trigger. Remark k = 1 to 3 Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0/1 0/1 TAB1MD2 TAB1MD1 TAB1MD0 0 0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TAB1CKS0 to TAB1CKS2 bits 1: Count by external event count input signal Generate software trigger when 1 is written Note The setting is invalid when the TAB1CTL1.TAB1EEE bit = 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 337 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/3) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0/1Note 0: Disable TOAB10 pin output 1: Enable TOAB10 pin output Setting of output level while operation of TOAB10 pin is disabled 0: Low level 1: High level 0: Disable TOAB11 pin output 1: Enable TOAB11 pin output Specification of active level of TOAB11 pin output 0: Active-high 1: Active-low 0: Disable TOAB12 pin output 1: Enable TOAB12 pin output Specification of active level of TOAB12 pin output 0: Active-high 1: Active-low 0: Disable TOAB13 pin output 1: Enable TOAB13 pin output Specification of active level of TOAB13 pin output 0: Active-high 1: Active-low * When TAB1OLk bit = 0 * When TAB1OLk bit = 1 16-bit counter 16-bit counter TOAB1k pin output TOAB1k pin output (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register. Note Clear this bit to 0 when the TOAB10 pin is not used in the one-shot pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 338 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) If D0 is set to the TAB1CCR0 register and Dk to the TAB1CCRk register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 - Dk + 1) x Count clock cycle Output delay period = (Dk) x Count clock cycle Caution One-shot pulses are not output even in the one-shot pulse output mode, if the set value of the TAB1CCRk register is greater than that value of the TAB1CCR0 register. Remarks 1. TAB1 I/O control register 1 (TAB1IOC1) and TAB1 option register 0 (TAB1OPT0) are not used in the one-shot pulse output mode. 2. k = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 339 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH D00 D01 D30 16-bit counter D31 D20 D10 D11 D21 0000H TAB1CE bit External trigger input TRGAB1 pin input TAB1CCR0 register D00 D01 D10 D11 INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) TAB1CCR1 register INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D20 D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register D30 D31 INTTAB1CC3 signal TOAB13 pin output <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <3> Page 340 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TAB1CCR0 to TAB1CCR3 register setting change flow START Setting of TAB1CCR0 to TAB1CCR3 registers Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC0 register, TAB1IOC2 register, TAB1CCR0 to TAB1CCR3 registers TAB1CE bit = 1 The initial setting of these registers is performed before setting the TAB1CE bit to 1. As rewriting the TAB1CCRm register immediately sends the data to the CCRm buffer register, rewriting immediately after the generation of the INTTAB1CCR0 signal is recommended. <3> Count operation stop flow The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). Trigger wait status TAB1CE bit = 0 Count operation is stopped STOP Remark m = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 341 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in one-shot pulse output mode (a) Notes on rewriting TAB1CCRm register To change the set value of the TAB1CCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TAB1CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter D00 D00 D01 Dk0 D01 Dk0 Dk1 Dk1 0000H TAB1CE bit External trigger input (TRGAB1 pin input) TAB1CCR0 register D00 D01 INTTAB1CC0 signal TOAB10 pin output (only when software trigger is used) TAB1CCRk register Dk0 Dk1 INTTAB1CCk signal TOAB1k pin output Delay (Dk0) Active level width (D00 - Dk0 + 1) Delay (Dk1) Delay (10000H + Dk1) Active level width (D01 - Dk1 + 1) Active level width (D01 - Dk1 + 1) When the TAB1CCR0 register is rewritten from D00 to D01 and the TAB1CCRk register from Dk0 to Dk1 where D00 > D01 and Dk0 > Dk1, if the TAB1CCRk register is rewritten when the count value of the 16-bit counter is greater than Dk1 and less than Dk0 and if the TAB1CCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches Dk1, the counter generates the INTTAB1CCk signal and asserts the TOAB1k pin. When the count value matches D01, the counter generates the INTTAB1CC0 signal, deasserts the TOAB1k pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected. Remark k = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 342 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Generation timing of compare match interrupt request signal (INTTAB1CCk) The generation timing of the INTTAB1CCk signal in the one-shot pulse output mode is different from other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the TAB1CCRk register. Count clock 16-bit counter Dk - 2 Dk - 1 TAB1CCRk register Dk Dk + 1 Dk + 2 Dk TOAB1k pin output INTTAB1CCk signal Usually, the INTTAB1CCk signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TAB1CCRk register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOAB1k pin. Remark k = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 343 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.5 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) PWM output mode (TAB1MD2 to TAB1MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOAB11 to TOAB13 pins when the TAB1CTL0.TAB1CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAB10 pin. Figure 7-24. Configuration in PWM Output Mode TAB1CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOAB11 pin INTTAB1CC1 signal TAB1CCR2 register Transfer Output S controller R (RS-FF) CCR2 buffer register Match signal TOAB12 pin INTTAB1CC2 signal TAB1CCR3 register Transfer CCR3 buffer register Output S controller R (RS-FF) Match signal TOAB13 pin INTTAB1CC3 signal Clear Count clock selection 16-bit counter Output controller Match signal TAB1CE bit TOAB10 pin INTTAB1CC0 signal CCR0 buffer register Transfer TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 344 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-25. Basic Timing in PWM Output Mode FFFFH D3 16-bit counter D1 D0 D3 D0 D3 D2 D2 D0 D3 D2 D1 D0 D2 D1 D1 0000H TAB1CE bit D0 TAB1CCR0 register INTTAB1CC0 signal TOAB10 pin output TAB1CCR1 register D1 INTTAB1CC1 signal TOAB11 pin output Active level width (D1) Active level width (D1) Active level width (D1) TAB1CCR2 register Active level width (D1) D2 INTTAB1CC2 signal TOAB12 pin output Active level width (D2) Active level width (D2) TAB1CCR3 register Active level width (D2) Active level width (D2) D3 INTTAB1CC3 signal TOAB13 pin output Active level width (D3) Cycle (D0 + 1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Page 345 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOAB1k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAB1CCRk register) x Count clock cycle Cycle = (Set value of TAB1CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TAB1CCRk register)/(Set value of TAB1CCR0 register + 1) The PWM waveform can be changed by rewriting the TAB1CCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTAB1CC0) is generated when the 16-bit counter counts up next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTAB1CCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Remark k = 1 to 3, m = 0 to 3, Figure 7-26. Setting of Registers in PWM Output Mode (1/3) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0 0/1 TAB1MD2 TAB1MD1 TAB1MD0 0 0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TAB1CKS0 to TAB1CKS2 bits 1: Count by external event count input signal Note The setting is invalid when the TAB1CTL1.TAB1EEE bit = 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 346 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-26. Setting of Registers in PWM Output Mode (2/3) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0/1Note 0: Disable TOAB10 pin output 1: Enable TOAB10 pin output Setting of output level while operation of TOAB10 pin is disabled 0: Low level 1: High level 0: Disable TOAB11 pin output 1: Enable TOAB11 pin output Specification of active level of TOAB11 pin output 0: Active-high 1: Active-low 0: Disable TOAB12 pin output 1: Enable TOAB12 pin output Specification of active level of TOAB12 pin output 0: Active-high 1: Active-low 0: Disable TOAB13 pin output 1: Enable TOAB13 pin output Specification of active level of TOAB13 pin output 0: Active-high 1: Active-low * When TAB1OLk bit = 0 * When TAB1OLk bit = 1 16-bit counter 16-bit counter TOAB1k pin output TOAB1k pin output (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register. Note Clear this bit to 0 when the TOAB10 pin is not used in the PWM output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 347 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-26. Register Setting in PWM Output Mode (3/3) (f) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) If D0 is set to the TAB1CCR0 register and Dk to the TAB1CCRk register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = Dk x Count clock cycle Remarks 1. TAB1 I/O control register 1 (TAB1IOC1) and TAB1 option register 0 (TAB1OPT0) are not used in the PWM output mode. 2. Updating TAB1 capture/compare register 2 (TAB1CCR2) and TAB1 capture/compare register 3 (TAB1CCR3) is enabled by writing TAB1 capture/compare register 1 (TAB1CCR1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 348 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 D00 16-bit counter D30 D10 D20 D00 D31 D21 D31 D21 D11 D11 D00 D00 D31 D21 D30 D20 D10 D10 D00 D31 D21 D11 0000H TAB1CE bit TAB1CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTAB1CC0 signal TOAB10 pin output TAB1CCR1 register D10 CCR1 buffer register D11 D10 D11 D10 D11 D11 D10 D10 D11 D10 D11 INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D20 CCR2 buffer register D20 D21 D20 D21 D21 D20 D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register D30 CCR3 buffer register D30 D31 D30 D31 D31 D30 D31 INTTAB1CC3 signal TOAB13 pin output <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <3> <4> <5> <6> <7> Page 349 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC0 register, TAB1IOC2 register, TAB1CCR0 to TAB1CCR3 registers TAB1CE bit = 1 <4> TAB1CCR1 to TAB1CCR3 register setting change flow Setting of TAB1CCR2, TAB1CCR3 registers The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting is enabled (TAB1CE bit = 1). Setting of TAB1CCR1 register <5> TAB1CCR2, TAB1CCR3 register setting change flow Setting of TAB1CCR2, TAB1CCR3 registers Setting of TAB1CCR1 register <2> TAB1CCR0 to TAB1CCR3 register setting change flow Setting of TAB1CCR0, TAB1CCR2, and TAB1CCR3 registers Setting of TAB1CCR1 register Writing the TAB1CCR1 register must be performed after writing the TAB1CCR0, TAB1CCR2, and TAB1CCR3 registers. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer registers. Writing the TAB1CCR1 register must be performed only when the set duty factor is changed after writing the TAB1CCR2 and TAB1CCR3 registers. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. Writing the same value to the TAB1CCR1 register is necessary only when the set duty factor of TOAB12 and TOAB13 pin outputs is changed. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. <6> TAB1CCR1 register setting change flow Setting of TAB1CCR1 register The TAB1CCR1 register only needs to be written, only when the set duty factor is changed. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. <3> TAB1CCR0 register setting change flow Setting of TAB1CCR0 register Setting of TAB1CCR1 register Remark Writing the same value to TAB1CCR1 is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TAB1CCRm register is transferred to the CCRm buffer register. <7> Count operation stop flow TAB1CE bit = 0 Counting is stopped. STOP k = 1 to 3, m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 350 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAB1CCR1 register last. Rewrite the TAB1CCRk register after writing the TAB1CCR1 register after the INTTAB1CC1 signal is detected. FFFFH 16-bit counter 0000H D01 D00 D30 D20 D10 D00 D30 D20 D10 D00 D30 D20 D10 D01 D31 D21 D31 D21 D11 D11 TAB1CE bit TAB1CCR0 register D00 D01 D00 CCR0 buffer register D01 INTTAB1CC0 signal TOAB10 pin output D10 TAB1CCR1 register CCR1 buffer register D11 D10 D11 INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register CCR2 buffer register D20 D21 D20 D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register CCR3 buffer register D30 D30 D31 D31 INTTAB1CC3 signal TOAB13 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 351 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TAB1CCRm register to the CCRm buffer register, the TAB1CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TAB1CCR0 register, set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then set the active level width to the TAB1CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAB1CCR0 register, and then write the same value to the TAB1CCR1 register. To change only the active level width (duty factor) of the PWM wave, first set the active level to the TAB1CCR2 and TAB1CCR3 registers, and then set the active level to the TAB1CCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOAB11 pin, only the TAB1CCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOAB12 and TOAB13 pins, first set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then write the same value to the TAB1CCR1 register. After the TAB1CCR1 register is written, the value written to the TAB1CCRm register is transferred to the CCRm buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as the value to be compared with the value of the 16-bit counter. To write the TAB1CCR0 to TAB1CCR3 registers again after writing the TAB1CCR1 register once, do so after the INTTAB1CC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAB1CCRm register to the CCRm buffer register conflicts with writing the TAB1CCRm register. Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 352 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAB1CCRk register to 0000H. If the set value of the TAB1CCR0 register is FFFFH, the INTTAB1CCk signal is generated periodically. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAB1CE bit TAB1CCR0 register D0 D0 D0 TAB1CCRk register 0000H 0000H 0000H INTTAB1CC0 signal INTTAB1CCk signal TOAB1k pin output Remark L k = 1 to 3 To output a 100% waveform, set a value of "set value of TAB1CCR0 register + 1" to the TAB1CCRk register. If the set value of the TAB1CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TAB1CE bit TAB1CCR0 register D0 D0 D0 TAB1CCRk register D0 + 1 D0 + 1 D0 + 1 INTTAB1CC0 signal INTTAB1CCk signal TOAB1k pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 353 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Generation timing of compare match interrupt request signal (INTTAB1CCk) The timing of generation of the INTTAB1CCk signal in the PWM output mode differs from the timing of other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the TAB1CCRk register. Count clock 16-bit counter CCRk buffer register Dk - 2 Dk - 1 Dk Dk + 1 Dk + 2 Dk TOAB1k pin output INTTAB1CCk signal Remark k = 1 to 3 Usually, the INTTAB1CCk signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TAB1CCRk register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOAB1k pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 354 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.6 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Free-running timer mode (TAB1MD2 to TAB1MD0 bits = 101) In the free-running timer mode, TAB1 starts counting when the TAB1CTL0.TAB1CE bit is set to 1. At this time, the TAB1CCRm register can be used as a compare register or a capture register, according to the setting of the TAB1OPT0.TAB1CCS0 and TAB1OPT0.TAB1CCS1 bits. Remark m = 0 to 3, Figure 7-28. Configuration in Free-Running Timer Mode TAB1CCR3 register (compare) TAB1CCR2 register (compare) TAB1CCR1 register (compare) TAB1CCR0 register (compare) Internal count clock External event count input (EVTAB1 pin input) Edge detector TIAB12 pin (capture trigger input) TIAB13 pin (capture trigger input) TOAB13 pin output Output controller TOAB12 pin output Output controller TOAB11 pin output Output controller TOAB10 pin output TAB1CCS0, TAB1CCS1 bits (capture/compare selection) Count clock selection INTTAB1OV signal 16-bit counter TAB1CE bit 0 Edge detector TIAB11 pin (capture trigger input) Output controller INTTAB1CC3 signal 1 TAB1CCR0 register (capture) 0 INTTAB1CC2 signal 1 Edge detector 0 TAB1CCR1 register (capture) Edge detector INTTAB1CC1 signal 1 0 1 INTTAB1CC0 signal TAB1CCR2 register (capture) Edge detector TAB1CCR3 register (capture) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 355 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, TAB1 starts counting, and the output signals of the TOAB10 to TOAB13 pins are inverted. When the count value of the 16-bit counter subsequently matches the set value of the TAB1CCRm register, a compare match interrupt request signal (INTTAB1CCm) is generated, and the output signal of the TOAB1m pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAB1OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAB1OPT0.TAB1OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TAB1CCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Remark m = 0 to 3, Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH 16-bit counter D00 D30 D00 D30 D20 D01 D31 D20 D10 D11 D21 D11 D01 D31 D21 D11 0000H TAB1CE bit D00 TAB1CCR0 register D01 INTTAB1CC0 signal TOAB10 pin output TAB1CCR1 register D10 D11 INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D20 D21 INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register D30 D31 INTTAB1CC3 signal TOAB13 pin output INTTAB1OV signal TAB1OVF bit Cleared to 0 by CLR instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Page 356 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAB1m pin is detected, the count value of the 16-bit counter is stored in the TAB1CCRm register, and a capture interrupt request signal (INTTAB1CCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAB1OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAB1OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Remark m = 0 to 3, Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH 16-bit counter D10 D30 D31 D21 D00 D20 D32 D22 D23 D33 D11 D02 D12 D01 D13 D03 0000H TAB1CE bit TIAB10 pin input TAB1CCR0 register 0000 D00 D01 D02 D03 INTTAB1CC0 signal TIAB11 pin input TAB1CCR1 register 0000 D10 D11 D12 D13 INTTAB1CC1 signal TIAB12 pin input TAB1CCR2 register 0000 D20 D21 D22 D23 INTTAB1CC2 signal TIAB13 pin input TAB1CCR3 register 0000 D30 D31 D32 D33 INTTAB1CC3 signal INTTAB1OV signal TAB1OVF bit Cleared to 0 by CLR instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Page 357 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (1/3) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 TAB1CKS2 TAB1CKS1 TAB1CKS0 0/1 0 0 0 0/1 0 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TAB1CTL1.TAB1EEE bit = 1 (b) TAB1 control register 1 (TAB1CTL1) TAB1SYE TAB1EST TAB1EEE TAB1CTL1 0 0 0/1 TAB1MD2 TAB1MD1 TAB1MD0 0 0 1 0 1 1, 0, 1: Free-running mode 0: Operate with count clock selected by TAB1CKS0 to TAB1CKS2 bits 1: Count by external event count input signal (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOAB10 pin output 1: Enable TOAB10 pin output Setting of output level with operation of TOAB10 pin disabled 0: Low level 1: High level 0: Disable TOAB11 pin output 1: Enable TOAB11 pin output Setting of output level with operation of TOAB11 pin disabled 0: Low level 1: High level 0: Disable TOAB12 pin output 1: Enable TOAB12 pin output Setting of output level with operation of TOAB12 pin disabled 0: Low level 1: High level 0: Disable TOAB13 pin output 1: Enable TOAB13 pin output Setting of output level with operation of TOAB13 pin disabled 0: Low level 1: High level R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 358 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (2/3) (d) TAB1 I/O control register 1 (TAB1IOC1) TAB1IS7 TAB1IS6 TAB1IS5 TAB1IS4 TAB1IS3 TAB1IS2 TAB1IS1 TAB1IS0 TAB1IOC1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Select valid edge of TIAB10 pin input Select valid edge of TIAB11 pin input Select valid edge of TIAB12 pin input Select valid edge of TIAB13 pin input (e) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (f) TAB1 option register 0 (TAB1OPT0) TAB1CCS3 TAB1CCS2 TAB1CCS1 TAB1CCS0 TAB1OPT0 0/1 0/1 0/1 0/1 TAB1OVF 0 0 0 0/1 Overflow flag Specifies if TAB1CCR0 register functions as capture or compare register Specifies if TAB1CCR1 register functions as capture or compare register Specifies if TAB1CCR2 register functions as capture or compare register Specifies if TAB1CCR3 register functions as capture or compare register (g) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 359 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (3/3) (h) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) These registers function as capture registers or compare registers according to the setting of the TAB1OPT0.TAB1CCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIAB1m pin is detected. When the registers function as compare registers and when Dm is set to the TAB1CCRm register, the INTTAB1CCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOAB1m pin is inverted. Remark m = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 360 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D21 D00 D30 D20 16-bit counter D21 D00 D30 D20 D10 D01 D31 D10 D11 D01 D31 D11 D11 0000H TAB1CE bit TAB1CCR0 register D00 D01 Set value changed INTTAB1CC0 signal TOAB10 pin output D10 TAB1CCR1 register D11 Set value changed INTTAB1CC1 signal TOAB11 pin output TAB1CCR2 register D21 D20 Set value changed INTTAB1CC2 signal TOAB12 pin output TAB1CCR3 register D31 D30 Set value changed INTTAB1CC3 signal TOAB13 pin output INTTAB1OV signal TAB1OVF bit <1> Cleared to 0 by CLR instruction <2> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> <3> <2> Page 361 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC0 register, TAB1IOC2 register, TAB1OPT0 register, TAB1CCR0 to TAB1CCR3 registers TAB1CE bit = 1 The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). <2> Overflow flag clear flow Read TAB1OPT0 register (check overflow flag). TAB1OVF bit = 1 NO YES Execute instruction to clear TAB1OVF bit (CLR TAB1OVF). <3> Count operation stop flow TAB1CE bit = 0 The counter is initialized and counting is stopped by clearing the TAB1CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 362 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D30 D31 D21 D00 D20 16-bit counter D32 D22 D23 D33 D11 D02 D12 D01 D13 D03 0000H TAB1CE bit TIAB10 pin input TAB1CCR0 register 0000 D00 D01 D02 D03 0000 INTTAB1CC0 signal TIAB11 pin input TAB1CCR1 register 0000 D10 0000 D20 D11 D12 0000 D13 INTTAB1CC1 signal TIAB12 pin input TAB1CCR2 register D21 D22 D23 0000 INTTAB1CC2 signal TIAB13 pin input TAB1CCR3 register 0000 D30 D31 D32 0000 D33 INTTAB1CC3 signal INTTAB1OV signal TAB1OVF bit <1> Cleared to 0 by CLR instruction <2> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> <3> <2> Page 363 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC1 register, TAB1OPT0 register TAB1CE bit = 1 The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). <2> Overflow flag clear flow Read TAB1OPT0 register (check overflow flag). TAB1OVF bit = 1 NO YES Execute instruction to clear TAB1OVF bit (CLR TAB1OVF). <3> Count operation stop flow TAB1CE bit = 0 The counter is initialized and counting is stopped by clearing the TAB1CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 364 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When TAB1 is used as an interval timer with the TAB1CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAB1CCm signal has been detected. FFFFH D01 D11 D30 D04 D13 D31 D22 D03 D20 D10 16-bit counter D12 D00 D23 D02 D21 0000H TAB1CE bit TAB1CCR0 register D00 D01 D02 D03 D04 D05 INTTAB1CC0 signal TOAB10 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (D01 - D00) (10000H + (D03 - D02) (D04 - D03) D02 - D01) TAB1CCR1 register D10 D11 D12 D13 D14 INTTAB1CC1 signal TOAB11 pin output Interval period (D10 + 1) TAB1CCR2 register Interval period Interval period Interval period (D11 - D10) (10000H + D12 - D11) (D13 - D12) D20 D21 D22 D23 INTTAB1CC2 signal TOAB12 pin output Interval period Interval period Interval period Interval period (D20 + 1) (10000H + D21 - D20) (D22 - D21) (10000H + D23 - D22) TAB1CCR3 register D30 D31 D32 INTTAB1CC3 signal TOAB13 pin output Interval period (D30 + 1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Interval period (10000H + D31 - D30) Page 365 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When performing an interval operation in the free-running timer mode, four intervals can be set with one channel. To perform the interval operation, the value of the corresponding TAB1CCRm register must be re-set in the interrupt servicing that is executed when the INTTAB1CCm signal is detected. The set value for re-setting the TAB1CCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent times: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 366 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TAB1CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAB1CCm signal has been detected and for calculating an interval. FFFFH 16-bit counter D10 D30 D31 D21 D00 D20 D13 D32 D23 D33 D11 D02 D12 D01 D22 D03 0000H TAB1CE bit TIAB10 pin input 0000 TAB1CCR0 register D00 D01 D02 Pulse interval (10000H + D02 - D01) Pulse interval (10000H + D03 - D02) D03 INTTAB1CC0 signal Pulse interval Pulse interval (D00 + 1) (10000H + D01 - D00) TIAB11 pin input TAB1CCR1 register 0000 D10 D11 D12 D13 INTTAB1CC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10 + 1) (10000H + (10000H + (D13 - D12) D11 - D10) D12 - D11) TIAB12 pin input TAB1CCR2 register 0000 D21 D20 D22 D23 INTTAB1CC2 signal Pulse interval (D20 + 1) Pulse interval (10000H + D21 - D20) Pulse interval (20000H + D22 - D21) Pulse interval (D23 - D22) D31 D32 TIAB13 pin input TAB1CCR3 register 0000 D30 D33 INTTAB1CC3 signal Pulse interval Pulse interval (10000H + (D30 + 1) D31 - D30) Pulse interval (10000H + D32 - D31) Pulse interval (10000H + D33 - D32) INTTAB1OV signal TAB1OVF bit Cleared to 0 by CLR instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction Page 367 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TAB1CCRm register in synchronization with the INTTAB1CCm signal, and calculating the difference between the value read this time and the previously read value. Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 368 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH D11 D10 16-bit counter D01 D00 0000H TAB1CE bit TIAB10 pin input TAB1CCR0 register D01 D00 TIAB11 pin input D11 D10 TAB1CCR1 register INTTAB1OV signal TAB1OVF bit <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TAB1CCR0 register (setting of the default value of the TIAB10 pin input). <2> Read the TAB1CCR1 register (setting of the default value of the TIAB11 pin input). <3> Read the TAB1CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TAB1CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two or more capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two or more capture registers. An example of how to use software is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 369 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAB1CE bit INTTAB1OV signal TAB1OVF bit TAB1OVF0 flagNote TIAB10 pin input D01 D00 TAB1CCR0 register TAB1OVF1 flagNote TIAB11 pin input D11 D10 TAB1CCR1 register <1> <2> <3> <4> <5> <6> Note The TAB1OVF0 and TAB1OVF1 flags are set in the internal RAM by software. <1> Read the TAB1CCR0 register (setting of the default value of the TIAB10 pin input). <2> Read the TAB1CCR1 register (setting of the default value of the TIAB11 pin input). <3> An overflow occurs. Set the TAB1OVF0 and TAB1OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TAB1CCR0 register. Read the TAB1OVF0 flag. If the TAB1OVF0 flag is 1, clear it to 0. Because the TAB1OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TAB1CCR1 register. Read the TAB1OVF1 flag. If the TAB1OVF1 flag is 1, clear it to 0 (the TAB1OVF0 flag is cleared in <4>, and the TAB1OVF1 flag remains 1). Because the TAB1OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 370 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TAB1CE bit INTTAB1OV signal TAB1OVF bit TAB1OVF0 flagNote TIAB10 pin input D01 D00 TAB1CCR0 register TAB1OVF1 flagNote TIAB11 pin input D11 D10 TAB1CCR1 register <1> <2> <3> <4> <5> <6> Note The TAB1OVF0 and TAB1OVF1 flags are set in the internal RAM by software. <1> Read the TAB1CCR0 register (setting of the default value of the TIAB10 pin input). <2> Read the TAB1CCR1 register (setting of the default value of the TIAB11 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TAB1CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TAB1OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TAB1CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TAB1OVF1 flag. If the TAB1OVF1 flag is 1, clear it to 0. Because the TAB1OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 371 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TAB1CE bit TIAB1m pin input TAB1CCRm register Dm0 Dm1 INTTAB1OV signal TAB1OVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> The following problem may occur when a long pulse width is measured in the free-running timer mode. <1> Read the TAB1CCRm register (setting of the default value of the TIAB1m pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TAB1CCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. Remark m = 0 to 3, If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 372 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TAB1CE bit TIAB1m pin input TAB1CCRm register Dm0 Dm1 INTTAB1OV signal TAB1OVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software in the internal RAM. <1> Read the TAB1CCRm register (setting of the default value of the TIAB1m pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TAB1CCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 373 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAB1OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAB1OPT0 register. To accurately detect an overflow, read the TAB1OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) Overflow set signal L 0 write signal Overflow flag (TAB1OVF bit) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal L 0 write signal Register access signal Read Write Overflow flag (TAB1OVF bit) (ii) Operation to write 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TAB1OVF bit) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Register access signal Overflow flag (TAB1OVF bit) Read Write H To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 374 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.7 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Pulse width measurement mode (TAB1MD2 to TAB1MD0 bits = 110) In the pulse width measurement mode, TAB1 starts counting when the TAB1CTL0.TAB1CE bit is set to 1. Each time the valid edge input to the TIAB1m pin has been detected, the count value of the 16-bit counter is stored in the TAB1CCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TAB1CCRm register after a capture interrupt request signal (INTTAB1CCm) occurs. Select one of the TIAB10 to TIAB13 pins as the capture trigger input pin. Specify "No edge detected" for the unused pins by using the TAB1IOC1 register. When an external clock is used as the count clock, measure the pulse width of the TIAB0k pin because the external clock is fixed to the TIAB00 pin. At this time, clear the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture trigger input (TIAB00 pin): No edge detected). For TAB1, the external clock is input from the EVTAB1 pin, and the pulse width can be measured by using the TIAB10 to TIAB13 pins. Remark m = 0 to 3, k = 1 to 3 Figure 7-34. Configuration in Pulse Width Measurement Mode Internal count clock EVTAB1 pin input (External event count input) Edge detector Count clock selection Clear 16-bit counter TAB1CE bit Edge detector TIAB11 pin (capture trigger input) TIAB12 pin (capture trigger input) TIAB13 pin (capture trigger input) INTTAB1OV signal INTTAB1CC0 signal TAB1CCR0 register (capture) INTTAB1CC1 signal Edge detector TAB1CCR1 register (capture) INTTAB1CC2 signal INTTAB1CC3 signal Edge detector TAB1CCR2 register (capture) Edge detector TAB1CCR3 register (capture) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 375 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAB1CE bit TIAB1m pin input TAB1CCRm register 0000H D0 D1 D2 D3 INTTAB1CCm signal INTTAB1OV signal TAB1OVF bit Remark Cleared to 0 by CLR instruction m = 0 to 3, When the TAB1CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAB1m pin is later detected, the count value of the 16-bit counter is stored in the TAB1CCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTAB1CCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIAB1m pin even when the 16-bit counter has counted up to FFFFH, an overflow interrupt request signal (INTTAB1OV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TAB1OPT0.TAB1OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TAB1OVF bit setting (1) count + Captured value) x Count clock cycle Remark m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 376 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CTL0 0/1 TAB1CKS2 TAB1CKS1 TAB1CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TAB1EEE bit = 1. (b) TAB1 control register 1 (TAB1CTL1) TAB1MD2 TAB1MD1 TAB1MD0 TAB1EST TAB1EEE TAB1CTL1 0 0 0/1 0 0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate on count clock selected by TAB1CKS0 to TAB1CKS2 bits 1: Count by external event count input signal (c) TAB1 I/O control register 1 (TAB1IOC1) TAB1IS7 TAB1IS6 TAB1IS5 TAB1IS4 TAB1IS3 TAB1IS2 TAB1IS1 TAB1IS0 TAB1IOC1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Select valid edge of TIAB10 pin input Select valid edge of TIAB11 pin input Select valid edge of TIAB12 pin input Select valid edge of TIAB13 pin input (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1EES1 TAB1EES0 TAB1ETS1 TAB1ETS0 TAB1IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 377 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TAB1 option register 0 (TAB1OPT0) TAB1OVF TAB1CCS3 TAB1CCS2 TAB1CCS1 TAB1CCS0 TAB1OPT0 0 0 0 0 0 0 0 0/1 Overflow flag (f) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register. (g) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIAB1m pin is detected. Remarks 1. TAB1 I/O control register 0 (TAB1IOC0) is not used in the pulse width measurement mode. 2. m = 0 to 3, R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 378 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAB1CE bit TIAB10 pin input 0000H TAB1CCR0 register D0 D1 D2 0000H INTTAB1CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TAB1CTL0 register (TAB1CKS0 to TAB1CKS2 bits), TAB1CTL1 register, TAB1IOC1 register, TAB1IOC2 register, TAB1OPT0 register Set TAB1CTL0 register (TAB1CE bit = 1) The initial setting of these registers is performed before setting the TAB1CE bit to 1. The TAB1CKS0 to TAB1CKS2 bits can be set at the same time when counting has been started (TAB1CE bit = 1). <2> Count operation stop flow TAB1CE bit = 0 The counter is initialized and counting is stopped by clearing the TAB1CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 379 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAB1OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAB1OPT0 register. To accurately detect an overflow, read the TAB1OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) Overflow set signal L 0 write signal Overflow flag (TAB1OVF bit) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal L 0 write signal Register access signal Read Write Overflow flag (TAB1OVF bit) (ii) Operation to write 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TAB1OVF bit) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Register access signal Overflow flag (TAB1OVF bit) Read Write H To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 380 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.8 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Triangular wave PWM mode (TAB1MD2 to TAB1MD0 bits = 111) In the triangular wave PWM mode, TAB1 capture/compare register k (TAB1CCRk) is used to set the duty factor, and TAB1 capture/compare register 0 (TAB1CCR0) is used to set the cycle. By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output. The value of the TAB1CCRm register can be rewritten when TAB1CE = 1. To stop timer AB, clear TAB1CE to 0. The PWM waveform is output from the TOAB1k pin. The TOAB10 pin produces a toggle output when the value of the 16-bit counter matches the value of the TAB1CCR0 register and when the counter underflows. Caution In the PWM mode, the capture function of the TAB1CCRm register cannot be used because this register can be used only as a compare register. Remark m = 0 to 3 k = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 381 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-38. Timing of Basic Operation in Triangular Wave PWM Mode (TAB1OE0 = 1, TAB1OE1 = 1, TAB1OE2 = 1, TAB1OE3 = 1, TAB1OL0 = 0, TAB1OL1 = 0, TAB1OL2 = 0, TAB1OL3 = 0) TAB1CE = 1 FFFFH D00 16-bit counter D30 D20 D10 D00 D30 D30 D00 D30 D20 D20 D10 D30 D20 D20 D10 TAB1CCR0 0000H D00 TAB1CCR1 0000H D10 TAB1CCR2 0000H D20 TAB1CCR3 0000H D30 D30 D20 INTTAB1CC0 match interrupt INTTAB1CC1 match interrupt INTTAB1CC2 match interrupt INTTAB1CC3 match interrupt INTTAB1OV TOAB10 TOAB11 TOAB12 TOAB13 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 382 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.5.9 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer output operations The following table shows the operations and output levels of the TOAB10 to TOAB13 pins. Table 7-6. Timer Output Control in Each Mode Operation Mode TOAB10 Pin Interval timer mode Square wave output External event count mode Square wave output External trigger pulse output mode Square wave output One-shot pulse output mode PWM output mode Free-running timer mode TOAB11 Pin TOAB12 Pin TOAB13 Pin - External trigger pulse External trigger pulse External trigger pulse output output output One-shot pulse One-shot pulse One-shot pulse output output output PWM output PWM output PWM output Square wave output (only when compare function is used) - Pulse width measurement mode Triangular wave PWM output mode Square wave output Triangular PWM Triangular PWM Triangular PWM output output output Table 7-7. Truth Table of TOAB10 to TOAB13 Pins Under Control of Timer Output Control Bits TAB1IOC0.TAB1OLm Bit TAB1IOC0.TAB1OEm Bit TAB1CTL0.TAB1CE Bit Level of TOAB1m Pin 0 0 x Low-level output 1 0 Low-level output 1 Low level immediately before counting, 0 x High-level output 1 0 High-level output 1 High level immediately before counting, low high level after counting is started 1 level after counting is started Remark m = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 383 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.6 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer-Tuned Operation Function/Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function/simultaneous-start function. The timers that can be synchronized are listed in Table 7-8. Table 7-8. Timer-Tuned Operation Mode Master Timer Slave Timer TAA1 TAA0 TAB1 TAA4 For details of the timer-tuned operation function, see 6.6 Timer-Tuned Operation Function, and for details of the simultaneous-start function, see 6.7 Simultaneous-Start Function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 384 of 1442 V850ES/JC3-H, V850ES/JE3-H 7.7 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TAB1CCR0, TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers if the capture trigger is input immediately after the TAB1CE bit is set to 1. (a) Free-running timer mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TAB1CCR0 register 0000H FFFFH 0001H TAB1CE bit TIAB10 pin input Capture trigger input Capture trigger input (b) Pulse width measurement mode FFFFH 16-bit counter 0000H Count clock Sampling clock (fXX) TAB1CCR0 register 0000H FFFFH 0002H TAB1CE bit TIAB10 pin input Capture trigger input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Capture trigger input Page 385 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Timer T (TMT) is a 16-bit timer/event counter. An encoder count function and other functions are added to timer AA (TAA). However, TMT does not have a function to operate with an external event count input when it operates in the interval timer mode. The following table shows the function of TMT can be used. Timer mode V850ES/JC3-H (40 pin) V850ES/JC3-H (48 pin) V850ES/JE3-H Interval timer mode External event count mode - - External trigger pulse output mode - - One-shot pulse output mode - - PWM output mode - - Free-running timer mode - - Pulse width measurement mode - - Triangular wave PWM mode - - Encoder compare mode - - 8.1 Overview An overview of TMT0 is given below. * Clock selection: * Capture trigger input pins (TIT00, TIT01): * External event count input pin (EVTT0): * Encoder input pins (TENC00, TENC01): * Encoder clear input pin (TECR0): Note * External trigger input pin : * Timer counter: * Capture/compare registers: * Capture/compare match interrupt request signals: * Timer output pins: Note 8.2 8 types 2 1 2 1 1 1 2 2 2 The external trigger input pin and external event count input pin (EVTT0) are shared with an encoder input pin (TENC00). Functions The functions of TMT0 are shown below. * * * * * * * * * Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Triangular-wave PWM output Encoder count R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 386 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Configuration TMT0 includes the following hardware. Table 8-1. Configuration of TMT0 Item Registers Configuration 16-bit counter x 1 TMT0 capture/compare registers 0, 1 (TT0CCR0, TT0CCR1) TMT0 counter read buffer register (TT0CNT) TMT0 counter write register (TT0TCW) CCR0, CCR1 buffer registers TMT0 control registers 0, 1 (TT0CTL0, TT0CTL1) TMT0 control registers 2 (TT0CTL2) TMT0 I/O control registers 0 to 3 (TT0IOC0 to TT0IOC3) TMT0 option register 0 (TT0OPT0) TMT0 option register 1 (TT0OPT1) TMT noise elimination control register (TTNFC) Timer input * TIT00, TIT01 (capture trigger input pins) * EVTT0/TENC00 (external event input/encoder 0 input pin)Note * TENC01 (encoder 1 input pin) * TENCR0 (encoder clear input pin) Timer output TOT00, TOT01 Note Shared with the external trigger input function R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 387 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-1. Block Diagram of TMT0 Internal bus Counter control Edge detection/ Noise eliminator EVTT0/TENC00 Edge detection/ Noise eliminator TENC01 Edge detection/ Noise eliminator TIT00 Edge detection/ Noise eliminator TIT01 Edge detection/ Noise eliminator fXX fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 Remark Selector TECR0 TT0TCW INTTT0OV 16-bit counter Clear Output controller fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Selector TT0CNT CCR0 buffer register CCR1 buffer register TT0CCR0 TOT00 TOT01 INTTT0CC0 INTTT0CC1 TT0CCR1 INTTT0EC Sampling clock Internal bus fXX: Peripheral clock R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 388 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TT0CNT register. When the TT0CTL0.TT0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TT0CNT register is read at this time, 0000H is read. Reset sets the TT0CE bit to 0. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TT0CCR0 register is used as a compare register, the value written to the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTTCC00) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is set to 0000H after reset, and the TT0CCR0 register is set to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TT0CCR1 register is used as a compare register, the value written to the TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTTCC01) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is set to 0000H after reset, and the TT0CCR1 register is set to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIT00, TIT01, EVTT0/TENC00, TENC01, and TECR0 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TT0IOC1, TT0IOC2, and TT0IOC3 registers. (5) Output controller This circuit controls the output of the TOT00 and TOT01 pins via the TT0IOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. (7) Counter control The count operation is controlled by the timer mode selected by the TT0CTL1 register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 389 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.3.1 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Pin configuration The timer inputs and outputs that configure TMT0 are shared with the following ports. The port functions must be set when using each pin (see Table 4-17 Using Port Pin as Alternate-Function Pin). Table 8-2. Pin Configuration Port Timer Input Pin Timer Output Other Alternate Function P92 TIT01 (capture trigger input 1) TENC01 (encoder input) TOT01 - P93 TIT00 (capture trigger input 0) TECR0 (encoder clear input) TOT00 - P94 Note EVTT0/TENC00 Note - - - The external event count input (EVTT0), encoder input (TENC00), and external trigger input are shared in a state that cannot be controlled by using the port functions. To use each function, set them by using the TT0IOC2 and TT0IOC3 registers after setting their corresponding ports. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 390 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.4 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Registers (1) TMT0 control register 0 (TT0CTL0) The TT0CTL0 register is an 8-bit register that controls the operation of TMT0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TT0CTL0 register by software. After reset: 00H TT0CTL0 R/W Address: FFFF600H <7> 6 5 4 3 TT0CE 0 0 0 0 TT0CE 2 1 0 TT0CKS2 TT0CKS1 TT0CKS0 TMT0 operation control 0 TMT0 operation disabled (TMT0 reset asynchronouslyNote) 1 TMT0 operation enabled. TMT0 operation start Internal count clock selection TT0CKS2 TT0CKS1 TT0CKS0 0 0 0 fXX 0 0 1 fXX/2 0 1 0 fXX/4 0 1 1 fXX/8 1 0 0 fXX/16 1 0 1 fXX/32 1 1 0 fXX/64 1 1 1 fXX/128 Note The TT0OPT0.TT0OVF bit and 16-bit counter are reset simultaneously. Moreover, timer outputs (TOT00 and TOT01) are reset at the same time as the 16-bit counter. Cautions 1. Set the TT0CKS2 to TT0CKS0 bits when the TT0CE bit = 0. When the value of the TT0CE bit is changed from 0 to 1, the TT0CKS2 to TT0CKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to "0". Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 fXX: Peripheral clock Page 391 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) TMT0 control register 1 (TT0CTL1) The TT0CTL1 register is an 8-bit register that controls the TMT0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H TT0CTL1 R/W Address: FFFFF601H 7 6 5 4 0 TT0EST TT0EEE 0 3 1 0 Software trigger control TT0EST - 0 1 2 TT0MD3 TT0MD2 TT0MD1 TT0MD0 Generates a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TT0EST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TT0EST bit as the trigger. The read value of the TT0EST bit is always 0. TT0EEE Count clock selection 0 Disables operation with external event count input (EVTT0 pin). (Performs counting with the count clock selected by the TT0CTL0.TT0CKS0 to TT0CTL0.TT0CKS2 bits.) 1 Enables operation with external event count input (EVTT0 pin). (Performs counting at every valid edge of the external event count input signal (EVTT0 pin).) The TT0EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TT0MD3 TT0MD2 TT0MD1 TT0MD0 0 0 0 0 Interval timer mode 0 0 0 1 External event count mode 0 0 1 0 External trigger pulse output mode 0 0 1 1 One-shot pulse output mode 0 1 0 0 PWM output mode 0 1 0 1 Free-running timer mode 0 1 1 0 Pulse width measurement mode 0 1 1 1 Triangular-wave PWM output mode 1 0 0 0 Encoder compare mode Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Timer mode selection Setting prohibited Page 392 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Cautions 1. The TT0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. The TT0EEE bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, free-running timer mode, pulse width measurement mode, or triangular-wave PWM output mode. In any other mode, writing 1 to this bit is ignored. 3. External event count input (EVTT0) or encoder inputs (TENC00, TENC01) is selected in the external event count mode or encoder compare mode regardless of the value of the TT0EEE bit. 4. Set the TT0EEE and TT0MD3 to TT0MD0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TT0CE bit = 1. If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 5. Be sure to set bits 4 and 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 393 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (3) TMT0 control register 2 (TT0CTL2) The TT0CTL2 register is an 8-bit register that controls the encoder count function operation. The TT0CTL2 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution For details of each bit of the TT0CTL2 register, see 8.6.9 (5) Controlling bits of TT0CTL2 register. (1/2) After reset: 00H 7 TT0CTL2 TT0ECC R/W 6 0 Address: FFFFF602H 5 4 0 3 2 1 0 TT0LDE TT0ECM1 TT0ECM0 TT0UDS1 TT0UDS0 TT0ECC Encoder counter control 0 Normal operation 1 Holds count value of 16-bit counter when TT0CTL0.TT0CE bit = 0. TT0LDE Transfer setting to 16-bit counter 0 Disables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow. 1 Enables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow. TT0ECM1 Control of encoder clear operation 1 0 The 16-bit counter is not cleared to 0000H when its count value matches value of CCR1 register. 1 The 16-bit counter is cleared to 0000H when the count after a match between the 16-bit counter count value and CCR1 register value is a down-count TT0ECM0 0 Control of encoder clear operation 0 The 16-bit counter is not cleared to 0000H when its count value matches value of CCR0 register. 1 The 16-bit counter is cleared to 0000H when the count after a match between the 16-bit counter count value and CCR0 register value is an up-count R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 394 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Up/down count selection TT0UDS1 TT0UDS0 0 0 When valid edge of TENC00 input is detected Counts down when TENC01 = high level. Counts up when TENC01 = low level. 0 1 1 0 Counts up when valid edge of TENC00 input is detected. Counts down when valid edge of TENC01 input is detected. Counts down when rising edge of TENC00 input is detected. Counts up when falling edge of TENC00 input is detected. However, count operation is performed only when TENC01 = low level. 1 1 Both rising and falling edges of TENC00 and TENC01 are detected. Count operation is automatically identified by combination of edge detection and level detection. Cautions 1. The TT0ECC bit is valid only in the encoder compare mode. In any other mode, writing "1" to this bit is ignored. If the TT0CTL0.TT0CE bit is cleared to 0 while the TT0ECC bit = 1, the values of the timer/counter and capture registers (TT0CCR0 and TT0CCR1), and the TT0OPT1, TT0EUF, TT0EOF, and TT0ESF flags are retained. If the TT0CE bit is set from 0 to 1 when the TT0ECC bit = 1, the value of the TT0TCW register is not transferred to the 16-bit counter. 2. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits = 00, 01. Writing "1" to this bit is ignored when the TT0ECM1 and TT0ECM0 bits = 10, 11. 3. The edge detection of the TENC00 and TENC01 inputs specified by the TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits is invalid and fixed to both the rising and falling edges when the TT0UDS1 and TT0UDS0 bits = 10, 11. 4. Set the TT0LDE, TT0ECM1, TT0ECM0, TT0UDS1, and TT0UDS0 bits when the TT0CTL0.TT0CE bit = 0 (the same value can be written to these bits when the TT0CE bit = 1). If the value of these bits is changed when the TT0CE bit = 1, the operation cannot be guaranteed. If it is changed by mistake, clear the TT0CE bit and then set the correct value. 5. Be sure to set bits 5 and 6 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 395 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (4) TMT0 I/O control register 0 (TT0IOC0) The TT0IOC0 register is an 8-bit register that controls the timer output (TOT00, TOT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 396 of 1442 V850ES/JC3-H, V850ES/JE3-H After reset: 00H TT0IOC0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) R/W Address: FFFFF603H 7 6 5 4 0 0 0 0 3 <2> TT0OL1 TT0OE1 1 <0> TT0OL0 TT0OE0 TOT01 pin output level settingNote TT0OL1 0 TOT01 pin starts output at high level. 1 TOT01 pin starts output at low level. TT0OE1 TOT01 pin output setting 0 Timer output prohibited * Low level is output from the TOT01 pin when the TT0OL1 bit = 0. * High level is output from the TOT01 pin when the TT0OL1 bit = 1. 1 Timer output enabled (A pulse is output from the TOT01 pin.) TOT00 pin output level settingNote TT0OL0 0 TOT00 pin starts output at high level. 1 TOT00 pin starts output at low level. TT0OE0 TOT00 pin output setting 0 Timer output prohibited * Low level is output from the TOT00 pin when the TT0OL0 bit = 0. * High level is output from the TOT00 pin when the TT0OL0 bit = 1. 1 Timer output enabled (A pulse is output from the TOT00 pin.) Note The output level of the timer output pins (TOT00 and TOT01) specified by the TT0OLn bit is shown below (). * When TT0OLn bit = 0 * When TT0OLn bit = 1 16-bit counter 16-bit counter TT0CE bit TT0CE bit TOT0n pin output TOT0n pin output Cautions 1. If the setting of the TT0IOC0 register is changed when TOT00 and TOT01 outputs are set for the port mode, the output of the pins change. Set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. Rewrite the TT0OL1, TT0OE1, TT0OL0, and TT0OE0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 3. Even if the TT0OL0 or TT0OL1 bit is manipulated when the TT0CE, TT0OE0, and TT0OE1 bits are 0, the output level of the TOT00 and TOT01 pins changes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 397 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (5) TMT0 I/O control register 1 (TT0IOC1) The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00, TIT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF604H 7 6 5 4 3 2 1 0 0 0 0 0 TT0IS3 TT0IS2 TT0IS1 TT0IS0 TT0IS3 TT0IS2 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TT0IS1 TT0IS0 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TT0IOC1 Capture trigger input signal (TIT01 pin) valid edge setting Capture trigger input signal (TIT00 pin) valid edge setting Cautions 1. Rewrite the TT0IS3 to TT0IS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 2. The TT0IS3 and TT0IS2 bits are valid only in the free-running timer mode (only when the TT0OPT0.TT0CCS1 bit = 1) and the pulse width measurement mode. In all other modes, a capture operation is not performed. The TT0IS1 and TT0IS0 bits are valid only in the free-running timer mode (only when the TT0OPT0. TT0CCS0 bit = 1) and the pulse width measurement mode. In all other modes, a capture operation is not performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 398 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (6) TMT0 I/O control register 2 (TT0IOC2) The TT0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (EVTT0 pin) and external trigger input signal (EVTT0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TT0IOC2 R/W Address: FFFFF605H 7 6 5 4 0 0 0 0 3 2 1 0 TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0EES1 TT0EES0 External event count input signal (EVTT0 pin) valid edge setting 0 0 No edge detection (external event count invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TT0ETS1 TT0ETS0 External trigger input signal (EVTT0 pin) valid edge setting 0 0 No edge detection (external trigger invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TT0EES1, TT0EES0, TT0ETS1, and TT0ETS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 2. The TT0EES1 and TT0EES0 bits are valid only when the TT0CTL1.TT0EEE bit = 1 or when the external event count mode (the TT0CTL1.TT0MD3 to TT0CTL1.TT0MD0 bits = 0001) has been set. 3. The TT0ETS1 and TT0ETS0 bits are valid only in the external trigger pulse mode or one-shot pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 399 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (7) TMT0 I/O control register 3 (TT0IOC3) The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation. The TT0IOC3 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H 7 TT0IOC3 R/W Address: FFFFF606H 6 5 TT0SCE TT0ZCL 4 3 2 1 0 TT0BCL TT0ACL TT0ECS1 TT0ECS0 TT0EIS1 TT0EIS0 TT0SCE Encoder clear selection 0 Clears 16-bit counter on detection of edge of encoder clear signal (TECR0 pin). 1 Clears 16-bit counter on detection of clear level condition of the TENC00, TENC01, and TECR0 pins. * Clears the 16-bit counter to 0000H when the valid edge of TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected when the TT0SCE bit = 0. * Clears the 16-bit counter to 0000H when the clear level conditions of the TT0ZCL, TT0BCL, and TT0ACL bits match the input levels of the TECR0, TENC01, and TENC00 pins when TT0SCE bit = 1. * Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is valid and that of the TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1. An encoder clear interrupt request signal (INTTTI0EC) is not generated. * Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid and setting of the TT0ECS1 and TT0ECS0 bits is valid when the TT0SCE bit = 0. The INTTTI0EC signal is generated when the valid edge specified by the TT0ECS1 and TT0ECS0 bits is detected. * Be sure to set the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits to 10 or 11 when the TT0SCE bit = 1. Operation is not guaranteed if the TT0UDS1 and TT0UDS0 bits = 00 or 01 and the TT0SCE bit = 1. TT0ZCL Clear level selection of encoder clear signal (TECR0 pin) 0 Clears low level of the TECR0 pin. 1 Clears high level of the TECR0 pin. Setting of the TT0ZCL bit is valid only when the TT0SCE bit = 1. TT0BCL Clear level selection of encoder input signal (TENC01 pin) 0 Clears low level of the TENC01 pin. 1 Clears high level of the TENC01 pin. Setting of the TT0BCL bit is valid only when the TT0SCE bit = 1. TT0ACL Clear level selection of encoder input signal (TENC00 pin) 0 Clears low level of the TENC00 pin. 1 Clears high level of the TENC00 pin. Setting of the TT0ACL bit is valid only when the TT0SCE bit = 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 400 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0ECS1 TT0ECS0 Valid edge setting of encoder clear signal (TECR0 pin) 0 0 Detects no edge (clearing encoder is invalid). 0 1 Detects rising edge. 1 0 Detects falling edge. 1 1 Detects both edges. TT0EIS1 TT0EIS0 Valid edge setting of encoder input signals (TENC00, TENC01 pins) 0 0 Detects no edge (inputting encoder is invalid). 0 1 Detects rising edge. 1 0 Detects falling edge. 1 1 Detects both edges. Cautions 1. Rewrite the TT0SCE, TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, TT0ECS0, TT0EIS1, and TT0EIS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written to these bits when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set these bits again. 2. The TT0ECS1 and TT0ECS0 bits are valid only when the TT0SCE bit = 0 and the encoder compare mode is set. 3. The TT0EIS1 and TT0EIS0 bits are valid only when the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits = 00 or 01. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 401 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (8) TMT0 option register 0 (TT0OPT0) The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TT0OPT0 R/W Address: FFFFF607H 7 6 0 0 5 4 TT0CCS1 TT0CCS0 TT0CCS1 3 2 1 <0> 0 0 0 TT0OVF TT0CCR1 register capture/compare selection 0 Selected as compare register 1 Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0) The TT0CCS1 bit setting is valid only in the free-running timer mode. TT0CCS0 TT0CCR0 register capture/compare selection 0 Selected as compare register 1 Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0) The TT0CCS0 bit setting is valid only in the free-running timer mode. TT0OVF TMT0 overflow detection flag Set (1) Overflow occurred Reset (0) 0 written to TT0OVF bit or TT0CTL0.TT0CE bit = 0 * The TT0OVF bit is set to 1 when the 16-bit counter value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An overflow interrupt request signal (INTTT0OV) is generated when the TT0OVF bit is set to 1. The INTTT0OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TT0OVF bit is not cleared to 0 even when the TT0OVF bit or the TT0OPT0 register are read when the TT0OVF bit = 1. * Before clearing the TT0OVF bit to 0 after generation of the INTTT0OV signal, be sure to confirm (by reading) that the TT0OVF bit is set to 1. * The TT0OVF bit can be both read and written, but the TT0OVF bit cannot be set to 1 by software. Writing 1 has no effect on the operation of TMT0. Cautions 1. Rewrite the TT0CCS1 and TT0CCS0 bits when the TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set these bits again. 2. Be sure to set bits 1 to 3, 6, and 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 402 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (9) TMT0 option register 1 (TT0OPT1) The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the encoder count function. The TT0OPT1 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register can be rewritten even when the TT0CTL0.TT0CE bit = 1. (1/2) After reset: 00H TT0OPT1 R/W Address: FFFFF608H 7 6 5 4 3 0 0 0 0 0 TT0EUF Set (1) <2> <0> <1> TT0EUF TT0EOF TT0ESF TMT0 underflow detection flag Underflow occurs. Reset (0) Cleared by writing to TT0EUF bit or when TT0CTL0.TT0CE bit = 0 * The TT0EUF bit is set to 1 when the 16-bit counter underflows from 0000H to FFFFH in the encoder compare mode. * When the TT0CTL2.TT0LDE bit = 1, the TT0EUF bit is set to 1 when the value of the 16-bit counter is changed from 0000H to the set value of the TT0CCR0 register. * An overflow interrupt request signal (INTTTOV0) is generated as soon as the TT0EUF bit is set to 1. * The TT0EUF bit is not cleared to 0 even if the TT0EUF bit or TT0OPT1 register is read when the TT0EUF bit = 1. * The status of the TT0EUF bit is retained even if the TT0CTL0.TT0CE bit is cleared to 0 when the TT0CTL2.TT0ECC bit = 1. * Before clearing the TT0EUF bit to 0 after the INTTTOV0 signal is generated, be sure to confirm (read) that the TT0EUF bit is set to 1. * The TT0EUF bit can be read or written, but it cannot be set to 1 by software. Setting this bit to 1 does not affect the operation of TMT0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 403 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0EOF Set (1) Overflow detection flag for TMT0 encoder function Overflow occurs. Reset (0) Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE bit = 0 * The TT0EOF bit is set to 1 when the 16-bit counter overflows from FFFFH to 0000H in the encoder compare mode. * As soon as the TT0EOF bit has been set to 1, an overflow interrupt request signal (INTTTOV0) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1. * The TT0EOF bit is not cleared to 0 even if the TT0EOF bit or TT0OPT1 register is read when the TT0EOF bit = 1. * The status of the TT0EOF bit is retained even if the TT0CTL0.TT0CE bit is cleared to 0 when the TT0CTL2.TT0ECC bit = 1. * Before clearing the TT0EOF bit to 0 after the INTTTOV0 signal is generated, be sure to confirm (read) that the TT0EOF bit is set to 1. * The TT0EOF bit can be read or written, but it cannot be set to 1 by software. Writing 1 to this bit does not affect the operation of TMT0. TT0ESF TMT0 count-up/-down operation status detection flag 0 TMT0 is counting up. 1 TMT0 is counting down. * This bit is cleared to 0 if the TT0CTL0.TT0CE bit = 0 when the TT0CTL2.TT0ECC bit = 0. * The status of the TT0ESF bit is retained even if the TT0CE bit = 0 when the TT0ECC bit = 1. Caution R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Be sure to set bits 3 to 7 to "0". Page 404 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (10) TMT0 capture/compare register 0 (TT0CCR0) The TT0CCR0 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS0 bit. In the pulse width measurement mode, the TT0CCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TT0CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. After reset: 0000H 15 14 R/W 13 12 Address: FFFFF60AH 11 10 9 8 7 6 5 4 3 2 1 0 TT0CCR0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 405 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR0 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. If TOT00 pin output is enabled at this time, the output of the TOT00 pin is inverted. When the TT0CCR0 register is used as a cycle register in the interval timer mode, or when the TT0CCR0 register is used as a cycle register in the external event count mode, external trigger pulse output mode, oneshot pulse output mode, PWM output mode, triangular-wave PWM output mode, or encoder compare mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0. (b) Function as capture register In the free-running timer mode (when the TT0CCR0 register is used as a capture register), the count value of the 16-bit counter is stored in the TT0CCR0 register if the valid edge of the capture trigger input pin (TIT00 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TT0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIT00 pin) is detected. Even if the capture operation and reading the TT0CCR0 register conflict, the correct value of the TT0CCR0 register can be read. The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode TT0CCR0 Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None Triangular-wave WPM output Compare register Batch write Encoder compare Compare register Anytime write Note Note Note Note Writing to the TT0CCR1 register is the trigger. Remark For anytime write and batch write, see 8.6 (2) Anytime write and batch write. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 406 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (11) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS1 bit. In the pulse width measurement mode, the TT0CCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TT0CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. After reset: 0000H 15 14 R/W 13 12 Address: FFFFFF60CH 11 10 9 8 7 6 5 4 3 2 1 0 TT0CCR1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 407 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR1 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC01) is generated. If TOT01 pin output is enabled at this time, the output of the TOT01 pin is inverted. The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0. (b) Function as capture register In the free-running timer mode (when the TT0CCR1 register is used as a capture register), the count value of the 16-bit counter is stored in the TT0CCR1 register if the valid edge of the capture trigger input pin (TIT01 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TT0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIT01 pin) is detected. Even if the capture operation and reading the TT0CCR1 register conflict, the correct value of the TT0CCR1 register can be read. The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode TT0CCR1 Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None Triangular-wave PWM output Compare register Batch write Encoder compare Compare register Anytime write Note Note Writing to the TT0CCR1 register is the trigger. Remark For anytime write and batch write, see 8.6 (2) Anytime write and batch write. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 408 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (12) TMT0 counter write register (TT0TCW) The TT0TCW register is used to set the initial value of the 16-bit counter. The TT0TCW register is valid only in the encoder compare mode. This register can be read or written in 16-bit units. Rewrite the TT0TCW register when the TT0CTL0.TT0CE bit = 0. The value of the TT0TCW register is transferred to the 16-bit counter when the TT0CE bit is set (1). Reset sets this register to 0000H. After reset: 0000H 15 14 R/W Address: FFFFF610H 12 13 11 10 9 8 7 6 4 5 2 3 1 0 TT0TCW (13) TMT0 counter read buffer register (TT0CNT) The TT0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TT0CTL0.TT0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TT0CNT register is set to 0000H when the TT0CTL2.TT0ECC and TT0CE bits = 0. If the TT0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The TT0CNT register is not set to 0000H but the previous value is read when the TT0ECC bit = 1 and TT0CE bit = 0. The TT0ECC and TT0CE bits are set to 0 after reset, and the value of the TT0CNT register is set to 0000H. After reset: 0000H 15 14 R 13 Address: FFFFFF60EH 12 11 10 9 8 7 6 5 4 3 2 1 0 TT0CNT R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 409 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (14) Noise elimination control register (TTNFC) Digital noise elimination can be selected for the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins. The noise elimination settings are performed using the TTNFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX, fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. Sampling is performed 3 times. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Time equal to the sampling clock x 3 clocks is required until the digital noise eliminator is initialized after the sampling clock has been changed. If the valid edge of the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins is input after the sampling clock has been changed and before the time of the sampling clock x 3 clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using the external trigger function, the external event function, the capture trigger function, and the encoder function of TMT, enable TMT operation after the sampling clock x 3 clocks have elapsed. After reset: 00H TTNFC TTNFEN R/W Address: FFFFF726H 0 0 TTNFEN 0 0 TTNFC2 TTNFC1 TTNFC0 Settings of digital noise elimination 0 Digital noise elimination not executed 1 Digital noise elimination executed TTNFC2 TTNFC1 TTNFC0 Digital sampling clock 0 0 0 fXX 0 0 1 fXX/4 0 1 0 fXX/8 0 1 1 fXX/16 1 0 0 fXX/32 1 0 1 fXX/64 Other than above Setting prohibited Remarks 1. Since sampling is performed three times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 410 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 8-2. Figure 8-2. Example of Digital Noise Elimination Timing Noise elimination clock Input signal Sampling 3 times Sampling 3 times 1 clock 1 clock 2 clocks 2 clocks 3 clocks 3 clocks Internal signal Remark If there are two or fewer noise elimination clocks while the TIT00, TIT01, TENC01, TECR0, and EVTT00 input signals are high level (or low level), the input signal is eliminated as noise. If it is sampled three times or more, the edge is detected as a valid input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 411 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.5 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Timer Output Operations The following table shows the operations and output levels of the TOT00 and TOT01 pins. Table 8-5. Timer Output Control in Each Mode Operation Mode TOT01 Pin TOT00 Pin Interval timer mode Square wave output External event count mode None External trigger pulse output mode External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode None Triangular-wave PWM output mode Triangular-wave PWM output Encoder compare mode None Square wave output Table 8-6. Truth Table of TOT00 and TOT01 Pins Under Control of Timer Output Control Bits TT0IOC0.TT0OLn Bit TT0IOC0.TT0OEn Bit TT0CTL0.TT0CE Bit Level of TOT0n Pin 0 0 x Low-level output 1 0 Low-level output 1 Low level immediately before counting, high level after counting is started 1 0 1 x High-level output 0 High-level output 1 High level immediately before counting, low level after counting is started Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 412 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Operation The functions of TMT0 that can be implemented differ from one channel to another. The functions of each channel are shown below. Table 8-7. TMT0 Specifications in Each Mode Operation TT0CTL1.TT0EST Bit EVTT0 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input) Register Setting Write Method Interval timer mode Invalid Invalid Compare only Anytime write External event count mode Invalid Invalid Compare only Anytime write External trigger pulse output mode Valid Valid Compare only Batch write One-shot pulse output mode Valid Valid Compare only Anytime write PWM output mode Invalid Invalid Compare only Batch write Free-running timer mode Invalid Invalid Switchable Anytime write Pulse width measurement mode Invalid Invalid Capture only Not applicable Triangular-wave PWM output mode Invalid Invalid Compare only Batch write Encoder compare mode Invalid Invalid Compare only Anytime write R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 413 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Basic counter operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. (a) Count start operation * Encoder compare mode A count operation is controlled by TENC00 and TENC01 phases. The 16-bit counter initial setting is performed by transferring the set value of the TT0TCW register to the 16bit counter and the count operation is started. (When the TT0CTL2.TT0ECC bit = 0, the TT0TCW register set value is transferred to the 16-bit counter at the timing when the TT0CTL0.TT0CE bit changes from 0 to 1.) * Triangular-wave PWM mode The 16-bit counter starts counting from the initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on. Following the count-up operation, the counter counts down upon a match between the 16-bit count value and the CCR0 buffer register. * Mode other than above The 16-bit counter starts counting from the initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on. (b) Clear operation The 16-bit counter is cleared to 0000H when its value matches the value of the compare register, when its value is captured, when the edge of the encoder clear signal is detected, and when the clear level condition of the TENC00, TENC01, and TECR0 pins is detected. The count operation from FFFFH to 0000H that takes place immediately after the counter has started counting or when the counter overflows is not a clear operation. Therefore, the INTTT0CC0 and INTTT0CC1 interrupt signals are not generated. (c) Overflow operation The 16-bit counter overflows when it counts up from FFFFH to 0000H in the free-running mode, pulse width measurement mode, and encoder compare mode. If the counter overflows in the free-running mode and pulse width measurement mode, the TT0OPT0.TT0OVF bit is set to 1 and an interrupt request signal (INTTT0OV) is generated. If the counter overflows in the encoder compare mode, the TT0OPT1.TT0EOF bit is set to 1 and an interrupt request signal (INTTT0OV) is generated. Note that the INTTT0OV signal is not generated under the following conditions. * Immediately after a count operation has been started * If the counter value matches the compare value FFFFH and is cleared * When FFFFH is captured and cleared to 0000H in the pulse width measurement mode Caution After the overflow interrupt request signal (INTTT0OV) has been generated, be sure to check that the overflow flag (TT0OVF, TT0EOF bits) is set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 414 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Count value hold operation The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count operation is performed. If the TT0ECC bit = 1 and TT0CE bit = 0, the value of the 16-bit counter is held. When the TT0CE bit is next set to 1, the counter resumes the count operation from the held value. (e) Counter read operation during count operation The value of the 16-bit counter of TMT0 can be read by using the TT0CNT register during the count operation. When the TT0CTL0.TT0CE bit = 1, the value of the 16-bit counter can be read by reading the TT0CNT register. If the TT0CNT register is read when the TT0CTL2.TT0ECC bit = 0 and TT0CE bit = 0, however, it is 0000H. The held value of the TT0CNT register is read if the register is read when the TT0ECC bit = 1 and TT0CE bit = 0. (f) Underflow operation A 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000H to FFFFH in the encoder compare mode. When an underflow occurs, the TT0OPT1.TT0EUF bit is set to 1 and an interrupt request signal (INTTT0OV) is generated. (g) Interrupt operation TMT0 generates the following four types of interrupt request signals. * INTTT0CC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TT0CCR0 register. * INTTT0CC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer register and as a capture interrupt request signal to the TT0CCR1 register. * INTTT0OV interrupt: This signal functions as an overflow interrupt request signal. * INTTT0EC interrupt: This signal functions as a valid edge detection interrupt request signal of the encoder clear input (TECR0 pin). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 415 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Anytime write and batch write The TT0CCR0 and TT0CCR1 registers in TMT0 can be rewritten during timer operation (TT0CTL0.TT0CE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation (). Figure 8-3. Flowchart of Basic Operation for Anytime Write START Initial settings * Set values to TT0CCRn register * Timer operation enable (TT0CE bit = 1) Transfer values of TT0CCRn register to CCRn buffer register TTnCCRn register rewrite Transfer to CCRn buffer register Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start IINTTT0CC1 signal output IINTTT0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remark The above flowchart illustrates an example of the operation in the interval timer mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 416 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-4. Timing of Anytime Write TT0CE bit = 1 D01 FFFFH D01 D02 16-bit counter D11 D11 D12 D12 0000H D01 TT0CCR0 register CCR0 buffer register 0000H D01 D11 TT0CCR1 register CCR1 buffer register D02 0000H D02 D12 D11 D12 INTTT0CC0 signal INTTT0CC1 signal Remarks 1. D01, D02: Set values of TT0CCR0 register D11, D12: Set values of TT0CCR1 register 2. The above timing chart illustrates an example of the operation in the interval timer mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 417 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Batch write In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TT0CCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TT0CCR1 register. In order for the set value when the TT0CCR0 and TT0CCR1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1 buffer registers), it is necessary to rewrite the TT0CCR0 register and then write to the TT0CCR1 register before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TT0CCR0 and TT0CCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite the value of the TT0CCR0 register, also write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 418 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-5. Flowchart of Basic Operation for Batch Write START Initial settings * Set values to TT0CCRn register * Timer operation enable (TT0CE bit = 1) Transfer values of TT0CCRn register to CCRn buffer register TT0CCR0 register rewrite TT0CCR1 register rewrite Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start * Transfer of values of TT0CCRn register to CCRn buffer register Batch write enable INTTT0CC1 signal output INTTT0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TT0CCR1 register includes enabling of batch write. Thus, rewrite the TT0CCR1 register after rewriting the TT0CCR0 register. Remark The above flowchart illustrates an example of the operation in the PWM output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 419 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-6. Timing of Batch Write TT0CE bit = 1 D01 FFFFH D02 D11 D12 16-bit counter D03 D02 D12 D12 D12 0000H TT0CCR0 register D01 CCR0 buffer register 0000H TT0CCR1 register D02 D01 D11 CCR1 buffer register 0000H D03 D02 Note 1 Note 2 D12 D11 D12 Note 1 Note 1 Same value write D12 Note 3 D03 D12 Note 1 INTTT0CC0 signal INTTT0CC1 signal TOT00 pin output TOT01 pin output Notes 1. Because the TT0CCR1 register was not rewritten, D03 is not transferred. 2. Because the TT0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TT0CCR0 register (D01). 3. Because the TT0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TT0CCR0 register (D02). Remarks 1. D01, D02, D03: Set values of TT0CCR0 register D11, D12: Set values of TT0CCR1 register 2. The above timing chart illustrates the operation in the PWM output mode as an example. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 420 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.1 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Interval timer mode (TT0MD3 to TT0MD0 bits = 0000) In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0 register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOT00 pin. The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register, and when the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. In addition, a square wave, which is inverted when the INTTT0CC1 signal is generated, can be output from the TOT01 pin. The value of the TT0CCR0 and TT0CCR1 registers can be rewritten even while the timer is operating. Figure 8-7. Configuration of Interval Timer Clear Count clock selection Output controller 16-bit counter Match signal TT0CE bit TOT00 pin INTTT0CC0 signal CCR0 buffer register TT0CCR0 register Figure 8-8. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 0000H TT0CE bit TT0CCR0 register D0 TOT00 pin output INTTT0CC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 421 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOT00 pin is inverted. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOT00 pin is inverted, and a compare match interrupt request signal (INTTT0CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TT0CCR0 register + 1) x Count clock cycle Figure 8-9. Register Setting for Interval Timer Mode Operation (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 0/1 TT0CKS2 TT0CKS1 TT0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0EEE TT0CTL1 0 0 0 TT0MD3 0 0 TT0MD2 TT0MD1 TT0MD0 0 0 0 0, 0, 0, 0: Interval timer mode (c) TMT0 I/O control register 0 (TT0IOC0) TT0IOC0 0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 0/1 0/1 0/1 0/1 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 422 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-9. Register Setting for Interval Timer Mode Operation (2/2) (d) TMT0 counter read buffer register (TT0CNT) By reading the TT0CNT register, the count value of the 16-bit counter can be read. (e) TMT0 capture/compare register 0 (TT0CCR0) If the TT0CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the TOT01 pin output is inverted and a compare match interrupt request signal (INTTT0CC1) is generated. By setting this register to the same value as the value set in the TT0CCR0 register, a square wave with a duty factor of 50% can be output from the TOT01 pin. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the register by the interrupt mask flag (TT0CCIC1.TT0CCMK1). Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 2 (TT0IOC2), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the interval timer mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 423 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Interval timer mode operation flow Figure 8-10. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TT0CE bit TT0CCR0 register D0 TOT00 pin output INTTT0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0CCR0 register TT0CE bit = 1 Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). <2> Count operation stop flow TT0CE bit = 0 The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. The output level of the TOT00 pin is as specified by the TT0IOC0 register. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 424 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Interval timer mode operation timing (a) Operation if TT0CCR0 register is set to 0000H If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the output of the TOT00 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TT0CE bit TT0CCR0 register 0000H TOT00 pin output INTTT0CC0 signal Interval time Interval time Interval time Count clock cycle Count clock cycle Count clock cycle R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 425 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted. At this time, an overflow interrupt request signal (INTTT0OV) is not generated, nor is the overflow flag (TT0OPT0.TT0OVF bit) set to 1. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register FFFFH TOT00 pin output INTTT0CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 426 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. FFFFH D1 D1 16-bit counter D2 D2 D2 0000H TT0CE bit D1 TT0CCR0 register TT0OL0 bit D2 L TOT00 pin output INTTT0CC0 signal Interval time (1) Remark Interval time (1): Interval time (NG) Interval time (2) (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle If the value of the TT0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted. Therefore, the INTTT0CC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" as originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock cycle". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 427 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Operation of TT0CCR1 register Figure 8-11. Configuration of TT0CCR1 Register TT0CCR1 register CCR1 buffer register Output controller Match signal TOT01 pin INTTT0CC1 signal Clear Count clock selection 16-bit counter Match signal TT0CE bit Output controller TOT00 pin INTTT0CC0 signal CCR0 buffer register TT0CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 428 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CCR1 register is set to the same value as the TT0CCR0 register, the INTTT0CC0 signal is generated at the same timing as the INTTT0CC1 signal and the TOT01 pin output is inverted. In other words, a square wave can be output from the TOT01 pin. The following shows the operation when the TT0CCR1 register is set to other than the value set in the TT0CCR0 register. If the set value of the TT0CCR1 register is less than the set value of the TT0CCR0 register, the INTTT0CC1 signal is generated once per cycle. At the same time, the output of the TOT01 pin is inverted. The TOT01 pin outputs a square wave after outputting a short-width pulse. Figure 8-12. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TT0CE bit TT0CCR0 register D01 TOT00 pin output INTTT0CC0 signal TT0CCR1 register D11 TOT01 pin output INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 429 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the count value of the 16-bit counter does not match the value of the TT0CCR1 register. Consequently, the INTTT0CC1 signal is not generated, nor is the output of the TOT01 pin changed. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 8-13. Timing Chart When D01 < D11 FFFFH D01 D01 D01 D01 16-bit counter 0000H TT0CE bit TT0CCR0 register D01 TOT00 pin output INTTT0CC0 signal D11 TT0CCR1 register TOT01 pin output INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 L Page 430 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.2 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) External event count mode (TT0MD3 to TT0MD0 bits = 0001) In the external event count mode, the valid edge of the external event count input (EVTT0) is counted when the TT0CTL0.TT0CE bit is set to 1, and an interrupt request signal (INTTT0CC0) is generated each time the number of edges set by the TT0CCR0 register have been counted. The TOT00 and TOT01 pins cannot be used. The TT0CCR1 register is not used in the external event count mode. Figure 8-14. Configuration in External Event Count Mode Clear EVTT0 pin (external event count input) Edge detectorNote 16-bit counter Match signal TT0CE bit INTTT0CC0 signal CCR0 buffer register TT0CCR0 register Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 431 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-15. Basic Timing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H 16-bit counter TT0CE bit External event count input (EVTT0 pin input) TT0CCR0 register TT0CCR0 register D0 D0 0000 0001 D0 INTTT0CC0 signal INTTT0CC0 signal External event count (D0 + 1) Remark D0 - 1 External event count (D0 + 1) External event count (D0 + 1) This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 432 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTT0CC0) is generated. The INTTT0CC0 signal is generated each time the valid edge of the external event count input has been detected "value set to TT0CCR0 register + 1" times. Figure 8-16. Register Setting for Operation in External Event Count Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 0/1 TT0CKS2 TT0CKS1 TT0CKS0 0 0 0 0 0 0 0 0: Stops counting 1: Enables counting (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0EEE TT0CTL1 0 0 0 TT0MD3 TT0MD2 TT0MD1 TT0MD0 0 0 0 0 1 0, 0, 0, 1: External event count mode (c) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (EVTT0 pin) (d) TMT0 counter read buffer register (TT0CNT) The count value of the 16-bit counter can be read by reading the TT0CNT register. (e) TMT0 capture/compare register 0 (TT0CCR0) If the TT0CCR0 register is set to D0, the count is cleared when the number of external events has reached (D0 + 1) and the compare match interrupt request signal (INTTT0CC0) is generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 433 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-16. Register Setting for Operation in External Event Count Mode (2/2) (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the external event count mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the register by the interrupt mask flag (TT0CCIC1.TT0CCMK1). Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the external event count mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 434 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) External event count mode operation flow Figure 8-17. Software Processing Flow in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TT0CE bit TT0CCR0 register D0 INTTT0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TT0CTL1 register, TT0IOC2 register, TT0CCR0, TT0CCR1 registers Initial setting of these registers is performed before setting the TT0CE bit to 1. TT0CE bit = 1 <2> Count operation stop flow TT0CE bit = 0 The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 435 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in external event count mode (a) Operation if TT0CCR0 register is set to 0000H When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value has matched that of the CCR0 buffer register. The value of the 16-bit counter is always 0000H. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register 0000H INTTT0CC0 signal INTTT0CC0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time the valid edge of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not set. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register FFFFH INTTT0CC0 signal External event count: 10000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 External event count: 10000H External event count: 10000H Page 436 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H When the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time it has detected the valid edge of the external event count signal. The counter is then cleared to 0000H in synchronization with the next count-up timing and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not set. If the TT0CCR1 register is set to 0000H, the INTTT0CC1 signal is generated when the 16-bit counter is cleared to 0000H. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register FFFFH INTTT0CC0 signal TT0CCR1 register 0000H INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 437 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting once and then change the set value. FFFFH D1 16-bit counter D1 D2 D2 D2 0000H TT0CE bit TT0CCR0 register D1 D2 INTTT0CC0 signal External event count (1): (D1 + 1) External event count (NG): External event (10000H + D2 + 1) count (2): (D2 + 1) If the value of the TT0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated. Therefore, the INTTT0CC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" as originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 438 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Operation of TT0CCR1 register Figure 8-18. Configuration of TT0CCR1 Register TT0CCR1 register CCR1 buffer register Match signal INTTT0CC1 signal Clear EVTT0 pin (external event count input) Edge detectorNote 16-bit counter Match signal TT0CE bit INTTT0CC0 signal CCR0 buffer register TT0CCR0 register Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. If the set value of the TT0CCR1 register is smaller than the set value of the TT0CCR0 register, the INTTT0CC1 signal is generated once per cycle. Figure 8-19. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TT0CE bit TT0CCR0 register D01 INTTT0CC0 signal TT0CCR1 register D11 INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 439 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the INTTT0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TT0CCR1 register do not match. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 8-20. Timing Chart When D01 < D11 FFFFH D01 D01 D01 D01 16-bit counter 0000H TT0CE bit TT0CCR0 register D01 INTTT0CC0 signal D11 TT0CCR1 register INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 L Page 440 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010) In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting, and outputs a PWM waveform from the TOT01 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has the set value of the TT0CCR0 register + 1 as half its cycle can also be output from the TOT00 pin. Figure 8-21. Configuration in External Trigger Pulse Output Mode Edge detectorNote 2 EVTT0 pinNote 1 (external trigger input/ external event count input) TT0CCR1 register Transfer Software trigger generation Edge detectorNote 3 Internal count clock Output S controller R (RS-FF) CCR1 buffer register Match signal Count clock selection TOT01 pin INTTT0CC1 signal Clear Count start control 16-bit counter Output controller Match signal TT0CE bit TOT00 pin INTTT0CC0 signal CCR0 buffer register Transfer TT0CCR0 register Notes 1. Since the external trigger input pin and external event count input pin are the same alternatefunction pin, the external event count input function cannot be used. 2. Edge detector for external trigger input. Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits. 3. Edge detector for external event count input. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 441 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-22. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 16-bit counter D1 D0 D0 D1 D1 D0 D1 0000H TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register D0 INTTT0CC0 signal TOT00 pin output D1 TT0CCR1 register INTTT0CC1 signal TOT01 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) 16-bit timer/event counter T waits for a trigger when the TT0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOT01 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOT00 pin is inverted. The TOT01 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TT0CCR1 register) x Count clock cycle Cycle = (Set value of TT0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1) The compare match request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input (EVTT0), or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used as the trigger (). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 442 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0EEE TT0CTL1 0 0/1 0 TT0MD3 0 0 TT0MD2 TT0MD1 TT0MD0 0 1 0 0, 0, 1, 0: External trigger pulse output mode Generates software trigger when 1 is written (c) TMT0 I/O control register 0 (TT0IOC0) TT0IOC0 0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 0/1 0/1 0/1 0/1 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level while waiting for external trigger 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level while waiting for external trigger 0: Low level 1: High level * When TT0OL1 bit = 0 * When TT0OL1 bit = 1 16-bit counter 16-bit counter TOT01 pin output TOT01 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 443 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (EVTT0 pin)Note Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the external trigger pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 444 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in external trigger pulse output mode Figure 8-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter D00 D10 D00 D10 D01 D01 D11 D10 D11 D00 D10 0000H TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTT0CC0 signal TOT00 pin output D10 TT0CCR1 register D10 D11 D10 CCR1 buffer register D10 D10 D11 D10 INTTT0CC1 signal TOT01 pin output <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <3> <4> <5> Page 445 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TT0CCR0, TT0CCR1 register setting change flow START Setting of TT0CCR1 register Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register TT0CE bit = 1 Initial setting of these registers is performed before setting the TT0CE bit to 1. Writing of the TT0CCR1 register must be performed when only the set duty factor is changed. When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. <4> TT0CCR0, TT0CCR1 register setting change flow The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting is enabled (TT0CE bit = 1). Trigger wait status. Setting of TT0CCR0 register When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. Setting of TT0CCR1 register <2> TT0CCR0 and TT0CCR1 register setting change flow Setting of TT0CCR0 register Setting of TT0CCR1 register <5> Count operation stop flow Writing the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register is necessary only when the set cycle is changed. When the counter is cleared after setting, the values of the TT0CCRn register are transferred to the CCRn buffer register in a batch. TT0CE bit = 0 Counting is stopped. STOP Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 446 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC0 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register CCR0 buffer register D00 D01 D00 D01 INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register D10 D10 D11 D11 INTTT0CC1 signal TOT01 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 447 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) In order to transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be set. After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer register may become undefined because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with writing the TT0CCRn register. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 448 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register D0 D0 D0 TT0CCR1 register 0000H 0000H 0000H Note Note Note Note INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output L Note The timing is actually delayed by one operating clock (fXX). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 449 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register D0 D0 D0 TT0CCR1 register D0 + 1 D0 + 1 D0 + 1 Note Note INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output Note The timing is actually delayed by one operating clock (fXX). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 450 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTT0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the TOT01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF D1 - 1 0000 0000 External trigger input (EVTT0 pin input) D1 CCR1 buffer register INTTT0CC1 signal TOT01 pin output Shortened If the trigger is detected immediately before the INTTT0CC1 signal is generated, the INTTT0CC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOT01 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter FFFF 0000 D1 - 2 0000 0001 D1 - 1 D1 External trigger input (EVTT0 pin input) CCR1 buffer register D1 INTTT0CC1 signal TOT01 pin output Extended R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 451 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTT0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up again from that point. Therefore, the active period of the TOT01 pin is extended by the time from generation of the INTTT0CC0 signal to trigger detection. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0000 External trigger input (EVTT0 pin input) D0 CCR0 buffer register INTTT0CC0 signal TOT01 pin output Extended If the trigger is detected immediately before the INTTT0CC0 signal is generated, the INTTT0CC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOT01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 External trigger input (EVTT0 pin input) CCR0 buffer register D0 INTTT0CC0 signal TOT01 pin output Shortened R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 452 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generating the INTTT0CC1 signal in the external trigger pulse output mode differs from the timing of generating INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter D1 - 2 D1 - 1 D1 TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 + 1 D1 + 2 D1 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is generated in synchronization with the next count-up, after the count value of the 16-bit counter matches the value of the TT0CCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing when the output signal of the TOT01 pin changes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 453 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.4 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting, and outputs a one-shot pulse from the TOT01 pin. Instead of the external trigger input (EVTT0), a software trigger can also be generated to output the pulse. When the software trigger is used, the TOT00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 8-25. Configuration in One-Shot Pulse Output Mode Edge detectorNote 2 EVTT0 pinNote 1 (external trigger input/ external event count input) TT0CCR1 register Transfer Software trigger generation Edge detectorNote 3 Internal count clock Output S controller R (RS-FF) CCR1 buffer register Match signal Count clock selection TOT01 pin INTTT0CC1 signal Clear Count start control Output S controller R (RS-FF) 16-bit counter Match signal TT0CE bit TOT00 pin INTTT0CC0 signal CCR0 buffer register Transfer TT0CCR0 register Notes 1 Edge detector for external trigger input. Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits. 2. Edge detector for external event count input. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 454 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-26. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 16-bit counter D1 D0 D1 D0 D1 0000H TT0CE bit External trigger input (EVTT0 pin input) D0 TT0CCR0 register INTTT0CC0 signal TOT00 pin output D1 TT0CCR1 register INTTT0CC1 signal TOT01 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Delay Active level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) When the TT0CE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOT01 pin. After the oneshot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger. When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TT0CCR1 register) x Count clock cycle Active level width = (Set value of TT0CCR0 register - Set value of TT0CCR1 register + 1) x Count clock cycle The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input (EVTT0 pin) or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used as the trigger. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 455 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-27. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stops counting 1: Enables counting (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0CTL1 0 0/1 TT0EEE 0 TT0MD3 0 0 TT0MD2 TT0MD1 TT0MD0 0 1 1 0, 0, 1, 1: One-shot pulse output mode Generates software trigger when 1 is written (c) TMT0 I/O control register 0 (TT0IOC0) TT0IOC0 0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 0/1 0/1 0/1 0/1 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level while waiting for external trigger 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level while waiting for external trigger 0: Low level 1: High level * When TT0OL1 bit = 0 * When TT0OL1 bit = 1 16-bit counter 16-bit counter TOT01 pin output TOT01 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 456 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-27. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (EVTT0 pin)Note Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 - D1 + 1) x Count clock cycle Output delay period = D1 x Count clock cycle Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the one-shot pulse output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 457 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in one-shot pulse output mode Figure 8-28. Software Processing Flow in One-Shot Pulse Output Mode FFFFH D00 16-bit counter D01 D10 D11 0000H TT0CE bit External trigger input (EVTT0 pin input) TT0CCR0 register D00 D01 D10 D11 INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal TOT01 pin output <1> <2> <1> Count operation start flow <3> Count operation stop flow TT0CE bit = 0 START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register TT0CE bit = 1 <3> Initial setting of these registers is performed before setting the TT0CE bit to 1. Count operation is stopped STOP The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). Trigger wait status <2> TT0CCR0, TT0CCR1 register setting change flow Setting of TT0CCR0, TT0CCR1 registers Remark As rewriting the TT0CCRn register immediately forwards to the CCRn buffer register, rewriting immediately after the generation of the INTTT0CC0 signal is recommended. n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 458 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TT0CCRn register If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. Remark n = 0, 1 FFFFH D00 16-bit counter D00 D10 D10 D00 D10 D01 D11 0000H TT0CE bit External trigger input (EVTT0 pin input) D00 TT0CCR0 register D01 INTTT0CC0 signal TOT00 pin output D10 TT0CCR1 register D11 INTTT0CC1 signal TOT01 pin output Delay (D10) Delay (D10) Active level width (D00 - D10 + 1) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) When the TT0CCR0 register is rewritten from D00 to D01 and the TT0CCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TT0CCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TT0CCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTT0CC1 signal and asserts the TOT01 pin. When the count value matches D01, the counter generates the INTTT0CC0 signal, deasserts the TOT01 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 459 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Generation timing of compare match interrupt request signal (INTTT0CC1) The generation timing of the INTTT0CC1 signal in the one-shot pulse output mode is different from INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter D1 - 2 D1 - 1 D1 TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 + 1 D1 + 2 D1 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is generated the next time the 16-bit counter counts up after its count value matches the value of the TT0CCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing the output signal of the TOT01 pin changes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 460 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.5 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) PWM output mode (TT0MD3 to TT0MD0 bits = 0100) In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. In addition, a square wave with the set value of the TT0CCR0 register + 1 as half its cycle is output from the TOT00 pin. Figure 8-29. Configuration in PWM Output Mode TT0CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal Internal count clock EVTT0 pin (external event count input) Edge detectorNote INTTT0CC1 signal Clear Count clock selection 16-bit counter Output controller Match signal TT0CE bit TOT01 pin TOT00 pin INTTT0CC0 signal CCR0 buffer register Transfer TT0CCR0 register Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 461 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-30. Basic Timing in PWM Output Mode FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TT0CE bit TT0CCR0 register CCR0 buffer register D00 D01 D00 D01 INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register D10 D11 D10 D11 INTTT0CC1 signal TOT01 pin output Active period Cycle (D10) (D00 + 1) Inactive period (D00 - D10 + 1) When the TT0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOT01 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TT0CCR1 register) x Count clock cycle Cycle = (Set value of TT0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1) The PWM waveform can be changed by rewriting the TT0CCRn register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 462 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-31. Setting of Registers in PWM Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) TT0MD3 TT0MD2 TT0MD1 TT0MD0 TT0EST TT0EEE TT0CTL1 0 0 0/1 0 0 1 0 0 0, 1, 0, 0: PWM output mode 0: Operates on count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts with external event count input signal (c) TMT0 I/O control register 0 (TT0IOC0) TT0IOC0 0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 0/1 0/1 0/1 0/1 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level * When TT0OL1 bit = 0 * When TT0OL1 bit = 1 16-bit counter 16-bit counter TOT01 pin output TOT01 pin output R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 463 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-31. Register Setting in PWM Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (EVTT0 pin). (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0CTL3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the PWM output mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 464 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in PWM output mode Figure 8-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D00 D01 D00 D10 D10 D01 D11 D11 D10 D00 D10 0000H TT0CE bit TT0CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTT0CC0 signal TOT00 pin output D10 TT0CCR1 register D10 D10 CCR1 buffer register D11 D10 D10 D11 D10 INTTT0CC1 signal TOT01 pin output <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <3> <4> <5> Page 465 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-32. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TT0CCR0, TT0CCR1 register setting change flow (duty only) START Setting of TT0CCR1 register Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register TT0CE bit = 1 Initial setting of these registers is performed before setting the TT0CE bit to 1. Only writing of the TT0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register n is transferred to the CCRn buffer register. <4> TT0CCR0, TT0CCR1 register setting change flow (cycle and duty) The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting is enabled (TT0CE bit = 1). Setting of TT0CCR0 register When the counter is cleared after setting, the values of compare register n are transferred to the CCRn buffer register in a batch. Setting of TT0CCR1 register <2> TT0CCR0, TT0CCR1 register setting change flow (cycle only) Setting of TT0CCR0 register Setting of TT0CCR1 register Remark <5> Count operation stop flow Writing the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. TT0CE bit = 0 Counting is stopped. STOP n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 466 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC1 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TT0CE bit TT0CCR0 register CCR0 buffer register TT0CCR1 register CCR1 buffer register D00 D01 D00 D10 D10 D01 D11 D11 TOT01 pin output INTTT0CC0 signal To transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be set. After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer register may become undefined because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with writing the TT0CCRn register. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 467 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TT0CE bit TT0CCR0 register D00 D00 D00 TT0CCR1 register 0000H 0000H 0000H Note Note Note Note INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output L Note The timing is actually delayed by one operating clock (fXX). To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TT0CE bit TT0CCR0 register D00 D00 D00 TT0CCR1 register D00 + 1 D00 + 1 D00 + 1 Note Note INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output Note The timing is actually delayed by one operating clock (fXX). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 468 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generation of the INTTT0CC1 signal in the PWM output mode differs from the timing of INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter D1 - 2 D1 - 1 D1 TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 + 1 D1 + 2 D1 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is generated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the TT0CCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing at which the output signal of the TOT01 pin changes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 469 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.6 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits. Figure 8-33. Configuration in Free-Running Timer Mode TT0CCR1 register (compare) TT0CCR0 register (capture) Output controller TOT01 pinNote 1 output Output controller TOT00 pinNote 1 output TT0CCS0, TT0CCS1 bits (capture/compare selection) Internal count clock EVTT0 pin (external event count input) Note 1 TIT00 pin (capture trigger input) TIT01 pinNote 1 (capture trigger input) Edge detectorNote 2 Count clock selection INTTT0OV signal 16-bit counter 0 TT0CE bit INTTT0CC1 signal 1 Edge detectorNote 3 0 TT0CCR0 register (capture) INTTT0CC0 signal 1 Edge detectorNote 4 TT0CCR1 register (compare) Notes 1. Because the capture trigger input pins (TIT00, TIT01) and timer output pins (TOT00, TOT01) are the same alternate-function pins, two functions cannot be used at the same time. 2. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. 3. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits. 4. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 470 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) * Compare operation When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. The TT0CCRn register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. Figure 8-34. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH D00 D00 D01 16-bit counter D10 D10 D11 D01 D11 D11 0000H TT0CE bit TT0CCR0 register D00 D01 INTTT0CC0 signal TOT00 pin output TT0CCR1 register D10 D11 INTTT0CC1 signal TOT01 pin output INTTT0OV signal TT0OVF bit Cleared to 0 by CLR instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Page 471 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) * Capture operation When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request signal (INTTT0CCn) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. Figure 8-35. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH D10 D00 16-bit counter D11 D12 D13 D01 D02 D03 0000H TT0CE bit TIT00 pin input TT0CCR0 register D00 D01 D02 D03 INTTT0CC0 signal TIT01 pin input TT0CCR1 register D10 D11 D12 D13 INTTT0CC1 signal INTTT0OV signal TT0OVF bit Cleared to 0 by CLR instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Page 472 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-36. Register Setting in Free-Running Timer Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 TT0CKS2 TT0CKS1 TT0CKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1 (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0EEE TT0CTL1 0 0 TT0MD3 TT0MD2 TT0MD1 TT0MD0 0/1 0 0 1 0 1 0, 1, 0, 1: Free-running timer mode 0: Operates with count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts on external event count input signal (c) TMT0 I/O control register 0 (TT0IOC0) TT0IOC0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 0/1 0/1 0/1 0/1 0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level (d) TMT0 I/O control register 1 (TT0IOC1) TT0IOC1 0 0 0 0 TT0IS3 TT0IS2 TT0IS1 TT0IS0 0/1 0/1 0/1 0/1 Select valid edge of TIT00 pin input Select valid edge of TIT01 pin input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 473 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-36. Register Setting in Free-Running Timer Mode (2/2) (e) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (EVTT0 pin) (f) TMT0 option register 0 (TT0OPT0) TT0CCS1 TT0CCS0 TT0OPT0 0 0 0/1 0/1 TT0OVF 0 0 0 0/1 Overflow flag Specifies if TT0CCR0 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TT0CCR1 register functions as capture or compare register 0: Compare register 1: Capture register (g) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (h) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1) These registers function as capture registers or compare registers depending on the setting of the TT0OPT0.TT0CCSn bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIT0n pin is detected. When the registers function as compare registers and when Da is set to the TT0CCRn register, the INTTT0CCn signal is generated when the counter reaches (Da + 1), and the output signals of the TOT00 and TOT01 pins are inverted. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 474 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 D00 D01 16-bit counter D10 D10 D11 D01 D11 D11 0000H TT0CE bit TT0CCR0 register D00 D01 INTTT0CC0 signal TOT00 pin output D10 TT0CCR1 register D11 INTTT0CC1 signal TOT01 pin output INTTT0OV signal TT0OVF bit <1> Cleared to 0 by CLR instruction <2> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <3> <2> Page 475 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0OPT0 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). TT0CE bit = 1 <2> Overflow flag clear flow Read TT0OPT0 register (check overflow flag). TT0OVF bit = 1 No Yes Execute instruction to clear TT0OVF bit (CLR TT0OVF). <3> Count operation stop flow TT0CE bit = 0 Counter is initialized and counting is stopped by clearing TT0CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 476 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) When using capture/compare register as capture register Figure 8-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D00 D11 D12 D01 16-bit counter D02 D03 0000H TT0CE bit TIT00 pin input TT0CCR0 register 0000 D00 D01 D02 D03 0000 INTTT0CC0 signal TIT01 pin input 0000 TT0CCR1 register D10 D11 D12 0000 INTTT0CC1 signal INTTT0OV signal TT0OVF bit <1> Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <2> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <3> <2> Page 477 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC1 register, TT0OPT0 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). TT0CE bit = 1 <2> Overflow flag clear flow Read TT0OPT0 register (check overflow flag). TT0OVF bit = 1 No Yes Execute instruction to clear TT0OVF bit (CLR TT0OVF). <3> Count operation stop flow TT0CE bit = 0 Counter is initialized and counting is stopped by clearing TT0CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 478 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTT0CCn signal has been detected. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TT0CE bit TT0CCR0 register D00 D01 D02 D03 D04 D05 INTTT0CC0 signal TOT00 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TT0CCR1 register D10 D11 D12 D13 D14 INTTT0CC1 signal TOT01 pin output Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TT0CCRn register must be re-set in the interrupt servicing that is executed when the INTTT0CCn signal is detected. The set value for re-setting the TT0CCRn register can be calculated by the following expression, where "Da" is the interval period. Compare register default value: Da - 1 Value set to compare register second and subsequent time: Previous set value + Da (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 479 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TT0CCRn register used as a capture register, software processing is necessary for reading the capture register each time the INTTT0CCn signal has been detected and for calculating an interval. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TT0CE bit TIT00 pin input TT0CCR0 register 0000H D00 D01 D02 D03 D04 INTTT0CC0 signal Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (10000H + (D02 - D01) (10000H + D01 - D00) D03 - D02) D04 - D03) TIT01 pin input TT0CCR1 register 0000H D10 D11 D12 D13 INTTT0CC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) INTTT0OV signal TT0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TT0CCRn register in synchronization with the INTTT0CCn signal, and calculating the difference between the read value and the previously read value. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 480 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH D11 D10 16-bit counter D01 D00 0000H TT0CE bit TIT00 pin input TT0CCR0 register D01 D00 TIT01 pin input D11 D10 TT0CCR1 register INTTT0OV signal TT0OVF bit <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TT0CCR0 register (setting of the default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of the default value of the TIT01 pin input). <3> Read the TT0CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TT0CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 481 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input D01 D00 TT0CCR0 register TT0OVF1 flagNote TIT01 pin input D11 D10 TT0CCR1 register <1> <2> <3> <4> <5> <6> Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software. <1> Read the TT0CCR0 register (setting of the default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of the default value of the TIT01 pin input). <3> An overflow occurs. Set the TT0OVF0 and TT0OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TT0CCR0 register. Read the TT0OVF0 flag. If the TT0OVF0 flag is 1, clear it to 0. Because the TT0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TT0CCR1 register. Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0 (the TT0OVF0 flag is cleared in <4>, and the TT0OVF1 flag remains 1). Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 482 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input D01 D00 TT0CCR0 register TT0OVF1 flagNote TIT01 pin input D11 D10 TT0CCR1 register <1> <2> <3> <4> <5> <6> Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software. <1> Read the TT0CCR0 register (setting of the default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of the default value of the TIT01 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TT0CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TT0OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TT0CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0. Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 483 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH Da0 16-bit counter Da1 0000H TT0CE bit TIT0n pin input TT0CCRn register Da0 Da1 INTTT0OV signal TT0OVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TT0CCRn register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Da1 - Da0) (incorrect). Actually, the pulse width must be (20000H + Da1 - Da0) because an overflow occurs twice. Remark n = 0, 1 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 484 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Example when capture trigger interval is long FFFFH Da0 16-bit counter Da1 0000H TT0CE bit TIT0n pin input TT0CCRn register Da0 Da1 INTTT0OV signal TT0OVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TT0CCRn register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Da1 - Da0). In this example, the pulse width is (20000H + Da1 - Da0) because an overflow occurs twice. Clear the overflow counter (0H). Remark n = 0, 1 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 485 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.7 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TT0CCRn register after a capture interrupt request signal (INTTT0CCn) occurs. As shown in Figure 8-39, select either the TIT00 or TIT01 pin as the capture trigger input pin and set the unused pins to "No edge detection" by using the TT0IOC1 register. Figure 8-39. Configuration in Pulse Width Measurement Mode Clear Internal count clock EVTT0 pin (external event count input) Edge detectorNote 1 Count clock selection 16-bit counter INTTT0OV signal INTTT0CC0 signal TT0CE bit TIT00 pin (capture trigger input) Edge detectorNote 2 TIT01 pin (capture trigger input) Edge detectorNote 3 INTTT0CC1 signal TT0CCR0 register (capture) TT0CCR1 register (capture) Notes 1. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. 2. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits. 3. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 486 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register 0000H D0 D1 D2 D3 INTTT0CCn signal INTTT0OV signal TT0OVF bit Remark Cleared to 0 by CLR instruction n = 0, 1 When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is later detected, the count value of the 16-bit counter is stored in the TT0CCRn register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTT0CCn) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIT0n pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTT0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TT0OVF bit set (1) count + Captured value) x Count clock cycle Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 487 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-41. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CTL0 0/1 TT0CKS2 TT0CKS1 TT0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stops counting 1: Enables counting Note Setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) TT0EST TT0EEE TT0CTL1 0 0 0/1 TT0MD3 TT0MD2 TT0MD1 TT0MD0 0 0 1 1 0 0, 1, 1, 0: Pulse width measurement mode 0: Operates with count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts on external event count input signal (c) TMT0 I/O control register 1 (TT0IOC1) TT0IOC1 0 0 0 0 TT0IS3 TT0IS2 TT0IS1 TT0IS0 0/1 0/1 0/1 0/1 Select valid edge of TIT00 pin input Select valid edge of TIT01 pin input (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (EVTT0 pin) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 488 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-41. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMT0 option register 0 (TT0OPT0) TT0CCS1 TT0CCS0 TT0OPT0 0 0 0 0 TT0OVF 0 0 0 0/1 Overflow flag (f) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (g) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIT00 and TIT01 pins is detected. Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the pulse width measurement mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 489 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in pulse width measurement mode Figure 8-42. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register 0000H D0 D1 D2 0000H INTTT0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits), TT0CTL1 register, TT0IOC1 register, TT0IOC2 register, TT0OPT0 register TT0CE bit = 1 Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). <2> Count operation stop flow TT0CE bit = 0 The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. STOP R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 490 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 491 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.8 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) In the triangular-wave PWM output mode, a triangular-wave PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. A PWM waveform that is inverted when the count value of the 16-bit counter matches the value of the CCR0 buffer register and when the 16-bit counter is set to 0000H is output from the TOT00 pin. Figure 8-43. Configuration in Triangular-Wave PWM Output Mode TT0CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal Internal count clock EVTT0 pin (external event count input) Edge detectorNote INTTT0CC1 signal Clear Count clock selection 16-bit counter Output controller Match signal TT0CE bit TOT01 pin TOT00 pin INTTT0CC0 signal CCR0 buffer register Transfer TT0CCR0 register Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 492 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-44. Basic Timing in Triangular-Wave PWM Output Mode FFFFH D02 D00 D01 16-bit counter D10 D11 D10 D12 D12 D11 0000H TT0CE bit TT0CCR0 register D00 CCR0 buffer register D01 D02 D00 D01 D02 INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register D10 D11 D10 D12 D11 D12 INTTT0CC1 signal TOT01 pin output INTTT0OV signal The 16-bit counter is cleared from FFFFH and 0000H and starts counting when the TT0CE bit is set to 1. The triangular PWM waveform is output from the TOT01 pin. In the triangular-wave PWM output mode, the counter counts up or down. When the 16-bit counter reaches 0000H while it is counting down, an overflow interrupt request signal (INTTT0OV) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1. If the count value of the 16-bit counter matches the value of the CCR0 buffer register while the counter is counting up, a compare match interrupt request signal (INTTT0CC0) is generated. The counting direction is changed from up to down when the value of the 16-bit counter matches that of the CCR0 buffer register, and from down to up when the counter is cleared to 0000H. The PWM waveform can be changed by rewriting the TT0CCRn register during operation. To change the PWM waveform during operation, write the TT0CCR1 register last. The cycle of the triangular PWM waveform is set by the TT0CCR0 register and its duty factor is set by the TT0CCR1 register. Set a value to the TT0CCR0 register in a range of "0 TT0CCR0 FFFEH". The rewritten value is reflected when the 16-bit counter reaches 0000H while it is counting down. Even when changing only the cycle of the PWM waveform, first set a period to the TT0CCR0 register, and then write the same value (value same as that set to the TT0CCR1 register) to the TT0CCR1 register. To transfer data from the TT0CCRn register to the CCRn buffer register, the data must be written to the TT0CCR1 register (n = 0, 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 493 of 1442 V850ES/JC3-H, V850ES/JE3-H 8.6.9 CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Encoder count function The encoder count function includes an encoder compare mode (see 8.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)). Mode Encoder compare mode TT0CCR0 Register Compare only TT0CCR1 Register Compare only (1) Count-up/-down control Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits. When the encoder count function is used, the internal count clock and external event count input (EVTT0) cannot be used. Set the TT0CTL0.TT0CKS2 to TT0CTL0.TT0CKS0 bits to 000 and the TT0CTL1.TT0EEE bit to 0. (2) Setting initial value of 16-bit counter The initial count value set to the TT0TCW register when the TT0CTL2.TT0ECC bit = 0 is transferred to the 16-bit counter immediately after the counter starts its operation (TT0CTL0.TT0CE bit = 0 1), and the counter starts the operation after it detects the valid edge of the encoder input signal (TENC00 or TENC01). (3) Basic operation The TT0CCRn register generates a compare match interrupt request signal (INTTT0CCn) when the count value of the 16-bit counter matches the value of the CCRn buffer register. (4) Clear operation The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode. * When the value of the 16-bit counter matches the value of the compare register (the TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits are set) * When the edge of the encoder clear input signal (TECR0) is detected (the TT0ECS1 and TT0ECS0 bits are set when the TT0IOC3.TT0SCE bit = 0) * When the clear level condition of the TENC00, TENC01, and TECR0 pins is detected (the TT0ZCL, TT0BCL, and TT0ACL bits are set when the TT0SCE bit = 1) Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 494 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (5) Controlling bits of TT0CTL2 register The setting of the TT0CTL2 register in the encoder compare mode is shown below. Table 8-8. Setting of TT0CTL2 Register Mode TT0UDS1, TT0ECM1 Bit TT0ECM0 Bit TT0LDE Bit Counter Clear Transfer to TT0UDS0 Bits (<2>) (<2>) (<3>) (Target Compare Counter (<1>) Encoder compare mode Can be set to 00, Register) 0 0 - 0 01, 10, or 11. 1 0 1 Possible TT0CCR0 - Note 1 1 - Possible 0 Invalid TT0CCR1 - 1 Invalid TT0CCR0, - TT0CCR1 Note The counter can operate in a range from 0000H to the set value of the TT0CCR0 register. (a) Outline of each bit <1> The TT0UDS1 and TT0UDS0 bits identify the counting direction (up or down) of the 16-bit counter by the phase input from the encoder input pin (TENC00 or TENC01). <2> The TT0ECM1 and TT0ECM0 bits control clearing of the 16-bit counter when its count value matches the value of the CCR0 or CCR1 buffer register. <3> The TT0LDE bit controls a function to transfer the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits are 00 and 01, respectively. It is invalid when these bits are set to any other values. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 495 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Detailed explanation of each bit <1> TT0UDS1 and TT0UDS0 bits: Count-up/-down selection Whether the 16-bit counter is counting up or down is identified by the phase input from the TENC00 or TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits. These bits are valid only in the encoder compare mode. * When TT0UDS1 and TT0UDS0 bits = 00 TENC00 Pin TENC01 Pin Rising edge Count Operation High level Count down Low level Count up Falling edge Both edges Rising edge Falling edge Both edges Remark Detecting the edge of the TENC00 pin is specified by the TT0IOC3.TT0EIS1 and TT0EIS0 bits. Figure 8-45. Operation Example (When Valid Edge of TENC00 Pin Is Specified to Be Rising Edge and No Edge Is Specified as Valid Edge of TENC01 Pin) TENC00 TENC01 16-bit counter 0007H 0006H 0005H Count down R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0004H 0005H 0006H 0007H Count up Page 496 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) * When TT0UDS1 and TT0UDS0 bits = 01 TENC00 Pin TENC01 Pin Low level Count Operation Count down Rising edge Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge High level Count up Falling edge Both edges Rising edge Low level Falling edge Both edges Counter does not perform count Simultaneous input to TENC00 and TENC01 pins operation but holds value immediately before. Remark Detecting the edges of the TENC00 and TENC01 pins is specified by the TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits. Figure 8-46. Operation Example (When Rising Edge Is Specified as Valid Edges of TENC00 and TENC01 Pins) TENC00 TENC01 16-bit counter 0006H 0007H Count up R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0008H Value held 0007H 0006H 0005H Count down Page 497 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) * When TT0UDS1 and TT0UDS0 bits = 10 TENC00 Pin TENC01 Pin Low level Falling edge Count Operation Counter does not perform count operation but holds value immediately before. Rising edge Low level Count down High level Rising edge Counter does not perform count Falling edge High level operation but holds value immediately before. Rising edge High level Falling edge Falling edge Low level Count up Low level Rising edge Counter does not perform count operation but holds value immediately Rising edge before. Falling edge Falling edge Rising edge Count down Falling edge Caution Count up Specification of the valid edges of the TENC00 and TENC01 pins is invalid. Figure 8-47. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap) TENC00 TENC01 16-bit counter 0007H 0006H 0005H 0006H 0005H 0006H 0005H 0006H Count down Count Count Count Count up down up down 0007H Count up Figure 8-48. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap) TENC00 TENC01 16-bit counter 0007H Count down R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0006H Value held 0005H 0006H Count down 0007H Count up Page 498 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) * When TT0UDS1 and TT0UDS0 bits = 11 TENC00 Pin TENC01 Pin Low level Falling edge Rising edge Low level High level Rising edge Falling edge High level Count Operation Count down Rising edge Count up High level Falling edge Falling edge Low level Low level Rising edge Counter does not perform count Simultaneous input to TENC00 and TENC01 pins operation but holds value immediately before. Caution Specification of the valid edges of the TENC00 and TENC01 pins is invalid. Figure 8-49. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap) TENC00 TENC01 16-bit counter 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH Count up 0009H 0008H 0007H 0006H 0005H Count down Figure 8-50. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap) TENC00 TENC01 16-bit counter 0003H 0004H Count up R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0005H Value held 0006H 0007H 0008H Count up 0007H 0006H Count down 0005H 0006H Value Count held up Page 499 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) <2> TT0ECM1 and TT0ECM0 bits: Timer/counter clear function upon match of the compare register The 16-bit counter performs its count operation in accordance with the set value of the TT0ECM1 and TT0ECM0 bits when the count value of the counter matches the value of the CCRn buffer register. * When TT0ECM1 and TT0ECM0 bits = 00 The 16-bit counter is not cleared when its count value matches the value of the CCRn buffer register. * When TT0ECM1 and TT0ECM0 bits = 01 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR0 buffer register. Next Count Operation Description Count up 16-bit counter is cleared to 0000H. Count down Count value of 16-bit counter is counted down. * When TT0ECM1 and TT0ECM0 bits = 10 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR1 buffer register. Next Count Operation Description Count up Count value of 16-bit counter is counted up. Count down 16-bit counter is cleared to 0000H. * When TT0ECM1 and TT0ECM0 bits = 11 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR0 buffer register. Next Count Operation Description Count up 16-bit counter is cleared to 0000H. Count down Count value of 16-bit counter is counted down. The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR1 buffer register. Next Count Operation Description Count up Count value of 16-bit counter is counted up. Count down 16-bit counter is cleared to 0000H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 500 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) <3> TT0LDE bit: Transfer function of the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows When the TT0LDE bit = 1, the set value of the TT0CCR0 register can be transferred to the 16-bit counter when the counter underflows. The TT0LDE bit is valid only in the encoder compare mode. * Count operation in range from 0000H to set value of the TT0CCR0 register If the 16-bit counter performs a count operation when the TT0LDE bit = 1 and TT0ECM1 and TT0ECM0 bits = 01, and when the count value of the counter matches the set value of the CCR0 buffer register when the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is counting up. If the 16-bit counter underflows when the TT0LDE bit = 1, the set value of the TT0CCR0 register is transferred to the counter. Therefore, the counter can operate in a range from 0000H to the set value of the TT0CCR0 register in which the upper-limit count value is the set value of the TT0CCR0 register and the lower-limit value is 0000H. Figure 8-51. Operation Example (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register) Count value of 16-bit counter matches value of CCR0 buffer register. Set value of TT0CCR0 register is transferred to 16-bit counter. Set value of TT0CCR0 register (N) 16-bit counter 0000H 16-bit counter is cleared to 0000H. Count up R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 16-bit counter underflows. Count down Page 501 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-52. Operation Timing (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register) Peripheral clock Count timing signal TT0ESF bit H = down counting 0002H TT0CNT register 0001H 0000H N N-1 N TT0CCR0 register INTTT0CC0 signal TT0EOF bit L TT0EUF bit INTTT0OV signal Remark TT0ESF bit: Bit 0 of TMT0 option register 1 (TT0OPT1) TT0EOF bit: Bit 1 of TMT0 option register 1 (TT0OPT1) TT0EUF bit: Bit 2 of TMT0 option register 1 (TT0OPT1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 502 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin) The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by the TT0IOC3.TT0SCE bit. The TT0SCE bit also controls, depending on its setting, the TT0IOC3.TT0ZCL, TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits. The counter can be cleared by the methods described below only in the encoder compare mode. Table 8-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits Clearing Method TT0SCE Bit TT0ZCL Bit TT0BCL Bit TT0ACL Bit TT0ECS1, TT0ECS0 Bits <1> 0 Invalid Invalid Invalid Valid <2> 1 Valid Valid Valid Invalid (a) Clearing method <1>: By detecting edge of encoder clear signal (TECR0 pin) (TT0SCE bit = 0) When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral clock if the valid edge of the TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected. At this time, an encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the settings of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid. Figure 8-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and TT0UDS0 Bits = 11) Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Peripheral clock TT0CNT register N N+1 0000H 0001H 0002H Count timing signal INTTT0EC interrupt Counter clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 503 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins (TT0SCE bit = 1) When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0, TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the encoder clear interrupt request signal (INTTT0EC) is not generated. The settings of the TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1. Table 8-10. 16-bit Counter Clearing Condition When TT0SCE Bit = 1 Clear Level Condition Setting Input Level of Encoder Pin TT0ZCL Bit TT0BCL Bit TT0ACL Bit TECR0 Pin TENC01 Pin TENC00 Pin 0 0 0 L L L 0 0 1 L L H Caution 0 1 0 L H L 0 1 1 L H H 1 0 0 H L L 1 0 1 H L H 1 1 0 H H L 1 1 1 H H H The 16-bit counter is cleared to 0000H when the clear level condition of the TT0ZCL, TT0BCL, and TT0ACL bits match the input level of the TECR0, TENC01, or TENC00 pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 504 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3) (i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up. Encoder input (TENC00 pin input) H Encoder input (TENC01 pin input) L Encoder clear input (TECR0 pin input) H Peripheral clock Clear signal TT0CNT register N N+1 0000H Count timing signal N + 1 (when TT0CCR0 register is set to N + 1) TT0CCR0 register INTTT0CC0 signal Compare match interrupt request signal is not generated. TT0CCR1 register 0000H (when TT0CCR1 register is set to 0000H) INTTT0CC1 signal TT0CCR0 register N (when TT0CCR0 register is set to N) INTTT0CC0 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 505 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3) (ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin while the counter is counting up, the counter is cleared without counting up. Encoder input (TENC00 pin input) H Encoder input (TENC01 pin input) L Encoder clear input (TECR0 pin input) H Peripheral clock Clear signal TT0CNT register N 0000H Count timing signal (iii) If the high level is input to the TECR0 pin earlier than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared without counting up. Encoder input (TENC00 pin input) H Encoder input (TENC01 pin input) L Encoder clear input (TECR0 pin input) H Peripheral clock Clear signal TT0CNT register N 0000H Count timing signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 506 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (3/3) (iv) If the high level is input to the TECR0 pin later than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up. Encoder input (TENC00 pin input) H Encoder input (TENC01 pin input) L Encoder clear input (TECR0 pin input) H Peripheral clock Clear signal TT0CNT register N N-1 0000H Count timing signal N - 1 (when TT0CCR0 register is set to N - 1) TT0CCR0 register INTTT0CC0 signal Compare match interrupt request signal is not generated. TT0CCR1 register 0000H (when TT0CCR1 register is set to 0000H) INTTT0CC1 signal TT0CCR0 register N (when TT0CCR0 register is set to N) INTTT0CC0 signal If the counter is cleared in this way, a miscount does not occur even if inputting the signal to the TECR0 pin is late, because the clear level condition of the TECR0, TENC01, and TENC00 pins is set and the 16-bit counter is cleared to 0000H when the clear level condition is detected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 507 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (7) Notes on using encoder count function (a) If compare match interrupt is not generated immediately after operation is started If a value which is the same as that of the TT0TCW register is set to the TT0CCR0 or TT0CCR1 register and the counter operation is started when the TT0CTL2.TT0ECC bit = 0, and if the count value (TT0TCW) of the 16-bit counter matches the value of the CCRn buffer register immediately after the start of the operation, the match is masked and the compare match interrupt request signal (INTTT0CCn) is not generated (n = 0, 1). In addition, the 16-bit counter is not cleared to 0000H by setting the TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits. Count clock TT0CE bit Peripheral clock Count timing signal Count up/down signal TT0CNT register H = Count down FFFFH TT0CCR1 register INTTT0CC1 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 16-bit counter is not cleared. TT0TCW TT0TCW - 1 TT0TCW Match does not occur. Page 508 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) If overflow does not occur immediately after start of operation If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its count value that has been held is FFFFH and if the next count operation is counting up. After the counter starts operating and counts up from a count value (value of TT0TCW register = FFFFH), the counter overflows from FFFFH to 0000H. However, detection of the overflow is masked, the overflow flag (TT0EOF) is not set, and the overflow interrupt request signal (INTTT0OV) is not generated. Count clock TT0CE bit Peripheral clock Count timing signal Count up/down signal L = Count up TT0ECC bit H TT0CNT register Hold FFFFH TT0TCW register INTTT0OV signal TT0TCW = FFFFH 0000H FFFFH Overflow does not occur. TT0EOF bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 509 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0). In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count value of the counter matches the value of the CCRn buffer register (compare match interrupt request signal (INTTT0CCn) is generated), when the edge of the encoder clear input (TECR0 pin) is detected, and when the clear level condition of TENC00, TENC01, and TECR0 pins is detected. When the 16-bit counter underflows, the set value of the TT0CCR0 register can be transferred to the counter. (1) Encoder compare mode operation flow Figure 8-55. Encoder Compare Mode Operation Flow START Register initial setting TT0CTL1 register (TT0MD3 to TT0MD0 bits), TT0CTL2 register (TT0LDE, TT0ECM1, TT0ECM0, TT0UDS1, TT0UDS0 bits), TT0IOC3 register (TT0SCE, TT0ZCL, TT0ACL, TT0BCL, TT0ECS1, TT0ECS0, TT0EIS1, TT0EIS0 bits), TT0CCR0, TT0CCR1 registers, TT0TCW register TT0CE bit = 1 Encoder compare mode operation processing Operation end? : See Figure 9-56 Encoder Compare Mode Operation Processing. No Yes TT0CE bit = 0 END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 510 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-56. Encoder Compare Mode Operation Processing A Valid edge of TENC00, TENC01 detected? No Yes Count down Which count operation? Count up TT0ECM0 = 1? (TT0CTL2) No Yes Count value matches CCR0 register value? TT0ECM1 = 1? (TT0CTL2) No Yes No Yes Count value matches CCR1 register value? No Yes 16-bit counter cleared and started. INTTT0CC0 signal generated. 16-bit counter cleared and started. INTTT0CC1 signal generated. TT0LDE = 1? (TT0CTL2) No Yes Underflow? No Yes TT0CCR0 set value transferred to 16-bit counter. INTTT0CC0 signal generated. TT0SCE = 1? (TT0IOC3) No Yes Clear level condition of TENC00, TENC01, and TECR0 pins detected? Yes 16-bit counter cleared and started. No TECR0 edge detected? No Yes 16-bit counter cleared and started. INTTIEC0 signal generated. A R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 511 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Encoder compare mode operation timing (a) Basic timing 1 [Register setting conditions] * TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01 The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register. * TT0CTL2.TT0LDE bit = 1 The set value of the TT0CCR0 register is transferred to the 16-bit counter when it overflows. * TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) FFFFH CM01 TT0CNT register CM12 CM00 CM00 CM02 CM03 CM03 Clear Transfer CM11 Clear 0000H TT0CCR0 register CCR0 buffer register CM00 CM01 CM00 CM01 CM02 Clear CM03 CM02 CM03 INTTT0CC0 signal TT0CCR1 register CCR1 buffer register CM10 CM10 CM11 CM11 CM12 CM12 INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit L TT0EUF bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 512 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 1), the set value of the TT0TCW register is transferred to the counter and the 16-bit counter starts operating. When the count value of the counter matches the value of the CCR0 buffer register, the compare match interrupt request signal (INTTT0CC0) is generated. Because the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is counting up. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the compare match interrupt request signal (INTTT0CC1) is generated. Because the TT0ECM1 bit = 0, the 16-bit counter is not cleared to 0000H when its value matches that of the CCR1 buffer register. When the TT0LDE bit = 1 and TT0ECM0 bit = 1, the counter can operate in a range from 0000H to the set value of the TT0CCR0 register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 513 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Basic timing 2 [Register setting condition] * TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00 The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a = 0, 1). * TT0CTL2.TT0LDE bit = 0 The set value of the TT0CCR0 register is not transferred to the 16-bit counter after the counter underflows. * TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) Underflow FFFFH Overflow CM10 CM02 CM12 TT0CNT register CM01 CM00 CM00 CM01 CM11 0000H TT0CCR0 register CCR0 buffer register CM00 CM01 CM00 CM02 CM01 CM02 INTTT0CC0 signal TT0CCR1 register CCR1 buffer register CM10 CM10 CM11 CM11 CM12 CM12 INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit TT0EUF bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 514 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. The 16-bit counter is not cleared to 0000H even when its count value matches the value of the CCRn buffer register because the TT0ECM1 and TT0ECM0 bits = 00 (n = 0, 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 515 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Basic timing 3 [Register setting condition] * TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11 The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0 buffer register. The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR1 buffer register. * Setting of the TT0CTL2.TT0LDE bit is invalid. * TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) Underflow FFFFH Underflow Overflow Underflow CM01 CM01 CM02 TT0CNT register CM11 CM00 CM10 Clear Clear Clear CM12 Clear 0000H TT0CCR0 register CCR0 buffer register CM12 CM00 CM01 CM00 CM02 CM01 CM02 INTTT0CC0 signal TT0CCR1 register CCR1 buffer register CM10 CM10 CM11 CM11 CM12 CM12 INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit TT0EUF bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 516 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. At this time, the 16-bit counter is cleared to 0000H if the next count operation is counting up. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. At this time, the 16-bit counter is cleared to 0000H if the next count operation is counting down. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 517 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) The V850ES/JC3-H and V850ES/JE3-H have four TMM channels (TMMn). 9.1 Overview TMMn has the following features. * Interval function * 8 clocks selectable * 16-bit counter x 1 (Not available to counter lead in timer count operation.) * Compare register x 1 (Not available to write compare register in timer count operation.) * Compare match interrupt x 1 TMMn supports only the clear & start mode. The free-running timer mode is not supported. Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 518 of 1442 V850ES/JC3-H, V850ES/JE3-H 9.2 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMMn includes the following hardware. Table 9-1. Configuration of TMMn Item Configuration Timer register 16-bit counter Register TMMn compare register 0 (TMnCMP0) Control register TMMn control register 0 (TMnCTL0) Figure 9-1. Block Diagram of TMMn Internal bus TMnCTL0 TMnCE TMnCKS2 TMnCKS1TMnCKS0 TMnCMP0 Match Selector Note fXX/2 fXX/4 fXX/8 fXX/16 fXX/64 fXX/256 fXX/512 fXX/1024 Controller 16-bit counter INTTMnEQ0 Clear Note In case of TMM0, fXX, fXX/2, fXX/4, fXX/64, fXX/512, fXX/1024, fR, fXT Remark fXX: Main clock frequency fR: Internal oscillation clock frequency fXT: Subclock frequency n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 519 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMMn compare register 0 (TMnCMP0) The TMnCMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Software can be used to always write the same value to the TMnCMP0 register. Rewriting the TMnCMP0 register is prohibited when the TMnCTL0.TMnCE bit = 1. After reset: 0000H R/W Address: TM0CMP0 FFFFFA84H, TM1CMP0 FFFFFA94H, TM2CMP0 FFFFFAA4H, TM3CMP0 FFFFFAB4H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMnCMP0 (n = 0 to 3) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 520 of 1442 V850ES/JC3-H, V850ES/JE3-H 9.3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Registers (1) TMMn control register (TMnCTL0) The TMnCTL0 register is an 8-bit register that controls the TMMn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TMnCTL0 register. Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 521 of 1442 V850ES/JC3-H, V850ES/JE3-H After reset: 00H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) R/W Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H, TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H 6 <7> TMnCTL0 TMnCE 5 0 4 0 3 0 2 0 1 0 TMnCKS2 TMnCKS1 TMnCKS0 (n = 0 to 3) TMnCE Internal clock operation enable/disable specification 0 TMMn operation disabled (16-bit counter reset asynchronously). Operation clock application stopped. 1 TMMn operation enabled. Operation clock application started. TMMn operation started. Internal clock control and internal circuit reset for TMMn are performed asynchronously using the TMnCE bit. When the TMnCE bit is cleared to 0, the internal clock of TMMn is disabled (fixed to low level) and 16-bit counter is reset asynchronously. (m = 0) TMmCKS2 TMmCKS1 TMmCKS0 Count clock selection fXX = 48 MHz fXX = 32 MHz fXX = 24 MHz 0 0 0 fXX 20.8 ns 31.3 ns 41.7 ns 0 0 1 fXX/2 41.7 ns 62.5 ns 83.3 ns 0 1 0 fXX/4 83.3 ns 125 ns 167 ns 0 1 1 fXX/64 1.33 s 2.00 s 2.67 s 1 0 0 fXX/512 10.7 s 16.0 s 21.3 s 1 0 1 fXX/1024 21.3 s 32.0 s 42.7 s 1 1 0 fR/8 36.4 s 36.4 s 36.4 s 1 1 1 fXT 30.5 s 30.5 s 30.5 s (m = 1 to 3) TMmCKS2 TMmCKS1 TMmCKS0 Count clock selection fXX = 48 MHz fXX = 32 MHz fXX = 24 MHz 0 0 0 fXX/2 41.7 ns 62.5 ns 83.3 ns 0 0 1 fXX/4 83.3 ns 125 ns 167 ns 0 1 0 fXX/8 167 ns 250 ns 333 ns 0 1 1 fXX/16 333 ns 500 ns 667 ns 1 0 0 fXX/64 1.33 s 2.00 s 2.67 s 1 0 1 fXX/256 5.33 s 8.00 s 10.7 s 1 1 0 fXX/512 10.7 s 16.0 s 21.3 s 1 1 1 fXX/1024 21.3 s 32.0 s 42.7 s Cautions 1. Set the TMnCKS2 to TMnCKS0 bits when the TMnCE bit = 0. When changing the value of TMnCE from 0 to 1, it is not possible to set the value of the TMnCKS2 to TMnCKS0 bits simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency fR: Internal oscillation clock frequency fXT: Subclock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 522 of 1442 V850ES/JC3-H, V850ES/JE3-H 9.4 Operation Caution 9.4.1 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Do not set the TMnCMP0 register to FFFFH. Interval timer mode In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval if the TMnCTL0.TMnCE bit is set to 1. Figure 9-2. Configuration of Interval Timer Clear Count clock selection INTTMnEQ0 signal 16-bit counter Match signal TMnCE bit Remark TMnCMP0 register n = 0 to 3 Figure 9-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D D D D 0000H TMnCE bit TMnCMP0 register D INTTMnEQ0 signal Interval (D + 1) Remark Interval (D + 1) Interval (D + 1) Interval (D + 1) n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 523 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TMnCMP0 register, the 16-bit counter is cleared to 0000H and a compare match interrupt request signal (INTTMnEQ0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TMnCMP0 register + 1) x Count clock cycle Figure 9-4. Register Setting for Interval Timer Mode Operation (a) TMMn control register 0 (TMnCTL0) TMnCE TMnCTL0 0/1 TMnCKS2 TMnCKS1 TMnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMMn compare register 0 (TMnCMP0) If the TMnCMP0 register is set to D, the interval is as follows. Interval = (D + 1) x Count clock cycle Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 524 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH D 16-bit counter D D 0000H TMnCE bit TMnCMP0 register D INTTMnEQ0 signal <1> <2> <1> Count operation start flow START Register initial setting TMnCTL0 register (TMnCKS0 to TMnCKS2 bits) TMnCMP0 register TMnCE bit = 1 The initial setting of these registers is performed before setting the TMnCE bit to 1. The TMnCKS0 to TMnCKS2 bits cannot be set at the same time when counting has been started (TMnCE bit = 1). <2> Count operation stop flow TMnCE bit = 0 The counter is initialized and counting is stopped by clearing the TMnCE bit to 0. STOP Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 525 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TMnCMP0 register to FFFFH. (a) Operation if TMnCMP0 register is set to 0000H If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TMnCE bit TMnCMP0 register 0000H INTTMnEQ0 signal Interval time Count clock cycle Remark Interval time Count clock cycle n = 0 to 3 (b) Operation if TMnCMP0 register is set to N If the TMnCMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in synchronization with the next count-up timing and the INTTMnEQ0 signal is generated. FFFFH N 16-bit counter 0000H TMnCE bit TMnCMP0 register N INTTMnEQ0 signal Interval time (N + 1) x count clock cycle Remark Interval time (N + 1) x count clock cycle Interval time (N + 1) x count clock cycle n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 526 of 1442 V850ES/JC3-H, V850ES/JE3-H 9.4.2 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1, depending on the count clock selected. (n = 0) Selected Count Clock Maximum Time Before Counting Start fXX 2/fXX fXX/2 3/fXX fXX/4 6/fXX fXX/64 128/fXX fXX/512 1024/fXX fXX/1024 2048/fXX fR/8 16/fR fXT 2/fXT (n = 1 to 3) Selected Count Clock Maximum Time Before Counting Start fXX/2 4/fXX fXX/4 6/fXX fXX/8 12/fXX fXX16 32/fXX fXX/64 128/fXX fXX/256 512/fXX fXX/512 1024/fXX fXX/1024 2048/fXX (2) Rewriting the TMnCMP0 and TMnCTL0 registers is prohibited while TMMn is operating. If these registers are rewritten while the TMnCE bit is 1, the operation cannot be guaranteed. If they are rewritten by mistake, clear the TMnCTL0.TMnCE bit to 0, and re-set the registers. Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 527 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.1 Functional Overview Timer AB1 (TAB1) and the TMQ0 option (TMQOP0) can be used as an inverter function that controls a motor. It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when the value of TAB1 matches the value of TAA4. The following operations can be performed as motor control functions. * 6-phase PWM output function with 16-bit resolution (with dead-timer, for upper and lower arms) * Timer tuning operation function (tunable with TAA4) * Cycle setting function (cycle can be changed during operation of crest or valley interrupt) * Compare register rewriting: Anytime rewrite, batch rewrite, or intermittent rewrite (selectable during TAB1 operation) * Interrupt and transfer culling functions * Dead-time setting function * A/D trigger timing function of the A/D converter (four types of timing can be generated) * 0% output and 100% output available * 0% output and 100% output selectable by crest interrupt and valley interrupt * Forcible output stop function * When valid edge detected by external pin input (INTP09/TOAB1OFF, INTP16/TOAA1OFF) * When main clock oscillation stop detected by clock monitor function R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 528 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.2 Configuration The motor control function consists of the following hardware. Item Configuration Timer register Dead-time counters Compare register TAB1 dead-time compare register (TAB1DTC register) Control registers TAB1 option register 1 (TAB1OPT1) TAB1 option register 2 (TAB1OPT2) TAB1 I/O control register 3 (TAB1IOC3) High-impedance output control register 0 (HZA0CTL0) High-impedance output control register 1 (HZA0CTL1) * 6-phase PWM output can be produced with dead time by using the output of TAB1 (TOAB11, TOAB12, TOAB13). * The output level of the 6-phase PWM output can be set individually. * The 16-bit timer/counter of TAB1 counts up/down triangular waves. When the timer/counter underflows and when a cycle match occurs, an interrupt is generated. Interrupt generation, however, can be suppressed up to 31 times. * TAA4 can execute counting at the same time as TAB1 (timer tuning operation function). TAA4 can be set in three ways as it can generate an A/D trigger source (TABTADT0) and two types of interrupts: a TAB1 underflow interrupt (INTTAB1OV) and a cycle match interrupt (INTTAB1CC0). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 529 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-1. Block Diagram of Motor Control TOAB10 TAB1 * Carrier * 3-phase PWM generation TAA4 * A/D trigger generation in synchronization with TAB1 TOAB1T1 TMQ option * 6-phase PWM generation with dead time from 3-phase PWM * Culling control * A/D trigger selection TOAB1B1 TOAB1T2 TOAB1B2 TOAB1T3 TAA1 TOAB1B3 * PWM generation TOAA11 High-impedance output controller Crest interrupt (INTTAB1CC0) INTC * Interrupt control Valley interrupt (INTTAB1OV) Noise elimination INTP16/TOAB1OFF Noise elimination INTP09/TOAA1OFF A/D trigger of A/D converter Edge detection Edge detection R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 530 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-2. TMQ1 Option Internal bus TOAB10 TABnDTC (10-bit dead-time value) TAB1 Channel 1 TOAB10 TOAB11Note (internal signal) Clear Edge detection Dead-time counter 1 (10 bits) High-impedance output controller Positive phase F/F Level control Active setting Output control Negative phase F/F Level control Active setting Output control TOAB1T1 TOAB1B1 TOAB1T2 Channel 2 TOAB12Note (internal signal) TOAB13Note (internal signal) TOAB1B2 TOAB1T3 Channel 3 TOAB1B3 Interrupt culling circuit INTC INTTAB1OV_BASE INTTAB1OV INTTAB1CC0 Counter Mask control Mask count buffer Crest/valley interrupt selection Culling enable Number of masks TABTICCn0 TABTIOVn A/D trigger generator 1 A/D converter A/D trigger selection (TAB1OPT2 register) Up/down selection TAA4 TABTADT0 INTTAA4CC0 INTTAA4CC1 Note TOAB10, TOAB12, and TOAB13 function alternately as output pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 531 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (1) TAB1 dead-time compare register (TAB1DTC) The TAB1DTC register is a 10-bit compare register that specifies the dead-time value. Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution When generating a dead-time period, set the TAB1DTC register to 1 or higher. Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are in their default states. Therefore, for the protection of the system, take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. When a dead-time period is not needed, set the TAB1DTC register to 0. After reset: 0000H R/W 10 15 TAB1DTC Address: FFFFF584H 000000 9 0 TAB1DTC9 to TAB1DTC0 (2) Dead-time counters 1 to 3 The dead-time counters are 10-bit counters that count dead time. These counters are cleared or count up at the rising or falling edge of the TOAB1m output signal of TAB1, and are cleared or stopped when their count value matches the value of the TAB1DTC register. The count clock of these counters is the same as that set by the TAB1CTL0.TAB1CKS2 to TAB1CTL0.TAB1CKS0 bits of TAB1. Remarks 1. The operation differs when the TAB1OPT2.TAB1DTM bit = 1. For details, see 10.4.2 (4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1). 2. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 532 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.3 Control Registers (1) TAB1 option register 1 (TAB1OPT1) The TAB1OPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer Q option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. Two rewrite modes (batch write mode and anytime write mode) can be selected, depending on the setting of the TAB1OPT0.TAB1CMS bit. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W <7> <6> TAB1OPT1 Address: FFFFF580H 5 4 3 2 1 0 TAB1ICE TAB1IOE 0 TAB1ID4 TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0 TAB1ICE Crest interrupt (INTTAB1CC0 signal) enable 0 Do not use INTTAB1CC0 signal (do not use it as count signal for interrupt culling). 1 Use INTTAB1CC0 signal (use it as count signal for interrupt culling). TAB1IOE Valley interrupt (INTTAB1OV signal) enable 0 Do not use INTTAB1OV signal (do not use it as count signal for interrupt culling). 1 Use INTTAB1OV signal (use it as count signal for interrupt culling). TAB1ID4 TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0 Number of times of interrupt 0 0 0 0 0 Not culled (all interrupts are output) 0 0 0 0 1 1 masked (one of two interrupts is output) 0 0 0 1 0 2 masked (one of three interrupts is output) 0 0 0 1 1 3 masked (one of four interrupts is output) : : : : : 1 1 1 0 0 28 masked (one of 29 interrupts is output) 1 1 1 0 1 29 masked (one of 30 interrupts is output) 1 1 1 1 0 30 masked (one of 31 interrupts is output) 1 1 1 1 1 31 masked (one of 32 interrupts is output) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 : Page 533 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2) TAB1 option register 2 (TAB1OPT2) The TAB1OPT2 register is an 8-bit register that controls the timer Q option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is prohibited when the TAB1CE bit is 1. The same value can be rewritten. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H R/W Address: FFFFF581H <7> <6> <5> TAB1OPT2 <4> <3> <2> <1> <0> TAB1RDE TAB1DTM TAB1ATM3 TAB1ATM2 TAB1AT3 TAB1AT2 TAB1AT1 TAB1AT0 TAB1RDE Transfer culling enable 0 Do not cull transfer (transfer timing is generated every time at crest and valley). 1 Cull transfer at the same interval as interrupt culling set by the TAB1OPT1 register. TAB1DTM Dead-time counter operation mode selection (m = 1 to 3) 0 The dead-time counter counts up normally and, if TOAB1m output of TAB1 is at a narrow interval (TOAB1m output width < dead-time width), the dead-time counter is cleared and counts up again. 1 The dead-time counter counts up normally and, if TOAB1m output of TAB1 is at a narrow interval (TOAB1m output width < dead-time width), the dead-time counter counts down and the dead-time control width is automatically narrowed. Rewriting the TAB1DTM bit is disabled during timer operation. If it is rewritten by mistake, stop the timer operation by clearing the TAB1CE bit to 0, and re-set the TAB1DTM bit. Cautions 1. When using interrupt culling (the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are set to other than 00000), be sure to set the TAB1RDE bit to 1. This means that interrupts and transfers are generated at the same timing. Interrupts and transfers, cannot be set separately. If interrupts and transfers are set separately (TAB1RDE bit = 0), transfers are not performed normally. 2. When generating a dead-time period, set the TAB1DTC register to 1 or higher. Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are in their default states. Therefore, for the protection of the system, take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. When a dead-time period is not needed, set the TAB1DTC register to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 534 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2/2) TAB1ATM3 TAB1ATM3 mode selection 0 Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting up. 1 Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting down. TAB1ATM2 TAB1ATM2 mode selection 0 Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while dead-time counter is counting up. 1 Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while dead-time counter is counting down. TAB1AT3Note A/D trigger output control 3 0 Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt. 1 Enable output of A/D trigger signal (TABTADT0) for INTRAA4CC1 interrupt. TAB1AT2Note A/D trigger output control 2 0 Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt. 1 Enable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt. TAB1AT1Note A/D trigger output control 1 0 Disable output of A/D trigger signal (TABTADT0) for INTTAB1CC0 (crest interrupt). 1 Enable output of A/D trigger signal (TABTADT0) for INTTAB1CC0 (crest interrupt). TAB1AT0Note A/D trigger output control 0 0 Disable output of A/D trigger signal (TABTADT0) for INTTAB1OV (valley interrupt). 1 Enable output of A/D trigger signal (TABTADT0) for INTTAB1OV (valley interrupt). Note For the setting of the TAB1AT3 to TAB1AT0 bits, see CHAPTER 14 A/D CONVERTER. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 535 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (3) TAB1 I/O control register 3 (TAB1IOC3) The TAB1IOC3 register is an 8-bit register that controls the output of the timer Q option function. To output from the TOAB1Tm pin, set the TAB1IOC0.TAB1OEm bit to 1 and then set the TAB1IOC3 register. The TAB1IOC3 register can be rewritten only when the TAB1CTL0.TAB1CE bit is 0. Rewriting each bit of the TAB1IOC3 register is prohibited when the TAB1CTL0.TAB1CE bit is 1; however the same value can be rewritten to each bit of the TAB1IOC3 register when the TAB1CTL0.TAB1CE bit is 1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to A8H. Caution Set the TAB1IOC3 register to the reset value (A8H) when the timer is used in a mode other than the 6-phase PWM output mode. Remarks 1. Set the output level of the TOAB1Tm pin by using the TAB1IOC0 register. 2. m = 1 to 3 After reset: A8H R/W Address: FFFFF582H <7> <6> <5> TAB1IOC3 <4> <3> <2> TAB1OLB3 TAB1OEB3 TAB1OLB2 TAB1OEB2 TAB1OLB1TAB1OEB1 TAB1OLBm R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 0 Setting of TOAB1Bm pin output level (m = 1 to 3) 0 Disable inversion of output of TOAB1Bm pin 1 Enable inversion of output of TOAB1Bm pin TAB1OEBm 1 0 TOAB1Bm pin output (m = 1 to 3) 0 Disable TOAB1Bm pin output. * When TAB1OLBm bit = 0, low level is output from TOAB1Bm pin. * When TAB1OLBm bit = 1, high level is output from TOAB1Bm pin. 1 Enable TOAB1Bm pin output. Page 536 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (a) Output from TOAB1Tm and TOAB1Bm pins The TOAB1Tm pin output is controlled by the TAB1IOC0.TAB1OLm and TAB1IOC0.TAB1OEm bits. The TOAB1Bm pin output is controlled by the TAB1IOC3.TAB1OLBm and TAB1IOC3.TAB1OEBm bits. The timer output with each setting in the 6-phase PWM output mode is shown below. Figure 10-3. Output Control of TOAB1Tm and TOAB1Bm Pins (Without Dead Time) 16-bit counter TAB1OEm bit = 0, TAB1OLm bit = 0 (status after reset) TAB1OEBm bit = 0, TAB1OLBm bit = 1 (status after reset) TOAB1Tm pin output Fixed to low-level output TOAB1Bm pin output Fixed to high-level output TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output) TOAB1Tm pin output TOAB1Bm pin output TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 0 (positive-phase output) TOAB1Tm pin output TOAB1Bm pin output TAB1OEm bit = 1, TAB1OLm bit = 1 (negative-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output) TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 537 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Table 10-1. TOAB1Tm Pin Output TAB1OLm Bit TAB1OEm Bit TAB1CE Bit 0 0 x Low-level output 1 0 Low-level output 1 TOAB1Tm positive-phase output 0 x High-level output 1 0 High-level output 1 TOAB1Tm negative-phase output 1 Remark TOAB1Tm Pin Output m = 1 to 3 Table 10-2. TOAB1Bm Pin Output TAB1OLBm Bit TAB1OEBm Bit 0 1 Remark TAB1CE Bit TOAB1Bm Pin Output 0 x Low-level output 1 0 Low-level output 1 TOAB1Bm positive-phase output 0 x High-level output 1 0 High-level output 1 TOAB1Bm negative-phase output m = 1 to 3 (6) High-impedance output control registers 0, 1 (HZA0CTL0, HZA0CTL1) The HZA0CTL0 and HZA0CTL1 registers are 8-bit registers that control the high-impedance state of the output buffer. These registers can be read or written in 8-bit or 1-bit units. However, the HZA0DCFn bit is a read-only bit and cannot be written. 16-bit access is not possible. Reset sets these registers to 00H. Software can be used to always write the same value to the HZA0CTLn register. The relationship between detection factor and the control registers is shown below. Pins Subject to High-Impedance Control High-Impedance Control Factor Control Register External Pin When TOAB1T1 to TOAB1T3 are output TOAB1OFF/INTP16 HZA0CTL0 TOAA1OFF/INTP09 HZA0CTL1 When TOAB1B1 to TOAB1B3 are output When TOAA11 is output Caution High impedance control is performed only when the target port is specified as a target pin in the above table. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 538 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (1/2) After reset: 00H R/W <7> HZA0CTLn Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H <6> 5 4 <3> <2> HZA0DCEn HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn 1 <0> 0 HZA0DCFn (n = 0, 1) High-impedance output control HZA0DCEn 0 Disable high-impedance output control operation. Pins can function as output pins. 1 Enable high-impedance output control operation. Condition of clearing high-impedance state by HZA0DCCn bit HZA0DCMn 0 Setting of the HZA0DCCn bit is valid regardless of the external pin input. 1 Setting of the HZA0DCCn bit is invalid while the external pin input holds a level detected as abnormal (active level). Rewrite the HZA0DCMn bit when the HZA0DCEn bit = 0. HZA0DCNn HZA0DCPn External pin input edge specification 0 0 No valid edge (setting the HZA0DCFn bit by external pin input is prohibited). 0 1 Rising edge of the external pin is valid (abnormality is detected by rising edge input). 1 0 Falling edge of the external pin is valid (abnormality is detected by falling edge input). 1 1 Setting prohibited * Rewrite the HZA0DCNn and HZA0DCPn bits when the HZA0DCEn bit is 0. * For the valid edge specification of the interrupts of the INTP09 and INTP16 pins, see 22.6.2 (3) External interrupt falling, rising edge specification register 3 (INTR3, INTF3) and (5) External interrupt falling, rising edge specification register 9H (INTR9, INTF9). * For the edge specification of the external pins, begin with the TOAB1OFF and TOAA1OFF pins. Then, perform edge specification for the external pins other than the TOAB1OFF and TOAA1OFF pins. Otherwise, an undefined edge may be detected when the edge for the TOAB1OFF and TOAA1OFF pins is specified. * High-impedance output control is performed when the valid edge is input after the operation is enabled (by setting HZA0DCEn bit to 1). If the external pin is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 539 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2/2) High-impedance output trigger bit HZA0DCTn 0 No operation 1 Pins are made to go into a high-impedance state by software and the HZA0DCFn bit is set to 1. * If an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn bit is invalid even if it is set to 1. * The HZA0DCTn bit is always 0 when it is read because it is a software-triggered bit. * The HZA0DCTn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0. * Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited. HZA0DCCn High-impedance output control clear bit 0 No operation 1 Pins that have gone into a high-impedance state are output-enabled by software and the HZA0DCFn bit is cleared to 0. * Pins can function as output pins when the HZA0DCM bit = 0, regardless of the status of the external pin. * If an edge indicating abnormality is input to the external pin (which is set by the HZA0DCNn and HZA0DCPn bits) when the HZA0DCM bit = 1, the HZA0DCCn bit is invalid even if it is set to 1. * The HZA0DCCn bit is always 0 when it is read. * The HZA0DCCn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0. * Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited. HZA0DCFn High-impedance output status flag Clear (0) Indicates that output of the pin is enabled. * This bit is cleared to 0 when the HZA0DCEn bit = 0. * This bit is cleared to 0 when the HZA0DCCn bit = 1. Set (1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Indicates that the pin goes into a high-impedance state. * This bit is set to 1 when the HZA0DCTn bit = 1. * This bit is set to 1 when an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits). Page 540 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-4. High-Impedance Output Controller Configuration TOAA1OFF/ INTP09 Analog filter TOAB1OFF/ INTP16 Analog filter Edge detection INTP16 Edge detection INTP09 HZA0CTL1 X2 Main oscillator TOAA11 TMQOP TOAB1B1 HZA0CTL0 PLL X1 TAA1 Clock monitor circuit TOAB1T1 TOAB1B2 TOAB1T2 TOAB1B3 TOAB1T3 Remark Also see Figures 10-1 and 10-2. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 541 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (a) Setting procedure (i) Setting of high-impedance control operation <1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits. <2> Set the HZA0DCEn bit to 1 (enable high-impedance control). (ii) Changing setting after enabling high-impedance control operation <1> Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation). <2> Change the setting of the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits. <3> Set the HZA0DCEn bit to 1 (to enable the high-impedance control operation again). (iii) Resuming output when pins are in high-impedance state If the HZA0DCMn bit is 1, set the HZA0DCCn bit to 1 to clear the high-impedance state after the valid edge of the external pin is detected. However, the high-impedance state cannot be cleared unless this bit is set while the input level of the external pin is inactive. <1> Set the HZA0DCCn bit to 1 (command signal to clear the high-impedance state). <2> Read the HZA0DCFn bit and check the flag status. <3> Return to <1> if the HZA0DCFn bit is 1. The input level of the external pin must be checked. The pin can function as an output pin if the HZA0DCFn bit is 0. (iv) Making pin go into high-impedance state by software The HZA0DCTn bit must be set to 1 by software to make the pin go into a high-impedance state while the input level of the external pin is inactive. The following procedure is an example in which the setting is not dependent upon the setting of the HZA0DCMn bit. <1> Set the HZA0DCTn bit to 1 (high-impedance output command). <2> Read the HZA0DCFn bit to check the flag status. <3> Return to <1> if the HZA0DCFn bit is 0. The input level of the external pin must be checked. The pin is in a high-impedance state if the HZA0DCFn bit is 1. However, if the external pin is not used with the HZA0DCPn bit and HZA0DCNn bit cleared to 0, the pin goes into a high-impedance state when the HZA0DCTn bit is set to 1. Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 542 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4 Operation 10.4.1 System outline (1) Outline of 6-phase PWM output The 6-phase PWM output mode is used to generate a 6-phase PWM output wave, by using the timer AB1 (TAB1) and the TMQ option (TMQOPA) in combination. The 6-phase PWM output mode is enabled by setting the TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits of TAB1 to "111". One 16-bit counter and four 16-bit compare registers of TAB1 are used to generate a basic 3-phase wave. The functions of the compare registers are as follows. TAA4 can perform a tuning operation with TAB1 to generate a conversion trigger source for the A/D converter. Compare Register Function Settable Range TAB1CCR0 register Setting of cycle 0002H m FFFEH TAB1CCR1 register Specifying output width of phase U 0000H i m + 1 TAB1CCR2 register Specifying output width of phase V 0000H j m + 1 TAB1CCR3 register Specifying output width of phase W 0000H k m + 1 Remark m = Set value of TAB1CCR0 register i = Set value of TAB1CCR1 register j = Set value of TAB1CCR2 register k = Set value of TAB1CCR3 register A dead-time interval is generated from the basic 3-phase wave generated by using three 10-bit dead-time counters and one compare register to create a wave with a reverse phase to that of the basic 3-phase wave. Then a 6phase PWM output wave (U, U, V, V, W, and W) is generated. The 16-bit counter for generating the basic 3-phase wave counts up or down. After the operation has been started, this counter counts up. When its count value matches the cycle set to the TAB1CCR0 register, the counter starts counting down. When the count value matches 0001H, the counter counts up again. This means that a value two times higher than the value set to the TAB1CCR0 register + 1 is the carrier cycle. 10-bit dead-time counters 1 to 3, which generate the dead-time interval, count up. Therefore, the value set to the TAB1 dead-time compare register (TAB1DTC) is used as a dead-time value as is. Because three counters are used, dead time can be generated independently in phases U, V, and W. However, because there is only one register that specifies a dead-time value (TAB1DTC), the same dead-time value is used in all three phases. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 543 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-5. Outline of 6-Phase PWM Output Mode 16-bit counter A/D trigger generator Up/down selection INTTAB1OV_BASE Interrupt culling circuit 0001H Dead-time counter 1 TAB1CCR1 register (phase U output data) TOAB12 (internal signal)Note Dead-time counter 2 TAB1CCR2 register (phase V output data) TOAB13 (internal signal)Note INTTAB1CC0 signal (crest interrupt) TOAB10 pin output TAB1CCR0 register (carrier cycle) TOAB11 (internal signal)Note INTTAB1OV signal (valley interrupt) Dead-time counter 3 TAB1CCR3 register (phase W output data) TOT1 TOAB1T1 pin output (U) TOB1 TOAB1B1 pin output (U) TOT2 TOAB1T2 pin output (V) TOB2 TOAB1B2 pin output (V) TOT3 TOAB1T3 pin output (W) TOB3 TOAB1B3 pin output (W) TAB1DTC register (dead-time value) Note TOAB11, TOAB12, and TOAB13 function alternately as output pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 544 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-6. Timing Chart of 6-Phase PWM Output Mode M+1 k 16-bit counter j i 0000H TAB1CCR0 register TAB1CCR1 register TAB1CCR2 register TAB1CCR3 register M+1 k k j k j i j i i M (carrier data) i (phase U data) j (phase V data) k (phase W data) TOAB11 signal (internal signal) TOAB12 signal (internal signal) TOAB13 signal (internal signal) Carrier cycle = (M + 1) x 2 Basic phase U output width = (M + 1 - i) 2 Basic phase V output width = (M + 1 - j) x 2 TAB1DTC register Basic phase W output width = (M + 1 - k) x 2 N (dead-time value) Dead-time counter 1 Dead-time counter 2 Dead-time counter 3 TOAB10 pin output TOAB1T1 pin output (U) TOAB1B1 pin output (U) TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TOAB1B3 pin output (W) Phase U output width = (M + 1 - i) x 2 - N Phase U output width = (M + 1 - i) x 2 + N Phase V output width = (M + 1 - j) x 2 - N Phase V output width = (M + 1 - j) x 2 + N Phase W output width = (M + 1 - k) x 2 - N Phase W output width = (M + 1 - k) x 2 + N Dead-time width = N Cautions 1. Set the value "M" of the TAB1CCR0 register in a range of 0002H M FFFEH in the 6-phase PWM output mode. 2. Only a value of up to "M + 1" can be set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. 3. The output is 100% if "0000H" is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. The output is 0% if "M + 1" is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. The output (duty 50%) rises at the crest (M + 1) of the 16-bit counter and falls at the valley (0000H) if "M + 2" or higher is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. 4. If the operation value of an equation (such as (M + 1 - i) x 2 - N) of the output width of phases U, V, and W is 0 or lower, it is converged to 0 (100% output). If the operation value is higher than "(M + 1) x 2", it is converged to (M + 1) x 2 (0% output). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 545 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2) Interrupt requests Two types of interrupt requests are available: the INTTAB1CC0 (crest interrupt) signal and INTTAB1OV (valley interrupt) signal. The INTTAB1CC0 and INTTAB1OV signals can be culled by using the TAB1OPT1 register. For details of culling interrupts, see 10.4.3 Interrupt culling function. * INTTAB1CC0 (crest interrupt) signal: An interrupt signal indicating a match between the value of the 16-bit counter that counts up and the value of the TAB1CCR0 register * INTTAB1OV (valley interrupt) signal: An interrupt signal indicating a match between the value of the 16-bit counter that counts down and the value 0001H (3) Rewriting registers during timer operation The following registers have a buffer register and can be rewritten in the anytime rewrite mode, batch rewrite mode, or intermittent batch rewrite mode. Related Unit Timer AA1 Register TAA1 capture/compare register 0 (TAA1CCR0) TAA1 capture/compare register 1 (TAA1CCR1) Timer AB1 TAB1 capture/compare register 0 (TAB1CCR0) TAB1 capture/compare register 1 (TAB1CCR1) TAB1 capture/compare register 2 (TAB1CCR2) TAB1 capture/compare register 3 (TAB1CCR3) Timer Q1 option TAB1 option register 1 (TAB1OPT1) For details of the transfer function of the compare register, see 10.4.4 Operation to rewrite register with transfer function. (4) Counting-up/down operation of 16-bit counter The operation status of the 16-bit counter can be checked by using the TAB1CUF bit of TAB1 option register 0 (TAB1OPT0). Status of TAB1CUF Bit Status of 16-Bit Counter Range of 16-Bit Counter Value TAB1CUF bit = 0 Counting up 0000H - m TAB1CUF bit = 1 Counting down (m + 1) - 0001H Remark m = Set value of TAB1CCR0 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 546 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-7. Interrupt and Up/Down Flag M+1 k 16-bit counter j i 0000H TAB1CCR0 register TAB1CCR1 register TAB1CCR2 register TAB1CCR3 register TOAB10 pin output TOAB1T1 pin output (U) TOAB1B1 pin output (U) TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TOAB1B3 pin output (W) M+1 k k j j i i k j i M (carrier data) i (phase U data) j (phase V data) k (phase W data) INTTAB1CC0 (crest interrupt) INTTAB1OV (valley interrupt) TAB1CUF (up/down flag) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 547 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4.2 Dead-time control (generation of negative-phase wave signal) (1) Dead-time control mechanism In the 6-phase PWM output mode, compare registers 1 to 3 (TAB1CCR1, TAB1CCR2, and TAB1CCR3) are used to set the duty factor, and compare register 0 (TAB1CCR0) is used to set the cycle. By setting these four registers and by starting the operation of TAB1, three types of PWM output waves (basic 3-phase waves) with a variable duty factor are generated. These three PWM output waves are input to the timer Q option unit (TMQOP) and their inverted signal with dead-time is created to generate three sets of (six) PWM waves. The TMQOP unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with the count clock of TAB1, and a TAB1 dead-time compare register (TAB1DTC) that specifies dead time. If "a" is set to the TAB1DTC register, the dead-time value is "a", and interval "a" is created between a positive-phase wave and a negative-phase wave. Figure 10-8. PWM Output Wave with Dead Time (1) (a) When dead time is inserted (TAB1DTC register = a) 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output a a (b) No dead time (TAB1DTC register = 000H) 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output 0000H TOAB1Bm pin output 0 Remark 0 m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 548 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2) PWM output of 0%/100% The V850ES/V850ES/JC3-H and V850ES/JE3-H are capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously output from the TOAB1Tm pin as the 100% wave output. A 0% wave is output by setting the TAB1CCRm register to "M + 1" when the TAB1CCR0 register = M. A 100% wave is output by setting the TAB1CCRm register to "0000H". Rewriting the TAB1CCRm register is enabled while the timer is operating, and 0% wave output or 100% wave output can be selected at the point of the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV). Remark m = 1 to 3 Figure 10-9. 0% PWM Output Waveform (With Dead Time) 16-bit counter i i TAB1CCR0 register i M TAB1CCR1 register CCR1 buffer register i i i M+1 i 0000H i M+1 i <2> <1> TOAB1T1 pin output M+1 i M+1 <3> <4> 0% output i i 0% output TOAB1B1 pin output Forced timing of timer output <1> 0% output is selected by the valley interrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output. This produces the 0% output. <2> 0% output is canceled by the crest interrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the timer output. This cancels the 0% output. <3> 0% output is selected by the crest interrupt (with a match with the 16-bit counter). The crest interrupt forcibly raises the timer output, but lowering the timer output takes precedence when the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 0% wave is output. <4> 0% output is canceled by the valley interrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output. This cancels the 0% output. Remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 549 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-10. 100% PWM Output Waveform (With Dead Time) 16-bit counter i i i TAB1CCR0 register i i M TAB1CCR1 register CCR1 buffer register i 0000H i 0000H i 0000H <1> TOAB1T1 pin output TOAB1B1 pin output Forced timing of timer output 0000H i 0000H i <2> 100% output i <3> i <4> 100% output <1> 100% output is selected by the valley interrupt (with a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 100% output is produced. <2> 100% output is canceled by the valley interrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output. This cancels the 100% output. <3> 100% output is selected by the crest interrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the timer output. This produces the 100% output. <4> 100% output is canceled by the crest interrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the timer output. This cancels the 100% output. Remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 550 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (With Dead Time) 16-bit counter TAB1CCR0 register TAB1CCR1 register CCR1 buffer register M 0000H 0000H 0000H <1> TOAB1T1 pin output TOAB1B1 pin output M+1 M+1 0000H M+1 100% output 0000H M+1 0000H <1> <2> 0% output 0000H <2> <1> 0% output 100% output 100% output Forced timing of timer output <1> The valley interrupt selects 100% 0% or 0% 100% output. Output can be selected from 100% 0% or 0% 100% immediately after the timer has been started. <2> The crest interrupt selects 100% 0% output. The crest interrupt selects 100% 0% output by using the timer output forcible raising function and by a match between the 16-bit counter value and the TAB1CCR0 register value. (3) Output waveform in vicinity of 0% and 100% output If an interrupt is generated because the value of the 16-bit counter matches the value of the compare register while dead time is being counted, the dead-time counter is cleared and starts its count operation again. The output waveform of dead-time control in the vicinity of 0% and 100% output is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 551 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-12. PWM Output Waveform with Dead Time (2) (a) 0% output (TAB1CCRm register = M + 1, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H L TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output 000H (dead-time counter m does not count) L H (b) In vicinity of 0% output (TAB1CCRm register = i M + 1 - a/2, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m 000H Dead-time counter is cleared and counts again TOAB1Tm pin output TOAB1Bm pin output L Negative-phase output width: (M + 1 - i) x 2 + a (e.g., output width is 2 + a where TAB1CCRm register = M) (c) In vicinity of 100% output (TAB1CCRm register = i a/2, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m 000H TOAB1Tm pin output Counter is cleared and counts again TOAB1Bm pin output Positive-phase output width: (M + 1 - i) x 2 - a) (e.g., output width is 2 - a where TAB1CCRm register = 0001H.) (d) 100% output (TAB1CCRm register = 0000H, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m 000H (dead-time counter m does not count) TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 552 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1) The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the TAB1OPT2.TAB1DTM bit to 1. By setting the TAB1DTM bit to 1, the dead-time counter is not cleared, but starts down counting if the TOAB1m (internal signal) output of timer AB changes during dead-time counting. The following timing chart shows the operation of the dead-time counter when the TAB1DTM bit is set to 1. Figure 10-13. Operation of Dead-Time Counter m (1) (a) In vicinity of 0% output (TAB1CCRm register = i M + 1 - a/2, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m 000H Dead-time counter m starts counting down TOAB1Tm pin output TOAB1Bm pin output Negative-phase wave output width: (M + 1 - i) x 4 (e.g., output width is 4 where TAB1CCRm = M) (b) In vicinity of 100% output (TAB1CCRm register = i a/2, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m 000H TOAB1Tm pin output Dead-time counter m starts counting down TOAB1Bm pin output Note Positive-phase wave output width: (M + 1 - i) x 2 - (i x 2) (e.g., output width is M x 2 - 2 where TAB1CCRm = 0001H) Note The output width of the first wave differs from that of the second and subsequent waves immediately after the TAB1CTL0.TAB1CE bit has been set. The first wave is shorter than the second wave because the dead time is fully counted. Remark m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 553 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (5) Dead-time control in case of incorrect setting Usually, the TOAB1m (internal signal) output of TAB1 changes only once during dead-time counting, only in the vicinity of 0% and 100% output. This section shows an example where the TAB1CCR0 register (carrier cycle) and TAB1DTC register (dead-time value) are incorrectly set. If these registers are incorrectly set, the TOAB1m (internal signal) output of TAB1 changes twice or three times during dead-time counting. The following flowchart shows the 6-phase PWM output wave in this case. Figure 10-14. Operation of Dead-Time Counter m (2) (a) When TAB1OPT2.TAB1DTM bit = 0, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH, TAB1CCRm register = 0004H 16-bit counter TOAB1m signal (internal signal) Dead-time counter m 001H 002H 003H 004H 005H 006H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH 000H 000H 001H TOAB1Tm pin output TOAB1Bm pin output Counter cleared Counter is not cleared but continues counting (b) When TAB1OPT2.TAB1DTM bit = 1, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH, TAB1CCRm register = 0002H 16-bit counter TOAB1m signal (internal signal) Dead-time counter m 000H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 009H 008H 007H 006H 005H 004H 003H 002H 001H 000H 001H 002H 003H 004H 003H 002H 001H TOAB1Tm pin output TOAB1Bm pin output Starts counting down. Remark Output does not change and dead-time counter m continues counting down m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 554 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4.3 Interrupt culling function * The interrupts to be culled are INTTAB1CC0 (crest interrupt) and INTTAB1OV (valley interrupt). * The TAB1OPT1.TAB1ICE bit is used to enable output of the INTTAB1CC0 interrupt and the number of times the interrupt is to be culled. * The TAB1OPT1.TAB1IOE bit is used to enable output of the INTTAB1OV interrupt and the number of times the interrupt is to be culled. * The TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are used to specify the number of counts by which a specified interrupt is to be culled. The interrupt is masked for the duration of the specified number of counts and is generated at the next interrupt timing. * The TAB1OPT2.TAB1RDE bit is used to specify whether transfer is to be culled or not. If it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling. If it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the TAB1CCR1 register has been written. * The TAB1OPT0.TAB1CMS bit is used to specify whether the registers with a transfer function are batch rewritten or anytime rewritten. The values of the registers are updated in synchronization with transfer when the TAB1CMS bit is 0. When the TAB1CMS bit is 1, the values of the registers are immediately updated when a new value is written to the registers. Transfer is performed from the TAB1CCRm register to the CCRm buffer register in synchronization with the interrupt culling timing. Cautions 1. When using the interrupt culling function in the batch rewrite mode (transfer mode), execute the function in the intermittent batch rewrite mode (transfer culling mode). 2. The interrupt is generated at the timing after culling. Remark m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 555 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (1) Interrupt culling operation Figure 10-15. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Crest/Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00101 (5 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00110 (6 masks) INTTAB1CC0 signal INTTAB1OV signal Remark : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 556 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-16. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT2.TAB1RDE Bit = 1 (Crest Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) INTTAB1CC0 signal INTTAB1OV signal Remark : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 557 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-17. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) INTTAB1CC0 signal INTTAB1OV signal TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) INTTAB1CC0 signal INTTAB1OV signal Remark : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 558 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2) To alternately output crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) To alternately output the crest and valley interrupts, set both the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits to 1. Figure 10-18. Crest/Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) 00100 00010 Transfer 00100 00010 Timing of rewriting transfer culling count from 2 to 4 Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) 00010 00100 Reflected immediately 00100 00010 Timing of rewriting transfer culling count from 2 to 4 Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 559 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (3) To output only crest interrupt (INTTAB1CC0) Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0. Figure 10-19. Crest Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal L TAB1ID4 to TAB1ID0 bits 00011 00010 Transfer TAB1ID4 to TAB1ID0 bits (slave bit) 00011 00010 Timing of rewriting transfer culling count from 2 to 3 Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal L TAB1ID4 to TAB1ID0 bits 00010 TAB1ID4 to TAB1ID0 bits (slave bit) 00010 00011 Reflected immediately 00011 Timing of rewriting transfer culling count from 2 to 3 Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 560 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (4) To output only valley interrupt (INTTAB1OV) Clear the TAB1OPT1.TAB1ICE bit to 0 and set the TAB1IOE bit to 1. Figure 10-20. Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal L TAB1ID4 to TAB1ID0 bits 00011 00010 Transfer TAB1ID4 to TAB1ID0 bits (slave bit) 00011 00010 Timing of rewriting transfer culling count from 2 to 3 Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal L TAB1ID4 to TAB1ID0 bits 00010 TAB1ID4 to TAB1ID0 bits (slave bit) 00010 00011 Reflected immediately 00011 Timing of rewriting transfer culling count from 2 to 3 Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 561 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4.4 Operation to rewrite register with transfer function The following seven registers are provided with a transfer function and are used to control a motor. Each of the registers has a buffer register. * TAB1CCR0: Register that specifies the cycle of the 16-bit counter (TAB) * TAB1CCR1: Register that specifies the duty factor of TOAB1T1 (U) and TOAB1B1 (U) * TAB1CCR2: Register that specifies the duty factor of TOAB1T2 (V) and TOAB1B2 (V) * TAB1CCR3: Register that specifies the duty factor of TOAB1T3 (W) and TOAB1B3 (W) * TAB1OPT1: Register that specifies the culling of interrupts * TAA4CCR0: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation) * TAA4CCR1: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation) The following three rewrite modes are provided in the registers with a transfer function. * Anytime rewrite mode This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The specification of the TAB1OPT2.TAB1RDE bit is ignored. In this mode, each compare register is updated independently, and the value of the compare register is updated as soon as a new value is written to it. * Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0. When data is written to the TAB1CCR1 register, data in the seven registers are transferred to the buffer register all at once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed even if the other six registers are rewritten. The transfer timing is the timing of each crest (match between the 16-bit counter value and TAB1CCR0 register value) and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt. * Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. When data is written to the TAB1CCR1 register, data from the seven registers is transferred to the buffer register all at once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed even if the other six registers are rewritten. If interrupt culling is specified by the TAB1OPT1 register, the transfer timing is also culled as the interrupts are culled, and data from the seven registers is transferred all at once at the culled timing of the crest interrupt (match between the 16-bit counter value and TAB1CCR0 register value) or valley interrupt (match between the 16-bit counter value and 0001H). For details of the interrupt culling function, see 10.4.3 Interrupt culling function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 562 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (1) Anytime rewrite mode This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The setting of the TAB1OPT2.TAB1RDE bit is ignored. In this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the value of the counter. If a register with transfer function is rewritten in this mode after the count value of the 16-bit counter matches the value of the TAB1CCRm register, the rewritten value is not reflected because the next match is ignored after the first match has occurred. If the register is rewritten during counting up, the new register value becomes valid after the counter has started counting down. Figure 10-21. Timing of Reflecting Rewritten Value Operating clock (fXX/2) TAB1CCR0 register b CCR0 buffer register b a a Note Note After the register (TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, or TAA4CCR1) has been written, the written value is transferred to an internal buffer register after four clocks of the operating clock. However, the value of the TAB1CCR1 register is transferred after 5 clocks. (a) Rewriting TAB1CCR0 register Even if the TAB1CCR0 register is rewritten in the anytime rewrite mode, the new value may not be reflected in some cases. Figure 10-22. Example of Rewriting TAB1CCR0 Register 16-bit counter <1> <2> <1> <2> Rewriting during period <1> (rewriting during counting up) If the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will match the value of the 16-bit counter. If the new value is less than the value of the 16-bit counter, it will not match the value of the counter. As a result, the 16-bit counter overflows and continues counting up from 0000H until it matches the register value again, and the correct PWM waveform is not output. Rewriting during period <2> (rewriting during counting down) A match with the value of the 16-bit counter is ignored during counting down. Therefore, the rewritten period value is reflected as the match point starting from counting up in the next cycle. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 563 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (b) Rewriting TAB1CCRm register Figure 10-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the TAB1CCRm register (<1> in Figure 10-23), and Figure 10-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the TAB1CCRm register (<2> in Figure 10-23). Figure 10-23. Basic Operation of 16-Bit Counter and TAB1CCRm Register (a) Basic figure i 16-bit counter i i TAB1CCRm register i i <1> <2> <1> <2> <1> <2> <1> <2> Remarks 1. i = Set value of TAB1CCRm register 2. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 564 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-24. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting Before Match Occurs) (a) If the TAB1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value will match the value of the 16-bit counter after the register has been rewritten. Consequently, the new register value is immediately reflected. i 16-bit counter TAB1CCRm register CCRm buffer register TOAB1Tm pin output k k k i k i k (b) If a value less than the value of the 16-bit counter (greater if the counter is counting down) is written to the TAB1CCRm register, the output waveform is as follows because the register value does not match the counter value. 16-bit counter TAB1CCRm register CCRm buffer register TOAB1Tm pin output r i r i r i r r If the register value does not match the counter value, the TOAB1Tm pin output does not change. Even if the value of the 16-bit counter does not match the value of the TAB1CCRm register, the TOAB1Tm pin output always changes to the high level if the crest interrupt occurs and to the low level if the valley interrupt occurs. This is a function provided for 0% output and 100% output. For details, see 10.4.2 (2) PWM output of 0%/100%. Remarks 1. i, r, k = Set values of TAB1CCRm register 2. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 565 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-25. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting After Match Occurs) 16-bit counter TAB1CCRm register CCRm buffer register i i k k i k k i TOAB1Tm pin output INTTAB1CCm signal k <1> <3> <2> <1> Matching of the count value of the 16-bit counter and the value of the TAB1CCRm register as a result of rewriting the register is ignored after a match signal has been generated, and the PWM output does not change. <2> Even if the PWM output does not change, the interrupt generated upon a match between the 16-bit counter value and the TAB1CCRm register value (INTTAB1CCm) is output. <3> The next match between the 16-bit counter and TAB1CCRm register is valid after the counter has changed its counting direction to up or down, and the PWM output changes. If the TAB1CCRm register is rewritten after its value matches the value of the 16-bit counter, the next match is ignored after the first match occurs and the rewritten value is not reflected in the TOAB1Tm pin output. If the register is rewritten while the counter is counting down, the match that occurs after the counter starts counting down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten while the counter is counting up). Remarks 1. i, r, k = Set value of TAB1CCRm register 2. m = 1 to 3 (c) Rewriting TAB1OPT1 register The interrupt culling counter is cleared when the TAB1OPT1 register is written. When the interrupt culling counter has been cleared, the measured number of times the interrupt has occurred is discarded. Consequently, the interrupt generation interval is temporarily extended. To avoid this operation, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling mode). For details of rewriting the TAB1OPT1 register, see 10.4.3 Interrupt culling function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 566 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the counter value. (a) Rewriting procedure If data is written to the TAB1CCR1 register, the values set to the TAB1CCR0 to TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the TAB1CCR1 register has been written and before the transfer timing is generated (until the crest (match between the 16-bit counter value and TAB1CCR0 register value) or the valley (match between the 16-bit counter value and 0001H)). The operation procedure is as follows. <1> Rewriting the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers Do not rewrite registers that do not have to be rewritten. <2> Rewriting the TAB1CCR1 register Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register. <3> Holding the next rewriting pending until the transfer timing is generated Rewrite the register next time after the INTTAB1OV or INTTAB1CC0 interrupt has occurred. <4> Return to <1>. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 567 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-26. Basic Operation in Batch Mode 16-bit counter (TAB1) Transfer timing TAB1CCR0 register CCR0 buffer register TAB1CCR1 register CCR1 buffer register TAB1CCR2 register CCR2 buffer register TAB1CCR3 register CCR3 buffer register TAB1OPT1 register OPT1 buffer register <Q2> <Q3> <Q1>&<P1> <Q3> <Q3> <Q3> <Q3> INTTAB1OV signal INTTAB1CC0 signal 16-bit counter (TAA4) Transfer timing <P2> TAA4CCR0 register CCR0 buffer register TAA4CCR1 register <P3> <P3> CCR1 buffer register [Operation of TAB1] <Q1> Write the TAB1CCR1 register <Q2> The target timing is the first transfer timing after a write to the TAB1CCR1 register. <Q3> The values are transferred all at once at the transfer timing. [Operation of TAA4] <P1> Write the TAB1CCR1 register <P2> The target timing is the first transfer timing after a write to the TAB1CCR1 register. <P3> The values are transferred all at once at the transfer timing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 568 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the batch rewrite mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and TAB1CCR0 register value) or at the valley (match between the 16-bit counter value and 0001H). Usually, it is recommended to rewrite the TAB1CCR0 register while the 16-bit counter is counting down, and transfer the register value at the transfer timing of the crest timing. Figure 10-28 shows an example of rewriting the TAB1CCR0 register while the 16-bit counter is counting up (during period <1> in Figure 10-27). Figure 10-29 shows an example of rewriting the TAB1CCR0 register while the counter is counting down (during period <2> in Figure 10-27). Figure 10-27. Basic Operation of 16-Bit Counter 16-bit counter <1> R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <2> <1> <2> Page 569 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) The transfer timing in Figure 10-28 is at the point where the crest timing occurs. While the 16-bit counter is counting down, the cycle changes and an asymmetrical triangular wave is output. Because the cycle changes, rewrite the duty factor (voltage data value). Figure 10-28. Example of Rewriting TAB1CCR0 Register (During Counting Up) (a) M > N M 16-bit counter Transfer timing TAB1CCR0 register CCR0 buffer register TAB1CCR1 register CCR1 buffer register TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal N+1 k i k k k k k N+1 N M N M 0000H i k k i 0000H (b) M < N N+1 N+1 M 16-bit counter Transfer timing TAB1CCR0 register CCR0 buffer register TAB1CCR1 register CCR1 buffer register i k N M N M 0000H i 0000H k k i k TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal Remarks 1. If transfer (match between the value of the 16-bit counter and the value of the CCR0 buffer register) occurs in the 6-phase PWM output mode, the value of the TAB1CCR0 register plus 1 is loaded to the 16-bit counter. In this way, the expected wave can be output even if the cycle value is changed at the transfer timing of the crest (match between the 16-bit counter value and the TAB1CCR0 register value) timing. 2. M: Value of CCR0 buffer register before rewriting N: Value of CCR0 buffer register after rewriting R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 570 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-29. Example of Rewriting TAB1CCR0 Register (During Counting Down) M+1 16-bit counter i i k N+1 k k k Transfer timing TAB1CCR0 register CCR0 buffer register TAB1CCR1 register CCR1 buffer register N M M 0000H k i 0000H N i k TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal Because the next transfer timing is at the point of the valley (match between the 16-bit counter value and 0001H), the cycle value changes from the next cycle and output of a symmetrical triangular wave is maintained. Because the cycle changes, rewrite the duty value (voltage data value) as required. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 571 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (c) Rewriting TAB1CCRm register Figure 10-30. Example of Rewriting TAB1CCRm Register 16-bit counter r i r k Transfer timing TAB1CCRm register CCRm buffer register TOAB1Tm register INTTAB1CCm signal i 0000H r k i r k <1> <2> <1> <2> Rewriting during period <1> (rewriting during counting up) Because the TAB1CCRm register value is transferred at the transfer timing of the crest (match between the 16-bit counter value and TAB1CCRm register value), an asymmetrical triangular wave is output. Rewriting during period <2> (rewriting during counting down) Because the TAB1CCRm register value is transferred at the transfer timing of the valley (match between the 16-bit counter value and 0001H), a symmetrical triangular wave is output. Remark m = 1 to 3 (d) Transferring TAB1OPT1 register value Do not set the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to other than 00000. When using the interrupt culling function, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling mode). For details of rewriting the TAB1OPT1 register, see 10.4.3 Interrupt culling function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 572 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (3) Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value. The transfer timing is the timing at which an interrupt is generated (INTTAB1CC0, INTTAB1OV) by interrupt culling. For details of the interrupt culling function, see 10.4.3 Interrupt culling function. (a) Rewriting procedure If data is written to the TAB1CCR1 register, the data of the TAB1CCR0 to TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the TAB1CCR1 register has been written until the transfer timing is generated (until the INTTAB1OV or INTTAB1CC0 interrupt occurs). The operation procedure is as follows. <1> Rewrite the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers. Do not rewrite registers that do not have to be rewritten. <2> Rewrite the TAB1CCR1 register. Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register. <3> Hold the next rewriting pending until the transfer timing is generated. Perform the next rewrite after the INTTAB1OV or INTTAB1CC0 interrupt has occurred. <4> Return to <1>. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 573 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-31. Basic Operation in Intermittent Batch Rewrite Mode 16-bit counter (TAB1) Transfer timing TAB1CCR0 register CCR0 buffer register TAB1CCR1 register <Q4> <Q2> <Q4> <Q3> <Q3> <Q1>&<P1> CCR1 buffer register TAB1CCR2 register CCR2 buffer register TAB1CCR3 register CCR3 buffer register TAB1OPT1 register OPT1 buffer register <Q3> <Q3> <Q3> INTTAB1OV signal <Q4> <Q4> INTTAB1CC0 signal 16-bit counter (TAA4) Transfer timing <P4> TAA4CCR0 register CCR0 buffer register TAA4CCR1 register <P2> <P4> <P3> <P3> CCR1 buffer register [TAB1 operation] <Q1> Write the TAB1CCR1 register. <Q2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been rewritten. <Q3> The registers are transferred all at once at the transfer timing. <Q4> The transfer timing is also culled as the interrupts are culled. [TAA4 operation] <P1> Write the TAB1CCR1 register. <P2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been rewritten. <P3> The registers are transferred all at once at the transfer timing. <P4> The transfer timing is also culled as the interrupts are culled. Remark This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 574 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The following figure illustrates the change of the output waveform when interrupts are culled. Figure 10-32. Rewriting TAB1CCR0 Register (When Crest Interrupt Is Set) M 16-bit counter i i N+1 i k k k k Transfer timing TAB1CCR0 register N M CCR0 buffer register TAB1CCR1 register i CCR1 buffer register N M 0000H 0000H k i k TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal L The transfer timing is generated when the crest interrupt occurs, the cycle of counting up and counting down changes, and an asymmetrical triangular wave is output. Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit = 0, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001. 2. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 575 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-33. Rewriting TAB1CCR0 Register (When Valley Interrupt Is Set) M+1 16-bit counter M+1 i i i i k N+1 k Transfer timing TAB1CCR0 register N M CCR0 buffer register TAB1CCR1 register i CCR1 buffer register N M 0000H 0000H k i k TOAB1T1 pin output INTTAB1CC0 signal L INTTAB1OV signal The transfer timing is generated when the valley interrupt occurs, the cycle of counting up becomes same as cycle of counting down, and a symmetrical triangular wave is output. Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 0, TAB1OPT1.TAB1IOE bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001. 2. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 576 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (c) Rewriting TAB1CCR1 to TAB1CCR3 registers * Transfer at crest when crest interrupt is set Because the register is transferred at the transfer timing of the crest interrupt, an asymmetrical triangular wave is output. Figure 10-34. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001) 16-bit counter i i i k Transfer timing TAB1CCR1 register i CCR1 buffer register r k i k TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal Transfer at crest interrupt Remark : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 577 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) * Transfer at valley when valley interrupt is set Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. Figure 10-35. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001) 16-bit counter i i k k Transfer timing TAB1CCR1 register i CCR1 buffer register r k i r k TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal Transfer at valley interrupt Remark Transfer at valley interrupt : Culled interrupt (d) Rewriting TAB1OPT1 register Because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval. For details of rewriting the TAB1OPT1 register, see 10.4.3 Interrupt culling function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 578 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (4) Rewriting TAB1OPT0.TAB1CMS bit The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 10-36 are necessary. If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal signal) is set. When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer request signal is cleared. This transfer request signal is also cleared when the TAB1CMS bit is set to 1. Figure 10-36. Rewriting TAB1CMS Bit 16-bit counter Transfer timing TAB1CCR1 register CCR1 buffer register Write signal of TAB1CCR1 Transfer request signal k i 0000H r i TAB1CMS bit s r <2> Clear <4> <3> s <5> <6> Clear <1> <1> If the TAB1CCR1 register is rewritten when the TAB1CMS bit is 0, the transfer request signal is set. If the TAB1CMS bit is set to 1 in this status, the transfer request signal is cleared. <2> The register is not transferred because the TAB1CMS bit is set to 1 and the transfer request signal is cleared. <3> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1. <4> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1, so even if the TAB1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing. <5> The transfer request signal is set if the TAB1CCR1 register is written when the TAB1CMS bit is 0. Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not performed at the next transfer timing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 579 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4.5 TAA4 tuning operation for A/D conversion start trigger signal output This section explains the tuning operation of TAA4 and TAB1 in the 6-phase PWM output mode. In the 6-phase PWM output mode, the tuning operation is performed with TAB1 serving as the master and TAA4 as a slave. The conversion start trigger signal of the A/D converter can be set as the A/D conversion start trigger source by the INTTAA4CC0 and INTTAA4CC1 signals of TAA4 and the INTTAB1OV and INTTAB1CC0 signals of TAB1. (1) Tuning operation starting procedure The TAA4 and TAB1 registers should be set using the following procedure to perform the tuning operation. (a) Setting of TAA4 register (stop the operations of TAB1 and TAA4 (by clearing the TAB1CTL0.TAB1CE bit and TAA4CTL0.TAA4CE bit to 0)). * Set the TAA4CTL1 register to 85H (set the tuning operation slave mode and free-running timer mode). * Clear the TAA4OPT0 register to 00H (select the compare register). * Set an appropriate value to the TAA4CCR0 and TAA4CCR1 registers (set the default value for comparison for starting the operation). (b) Setting of TAB1 register * Set the TAB1CTL1 register to 07H (master mode and 6-phase PWM output mode). * Set an appropriate value to the TAB1IOC0 register (set the output mode of TOAB1T1 to TOAB1T3). However, clear the TAB1OL0 bit to 0 and set the TAB1OE0 bit to 1 (enable positive phase output). Unless this setting is made, the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) do not occur. Consequently, the conversion start trigger signal of the A/D converter is not correctly generated. * Set the TAB1IOC1 and TAB1IOC2 registers to 00H (the TIAB10 to TIAB13, EVTB1, and TRGB1 pins of TAB1 are not used). * Clear the TAB1OPT0 register to 00H (select the compare register). * Set an appropriate value to the TAB1CCR0 to TAB1CCR3 registers (set the default value for comparison for starting the operation). * Set the TAB1CTL0 register to 0xH (clear the TAB1CE bit to 0 and set the operating clock of TAB1). * The operating clock of TAB1 set by the TAB1CTL0 register is also supplied to TAA4, and the count operation is performed at the same timing. The operating clock of TAA4 set by the TAA4CTL0 register is ignored. (c) Setting of TMQOP (TMQ option) register * Set an appropriate value to the TAB1OPT1 and TAB1OPT2 registers. * Set an appropriate value to the TAB1IOC3 register (set TOAB1B1 to TOAB1B3 in the output mode). * Set an appropriate value to the TAB1DTC register (set the default value for comparison for starting the operation). (d) Setting of alternate function * Set the port to alternate function mode using the port control mode setting. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 580 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (e) Set the TAA4CE bit to 1 and set the TAB1CE bit to 1 immediately after that to start the 6-phase PWM output operation Rewriting the TAB1CTL0, TAB1CTL1, TAB1IOC1, TAB1IOC2, TAA4CTL0, and TAA4CTL1 registers is prohibited during operation. The operation and the PWM output waveform are not guaranteed if any of these registers is rewritten during operation. However, rewriting the TAB1CTL0.TAB1CE bit to clear it is permitted. Manipulating (reading/writing) the other TAB1, TAA4, and TMQ option registers is prohibited until the TAA4CTL0.TAA4CE bit is set to 1 and then the TAB1CE bit is set to 1. (2) Tuning operation clearing procedure To clear the tuning operation and exit the 6-phase PWM output mode, set the TAA4 and TAB1 registers using the following procedure. <1> Clear the TAB1CTL0.TAB1CE bit to 0 and stop the timer operation. <2> Clear the TAA4CTL0.TAA4CE bit to 0 so that TAA4 can be separated. <3> Stop the timer output by using the TAB1IOC0 register. <4> Clear the TAA4CTL1.TAA4SYE bit to 0 to clear the tuning operation. Caution Manipulating (reading/writing) the other TAB1, TAA4, and TMQ option registers is prohibited until the TAB1CE bit is set to 1 and then the TAA4CE bit is set to 1. (3) When not tuning TAA4 When the match interrupt signal of TAA4 is not necessary as the conversion trigger source that starts the A/D converter, TAA4 can be used independently as a separate timer without being tuned. In this case, the match interrupt signal of TAA4 cannot be used as a trigger source to start A/D conversion in the 6-phase PWM output mode. Therefore, fix the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits to 0. The other control bits can be used in the same manner as when TAA4 is tuned. If TAA4 is not tuned, the compare registers (TAA4CCR0 and TAA4CCR1) of TAA4 are not affected by the setting of the TAB1OPT0.TAB1CMS and TAB1OPT2.TAB1RDE bit. For the initialization procedure when TAA4 is not tuned, see (b) to (e) in 10.4.5 (1) Tuning operation starting procedure. (a) is not necessary because it is a step used to set TAA4 for the tuning operation. (4) Basic operation of TAA4 during tuning operation The 16-bit counter of TAA4 only counts up. The 16-bit counter is cleared by the set cycle value of the TAB1CCR0 register and starts counting from 0000H again. The count value of this counter is the same as the value of the 16bit counter of TAB1 when it counts up. However, it is not the same when the 16-bit counter of TAA4 counts down. * When TAB1 counts up (same value) 16-bit counter of TAB1: 0000H M (counting up) 16-bit counter of TAA4: 0000H M (counting up) * When TAB1 counts down (not same value) 16-bit counter of TAB1: M + 1 0001H (counting down) 16-bit counter of TAA4: 0000H M (counting up) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 581 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-37. TAA4 During Tuning Operation M+1 16-bit counter of TAB1 TAB1CCR0 register TAB1CCR1 register TAB1CCR2 register TAB1CCR3 register k M+1 k j k j k j i i j i i M (carrier data) i (phase U data) j (phase V data) k (phase W data) TOAB0T1 pin output (U) TOAB1B1 pin output (U) TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TOAB1B3 pin output (W) M M r 16-bit counter of TAA4 TAA4CCR0 register TAA4CCR1 register s M r s r s r s s (A/D conversion start trigger timing 2) r (A/D conversion start trigger timing 3) INTTAA4CC0 signal INTTAA4CC1 signal TABTADT0 signal Note Note Note The TABTADT0 signal is masked by the TAB1OPT2.TAB1ATM2 and TAB1OPT2.TAB1ATM3 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 582 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) 10.4.6 A/D conversion start trigger output function The V850ES/JC3-H and V850ES/JE3-H have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0, INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0). The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits. * TAB1AT0 bit = 1: A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs. * TAB1AT1 bit = 1: A/D conversion start trigger signal generated when INTTAB1CC0 (cycle match) occurs. * TAB1AT2 bit = 1: A/D conversion start trigger signal generated when INTTAA4CC0 (match of TAA4CCR0 register of TAA4 during tuning operation) occurs. * TAB1AT3 bit = 1: A/D conversion start trigger signal generated when INTTAA4CC1 (match of TAA4CCR1 register of TAA4 during tuning operation) occurs. The A/D conversion start trigger signals selected by the TAB1AT0 to TAB1AT3 bits are ORed and output. Therefore, two or more trigger sources can be specified at the same time. The INTTAB1OV and INTTAB1CC0 signals selected by the TAB1AT0 and TAB1AT1 bits are culled interrupt signals. Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits), the A/D conversion start trigger signal is not output. The trigger sources (INTTAA4CC0 and INTTAA4CC1) from TAA4 have a function to mask the A/D conversion start trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the TAB1AT2 and TAB1AT3 bits. * TAB1ATM2 bit: Corresponds to the TAB1AT2 bit and controls INTTAA4CC0 (match interrupt signal) of TAA4. * TAB1ATM2 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1). * TAB1ATM2 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0). * TAB1ATM3 bit: Corresponds to the TAB1AT3 bit and controls INTTAA4CC1 (match interrupt signal) of TAA4. * TAB1ATM3 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1). * TAB1ATM3 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0). The TAB1ATM3, TAB1ATM2, and TAB1AT3 to TAB1AT0 bits can be rewritten while the timer is operating. If the bit that sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected in the output status of the A/D conversion start trigger signal. These control bits do not have a transfer function and can be used only in the anytime rewrite mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 583 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Cautions 1. The A/D conversion start trigger signal output that is set by the TAB1AT2 and TAB1AT3 bits can be used only when TAA4 is performing a tuning operation as the slave timer of TAB1. If TAB1 and TAA4 are not performing a tuning operation, or if a mode other than the 6-phase PWM output mode is used, the output cannot be guaranteed. 2. The TAB1 signal output is internally used to identify whether the 16-bit counter is counting up or down. Therefore, enable TOAB10 pin output by clearing the TAB1IOC0.TAB1OL0 bit to 0 and setting the TAB1IOC0.TAB1OE0 bit to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 584 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00000: Without Interrupt Culling) 16-bit counter INTTAB1CC0 signal INTTAB1OV signal INTTAA4CC0 signal INTTAA4CC1 signal TAB1CUF bit TAB1AT3 to TAB1AT0 bits = 0001 (INTTAB1OV signal output) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 0010 (INTTAB1CC0 signal output) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 0 (INTTAA4CC0 signal output during counting up) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 1 (INTTAA4CC0 signal output during counting down) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 0 (INTTAA4CC1 signal output during counting up) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 1 (INTTAA4CC1 signal output during counting down) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 0011 (setting to output A/D conversion start trigger signal when both crest and valley interrupts occur) TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 1100, TAB1ATM3 bit = 1, TAB1ATM2 bit = 0 (INTTAA4CC0 and INTTAA4CC1 signals ORed for output. Setting to output A/D conversion start trigger signal when match interrupt of TAA4 occurs when counter is counting up or down) TABTADT0 signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 585 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) Figure 10-39. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00010: With Interrupt Culling) (1) 16-bit counter INTTAB1CC0 signal L INTTAB1OV signal TAB1AT3 to TAB1AT0 bits = 0011 (both INTTAB1CC0 and INTTAB1OV signals are selected but crest interrupt (INTTAB1CC0) is not output because interrupt culling is not specified) TABTADT0 signal Remark : Culled interrupt Figure 10-40. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00010: With Interrupt Culling) (2) 16-bit counter INTTAB1CC0 signal L INTTAB1OV signal INTAA4CC0 signal INTAA4CC1 signal TAB1CUF bit TAB1AT3 to TAB1AT0 bits = 0101, TAB1ATM2 bit = 1 TABTADT0 signal Caution Remark The INTTAB1CC0 signal is culled but the INTTAA4CC0 signal is not. : Culled interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 586 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JE3-H only) (1) Operation under boundary condition (operation when 16-bit counter matches INTTAA4CC0 signal) Table 10-3. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 0 (Counting Up Period Selected) Value of TAA4CCR0 Value of 16-Bit Value of 16-Bit Status of 16-Bit TABTADT0 Signal Output Register Counter of TAB1 Counter of TAA4 Counter of TAB1 by INTTAA4CC0 Signal 0000H 0000H 0000H - Output 0000H M+1 0000H - Not output 0001H 0001H 0001H Count-up Output 0001H M 0001H Count-down Not output M M M Count-up Output M 0001H M Count-down Not output Table 10-4. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 1 (Counting Down Period Selected) Value of TAA4CCR0 Value of 16-Bit Value of 16-Bit Status of 16-Bit TABTADT0 Signal Output Register Counter of TAB1 Counter of TAA4 Counter of TAB1 by INTTAA4CC0 Signal 0000H 0000H 0000H - Not output 0000H M+1 0000H - Output 0001H 0001H 0001H Count-up Not output 0001H M 0001H Count-down Output M M M Count-up Not output M 0001H M Count-down Output Caution The TAA4CCRm register enables the setting of "0" to "M" when the TAB1CCR0 register = M. Setting a value of "M + 1" or higher is prohibited. If a value of "M + 1" or higher is set, the 16-bit counter of TAA4 is cleared by "M". Therefore, the TABTADT0 signal is not output. Remark m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 587 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER CHAPTER 11 REAL-TIME COUNTER 11.1 Functions The real-time counter (RTC) has the following features. * Counting up to 99 years using year, month, day-of-week, day, hour, minute, and second sub-counters provided * Year, month, day-of-week, day, hour, minute, and second counter display using BCD codesNote 1 * Alarm interrupt function * Constant-period interrupt function (period: 1 month to 0.5 second) * Interval interrupt function (period: 1.95 ms to 125 ms) * Pin output function Note 2 of 1 Hz * Pin output function Note 2 of 32.768 kHz * Pin output function Note 2 of 512 Hz or 16.384 kHz * Watch error correction function * Subclock operation or main clock operationNote 3 selectable Notes 1. A BCD (binary coded decimal) code expresses each digit of a decimal number in 4-bit binary format. 2. V850ES/JE3-H only 3. Use the baud rate generator dedicated to the real-time counter to divide the main clock frequency to 32.768 kHz for use. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 588 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.2 Configuration The real-time counter includes the following hardware. Table 11-1. Configuration of Real-Time Counter Item Control registers Configuration Real-time counter control register 0 (RC1CC0) Real-time counter control register 1 (RC1CC1) Real-time counter control register 2 (RC1CC2) Real-time counter control register 3 (RC1CC3) Sub-count register (RC1SUBC) Second count register (RC1SEC) Minute count register (RC1MIN) Hour count register (RC1HOUR) Day count register (RC1DAY) Day-of-week count register (RC1WEEK) Month count register (RC1MONTH) Year count register (RC1YEAR) Watch error correction register (RC1SUBU) Alarm minute register (RC1ALM) Alarm hour register (RC1ALH) Alarm week register (RC1ALW) Prescaler mode register 0 (PRSM0) Prescaler compare register 0 (PRSCM0) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 589 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER Figure 11-1. Block Diagram of Real-Time Counter CLOE1 RTC1HZNote2 Hour alarm Minute alarm Day-of-week alarm Selector INTRTC1 fBRGNote1 fXT Selector Count clock = 32.768 kHz Sub-counter (16-bit) 1 minute Second counter (7-bit) 1 hour Minute counter (7-bit) 1 month 1 day Day counter (3-bit) Hour counter (6-bit) INTRTC0 Day-of week counter (3-bit) Month counter (5-bit) Year counter (8-bit) Count enable/ disable circuit Second counter write buffer Minute counter write buffer Hour counter write buffer Day counter write buffer Week counter write buffer Month counter write buffer Year counter write buffer ICT2 to ICT0 fXT/211 fXT/210 fXT/29 fXT/28 fXT/27 fXT/26 RINTE fXT/26 fXT/2 INTRTC2 CKDIV Selector fXT/2 Selector 12-bit counter 12 CLOE2 RTCDIVNote2 CLOE0 RTCCLNote2 Notes1. For detail of fBRG, refer to 11.3 (17) Prescaler mode register 0 (PRSM0) and 11.3 (18) Prescaler compare register 0 (PRSCM0). 2. Remark V850ES/JE3-H only. fBRG: Real-time counter count clock frequency fXT: Subclock frequency INTRTC0: Real-time counter fixed-cycle interrupt signal INTRTC1: Real-time counter alarm match interrupt signal INTRTC2: Real-time counter interval interrupt signal R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 590 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.2.1 Pin configuration The RTC outputs included in the real-time counter are alternatively used as shown in Table 11-2. The port function must be set when using each pin (see Table 4-17 Settings When Pins Are Used for Alternate Functions). Table 11-2. Pin Configuration Port Pin Number RTC Output Other Alternate Function V850ES/JC3-H V850ES/JE3-H - 36 P35 RTC1HZ TIAB01/TOAB01 - 35 P33 RTCDIV TIAB00/TOAB00/RTCCL - 35 P33 RTCCL TIAB00/TOAB00/RTCDIV 11.2.2 Interrupt functions The RTC includes the following three types of interrupt signals. (1) INTRTC0 A fixed-cycle interrupt signal is generated every 0.5 second, second, minute, hour, day, or month. (2) INTRTC1 Alarm interrupt signal (3) INTRTC2 An interval interrupt signal of a cycle of fXT/26, fXT/27, fXT/28, fXT/29, fXT/210, fXT/211, or fXT/212 is generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 591 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.3 Registers The real-time counter is controlled by the following 18 registers. (1) Real-time counter control register 0 (RC1CC0) The RC1CC0 register selects the real-time counter input clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 7 RC1CC0 6 RC1PWR RC1CKS Address: FFFFFADDH 5 4 3 2 1 0 0 0 0 0 0 0 RC1PWR Real-time counter operation control 0 Stops real-time counter operation. 1 Enables real-time counter operation. RC1CKS Operation clock selection 0 Selects fXT as operation clock. 1 Selects fBRG as operation clock. Cautions 1. Follow the description in 11.4.8 Initializing real-time counter when stopping (RC1PWR = 1 0) the real-time counter while it is operating. 2. The RC1CKS bit can be rewritten only when the real-time counter is stopped (RC1PWR bit = 0). Furthermore, rewriting the RC1CKS bit at the same time as setting the RC1PWR bit from 0 to 1 is prohibited. (2) Real-time counter control register 1 (RC1CC1) The RC1CC1 register is an 8-bit register that starts or stops the real-time counter, controls the RTCCL and RTC1HZ pins, selects the 12-hour or 24-hour system, and sets the fixed-cycle interrupt function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 592 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER After reset: 00H RC1CC1 R/W 7 6 RTCE 0 Address: FFFFFADEH 5 4 RTCE 1 0 CT1 CT0 Control of operation of each counter 0 Stops counter operation. 1 Enables counter operation. CLOE1Note RTC1HZ pin output control 0 Disables RTC1HZ pin output (1 Hz) 1 Enables RTC1HZ pin output (1 Hz) CLOE0Note RTCCL pin output control 0 Disables RTCCL pin output (32.768 kHz) 1 Enables RTCCL pin output (32.768 kHz) AMPM Note 2 CT2 3 CLOE1Note CLOE0Note AMPM 12-hour system/24-hour system selection 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system CT2 CT1 CT0 Fixed-cycle interrupt (INTRTC0) selection 0 0 0 Does not use fixed-cycle interrupts 0 0 1 Once in 0.5 second (synchronous with second count-up) 0 1 0 Once in 1 second (simultaneous with second count-up) 0 1 1 Once in 1 minute (every minute at 00 seconds) 1 0 0 Once in 1 hour (every hour at 00 minutes 00 seconds) 1 0 1 Once in 1 day (every day at 00 hours 00 minutes 00 seconds) 1 1 x Once in 1 month (one day every month at 00 hours 00 minutes 00 seconds a.m.) V850ES/JE3-H only. Cautions 1. Writing 0 to the RTCE bit while the RTCE bit is 1 is prohibited. Clear the RTCE bit by clearing the RC1PWR bit according to 11.4.8 Initializing real-time counter. 2. The RTC1HZ output operates as follows when the CLOE1 bit setting is changed. * When changed from 0 to 1: The RTC1HZ output outputs a 1 Hz pulse after two clocks or less (2 x 32.768 kHz). * When changed from 1 to 0: The RTC1HZ output is stopped (fixed to low level) after two clocks or less (2 x 32.768 kHz). 3. See 11.4.1 Initial settings and 11.4.2 Rewriting each counter during real-time counter operation for setting or changing the AMPM bit. Furthermore, re-set the RC1HOUR register when the AMPM bit is rewritten. 4. See 11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation when rewriting the CT2 to CT0 bits while the real-time counter operates (RC1PWR bit = 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 593 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (3) Real-time counter control register 2 (RC1CC2) The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 RC1CC2 WALE WALE R/W 6 0 Address: FFFFFADFH 5 4 0 0 3 2 1 0 0 0 RWST RWAIT Alarm interrupt (INTRTC1) operation control 0 Does not generate interrupt upon alarm match. 1 Generates interrupt upon alarm match. RWST Real-time counter wait state 0 Counter operating 1 Counting up of second to year counters stopped (Reading and writing of counter values enabled) This is a status flag indicating whether the RWAIT bit setting is valid. Read or write counter values after confirming that the RWST bit is 1. RWAIT Real-time counter wait control 0 Sets counter operation. 1 Stops count operation of second to year counters. (Counter value read/write mode) This bit controls the operation of the counters. Be sure to write 1 to this bit when reading or writing counter values. If the RC1SUBC register overflows while the RWAIT bit is 1, the overflow information is retained internally and the RC1SEC register is counted up after two clocks or less (2 x 32.768 kHz) after 0 is written to the RWAIT bit. However, if the second counter value is rewritten while the RWAIT bit is 1, the retained overflow information is discarded. Cautions 1. See 11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation when rewriting the WALE bit while the real-time counter operates (RC1PWR bit = 1). 2. Confirm that the RWST bit is set to 1 when reading or writing each counter value. 3. The RWST bit does not become 0 while each counter is being written, even if the RWAIT bit is set to 0. It becomes 0 when writing to each counter is completed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 594 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (4) Real-time counter control register 3 (RC1CC3) The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 7 RC1CC3 RINTE 6 CLOE2 Address: FFFFFAE0H 5 Note CKDIV 4 Note RINTE 2 1 0 0 ICT2 ICT1 ICT0 Interval interrupt (INTRTC2) control 0 Does not generate interval interrupt. 1 Generates interval interrupt. CLOE2Note RTCDIV pin output control 0 Disables RTCDIV pin output. 1 Enables RTCDIV pin output. CKDIVNote RTCDIV pin output frequency selection 0 Outputs 512 Hz (1.95 ms) from RTCDIV pin. 1 Outputs 16.384 kHz (0.061 ms) from RTCDIV pin. ICT2 Note 0 3 ICT1 Interval interrupt (INTRTC2) selection ICT0 6 0 0 0 2 /fXT (1.953125 ms) 0 0 1 27/fXT (3.90625 ms) 0 1 0 28/fXT (7.8125 ms) 0 1 1 29/fXT (15.625 ms) 1 0 0 210/fXT (31.25 ms) 1 0 1 211/fXT (62.5 ms) 1 1 x 212/fXT (125 ms) V850ES/JE3-H only. Cautions 1. See 11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation when rewriting the RINTE bit during real-time counter operation (RC1PWR bit = 1). 2. The RTCDIV output operates as follows when the CLOE2 bit setting is changed. * When changed from 0 to 1: A pulse set by the CKDIV bit is output after two clocks or less (2 x 32.768kHz). * When changed from 1 to 0: Output of the RTCDIV output is stopped after two clocks or less (fixed to low level, 2 x 32.768kHz)). 3. See 11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation when rewriting the ICT2 to ICT0 bits while the real-time counter operates (RC1PWR bit = 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 595 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (5) Sub-count register (RC1SUBC) The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts one second with a clock of 32.768 kHz. This register is read-only, in 16-bit units. Reset sets this register to 0000H. Cautions 1 When a correction is made by using the RC1SUBU register, the value may become 8000H or more. 2. This register is also cleared by writing to the second count register. 3. The value read from this register is not guaranteed if it is read during operation, because a changing value is read. After reset: 0000H 14 15 R 13 12 Address: FFFFFAD0H 11 10 9 8 7 6 5 4 3 2 1 0 RC1SUBC (6) Second count register (RC1SEC) The RC1SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the sub-counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside this range is set, the register value returns to the normal value after one period. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Setting the RC1SEC register to values other than 00 to 59 is prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1SEC register. After reset: 00H RC1SEC R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 R/W Address: FFFFFAD2H 0 Page 596 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (7) Minute count register (RC1MIN) The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code. This register can be read or written 8-bit units. Reset sets this register to 00H. Caution Setting a value other than 00 to 59 to the RC1MIN register is prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1MIN register. After reset: 00H RC1MIN R/W Address: FFFFFAD3H 0 (8) Hour count register (RC1HOUR) The RC1HOUR register is an 8-bit register that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. This register can be read or written 8-bit units. Reset sets this register to 12H. However, the value of this register is 00H if the AMPM bit is set to 1 after reset. Cautions 1. Bit 5 of the RC1HOUR register indicates a.m. (0) or p.m. (1) if AMPM = 0 (if the 12-hour system is selected). 2. Setting a value other than 01 to 12, 21 to 32 (AMPM bit= 0), or 00 to 23 (AMPM bit = 1) to the RC1HOUR register is prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1HOUR register. After reset: 12H RC1HOUR R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 R/W Address: FFFFFAD4H 0 Page 597 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER Table 11-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time. Table 11-3. Time Digit Display 12-Hour Display (AMPM Bit = 0) 24-Hour Display (AMPM Bit = 1) Time Time RC1HOUR Register Value RC1HOUR Register Value 0:00 a.m. 12 H 0:00 00H 1:00 a.m. 01 H 1:00 01 H 2:00 a.m. 02 H 2:00 02 H 3:00 a.m. 03 H 3:00 03 H 4:00 a.m. 04 H 4:00 04 H 5:00 a.m. 05 H 5:00 05 H 6:00 a.m. 06 H 6:00 06 H 7:00 a.m. 07 H 7:00 07 H 8:00 a.m. 08 H 8:00 08 H 9:00 a.m. 09 H 9:00 09 H 10:00 a.m. 10 H 10:00 10 H 11:00 a.m. 11 H 11:00 11 H 0:00 p.m. 32 H 12:00 12 H 1:00 p.m. 21 H 13:00 13 H 2:00 p.m. 22 H 14:00 14 H 3 :00 p.m. 23 H 15:00 15 H 4:00 p.m. 24 H 16:00 16 H 5:00 p.m. 25 H 17:00 17 H 6:00 p.m. 26 H 18:00 18 H 7:00 p.m. 27 H 19:00 19 H 8:00 p.m. 28 H 20:00 20 H 9:00 p.m. 29 H 21:00 21 H 10:00 p.m. 30 H 22:00 22 H 11:00 p.m. 31 H 23:00 23 H The RC1HOUR register value is displayed in 12 hour-format if the AMPM bit is 0 and in 24-hour format when the AMPM bit is 1. In 12-hour display, a.m. or p.m. is indicated by the fifth bit of RCHOUR: 0 indicating before noon (a.m.) and 1 indicating noon or afternoon (p.m.). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 598 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (9) Day count register (RC1DAY) The RC1DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows. * 01 to 31 (January, March, May, July, August, October, December) * 01 to 30 (April, June, September, November) * 01 to 29 (February in leap year) * 01 to 28 (February in normal year) When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Set a decimal value of 00 to 31 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 01H. Caution Setting a value other than 01 to 31 to the RC1DAY register is prohibited. Setting a value outside the above-mentioned count range, such as "February 30" is also prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1DAY register. After reset: 01H RC1DAY R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 R/W Address: FFFFFAD6H 0 Page 599 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (11) Day-of-week count register (RC1WEEK) The RC1WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the day-of-week count value. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 06 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H RC1WEEK 0 R/W 0 Address: FFFFFAD5H 0 0 0 Cautions 1. Setting a value other than 00 to 06 to the RC1WEEK register is prohibited. 2. Values corresponding to the month count register and day count register are not automatically stored to the day-of-week register. Be sure to set as follows after reset. Day of Week Remark RC1WEEK Sunday 00H Monday 01H Tuesday 02H Wednesday 03H Thursday 04H Friday 05H Saturday 06H See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1WEEK register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 600 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (11) Month count register (RC1MONTH) The RC1MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 01 to 12 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 01H. Caution Setting a value other than 01 to 12 to the RC1MONTH register is prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1MONTH register. After reset: 01H RC1MONTH R/W 0 0 Address: FFFFFAD7H 0 (12) Year count register (RC1YEAR) The RC1YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years. It counts up when the month counter overflows. Values 00, 04, 08, ..., 92, and 96 indicate a leap year. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz) later. Set a decimal value of 00 to 99 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Setting a value other than 00 to 99 to the RC1YEAR register is prohibited. Remark See 11.4.1 Initial settings, 11.4.2 Rewriting each counter during real-time counter operation, and 11.4.3 Reading each counter during real-time counter operation when reading or writing the RC1YEAR register. After reset: 00H R/W Address: FFFFFAD8H RC1YEAR R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 601 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (13) Watch error correction register (RC1SUBU) The RC1SUBU register is an 8-bit register that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (reference value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second counter register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Remarks 1. The RC1SUBU register can be rewritten only when the real-time counter is set to its initial values. Be sure to see 11.4.1 Initial settings. 2. See 11.4.9 Watch error correction example of real-time counter for details of watch error correction. After reset: 00H RC1SUBU R/W Address: FFFFFAD9H 7 6 5 4 3 2 1 0 DEV F6 F5 F4 F3 F2 F1 F0 DEV Setting of watch error correction timing 0 Corrects watch errors when RC1SEC (second counter) is at 00, 20, or 40 seconds (every 20 seconds). 1 Corrects watch errors when RC1SEC (second counter) is at 00 seconds (every 60 seconds). F6 Setting of watch error correction value 0 Increments the RC1SUBC count value by the value set using the F5 to F0 bits (positive correction). Expression for calculating increment value: (Setting value of F5 to F0 bits - 1) x 2 1 Decrements the RC1SUBC count value by the value set using the F5 to F0 bits (negative correction). Expression for calculating decrement value: (Inverted value of setting value of F5 to F0 bits + 1) x 2 If the F6 to F0 bit values are {1/0, 0, 0, 0, 0, 0, 1/0}, watch error correction is not performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 602 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (14) Alarm minute setting register (RC1ALM) The RC1ALM register is an 8-bit register that is used to set minutes of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. After reset: 00H RC1ALM R/W Address: FFFFFADAH 0 (15) Alarm hour setting register (RC1ALH) The RC1ALH register is an 8-bit register that is used to set hours of alarm. This register can be read or written in 8-bit units. Reset sets this register to 12H. Cautions 1. Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected. 2. Bit 5 of the RC1ALH register indicates a.m. (0) or p.m. (1) if the AMPM bit = 0 (12-hour system) is selected. After reset: 12H RC1ALH R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 R/W Address: FFFFFADBH 0 Page 603 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (16) Alarm day-of-week setting register (RC1ALW) The RC1ALW register is an 8-bit register that is used to set the day-of-week of the alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution See 11.4.5 Changing INTRTC1 interrupt setting during clock operation when rewriting the RC1ALW register while the real-time counter operates (RC1PWR bit = 1). After reset: 00H RC1ALW 0 R/W RC1ALW6 RC1ALW5 RC1ALW4 RC1ALW3 RC1ALW2 RC1ALW1 RC1ALW0 Saturday RC1ALW6 Address: FFFFFADCH Friday Thursday Wednesday Tuesday Monday Sunday Alarm interrupt day-of-week bit 6 0 Does not generate alarm interrupt if RC1WEEK = 06H (Saturday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 06H (Saturday). RC1ALW5 Alarm interrupt day-of-week bit 5 0 Does not generate alarm interrupt if RC1WEEK = 05H (Friday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 05H (Friday). RC1ALW4 Alarm interrupt day-of-week bit 4 0 Does not generate alarm interrupt if RC1WEEK = 04H (Thursday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 04H (Thursday). RC1ALW3 Alarm interrupt day-of-week bit 3 0 Does not generate alarm interrupt if RC1WEEK = 03H (Wednesday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 03H (Wednesday). RC1ALW2 Alarm interrupt day-of-week bit 2 0 Does not generate alarm interrupt if RC1WEEK = 02H (Tuesday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 02H (Tuesday). RC1ALW1 Alarm interrupt day-of-week bit 1 0 Does not generate alarm interrupt if RC1WEEK = 01H (Monday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 01H (Monday). RC1ALW0 Alarm interrupt day-of-week bit 0 0 Does not generate alarm interrupt if RC1WEEK = 00H (Sunday). 1 Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 00H (Sunday). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 604 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (a) Alarm interrupt setting examples (RC1ALM, RC1ALH, and RC1ALW setting examples) Tables 11-4 and 11-5 show setting examples if Sunday is RC1WEEK = 00, Monday is RC1WEEK = 01, Tuesday is RC1WEEK = 02, ***, and Saturday is RC1WEEK = 06. Table 11-4. Alarm Setting Example if AMPM = 0 (RC1HOUR Register 12-Hour Display) Register RC1ALW RC1ALH RC1ALM Sunday, 7:00 a.m. 01H 07H 00H Sunday/Monday, 00:15 p.m. 03H 32H 15H Monday/Tuesday/Friday, 5:30 p.m. 26H 25H 30H Everyday, 10:45 p.m. 7FH 30H 45H Alarm Setting Time Table 11-5. Alarm Setting Example if AMPM = 1 (RC1HOUR Register 24-Hour Display) Register RC1ALW RC1ALH RC1ALM Sunday, 7:00 01H 07H 00H Sunday/Monday, 12:15 03H 12H 15H Monday/Tuesday/Friday, 17:30 26H 17H 30H Everyday, 22:45 7FH 22H 45H Alarm Setting Time (17) Prescaler mode register 0 (PRSM0) The PRSM0 register is an 8-bit register that controls the generation of the real time counter count clock (fBRG). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset : 00H R/W Address : FFFFF8B0H < > PRSM0 0 0 0 BGCE0 0 0 BGCS01 BGCS00 Main clock operation enable 0 Disabled 1 Enabled BGCS01 BGCS00 Cautions1. BGCE0 Selection of real time counter source clock(fBGCS) 5 MHz 4 MHz 0 0 fX 200 ns 250 ns 0 1 fX/2 400 ns 500 ns 1 0 fX/4 800 ns 1 s 1 1 fX/8 1.6 s 2 s Do not change the values of the BGCS00 and BGCS01 bits during real time counteroperation. 2. Set the PRSM0 register before setting the BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 605 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (18) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H PRSCM0 R/W Address: FFFFF8B1H PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register during real time counter operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. The calculation for fBRG is shown below. fBRG = fBGCS/2N Remark fBGCS: Watch timer source clock set by the PRSM0 register N: Set value of the PRSCM0 register = 1 to 256 However, N = 256 when the PRSCM0 register is set to 00H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 606 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4 Operation 11.4.1 Initial settings The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation. Figure 11-2. Initial Setting Procedure Start RC1CC0.RC1PWR bit = 0 Setting RC1CKS RC1CC0.RC1PWR bit = 1 Setting AMPM and CT2 to CT0 Setting RC1SUBU Selects real-time counter (RTC) operation clock. Enables real-time counter (RTC) internal clock operation. Selects 12-hour system or 24-hour system and interrupt (INTRTC0). Sets watch error correction. Setting RC1SEC (Clearing RC1SUBC) Setting RC1MIN Setting RC1HOUR Setting RC1WEEK Setting RC1DAY Setting RC1MONTH Setting RC1YEAR Sets each count register. Clearing interrupt IF flag Clears interrupt request flag (RTC0IF) Clearing interrupt MK flag Clears interrupt mask flag (RTC0MK) RC1CC1.RTCE bit = 1 No Stops counter operation. Starts counter operation. INTRTC Intrrupt generated? Yes Reading counter R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 607 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.2 Rewriting each counter during real-time counter operation Set as follows when rewriting each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1). Figure 11-3. Rewriting Each Counter During Real-time Counter Operation Start No RC1CC2.RWST bit = 0? Checks whether previous writing to RC1SEC to RC1YEAR counters is completed. Yes No RC1CC2.RWAIT bit = 1 Stops RC1SEC to RC1YEAR counters. Counter value write/read mode RC1CC2.RWST bit = 1?Note Checks counter wait status. Yes Setting AMPM Selects watch counter display method. Writing RC1SEC Writing RC1MIN Writing RC1HOUR Writing RC1WEEK Writing RC1DAY Writing RC1MONTH Setting RC1YEAR Writes to each count register. RC1CC2.RWAIT bit = 0 Sets RC1SEC to RC1YEAR counter operation. End Note Be sure to confirm that RWST = 0 before setting STOP mode. Caution Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1 second. If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from RC1SUBC while RWAIT = 1, one carry can be internally retained. However, if two or more carries occur, the number of carries cannot be retained. Remark RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, and RC1YEAR may berewrite in any sequence. All the registers do not have to be set and only some registers may be read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 608 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.3 Reading each counter during real-time counter operation Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1, RTCE = 1). Figure 11-4. Reading Each Counter During Real-time Counter Operation Start No RC1CC2.RWST bit = 0? Checks whether previous writing to RC1SEC to RC1YEAR is completed. Yes No RC1CC2.RWAIT bit = 1 Stops RC1SEC to RC1YEAR counters. Counter value write/read mode RC1CC2.RWST bit = 1?Note Checks counter wait status. Yes Reading RC1SEC Reading RC1MIN Reading RC1HOUR Reading RC1WEEK Reading RC1DAY Reading RC1MONTH Setting RC1YEAR Reads each count register. RC1CC2.RWAIT bit = 0 Sets RC1SEC to RC1YEAR counter operation. End Note Caution Be sure to confirm that RWST = 0 before setting STOP mode. Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1 second. If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from RC1SUBC while RWAIT = 1, one carry can be internally retained. However, if two or more carries occur, the number of carries cannot be retained. Remark RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, and RC1YEAR may be read in any sequence. All the registers do not have to be set and only some registers may be read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 609 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock operates (PC1PWR = 1, RTCE =1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC0 interrupt signal during real-time counter operation (RC1PWR = 1), in order to mask the whiskers. Figure 11-5. Changing INTRTC0 Interrupt Setting During Real-time Counter Operation Start Setting RTC0MK bit Setting RC1CC1.CT2 to RC1CC1.CT0 Clearing RTC0IF flag Clearing RTC0MK flag Masks INTRTC0 interrupt signal. Changes INTRTC0 interrupt signal setting. Clears interrupt request flag. Unmasks INTRTC0 interrupt signal. End Remark See 22.3.4 Interrupt control register (xxICn) for details of the RTC0IF and RTC0MK bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 610 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (RC1PWR = 1, RTCE = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC1 interrupt signal during real-time counter operation (PC1PWR = 1, RTCE = 1), in order to mask the whiskers. Figure 11-6. Changing INTRTC1 Interrupt Setting During Real-time Counter Operation Start Setting RTC1MK bit RC1CC2.WALE bit = 0 Setting RC1ALM Setting RC1ALH Setting RC1ALW Masks interrupt signal (INTRTC1). Disables alarm interrupt. Sets alarm minute register. Sets alarm hour register Sets alarm day-of-week register Clearing RTC1IF flag Clears interrupt pending bit. Clearing RTC1MK flag Unmasks interrupt signal (INTRTC1). RC1CC2.WALE bit = 1 Enables alarm interrupt. End Remark See 22.3.4 Interrupt control register (xxICn) for details of the RTC1IF and RTC1MK bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 611 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.6 Initial INTRTC2 interrupt settings Set as follows to set the INTRTC1 interrupt (interval interrupt). Figure 11-7. INTRTC2 Interrupt Setting Start RC1CC0.RC1PWR bit = 1 Enables counter operation. Setting RC1CC3.ICT2 to RC1CC3.ICT0 bits <1> Selects INTRTC2 (interval) interrupt interval. RC1CC3.RINTE bit = 1 <2> Enables INTRTC2 (interval) interrupt. End Caution Set <1> and <2> simultaneously or set <1> first. Unintended waveform interrupts may occur if <2> is set first. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 612 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real-time counter clock operates (PC1PWR = 1, RTCE = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC2 interrupt signal during real-time counter operation (PC1PWR = 1, RTCE = 1), in order to mask the whiskers. Figure 11-8. Changing INTRTC2 Interrupt Setting During Real-time Counter Operation Start Setting RTC2MK bit Masks interrupt signal (INTRTC2). RC1CC3.RINTE bit = 1 Enables INTRTC2 (interval) interrupt. Setting RC1CC3.ICT2 to RC1CC3.ICT0 bits Selects INTRTC2 (interval) interrupt interval. Clearing RTC2IF flag Clearing RTC2MK flag Clears interrupt pending bit. Unmasks interrupt signal (INTRTC2). End Remark See 22.3.4 Interrupt control register (xxICn) for details of the RTC2IF and RTC2MK bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 613 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.8 Initializing real-time counter The procedure for initializing the real-time counter is shown below. Figure 11-9. Initializing Real-Time Counter Start Setting RTCnMK bit Masks interrupt signal (INTRTCn) RC1CC3.CLOE2 bit = 0 RTCDIV interrupt disable processing RC1CC1.CLOE1 bit = 0 RC1CC1.CLOE0 bit = 0 RTC1HZ interrupt disable processing RTCCL interrupt disable processing RC1CC0.RC1PWR bit = 0 Initializes real-time counter (RTC). Clearing RTCnIF flag Clearing RTCnMK flag Clears interrupt request bit. Unmasks interrupt signal (INTRTCn). End Remarks 1. See 22.3.4 Interrupt control register (xxICn) for details of the RTCnIF and RTCnMK bits. 2. n = 0 to 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 614 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER 11.4.9 Watch error correction example of real-time counter The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the V850ES/Jx3-H. Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed. Next, the timing chart when an error has occurred in the input clock intended to be 32.768 kHz but a 32.7681 kHz resonator has been connected when designing the system, and the RC1SUBC and RC1SEC count operations to correct the error are shown below. Figure 11-10. Watch Error Correction Example Watch count(32.768 kHz) RTCCLK (32.768 kHz) RC1SUBC 7FFFH 0000H 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 20 secondsNote 1 00 RC1SEC 01 20 19 Watch count (32.7681 kHz/no error correction) RTCCLK (32.7681 kHz) RC1SUBC 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 19.99994 secondsNote 2 19 01 00 RC1SEC 20 Watch count (32.7681 kHz/error correction(DEV bit = 0, F6 bit = 0, F5 to F0 bit = 000010)) RTCCLK (32.7681 kHz) 2 count numbers are added. RC1SUBC 0000H 2 count numbers are added. 7FFFH 8000H 8001H 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 0000H 7FFFH 8000H 8001H 20 secondsNote 3 RC1SEC 00 01 19 20 Notes 1. The RC1SEC counter counts 20 seconds every 32,768 cycles (0000H to 7FFFH) of the 32.768 kHz clock. 2. When 32,768 cycles (0000H to 7FFFH) of the 32.7681 kHz clock are input, the time counted by the RC1SEC counter is calculated as follows: 32,768/3,268.1 0.999997 seconds If this counting continues 20 times, the time is calculated as follows: (32,768/32,768.1) x 20 19.99994 seconds, which causes an error of 0.00006 seconds. 3. To precisely count 20 seconds by using a 32.7681 kHz clock, clear the DEV and F6 bits to 0 and set the F5 to F0 bits to 2H (000010B) in the RC1SUBU register. As a result, two additional cycles are counted every 20 seconds (when the RC1SEC counter count is 00, 20, and 40 seconds), so that the number of cycles counted at these points is not 32,768, but 32,770 (0000H to 8001H), which is exactly 20 seconds. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 615 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER As shown in Figure 12-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a negative error slower than 32.768 kHz occurs at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value. The RC1SUBC correction value is determined by using the RC1SUBU.F6 to RC1SUBU.F0 bits. The F6 bit is used to determine whether to increment or decrement RC1SUBC and the F5 to F0 bits to determine the RC1SUBC value. (1) Incrementing the RC1SUBC count value The RC1SUBC count value is incremented by the value set using the F5 to F0 bits, by setting the F6 bit to 0. Expression for calculating the increment value: (F5 to F0 bit value - 1) x 2 [Example of incrementing the RC1SUBC count value: F6 bit = 0] If 15H (010101B) is set to the F5 to F0 bits (15H - 1) x 2 = 40 (increments the RC1SUBC count value by 40) RC1SUBC count value = 32,768 + 40 = 32,808 (2) Decrementing the RC1SUBC count value The RC1SUBC count value is decremented by an inverted value of the value set using the F5 to F0 bits, by setting the F6 bit to 1. Expression for calculating the decrement value: (Inverted value of F5 to F0 bit value + 1) x 2 [Example of decrementing the RC1SUBC count value: F6 bit = 1] If 15H (010101B) is set to the F5 to F0 bits Inverted data of 15H (010101B) = 2AH (101010B) (2AH + 1) x 2 = 86 (decrements the RC1SUBC count value by 86) RC1SUBC count value = 32,768 - 86 = 32,682 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 616 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER (3) DEV bit The DEV bit determines when the setting by the F6 to F0 bits is enabled. The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time. Table 11-6. DEV Bit Setting DEV Bit Value Timing of Reflecting Value to RC1SUBC 0 When RC1SEC is 00, 20, or 40 seconds. 1 When RC1SEC is 00 seconds. [Example when 0010101B is set to F6 to F0 bits] * If the DEV bit is 0 The RC1SUBC count value is 32,808 at 00, 20, or 40 seconds. Otherwise, it is 32,768. * IF DEV bit is 1 The RC1SUBC count value is 32,808 at 00 seconds. Otherwise, it is 32,768. As described above, the RC1SUBC count value is corrected every 20 seconds or 60 seconds, instead of every second, in order to match the RC1SUBC count value with the deviation width of the resonator. The range in which the resonator frequency can be actually corrected is shown below. * If the DEV bit is 0: 32.76180000 kHz to 32.77420000 kHz * If the DEV bit is 1: 32.76593333 kHz to 32.77006667 kHz The range in which the frequency can be corrected when the DEV bit is 0 is three times wider than when the DEV bit is 1. However, the accuracy of setting the frequency when the DEV bit is 1 is three times that when the DEV bit is 0. Tables 11-7 and 11-8 show the setting values of the DEV, and F6 to F0 bits, and the corresponding frequencies that can be corrected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 617 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 11 REAL-TIME COUNTER Table 11-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0 F6 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) 0 000000 No correction - 0 000001 No correction - 0 000010 Increments RC1SUBC count value by 2 once every 20 seconds 32.76810000 kHz 0 000011 Increments RC1SUBC count value by 4 once every 20 seconds 32.76820000 kHz 0 000100 Increments RC1SUBC count value by 6 once every 20 seconds .. . . 32.76830000 kHz 0 111011 Increments RC1SUBC count value by 120 once every 20 seconds 32.77400000 kHz 0 111110 Increments RC1SUBC count value by 122 once every 20 seconds 32.77410000 kHz 32.77420000 kHz (upper limit) 0 111111 Increments RC1SUBC count value by 124 once every 20 seconds 1 000000 No correction - 1 000001 No correction - 1 000010 Decrements RC1SUBC count value by 124 once every 20 seconds 32.76180000 kHz (lower limit) 1 000011 Decrements RC1SUBC count value by 122 once every 20 seconds 32.76190000 kHz 1 000100 Decrements RC1SUBC count value by 120 once every 20 seconds . .. . 32.76200000 kHz 1 11011 Decrements RC1SUBC count value by 6 once every 20 seconds 32.76770000 kHz 1 11110 Decrements RC1SUBC count value by 4 once every 20 seconds 32.76780000 kHz 1 11111 Decrements RC1SUBC count value by 2 once every 20 seconds 32.76790000 kHz Table 11-8. Range of Frequencies That Can Be Corrected When DEV Bit = 1 F6 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) 0 000000 No correction - 0 000001 No correction - 0 000010 Increments RC1SUBC count value by 2 once every 60 seconds 32.76803333 kHz 0 000011 Increments RC1SUBC count value by 4 once every 60 seconds 32.76806667 kHz 0 000100 Increments RC1SUBC count value by 6 once every 60 seconds . .. . 32.76810000 kHz 0 111011 Increments RC1SUBC count value by 120 once every 60 seconds 32.77000000 kHz 0 111110 Increments RC1SUBC count value by 122 once every 60 seconds 32.77003333 kHz 32.77006667 kHz (upper limit) 0 111111 Increments RC1SUBC count value by 124 once every 60 seconds 1 000000 No correction - 1 000001 No correction - 1 000010 Decrements RC1SUBC count value by 124 once every 60 seconds 32.76593333 kHz (lower limit) 1 000011 Decrements RC1SUBC count value by 122 once every 60 seconds 32.76596667 kHz 1 000100 Decrements RC1SUBC count value by 120 once every 60 seconds .. . . 32.76600000 kHz 1 11011 Decrements RC1SUBC count value by 6 once every 60 seconds 32.76790000 kHz 1 11110 Decrements RC1SUBC count value by 4 once every 60 seconds 32.76793333 kHz 1 11111 Decrements RC1SUBC count value by 2 once every 60 seconds 32.76796667 kHz R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 618 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 In the V850ES/JC3-H and V850ES/JE3-H, one channel of watchdog timer 2 is provided. 12.1 Functions Watchdog timer 2 has the following functions. * Default-start watchdog timerNote 1 Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)Note 2 * Input from main clock, internal oscillation clock, and subclock selectable as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes once, even if the default settings (reset mode, interval time: fR/219) do not need to be changed. 2. For the non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), see 22.2.2 (2) From INTWDT2 signal. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 619 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 12-1. Block Diagram of Watchdog Timer 2 fXX/27 fR/23 Clock input controller 16-bit counter 2 fX/216 to fX/223, fR/212 to fR/219 Selector 3 Clear 0 Watchdog timer enable register (WDTE) Output controller INTWDT2 WDT2RES (internal reset signal) 3 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Watchdog timer mode register 2 (WDTM2) Internal bus Remark fXX: Main clock oscillation frequency fR: Internal oscillation clock frequency INTWDT2: Non-maskable interrupt request signal from watchdog timer 2 WDTRES2: Watchdog timer 2 reset signal Watchdog timer 2 includes the following hardware. Table 12-1. Configuration of Watchdog Timer 2 Item Control registers Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 620 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock After reset: 67H WDTM2 R/W Address: FFFFF6D0H 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 WDM21 WDM20 0 0 Stops operation 0 1 Non-maskable interrupt request mode (generation of INTWDT2 signal) 1 - Reset mode (generation of WDT2RES signal) Selection of operation mode of watchdog timer 2 Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 12-2 Watchdog Timer 2 Clock Selection. 2. Although watchdog timer 2 can be stopped just by stopping operation of the internal oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly generated and the counter is reset. 4. To intentionally generate an overflow signal, write data to the WDTM2 register twice, or write a value other than "ACH" to the WDTE register once. However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the WDTM2 register twice, or a value other than "ACH" is written to the WDTE register once. 5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be set to 1, set the WDCS23 bit to 1 (2n/fXX is selected and the clock can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 621 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 Table 12-2. Watchdog Timer 2 Clock Selection WDCS2 WDCS2 WDCS2 WDCS2 WDCS2 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 Selected Clock 41.0 ms 18.6 ms 10.2 ms 81.9 ms 37.2 ms 20.5 ms 14 163.8 ms 74.5 ms 41.0 ms 15 327.7 ms 148.9 ms 81.9 ms 16 655.4 ms 297.9 ms 163.8 ms 17 1,310.7 ms 595.8 ms 327.7 ms 18 2,621.4 ms 1191.6 ms 655.4 ms 19 5,242.9 ms 2383.1 ms 1,310.7 ms 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR (Default value) fXX = 24 MHz fXX = 32 MHz fXX = 48 MHz 19 21.8 ms 16.4 ms 10.9 ms 20 43.7 ms 32.8 ms 21.8 ms 21 87.4 ms 65.5 ms 43.7 ms 22 174.8 ms 131.1 ms 87.4 ms 23 349.5 ms 262.1 ms 174.8 ms 24 699.1 ms 524.3 ms 349.5 ms 25 1398.1 ms 1048.6 ms 699.1 ms 26 2796.2 ms 2097.2 ms 1398.1 ms 2 /fXX 2 /fXX 1 0 1 0 2 /fXX 1 0 1 1 2 /fXX 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 400 kHz (MAX.) 13 0 1 220 kHz (TYP.) 12 2 /fR 0 0 100 kHz (MIN.) 2 /fXX 2 /fXX 2 /fXX 0 1 2 /fXX 1 x 1 x 1 x 1 x 1 x 1 x 1 0 1 2 /fXT 1 x 1 1 0 2 /fXT 1 x fXT = 32.768 kHz 0 0 0 0 1 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 0 1 1 0 1 0 1 0 1 0 1 9 15.625 ms 10 31.25 ms 11 62.5 ms 12 125 ms 13 250 ms 14 500 ms 15 1,000 ms 16 2,000 ms 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT Page 622 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH. After reset: 9AH R/W Address: FFFFF6D1H WDTE Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. To intentionally generate an overflow signal, write a value other than "ACH" to the WDTE register once, or write data to the WDTM2 register twice. However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the WDTM2 register twice, or a value other than "ACH" is written to the WDTE register once. 4. The read value of the WDTE register is "9AH" (which differs from written value "ACH"). 12.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped. The WDTM2.WDCS24 to WDTM2.WDCS20 bits are used to select the watchdog timer 2 loop detection time interval. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation has started, write ACH to WDTE within the loop detection time interval. If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a nonmaskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDTM2.WDM21 and WDTM2.WDM20 bits. When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock. To not use watchdog timer 2, write 00H to the WDTM2 register. For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 22.2.2 (2) From INTWDT2 signal. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 623 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function The real-time output function transfers the data preset to the RTBL0 and RTBH0 registers to the output latches via hardware and outputs the data to an external device, at the same time as a timer interrupt occurs. The pins through which the data is output to an external device constitute a port called the real-time output (RTO) port. Because signals without jitter can be output by using RTO, it is suitable for controlling a stepper motor. In the V850ES/JC3-H and V850ES/JE3-H, one 4-bit real-time output port channel is provided. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 624 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration The block diagram of RTO is shown below. Internal bus Figure 13-1. Block Diagram of RTO Real-time output buffer register 0H (RTBH0) Real-time output latch 0H 2 Real-time output buffer register 0L (RTBL0) Real-time output latch 0L 2 RTP04, RTP05 RTP02, RTP03 INTTAA0CC0 Transfer trigger (H) Selector INTTAA4CC0 Transfer trigger (L) 2 RTPOE0 RTPEG0 BYTE0 EXTR0 Real-time output port control register 0 (RTPC0) 2 RTPM05 RTPM04 RTPM03 RTPM02 Real-time output port mode register 0 (RTPM0) RTO includes the following hardware. Table 13-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 625 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance. These registers are each mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. If an operation mode of 2 bits x 2 channel is specified (RTPC0.BYTE0 bit = 0), data can be individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 4 bits x 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these registers can be read at once by specifying the address of either of these registers. Table 13-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated. After reset: 00H R/W Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H RTBL0 RTBL03 RTBL02 0 RTBH0 0 0 0 RTBH05 RTBH04 Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always set 0. 2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock Table 13-2. Operation During Manipulation of RTBL0 and RTBH0 Registers Operation Mode Register to Be Manipulated 2 bits x 2 channel 4 bits x 1 channel Note Read Higher 4 Bits Write Lower 4 Bits Higher 4 Bits Lower 4 Bits RTBL0 RTBH0 RTBL0 Invalid RTBL0 RTBH0 RTBH0 RTBL0 RTBH0 Invalid RTBL0 RTBH0 RTBL0 RTBH0 RTBL0 RTBH0 RTBH0 RTBL0 RTBH0 RTBL0 Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-time output trigger is generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 626 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.3 Registers RTO is controlled using the following two registers. * Real-time output port mode register 0 (RTPM0) * Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H RTPM0 R/W 0 0 RTPM0m Address: RTPM0 FFFFF6E4H RTPM05 RTPM04 RTPM03 RTPM02 0 0 Control of real-time output port (m = 2 to 5) 0 Real-time output disabled 1 Real-time output enabled Cautions 1. By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits enabled for real-time output among the RTP02 to RTP05 signals perform realtime output, and the bits set to port mode output 0. 2. If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins (RTP02 to RTP05) all output 0, regardless of the RTPM0 register setting. 3. In order to use this register for the real-time output pins (RTP02 to RTP05), set these pins as real-time output port pins using the PMC and PFC registers. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 627 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 13-3. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF6E5H < > RTPC0 RTPOE0 RTPEG0 BYTE0 RTPOE0 0 0 0 0 Control of real-time output operation 0 Disables operation 1 Enables operation Note 1 Valid edge of INTTP0CC0 signal RTPEG0 0 Falling edgeNote 2 1 Rising edge BYTE0 EXTR0 Specification of channel configuration for real-time output 0 2 bits x 2 channels 1 4 bits x 1 channels Notes 1. When the real-time output operation is disabled (RTPOE0 bit = 0), all real-time output pins (RTP02 to RTP05) output "0". 2. The INTTAA0CC0 signal is output for 1 clock of the count clock selected by TAA0. Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when the RTPOE0 bit = 0. Table 13-3. Operation Modes and Output Triggers of Real-Time Output Port BYTE0 EXTR0 0 0 Operation Mode 2 bits x 2 channel 1 1 0 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 RTBH0 (RTP04, RTP05) - INTTAA4CC0 4 bits x 1 channel RTBL0 (RTP02, RTP03) INTTAA4CC0 INTTAA0CC0 INTTAA4CC0 INTTAA0CC0 Page 628 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits). Of the transferred data, only the data of the bits for which real-time output is enabled by the RTPM0 register is output from the RTP01 to RTP05 bits. The bits for which real-time output is disabled by the RTPM0 register output 0. If the real-time output operation is disabled by clearing the RTPOE0 bit to 0, the RTP01 to RTP05 signals output 0 regardless of the setting of the RTPM0 register. Figure 13-2. Example of Operation Timing of RTO0 (When EXTR1 Bit = 0, BYTE0 Bit = 0) INTTAA4CC0 (internal) INTTAA0CC0 (internal) CPU operation A B RTBH0 D01 RTBL0 RT output latch 0 (H) RT output latch 0 (L) A B D02 A B D03 D11 D13 D02 D11 B D04 D12 D01 A D14 D03 D12 D04 D13 D14 A: Software processing by INTTAA4CC0 interrupt request (RTBH0 write) B: Software processing by INTTAA0CC0 interrupt request (RTBL0 write) Remark For the operation during standby, see CHAPTER 24 STANDBY FUNCTION. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 629 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. * Set the alternate-function pins of port 2 or port 5 After setting the PFC2.PFC2m bit and PFCE2.PFCE2m bit to the RTO pin, set the PMC2.PMC2m bit to 1 (m = 0 to 3). After setting the PFC5.PFC5m bit and PFCE5.PFCE5m bit to the RTO pin, set the PMC5.PMC5m bit to 1 (m = 0 to 5). * Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. * Channel configuration: Select the trigger and valid edge. Set the RTPC0.EXTR0, RTPC0.BYTE0, and RTPC0.RTPEG0 bits. * Set the initial values to the RTBH0 and RTBL0 registersNote 1. (3) Enable real-time output. Set the RTPOE0 bit = 1. (4) Set the next output value to the RTBH0 and RTBL0 registers by the time the selected transfer trigger is generatedNote 2. (5) Sequentially set the next real-time output value to the RTBH0 and RTBL0 registers via interrupt servicing corresponding to the selected trigger. Notes 1. If the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 0, that value is transferred to real-time output latches 0H and 0L. 2. Even if the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 1, data is not transferred to real-time output latches 0H and 0L. 13.6 Cautions (1) Prevent the following conflicts by software. * Conflict between real-time output disable/enable switching (RTPOE0 bit) and the selected real-time output trigger. * Conflict between writing to the RTBH0 and RTBL0 registers in the real-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOE0 bit = 0). (3) Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0 bit = 0 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 630 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER CHAPTER 14 A/D CONVERTER 14.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 10 analog input signal channels (ANI0 to ANI9). The A/D converter has the following features. { 10-bit resolution { 10 channels (JE3-H (64pin)) 6 channels (JC3-H (48pin)) 5 channels (JC3-H (40pin)) { Successive approximation method { Operating voltage: AVREF0 = 3.0 to 3.6 V { Analog input voltage: 0 V to AVREF0 { The following functions are provided as operation modes. * Continuous select mode * Continuous scan mode * One-shot select mode * One-shot scan mode { The following functions are provided as trigger modes. * Software trigger mode * External trigger mode (external, 1) * Timer trigger mode { Power-fail monitor function (conversion result compare function) 14.2 Functions (1) 10-bit resolution A/D conversion An analog input channel is selected from ANI0 to ANI9, and an A/D conversion operation is repeated at a resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is generated. (2) Power-fail detection function This function is used to detect a drop in the battery voltage. The result of A/D conversion (the value of the ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated only when a specified comparison condition is satisfied (n = 0 to 9). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 631 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.3 Configuration The block diagram of the A/D converter is shown below. Figure 14-1. Block Diagram of A/D Converter AVREF0 ANI0 ANI1 ANI2 : : : : : ANI9 Selector Sample & hold circuit ADA0CE bit ADA0CE bit Voltage comparator & Compare voltage generation DAC AVSS SAR ADA0TMD1 bit ADA0TMD0 bit INTAD INTTAA2CC1 TQTADTO Notes1, 2 Edge detection ADTRG Selector INTTAA2CC0 Controller ADA0CR0 ADA0CR1 ADA0CR2 : : ADA0CR8 ADA0ETS0 bit ADA0ETS1 bit ADA0M0 Controller ADA0PFE bit ADA0PFC bit ADA0M1 ADA0M2 ADA0S ADA0CR9 Voltage comparator ADA0PFT ADA0PFM Internal bus Notes1. 2. V850ES/JE3-H only The timer trigger signal from 6-phase PWM output circuit (TMQOP) The A/D converter includes the following hardware. Table 14-1. Configuration of A/D Converter Item Configuration Analog inputs 10 channels (ANI0 to ANI9 pins) Registers Successive approximation register (SAR) A/D conversion result registers 0 to 9 (ADA0CR0 to ADA0CR9) A/D conversion result registers 0H to 9H (ADCR0H to ADCR9H): Only higher 8 bits can be read Control registers A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M9) A/D converter channel specification register 0 (ADA0S) Power fail compare mode register (ADA0PFM) Power fail compare threshold value register (ADA0PFT) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 632 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) The SAR compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR are transferred to the ADA0CRn register. Remark n = 0 to 9 (2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH) The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 10 registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input. (The lower 6 bits are fixed to 0.) Remark n = 0 to 5 (V850ES/JC3-H (40 pin)) = 0 to 6 (V850ES/JC3-H (48 pin)) = 0 to 9 (V850ES/JE3-H) (3) A/D converter mode register 0 (ADA0M0) This register specifies the operation mode and controls the conversion operation by the A/D converter. (4) A/D converter mode register 1 (ADA0M1) This register sets the conversion time of the analog input signal to be converted. (5) A/D converter mode register 2 (ADA0M2) This register sets the hardware trigger mode. (6) A/D converter channel specification register (ADA0S) This register sets the input port that inputs the analog voltage to be converted. (7) Power-fail compare mode register (ADA0PFM) This register sets the power-fail monitor mode. (8) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the threshold value that is compared with the value of A/D conversion result register nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADA0CRnH). (9) Controller The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and generates the INTAD signal only when a specified comparison condition is satisfied. (10) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (11) Voltage comparator The voltage comparator compares a voltage value that has been sampled and held with the output voltage of the compare voltage generation DAC. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 633 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (13) ANI0 to ANI9 pins These are analog input pins for the 10 A/D converter channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins. Caution Make sure that the voltages input to the ANI0 to ANI9 pins do not exceed the rated values. In particular if a voltage of AVREF0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (14) AVREF0 pin This is the pin used to input the reference voltage of the A/D converter. Always make the potential at this pin the same as that at the VDD pin even when the A/D converter is not used. The signals input to the ANI0 to ANI9 pins are converted to digital signals based on the voltage applied between the AVREF0 and AVSS pins. (15) AVSS pin This is the ground potential pin of the A/D converter. Always make the potential at this pin the same as that at the VSS pin even when the A/D converter is not used. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 634 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.4 Registers The A/D converter is controlled by the following registers. * A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) * A/D converter channel specification register 0 (ADA0S) * Power-fail compare mode register (ADA0PFM) The following registers are also used. * A/D conversion result register n (ADA0CRn) * A/D conversion result register nH (ADA0CRnH) * Power-fail compare threshold value register (ADA0PFT) (1) A/D converter mode register 0 (ADA0M0) The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations. This register can be read or written in 8-bit or 1-bit units. However, the ADA0EF bit is read-only. Reset sets this register to 00H. (1/2) After reset: 00H R/W Address: FFFFF200H < > < > ADA0M0 ADA0CE 0 ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD ADA0EF A/D conversion control ADA0CE 0 Stops A/D conversion 1 Enables A/D conversion ADA0MD1 ADA0MD0 Specification of A/D converter operation mode 0 0 Continuous select mode 0 1 Continuous scan mode 1 0 One-shot select mode 1 1 One-shot scan mode ADA0ETS1 ADA0ETS0 Specification of external trigger (ADTRG pin) input valid edge R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 0 No edge detection 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Detection of both rising and falling edges Page 635 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (2/2) Trigger mode specification ADA0TMD 0 Software trigger mode 1 External trigger mode/timer trigger mode A/D converter status display ADA0EF 0 A/D conversion stopped 1 A/D conversion in progress Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock 2. A write operation to bit 0 is ignored. 3. Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while A/D conversion is enabled (ADA0CE bit = 1). 4. In the following modes, write data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT registers while A/D conversion is stopped (ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode in high-speed conversion mode If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written in other modes during A/D conversion (ADA0EF bit = 1), the following will be performed according to the mode. * In software trigger mode A/D conversion is stopped and started again from the beginning. * In hardware trigger mode A/D conversion is stopped, and the trigger standby status is set. 5. To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the highspeed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0CE bit = 1). 6. When not using the A/D converter, stop the operation by setting the ADA0CE bit to 0 to reduce the power consumption. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 636 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H. After reset: 00H ADA0M1 ADA0HS1 R/W 0 Address: FFFFF201H 0 0 ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0 ADA0HS1 Specification of normal conversion mode/high-speed mode (A/D conversion time) 0 Normal conversion mode 1 High-speed conversion mode Cautions 1. Changing the ADA0M1 register is prohibited while A/D conversion is enabled (ADA0M0.ADA0CE bit = 1). 2. To select the external trigger mode/timer trigger mode (ADA0M0.ADA0TMD bit = 1), set the high-speed conversion mode (ADA0HS1 bit = 1). Do not input a trigger during the stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0CE bit = 1). 3. Be sure to clear bits 6 to 4 to "0". Remark For A/D conversion time setting examples, see Tables 14-2 and 14-3. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 637 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Table 14-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0FR3 to A/D Conversion Time ADA0FR0 Stabilization Time Bits + Conversion Time + Wait Time 48 MHz 32 MHz 24 MHz 0000 26/fXX + 52/fXX + 54/fXX Setting prohibited Setting prohibited 5.50 s 0001 52/fXX + 104/fXX + 106/fXX 5.46 s 8.19 s Setting prohibited 0010 78/fXX + 156/fXX + 158/fXX 8.17 s Setting prohibited Setting prohibited 0011 100/fXX + 208/fXX + 210/fXX Setting prohibited Setting prohibited Setting prohibited 0100 100/fXX + 260/fXX + 262/fXX Setting prohibited Setting prohibited Setting prohibited 0101 100/fxx + 312/fxx + 314/fXX Setting prohibited Setting prohibited Setting prohibited 0110 100/fxx + 364/fxx + 366/fXX Setting prohibited Setting prohibited Setting prohibited 0111 100/fXX + 416/fXX + 418/fXX Setting prohibited Setting prohibited Setting prohibited 1000 100/fXX + 468/fXX + 470/fXX Setting prohibited Setting prohibited Setting prohibited 1001 100/fXX + 520/fXX + 522/fXX Setting prohibited Setting prohibited Setting prohibited 1010 100/fXX + 572/fXX + 574/fXX Setting prohibited Setting prohibited Setting prohibited 1011 100/fXX + 624/fXX + 626/fXX Setting prohibited Setting prohibited Setting prohibited 1100 100/fXX + 676/fXX + 678/fXX Setting prohibited Setting prohibited Setting prohibited 1101 100/fXX + 728/fXX + 730/fXX Setting prohibited Setting prohibited Setting prohibited 1110 100/fXX + 780/fXX + 782/fXX Setting prohibited Setting prohibited Setting prohibited 1111 100/fXX + 832/fXX + 834/fXX Setting prohibited Setting prohibited Setting prohibited Other than above Remark Setting prohibited Stabilization time: A/D converter setup time (1 s or longer) Conversion time: Actual A/D conversion time (2.17 to 9.75 s) Wait time: Wait time inserted before the next conversion fXX: Main clock frequency In the normal conversion mode, the conversion is started after the stabilization time elapses after the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75 s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated after the wait time elapses. Because the conversion operation is stopped during the wait time, operating current can be reduced. Cautions 1. Set as 2.17 s conversion time 9.75 s. 2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization time end timing conflicts with writing to these registers, or if the stabilization time end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. If a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted. Therefore do not set the trigger input interval and control register write interval to 64 clocks or lower. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 638 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Table 14-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to A/D Conversion Time ADA0FR0 Conversion Time Bits (+ Stabilization Time) 48 MHz 32 MHz 24 MHz 0000 52/fXX (+26/fXX) Setting prohibited Setting prohibited 2.17 s 0001 104/fXX (+52/fXX) 2.17 s 3.25 s 4.33 s 0010 156/fXX (+78/fXX) 3.25 s 4.88 s 6.50 s 0011 208/fXX (+100/fXX) 4.33 s 6.50 s 8.67 s 0100 260/fXX (+100/fXX) 5.42 s 8.13 s Setting prohibited 0101 312/fXX (+100/fXX) 6.50 s 9.75 s Setting prohibited 0110 364/fXX (+100/fXX) 7.58 s Setting prohibited Setting prohibited 0111 416/fXX (+100/fXX) 8.67 s Setting prohibited Setting prohibited 1000 468/fXX (+100/fXX) 9.75 s Setting prohibited Setting prohibited 1001 520/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1010 572/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1011 624/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1100 676/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1101 728/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1110 780/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited 1111 832/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Other than above Remark Setting prohibited Stabilization time: A/D converter setup time (1 s or longer) Conversion time: Actual A/D conversion time (2.17 to 9.75 s) fXX: Main clock frequency In the high-speed conversion mode, the conversion is started after the stabilization time elapses after the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75 s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion ends. In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the A/D converter remains running). Cautions 1. Set as 2.17 s conversion time 9.75 s. 2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input are prohibited during the stabilization time. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 639 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ADA0M2 R/W Address: FFFFF203H 7 6 5 4 3 2 0 0 0 0 0 0 ADA0TMD1 ADA0TMD0 1 0 ADA0TMD1 ADA0TMD0 Specification of hardware trigger mode 0 0 External trigger mode (when ADTRG pin valid edge is detected) 0 1 Timer trigger mode 0 (when INTTAA2CC0 interrupt request is generated) 1 0 Timer trigger mode 1 (when INTTAA2CC1 interrupt request is generated) 1 1 Timer trigger mode 2 (TQTADT0 signal) Cautions 1. In the following modes, write data to the ADA0M2 register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode in high-speed conversion mode 2. Be sure to clear bits 7 to 2 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 640 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (4) Analog input channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ADA0S R/W 0 0 Address: FFFFF202H 0 0 ADA0S3 ADA0S2 ADA0S1 ADA0S0 Scan mode 0 0 0 ANI0 ANI0 0 0 0 1 ANI1 ANI0, ANI1 0 0 1 0 ANI2 ANI0 to ANI2 0 0 1 1 ANI3 ANI0 to ANI3 0 1 0 0 ANI4 ANI0 to ANI4 0 1 1 0 1 1 0 Note1 ANI0 to ANI5 Note2 ANI0 to ANI6 Note2 ANI5 ANI6 0 1 1 1 ANI7 ANI0 to ANI7 1 0 0 0 ANI8Note2 ANI0 to ANI8 1 Note2 ANI0 to ANI9 1 2. Select mode 0 0 Notes1. ADA0S3 ADA0S2 ADA0S1 ADA0S0 0 0 ANI9 V850ES/JC3-H (48 pin), V850ES/JE3-H only V850ES/JE3-H only Cautions 1. In the following modes, write data to the ADA0S register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode in high-speed conversion mode 2. Be sure to clear bits 7 to 4 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 641 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, the ADA0CRn register is used for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read to the higher 10 bits of the ADA0CRn register, and 0 is read to the lower 6 bits. The higher 8 bits of the conversion result are read to the ADA0CRnH register. Caution Accessing the ADA0CRn and ADA0CRnH registers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock After reset: Undefined ADA0CRn (n = 0 to 9) R Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H, ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H, ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH, ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH, ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 After reset: Undefined R 0 0 0 0 0 0 Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H, ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H, ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH, ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH, ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H ADA0CRnH 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 (n = 0 to 9) Caution A write operation to the ADA0M0 and ADA0S registers may cause the contents of the ADA0CRn register to become undefined. After the conversion, read the conversion result before writing to the ADA0M0 and ADA0S registers. Correct conversion results may not be read at a timing other than the above. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 642 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI9) and the A/D conversion result (ADA0CRn register) is as follows. SAR = INT ( VIN AVREF0 x 1,024 + 0.5) ADA0CRNote = SAR x 64 Or, (SAR - 0.5) x AVREF0 1,024 VIN < (SAR + 0.5) x AVREF0 1,024 INT( ): Function that returns the integer of the value in ( ) VIN: Analog input voltage AVREF0: AVREF0 pin voltage ADA0CR: Value of ADA0CRn register Note The lower 6 bits of the ADA0CRn register are fixed to 0. The following shows the relationship between the analog input voltage and the A/D conversion results. Figure 14-2. Relationship Between Analog Input Voltage and A/D Conversion Results ADA0CRn SAR A/D conversion results 1,023 FFC0H 1,022 FF80H 1,021 FF40H 3 00C0H 2 0080H 1 0040H 0 0000H 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 1 2,048 1,024 2,048 1,024 2,048 Input voltage/AVREF0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 643 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W <7> ADA0PFM Address: FFFFF204H 6 ADA0PFE ADA0PFC ADA0PFE 5 4 3 2 1 0 0 0 0 0 0 0 Selection of power-fail compare enable/disable 0 Power-fail compare disabled 1 Power-fail compare enabled ADA0PFC Selection of power-fail compare mode 0 Generates an interrupt request signal (INTAD) when ADA0CRnH ADA0PFT 1 Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the value of the ADA0CRnH register specified by the ADA0S register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register and the INTAD signal is generated. If it does not match, however, the interrupt signal is not generated. 2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the contents of the ADA0CR0H register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, however, the INTAD signal is not generated. Regardless of the comparison result, the scan operation is continued and the conversion result is stored in the ADA0CRn register until the scan operation is completed. However, the INTAD signal is not generated after the scan operation has been completed. 3. In the following modes, write data to the ADA0PFM register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode in high-speed conversion mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 644 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 7 6 Address: FFFFF205H 5 4 3 2 1 0 ADA0PFT Caution In the following modes, write data to the ADA0PFT register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode in high-speed conversion mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 645 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.5 Operation 14.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode. <2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until A/D conversion is complete. <4> Set bit 9 of the successive approximation register (SAR), and set the compare voltage generation DAC to (1/2) AVREF0. <5> The voltage difference between the voltage of the compare voltage generation DAC and the analog input voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the SAR remains set. If it is lower than (1/2) AVREF0, the MSB is reset. <6> Next, bit 8 of the SAR is automatically set and the next comparison is started. Depending on the value of bit 9, to which a result has been already set, the compare voltage generation DAC is selected as follows. * Bit 9 = 1: (3/4) AVREF0 * Bit 9 = 0: (1/4) AVREF0 This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. Analog input voltage Compare voltage: Bit 8 = 1 Analog input voltage Compare voltage: Bit 8 = 0 <7> This comparison is continued to bit 0 of the SAR. <8> When comparison of the 10 bits is complete, the valid digital result remains in the SAR, and is then transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal (INTAD) is generated. <9> In one-shot select mode, conversion is stoppedNote. In one-shot scan mode, conversion is stopped after scanning Note once . In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel. Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. Remark The trigger standby status means the status after the stabilization time has elapsed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 646 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.5.2 Conversion operation timing Figure 14-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Wait Conversion time Wait time Setup Sampling INTAD signal Stabilization time 2/fXX (MAX.) Sampling time 0.5/fXX (2) Operation in high-speed conversion mode (ADA0HS1 bit = 1) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Sampling A/D conversion INTAD signal Stabilization time 2/fXX (MAX.) Remark Conversion time Sampling time 0.5/fXX The above timings are applicable when a trigger is generated within the stabilization time. If a trigger is generated after the stabilization time has elapsed, a trigger response time is inserted. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 647 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.5.3 Trigger mode The timing of starting the conversion operation is specified by setting the trigger mode. The trigger mode includes the software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits. (1) Software trigger mode When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI9 pin) specified by the ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated. If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous select/scan mode, the next conversion is repeated, unless the ADA0CE bit is cleared to 0 after completion of the conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan mode. When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress). If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is aborted and started again from the beginning. However, writing to these registers is prohibited in the normal conversion mode and one-shot select mode/one-shot scan mode in the high-speed conversion mode. (2) External trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI9) specified by the ADA0S register is started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits for the trigger, and starts conversion after the external trigger has been input. When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation, the conversion is aborted, and the A/D converter waits for the trigger again. However, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. Caution To select the external trigger mode, set the high-speed conversion mode. Do not input a trigger during the stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). Remark The trigger standby status means the status after the stabilization time has elapsed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 648 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI9) specified by the ADA0S register is started by the compare match interrupt request signal (INTTAA2CC0 or INTTAA2CC1) of the capture/compare register connected to the timer. The INTTAA2CC0 or INTTAA2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. When conversion is completed, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is stopped and the A/D converter waits for the trigger again. However, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. Caution To select the timer trigger mode, set the high-speed conversion mode. Do not input a trigger during the stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). Remark The trigger standby status means the status after the stabilization time has elapsed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 649 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI9 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 9). Figure 14-4. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 1 (ANI1) A/D conversion Data 2 Data 3 Data 2 (ANI1) Data 3 (ANI1) Data 1 (ANI1) ADA0CR1 Data 2 (ANI1) Data 4 (ANI1) Data 3 (ANI1) Data 5 Data 5 (ANI1) Data 4 (ANI1) Data 6 Data 7 Data 6 (ANI1) Data 7 (ANI1) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are continuously converted into digital values. The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated, and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0 (n = 0 to 9). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 650 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Figure 14-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 5 (ANI0) Data 4 (ANI3) Data 6 (ANI1) Data 5 (ANI0) Data 7 (ANI2) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 651 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (3) One-shot select mode In this mode, the voltage of one analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been completed once, the INTAD signal is generated. The A/D conversion operation is stopped after it has been completed (n = 0 to 9). Figure 14-6. Timing Example of One-Shot Select Mode Operation (ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 2 Data 3 Data 1 (ANI1) A/D conversion Data 5 Data 6 Data 7 Data 6 (ANI1) Data 1 (ANI1) ADA0CR1 Data 6 (ANI1) INTAD Conversion end Conversion start Set ADA0CE bit = 1 Conversion end Conversion start Set ADA0CE bit = 1 (4) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values . Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated. A/D conversion is stopped after it has been completed (n = 0 to 9). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 652 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Figure 14-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 4 (ANI3) INTAD Conversion end Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 653 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. * When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter). * When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH ADA0PFT. * When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH < ADA0PFT. Remark n = 0 to 9 In the power-fail compare mode, four modes are available as modes in which to set the ANI0 to ANI9 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 654 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 9). Figure 14-8. Timing Example of Continuous Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 1 (ANI1) A/D conversion ADA0CR1 Data 2 Data 3 Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) ADA0PFT unmatch ADA0PFT unmatch ADA0PFT match Data 5 Data 5 (ANI1) Data 4 (ANI1) Data 6 Data 7 Data 6 (ANI1) Data 7 (ANI1) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT ADA0PFT match match Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the ADA0CE bit is cleared to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 655 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Figure 14-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 5 (ANI0) Data 4 (ANI3) Data 6 (ANI1) Data 5 (ANI0) Data 7 (ANI2) Data 6 (ANI1) INTAD ADA0PFT match ADA0PFT unmatch Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 656 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. Conversion is stopped after it has been completed. Figure 14-10. Timing Example of One-Shot Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 2 Data 1 (ANI1) A/D conversion Data 5 Data 6 Data 7 Data 6 (ANI1) Data 1 (ANI1) ADA0CR1 Data 3 Data 6 (ANI1) INTAD ADA0PFT unmatch Conversion end Conversion start Set ADA0CE bit = 1 ADA0PFT match Conversion end Conversion start Set ADA0CE bit = 1 (4) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD0 signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of converting the signals on the analog input pins specified by the ADA0S register are sequentially stored. The conversion is stopped after it has been completed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 657 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER Figure 14-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data 2 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 4 (ANI3) INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT match Conversion end (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 ADA0CR5 ANI6 ADA0CR6 ANI7 ADA0CR7 ANI8 ADA0CR8 ANI9 ADA0CR9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 658 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI9 pins Input the voltage within the specified range to the ANI0 to ANI9 pins. If a voltage equal to or higher than AVREF0 or equal to or lower than AVSS (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) Countermeasures against noise To maintain the 10-bit resolution, the ANI0 to ANI9 pins must be effectively protected from noise. The effect of noise increases as the output impedance of the analog input source becomes higher. To lower the noise, connecting an external capacitor as shown in Figure 14-12 is recommended. Figure 14-12. Processing of Analog Input Pin Clamp with a diode with a low VF (0.3 V or less) if noise equal to or higher than AVREF0 or equal to or lower than AVSS may be generated. VDD AVREF0 ANI0 to ANI9 AVSS VSS (4) Alternate I/O The analog input pins (ANI0 to ANI9) function alternately as port pins. When selecting one of the ANI0 to ANI9 pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. Also the conversion resolution may drop at the pins set as output port pins during A/D conversion if the output current fluctuates due to the effect of the external circuit connected to the port pins. If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D conversion value may not be as expected due to the effect of coupling noise. Therefore, do not apply a pulse to a pin adjacent to the pin undergoing A/D conversion. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 659 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the ADIF flag may be set even though the A/D conversion of the newly selected analog input pin has not been completed. When A/D conversion is stopped, clear the ADIF flag before resuming conversion. Figure 14-13. Generation Timing of A/D Conversion End Interrupt Request ADA0S rewriting (ANIn conversion start) ADA0S rewriting (ANIm conversion start) ANIn A/D conversion ANIn ADA0CRn ANIn ADIF is set, but ANIm conversion does not end ANIm ANIm ANIn ANIm ANIm INTAD Remark n = 0 to 9 m = 0 to 9 (6) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 14-14. Internal Equivalent Circuit of ANIn Pin RIN ANIn CIN RIN CIN 14 k 8.4 pF Remarks 1. The above values are reference values. 2. n = 0 to 9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 660 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternatefunction ports. In an application where a backup power supply is used, be sure to supply the same potential as VDD to the AVREF0 pin as shown in Figure 14-15. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to the AVREF0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop. To avoid this, it is recommended to connect a capacitor across the AVREF0 and AVSS pins to suppress the reference voltage fluctuation as shown in Figure 14-15. (c) If the source supplying power to the AVREF0 pin has a high DC resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the A/D conversion current. Figure 14-15. AVREF0 Pin Processing Example Note AVREF0 Main power supply AVSS Note Parasitic inductance (8) Reading ADA0CRn register When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register. Also, when an external/timer trigger is acknowledged, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before the next external/timer trigger is acknowledged. The correct conversion result may not be read at a timing different from the above. (9) External trigger mode When using the external trigger mode, the input trigger during A/D conversion will not be acknowledged. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 661 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (10) Standby mode Because the A/D converter stops operating in the STOP mode, the conversion results are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is released, clear the ADA0M0.ADA0CE bit to 0 before setting the STOP mode or after releasing the STOP mode, then set the ADA0CE bit to 1 after releasing the STOP mode. In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower the power consumption, therefore, clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid. The results of conversions before the IDLE1 and IDLE2 modes were set are valid. (11) High-speed conversion mode In the high-speed conversion mode, rewriting the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input during the stabilization time are prohibited. (12) A/D conversion time The A/D conversion time is the total of the stabilization time, conversion time, wait time, and trigger response time (for details of these times, refer to Table 14-2 Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) and Table 14-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)). During A/D conversion in the normal conversion mode, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization time end timing conflicts with writing to these registers, or if the stabilization time end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. If a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted. Therefore do not set the trigger input interval and control register write interval to 64 clocks or lower. (13) Variation of A/D conversion results The results of A/D conversion may vary due to a fluctuation in the supply voltage or the effect of noise. To reduce this variation, take countermeasures with the program such as averaging the A/D conversion results. (14) A/D conversion result hysteresis characteristics The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion. After A/D conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. As a result, the following phenomena may occur. * When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D conversion, then hysteresis characteristics may appear in which the conversion result is affected by the previous value. Thus, even if the conversion is performed at the same potential, the result may vary. * When switching the analog input channel, hysteresis characteristics may appear in which the conversion result is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions. Thus, even if the conversion is performed at the same potential, the result may vary. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 662 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER 14.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%FSR = (Maximum value of convertible analog input voltage - Minimum value of convertible analog input voltage)/100 = (AVREF0 - 0)/100 = AVREF0/100 When the resolution is 10 bits, 1 LSB is as follows: 1 LSB = 1/210 = 1/1,024 = 0.098%FSR The accuracy is determined by the overall error, independently of the resolution. (2) Overall error This is the maximum value of the difference between an actually measured value and a theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. The overall error in the characteristics table does not include the quantization error. Figure 14-16. Overall Error 1......1 Digital output Ideal line Overall error 0......0 0 AVREF0 Analog input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 663 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (3) Quantization error This is an error of 1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of 1/2 LSB into the same digital codes, a quantization error is unavoidable. This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. Figure 14-17. Quantization Error Digital output 1......1 1/2 LSB Quantization error 1/2 LSB 0......0 0 AVREF0 Analog input (4) Zero-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0...000 to 0...001 (1/2 LSB). Figure 14-18. Zero-Scale Error Digital output (lower 3 bits) 111 Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 AVREF0 Analog input (LSB) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 664 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1...110 to 1...111 (full scale - 3/2 LSB). Figure 14-19. Full-Scale Error Digital output (lower 3 bits) Full-scale error 111 100 011 010 000 0 AVREF0 - 3 AVREF0 - 2 AVREF0 - 1 AVREF0 Analog input (LSB) (6) Differential linearity error Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually measured value and its theoretical value when a specific code is output. This indicates the basic characteristics of the A/D conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from AVSS to AVREF0. When the input voltage is increased or decreased, or when two or more channels are used, see 14.7 (2) Overall error. Figure 14-20. Differential Linearity Error 1......1 Digital output Ideal width of 1 LSB Differential linearity error 0......0 AVREF0 Analog input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 665 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 14 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 14-21. Integral Linearity Error 1......1 Digital output Ideal line Integral linearity error 0......0 0 AVREF0 Analog input (8) Conversion time This is the time required to obtain a digital output after each trigger has been generated. The conversion time in the characteristics table includes the sampling time. (9) Sampling time This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit. Figure 14-22. Sampling Time Sampling time Conversion time R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 666 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) 15.1 Functions The D/A converter has the following functions. 8-bit resolution 1 channels (DA0CS0) R-2R ladder method Settling time: 3 s (target). (when AVREF1 is 3.0 to 3.6 V and external load is 20 pF) Analog output voltage: AVREF1 x m/256 (m = 0 to 255; value set to DA0CS0 register) Operation modes: Normal mode, real-time output mode 15.2 Configuration The D/A converter configuration is shown below. Figure 15-1. Block Diagram of D/A Converter DACS0 register write DA0M.DAMD0 bit DACS0 register INTTAA2CC0 signal ANO0 pin DA0M.DACE0 bit AVREF1 pin Selector AVSS pin Caution The AVSS pin is also shared by the A/D converter. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 667 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) The D/A converter includes the following hardware. Table 15-1. Configuration of D/A Converter Item Configuration D/A converter mode register (DA0M) Control registers D/A conversion value setting registers 0 (DA0CS0) 15.3 Registers The registers that control the D/A converter are as follows. * D/A converter mode register (DA0M) * D/A conversion value setting registers 0 (DA0CS0) (1) D/A converter mode register (DA0M) The DA0M register controls the operation of the D/A converter. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF282H < > DA0M 0 DA0CE0 0 0 DA0CE0 0 0 0 DA0MD0 Control of D/A converter operation enable/disable 0 Disables operation 1 Enables operation DA0MD0 Selection of D/A converter operation mode 0 Normal mode 1 Real-time output modeNote Note The output trigger in the real-time output mode (DA0MD0 bit = 1) is INTTAA2CC0 signal (see CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 668 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) (2) D/A conversion value setting registers 0 (DA0CS0) The DA0CS0 registers set the analog voltage value output to the ANO0 pin. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H DA0CS0 Caution R/W Address: DA0CS0 FFFFF280H DA0CS07 DA0CS06 DA0CS05 DA0CS04 DA0CS03 DA0CS02 DA0CS01 DA0CS00 In the real-time output mode (DA0M.DA0MD0 bit = 1), set the DA0CS0 register before the INTTAA2CC0 signals are generated. D/A conversion starts when the INTTAA2CC0 signals are generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 669 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) 15.4 Operation 15.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CS0 register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MD0 bit to 0 (normal mode). <2> Set the analog voltage value to be output to the ANO0 pin to the DA0CS0 register. Steps <1> and <2> above constitute the initial settings. <3> Set the DA0M.DA0CE0 bit to 1 (D/A conversion enable). D/A conversion starts when this setting is performed. <4> To perform subsequent D/A conversions, write to the DA0CS0 register. The previous D/A conversion result is held until the next D/A conversion is performed. Remark For the alternate-function pin settings, see Table 4-17 Using Port Pins as Alternate-Function Pins. 15.4.2 Operation in real-time output mode D/A conversion is performed using the interrupt request signals (INTTAA2CC0) of TAA2 as triggers. The setting method is described below. <1> Set the DA0M.DA0MD0 bit to 1 (real-time output mode). <2> Set the analog voltage value to be output to the ANO0 pin to the DA0CS0 register. <3> Set the DA0M.DA0CE0 bit to 1 (D/A conversion enable). Steps <1> to <3> above constitute the initial settings. <4> Operate TAA2. <5> D/A conversion starts when the INTTAA2CC0 signal are generated. <6> After that, the value set in DA0CS0 register is output every time the INTTAA2CC0 signals are generated. Remarks 1. The output values of the ANO0 pin up to <5> above are undefined. 2. For the output values of the ANO0 pin in the HALT, IDLE1, IDLE2, and STOP modes, see CHAPTER 24 STANDBY FUNCTION. 3. For the alternate-function pin settings, see Table 4-17 Using Port Pins as Alternate-Function Pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 670 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 15 D/A CONVERTER (V850ES/JC3-H (48 pin), V850ES/JE3-H only) 15.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/JC3-H (48 pin) and V850ES/JE3-H. (1) Do not change the set value of the DA0CS0 register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0M.DA0CE0 bit to 0. (3) When using one of the P10/ANO0 pin as an I/O port and the other as a D/A output pin, do so in an application where the port I/O level does not change during D/A output. (4) Make sure that AVREF0 = VDD = AVREF1 = 3.0 to 3.6 V. If this range is exceeded, the operation is not guaranteed. (5) Apply power to AVREF1 at the same timing as AVREF0. (6) No current can be output from the ANO0 pin because the output impedance of the D/A converter is high. When connecting a resistor of 2 M or less, insert a JFET input operational amplifier between the resistor and the ANOn pin. Figure 15-2. External Pin Connection Example - Output ANO0 + AVREF0 AVSS AVREF1 JFET input operational amplifier 0.1 F 10 F 0.1 F 10 F VDD (7) Because the D/A converter stops operating in the STOP mode, the ANO0 pin go into a high-impedance state, and the power consumption can be reduced. In the IDLE1, IDLE2, or subclock operation mode, however, operation continues. To lower the power consumption, therefore, clear the DA0M.DA0CE0 bit to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 671 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) The V850ES/JC3-H (40 pin) have a 3 channels UARTC. The V850ES/JC3-H (48 pin) and V850ES/JE3-H have a 4channels UARTC. 16.1 Features { Transfer rate: 300 bps to 3 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator) { Full-duplex communication: Internal UARTCn receive data register (UCnRX) Internal UARTCn transmit data register (UCnTX) { 2-pin configuration: TXDCn: Transmit data output pin RXDCn: Receive data input pin { Reception error detection function * Parity error * Framing error * Overrun error * LIN communication data consistency error detect function * SBF reception success detect function { Interrupt sources: 2 types * Reception completion interrupt (INTUCnR): This interrupt occurs upon transfer of receive data from the receive shift register to the receive data register after serial transfer is complete, in the reception enabled status. * Transmission enable interrupt (INTUCnT): This interrupt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. { Character length: 7 to 9 bits { Parity function: Odd, even, 0, none { Transmission stop bit: 1, 2 bits { On-chip dedicated baud rate generator { MSB-/LSB-first transfer selectable { Transmit/receive data inverted input/output possible { SBF (Sync Break Field) transmission in the LIN (Local Interconnect Network) communication format * 13 to 20 bits selectable for the SBF transmission * Recognition of 11 bits or more possible for SBF reception * SBF reception flag provided Remark n = 0, 2, 4 (V850ES/JC3-H (40 pin)) n = 0, 2 to 4 (V850ES/JC3-H (48 pin), V850ES/JE3-H) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 672 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.2 Configuration The block diagram of the UARTCn is shown below. Figure 16-1. Block Diagram of Asynchronous Serial Interface Cn Internal bus INTUCnT INTUCnR UCnRX Reception unit Transmission unit UCnTX Receive shift register Reception controller Transmission controller Transmit shift register Filter Baud rate generator Baud rate generator Selector RXDCn Clock selector Selector fXX to fXX/210 ASCKC0Note TXDCn UCnCTL1 UCnCTL2 UCnCTL0 UCnSTR UCnOPT0 Internal bus Note UARTC0 only Remarks 1. n = 0, 2, 4 (V850ES/JC3-H (40 pin)) n = 0, 2 to 4 (V850ES/JC3-H (48 pin), V850ES/JE3-H) 2. For the configuration of the baud rate generator, see Figure 16-19. 3. fXX: Main clock frequency. UARTCn includes the following hardware. Table 16-1. Configuration of UARTCn Item Registers Configuration UARTCn control register 0 (UCnCTL0) UARTCn control register 1 (UCnCTL1) UARTCn control register 2 (UCnCTL2) UARTCn option control register 0 (UCnOPT0) UARTCn option control register 1 (UCnOPT1) UARTCn status register (UCnSTR) UARTCn receive shift register UARTCn receive data register (UCnRX) UARTCn transmit shift register UARTCn transmit data register (UCnTX) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 673 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register used to specify the UARTCn operation. (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register used to select the input clock for the UARTCn. (3) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register used to control the baud rate for the UARTCn. (4) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register used to control serial transfer for the UARTCn. (5) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register used to control 9-bit length serial transfer for the UARTCn. (6) UARTCn status register (UCnSTR) The UCnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one of the reception error flags is set (to 1) upon occurrence of a reception error. (7) UARTCn receive shift register This is a shift register used to convert the serial data input to the RXDCn pin into parallel data. Upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the UCnRX register. This register cannot be manipulated directly. (8) UARTCn receive data register (UCnRX) The UCnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the most significant bit (when data is received with the LSB first). In the reception enabled status, receive data is transferred from the UARTCn receive shift register to the UCnRX register in synchronization with the completion of shift-in processing of 1 frame. Transfer to the UCnRX register also causes the reception completion interrupt request signal (INTUCnR) to be output. (9) UARTCn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UCnTX register into serial data. When 1 byte of data is transferred from the UCnTX register, the shift register data is output from the TXDCn pin. This register cannot be manipulated directly. (10) UARTCn transmit data register (UCnTX) The UCnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UCnTX register. When data can be written to the UCnTX register (when data of one frame is transferred from the UCnTX register to the UARTCn transmit shift register), the transmission enable interrupt request signal (INTUCnT) is generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 674 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.3 Mode Switching Between UARTC and Other Serial Interfaces 16.3.1 Mode switching between UARTC0 and CSIF4 In the V850ES/JC3-H and V850ES/JE3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used simultaneously. Set UARTC0 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of CSIF4 and UARTC0 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-2. CSIF4 and UARTC0 Mode Switch Settings After reset: 00H PMC3 R/W R/W PFC33Note2 PFC32 PMC32 PFCE32 PFC32 0 x x Port I/O mode 1 0 0 ASCKC0 (UARTC0) 1 0 1 SCKF4 (CSIF4) PMC31 PFCE31 PFC31 x x Port I/O mode 0 0 RXDC0 (UARTC) 1 0 1 SIF4 (CSIF4) PMC30 PFCE30 PFC30 PFCE31 PFCE30 Operation mode 0 x x Port I/O mode 1 0 0 TXDC0 (UARTC) 1 0 1 SOF4 (CSIF4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 PFC30 Operation mode 1 Remark PFC31 Operation mode 0 2. PMC30 Address: FFFFF706H PFCE37Note1 PFCE36Note1 PFCE35Note2 PFCE34 PFCE33Note2 PFCE32 Notes1. PMC31 Address: FFFFF466H PFC37Note1 PFC36Note1 PFC35Note2 PFC34 After reset: 00H PFCE3 Address: FFFFF446H PMC37Note1 PMC36Note1 PMC35Note2 PMC34 PMC33Note2 PMC32 After reset: 00H PFC3 R/W V850ES/JC3-H (48 pin), V850ES/JE3-H only V850ES/JE3-H only x = don't care Page 675 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.3.2 Mode switching between UARTC2 and CSIF3 In the V850ES/JC3-H and V850ES/JE3-H, UARTC2 and CSIF3 share of the same pin and therefore cannot be used simultaneously. Set UARTC2 in advance, using the PMC9, PFC9 and PFCE9 registers, before use. Caution The transmit/receive operation of UARTC2 and CSIF3 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-3. UARTC2 and CSIF3 Mode Switch Settings After reset: 0000H PMC9 15 14 0 0 PMC97 PMC96 After reset: 0000H PFC9 R/W 15 14 0 0 PFC97 PFC96 After reset: 0000H PFCE9 R/W R/W Address: FFFFF452H, FFFFF453H 9 8 PMC913 PMC912 PMC911 PMC910 13 0 0 PMC94Note PMC93Note PMC92Note 0 0 9 8 PFC911 PFC910 0 0 PFC94Note PFC93Note PFC92Note 0 0 9 8 PFCE911 PFCE910 0 0 PFCE94Note PFCE93Note PFCE92Note 0 0 0 12 13 12 PFC913 PFC912 0 13 12 0 0 0 0 Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 11 10 Address: FFFFF712H, FFFFF713H 14 Note 10 Address: FFFFF472H, FFFFF473H 15 PFCE97 PFCE96 11 0 11 10 V850ES/JC3-H (48 pin), V850ES/JE3-H only x = don't care Page 676 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 2 16.3.3 Mode switching between UARTC3, I C00 and CAN0 In the V850ES/JC3-H (48 pin) and V850ES/JE3-H, UARTC3, I2C00, and CAN0 (PD70F3819, 70F3825 only) share the same pins and therefore cannot be used simultaneously. Set UARTC3 in advance, using the PMC3, PFC3 and PFCE3 registers, before use. Caution The transmit/receive operation of UARTC3, I2C00, and CAN0 (PD70F3819, 70F3825 only) is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-4. UARTC3, I2C00, and CAN0 Mode Switch Settings After reset: 0000H R/W 15 14 0 0 PMC97 PMC96 PMC9 After reset: 0000H R/W 15 14 0 0 PFC97 PFC96 PFC9 After reset: 0000H PFCE9 R/W Address: FFFFF452H, FFFFF453H 9 8 PMC913 PMC912 PMC911 PMC910 13 0 0 PMC94Note PMC93Note PMC92Note 0 0 9 8 0 0 0 0 0 12 11 10 Address: FFFFF472H, FFFFF473H 13 12 PFC913 PFC912 0 11 10 PFC911 PFC910 PFC94Note PFC93Note PFC92Note Address: FFFFF712H, FFFFF713H 15 14 13 12 0 0 0 0 PFCE97 PFCE96 0 9 8 PFCE911 PFCE910 11 10 0 0 PFCE94Note PFCE93Note PFCE92Note 0 0 PMC91 PFCE91 PFC91 0 x x Port I/O mode 1 0 1 TXDC1 (UARTC1) 1 1 0 SDA02 (I2C02) PMC90 PFCE90 PFC90 0 x x Port I/O mode 1 0 1 RXDC1 (UARTC1) 1 1 0 SCL02 (I2C02) Operation mode Operation mode Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 x = don't care Page 677 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 2 16.3.4 Mode switching between UARTC4, CSIF0, and I C01 In the V850ES/JC3-H and V850ES/JE3-H, UARTC4, CSIF0, and I2C01 share the same pin and therefore cannot be used simultaneously. Set UARTC4 in advance, using the PMC4, PFC4, and PMCE4 registers, before use. Caution The transmit/receive operation of UARTC4, CSIF0, and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-5. UARTC4, CSIF0 and I2C01 Mode Switch Settings After reset: 00H PMC3 PMC37 After reset: 00H PFC3 Address: FFFFF446H PMC36 R/W PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PFC33Note2 PFC32 PFC31 PFC30 PFCE31 PFCE30 Address: FFFFF466H PFC37Note1 PFC36Note1 PFC35Note2 PFC34 After reset: 00H PFCE3 R/W R/W Address: FFFFF706H PFCE37Note1 PFCE36Note1 PFCE35Note2 PFCE34 PFCE33Note2 PFCE32 PMC37 Note1 Note1 PFCE37 PFC37 Note1 Operation mode 0 x x Port I/O mode 1 0 0 RXDC3 (UARTC3) 1 0 1 SDA00 (I2C00) 1 1 0 CRXD0 (CAN0)Note3 PMC36 Note1 Note1 PFCE36 PFC36 Note1 Operation mode 0 x x Port I/O mode 1 0 0 TXDC3 (UARTC3) 1 0 1 SCL00 (I2C00) 1 1 0 CTXD0 (CAN0) Notes1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only 3. PD70F3819, 70F3825 only Remark Note3 x = don't care Page 678 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.4 Registers (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H. (1/2) After reset: 10H R/W Address: UC0CTL0 FFFFFA00H, UC2CTL0 FFFFFA20H, UC3CTL0 FFFFFA30HNote, UC4CTL0 FFFFFA40H <7> UCnCTL0 <6> <5> <4> UCnPWR UCnTXE UCnRXE UCnDIR 3 2 UCnPS1 UCnPS0 1 0 UCnCL UCnSL (n = 0, 2 to 4) UCnPWR UCRTCn operation control 0 Disable UCRTCn operation (UCRTCn reset asynchronously) 1 Enable UCRTCn operation The UARTCn operation is controlled by the UCnPWR bit. The TXDCn pin output is fixed to high level by clearing the UCnPWR bit to 0 (fixed to low level if UCnOPT0.UCnTDL bit = 1). UCnTXE Transmission operation enable 0 Disable transmission operation 1 Enable transmission operation * To start transmission, set the UCnPWR bit to 1 and then set the UCnTXE bit to 1. To stop transmission, clear the UCnTXE bit to 0 and then UCnPWR bit to 0. * To initialize the transmission unit, clear the UCnTXE bit to 0, wait for two cycles of the base clock, and then set the UCnTXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) Base clock). UCnRXE Reception operation enable 0 Disable reception operation 1 Enable reception operation * To start reception, set the UCnPWR bit to 1 and then set the UCnRXE bit to 1. To stop reception, clear the UCnRXE bit to 0 and then UCnPWR bit to 0. * To initialize the reception unit, clear the UCnRXE bit to 0, wait for two periods of the base clock, and then set the UCnRXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) Base clock). Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 679 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2/2) UCnDIR Transfer direction selection 0 MSB-first transfer 1 LSB-first transfer * This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. * When transmission and reception are performed in the LIN format, set the UCnDIR bit to 1. UCnPS1 UCnPS0 Parity selection during transmission Parity selection during reception 0 0 No parity output Reception with no parity 0 1 0 parity output Reception with 0 parity 1 0 Odd parity output Odd parity check 1 1 Even parity output Even parity check * This register is rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. * If "Reception with 0 parity" is selected during reception, a parity check is not performed. Therefore, the UCnSTR.UCnPE bit is not set. * When transmission and reception are performed in the LIN format, clear the UCnPS1 and UCnPS0 bits to 00. UCnCL Specification of data character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits * This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. * When transmission and reception are performed in the LIN format, set the UCnCL bit to 1. UCnSL Specification of length of stop bit for transmit data 0 1 bit 1 2 bits This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. Remark For details of parity, see 16.6.9 Parity types and operations. (2) UARTCn control register 1 (UCnCTL1) For details, see 16.7 (2) UARTCn control register 1 (UCnCTL1). (3) UARTCn control register 2 (UCnCTL2) For details, see 16.7 (3) UARTCn control register 2 (UCnCTL2). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 680 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (4) UARTCn option control register 0 (UCnOPT0) The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H. (1/2) After reset: 14H R/W Address: UC0OPT0 FFFFFA03H, UC2OPT0 FFFFFA23H, UC3OPT0 FFFFFA33HNote, UC4OPT0 FFFFFA43H <7> UCnOPT0 6 5 4 3 2 1 0 UCnSRF UCnSRT UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL UCnRDL (n = 0, 2 to 4) UCnSRF SBF reception flag 0 When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnRXE bit = 0 are set, or upon normal end of SBF reception. 1 During SBF reception * SBF (Sync Brake Field) reception is judged during LIN communication. * The UCnSRF bit is held at 1 when an SBF reception error occurs, and then SBF reception is started again. * The UCnSRF bit is a read-only bit. UCnSRT SBF reception trigger - 0 1 SBF reception trigger * This is the SBF reception trigger bit during LIN communication, and when read, "0" is always read. For SBF reception, set the UCnSRT bit (to 1) to enable SBF reception. * Set the UCnSRT bit after setting the UCnPWR bit = UCnRXE bit = 1. UCnSTT SBF transmission trigger - 0 1 SBF transmission trigger * This is the SBF transmission trigger bit during LIN communication, and when read, "0" is always read. * Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1. Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Caution Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception (UCnSRF bit = 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 681 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2/2) UCnSLS2 UCnSLS1 UCnSLS0 SBF transmission length selection 1 0 1 13-bit output (reset value) 1 1 0 14-bit output 1 1 1 15-bit output 0 0 0 16-bit output 0 0 1 17-bit output 0 1 0 18-bit output 0 1 1 19-bit output 1 0 0 20-bit output This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0. UCnTDL Transmit data level bit 0 Normal output of transfer data 1 Inverted output of transfer data * The output level of the TXDCn pin can be inverted using the UCnTDL bit. * This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0. UCnRDL Receive data level bit 0 Normal input of transfer data 1 Inverted input of transfer data * The input level of the RXDCn pin can be inverted using the UCnRDL bit. * This register can be set when the UCnPWR bit = 0 or the UCnRXE bit = 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 682 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (5) UARTCn option control register 1 (UCnOPT1) The UCnOPT1 register is an 8-bit register that controls the serial transfer operation of UARTCn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution Set the UCnEBE bit while the operation of UARTC is disabled (UCnCTL0.UCnPWR = 0). After reset: 00H R/W Address: UC0OPT1 FFFFFA0AH, UC2OPT1 FFFFFA2AH, UC3OPT1 FFFFFA3AHNote, UC4OPT1 FFFFFA4AH UCnOPT1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 UCnEBE (n = 0 , 2 to 4) UCnEBE Extension bit enable/disable 0 Extension-bit operation is prohibited. Transmission/reception is performed in the data length set by the UCnCTL0.UCnCL bit. 1 Extension-bit operation enabled. Transmission/reception can be performed in 9-bit character length. * When setting the UCnEBE bit to 1, and transmitting in 9-bit data length, be sure to set the following. If this setting is not performed, the setting of UCnEBE bit is invalid. * UCnCTL0.UCnPS1, UCnPS0 = 00 (no parity) * CnCTL0.UCnCL = 1 (8-bit character length) * If transmitting or receiving in the LIN communication format, set the UCnEBE to 0. Note V850ES/JC3-H (48 pin), V850ES/JE3-H only The following shows the relationship between the register setting value and the data format. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 683 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Table 16-2. Relationship Between Register Setting and Data Format Register Setting Data Format UCnCTL0 UCnOPT1 D0 to D6 D7 D8 D9 D10 Data Stop - - - UCnCL UCnPS1 UCnPS0 UCnSL UCnEBE 0 0 0 0 0 0 Other than 00 Data Parity Stop - - 1 0 0 Data Data Stop - - 1 Other than 00 Data Data Parity Stop - 0 0 Data Stop Stop - - 0 1 0 0 Other than 00 Data Parity Stop Stop - 1 0 0 Data Data Stop Stop - 1 Other than 00 Data Data Parity Stop Stop 0 0 Data Stop - - - 0 Other than 00 Data Parity Stop - - 1 0 0 Data Data Data Stop - 1 Other than 00 Data Data Parity Stop - 0 0 Data Stop Stop - - 0 0 0 1 1 1 0 Other than 00 Data Parity Stop Stop - 1 0 0 Data Data Data Stop Stop 1 Other than 00 Data Data Parity Stop Stop Remark Data: Data bit Stop: Stop bit Parity: Parity bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 684 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (6) UARTCn status register (UCnSTR) The UCnSTR register is an 8-bit register that displays the UARTCn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UCnTSF bit is a read-only bit, while the UCnPE, UCnFE, and UCnOVE bits can both be read and written. However, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). The initialization conditions are shown below. Register/Bit UCnSTR register Initialization Conditions * Reset * UCnCTL0.UCnPWR = 0 UCnTSF bit * UCnCTL0.UCnTXE = 0 UCnPE, UCnFE, UCnOVE bits * 0 write * UCnCTL0.UCnRXE = 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 685 of 1442 V850ES/JC3-H, V850ES/JE3-H After reset: 00H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) R/W Address: UC0STR FFFFFA04H, UC2STR FFFFFA24H, UC3STR FFFFFA34HNote, UC4STR FFFFFA44H UCnSTR <7> 6 5 4 3 <2> <1> <0> UCnTSF 0 0 0 0 UCnPE UCnFE UCnOVE (n = 0, 2 to 4) UCnTSF Transfer status flag 0 * When the UCnPWR bit = 0 or the UCnTXE bit = 0 has been set. * When, following transfer completion, there was no next data transfer from UCnTX register 1 Write to UCnTX register The UCnTSF bit is always 1 when performing continuous transmission. When initializing the transmission unit, check that the UCnTSF bit = 0 before performing initialization. The transmit data is not guaranteed when initialization is performed while the UCnTSF bit = 1. UCnPE Parity error flag 0 * When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set. * When 0 has been written 1 When parity of data and parity bit do not match during reception. * The operation of the UCnPE bit is controlled by the settings of the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits. * The UCnPE bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UCnFE Framing error flag 0 * When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set * When 0 has been written 1 When no stop bit is detected during reception * Only the first bit of the receive data stop bits is checked, regardless of the value of the UCnCTL0.UCnSL bit. * The UCnFE bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UCnOVE Overrun error flag 0 * When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set. * When 0 has been written 1 When receive data has been set to the UCnRX register and the next receive operation is completed before that receive data has been read * When an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. * The UCnOVE bit can be both read and written, but it can only be cleared by writing 0 to it. When 1 is written to this bit, the value is retained. Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 686 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (7) UARTCn receive data register L (UCnRXL) and UARTCn receive data register (UCnRX) The UCnRXL and UCnRX register are an 8- bit or 9-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UCnRXL and UCnRX register upon completion of reception of 1 byte of data. During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the UCnRXL register and the MSB always becomes 0. During MSB-first reception, the receive data is transferred to bits 7 to 1 of the UCnRXL register and the LSB always becomes 0. When an overrun error (UCnOVE) occurs, the receive data at this time is not transferred to the UCnRXL and UCnRX register and is discarded. The access unit or reset value differs depending on the character length. * Character length 7/8-bit (UCnOPT1.UCnEBE = 0) This register is read-only, in 8-bit units. Reset or UCnCTL0.UCnPWR bit = 0 sets this register to FFH. * Character length 9-bit (UCnOPT1.UCnEBE = 0) This register is read-only, in 16-bit units. Reset or UCnCTL0.UCnPWR bit = 0 sets this register to 01FFH. (a) Character length 7/8-bit (UCnOPT1.UCnEBE = 0) After reset: FFH R Address: UC0RXL FFFFFA06H, UC2RXL FFFFFA26H, UC3RXL FFFFFA36HNote, UC4RXL FFFFFA46H 6 7 5 4 3 2 1 0 UCnRXL (n = 0, 2 to 4) Note V850ES/JC3-H (48 pin), V850ES/JE3-H only (b) Character length 9-bit (UCnOPT1.UCnEBE = 1) After reset: 01FFH R Address: UC0RX FFFFFA06H, UC2RX FFFFFA26H, UC3RX FFFFFA36HNote, UC4RX FFFFFA46H UCnRX (n = 0 , 2 to 4) 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 687 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (8) UARTCn transmit data register L (UCnTXL), UARTCn transmit data register (UCnTX) The UCnTXL and UCnTX register is an 8-bit or 9-bit register used to set transmit data. During LSB-first transmission when the data length has been specified as 7 bits, the transmit data is transferred to bits 6 to 0 of the UCnRX register. During MSB-first transmission, the receive data is transferred to bits 7 to 1 of the UCnRX register. The access unit or reset value differs depending on the character length. * Character length 7/8-bit (UCnOPT1.UCnEBE = 0) This register can be read or written in 8-bit units. Reset sets this register to FFH. * Character length 9-bit (UCnOPT1.UCnEBE = 0) This register can be read or written in 16-bit units. Reset sets this register to 01FFH. Cautions 1. In the transmission operation enable status (UCnPWR = 1 and UCnTXE = 1), Writing to the UCnTXL, UCnTX register, as operate as trigger of transmission star, if writing the value of as soon as before and save value, before the INTUCnT interrupt is occurred, the same data is transferred at twice. 2. Data writing for consecutive transmission, after be generated the INTUCnT interrupt. If writing the next data before the INTUCnT interrupt is occurred, transmission start processing and source of conflict writing the UCnTXL, UCnTX register, unexpected operations may occur. 3. If perform to write the UCnTXL, UCnTXLin the disable transmission operation register, can not be used as transmission start trigger. Consequently, even if transmission enable status after perform to write the UCnTXL, UCnTX register in the disable transmission operation status, can not be started transmission. (a) Character length 7/8-bit (UCnOPT1.UCnEBE = 0) After reset: FFH R/W Address: UC0TXL FFFFFA08H, UC2TXL FFFFFA28H, UC3TXL FFFFFA38HNote, UC4TXL FFFFFA48H 6 7 5 4 3 2 1 0 UCnTXL (n = 0, 2 to 4) Note V850ES/JC3-H (48 pin), V850ES/JE3-H only (b) Character length 9-bit (UCnOPT1.UCnEBE = 1) After reset: 01FFH R/W Address: UC0TX FFFFFA08H, UC2TX FFFFFA28H, UC3TX FFFFFA38HNote, UC4TX FFFFFA48H UCnTX (n = 0, 2 to 4) 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 688 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTCn. * Reception completion interrupt request signal (INTUCnR) * Transmission enable interrupt request signal (INTUCnT) The default priority for these two interrupt request signals is reception completion interrupt request signal then transmission enable interrupt request signal. Table 16-3. Interrupts and Their Default Priorities Interrupt Priority Reception complete High Transmission enable Low (1) Reception completion interrupt request signal (INTUCnR) A reception completion interrupt request signal is output when data is shifted into the receive shift register and transferred to the UCnRX register in the reception enabled status. A reception completion interrupt request signal is also output when a reception error occurs. Therefore, when a reception completion interrupt request signal is acknowledged and the data is read, read the UCnSTR register and check that the reception result is not an error. No reception completion interrupt request signal is generated in the reception disabled status. (2) Transmission enable interrupt request signal (INTUCnT) If transmit data is transferred from the UCnTX register to the UARTCn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 689 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6 Operation 16.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 16-7, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UCnCTL0 register. Moreover, control of UART output/inverted output for the TXDCn bit is performed using the UCnOPT0.UCnTDL bit. * Start bit..................1 bit * Character bits ........7 bits/8 bits * Parity bit ................Even parity/odd parity/0 parity/no parity * Stop bit ..................1 bit/2 bits R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 690 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 16-6. UARTC Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDCn inversion 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity Stop bit bit Stop bit (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Page 691 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.2 SBF transmission/reception format The V850ES/JC3-H and V850ES/JE3-H have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 16-8 and 16-9 outline the transmission and reception manipulations of LIN. Figure 16-7. LIN Transmission Manipulation Outline Sync break field Sync field Note 2 13 bits 55H transmission Wake-up signal frame DATA field DATA field Check SUM field Data transmission Data transmission Data transmission Identifier field LIN bus Note 3 8 bits Note 1 Data transmission TXDCn (output) SBF transmissionNote 4 INTUCnT interrupt Notes 1. The interval between each field is controlled by software. 2. SBF output is performed by hardware. The output width is the bit length set by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits. required, such adjustments can be If even finer output width adjustments are performed using the UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits. 3. 80H transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. A transmission enable interrupt request signal (INTUCnT) is output at the start of each transmission. The INTUCnT signal is also output at the start of each SBF transmission. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 692 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 16-8. LIN Reception Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field Note 2 13 bits SF reception ID reception Data transmission DATA field Check SUM field LIN bus RXDCn (input) SBF reception Enable Disable Data Note 5 transmission Data transmission Note 3 Reception interrupt (INTUCnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes 1. The wakeup signal is sent by the pin edge detector, UARTCn is enabled, and the SBF reception mode is set. 2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal is output, and the mode returns to the SBF reception mode. 3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF reception completion interrupt. Moreover, error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART communication error detection processing and UARTCn receive shift register and data transfer of the UCnRX register are not performed. The UARTCn receive shift register holds the initial value, FFH. 4. The RXDCn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. The value of the UCnCTL2 register obtained by correcting the baud rate error after dropping UARTC enable is set again, causing the status to become the reception status. 5. Check-sum field distinctions are made by software. UARTCn is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 693 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.3 SBF transmission When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UCnOPT0.UCnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits is output. A transmission enable interrupt request signal (INTUCnT) is generated upon SBF transmission start. Following the end of SBF transmission, the UCnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF transmission trigger (UCnSTT bit) is set. Figure 16-9. SBF Transmission TXDCn 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop bit INTUCnT interrupt Setting of UCnSTT bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 694 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.4 SBF reception The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit detection is performed. Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception completion interrupt request signal (INTUCnR) is output. The UCnOPT0.UCnSRF bit is automatically cleared and SBF reception ends. Error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART communication error detection processing is not performed. Moreover, data transfer of the UARTCn reception shift register and UCnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to. The UCnSRF bit is not cleared at this time. Cautions 1. If SBF is transmitted during a data reception, a framing error occurs. 2. Do not set the SBF reception trigger bit (UCnSRT) and SBF transmission trigger bit (UCnSTT) to 1 during an SBF reception (UCnSRF = 1). Figure 16-10. SBF Reception (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) RXDCn 1 2 3 4 5 6 7 8 9 10 11 11.5 UCnSRF INTUCnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDCn 1 2 3 4 5 6 7 8 9 10 10.5 UCnSRF INTUCnR interrupt R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 695 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.5 UART transmission A high level is output to the TXDCn pin by setting the UCnCTL0.UCnPWR bit to 1. Next, the transmission enabled status is set by setting the UCnCTL0.UCnTXE bit to 1, and transmission is started by writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added. Since the CTS (transmit enable signal) input pin is not provided in UARTCn, use a port to check that reception is enabled at the transmit destination. The data in the UCnTX register is transferred to the UARTCn transmit shift register upon the start of the transmit operation. A transmission enable interrupt request signal (INTUCnT) is generated upon completion of transmission of the data of the UCnTX register to the UARTCn transmit shift register, and thereafter the contents of the UARTCn transmit shift register are output to the TXDCn pin. Write of the next transmit data to the UCnTX register is enabled after the INTUCnT signal is generated. Figure 16-11. UART Transmission TXDCn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUCnT Remark LSB first R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 696 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.6 Continuous transmission procedure UARTCn can write the next transmit data to the UCnTX register when the UARTCn transmit shift register starts the shift operation. The transmit timing of the UARTCn transmit shift register can be judged from the transmission enable interrupt request signal (INTUCnT). An efficient communication rate is realized by writing the data to be transmitted next to the UCnTX register during transfer. Caution When initializing transmissions during the execution of continuous transmissions, make sure that the UCnSTR.UCnTSF bit is 0, then perform the initialization. Transmit data that is initialized when the UCnTSF bit is 1 cannot be guaranteed. Figure 16-12. Continuous Transmission Processing Flow Start Register settings UCnTX write Occurrence of transmission interrupt? No Yes Required number of writes performed? No Yes End R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 697 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 16-13. Continuous Transmission Operation Timing (a) Transmission start Start TXDCn UCnTX Data (1) Parity Stop Data (1) Transmission shift register Start Data (2) Parity Data (2) Stop Start Data (3) Data (2) Data (1) INTUCnT UCnTSF (b) Transmission end TXDCn UCnTX Parity Stop Start Data (n - 1) Parity Data (n - 1) Transmission shift register Stop Start Data (n) Parity Stop Data (n) Data (n - 1) Data (n) FF INTUCnT UCnTSF UCnPWR or UCnTXE bit R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 698 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.7 UART reception The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge. The start bit is recognized if the RXDCn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate. When the reception completion interrupt request signal (INTUCnR) is output upon reception of the stop bit, the data of the UARTCn receive shift register is written to the UCnRX register. However, if an overrun error (UCnSTR.UCnOVE bit) occurs, the receive data at this time is not written to the UCnRX register and is discarded. Even if a parity error (UCnSTR.UCnPE bit) or a framing error (UCnSTR.UCnFE bit) occurs during reception, reception continues until the reception position of the first stop bit, and INTUCnR is output following reception completion. Figure 16-14. UART Reception RXDCn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUCnR UCnRX Cautions 1. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. The operation during reception is performed assuming that there is only one stop bit. A second stop bit is ignored. 3. When reception is completed, read the UCnRX register after the reception completion interrupt request signal (INTUCnR) has been generated, and clear the UCnPWR or UCnRXE bit to 0. If the UCnPWR or UCnRXE bit is cleared to 0 before the INTUCnR signal is generated, the read value of the UCnRX register cannot be guaranteed. 4. If receive completion processing (INTUCnR signal generation) of UARTCn and the UCnPWR bit = 0 or UCnRXE bit = 0 conflict, the INTUCnR signal may be generated in spite of these being no data stored in the UCnRX register. To complete reception without waiting for the INTUCnR signal to be generated, be sure to set (1) the interrupt mask flag (UCnRMK) of the interrupt control register (UCnRIC), clear (0) the UCnPWR bit or UCnRXE bit, and then clear the interrupt request flag (UCnRIF) of the UCnRIC register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 699 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UCnSTR register and a reception completion interrupt request signal (INTUCnR) is output when an error occurs. It is possible to ascertain which error occurred during reception by reading the contents of the UCnSTR register. Clear the reception error flag by writing 0 to it after reading it. Figure 16-15. Receive Data Read Flow START INTUCnR signal generated? No Yes Read UCnRX register Read UCnSTR register No Error occurs? Yes Error processing END Caution When an INTUCnR signal is generated, the UCnSTR register must be read to check for errors. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 700 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) * Reception error causes Error Flag Reception Error Cause UCnPE Parity error Received parity bit does not match the setting UCnFE Framing error Stop bit not detected UCnOVE Overrun error Reception of next data completed before data was read from receive buffer When reception errors occur, perform the following procedures depending upon the kind of error. * Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit. * Framing error A baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing each other, and then start the communication again. * Overrun error Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was needed, do a retransmission. Caution If a receive error interrupt occurs during continuous reception, read the contents of the UCnSTR register must be read before the next reception is completed, then perform error processing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 701 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.9 Parity types and operations Caution When using the LIN function, fix the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected. (a) Even parity (i) During transmission The number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so as to be an even number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 1 * Even number of bits whose value is "1" among transmit data: 0 (ii) During reception The number of bits whose value is "1" among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) Odd parity (i) During transmission Opposite to even parity, the number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 0 * Even number of bits whose value is "1" among transmit data: 1 (ii) During reception The number of bits whose value is "1" among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity During transmission, the parity bit is always made 0, regardless of the transmit data. During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (d) No parity No parity bit is added to the transmit data. Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 702 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.6.10 Receive data noise filter This filter samples the RXDCn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDCn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 16-18). See 16.7 (1) (a) Base clock regarding the base clock. Moreover, since the circuit is as shown in Figure 16-17, the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. Figure 16-16. Noise Filter Circuit Base clock (fUCLK) RXDCn In Q Internal signal A In Q Internal signal B In Match detector Q Internal signal C LD_EN Figure 16-17. Timing of RXDCn Signal Judged as Noise Base clock RXDCn (input) Internal signal A Internal signal B Match Mismatch (judged as noise) Match Mismatch (judged as noise) Internal signal C R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 703 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception. (1) Baud rate generator configuration Figure 16-18. Configuration of Baud Rate Generator UCnPWR fXX/2 fXX/4 UCnPWR, UCnTXEn bits (or UCnRXE bit) fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXX/2048 ASCKC0Note Selector 8-bit counter fUCLK Match detector UCnCTL1: UCnCKS3 to UCnCKS0 1/2 Baud rate UCnCTL2: UCnBRS7 to UCnBRS0 Note Only UARTC0 is valid; setting UARTC4 is prohibited. Remarks1. n = 0, 2, 4 (V850ES/JC3-H (40 pin)) n = 0, 2 to 4 (V850ES/JC3-H (48 pin), V850ES/JE3-H) 2. fXX: Main clock frequency fUCLK: Base clock frequency (a) Base clock When the UCnCTL0.UCnPWR bit is 1, the clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (fUCLK). (b) Serial clock generation A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register (n = 0 to 4). The base clock is selected by UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits. The frequency division value for the 8-bit counter can be set using the UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 704 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register that selects the UARTCn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UCnCTL0.UCnPWR bit to 0 before rewriting the UCnCTL1 register. After reset: 00H R/W Address: UC0CTL1 FFFFFA01H, UC2CTL1 FFFFFA21H, UC3CTL1 FFFFFA31HNote1, UC4CTL1 FFFFFA41H UCnCTL1 7 6 5 4 0 0 0 0 3 2 1 0 UCnCKS3UCnCKS2 UCnCKS1 UCnCKS0 (n = 0, 2 to 4) UCnCKS3 UCnCKS2 UCnCKS1UCnCKS0 Base clock (fUCLK) selection 0 0 0 0 fXX/2 0 0 0 1 fXX/4 0 0 1 0 fXX/8 0 0 1 1 fXX/16 0 1 0 0 fXX/32 0 1 0 1 fXX/64 0 1 1 0 fXX/128 0 1 1 1 fXX/256 1 0 0 0 fXX/512 1 0 0 1 fXX/1,024 1 0 1 0 fXX/2,048 1 0 1 1 External clockNote2 (ASCKC0 pin) Other than above Setting prohibited Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. Only UARTC0 is valid; setting UARTC2 to UARTC4 is prohibited. Remark R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 fXX: Main clock frequency Page 705 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (3) UARTCn control register 2 (UCnCTL2) The UCnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTCn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution Clear the UCnCTL0.UCnPWR bit to 0 or clear the UCnTXE and UCnRXE bits to 00 before rewriting the UCnCTL2 register. After reset FFH R/W Address: UC0CTL2 FFFFFA02H, UC2CTL2 FFFFFA22H, UC3CTL2 FFFFFA32HNote, UC4CTL2 FFFFFA42H 6 7 UCnCTL2 5 4 3 2 1 0 UCnBRS7 UCnBRS6 UCnBRS5UCnBRS4 UCnBRS3UCnBRS2 UCnBRS1 UCnBRS0 (n = 0, 2 to 4) UCn BRS7 UCn BRS6 UCn BRS5 UCn BRS4 UCn BRS3 UCn BRS2 UCn BRS1 UCn Default BRS0 (k) Serial clock 0 0 0 0 0 0 x x x 0 0 0 0 0 1 0 0 4 fUCLK/4 0 0 0 0 0 1 0 1 5 fUCLK/5 0 0 0 0 0 1 1 0 6 fUCLK/6 : : : : : : : : : : 1 1 1 1 1 1 0 0 252 fUCLK/252 1 1 1 1 1 1 0 1 253 fUCLK/253 1 1 1 1 1 1 1 0 254 fUCLK/254 1 1 1 1 1 1 1 1 255 fUCLK/255 Setting prohibited Note. V850ES/JC3-H (48 pin), V850ES/JE3-H only Remark fUCLK: Clock frequency selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 706 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (4) Baud rate The baud rate is obtained by the following equation. Baud rate = fUCLK 2xk [bps] When using the internal clock, the equation will be as follows (when using the ASCKC0 pin as clock at UARTC0, calculate using the above equation). Baud rate = fXX m+1 2 Remark xk [bps] fUCLK = Frequency of base clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits fXX: Main clock frequency m = Value set using the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits (m = 0 to 10) k = Value set using the UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (k = 4 to 255) The baud rate error is obtained by the following equation. Error (%) = = Actual baud rate (baud rate with error) Target baud rate (correct baud rate) fUCLK 2 x k x Target baud rate - 1 x 100 [%] - 1 x 100 [%] When using the internal clock, the equation will be as follows (when using the ASCKC0 pin input as the clock for UARTC0, calculate the baud rate error using the above equation). fXX Error (%) = m+1 2 x k x Target baud rate - 1 x 100 [%] Cautions 1. The baud rate error during transmission must be within the error tolerance on the receiving side. 2. The baud rate error during reception must satisfy the range indicated in (5) Allowable baud rate range during reception. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 707 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when using internal clock). <1> Set k to fxx/2/(2 x target baud rate) and m to 0. <2> If k is 256 or greater (k 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> Repeat Step <2> until k becomes less than 256 (k < 256). <4> Round off the first decimal point of k to the nearest whole number. If k becomes 256 after round-off, perform Step <2> again to set k to 128. <5> Set the value of m to UCnCTL1 register and the value of k to the UCnCTL2 register. Example: When fXX = 48 MHz and target baud rate = 153,600 bps <1> k = 480,000,000/2/(2 x 153,600) = 78.125..., m = 0 <2>, <3> k = 78.125... < 256, m = 0 <4> Set value of UCnCTL2 register: k = 78 = 4EH, set value of UCnCTL1 register: m = 0 Actual baud rate = 48,000,000/2/(2 x 78) = 153,846 [bps] Baud rate error = {48,000,000/2/(2 x 78 x 153,600) - 1} x 100 = 0.160 [%] The representative examples of baud rate settings are shown below. Table 16-4. Baud Rate Generator Setting Data Baud Rate (bps) fXX = 48 MHz UCnCTL1 UCnCTL2 fXX = 32 MHz ERR (%) UCnCTL1 UCnCTL2 fXX = 24 MHz ERR (%) UCnCTL1 UCnCTL2 ERR (%) 300 08H 9CH 0.16 07H D0H 0.16 07H 9CH -2.3 600 07H 9CH 0.16 06H D0H 0.16 06H 9CH 0.16 1,200 06H 9CH 0.16 05H D0H 0.16 05H 9CH 0.16 2,400 05H 9CH 0.16 04H D0H 0.16 04H 9CH 0.16 4,800 04H 9CH 0.16 03H D0H 0.16 03H 9CH 0.16 9,600 03H 9CH 0.16 02H D0H 0.16 02H 9CH 0.16 19,200 02H 9CH 0.16 01H D0H 0.16 01H 9CH 0.16 31,250 01H C0H 0.00 01H 80H 0.00 00H C0H 0.00 38,400 01H 9CH 0.16 00H D0H 0.16 00H 9CH 0.16 76,800 00H 9CH 0.16 00H 68H 0.16 00H 4EH 0.16 153,600 00H 4EH 0.16 00H 34H 0.16 00H 27H 0.16 312,500 00H 26H 1.05 00H 1AH -1.54 00H 13H 1.05 625,000 00H 13H 1.05 00H 0DH -1.54 00H 0AH -4.00 1,000,000 00H 0CH 0.00 00H 08H 0.00 00H 06H 0.00 1,250,000 00H 0AH 00H 05H -4.00 2,000,000 00H 06H 2,500,000 00H 05H 3,000,000 00H 04H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 -4.00 Setting prohibited 0.00 00H 04H 0.00 Setting prohibited -4.00 Setting prohibited 0.00 Page 708 of 1442 V850ES/JC3-H, V850ES/JE3-H Remark fXX: CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Main clock frequency ERR: Baud rate error (%) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. Figure 16-19. Allowable Baud Rate Range During Reception Latch timing UARTCn transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Parity bit Bit 7 Stop bit FLmax n = 0, 2 to 4 (V850ES/JC3-H (48 pin) (Except the PD70F3819), Remark V850ES/JE3-H (64 pin) (Except the PD70F3825)) n = 0, 2, 4 (V850ES/JC3-H (40 pin)) As shown in Figure 16-20, the receive data latch timing is determined by the counter set using the UCnCTL2 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. When this is applied to 11-bit reception, the following is the theoretical result. FL = (Brate)-1 Brate: UARTCn baud rate (n = 0 to 2, 4) k: Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (n = 0 to 2, 4) FL: 1-bit data length Latch timing margin: 2 clocks Minimum allowable transfer rate: FLmin = 11 x FL - R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 k-2 2k x FL = 21k + 2 FL 2k Page 709 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Therefore, the maximum baud rate that can be received by the destination is as follows. BRmax = (FLmin/11)-1 = 22k Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 10 k+2 x FLmax = 11 x FL - 2xk 11 FLmax = 21k - 2 x FL = 21k - 2 2xk FL FL x 11 20 k Therefore, the minimum baud rate that can be received by the destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate Obtaining the allowable baud rate error for UARTCn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. Table 16-5. Maximum/Minimum Allowable Baud Rate Error Division Ratio (k) Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 4 +2.32% -2.43% 8 +3.52% -3.61% 20 +4.26% -4.30% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.72% Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (n = 0 to 2, 4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 710 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (6) Transfer rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. Figure 16-20. Transfer Rate During Continuous Transfer Start bit of 2nd byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL The following equation can be obtained assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: fUCLK. FLstp = FL + 2/fUCLK Therefore, the transfer rate during continuous transmission is as follows. Transfer rate = 11 x FL + (2/fUCLK) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 711 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 16.8 Cautions (1) When the clock supply to UARTCn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDCn pin output also holds and outputs the value it had immediately before the clock supply was stopped. However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the circuits should be initialized by setting the UCnCTL0.UCnPWR, UCnCTL0.UCnRXEn, and UCnCTL0.UCnTXEn bits to 000. (2) Start up the UARTCn in the following sequence. <1> Set the UCnCTL0.UCnPWR bit to 1. <2> Set the ports. <3> Set the UCnCTL0.UCnTXE bit to 1, UCnCTL0.UCnRXE bit to 1. (3) Stop the UARTCn in the following sequence. <1> Set the UCnCTL0.UCnTXE bit to 0, UCnCTL0.UCnRXE bit to 0. <2> Set the ports and set the UCnCTL0.UCnPWR bit to 0 (it is not a problem if port setting is not changed). (4) In transmit mode (UCnCTL0.UCnPWR bit = 1 and UCnCTL0.UCnTXE bit = 1), do not overwrite the same value to the UCnTX register by software because transmission starts by writing to this register. To transmit the same value continuously, overwrite the same value. (5) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. However, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 712 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.1 Mode Switching of CSIF and Other Serial Interfaces 17.1.1 CSIF4 and UARTC0 mode switching In the V850ES/JC3-H and V850ES/JE3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used simultaneously. To use CSIF4, the use of CSIF4 must be set in advance, using the PMC3, PFC3 and PFCE3 registers. Caution The transmit/receive operation of CSIF4 and UARTC0 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-1. CSIF4 and UARTC0 Mode Switch Settings After reset: 00H PMC3 R/W PMC37Note1 PMC36Note1 PMC35Note2 PMC34 PMC33Note2 PMC32 After reset: 00H R/W 7 PFC3 PFC37 PMC31 PMC30 2 1 0 PFC32 PFC31 PFC30 PFCE31 PFCE30 Address: FFFFF466H 6 Note1 After reset: 00H PFCE3 Address: FFFFF446H PFC36 5 Note1 R/W PFC35 4 Note2 PFC34 3 PFC33 Note2 Address: FFFFF706H PFCE37Note1 PFCE36Note1PFCE35Note2 PFCE34 PFCE33Note2 PFCE32 PMC32 PFCE32 PFC32 0 x x Port I/O mode 1 0 0 ASCKC0 1 0 1 SCKF4 PMC3n PFC3n 0 x Port I/O mode 1 0 UARTC0 mode 1 1 CSIF4 mode Notes1. 2. Operation mode Operation mode V850ES/JC3-H (48 pin), V850ES/JE3-H only V850ES/JE3-H only Remarks 1. n = 0, 1 2. x = don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 713 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 2 17.1.2 CSIF0, UARTC4, and I C01 mode switching In the V850ES/JC3-H and V850ES/JE3-H, CSIF0, UARTC4, and I2C01 share the same pins and therefore cannot be used simultaneously. Switching among CSIF0, UARTC4, and I2C01 must be set in advance, using the PMC4, PFC4, and PFCE4 registers. Caution The transmit/receive operation of CSIF0, UARTC4, and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-2. CSIF0, UARTC4, and I2C01 Mode Switch Settings After reset: 00H PMC4 0 After reset: 00H PFC4 Address: FFFFF448H 0 R/W 0 0 0 PMC42 PMC41 PMC40 Address: FFFFF468H 7 6 5 4 3 2 1 0 0 0 0 0 0 PFC42 PFC41 PFC40 0 0 PFCE41 PFCE40 After reset: 00H PFCE4 R/W R/W Address: FFFFF708H 0 0 0 PMC4n PFCE4n PFC4n 0 Operation mode 0 x x Port I/O mode 1 0 0 CSIF0 mode 1 0 1 UARTC4 mode 1 1 0 I2C01 mode Remarks 1. n = 0, 1 2. x = don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 714 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.1.3 CSIF3 and UARTC2 mode switching In the V850ES/JC3-H and V850ES/JE3-H, CSIF3 and UARTC2 share the same pins and therefore cannot be used simultaneously. Switching between CSIF3 and UARTC2 must be set in advance, using the PMC9, PFC9 and PFCE9 registers. Caution The transmit/receive operation of CSIF3 and UARTC2 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-3. CSIF3 and UARTC2 Mode Switch Settings After reset: 0000H PMC9 15 14 0 0 PMC97 PMC96 After reset: 0000H PFC9 R/W 15 14 0 0 PFC97 PFC96 After reset: 0000H PFCE9 R/W R/W Address: FFFFF452H, FFFFF453H 9 8 PMC913 PMC912 PMC911 PMC910 13 0 0 PMC94Note PMC93Note PMC92Note 0 0 9 8 PFC911 PFC910 0 0 PFC94Note PFC93Note PFC92Note 0 0 9 8 PFCE911 PFCE910 0 0 PFCE94Note PFCE93Note PFCE92Note 0 0 0 12 11 10 Address: FFFFF472H, FFFFF473H 13 12 PFC913 PFC912 0 11 10 Address: FFFFF712H, FFFFF713H 15 14 13 12 0 0 0 0 PFCE97 PFCE96 0 11 10 Operation mode PMC91n PFCE91n PFC91n 0 x x Port I/O mode 1 0 0 CSIF3 mode 1 0 1 UARTC2 mode Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. n = 0, 1 2. x = don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 715 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.2 Features { Transfer rate: 12 Mbps max. (fXX = 48 MHz, using internal clock, CSIF3) 8 Mbps (fXX = 48 MHz, using internal clock, CSIF0, CSIF2, CSIF4) { Master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { Interrupt request signals (INTCFnT, INTCFnR) x 2 { Serial clock and data phase switchable { Transfer data length selectable in 1-bit units between 8 and 16 bits { Transfer data MSB-first/LSB-first switchable { 3-wire transfer SOFn: SIFn: Serial data output Serial data input SCKFn: Serial clock I/O { Transmission mode, reception mode, and transmission/reception mode specifiable Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 716 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.3 Configuration The following shows the block diagram of CSIFn. Figure 17-4. Block Diagram of CSIFn Internal bus CFnCTL1 CFnCTL0 CFnCTL2 CFnSTR INTCFnT Note fXX/3 fXX/4 fXX/6 fXX/8 fXX/32 fXX/64 Selector Controller fCCLK INTCFnR Phase control fBRGm CFnTX SCKFn SO latch SIFn Shift register Phase control SOFn CFnRX Note For CSIF3: fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXX/64 Remark fCCLK: Communication clock fXX: Main clock frequency fBRGm: Count clock of the baud rate generator n = 0, 2 to 4 m = 1 (n = 0) m = 2 (n = 2, 3) m = 3 (n = 4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 717 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) CSIFn includes the following hardware. Table 17-1. Configuration of CSIFn Item Configuration CSIFn receive data register (CFnRX) Registers CSIFn transmit data register (CFnTX) CSIFn control register 0 (CFnCTL0) CSIFn control register 1 (CFnCTL1) CSIFn control register 2 (CFnCTL2) CSIFn status register (CFnSTR) (1) CSIFn receive data register (CFnRX) The CFnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CFnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CFnRXL register. Reset sets this register to 0000H. In addition to reset input, the CFnRX register can be initialized by clearing (to 0) the CFnPWR bit of the CFnCTL0 register. After reset: 0000H R Address: CF0RX FFFFFD04H, CF2RX FFFFFD24H, CF3RX FFFFFD34HNote, CF4RX FFFFFD44H CFnRX (n = 0, 2 to 4) Note V850ES/JC3-H (48 pin), V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 718 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) CSIFn transmit data register (CFnTX) The CFnTX register is a 16-bit buffer register used to write the CSIFn transfer data. This register can be read or written in 16-bit units. The transmit operation is started by writing data to the CFnTX register in the transmission enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CFnTXL register. Reset sets this register to 0000H. After reset 0000H R/W Address: CF0TX FFFFFD06H, CF2TX FFFFFD26H, CF3TX FFFFFD36HNote, CF4TX FFFFFD46H CFnTX (n = 0, 2 to 4) Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remark The communication start conditions are shown below. Transmission mode (CFnTXE bit = 1, CFnRXE bit = 0): Write to CFnTX register Transmission/reception mode (CFnTXE bit = 1, CFnRXE bit = 1): Write to CFnTX register Reception mode (CFnTXE bit = 0, CFnRXE bit = 1): R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Read from CFnRX register Page 719 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.4 Registers The following registers are used to control CSIFn. * CSIFn control register 0 (CFnCTL0) * CSIFn control register 1 (CFnCTL1) * CSIFn control register 2 (CFnCTL2) * CSIFn status register (CFnSTR) (1) CSIFn control register 0 (CFnCTL0) CFnCTL0 is a register that controls the CSIFn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. (1/3) After reset: 01H R/W Address: CF0CTL0 FFFFFD00H, CF2CTL0 FFFFFD20H, CF3CTL0 FFFFFD30HNote1, CF4CTL0 FFFFFD40H < > < > CFnCTL0 < > < > < > CFnPWR CFnTXENote2 CFnRXENote2 CFnDIRNote2 0 0 CFnTMSNote2 CFnSCE (n = 0, 2 to 4) CFnPWR Specification of CSIFn operation disable/enable 0 Disables CSIFn operation and resets the CFnSTR register 1 Enables CSIFn operation * The CFnPWR bit controls the CSIFn operation and resets the internal circuit. CFnTXENote2 Specification of transmit operation disable/enable 0 Disables transmit operation 1 Enables transmit operation * The SOFn output is low level when the CFnTXE bit is 0. CFnRXENote2 Specification of receive operation disable/enable 0 Disables receive operation 1 Enables receive operation * No reception completion interrupt is output even when the prescribed data is transferred, and the receive data (CFnRX register) is not updated, because the receive operation is disabled by clearing the CFnRXE bit to 0. Notes1. 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only These bits can only be rewritten when the CFnPWR bit = 0. However, CFnPWR bit = 1 can also be set at the same time as rewriting these bits. Caution To forcibly suspend transmission/reception, clear the CFnPWR bit to 0 instead of the CFnRXE and CFnTXE bits. At this time, the clock output is stopped. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 720 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/3) CFnDIRNote Specification of transfer direction mode (MSB/LSB) 0 MSB-first transfer 1 LSB-first transfer CFnTMSNote Transfer mode specification 0 Single transfer mode 1 Continuous transfer mode [In single transfer mode] The reception completion interrupt (INTCFnR) occurs when communication is complete. Even if transmission is enabled (CFnTXE bit = 1), the transmission enable interrupt (INTCFnT) does not occur. If the next transmit data is written during communication (CFnSTR.CFnTSF bit = 1), it is ignored and the next communication is not started. Also, if reception-only communication is set (CFnTXE bit = 0, CFnRXE bit = 1), the next communication is not started even if the receive data is read during communication (CFnSTR. CFnTSF bit = 1). [In continuous transfer mode] The continuous transmission is enabled by writing the next transmit data during communication (CFnSTR.CFnTSF bit = 1). Writing the next transmission data is enabled after a transmission enable interrupt (INTCFnT) occurs. If reception-only communication is set (CFnTXE bit = 0, CFnRXE bit = 1) in the continuous transfer mode, the next reception is started immediately after a reception completion interrupt (INTCFnR), regardless of the read operation of the CFnRX register. Therefore, immediately read the receive data from the CFnRX register. If this read operation is delayed, an overrun error (CFnOVE bit = 1) occurs. Note These bits can only be rewritten when the CFnPWR bit = 0. However, the CFnPWR can be set to 1 at the same time as these bits are rewritten. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 721 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (3/3) CFnSCE Specification of start transfer disable/enable 0 Communication start trigger invalid 1 Communication start trigger valid * In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode A communication operation can be started by writing data to the CFnTX register when the CFnSCE bit is 1. Set the CFnSCE bit to 1. (b) In single reception mode Disable starting the next receive operation by clearing the CFnSCE bit to 0 before reading the last receive data, because a receive operation is started by reading receive data (CFnRX register)Note 1. (c) In continuous reception mode Clear the CFnSCE bit to 0 one communication clock before reception of the last data is completed to disable the start of reception after the last data is receivedNote 2. * In slave mode This bit enables or disables the communication start trigger. Set the CFnSCE bit to 1. [Usage of CFnSCE bit] * In single reception mode <1>When reception of the last data is completed by INTCFnR interrupt servicing, clear the CFnSCE bit to 0 before reading the CFnRX register. <2>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to disable reception. To continue reception, set the CFnSCE bit to 1 to start the next reception by dummy-reading the CFnRX register. * In continuous reception mode <1>Clear the CFnSCE bit to 0 during reception of the last data by INTCFnR interrupt servicing. <2>Read the CFnRX register. <3>Read the last reception data by reading the CFnRX register after acknowledging the CFnTIR interrupt. <4>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to disable reception. To continue reception, set the CFnSCE bit to 1 to wait for the next reception by dummy-reading the CFnRX register. Notes 1. If the CFnSCE bit is read while it is 1, the next communication operation is started. 2. The CFnSCE bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication operation is automatically started. Caution R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Be sure to clear bits 3 and 2 to "0". Page 722 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) CSIFn control register 1 (CFnCTL1) CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0. After reset: 00H R/W Address: CF0CTL1 FFFFFD01H, CF2CTL1 FFFFFD21H, CF3CTL1 FFFFFD31HNote1 , CF4CTL1 FFFFFD41H CFnCTL1 0 0 CFnCKP CFnDAP CFnCKS2 CFnCKS1 CFnCKS0 0 (n = 0, 2 to 4) Specification of data transmission/ reception timing in relation to SCKFn CFnCKP CFnDAP 0 Communication type 1 0 SCKFn (I/O) D7 SOFn (output) D6 D5 D4 D3 D2 D1 D0 SIFn capture 0 Communication type 2 1 SCKFn (I/O) SOFn (output) D7 D6 D5 D4 D3 D2 D1 D0 SIFn capture 1 Communication type 3 0 SCKFn (I/O) D7 SOFn (output) D6 D5 D4 D3 D2 D1 D0 SIFn capture 1 Communication type 4 1 SCKFn (I/O) SOFn (output) D7 D6 D5 D4 D3 D2 D1 D0 SIFn capture CFnCKS2 CFnCKS1 CFnCKS0 Communication clock (fCCLK) n = 0, 2, 4 0 0 0 0 0 1 0 1 0 1 1 1 Note 2 Mode Note 3 n=3 fXX/3 fXX/2 Master mode fXX/4 fXX/4 Master mode 0 fXX/6 fXX/8 Master mode 1 fXX/8 fXX/16 Master mode 0 0 fXX/32 fXX/32 Master mode 0 1 fXX/64 fXX/64 Master mode 1 1 0 fBRGm Master mode 1 1 1 External clock (SCKFn) Slave mode Notes 1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. Set the communication clock (fCCLK) to 8 MHz or lower. 3. Set the communication clock (fCCLK) to 12 MHz or lower. Remark When n = 0, m = 1 When n = 2, 3, m = 2 When n = 4, m = 3 For details of fBRGm, see 17.8 Baud Rate Generator. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 723 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (3) CSIFn control register 2 (CFnCTL2) CFnCTL2 is an 8-bit register that controls the number of CSIFn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CFnCTL2 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0 or when both the CFnTXE and CFnRXE bits = 0. After reset: 00H R/W Address: CF0CTL2 FFFFFD02H, CF2CTL2 FFFFFD22H, CF3CTL2 FFFFFD32HNote, CF4CTL2 FFFFFD42H CFnCTL2 0 0 0 0 CFnCL3 CFnCL2 CFnCL1 CFnCL0 (n = 0, 2 to 4) CFnCL3 CFnCL2 CFnCL1 CFnCL0 Serial register bit length 0 0 0 0 8 bits 0 0 0 1 9 bits 0 0 1 0 10 bits 0 0 1 1 11 bits 0 1 0 0 12 bits 0 1 0 1 13 bits 0 1 1 0 14 bits 0 1 1 1 15 bits 1 x x x 16 bits Note V850ES/JC3-H (48 pin), V850ES/JE3-H only Remarks 1. If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the LSB of the CFnTX and CFnRX registers. 2. x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 724 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (a) Transfer data length change function The CSIFn transfer data length can be set in 1-bit units between 8 and 16 bits using the CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CFnTX or CFnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) Transfer bit length = 10 bits, MSB first SOFn SIFn 15 10 9 0 Insertion of 0 (ii) Transfer bit length = 12 bits, LSB first SIFn 15 12 SOFn 11 0 Insertion of 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 725 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (4) CSIFn status register (CFnSTR) CFnSTR is an 8-bit register that displays the CSIFn status. This register can be read or written in 8-bit or 1-bit units, but the CFnTSF flag is read-only. Reset sets this register to 00H. In addition to reset input, the CFnSTR register can be initialized by clearing (0) the CFnCTL0.CFnPWR bit. After reset: 00H R/W Address: CF0STR FFFFFD03H, CF2STR FFFFFD23H, CF3STR FFFFFD33HNote, CF4STR FFFFFD43H < > < > CFnSTR CFnTSF 0 0 0 0 0 0 CFnOVE (n = 0, 2 to 4) CFnTSF Communication status flag 0 Communication stopped 1 Communicating * During transmission, this register is set when data is prepared in the CFnTX register, and during reception, it is set when a dummy read of the CFnRX register is performed. When transfer ends, this flag is cleared to 0 at the last edge of the clock. CFnOVE Overrun error flag 0 No overrun 1 Overrun * An overrun error occurs when the next reception is completed without the CPU reading the value of the receive buffer, upon completion of the receive operation. The CFnOVE flag displays the overrun error occurrence status in this case. * The CFnOVE bit is valid also in the single transfer mode. Therefore, when only using transmission, note the following. * Do not check the CFnOVE flag. * Read this bit even if reading the reception data is not required. * The CFnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 726 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.5 Interrupt Request Signals CSIFn can generate the following two types of interrupt request signals. * Reception completion interrupt request signal (INTCFnR) * Transmission enable interrupt request signal (INTCFnT) Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. Table 17-2. Interrupts and Their Default Priority Interrupt Priority Reception complete High Transmission enable Low (1) Reception completion interrupt request signal (INTCFnR) When receive data is transferred to the CFnRX register while reception is enabled, the reception completion interrupt request signal is generated. This interrupt request signal can also be generated if an overrun error occurs. When the reception completion interrupt request signal is acknowledged and the data is read, read the CFnSTR register to check that the result of reception is not an error. In the single transfer mode, the INTCFnR interrupt request signal is generated upon completion of transmission, even when only transmission is executed. (2) Transmission enable interrupt request signal (INTCFnT) In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from the CFnTX register and, as soon as writing to CFnTX has been enabled, the transmission enable interrupt request signal is generated. In the single transmission and single transmission/reception modes, the INTCFnT interrupt is not generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 727 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6 Operation 17.6.1 Single transfer mode (master mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 00H CFnCTL2 register 00H CFnCTL0 register C1H (4) Write CFnTX register (5) Start transmission (6) INTCFnR interrupt generated? No Yes Transmission completed? No (7) Yes (8) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 728 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 (5) Bit 2 Bit 1 Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 (8) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start transmission. (5) When transmission is started, output the serial clock to the SCKFn pin, and output the transmit data from the SOFn pin in synchronization with the serial clock. (6) When transmission of the transfer data length set with the CFnCTL2 register is completiond, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) To continue transmission, start the next transmission by writing the transmit data to the CFnTX register again after the INTCFnR signal is generated. (8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 729 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.2 Single transfer mode (master mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 00H CFnCTL2 register 00H CFnCTL0 register A1H (4) CFnRX register dummy read (5) Start reception (6) INTCFnR interrupt generated? No Yes Reception completed? Yes (8) CFnSCE bit = 0 (CFnCTL0) (9) Read CFnRX register (10) CFnCTL0 register 00H No (7) Read CFnRX register END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 730 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start reception. (5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the SIFn pin in synchronization with the serial clock. (6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial clock output and data capturing, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the INTCFnR signal is generated. (8) To read the CFnRX register without starting the next reception, write the CFnSCE bit = 0. (9) Read the CFnRX register. (10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 731 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register E1H (4) Write CFnTX register (5) Start transmission/reception (6) INTCFnR interrupt generated? No Yes (7), (9) Read CFnRX register Transmission/reception completed? No (8) Yes (10) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 732 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write E1H to the CFnCTL0 register, and select the transmission/reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start transmission/reception. (5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn pin. (6) When transmission/reception of the transfer data length set by the CFnCTL2 register is completed, stop the serial clock output, transmit data output, and data capturing, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) Read the CFnRX register. (8) To continue transmission/reception, write the transmit data to the CFnTX register again. (9) Read the CFnRX register. (10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 733 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register C1H (4) Write CFnTX register (4) SCKFn pin input started? No Yes (5) Start transmission (6) INTCFnR interrupt generated? No Yes Transmission completed? No (7) Yes (8) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 734 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (5) Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 (8) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the serial clock. (6) When transmission of the transfer data length set with the CFnCTL2 register is completed, stop the serial clock input and transmit data output, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnR signal is generated, and wait for a serial clock input. (8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 735 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.5 Single transfer mode (slave mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register A1H (4) CFnRX register dummy read (4) SCKFn pin input started? No Yes (5) Start reception (6) INTCFnR interrupt generated? No Yes (6) Reception completed? Yes (8) CFnSCE bit = 0 (CFnCTL0) (9) Read CFnRX register (10) CFnCTL0 register 00H No (7) Read CFnRX register END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 736 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by performing a dummy read of the CFnRX register, and the device waits for a serial clock input. (5) When a serial clock is input, capture the receive data of the SIFn pin in synchronization with the serial clock. (6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial clock input and data capturing, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the INTCFnR signal is generated, and wait for a serial clock input. (8) To end reception, write the CFnSCE bit = 0. (9) Read the CFnRX register. (10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 737 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register E1H (4) Write CFnTX register (4) SCKFn pin input started? No Yes (5) Start transmission/reception (6) INTCFnR interrupt generated? No Yes (7), (9) Read CFnRX register Transmission/reception completed? No (8) Yes (10) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 738 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write E1H to the CFnCTL0 register, and select the transmission/reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn pin. (6) When transmission/reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial clock input, transmit data output, and data capturing, generate the reception completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0. (7) Read the CFnRX register. (8) To continue transmission/reception, write the transmit data to the CFnTX register again, and wait for a serial clock input. (9) Read the CFnRX register. (10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 739 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) (4), (8) CFnCTL1 register 00H CFnCTL2 register 00H CFnCTL0 register C3H Write CFnTX register (5) Start transmission (6), (9) INTCFnT interrupt generated? No Yes Transmission completed? No (7) Yes (10) CFnTSF bit = 0? (CFnSTR register) No Yes (11) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 740 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnT signal INTCFnR signal L SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (8) (9) (10) (11) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write C3H to the CFnCTL0 register, and select the transmission mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start transmission. (5) When transmission is started, output the serial clock to the SCKFn pin, and output the transmit data from the SOFn pin in synchronization with the serial clock. (6) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is generated. (7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal is generated. (8) When a new transmit data is written to the CFnTX register before communication completion, the next communication is started following communication completion. (9) The transfer of the transmit data from the CFnTX register to the shift register is completed and the INTCFnT signal is generated. To end continuous transmission with the current transmission, do not write to the CFnTX register. (10) When the next transmit data is not written to the CFnTX register before transfer completion, stop the serial clock output to the SCKFn pin after transfer completion, and clear the CFnTSF bit to 0. (11) To release the transmission enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0 after checking that the CFnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCFnR) is not generated. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 741 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 742 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register 00H CFnCTL2 register 00H CFnCTL0 register A3H (4) CFnRX register dummy read (5) Start reception No INTCFnR interrupt generated? Yes CFnOVE bit = 1? (CFnSTR) No (6) Yes (8) Is data being received last data? CFnSCE bit = 0 (CFnCTL0) No (7) Yes (9) Read CFnRX register (12) CFnOVE bit = 0 (CFnSTR) (8) CFnSCE bit = 0 (CFnCTL0) (9) (9) Read CFnRX register (10) INTCFnR interrupt generated? Read CFnRX register No Yes (11) (13) CFnTSF bit = 0? (CFnSTR) Read CFnRX register No Yes (13) CFnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 743 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal CFnSCE bit SCKFn pin SOFn pin L SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write A3H to the CFnCTL0 register, and select the reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start reception. (5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the SIFn pin in synchronization with the serial clock. (6) When reception is completed, the reception completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is enabled. (7) When the CFnCTL0.CFnSCE bit = 1 upon communication completion, the next communication is started following communication completion. (8) To end continuous reception with the current reception, write the CFnSCE bit = 0. (9) Read the CFnRX register. (10) When reception is completed, the INTCFnR signal is generated, and reading of the CFnRX register is enabled. When the CFnSCE bit = 0 is set before communication completion, stop the serial clock output to the SCKFn pin, and clear the CFnTSF bit to 0, to end the receive operation. (11) Read the CFnRX register. (12) If an overrun error occurs, write the CFnSTR.CFnOVE bit = 0, and clear the error flag. (13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 744 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 745 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register 00H CFnCTL2 register 00H CFnCTL0 register E3H (4) Write CFnTX register (5) Start transmission/reception (6), (11) INTCFnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CFnTX register INTCFnR interrupt generated? (8) Yes No (9) CFnOVE bit = 1? (CFnSTR) (10) Read CFnRX register Yes (13) (13) Read CFnRX register Is receive data last data? (14) (15) CFnOVE bit = 0 (CFnSTR) CFnTSF bit = 0? (CFnSTR) No Yes (12) No Yes (15) CFnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 746 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing (1/2) CFnTSF bit INTCFnT signal INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2 or fXX/3, and master mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start transmission/reception. (5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn pin. (6) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is generated. (7) To continue transmission/reception, write the transmit data to the CFnTX register again after the INTCFnT signal is generated. (8) When one transmission/reception is completed, the reception completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is enabled. (9) When a new transmit data is written to the CFnTX register before communication completion, the next communication is started following communication completion. (10) Read the CFnRX register. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 747 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (11) The transfer of the transmit data from the CFnTX register to the shift register is completed and the INTCFnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CFnTX register. (12) When the next transmit data is not written to the CFnTX register before transfer completion, stop the serial clock output to the SCKFn pin after transfer completion, and clear the CFnTSF bit to 0. (13) When the reception error interrupt request signal (INTCFnR) is generated, read the CFnRX register. (14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag. (15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 748 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register C3H (4) Write CFnTX register (4) SCKFn pin input started? No Yes (5), (8) Start transmission (6), (9) INTCFnT interrupt generated? No Yes (9) Transmission completed? No (7) Yes (10) CFnTSF bit = 0? (CFnSTR register) No Yes (11) CFnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 749 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnT signal SCKFn pin SOFn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 (8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (9) Bit 0 (10) (11) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write C3H to the CFnCTL0 register, and select the transmission mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the serial clock. (6) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is generated. (7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal is generated. (8) When a serial clock is input following completion of the transmission of the transfer data length set with the CFnCTL2 register, continuous transmission is started. (9) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the INTCFnT signal is generated. To end continuous transmission with the current transmission, do not write to the CFnTX register. (10) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the CFnTX register, clear the CFnTSF bit to 0 to end transmission. (11) To release the transmission enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0 after checking that the CFnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCFnR) is not generated. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 750 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 751 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register A3H (4) CFnRX register dummy read (4) SCKFn pin input started? No Yes (5) Reception start No INTCFnR interrupt generated? Yes CFnOVE bit = 1? (CFnSTR) No (6) Yes (8) (9) CFnSCE bit = 0 (CFnCTL0) Is data being received last data? Read CFnRX register (7) Yes (8) (12) No CFnOVE bit = 0 (CFnSTR) CFnSCE bit = 0 (CFnCTL0) (9) (9) Read CFnRX register (10) INTCFnR interrupt generated? Read CFnRX register No Yes (11) (13) CFnTSF bit = 0? (CFnSTR) Read CFnRX register No Yes (13) CFnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 752 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing CFnTSF bit INTCFnR signal CFnSCE bit SCKFn pin SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write A3H to the CFnCTL0 register, and select the reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by performing a dummy read of the CFnRX register, and the device waits for a serial clock input. (5) When a serial clock is input, capture the receive data of the SIFn pin in synchronization with the serial clock. (6) When reception is completed, the reception completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is enabled. (7) When a serial clock is input in the CFnCTL0.CFnSCE bit = 1 status, continuous reception is started. (8) To end continuous reception with the current reception, write the CFnSCE bit = 0. (9) Read the CFnRX register. (10) When reception is completed, the INTCFnR signal is generated, and reading of the CFnRX register is enabled. When CFnSCE bit = 0 is set before communication completion, clear the CFnTSF bit to 0 to end the receive operation. (11) Read the CFnRX register. (12) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag. (13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 753 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 754 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (1) Operation flow START (1), (2), (3) CFnCTL1 register 07H CFnCTL2 register 00H CFnCTL0 register E3H (4) Write CFnTX register (4) SCKFn pin input started? No Yes (5) (6), (11) Start transmission/reception INTCFnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CFnTX register INTCFnR interrupt generated? (8) Yes No (9) CFnOVE bit = 1? (CFnSTR) (10) Yes (13) (13) Read CFnRX register (14) CFnOVE bit = 0 (CFnSTR) Read CFnRX register Is receive data last data? No Yes (12) (15) CFnTSF bit = 0? (CFnSTR) No Yes (15) CFnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 755 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Operation timing (1/2) CFnTSF bit INTCFnT signal INTCFnR signal SCKFn pin SOFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIFn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKFn), and slave mode. (2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits. (3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn pin. (6) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is generated. (7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal is generated. (8) When reception of the transfer data length set with the CFnCTL2 register is completed, the reception completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is enabled. (9) When a serial clock is input continuously, continuous transmission/reception is started. (10) Read the CFnRX register. (11) When transfer of the transmit data from the CFnTX register to the shift register is completed and writing to the CFnTX register is enabled, the INTCFnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CFnTX register. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 756 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (12) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the CFnTX register, the INTCFnR signal is generated. Clear the CFnTSF bit to 0 to end transmission/reception. (13) When the INTCFnR signal is generated, read the CFnRX register. (14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag. (15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 757 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.13 Reception error When transfer is performed with reception enabled (CFnCTL0.CFnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCFnR) is generated again when the next receive operation is completed before the CFnRX register is read after the INTCFnR signal is generated, and the overrun error flag (CFnSTR.CFnOVE) is set to 1. Even if an overrun error has occurred, the previous receive data is lost since the CFnRX register is updated. Even if a reception error has occurred, the INTCFnR signal is generated again upon the next reception completion if the CFnRX register is not read. To avoid an overrun error, complete reading the CFnRX register by one half clock before sampling the last bit of the next receive data from the INTCFnR signal generation. (1) Operation timing CFnRX register read signal INTCFnR signal CFnOVE bit CFnRX register AAH Shift register 01H 02H 05H 0AH 15H 2AH 55H AAH 00H 01H 55H 02H 05H 0AH 15H 2AH 55H SCKFn pin SIFn pin SIFn pin capture timing (1) (2) (3)(4) (1) Start continuous transfer. (2) Completion of the first transfer (3) The CFnRX register cannot be read until one half clock before the completion of the second transfer. (4) An overrun error occurs, and the reception completion interrupt request signal (INTCFnR) is generated, and then the overrun error flag (CFnSTR.CFnOVE) is set to 1. The receive data is overwritten. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 758 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.6.14 Clock timing (1/2) (i) Communication type 1 (CFnCKP and CFnDAP bits = 00) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit (ii) Communication type 3 (CFnCKP and CFnDAP bits = 10) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. In the single transmission or single transmission/reception mode, the INTCFnT interrupt request signal is not generated, but the INTCFnR interrupt request signal is generated upon end of communication. 2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is generated even in the transmission mode, upon end of communication. Caution In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored. This has no effect on the operation during transfer. For example, if the next data is written to the CFnTX register when DMA is started by generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 759 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2/2) (iii) Communication type 2 (CFnCKP and CFnDAP bits = 01) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit (iv) Communication type 4 (CFnCKP and CFnDAP bits = 11) SCKFn pin SIFn capture SOFn pin D7 D6 D5 D4 D3 Reg-R/W INTCFnT interruptNote 1 INTCFnR interruptNote 2 CFnTSF bit Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. In the single transmission or single transmission/reception modes, the INTCFnT interrupt request signal is not generated, but the INTCFnR interrupt request signal is generated upon end of communication. 2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is generated even in the transmission mode, upon end of communication. Caution In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored. This has no effect on the operation during transfer. For example, if the next data is written to the CFnTX register when DMA is started by generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 760 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.7 Output Pins (1) SCKFn pin When CSIFn operation is disabled (CFnCTL0.CFnPWR bit = 0), the SCKFn pin output status is as follows. CFnCKP CFnCKS2 CFnCKS1 CFnCKS0 0 1 1 1 Other than above 1 1 1 High impedance Fixed to high level 1 Other than above SCKFn Pin Output High impedance Fixed to low level Remarks 1. The output level of the SCKFn pin changes if any of the CFnCTL1.CFnCKP or CFnCKS2 to CFnCKS0 bits is rewritten. 2. n = 0, 2 to 4 (2) SOFn pin When CSIFn operation is disabled (CFnPWR bit = 0), the SOFn pin output status is as follows. CFnTXE CFnDAP CFnDIR 0 x x Fixed to low level 1 0 x SOFn latch value (low level) 1 SOFn Pin Output 0 CFnTX value (MSB) 1 CFnTX value (LSB) Remarks 1. The SOFn pin output changes when any one of the CFnCTL0.CFnTXE, CFnCTL0.CFnDIR or CFnCTL1.CFnDAP bit is rewritten. 2. x: Don't care 3. n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 761 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.8 Baud Rate Generator The BRG1 to BRG3 baud rate generators are connected to CSIF0, CSIF2 to CSIF4 as shown in the following block diagram. fXX BRG1 fXX BRG2 fBRG1 CSIF0 fBRG2 CSIF2 CSIF3 fXX BRG3 fBRG3 CSIF4 (1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIF. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSM1 FFFFF320H, PRSM2 FFFFF324H, PRSM3 FFFFF328H < > PRSMm (m = 1 to 3) 0 0 0 BGCEm BGCEm 0 0 BGCSm1 BGCSm0 Baud rate output 0 Disabled 1 Enabled Input clock selection (fBGCSm) BGCSm1 BGCSm0 0 0 0 1 1 Setting value (k) fXX 0 1 fXX/2 1 0 fXX/4 2 1 fXX/8 3 Cautions 1. Do not rewrite the PRSMm register during operation. 2. Set the PRSMm register before setting the BGCEm bit to 1. 3. Be sure to set bits 7 to 5, 3, and 2 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 762 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H PRSCMm PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 Cautions 1. Do not rewrite the PRSCMm register during operation. 2. Set the PRSCMm register before setting the PRSMm.BGCEm bit to 1. 17.8.1 Baud rate generation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. fXX fBRGm = k+1 2 Caution Remark xN Set fBRGm to 8 MHz, (CSIF0, CSIF2 and CSIF4), 12 MHz (CSIF3), or lower. fBRGm: BRGm count clock fXX: Main clock oscillation frequency k: PRSMm register setting value = 0 to 3 N: PRSCMm register setting value = 1 to 256 However, N = 256 only when the PRSCMm register is set to 00H. m = 1 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 763 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 17 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) 17.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CFnSTR.CFnOVE bit after DMA transfer has been completed. (2) If a register that is prohibited to be rewritten during operation (CFnCTL0.CFnPWR bit = 1) is rewritten by mistake during operation, set the CFnCTL0.CFnPWR bit to 0 once, then initialize CSIFn. Registers to which rewriting during operation is prohibited are shown below. * CFnCTL0 register: CFnTXE, CFnRXE, CFnDIR, CFnTMS bits * CFnCTL1 register: CFnCKP, CFnDAP, CFnCKS2 to CFnCKS0 bits * CFnCTL2 register: CFnCL3 to CFnCL0 bits (3) In communication type 2 or 4 (CFnCTL1.CFnDAP bit = 1), the CFnSTR.CFnTSF bit is cleared half a SCKFn clock after the occurrence of a reception completion interrupt (INTCFnR). In the single transfer mode, writing the next transmit data is ignored during communication (CFnTSF bit = 1), and the next communication is not started. Also if reception-only communication (CFnCTL0.CFnTXE bit = 0, CFnCTL0.CFnRXE bit = 1) is set, the next communication is not started even if the receive data is read during communication (CFnTSF bit = 1). Therefore, when using the single transfer mode with communication type 2 or 4 (CFnDAP bit = 1), pay particular attention to the following. * To start the next transmission, confirm that CFnTSF bit = 0 and then write the transmit data to the CFnTX register. * To perform the next reception continuously when reception-only communication (CFnTXE bit = 0, CFnRXE bit = 1) is set, confirm that CFnTSF bit = 0 and then read the CFnRX register. Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode is recommended especially when using DMA. Remark n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 764 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS To use the I2C bus function, set the P36/SCL00, P37/SDA00, P40/SDA01, and P41/SCL01 pins as alternatefunction pins, and set them to N-ch open-drain output. The V850ES/JC3-H and V850ES/JE3-H includes I2C. The number of channels differs depending on the product. Table 18-1 shows the number of channels of each product. Table 18-1. Number of Channels of I2C BUS Part Number Number of Channels V850ES/JC3-H (40 pin) 1 channel V850ES/JC3-H (48 pin) 2 channels V850ES/JE3-H(64 pin) 2 channels In this chapter, the number of channels is expressed as n. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 765 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.1 Mode Switching of I2C Bus and Other Serial Interfaces 18.1.1 UARTC3 and I2C00 mode switching In the V850ES/JC3-H (48 pin) and V850ES/JE3-H, UARTC3 and I2C00 share the same pins and therefore cannot be used simultaneously. Switching between UARTC3 and I2C00 must be set in advance, using the PMC3, PFC3, and PFCE3 registers. Caution The transmit/receive operation of UARTC3 and I2C00 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 18-1. UARTC3 and I2C00 Mode Switch Settings After reset: 00H PMC3 R/W 7 PFC37 PMC33Note2 PMC32 PMC31 PMC30 2 1 0 PFC32 PFC31 PFC30 PFCE31 PFCE30 Address: FFFFF466H 6 Note1 After reset: 00H PFCE3 Address: FFFFF446H PMC37Note1 PMC36Note1 PMC35Note2 PMC34 After reset: 00H PFC3 R/W PFC36 5 Note1 R/W PFC35 4 Note2 PFC34 3 PFC33 Note2 Address: FFFFF706H PFCE37Note1 PFCE36Note1 PFCE35Note2 PFCE34 PFCE33Note2 PFCE32 PMC3m PFCE3m Operation mode PFC3m 0 x x Port I/O mode 1 0 0 UARTC3 mode 1 0 1 I2C00 mode Notes1. V850ES/JC3-H (48 pin), V850ES/JE3-H only 2. V850ES/JE3-H only Remarks 1. m = 6, 7 2. x = don't care + R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 766 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 2 18.1.2 UARTC4, CSIF0, and I C01 mode switching In the V850ES/JC3-H and V850ES/JE3-H, UARTC4, CSIF0, and I2C01 share the same pins and therefore cannot be used simultaneously. Switching among UARTC4, CSIF0, and I2C01 must be set in advance, using the PMC4, PFC4, and PFCE4 registers. Caution The transmit/receive operation of UARTC4, CSIF0, and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 18-2. UARTC4, CSIF0, and I2C01 Mode Switch Settings After reset: 00H PMC4 0 After reset: 00H PFC4 0 After reset: 00H PFCE4 R/W Address: FFFFF448H 0 R/W 0 0 PMC42 PMC41 PMC40 0 PFC42 PFC41 PFC40 0 0 PFCE41 PFCE40 Address: FFFFF468H 0 R/W 0 0 0 Address: FFFFF708H 0 0 0 0 PMC4m PFC4m PFCE4m 0 x x Port I/O mode 1 0 0 CSIF0 mode 1 0 1 I2C01 mode 1 1 0 UARTC4 mode Operation mode Remarks 1. m = 0, 1 2. x = don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 767 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.2 Features I2C00, I2C01 have the following two modes. * Operation stop mode * I2C (Inter IC) bus mode (multimasters supported) (1) Operation stop mode In this mode, serial transfer is not performed, thus enabling a reduction in power consumption. (2) I2C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a serial data bus pin (SDA0n). This mode complies with the I2C bus format and the master device can generate "start condition", "address", "transfer direction specification", "data", and "stop condition" data for the slave device on the serial data bus. The slave device automatically detects the received statuses and data by hardware. This function can simplify the part of an application program that controls the I2C bus. Since SCL0n and SDA0n pins are used for N-ch open-drain outputs, I2C0n requires pull-up resistors for the serial clock line and the serial data bus line. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 768 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.3 Configuration The block diagram of the I2C0n is shown below. Figure 18-4. Block Diagram of I2C0n Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Slave address register n (SVAn) SDA0n Set Match signal Noise eliminator IIC shift register n (IICn) DFCn D Q Stop condition generator SO latch CLn1, CLn0 Data retention time correction circuit TRCn N-ch open-drain output Start condition generator Clear Acknowledge generator Output control Wakeup controller Acknowledge detector Start condition detector Stop condition detector SCL0n Noise eliminator Interrupt request signal generator Serial clock counter DFCn Serial clock controller IIC shift register n (IICn) IICCn.STTn, SPTn IICSn.MSTSn, EXCn, COIn fxx Prescaler IICSn.MSTSn, EXCn, COIn Serial clock wait controller N-ch open-drain output INTIICn Bus status detector Prescaler fxx to fxx/5 OCKSENn OCKSTHn OCKSn1 OCKSn0 CLDn DADn SMCn DFCn CLn1 CLn0 IIC division clock select register m (OCKSm) IIC clock select register n (IICCLn) CLXn STCFn IICBSYn STCENn IICRSVn IIC function expansion register n (IICXn) IIC flag register n (IICFn) Internal bus Remark m=1 fXX : Main clock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 769 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H A serial bus configuration example is shown below. Figure 18-5. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 SDA Slave CPU1 Address 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 SCL Serial data bus Serial clock SDA Master CPU2 Slave CPU2 SCL Address 2 SDA Slave CPU3 SCL Address 3 SDA Slave IC SCL Address 4 SDA Slave IC SCL Address N Page 770 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 2 I C0n includes the following hardware Table 18-2. Configuration of I2C0n Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn) IIC status register n (IICSn) IIC flag register n (IICFn) IIC clock select register n (IICCLn) IIC function expansion register n (IICXn) IIC division clock select registers 0, 1 (OCKS0, OCKS1) (1) IIC shift register n (IICn) The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception Write and read operations to the IICn register are used to control the actual transmit and receive operations. This register can be read or written in 8-bit units. Reset sets this register to 00H. (2) Slave address register n (SVAn) The SVAn register sets local addresses when in slave mode This register can be read or written in 8-bit units. Reset sets this register to 00H. (3) SO latch The SO latch is used to retain the output level of the SDA0n pin (4) Wakeup controller This circuit generates an interrupt request signal (INTIICn) when the address value set to the SVAn register matches the received address or when an extension code is received (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 771 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I2C interrupt is generated by either of the following two triggers. * The falling edge of the eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) * Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit) (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits are used to generate and detect various statuses. (11) Data hold time correction circuit This circuit generates the hold time for the data corresponding to the falling edge of the SCL0n pin. (12) Start condition generator This circuit generates a start condition when the IICCn.STTn bit is set. However, when in the communication reservation disabled status (IICFn.IICRSVn bit = 1) and when the bus is not released (IICFn.IICBSYn bit = 1), this request is ignored and the IICFn.STCFn bit is set to 1. (13) Stop condition generator This circuit generates a stop condition when the IICCn.SPTn bit is set. (14) Bus status detector This circuit detects whether the bus is released by detecting a start condition and stop condition. However, the bus status cannot be detected immediately after operation, so set the bus status detector to the initial status by using the IICFn.STCENn bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 772 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.4 Registers I2C00 to I2C01 are controlled by the following registers. * IIC control registers 0 to 1 (IICC0 to IICC1) * IIC status registers 0 to 1 (IICS0 to IICS1) * IIC flag registers 0 to 1 (IICF0 to IICF1) * IIC clock select registers 0 to 1 (IICCL0 to IICCL1) * IIC function expansion registers 0 to 1 (IICX0 to IICX1) * IIC division clock select registers 0, 1 (OCKS0, OCKS1) The following registers are also used. * IIC shift registers 0 to 1 (IIC0 to IIC1) * Slave address registers 0 to 1 (SVA0 to SVA1) Remark For the alternate-function pin settings, see Table 4-17 Settings When Port Pins Are Used for Alternate Functions. (1) IIC control registers 0, 1 (IICC0, IICC1) The IICCn registers enable/stop I2C0n operations, set the wait timing, and set other I2C operations. These registers can be read or written in 8-bit or 1-bit units. However, set the SPIEn, WTIMn, and ACKEn bits when the IICEn bit is 0 or during the wait period. When changing the IICEn bit from "0" to "1", these bits can also be set at the same time. Reset sets these registers to 00H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 773 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (1/4) After reset: 00H IICCn R/W Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H <7> <6> <5> <4> <3> <2> <1> <0> IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Specification of I2Cn operation enable/disable 0 Operation stopped. IICSn register reset 1 Operation enabled. Note 1 . Internal operation stopped. Be sure to set this bit to 1 when the SCL0n and SDA0n lines are high level. Condition for clearing (IICEn bit = 0) Condition for setting (IICEn bit = 1) * Cleared by instruction * Set by instruction * After reset LRELn Note 2 Exit from communications 0 Normal operation 1 This exits from the current communication operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0n and SDA0n lines are set to high impedance. The STTn and SPTn bits and the MSTSn, EXCn, COIn, TRCn, ACKDn, and STDn bits of the IICSn register are cleared. The standby mode following exit from communications remains in effect until the following communication entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match occurs or an extension code is received after the start condition. Condition for clearing (LRELn bit = 0) Condition for setting (LRELn bit = 1) * Automatically cleared after execution * Set by instruction * After reset WRELn Note 2 Wait state cancellation control 0 Wait state not canceled 1 Wait state canceled. This setting is automatically cleared after wait state is canceled. Condition for clearing (WRELn bit = 0) Condition for setting (WRELn bit = 1) * Automatically cleared after execution * After reset * Set by instruction Notes 1. The IICSn register, IICFn.STCFn and IICFn.IICBSYn bits, and IICCLn.CLDn and IICCLn.DADn bits are reset. 2. This flag's signal is invalid when the IICEn bit = 0. Caution If the I2Cn operation is enabled (IICEn bit = 1) when the SCL0n line is high level and the SDA0n line is low level, the start condition is detected immediately. To avoid this, after enabling the I2Cn operation, immediately set the LRELn bit to 1 with a bit manipulation instruction. Remark The LRELn and WRELn bits are 0 when read after the data has been set. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 774 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2/4) Note SPIEn Enabling/disabling generation of interrupt request when stop condition is detected 0 Disabled 1 Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) * Cleared by instruction * After reset * Set by instruction Note WTIMn 0 Control of wait state and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and the wait state is set. Slave mode: After input of eight clocks, the clock is set to low level and the wait state is set for the master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and the wait state is set. Slave mode: After input of nine clocks, the clock is set to low level and the wait state is set for the master device. During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This bit setting becomes valid when the address transfer is completed. In master mode, a wait state is inserted at the falling edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait state is inserted at the falling edge of the ninth clock after ACK is generated. The slave device that has received an extension code, however, enters a wait state at the falling edge of the eighth clock. Condition for clearing (WTIMn bit = 0) Condition for setting (WTIMn bit = 1) * Cleared by instruction * Set by instruction * After reset Note ACKEn Acknowledgment control 0 Acknowledgment disabled. 1 Acknowledgment enabled. During the ninth clock period, the SDA0n line is set to low level. The ACKEn bit setting is invalid for address reception by the slave device. In this case, ACK is generated when the addresses match. However, the ACKEn bit setting is valid for reception of the extension code. Set the ACKEn bit in the system that receives the extension code. Condition for clearing (ACKEn bit = 0) Condition for setting (ACKEn bit = 1) * Cleared by instruction * Set by instruction * After reset Note This flag's signal is invalid when the IICEn bit = 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 775 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3/4) STTn Start condition trigger 0 Start condition is not generated. 1 When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level. During communication with a third party: If the communication reservation function is enabled (IICFn.IICRSVn bit = 0) * This trigger functions as a start condition reserve flag. When set to 1, it releases the bus and then automatically generates a start condition. If the communication reservation function is disabled (IICRSVn = 1) * The IICFn.STCFn bit is set to 1 and information set (1) to the STTn bit is cleared. This trigger does not generate a start condition. In the wait state (when master device): A restart condition is generated after the wait state is released. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been set to 0 and the slave has been notified of final reception. For master transmission: A start condition may not be generated normally during the ACK period. Set to 1 during the wait period that follows output of the ninth clock. For slave: Even when the communication reservation function is disabled (IICRSVn bit = 1), the communication reservation status is entered. * Setting to 1 at the same time as the SPTn bit is prohibited. * When the STTn bit is set to 1, setting the STTn bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (STTn bit = 0) Condition for setting (STTn bit = 1) * When the STTn bit is set to 1 in the communication * Set by instruction reservation disabled status * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When the LRELn bit = 1 (communication save) * When the IICEn bit = 0 (operation stop) * After reset Remark The STTn bit is 0 if it is read immediately after data setting. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 776 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (4/4) SPTn 0 1 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed from low level to high level and a stop condition is generated. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period after the slave has been notified of final reception. For master transmission: A stop condition may not be generated normally during the ACK reception period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as the STTn bit. * The SPTn bit can be set to 1 only when in master mode Note . * When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the SPTn bit should be set to 1 during the wait period that follows output of the ninth clock. * When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (SPTn bit = 0) Condition for setting (SPTn bit = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * Cleared when the LRELn bit = 1 (communication save) * When the IICEn bit = 0 (operation stop) * After reset Note Set the SPTn bit to 1 only in master mode. However, to perform a master operation before detecting the first stop condition after operation has been enabled when the IICRSVn bit is 0, the SPTn bit must be set to 1 and a stop condition must be set. For details, see 18.15 Cautions. Caution If the WRELn bit is set to 1 during the ninth clock and the wait state is canceled when the TRCn bit is 1, the TRCn bit is cleared to 0 and the SDA0n line is set to high impedance. Remark The SPTn bit is 0 if it is read immediately after data setting. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 777 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2) IIC status registers 0, 1 (IICS0, IICS1) The IICSn registers indicate the status of I2C0n. These registers are read-only, in 8-bit or 1-bit units. However, the IICSn registers can only be read when the IICCn.STTn bit is 1 or during the wait period. Reset sets these registers to 00H. Caution Accessing the IICSn registers is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates on the subclock and the main clock oscillation is stopped * When the CPU operates on the internal oscillation clock (1/3) After reset: 00H IICSn R Address: IICS0 FFFFFD86H, IICS1 FFFFFD96H <7> <6> <5> <4> <3> <2> <1> <0> MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn MSTSn Master device status 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTSn bit = 0) Condition for setting (MSTSn bit = 1) * When a stop condition is detected * When the ALDn bit = 1 (arbitration loss) * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When a start condition is generated ALDn Arbitration loss detection 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". The MSTSn bit is cleared to 0. Condition for clearing (ALDn bit = 0) Condition for setting (ALDn bit = 1) * Automatically cleared after the IICSn register is Note read * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When the arbitration result is a "loss". EXCn Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXCn bit = 0) Condition for setting (EXCn bit = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When the higher four bits of the received address data are either "0000" or "1111" (set at the rising edge of the eighth clock). Note This bit is also cleared when a bit manipulation instruction is executed for another bit in the IICSn register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 778 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2/3) COIn Matching address detection 0 Addresses do not match. 1 Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) * When a start condition is detected * When the received address matches the local * When a stop condition is detected address (SVAn register) (set at the rising edge of the * Cleared by LRELn bit = 1 (communication save) eighth clock). * When the IICEn bit changes from 1 to 0 (operation stop) * After reset TRCn 0 Transmit/receive status detection Receive status (other than transmit status). The SDA0n line is set to high impedance. Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at 1 the falling edge of the first byte's ninth clock). Condition for clearing (TRCn bit = 0) Condition for setting (TRCn bit = 1) * When a stop condition is detected Master * Cleared by LRELn bit = 1 (communication save) * When a start condition is generated * When the IICEn bit changes from 1 to 0 (operation * When "0" is output to the first byte's LSB (transfer stop) direction specification bit) * Cleared by IICCn.WRELn bit = 1 Note * When the ALDn bit changes from 0 to 1 (arbitration loss) Slave * When "1" is input by the first byte's LSB (transfer direction specification bit) * After reset Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication ACKDn ACK detection 0 ACK was not detected. 1 ACK was detected. Condition for clearing (ACKDn bit = 0) Condition for setting (ACKD bit = 1) * When a stop condition is detected * After the SDA0n bit is set to low level at the rising edge of the SCL0n pin's ninth clock * At the rising edge of the next byte's first clock * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is set to 1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 779 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3/3) STDn Start condition detection 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset SPDn Stop condition detection 0 Stop condition was not detected. 1 Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPDn bit = 0) Condition for setting (SPDn bit = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When the IICEn bit changes from 1 to 0 (operation stop) * After reset R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 780 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS (3) IIC flag registers 0, 1 (IICF0, IICF1) The IICFn registers set the I2C0n operation mode and indicate the I2C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only. IICRSVn enables/disables the communication reservation function (see 18.14 Communication Reservation). The initial value of the IICBSYn bit is set by using the STCENn bit (see 18.15 Cautions). The IICRSVn and STCENn bits can be written only when operation of I2C0n is disabled (IICCn.IICEn bit = 0). After operation is enabled, IICFn can be read. Reset sets these registers to 00H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 781 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H After reset: 00H IICFn R/W Note Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH <7> <6> 5 4 3 2 <1> <0> STCFn IICBSYn 0 0 0 0 STCENn IICRSVn STCFn STTn bit clear 0 Start condition issued 1 Start condition cannot be issued, STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) * Cleared by IICCn.STTn bit = 1 * When the IICCn.IICEn bit = 0 * After reset * When start condition is not issued and STTn flag is cleared to 0 when communication reservation is disabled (IICRSVn bit = 1). 2 IICBSYn I C0n bus status 0 Bus release status (default communication status when STCENn bit = 1) 1 Bus communication status (default communication status when STCENn bit = 0) Condition for clearing (IICBSYn bit = 0) Condition for setting (IICBSYn bit = 1) * When stop condition is detected * When the IICEn bit = 0 * After reset * When start condition is detected * By setting the IICEn bit when the STCENn bit = 0 STCENn Initial start enable trigger 0 Start conditions cannot be generated until a stop condition is detected following operation enable (IICEn bit = 1). 1 Start conditions can be generated even if a stop condition is not detected following operation enable (IICEn bit = 1). Condition for clearing (STCENn bit = 0) Condition for setting (STCENn bit = 1) * When start condition is detected * After reset * Setting by instruction IICRSVn Communication reservation function disable bit 0 Communication reservation enabled 1 Communication reservation disabled Condition for clearing (IICRSVn bit = 0) Condition for setting (IICRSVn bit = 1) * Clearing by instruction * After reset * Setting by instruction Note Bits 6 and 7 are read-only bits. Cautions 1. Write the STCENn bit only when operation is stopped (IICEn bit = 0). 2. When the STCENn bit = 1, the bus released status (IICBSYn bit = 0) is recognized regardless of the actual bus status immediately after the I2Cn bus operation is enabled. Therefore, to issue the first start condition (STTn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 3. Write the IICRSVn bit only when operation is stopped (IICEn bit = 0). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 782 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (4) IIC clock select registers 0, 1 (IICCL0, IICCL1) The IICCLn registers set the transfer clock for I2C0n. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn registers when the IICCn.IICEn bit = 0. The SMCn, CLn1, and CLn0 bits are set by combining the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 18.4 (6) I2C0n transfer clock setting method) (m = 0, 1). Reset sets these registers to 00H. Note Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H 7 6 <5> <4> 3 2 1 0 0 0 CLDn DADn SMCn DFCn CLn1 CLn0 After reset: 00H IICCLn R/W CLDn Detection of SCL0n pin level (valid only when IICCn.IICEn bit = 1) 0 The SCL0n pin was detected at low level. 1 The SCL0n pin was detected at high level. Condition for clearing (CLDn bit = 0) Condition for setting (CLDn bit = 1) * When the SCL0n pin is at low level * When the IICEn bit = 0 (operation stop) * After reset * When the SCL0n pin is at high level DADn Detection of SDA0n pin level (valid only when IICEn bit = 1) 0 The SDA0n pin was detected at low level. 1 The SDA0n pin was detected at high level. Condition for clearing (DADn bit = 0) Condition for setting (DAD0n bit = 1) * When the SDA0n pin is at low level * When the IICEn bit = 0 (operation stop) * After reset * When the SDA0n pin is at high level SMCn Operation mode switching 0 Operation in standard mode. 1 Operation in high-speed mode. DFCn Digital filter operation control 0 Digital filter off. 1 Digital filter on. The digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary according to the DFCn bit setting (on/off). The digital filter is used to eliminate noise in high-speed mode. Note Bits 4 and 5 are read-only bits. Caution Be sure to clear bits 7 and 6 to "0". Remark When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 783 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (5) IIC function expansion registers 0, 1 (IICX0, IICX1) The IICXn registers set I2C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 18.4 (6) I2C0n transfer clock setting method) (m = 0, 1). Set the IICXn registers when the IICCn.IICEn bit = 0. Reset sets these registers to 00H. After reset: 00H R/W Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H < > IICXn 0 0 0 0 0 0 0 CLXn (6) I2C0n transfer clock setting method The I2C0n transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 24, 48, 72, 96, 108, 120, 144, 172, 192, 240, 264, 344, 352, 396, 440, 516, 688, 860 (see Table 18-3 Clock Settings). T: 1/fXX tR: SCL0n pin rise time tF: SCL0n pin fall time For example, the I2C0n transfer clock frequency (fSCL) when fXX = 19.2 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(198 x 52 ns + 200 ns + 50 ns) 94.7 kHz m x T + tR + tF tR m/2 x T tF m/2 x T SCL0n SCL0n inversion SCL0n inversion SCL0n inversion The clock to be selected can be set by combining of the SMCn, CLn1, and CLn0 bits of the IICCLn register, the CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (n = 0, 1, m = 0, 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 784 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Table 18-3. Clock Settings IICXn IICCLn Selection Clock CLXn SMCn CLn1 CLn0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 Other than above 0 1 1 X 1 X Transfer Clock Settable Main Clock Frequency (fXX) Range Transfer Speed Operating Mode fxx/6 (OCKSm = 11H) fxx/264 24.00 MHz fxx 25.14 MHz 90.91 kHz to 95.23 kHz Standard fxx/8 (OCKSm= 12H) fxx/352 24.00 MHz fxx 33.52 MHz 68.18 kHz to 95.23 kHz fxx/10 (OCKSm = 13H) fxx/440 30.00 MHz fxx 41.90 MHz mode (SMCn = 0) 68.18 kHz to 95.23 kHz fxx/4 (OCKSm = 10H) fxx/344 24.00 MHz fxx 33.52 MHz 48.72 kHz to 97.44 kHz fxx/6 (OCKSm= 11H) fxx/516 25.14 MHz fxx 48.00 MHz 48.72 kHz to 93.02 kHz fxx/8 (OCKSm = 12H) fxx/688 33.52 MHz fxx 48.00 MHz 48.72 kHz to 69.77 kHz fxx/10 (OCKSm = 13H) fxx/860 41.90 MHz fxx 48.00 MHz 48.72 kHz to 55.81 kHz fxx/4 (OCKSm = 10H) fxx/264 24.00 MHz fxx 25.60 MHz 90.91 kHz to 96.97 kHz fxx/6 (OCKSm = 11H) fxx/396 38.40 MHz 96.97 kHz fxx/4 (OCKSm = 10H) fxx/96 24.00 MHz fxx 33.52 MHz 250.00 kHz to 349.17 kHz High-speed fxx/6 (OCKSm = 11H) fxx/144 24.00 MHz fxx 48.00 MHz 166.67 kHz to 333.33 kHz fxx/8 (OCKSm = 12H) fxx/192 32.00 MHz fxx 48.00 MHz mode (SMCn = 1) 166.67 kHz to 250.00 kHz fxx/10 (OCKSm = 13H) fxx/240 40.00 MHz fxx 48.00 MHz 166.67 kHz to 200.00 kHz fxx/4 (OCKSm = 10H) fxx/72 24.00 MHz fxx 25.60 MHz 333.33 kHz to 355.56 kHz fxx/6 (OCKSm= 11H) fxx/108 38.40 MHz fxx/6 (OCKSm = 11H) fxx/72 24.00 MHz fxx 25.14 MHz 333.33 kHz to 349.17 kHz fxx/8 (OCKSm = 12H) fxx/96 32.00 MHz fxx 33.52 MHz 333.33 kHz to 349.17 kHz fxx/10 (OCKSm = 13H) fxx/120 40.00 MHz fxx 41.90 MHz 333.33 kHz to 349.17 kHz Setting prohibited - 355.56 kHz - - - Remarks 1. m = 0, 1 2. x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 785 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm registers control the I2C0n division clock (m = 0, 1). These registers control the I2C00 division clock via the OCKS0 register and the I2C01 division clocks via the OCKS1 register. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H OCKSm 0 R/W Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H 0 0 OCKSENm OCKSTHm 0 OCKSm1 OCKSm0 (m = 0, 1) Operation setting of I2C division clock OCKSENm 0 Stops I2C division clock operation 1 Enables I2C division clock operation Selection of I2C division clock OCKSTHm OCKSm1 OCKSm0 0 0 0 fXX/4 0 0 1 fXX/6 0 1 0 fXX/8 0 1 1 fXX/10 1 0 0 fXX/2 (8) IIC shift registers 0, 1 (IIC0, IIC1) The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. These registers can be read or written in 8-bit units, but data should not be written to the IICn registers during a data transfer. Access (read/write) the IICn registers only during the wait period. Accessing these registers in communication states other than the wait period is prohibited. However, for the master device, the IICn registers can be written once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1. A wait state is released by writing the IICn registers during the wait period, and data transfer is started. Reset sets these registers to 00H. After reset: 00H R/W 7 Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H 6 5 4 3 2 1 0 IICn R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 786 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (9) Slave address registers 0, 1 (SVA0, SVA1) The SVAn registers hold the I2C bus's slave address. These registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting these registers is prohibited when the IICSn.STDn bit = 1 (start condition detection). Reset sets these registers to 00H. After reset: 00H R/W 7 SVAn R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Address: SVA0 FFFFFD83H, SVA1 FFFFFD93H, SVA2 FFFFFDA3H 6 5 4 3 2 1 0 0 Page 787 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.5 I2C Bus Mode Functions 18.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows. SCL0n .................This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0n ................This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 18-6. Pin Configuration Diagram VDD Slave device Master device SCL0n SCL0n Clock output (Clock output) VDD (Clock input) Clock input SDA0n Data output Data input R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 SDA0n Data output Data input Page 788 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6 I2C Bus Definitions and Control Methods 2 2 The following section describes the I C bus's serial data communication format and the signals used by the I C bus. The transfer timing for the "start condition", "address", "transfer direction specification", "data", and "stop condition" generated on the I2C bus's serial data bus is shown below. 2 Figure 18-7. I C Bus Serial Data Transfer Timing 1 to 7 SCL0n 8 9 1 to 8 9 1 to 8 9 R/W ACK Data ACK Data ACK SDA0n Start Address condition Stop condition The master device generates the start condition, slave address, and stop condition. ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-bit data). The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin's low-level period can be extended and a wait state can be inserted. 18.6.1 Start condition A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level. The start condition for the SCL0n and SDA0n pins is a signal that the master device outputs to the slave device when starting a serial transfer. The slave device can detect the start condition. Figure 18-8. Start Condition H SCL0n SDA0n A start condition is output when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn bit = 1). When a start condition is detected, the IICSn.STDn bit is set (1). Caution When the IICCn.IICEn bit of the V850ES/JC3-H and V850ES/JE3-H is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 789 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output so that the master device can select one of the slave devices that are connected to the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices detect via hardware the start condition and check whether or not the 7-bit address data matches the data values stored in the SVAn register. If the address data matches the values of the SVAn register, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 18-9. Address SCL0n 1 2 3 4 5 6 7 8 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W Address 9 Note INTIICn Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. An address is output when the slave address and the transfer direction described in 18.6.3 Transfer direction specification are written together to the IICn registers as eight bits of data. Received addresses are written to the IICn register. The slave address is assigned to the higher 7 bits of the IICn register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 790 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit of data that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 18-10. Transfer Direction Specification SCL0n 1 2 3 4 5 6 7 8 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W 9 Transfer direction specification Note INTIICn Note The INTIICn signal is generated if a local address or extension code is received during slave device operation. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 791 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed using the IICSn.ACKDn bit. When the master device is the receiving device, after receiving the final data, it does not return ACK and generates a stop condition. When the slave device is the receiving device and does not return ACK, the master device generates either a stop condition or a restart condition, and then stops the current transmission. Failure to return ACK may be caused by the following factors. (a) Reception was not performed normally. (b) The final data was received. (c) The receiving device (slave) does not exist at the specified address. When the receiving device sets the SDA0n line to low level during the ninth clock, ACK is generated (normal reception). When the IICCn.ACKEn bit is set to 1, automatic ACK generation is enabled. Transmission of the eighth bit following the 7 address data bits causes the IICSn.TRCn bit to be set. Normally, set the ACKEn bit to 1 for reception (TRCn bit = 0). When the slave device is receiving (when TRCn bit = 0), if the slave device cannot receive data or does not need the subsequent data, clear the ACKEn bit to 0 to indicate to the master that no more data can be received. Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed, clear the ACKEn bit to 0 to prevent ACK from being generated. This notifies the slave device (transmitting device) of the end of the data transmission (transmission stopped). Figure 18-11. ACK SCL0n 1 2 3 4 5 6 7 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 8 9 R/W ACK When the local address is received, ACK is automatically generated regardless of the value of the ACKEn bit. No ACK is generated if an address other than the local address is received (NACK). When receiving the extension code, set the ACKEn bit to 1 in advance to generate ACK. The ACK generation method during data reception is based on the wait timing setting, as described by the following. * When 8-clock wait is selected (IICCn.WTIMn bit = 0): ACK is generated in synchronization with the falling edge of the SCL0n pin's eighth clock if the ACKEn bit is set to 1 before wait state cancellation. * When 9-clock wait is selected (IICCn.WTIMn bit = 1): ACK is generated if the ACKEn bit is set to 1 in advance. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 792 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition. A stop condition is generated when serial transfer from the master device to the slave device has been completed. When the V850ES/JC3-H or V850ES/JE3-H is used as the slave device, it can detect the stop condition. Figure 18-12. Stop Condition H SCL0n SDA0n A stop condition is generated when the IICCn.SPTn bit is set to 1. When the stop condition is detected, the IICSn.SPDn bit is set to 1 and the interrupt request signal (INTIICn) is generated when the IICCn.SPIEn bit is set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 793 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 18-13. Wait State (1/2) (a) When master device is in a nine-clock wait state and slave device is in an eight-clock wait state (master: transmission, slave: reception, and IICCn.ACKEn bit = 1) Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IICn data write (cancel wait state) IICn 6 SCL0n 7 8 1 9 2 3 Slave Wait after output of eighth clock. FFH is written to IICn register or IICCn.WRELn bit is set to 1. IICn SCL0n ACKEn H Transfer lines Wait state from master Wait state from slave SCL0n 6 7 8 SDA0n D2 D1 D0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 9 ACK 1 2 3 D7 D6 D5 Page 794 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-13. Wait State (2/2) (b) When master and slave devices are both in a nine-clock wait state (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait after output of ninth clock. IICn data write (cancel wait state) Master IICn 6 SCL0n 7 8 1 9 2 3 Slave FFH is written to IICn register or WRELn bit is set to 1. IICn SCL0n ACKEn H Transfer lines Wait state Wait state from master/ from slave slave SCL0n 6 7 8 9 SDA0n D2 D1 D0 ACK 1 D7 2 3 D6 D5 Generate according to previously set ACKEn bit value A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit. Normally, the receiving side cancels the wait state when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register and the transmitting side cancels the wait state when data is written to the IICn register. The master device can also cancel the wait state via either of the following methods. * By setting the IICCn.STTn bit to 1 * By setting the IICCn.SPTn bit to 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 795 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.6.7 Wait state cancellation method In the case of I2C0n, a wait state can be canceled normally in the following ways. * By writing data to the IICn register * By setting the IICCn.WRELn bit to 1 (wait state cancellation) * By setting the IICCn.STTn bit to 1 (start condition generation) * By setting the IICCn.SPTn bit to 1 (stop condition generation) If any of these wait state cancellation actions is performed, I2C0n will cancel the wait state and restart communication. When canceling the wait state and sending data (including address), write data to the IICn register. To receive data after canceling the wait state, or to complete data transmission, set the WRELn bit to 1. To generate a restart condition after canceling the wait state, set the STTn bit to 1. To generate a stop condition after canceling the wait state, set the SPTn bit to 1. Execute cancellation only once for each wait state. For example, if data is written to the IICn register following wait state cancellation by setting the WRELn bit to 1, a conflict between the SDA0n line change timing and IICn register write timing may result in the data output to SDA0n being an incorrect value. Even in other operations, if communication is stopped halfway, clearing the IICCn.IICEn bit to 0 will stop communication, enabling the wait state to be cancelled. If the I2C bus dead-locks due to noise, etc., setting the IICCn.LRELn bit to 1 causes the communication operation to be exited, enabling the wait state to be cancelled. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 796 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.7 I2C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. 18.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 5 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B S3: IICSn register = 1000X000B (WTIMn bit = 1) S4: IICSn register = 1000XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X100B S3: IICSn register = 1000XX00B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 797 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 STTn bit = 1 SPTn bit = 1 ACK S2 ST AD6 to AD0 R/W ACK S3 D7 to D0 S4 ACK S5 SP S6 7 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B (WTIMn bit = 0) S4: IICSn register = 1000X110B (WTIMn bit = 0) S5: IICSn register = 1000X000B (WTIMn bit = 1) S6: IICSn register = 1000XX00B 7: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 STTn bit = 1 SPTn bit = 1 ACK ST AD6 to AD0 S2 R/W ACK D7 to D0 S3 ACK SP S4 5 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B S3: IICSn register = 1000X110B S4: IICSn register = 1000XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 798 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 5 S1: IICSn register = 1010X110B S2: IICSn register = 1010X000B S3: IICSn register = 1010X000B (WTIMn bit = 1) S4: IICSn register = 1010XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 1010X110B S2: IICSn register = 1010X100B S3: IICSn register = 1010XX00B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 799 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X100B S3: IICSn register = 0001XX00B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 800 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 S2 R/W ACK D7 to D0 S3 ACK SP S4 5 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B S3: IICSn register = 0001X110B S4: IICSn register = 0001XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 801 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 S2 R/W ACK S3 D7 to D0 S4 ACK SP S5 6 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B S3: IICSn register = 0010X010B S4: IICSn register = 0010X110B S5: IICSn register = 0010XX00B 6: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 802 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP 4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 S2 R/W ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B S3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 803 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK D7 to D0 S3 ACK SP S4 5 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010X100B S4: IICSn register = 0010XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 804 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, address match) ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK ST AD6 to AD0 S3 R/W ACK D7 to D0 S4 ACK SP S5 6 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B S4: IICSn register = 0001X110B S5: IICSn register = 0001XX00B 6: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 805 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK ST AD6 to AD0 S3 R/W ACK S4 D7 to D0 S5 ACK SP S6 7 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B S4: IICSn register = 0010X010B S5: IICSn register = 0010X110B S6: IICSn register = 0010XX00B 7: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 806 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP 4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK ST AD6 to AD0 S3 R/W ACK D7 to D0 S4 ACK SP 5 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B S4: IICSn register = 00000X10B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 807 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICSn register = 00000001B Remarks : Generated only when SPIEn bit = 1 18.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0101X110B (Example: When IICSn.ALDn bit is read during interrupt servicing) S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 0101X110B (Example: When ALDn bit is read during interrupt servicing) S2: IICSn register = 0001X100B S3: IICSn register = 0001XX00B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 808 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK D7 to D0 S3 ACK SP S4 5 S1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) S2: IICSn register = 0010X110B S3: IICSn register = 0010X100B S4: IICSn register = 0010XX00B 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 809 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 2 S1 S1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing) 2: IICSn register = 00000001B Remark S: : Always generated Generated only when IICCn.SPIEn bit = 1 (2) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK S1 S1: D7 to D0 ACK SP 2 IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) IICCn.LRELn bit is set to 1 by software 2: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 810 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 ACK SP 3 S2 S1: IICSn register = 10001110B S2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remark S: : Always generated Generated only when SPIEn bit = 1 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 3 S1: IICSn register = 10001110B S2: IICSn register = 01000100B (Example: When ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remark S: : Always generated Generated only when SPIEn bit = 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 811 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK SP 3 S2 S1: IICSn register = 1000X110B S2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 <2> Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 S1 R/W ACK D7 to D0 S2 ACK SP 3 S1: IICSn register = 1000X110B S2: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) IICCn.LRELn bit is set to 1 by software 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 812 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (5) When arbitration loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn S1 SP 2 S1: IICSn register = 1000X110B 2: IICSn register = 01000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 813 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 D7 to D0 S3 ACK D7 to D0 ACK SP 5 S4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B (WTIMn bit = 0) S4: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 IICCn.STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B S3: IICSn register = 01000100B (Example: When ALDn bit is read during interrupt servicing) 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 814 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 SP 4 S3 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B 4: IICSn register = 01000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK SP S2 3 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B 3: IICSn register = 01000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 815 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 D7 to D0 S3 ACK D7 to D0 ACK SP 5 S4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B (WTIMn bit = 0) S4: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) 5: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care <2> When WTIMn bit = 1 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B S3: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) 4: IICSn register = 00000001B Remark S: Always generated : Generated only when SPIEn bit = 1 X: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 816 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 18-4. INTIICn Generation Timing and Wait Control WTIMn Bit During Slave Device Operation Address 0 9 1 9 Notes 1. Notes 1, 2 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 The slave device's INTIICn signal and wait period occur at the falling edge of the ninth clock only when there is a match with the address set to the SVAn register. At this point, the ACK is generated regardless of the value set to the IICCn.ACKEn bit. For a slave device that has received an extension code, the INTIICn signal occurs at the falling edge of the eighth clock. When the address does not match after restart, the INTIICn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. If the received address does not match the contents of the SVAn register and an extension code is not received, neither the INTIICn signal nor a wait occurs. Remarks The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined according to the conditions described in Notes 1 and 2 above, regardless of the WTIMn bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 817 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting the IICCn.WRELn bit to 1 * By writing to the IICn register * By start condition setting (IICCn.STTn bit = 1)Note * By stop condition setting (IICCn.SPTn bit = 1)Note Note Master only When an 8-clock wait has been selected (WTIMn bit = 0), whether or not ACK has been generated must be determined prior to wait cancellation. (5) Stop condition detection The INTIICn signal is generated when a stop condition is detected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 818 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.9 Address Match Detection Method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received. 18.10 Error Detection In I2C bus mode, the status of the serial data bus pin (SDA0n) during data transmission is captured by the IICn register of the transmitting device, so the data of the IICn register prior to transmission can be compared with the transmitted IICn data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. 18.11 Extension Code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock. The local address stored in the SVAn register is not affected. (2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXCn bit = 1 * Seven bits of data match: IICSn.COIn bit = 1 (3) Since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set the IICCn.LRELn bit to 1 and the CPU will enter the next communication wait state. Table 18-5. Extension Code Bit Definitions Slave Address R/W Bit Description 0000 000 0 General call address 1111 0xx 0 10-bit slave address specification (when the address is authorized) 1111 0xx 1 10-bit slave address specification (after the address match, the read command is issued) Remark For the expansion codes other than the above, see I2C bus specifications issued by NXP. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 819 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the timing at which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which releases the bus. Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software. For details of interrupt request timing, see 18.7 I2C Interrupt Request Signals (INTIICn). Figure 18-14. Arbitration Timing Example Master 1 SCL0n SDA0n Hi-Z Hi-Z Master 1 loses arbitration Master 2 SCL0n SDA0n Transfer lines SCL0n SDA0n R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 820 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Table 18-6. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Transmitting address transmission Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data ACK transfer period after data reception When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when IICCn.SPIEn bit = 1) When SDA0n pin is low level while attempting to generate At falling edge of eighth or ninth clock following byte transfer Note 1 restart condition When stop condition is detected while attempting to Note 2 When stop condition is generated (when IICCn.SPIEn bit = 1) generate restart condition When DSA0n pin is low level while attempting to generate Note 1 At falling edge of eighth or ninth clock following byte transfer stop condition When SCL0n pin is low level while attempting to generate restart condition Notes 1. When the IICCn.WTIMn bit = 1, an INTIICn signal occurs at the falling edge of the ninth clock. When the WTIMn bit = 0 and the extension code's slave address is received, an INTIICn signal occurs at the falling edge of the eighth clock. 2. When there is a possibility that arbitration will occur, set the SPIEn bit to 1 for master device operation. 18.13 Wakeup Function The makeup function is a function that generates an interrupt request signal (INTIICn) when a local address or extension code has been received by using the slave function of the I2C bus. This function makes processing more efficient by preventing unnecessary INTIICn signals from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which generated the start condition) to a slave device. However, when a stop condition is detected, the IICCn.SPIEn bit is set regardless of the wakeup function, and this determines whether INTIICn signal is enabled or disabled. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 821 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.14 Communication Reservation 18.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICCn.LRELn bit was set to 1). If the IICCn.STTn bit is set to 1 while the bus is not being used, a start condition is automatically generated and a wait status is set after the bus is released (after the stop condition is detected). When the bus release is detected (when the stop condition is detected), writing to the IICn register causes master address transfer to start. At this point, the IICCn.SPIEn bit should be set to 1. When STTn has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. If the bus has been released .............................................A start condition is generated If the bus has not been released (standby mode)..............Communication reservation To detect which operation mode has been determined, set the STTn bit to 1, wait for the wait period, then check the IICSn.MSTSn bit. The wait periods, which should be set via software, are listed in Table 18-7. These wait periods can be set by the SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 822 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Table 18-7. Wait Periods Clock Selection CLXn SMCn CLn1 CLn0 fXX/6 (OCKSm = 11H) 0 0 0 0 156 clocks fXX/8 (OCKSm = 12H) 0 0 0 0 208 clocks fXX/10 (OCKSm = 13H) 0 0 0 0 260 clocks fXX/4 (OCKSm = 10H) 0 0 0 1 188 clocks fXX/6 (OCKSm = 11H) 0 0 0 1 282 clocks fXX/8 (OCKSm = 12H) 0 0 0 1 376 clocks fXX/10 (OCKSm = 13H) 0 0 0 1 470 clocks fXX/4 (OCKSm = 10H) 0 0 1 1 148 clocks fXX/6 (OCKSm = 11H) 0 0 1 1 222 clocks fXX/4 (OCKSm = 10H) 0 1 0 x 64 clocks fXX/6 (OCKSm = 11H) 0 1 0 x 96 clocks fXX/8 (OCKSm = 12H) 0 1 0 x 128 clocks fXX/10 (OCKSm = 13H) 0 1 0 x 160 clocks fXX/4 (OCKSm = 10H) 0 1 1 1 52 clocks fXX/6 (OCKSm = 11H) 0 1 1 1 78 clocks fXX/6 (OCKSm = 11H) 1 1 0 x 60 clocks fXX/8 (OCKSm = 12H) 1 1 0 x 80 clocks fXX/10 (OCKSm = 13H) 1 1 0 x 100 clocks Remarks1. 2. Wait Period m = 0, 1 x = Don't care The communication reservation timing is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 823 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-15. Communication Reservation Timing Program processing Hardware processing SCL0n 1 2 3 4 STTn =1 Write to IICn Set SPDn and INTIICn Communication reservation 5 6 7 8 9 Set STDn 1 2 3 4 5 6 SDA0n Generated by master with bus access Remark STTn: Bit of IICCn register STDn: Bit of IICSn register SPDn: Bit of IICSn register Communication reservations are accepted via the following timing. After the IICSn.STDn bit is set to 1, a communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected. Figure 18-16. Timing for Accepting Communication Reservations SCL0n SDA0n STDn SPDn Standby mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 824 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H The communication reservation flowchart is illustrated below. Figure 18-17. Communication Reservation Flowchart DI SET1 STTn Define communication reservation Wait Sets STTn bit (communication reservation). Defines that communication reservation is in effect (defines and sets user flag to any RAM). Secures wait period set by software (see Table 18-6). Note (Communication reservation) Yes MSTSn bit = 0? Confirmation of communication reservation No (Generate start condition) Cancel communication reservation IICn register xxH Clears user flag. IICn register write operation EI Note The communication reservation operation executes a write to the IICn register when a stop condition interrupt request occurs. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 825 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not being used for communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICCn.LRELn bit was set to 1) (n = 0, 1) To confirm whether the start condition was generated or the request was rejected, check the IICFn.STCFn flag. The time shown in Table 18-8 is required until the STCFn flag is set after setting the STTn bit to 1. Therefore, secure the time by software. Table 18-8. Wait Periods OCKSENm OCKSm1 OCKSm0 CLn1 CLn0 Wait Period 1 0 0 0 x 20 clocks 1 0 1 0 x 30 clocks 1 1 0 0 x 40 clocks 1 1 1 0 x 50 clocks 0 0 0 1 0 10 clocks Remarks 1. x: don't care 2. m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 826 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.15 Cautions (1) When IICFn.STCENn bit = 0 Immediately after the I2C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition. <1> Set the IICCLn register. <2> Set the IICCn.IICEn bit. <3> Set the IICCn.SPTn bit. (2) When IICFn.STCENn bit = 1 Immediately after I2C0n operation is enabled, the bus release status (IICBSYn bit = 0) is recognized regardless of the actual bus status. To generate the first start condition (IICCn.STTn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) When the IICCn.IICEn bit of the V850ES/JC3-H and V850ES/JE3-H is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level. (4) Determine the operation clock frequency by using the IICCLn, IICXn, and OCKSm registers before enabling the operation (IICCn.IICEn bit = 1). To change the operation clock frequency, first clear the IICCn.IICEn bit to 0. (5) After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an interrupt request is generated by the detection of a stop condition. After an interrupt request has been generated, the wait status will be released by writing communication data to I2Cn, then transfer will begin. If an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait status because an interrupt request was not generated. However, it is not necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit. Remark m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 827 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.16 Communication Operations The following shows three operation procedures together with flowcharts. (1) Master operation in single master system The flowchart when using the V850ES/JC3-H and V850ES/JE3-H as the master in a single master system is shown below. This flowchart is broadly divided into initial settings and communication processing. Execute the initial settings at startup. If communication with a slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C0n bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and the clock are at a high level for a certain period (1 frame), the V850ES/JC3-H or V850ES/JE3-H takes part in communication in a bus release state. This flowchart is broadly divided into initial settings, communication waiting, and communication processing. The processing when the V850ES/JC3-H or V850ES/JE3-H loses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and includes arbitration with other masters data as well as transmission/reception with the slave. (3) Slave operation An example of when the V850ES/JC3-H or V850ES/JE3-H is used as the slave of the I2C0n bus is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for INTIICn interrupt occurrence (communication waiting). When the INTIICn interrupt occurs, the communication status is judged and its result is passed as a flag to the main processing. By checking the flags, the necessary communication processing can be performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 828 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.16.1 Master operation in single master system Figure 18-18. Master Operation in Single Master System START Initialize I2C busNote Set ports Initial settings IICXn 0XH IICCLn XXH OCKSm XXH Refer to Table 4-17 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used. Transfer clock selection SVAn XXH Local address setting IICFn 0XH Set STCENn, IICRSVn = 0 Start condition setting IICCn XXH ACKEn = WTIMn = SPIEn = 1 IICEn = 1 STCENn = 1? Yes No SPTn = 1 INTIICn interrupt occurred? Communication start preparation (stop condition generation) No Waiting for stop condition detection Yes STTn = 1 Communication start preparation (start condition generation) Write IICn Communication start (address, transfer direction specification) INTIICn interrupt occurred? No Waiting for ACK detection Yes No ACKDn = 1? Yes Communication processing TRCn = 1? No ACKEn = 1 WTIMn = 0 Yes Write IICn INTIICn interrupt occurred? Transmission start No Waiting for data transmission WRELn = 1 INTIICn interrupt occurred? Yes Yes ACKDn = 1? No Reception start No Waiting for data reception Read IICn Yes No Transfer completed? No Transfer completed? Yes Yes Restarted? Yes ACKEn = 0 WTIMn = WRELn = 1 No SPTn = 1 INTIICn interrupt occurred? No Waiting for ACK detection Yes END Note Release the I2C0n bus (SCL0n, SDA0n pins = high level) in compliance with the specifications of the communicating product. For example, when the EEPROMTM outputs a low level to the SDA0n pin, set the SCL0n pin to the output port and output clock pulses from that output port until the SDA0n pin becomes constantly high level. Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating product. 2. m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 829 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.16.2 Master operation in multimaster system Figure 18-19. Master Operation in Multimaster System (1/3) START Refer to Table 4-17 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used. Set ports IICXn 0XH IICCLn XXH OCKSm XXH Transfer clock selection SVAn XXH Local address setting IICFn 0XH Set STCENn, IICRSVn Start condition setting Initial settings IICCn XXH ACKEn = WTIMn = SPIEn = 1 IICEn = 1 Confirm bus statusNote Bus release status for a certain period Confirmation of bus status is in progress No INTIICn interrupt occurred? No STCENn = 1? Communication start preparation (stop condition generation) SPTn = 1 Yes Yes SPDn = 1? INTIICn interrupt occurred? No Yes Yes Slave operation SPDn = 1? No Waiting for stop condition detection No Yes 1 Master operation started? Communication waiting Slave operation * Waiting for slave specification from another master * Waiting for communication start request (depending on user program) No (no communication start request) Yes (communication start request issued) SPIEn = 0 INTIICn interrupt occurred? SPIEn = 1 No Waiting for communication request Yes IICRSVn = 0? No Slave operation Yes A B Communication Communication reservation enable reservation disable Note Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1) has been maintained for a certain period (1 frame, for example). When the SDA0n pin is constantly low level, determine whether to release the I2C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of the communicating product. Remark m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 830 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-19. Master Operation in Multimaster System (2/3) A Communication reservation enabled Communication start preparation (start condition generation) STTn = 1 Securing wait time by software (refer to Table 18-6) Communication processing Wait No MSTSn = 1? Yes INTIICn interrupt occurred? Yes No Wait status after stop condition detection and start condition generation by communication reservation function C EXCn = 1 or COIn =1? Yes Slave operation B Communication reservation disabled IICBSYn = 0? No Yes D Communication processing No Waiting for bus release (communication being reserved) STTn = 1 Wait STCFn = 0? Yes Communication start preparation (start condition generation) Securing wait time by software (refer to Table 18-7) No INTIICn interrupt occurred? No Waiting for bus release Yes C EXCn = 1 or COIn =1? No D R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Yes Stop condition detection Slave operation Page 831 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-19. Master Operation in Multimaster System (3/3) C Write IICn INTIICn interrupt occurred? Communication start (address, transfer direction specification) No Waiting for ACK detection Yes MSTSn = 1? No Yes No 2 ACKDn = 1? Yes Communication processing TRCn = 1? No ACKEn = 1 WTIMn = 0 Yes WTIMn = 1 WRELn = 1 Write IICn Transmission start INTIICn interrupt occurred? INTIICn interrupt occurred? No Waiting for data transmission Yes MSTSn = 1? Yes MSTSn = 1? No Waiting for data transmission No No Yes Yes ACKDn = 1? Reception start 2 2 Read IICn No Transfer completed? No Yes Yes No WTIMn = WRELn = 1 ACKEn = 0 Transfer completed? Yes INTIICn interrupt occurred? Restarted? No No Waiting for ACK detection Yes SPTn = 1 Yes MSTSn = 1? STTn = 1 END Yes No 2 Communication processing C 2 EXCn = 1 or COIn = 1? No Yes Slave operation 1 Not in communication Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating product. 2. When using the V850ES/JC3-H or V850ES/JE3-H as the master in a multimaster system, read the IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/JC3-H or V850ES/JE3-H as the slave in a multimaster system, confirm the status using the IICSn and IICFn registers for each INTIICn interrupt occurrence to determine the next processing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 832 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H 18.16.3 Slave operation The following shows the processing procedure of slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. The following description assumes that data communication does not support extension codes. Also, it is assumed that the INTIICn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. Figure 18-20. Overview of Software During Slave Operation Flag INTIICn signal Interrupt servicing Setting, etc. Main processing I2C Data Setting, etc. Therefore, the following three flags are prepared so that the data transfer processing can be performed by passing these flags to the main processing instead of the INTIICn signal. (1) Communication mode flag This flag indicates the following communication statuses. Clear mode: Data communication not in progress Communication mode: Data communication in progress (valid address detection stop condition detection, ACK from master not detected, address mismatch) (2) Ready flag This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block. The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clear processing (the address match is regarded as a request for the next data). (3) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. I2C0n starts and waits for the communication enable status. When communication is enabled, I2C0n performs transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). For transmission, the transmission operation is repeated until the master device stops returning ACK. When the master device stops returning ACK, transfer is complete. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 833 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H For reception, the required number of data is received and ACK is not returned for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. Figure 18-21. Slave Operation Flowchart (1) START Refer to Table 4-17 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used. Set ports Initial settings IICXn 0XH IICCLn XXH OCKSm XXH Transfer clock selection SVAn XXH Local address setting IICFn 0XH Start condition setting Set IICRSVn IICCn XXH ACKEn = WTIMn = 1 SPIEn = 0, IICEn = 1 No Communication mode flag = 1? Yes No Communication direction flag = 1? Yes WRELn = 1 Transmission start Communication processing Write IICn No Communication mode flag = 1? Communication mode flag = 1? No Yes Yes No Reception start Communication direction flag = 0? Communication direction flag = 1? No Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes Read IICn Clear ready flag Yes Clear ready flag ACKDn = 1? No Clear communication mode flag WRELn = 1 Remark m = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 834 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During INTIICn interrupt servicing, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated. If the address matches, the communication mode is set, the wait state is released, and operation returns from the interrupt (the ready flag is cleared). <3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I2C0n bus remains in the wait status. Remark <1> to <3> above correspond to <1> to <3> in Figure 18-22 Slave Operation Flowchart (2). Figure 18-22. Slave Operation Flowchart (2) INTIICn occurred Yes <1> Yes <2> SPDn = 1? No STDn = 1? No No <3> COIn = 1? Yes Set ready flag Communication direction flag TRCn Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 835 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 18 I2C BUS 18.17 Timing of Data Communication When using I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device. The shift operation of the IICn register is synchronized with the falling edge of the serial clock pin (SCL0n). The transmit data is transferred to the SO latch and is output (MSB first) via the SDA0n pin. Data input via the SDA0n pin is captured by the IICn register at the rising edge of the SCL0n pin. The data communication timing is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 836 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IICn address IICn IICn data Note 1 ACKDn STDn SPDn WTIMn H ACKEn H MSTSn STTn SPTn L WRELn L INTIICn TRCn Transmit Transfer lines 1 SCL0n 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n 8 9 1 2 3 4 W ACK D7 D6 D5 D4 Start condition Processing by slave device IICn FFH Note 2 IICn ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L Note 2 WRELn INTIICn TRCn L Receive Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 837 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn data Note 1 IICn IICn data Note 1 ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn H STTn L SPTn L WRELn L INTIICn TRCn H Transmit Transfer lines SCL0n 8 9 1 2 3 4 5 6 7 8 9 SDA0n D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 D7 D6 D5 Processing by slave device IICn FFH Note 2 IICn IICn FFH Note 2 ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn L STTn L SPTn L Note 2 WRELn Note 2 INTIICn TRCn L Receive Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 838 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IICn data Note 1 IICn IICn address ACKDn STDn SPDn WTIMn H ACKEn H MSTSn STTn SPTn WRELn L INTIICn (when SPIEn = 1) TRCn Transmit Transfer lines SCL0n 1 2 3 4 5 6 7 8 9 SDA0n D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 AD6 AD5 Stop condition Start condition Processing by slave device IICn FFH Note2 IICn IICn FFH Note2 ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L Note 2 WRELn Note 2 INTIICn (when SPIEn = 1) TRCn L Receive Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 839 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3) (a) Start condition ~ address Processing by master device IICn address IICn IICn FFH Note 1 ACKDn STDn SPDn WTIMn L ACKEn H MSTSn STTn L SPTn Note 1 WRELn INTIICn TRCn Transmit Receive Transfer lines 1 SCL0n 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n 8 9 R ACK 1 D7 2 3 4 5 6 D6 D5 D4 D3 D2 Processing by slave device IICn data Note 2 IICn ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L WRELn L INTIICn TRCn Receive Transmit Notes 1. To cancel the master wait state, write FFH to IICn or set WRELn. 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 840 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3) (b) Data Processing by master device IICn FFH Note 1 IICn IICn FFH Note 1 ACKDn STDn L SPDn L WTIMn L ACKEn H MSTSn H STTn L SPTn L WRELn Note 1 Note 1 INTIICn TRCn Receive L Transfer lines SCL0n 8 9 SDA0n D0 ACK 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK 1 2 3 D7 D6 D5 Processing by slave device IICn data Note 2 IICn IICn data Note 2 ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn L STTn L SPTn L WRELn L INTIICn TRCn H Transmit Notes 1. To cancel the master wait state, write FFH to IICn or set WRELn. 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 841 of 1442 CHAPTER 18 I2C BUS V850ES/JC3-H, V850ES/JE3-H Figure 18-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3) (c) Stop condition Processing by master device IICn address IICn FFH Note 1 IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note 1 WRELn INTIICn (when SPIEn = 1) TRCn Receive Transfer lines SCL0n 1 2 3 4 5 6 7 8 SDA0n D7 D6 D5 D4 D3 D2 D1 D0 Processing by slave device IICn data Note 2 IICn 9 1 AD6 Start condition NACK Stop condition IICn FFH Note 1 ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L Note 1, 3 WRELn INTIICn TRCn Transmit Note 3 (When SPIEn = 1) Receive Notes 1. To cancel the wait state, write FFH to IICn or set WRELn. 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. 3. When the wait during a slave transmission is canceled by setting WRELn, TRCn is cleared. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 842 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER CHAPTER 19 CAN CONTROLLER In the PD70F3819, 70F3825, one channel of CAN controller is provided. Caution 1. The CAN controller is allocated in the programmable peripheral I/O area. Before using the CAN controller, enable use of the programmable peripheral I/O area by using the BPC register. For details, refer to 3.4.7 Programmable peripheral I/O registers. 2. When using the CAN controller, make sure that fXX = 32 to 48 MHz. 19.1 Overview The V850ES/JC3-H and V850ES/JE3-H feature an on-chip 1-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The V850ES/JC3-H and V850ES/JE3-H products with an on-chip CAN controller are as follows. * PD70F3819, 70F3825 19.1.1 Features * Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) * Standard frame and extended frame transmission/reception enabled * Transfer rate: 1 Mbps max. (CAN clock input 8 MHz) * 32 message buffers/channels * Receive/transmit history list function * Automatic block transmission function * Multi-buffer receive block function * Mask setting of four patterns is possible for each channel R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 843 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.1.2 Overview of functions Table 19-1 presents an overview of the CAN controller functions. Table 19-1. Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Baud rate Maximum 1 Mbps (CAN clock input 8 MHz) Data storage Storing messages in the CAN RAM Number of messages * 32 message buffers/channels * Each message buffer can be set to be either a transmit message buffer or a receive message buffer. Message reception * Unique ID can be set to each message buffer. * Mask setting of four patterns is possible for each channel. * A receive completion interrupt is generated each time a message is received and stored in a message buffer. * Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer receive block function). * Receive history list function Message transmission * Unique ID can be set to each message buffer. * Transmit completion interrupt for each message buffer * Message buffer numbers 0 to 7 specified as transmit message buffers can be used for automatic block transfer. Message transmission interval is programmable (automatic block transmission function (hereafter referred to as "ABT")). * Transmission history list function Remote frame processing Remote frame processing by transmit message buffer Time stamp function * The time stamp function can be set for a receive message when a 16-bit timer is used in combination. * The time stamp capture trigger can be selected (SOF or EOF in a CAN message frame can be detected). Diagnostic function * Readable error counters * "Valid protocol operation flag" for verification of bus connections * Receive-only mode * Single-shot mode * CAN protocol error type decoding * Self-test mode Release from bus-off state * Can be forcibly released from bus-off by software (timing restrictions are ignored). * Cannot be automatically released from bus-off (release request by software is required). Power save mode * CAN sleep mode (can be woken up by CAN bus) * CAN stop mode (cannot be woken up by CAN bus) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 844 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.1.3 Configuration The CAN controller is composed of the following four blocks. (1) Internal bus interface This functional block provides an Internal bus interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Memory Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module. (3) CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings. (4) CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. Figure 19-1. Block Diagram of CAN Module CPU Interrupt request INTC0TRX INTC0REC INTC0ERR INTC0WUP Internal bus CAN bus CAN module NPB interface MCM (Memory Control Module) CAN protocol layer CTXD0 CRXD0 CAN transceiver CAN_H0 CAN_L0 CAN RAM TSOUT C0MASK1 C0MASK2 C0MASK3 C0MASK4 ... Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 845 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control. The composition of these layers is illustrated below. Figure 19-2. Composition of Layers * Logical link control (LLC) Higher Data link layerNote Lower * Medium access control (MAC) Physical layer * Acceptance filtering * Overload report * Recovery management * Data capsuled/not capsuled * Frame coding (stuffing/no stuffing) * Medium access management * Error detection * Error report * Acknowledgment * Seriated/not seriated Prescription of signal level and bit description Note CAN controller specification 19.2.1 Frame format (1) Standard format frame * The standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages. (2) Extended format frame * The extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 x 218 messages. * An extended format frame is set when "recessive level" (CMOS level of "1") is set for both the SRR and IDE bits in the arbitration field. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 846 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 19-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the next data frame or remote frame (1) Bus value The bus values are divided into dominant and recessive. * Dominant level is indicated by logical 0. * Recessive level is indicated by logical 1. * When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 19.2.3 Data frame and remote frame (1) Data frame A data frame is composed of seven fields. Figure 19-3. Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) Remark D: Dominant = 0 R: Recessive = 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 847 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 19-4. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1. The data field is not transferred even if the control field's data length code is not "0000B". 2. D: Dominant = 0 R: Recessive = 1 (3) Description of fields <1> Start of frame (SOF) The start of frame field is located at the start of a data frame or remote frame. Figure 19-5. Start of Frame (SOF) (Interframe space or bus idle) Start of frame (Arbitration field) R D 1 bit Remark D: Dominant = 0 R: Recessive = 1 * If a dominant level is detected in the bus idle state, a hardware synchronization is performed (the current TQ is assigned to be the SYNC segment). * If a dominant level is sampled at the sample point following such a hardware synchronization, the bit is assigned to be a SOF. If a recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a noise only. In this case an error frame is not generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 848 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 19-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) R D Identifier RTR ID28 . . . . . . . . . . . . . . . . . . . . ID18 (11 bits) (1 bit) IDE (r1) r0 (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Figure 19-7. Arbitration Field (in Extended Format Mode) Arbitration field (Control field) R D Identifier SRR IDE Identifier RTR r1 r0 ID28 * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Table 19-3. RTR Frame Settings Frame Type RTR Bit Data frame 0 (D) Remote frame 1 (R) Table 19-4. Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 (D) 11 bits Extended format mode 1 (R) 1 (R) 29 bits R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 849 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <3> Control field The control field sets "DLC" as the number of data bytes in the data field (DLC = 0 to 8). Figure 19-8. Control Field (Arbitration field) Control field (Data field) R D RTR Remark r1 (IDE) r0 DLC3 DLC2 DLC1 DLC0 D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field's IDE bit is the same as the r1 bit. Table 19-5. Data Length Setting Data Length Code Data Byte Count DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other than above 8 bytes regardless of the value of DLC3 to DLC0 Caution In the remote frame, there is no data field even if the data length code is not 0000B. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 850 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 19-9. Data Field (Control field) Data field (CRC field) R D MSB Remark Data 0 (8 bits) MSB LSB Data 7 (8 bits) LSB D: Dominant = 0 R: Recessive = 1 <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. Figure 19-10. CRC Field (Data field or control field) CRC field (ACK field) R D CRC sequence (15 bits) Remark CRC delimiter (1 bit) D: Dominant = 0 R: Recessive = 1 * The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows. P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 * Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. * Receiving node: Compares the CRC sequence calculated using data bits that exclude the stuffing bits in the receive data with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node issues an error frame. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 851 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 19-11. ACK Field (CRC field) ACK field (End of frame) R D ACK slot (1 bit) Remark ACK delimiter (1 bit) D: Dominant = 0 R: Recessive = 1 * If no CRC error is detected, the receiving node sets the ACK slot to the dominant level. * The transmitting node outputs two recessive-level bits. <7> End of frame (EOF) The end of frame field indicates the end of data frame/remote frame. Figure 19-12. End of Frame (EOF) (ACK field) End of frame (Interframe space or overload frame) R D (7 bits) Remark D: Dominant = 0 R: Recessive = 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 852 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. * The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field. Figure 19-13. Interframe Space (Error Active Node) (Frame) Interframe space (Frame) R D Intermission (3 bits) Bus idle (0 to bits) Remarks 1. Bus idle: State in which the bus is not used by any node. 2. D: Dominant = 0 R: Recessive = 1 (b) Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. Figure 19-14. Interframe Space (Error Passive Node) (Frame) (Frame) Interframe space R Intermission (3 bits) D Remarks 1. Bus idle: Suspend transmission: Suspend transmission (8 bits) Bus idle (0 to bits) State in which the bus is not used by any node. Sequence of 8 recessive-level bits transmitted from the node in the error passive status. 2. D: Dominant = 0 R: Recessive = 1 Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 853 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER * Operation in error status Table 19-6. Operation in Error Status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 854 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.2.4 Error frame An error frame is output by a node that has detected an error. Figure 19-15. Error Frame Error frame R D <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) Interframe space or overload frame Error delimiter Error flag 2 Error flag 1 Error bit Remark D: Dominant = 0 R: Recessive = 1 Table 19-7. Definition of Error Frame Fields No. <1> Name Error flag 1 Bit Count Definition Error active node: 6 Outputs 6 dominant-level bits consecutively. Error passive node: Outputs 6 recessive-level bits consecutively. If another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> Error flag 2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> Error delimiter 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Error bit - The bit at which the error was detected. The error flag is output from the bit next to the error bit. In the case of a CRC error, this bit is output following the ACK delimiter. <5> Interframe space/overload - An interframe space or overload frame starts from here. frame R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 855 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.2.5 Overload frame An overload frame is transmitted under the following conditions. * When the receiving node has not completed the reception operationNote * If a dominant level is detected at the first two bits during intermission * If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note In this CAN controller, all reception frames can be loaded without outputting an overload frame because of the enough high-speed internal processing. Figure 19-16. Overload Frame Overload frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Overload delimiter Overload flag (node n) Overload flag (node m) Frame Remark D: Dominant = 0 R: Recessive = 1 Node n node m Table 19-8. Definition of Overload Frame Fields No Name Bit Count Definition <1> Overload flag 6 Outputs 6 dominant-level bits consecutively. <2> Overload flag from other node 0 to 6 The node that received an overload flag in the interframe space outputs an overload flag. <3> Overload delimiter Outputs 8 recessive-level bits consecutively. 8 If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Frame - Output following an end of frame, error delimiter, or overload delimiter. <5> Interframe space/overload frame R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 - An interframe space or overload frame starts from here. Page 856 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.3 Functions 19.3.1 Determining bus priority (1) When a node starts transmission: * During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: * The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). * The transmitting node compares its output arbitration field and the data level on the bus. Table 19-9. Determining Bus Priority Level match Continuous transmission Level mismatch Continuous transmission (3) Priority of data frame and remote frame * When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the last bit in the arbitration field, carries a dominant level. Remark If the extended-format data frame and the standard-format remote frame conflict on the bus (if ID28 to ID18 of both of them are the same), the standard-format remote frame takes priority. 19.3.2 Bit stuffing Bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. Table 19-10. Bit Stuffing Transmission During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit. Reception During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, reception is continued after deleting the next bit. 19.3.3 Multi masters As the bus priority (a node which acquires transmission rights) is determined by the identifier, any node can be the bus master. 19.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 857 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power consumption. The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 19.3.6 Error control function (1) Error types Table 19-11. Error Types Type Description of Error Detection Method Comparison of the output level Bit error Detection State Detection Transmission/ Condition Reception Mismatch of levels and level on the bus Field/Frame Transmitting/ Bit that is outputting data on the bus receiving node at the start of frame to end of frame, error frame and overload frame. Stuff error CRC error Check of the receive data at 6 consecutive bits of the stuff bit the same output level Comparison of the CRC Receiving node Start of frame to CRC sequence Mismatch of CRC Receiving node CRC field Field/frame check of the fixed Detection of fixed Receiving node CRC delimiter format format violation sequence generated from the receive data and the received CRC sequence Form error ACK field End of frame Error frame Overload frame ACK error Check of the ACK slot by the Detection of recessive transmitting node level in ACK slot Transmitting node ACK slot (2) Output timing of error frame Table 19-12. Output Timing of Error Frame Type Bit error, stuff error, form Output Timing Error frame output is started at the timing of the bit following the detected error. error, ACK error CRC error Error frame output is started at the timing of the bit following the ACK delimiter. (3) Processing in case of error The transmission node re-transmits the data frame or remote frame after the error frame. (However, it does not retransmit the frame in the single-shot mode.) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 858 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. * Error active * Error passive * Bus-off These types of error states are classified by the values of the C0ERC.TEC7 to C0ERC.TEC0 bits (transmission error counter bits) and the C0ERC.REC6 to C0ERC.REC0 bits (reception error counter bits) as shown in Table 19-13. The present error state is indicated by the C0INFO register. When each error counter value becomes equal to or greater than the error warning level (96), the C0INFO.TECS0 or C0INFO.RECS0 bit is set to 1. In this case, the bus state must be tested because it is considered that the bus has a serious fault. An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit is set to 1. * If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the C0INFO.BOFF bit is set to 1. * If only one node is active on the bus at startup (i.e., when the bus is connected only to the local station), ACK is not returned even if data is transmitted. Consequently, re-transmission of the error frame and data is repeated. In the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 859 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-13. Types of Error States Type Error active Error passive Operation Value of Error Indication of C0INFO Counter Register Transmission 0 to 95 TECS1, TECS0 = 00 Reception 0 to 95 RECS1, RECS0 = 00 Transmission 96 to 127 TECS1, TECS0 = 01 Reception 96 to 127 RECS1, RECS0 = 01 Transmission 128 to 255 TECS1, TECS0 = 11 Reception 128 or more RECS1, RECS0 = 11 Operation Specific to Error State * Outputs an active error flag (6 consecutive dominantlevel bits) on detection of the error. * Outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. * Transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). Bus-off Transmission 256 or more BOFF = 1, Note (not indicated) TECS1, TECS0 = 11 * Communication is not possible. However, when the frame is received, no messages are stored and the following operations are performed. <1> TSOUT toggles. <2> REC is incremented/decremented. <3> VALID bit is set. * If the initialization mode is set, after request to transit to an operation mode other than the initialization mode, 11 consecutive recessive-level bits are generated 128 times, and then the error counter is reset to 0 and the error active state can be restored. Note The value of the transmit error counter (TEC) does not carry any meaning if BOFF has been set. If an error that increments the value of the transmission error counter by 8 while the counter value is in a range of 248 to 255 occurs, the counter is not incremented and the bus-off state is assumed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 860 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter counts up immediately after error detection. Table 19-14. Error Counter State Receiving node detects an error (except bit error in the active error Transmission Error Counter Reception Error Counter (TEC7 to TEC0 Bits) (REC6 to REC0 Bits) No change +1 (REPS bit = 0) No change +8 (REPS bit = 0) +8 No change +8 No change No change +8 (REPS bit = 0) +8 (transmitting) +8 (receiving, REPS bit = 0) -1 No change No change * -1 (1 REC6 to REC0 flag or overload flag). Receiving node detects dominant level following error flag of error frame. Transmitting node transmits an error flag. [As exceptions, the error counter does not change in the following cases.] <1> ACK error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. Bit error detection while active error flag or overload flag is being output (error-active transmitting node) Bit error detection while active error flag or overload flag is being output (error-active receiving node) When the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. When the node detects 8 consecutive dominant levels after a passive error flag When the transmitting node has completed transmission without error (0 if error counter = 0) When the receiving node has completed reception without error 127, REPS bit = 0) * 0 (REC6 to REC0 = 0, REPS bit = 0) * Any value of 119 to 127 is set (REPS bit = 1) (c) Occurrence of bit error in intermission An overload frame is generated. Caution If an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. The value of the error counter is incremented after the error flag has been output. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 861 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the transmission pins (CTXD0) cut off from the CAN bus always output the recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1> Request to enter the CAN initialization mode <2> Request to enter a CAN operation mode (a) Recovery operation through normal recovery sequence (b) Forced recovery operation that skips recovery sequence (a) Recovery from bus-off state through normal recovery sequence The CAN module first issues a request to enter the initialization mode (refer to timing <1> in Figure 19-17). This request will be immediately acknowledged, and the C0CTRL.OPMODE2 to OPMODE0 bits are cleared to 000B. Processing such as analyzing the fault that has caused the bus-off state, re-defining the CAN module and message buffer using application software, or stopping the operation of the CAN module can be performed by clearing the C0GMCTRL.GOM bit to 0. Next, the module requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in Figure 19-17). This starts an operation to recover the CAN module from the bus-off state. The conditions under which the module can recover from the bus-off state are defined by the CAN protocol ISO 11898, and it is necessary to detect 11 consecutive recessive-level bits more than 128 times. At this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. When the recovery conditions are satisfied (refer to timing <3> in Figure 19-17), the CAN module can enter the operation mode it has requested. Until the CAN module enters this operation mode, it stays in the initialization mode. Whether the CAN module has completed transition to any other operation mode can be confirmed by reading the OPMODE2 to OPMODE0 bits. Before transition to any other operation mode is completed, OPMODE2 to OPMODE0 bits = 000B is read. During the bus-off period and bus-off recovery sequence, the C0INFO.BOFF bit stays set (to 1). In the bus-off recovery sequence, the reception error counter (C0ERC.REC0 to C0ERC.REC6) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state can be checked by reading the REC0 to REC6 bits. Cautions 1. If a request to change the mode from the initialization mode to any operation mode to execute the bus-off recovery sequence again during a bus-off recovery sequence, the bus-off recovery sequence starts from the beginning and 11 contiguous recessive bits are counted 128 times again on the bus. 2. In the bus-off recovery sequence, the REC0 to REC6 bits counts up (+1) each time 11 consecutive recessive-level bits have been detected. Even during the bus-off period, the CAN module can enter the CAN sleep mode or CAN stop mode. To be released from the bus-off state, the module must enter the initialization mode once. If the module is in the CAN sleep mode or CAN stop mode, however, it cannot directly enter the initialization mode. In this case, the bus off recovery sequence is started at the same time as the CAN sleep mode is released even without shifting to the initialization mode. In addition to clearing the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits by software, the bus off recovery sequence is also started due to wakeup by dominant edge detection on the CAN bus (While the CAN clock is supplied, the C0CTRL.PSMODE0 bit must be cleared by software after a dominant edge is detected.) . R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 862 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-17. Recovery from Bus-off State Through Normal Recovery Sequence TEC > FFH bus-off error-passive bus-off-recovery-sequence error-active BOFF bit in C0INFO register <1> OPMODE[2:0] in C0CTRL register (written by user) 00H OPMODE[2:0] in C0CTRL register (read by user) 00H 00H 00H <3> TEC[7:0] in C0ERC 80H TEC[7:0] FFH register REC[7:0] in C0ERC register <2> 00H 00H FFH < TEC [7:0] 00H REC[7:0] 80H 00H Undefined 00H TEC[7:0] < 80H 00H REC[7:0] < 80H (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at this time, see 19.3.6 (5) (a) Recovery from bus-off state through normal recovery sequence. Next, the module requests to enter an operation mode. At the same time, the C0CTRL.CCERC bit must be set to 1. As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure 19-54. Caution This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 863 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (6) Initializing CAN module error counter register (C0ERC) in initialization mode If it is necessary to initialize the C0ERC and C0INFO registers for debugging or evaluating a program, they can be initialized to the default value by setting the C0CTRL.CCERC bit in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0. Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in a CAN operation mode, the C0ERC and C0INFO registers are not initialized. 2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 864 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN protocol layer base clock (fTQ) that is the CAN module system clock (fCANMOD) divided by 1 to 256 (see 19.6 (12) CAN0 module bit rate prescaler register (C0BRP)). (2) Data bit time (8 to 25 time quanta) One data bit time is defined as shown in Figure 19-18. 1 Time Quanta = 1/fTQ The CAN controller sets the data bit time by replacing it with the bit timing parameters such as time segment 1, time segment 2, and reSynchronization Jump Width (SJW), as shown in Figure 19-18. Time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN protocol specification. Time segment 2 is equivalent to phase segment 2. Figure 19-18. Segment Setting Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) Phase segment 2 Time segment 2 (TSEG2) Sample point (SPT) Segment name Settable range Time segment 1 (TSEG1) 2TQ to 16TQ Time segment 2 (TSEG2) 1TQ to 8TQ Notes on setting to conform to CAN specification - IPT of the CAN controller is 0TQ. To conform to the CAN protocol specification, therefore, a length equal or less to phase segment 1 must be set here. This means that the length of time segment 1 minus 1TQ is the settable upper limit of time segment 2. reSynchronization Jump Width 1TQ to 4TQ Remark The length of time segment 1 minus 1TQ or 4TQ, whichever smaller. (SJW) IPT: Information Processing Time TQ: Time Quanta R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 865 of 1442 V850ES/JC3-H, V850ES/JE3-H Remark CHAPTER 19 CAN CONTROLLER The CAN protocol specification defines the segments constituting the data bit time as shown in Figure 19-19. Figure 19-19. Configuration of Data Bit Time Defined by CAN Specification Data bit time (DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point (SPT) Segment name Sync segment Segment length 1 Description This segment starts at the edge where the level changes from recessive to dominant when hardware synchronization (Synchronization segment) is established. Prop segment Programmable to 1 to 8, This segment absorbs the delay of the output buffer, CAN (Propagation segment) or greater bus, and input buffer. The length of this segment is set so that ACK is returned before the start of phase segment 1. Time of prop segment (Delay of output buffer) + 2 x (Delay of CAN bus) + (Delay of input buffer) Phase segment 1 Programmable to 1 to 8 This segment compensates for an error in the data bit time. The longer this segment, the wider the permissible range (Phase buffer segment 1) but the slower the communication speed. Phase segment 2 Phase segment 1 or IPT, (Phase buffer segment 2) whichever greater SJW Programmable from 1TQ This width sets the upper limit of expansion or contraction (reSynchronization Jump to segment 1TQ to 4TQ, of the phase segment during resynchronization. Width) whichever is smaller Remark IPT: Information Processing Time TQ: Time Quanta R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 866 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (3) Synchronizing data bit * The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. * The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space. * When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the prop segment. In this case, synchronization is established regardless of SJW. Figure 19-20. Hardware Synchronization Due to Dominant Level Detection During Bus Idle Interframe space Start of frame CAN bus Bit timing R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Sync segment Prop segment Phase segment 1 Phase segment 2 Page 867 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). * The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error> 0: If the edge is within the sync segment Positive: If the edge is before the sample point (phase error) Negative: If the edge is after the sample point (phase error) If phase error is positive: Phase segment 1 is longer by specified SJW. If phase error is negative: Phase segment 2 is shorter by specified SJW. * The sample point of the data of the receiving node moves relatively due to the "discrepancy" in the baud rate between the transmitting node and receiving node. Figure 19-21. Resynchronization If phase error is positive CAN bus Bit timing Sync segment Prop segment Phase segment 2 Phase segment 1 Sample point If phase error is negative CAN bus Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 868 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.4 Connection with Target System The microcontroller with on-chip CAN controller has to be connected to the CAN bus using an external transceiver. Figure 19-22. Connection to CAN Bus Microcontroller with on-chip CAN controller R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 CTXD0 CRXD0 CANL Transceiver CANH Page 869 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.5 Internal Registers of CAN Controller 19.5.1 CAN controller configuration Table 19-15. List of CAN Controller Registers Item CAN global registers Register Name CAN0 global control register (C0GMCTRL) CAN0 global clock selection register (C0GMCS) CAN0 global automatic block transmission control register (C0GMABT) CAN0 global automatic block transmission delay setting register (C0GMABTD) CAN module registers CAN0 module mask 1 register (C0MASK1L, C0MASK1H) CAN0 module mask 2 register (C0MASK2L, C0MASK2H) CAN0 module mask 3 register (C0MASK3L, C0MASK3H) CAN0 module mask 4 registers (C0MASK4L, C0MASK4H) CAN0 module control register (C0CTRL) CAN0 module last error information register (C0LEC) CAN0 module information register (C0INFO) CAN0 module error counter register (C0ERC) CAN0 module interrupt enable register (C0IE) CAN0 module interrupt status register (C0INTS) CAN0 module bit rate prescaler register (C0BRP) CAN0 module bit rate register (C0BTR) CAN0 module last in-pointer register (C0LIPT) CAN0 module receive history list register (C0RGPT) CAN0 module last out-pointer register (C0LOPT) CAN0 module transmit history list register (C0TGPT) CAN0 module time stamp register (C0TS) Message buffer registers CAN0 message data byte 01 register m (C0MDATA01m) CAN0 message data byte 0 register m (C0MDATA0m) CAN0 message data byte 1 register m (C0MDATA1m) CAN0 message data byte 23 register m (C0MDATA23m) CAN0 message data byte 2 register m (C0MDATA2m) CAN0 message data byte 3 register m (C0MDATA3m) CAN0 message data byte 45 register m (C0MDATA45m) CAN0 message data byte 4 register m (C0MDATA4m) CAN0 message data byte 5 register m (C0MDATA5m) CAN0 message data byte 67 register m (C0MDATA67m) CAN0 message data byte 6 register m (C0MDATA6m) CAN0 message data byte 7 register m (C0MDATA7m) CAN0 message data length register m (C0MDLCm) CAN0 message configuration register m (C0MCONFm) CAN0 message ID register m (C0MIDLm, C0MIDHm) CAN0 message control register m (C0MCTRLm) Remarks 1. The CAN global register is defined as C0GM <register function>. The CAN module register is defined as C0 <register function>. The message buffer register is defined as C0M <register function>. 2. m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 870 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.5.2 Register access type Table 19-16. Register Access Types (1/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC000H CAN0 global control register C0GMCTRL 03FEC002H CAN0 global clock selection register C0GMCS 03FEC006H CAN0 global automatic block transmission C0GMABT 8 Bits 16 Bits R/W After Reset 0000H 0FH 0000H register 03FEC008H CAN0 global automatic block transmission C0GMABTD 00H delay register 03FEC040H CAN0 module mask 1 register 03FEC042H 03FEC044H CAN0 module mask 2 register 03FEC046H 03FEC048H CAN0 module mask 3 register 03FEC04AH 03FEC04CH CAN0 module mask 4 register 03FEC04EH C0MASK1L Undefined C0MASK1H Undefined C0MASK2L Undefined C0MASK2H Undefined C0MASK3L Undefined C0MASK3H Undefined C0MASK4L Undefined C0MASK4H Undefined 0000H 03FEC050H CAN0 module control register C0CTRL 03FEC052H CAN0 module last error code register C0LEC 03FEC053H CAN0 module information register C0INFO 03FEC054H CAN0 module error counter register C0ERC 03FEC056H CAN0 module interrupt enable register C0IE 03FEC058H CAN0 module interrupt status register C0INTS 03FEC05AH CAN0 module bit-rate prescaler register C0BRP 03FEC05CH CAN0 module bit-rate register C0BTR 03FEC05EH CAN0 module last in-pointer register C0LIPT 03FEC060H CAN0 module receive history list register C0RGPT 03FEC062H CAN0 module last out-pointer register C0LOPT R 03FEC064H CAN0 module transmit history list register C0TGPT R/W 03FEC066H CAN0 module time stamp register C0TS R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 R 00H R/W 00H 0000H 0000H 0000H FFH R Undefined R/W 370FH xx02H Undefined xx02H 0000H Page 871 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (2/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC100H After Reset 8 Bits 16 Bits CAN0 message data byte 01 register 00 C0MDATA0100 03FEC100H CAN0 message data byte 0 register 00 C0MDATA000 Undefined 03FEC101H CAN0 message data byte 1 register 00 C0MDATA100 Undefined CAN0 message data byte 23 register 00 C0MDATA2300 03FEC102H CAN0 message data byte 2 register 00 C0MDATA200 Undefined 03FEC103H CAN0 message data byte 3 register 00 C0MDATA300 Undefined 03FEC102H 03FEC104H R/W Undefined Undefined CAN0 message data byte 45 register 00 C0MDATA4500 03FEC104H CAN0 message data byte 4 register 00 C0MDATA400 Undefined 03FEC105H CAN0 message data byte 5 register 00 C0MDATA500 Undefined CAN0 message data byte 67 register 00 C0MDATA6700 03FEC106H CAN0 message data byte 6 register 00 C0MDATA600 Undefined 03FEC107H CAN0 message data byte 7 register 00 C0MDATA700 Undefined 03FEC108H CAN0 message data length register 00 C0MDLC00 0000xxxxB 03FEC109H CAN0 message configuration register 00 C0MCONF00 Undefined 03FEC10AH CAN0 message identifier register 00 C0MIDL00 Undefined C0MIDH00 Undefined C0MCTRL00 00x00000 03FEC106H 03FEC10CH 03FEC10EH CAN0 message control register 00 Undefined Undefined 000xx000B 03FEC120H CAN0 message data byte 01 register 01 C0MDATA0101 03FEC120H CAN0 message data byte 0 register 01 C0MDATA001 Undefined 03FEC121H CAN0 message data byte 1 register 01 C0MDATA101 Undefined CAN0 message data byte 23 register 01 C0MDATA2301 03FEC122H CAN0 message data byte 2 register 01 C0MDATA201 03FEC123H CAN0 message data byte 3 register 01 C0MDATA301 CAN0 message data byte 45 register 01 C0MDATA4501 03FEC124H CAN0 message data byte 4 register 01 C0MDATA401 Undefined 03FEC125H CAN0 message data byte 5 register 01 C0MDATA501 Undefined CAN0 message data byte 67 register 01 C0MDATA6701 03FEC126H CAN0 message data byte 6 register 01 C0MDATA601 Undefined 03FEC127H CAN0 message data byte 7 register 01 C0MDATA701 Undefined CAN0 message data length register 01 C0MDLC01 0000xxxxB 03FEC129H CAN0 message configuration register 01 C0MCONF01 03FEC12AH CAN0 message identifier register 01 C0MIDL01 Undefined C0MIDH01 Undefined C0MCTRL01 00x00000 03FEC122H 03FEC124H 03FEC126H 03FEC128H 03FEC12CH 03FEC12EH CAN0 message control register 01 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 872 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (3/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC140H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 02 C0MDATA0102 03FEC140H CAN0 message data byte 0 register 02 C0MDATA002 Undefined 03FEC141H CAN0 message data byte 1 register 02 C0MDATA102 Undefined CAN0 message data byte 23 register 02 C0MDATA2302 03FEC142H CAN0 message data byte 2 register 02 C0MDATA202 Undefined 03FEC143H CAN0 message data byte 3 register 02 C0MDATA302 Undefined 03FEC142H 03FEC144H Undefined Undefined CAN0 message data byte 45 register 02 C0MDATA4502 03FEC144H CAN0 message data byte 4 register 02 C0MDATA402 Undefined 03FEC145H CAN0 message data byte 5 register 02 C0MDATA502 Undefined CAN0 message data byte 67 register 02 C0MDATA6702 03FEC146H CAN0 message data byte 6 register 02 C0MDATA602 Undefined 03FEC147H CAN0 message data byte 7 register 02 C0MDATA702 Undefined 03FEC148H CAN0 message data length register 02 C0MDLC02 0000xxxxB 03FEC149H CAN0 message configuration register 02 C0MCONF02 Undefined 03FEC14AH CAN0 message identifier register 02 C0MIDL02 Undefined C0MIDH02 Undefined C0MCTRL02 00x00000 03FEC146H 03FEC14CH 03FEC14EH CAN0 message control register 02 Undefined Undefined 000xx000B 03FEC160H CAN0 message data byte 01 register 03 C0MDATA0103 03FEC160H CAN0 message data byte 0 register 03 C0MDATA003 Undefined 03FEC161H CAN0 message data byte 1 register 03 C0MDATA103 Undefined CAN0 message data byte 23 register 03 C0MDATA2303 CAN0 message data byte 2 register 03 C0MDATA203 03FEC162H 03FEC162H 03FEC163H Undefined Undefined Undefined CAN0 message data byte 3 register 03 C0MDATA303 CAN0 message data byte 45 register 03 C0MDATA4503 03FEC164H CAN0 message data byte 4 register 03 C0MDATA403 Undefined 03FEC165H CAN0 message data byte 5 register 03 C0MDATA503 Undefined CAN0 message data byte 67 register 03 C0MDATA6703 03FEC166H CAN0 message data byte 6 register 03 C0MDATA603 Undefined 03FEC167H CAN0 message data byte 7 register 03 C0MDATA703 Undefined 03FEC168H CAN0 message data length register 03 C0MDLC03 0000xxxxB 03FEC169H CAN0 message configuration register 03 C0MCONF03 03FEC16AH CAN0 message identifier register 03 C0MIDL03 Undefined C0MIDH03 Undefined C0MCTRL03 00x00000 03FEC164H 03FEC166H 03FEC16CH 03FEC16EH CAN0 message control register 03 Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 873 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (4/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC180H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 04 C0MDATA0104 03FEC180H CAN0 message data byte 0 register 04 C0MDATA004 Undefined 03FEC181H CAN0 message data byte 1 register 04 C0MDATA104 Undefined CAN0 message data byte 23 register 04 C0MDATA2304 03FEC182H CAN0 message data byte 2 register 04 C0MDATA204 Undefined 03FEC183H CAN0 message data byte 3 register 04 C0MDATA304 Undefined 03FEC182H 03FEC184H Undefined Undefined CAN0 message data byte 45 register 04 C0MDATA4504 03FEC184H CAN0 message data byte 4 register 04 C0MDATA404 Undefined 03FEC185H CAN0 message data byte 5 register 04 C0MDATA504 Undefined CAN0 message data byte 67 register 04 C0MDATA6704 03FEC186H CAN0 message data byte 6 register 04 C0MDATA604 Undefined 03FEC187H CAN0 message data byte 7 register 04 C0MDATA704 Undefined 03FEC188H CAN0 message data length register 04 C0MDLC04 0000xxxxB 03FEC189H CAN0 message configuration register 04 C0MCONF04 Undefined 03FEC18AH CAN0 message identifier register 04 C0MIDL04 Undefined C0MIDH04 Undefined C0MCTRL04 00x00000 03FEC186H 03FEC18CH 03FEC18EH CAN0 message control register 04 Undefined Undefined 000xx000B 03FEC1A0H CAN0 message data byte 01 register 05 C0MDATA0105 03FEC1A0H CAN0 message data byte 0 register 05 C0MDATA005 Undefined 03FEC1A1H CAN0 message data byte 1 register 05 C0MDATA105 Undefined CAN0 message data byte 23 register 05 C0MDATA2305 03FEC1A2H CAN0 message data byte 2 register 05 C0MDATA205 03FEC1A3H CAN0 message data byte 3 register 05 C0MDATA305 CAN0 message data byte 45 register 05 C0MDATA4505 03FEC1A4H CAN0 message data byte 4 register 05 C0MDATA405 Undefined 03FEC1A5H CAN0 message data byte 5 register 05 C0MDATA505 Undefined CAN0 message data byte 67 register 05 C0MDATA6705 03FEC1A6H CAN0 message data byte 6 register 05 C0MDATA605 Undefined 03FEC1A7H CAN0 message data byte 7 register 05 C0MDATA705 Undefined 03FEC1A8H CAN0 message data length register 05 C0MDLC05 0000xxxxB 03FEC1A9H CAN0 message configuration register 05 C0MCONF05 03FEC1AAH CAN0 message identifier register 05 C0MIDL05 Undefined C0MIDH05 Undefined C0MCTRL05 00x00000 03FEC1A2H 03FEC1A4H 03FEC1A6H 03FEC1ACH 03FEC1AEH CAN0 message control register 05 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 874 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (5/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC1C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 06 C0MDATA0106 03FEC1C0H CAN0 message data byte 0 register 06 C0MDATA006 Undefined 03FEC1C1H CAN0 message data byte 1 register 06 C0MDATA106 Undefined CAN0 message data byte 23 register 06 C0MDATA2306 03FEC1C2H CAN0 message data byte 2 register 06 C0MDATA206 Undefined 03FEC1C3H CAN0 message data byte 3 register 06 C0MDATA306 Undefined 03FEC1C2H 03FEC1C4H Undefined Undefined CAN0 message data byte 45 register 06 C0MDATA4506 03FEC1C4H CAN0 message data byte 4 register 06 C0MDATA406 Undefined 03FEC1C5H CAN0 message data byte 5 register 06 C0MDATA506 Undefined CAN0 message data byte 67 register 06 C0MDATA6706 03FEC1C6H CAN0 message data byte 6 register 06 C0MDATA606 Undefined 03FEC1C7H CAN0 message data byte 7 register 06 C0MDATA706 Undefined 03FEC1C8H CAN0 message data length register 06 C0MDLC06 0000xxxxB 03FEC1C9H CAN0 message configuration register 06 C0MCONF06 Undefined 03FEC1CAH CAN0 message identifier register 06 C0MIDL06 Undefined C0MIDH06 Undefined C0MCTRL06 00x00000 03FEC1C6H 03FEC1CCH 03FEC1CEH CAN0 message control register 06 Undefined Undefined 000xx000B 03FEC1E0H CAN0 message data byte 01 register 07 C0MDATA0107 03FEC1E0H CAN0 message data byte 0 register 07 C0MDATA007 Undefined 03FEC1E1H CAN0 message data byte 1 register 07 C0MDATA107 Undefined CAN0 message data byte 23 register 07 C0MDATA2307 03FEC1E2H CAN0 message data byte 2 register 07 C0MDATA207 03FEC1E3H CAN0 message data byte 3 register 07 C0MDATA307 CAN0 message data byte 45 register 07 C0MDATA4507 03FEC1E4H CAN0 message data byte 4 register 07 C0MDATA407 Undefined 03FEC1E5H CAN0 message data byte 5 register 07 C0MDATA507 Undefined CAN0 message data byte 67 register 07 C0MDATA6707 03FEC1E6H CAN0 message data byte 6 register 07 C0MDATA607 Undefined 03FEC1E7H CAN0 message data byte 7 register 07 C0MDATA707 Undefined 03FEC1E8H CAN0 message data length register 07 C0MDLC07 0000xxxxB 03FEC1E9H CAN0 message configuration register 07 C0MCONF07 03FEC1EAH CAN0 message identifier register 07 C0MIDL07 Undefined C0MIDH07 Undefined C0MCTRL07 00x00000 03FEC1E2H 03FEC1E4H 03FEC1E6H 03FEC1ECH 03FEC1EEH CAN0 message control register 07 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 875 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (6/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC200H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 08 C0MDATA0108 03FEC200H CAN0 message data byte 0 register 08 C0MDATA008 Undefined 03FEC201H CAN0 message data byte 1 register 08 C0MDATA108 Undefined CAN0 message data byte 23 register 08 C0MDATA2308 03FEC202H CAN0 message data byte 2 register 08 C0MDATA208 Undefined 03FEC203H CAN0 message data byte 3 register 08 C0MDATA308 Undefined 03FEC202H 03FEC204H Undefined Undefined CAN0 message data byte 45 register 08 C0MDATA4508 03FEC204H CAN0 message data byte 4 register 08 C0MDATA408 Undefined 03FEC205H CAN0 message data byte 5 register 08 C0MDATA508 Undefined CAN0 message data byte 67 register 08 C0MDATA6708 03FEC206H CAN0 message data byte 6 register 08 C0MDATA608 Undefined 03FEC207H CAN0 message data byte 7 register 08 C0MDATA708 Undefined 03FEC208H CAN0 message data length register 08 C0MDLC08 0000xxxxB 03FEC209H CAN0 message configuration register 08 C0MCONF08 Undefined 03FEC20AH CAN0 message identifier register 08 C0MIDL08 Undefined C0MIDH08 Undefined C0MCTRL08 00x00000 03FEC206H 03FEC20CH 03FEC20EH CAN0 message control register 08 Undefined Undefined 000xx000B 03FEC220H CAN0 message data byte 01 register 09 C0MDATA0109 03FEC220H CAN0 message data byte 0 register 09 C0MDATA009 Undefined 03FEC221H CAN0 message data byte 1 register 09 C0MDATA109 Undefined CAN0 message data byte 23 register 09 C0MDATA2309 03FEC222H CAN0 message data byte 2 register 09 C0MDATA209 03FEC223H CAN0 message data byte 3 register 09 C0MDATA309 CAN0 message data byte 45 register 09 C0MDATA4509 03FEC224H CAN0 message data byte 4 register 09 C0MDATA409 Undefined 03FEC225H CAN0 message data byte 5 register 09 C0MDATA509 Undefined CAN0 message data byte 67 register 09 C0MDATA6709 03FEC226H CAN0 message data byte 6 register 09 C0MDATA609 Undefined 03FEC227H CAN0 message data byte 7 register 09 C0MDATA709 Undefined 03FEC228H CAN0 message data length register 09 C0MDLC09 0000xxxxB 03FEC229H CAN0 message configuration register 09 C0MCONF09 03FEC22AH CAN0 message identifier register 09 C0MIDL09 Undefined C0MIDH09 Undefined C0MCTRL09 00x00000 03FEC222H 03FEC224H 03FEC226H 03FEC22CH 03FEC22EH CAN0 message control register 09 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 876 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (7/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC240H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 10 C0MDATA0110 03FEC240H CAN0 message data byte 0 register 10 C0MDATA010 Undefined 03FEC241H CAN0 message data byte 1 register 10 C0MDATA110 Undefined CAN0 message data byte 23 register 10 C0MDATA2310 03FEC242H CAN0 message data byte 2 register 10 C0MDATA210 Undefined 03FEC243H CAN0 message data byte 3 register 10 C0MDATA310 Undefined 03FEC242H 03FEC244H Undefined Undefined CAN0 message data byte 45 register 10 C0MDATA4510 03FEC244H CAN0 message data byte 4 register 10 C0MDATA410 Undefined 03FEC245H CAN0 message data byte 5 register 10 C0MDATA510 Undefined CAN0 message data byte 67 register 10 C0MDATA6710 03FEC246H CAN0 message data byte 6 register 10 C0MDATA610 Undefined 03FEC247H CAN0 message data byte 7 register 10 C0MDATA710 Undefined 03FEC248H CAN0 message data length register 10 C0MDLC10 0000xxxxB 03FEC249H CAN0 message configuration register 10 C0MCONF10 Undefined 03FEC24AH CAN0 message identifier register 10 C0MIDL10 Undefined C0MIDH10 Undefined C0MCTRL10 00x00000 03FEC246H 03FEC24CH 03FEC24EH CAN0 message control register 10 Undefined Undefined 000xx000B 03FEC260H CAN0 message data byte 01 register 11 C0MDATA0111 03FEC260H CAN0 message data byte 0 register 11 C0MDATA011 Undefined 03FEC261H CAN0 message data byte 1 register 11 C0MDATA111 Undefined CAN0 message data byte 23 register 11 C0MDATA2311 03FEC262H CAN0 message data byte 2 register 11 C0MDATA211 03FEC263H CAN0 message data byte 3 register 11 C0MDATA311 CAN0 message data byte 45 register 11 C0MDATA4511 03FEC264H CAN0 message data byte 4 register 11 C0MDATA411 Undefined 03FEC265H CAN0 message data byte 5 register 11 C0MDATA511 Undefined CAN0 message data byte 67 register 11 C0MDATA6711 03FEC266H CAN0 message data byte 6 register 11 C0MDATA611 Undefined 03FEC267H CAN0 message data byte 7 register 11 C0MDATA711 Undefined 03FEC268H CAN0 message data length register 11 C0MDLC11 0000xxxxB 03FEC269H CAN0 message configuration register 11 C0MCONF11 03FEC26AH CAN0 message identifier register 11 C0MIDL11 Undefined C0MIDH11 Undefined C0MCTRL11 00x00000 03FEC262H 03FEC264H 03FEC266H 03FEC26CH 03FEC26EH CAN0 message control register 11 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 877 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (8/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC280H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 12 C0MDATA0112 03FEC280H CAN0 message data byte 0 register 12 C0MDATA012 Undefined 03FEC281H CAN0 message data byte 1 register 12 C0MDATA112 Undefined CAN0 message data byte 23 register 12 C0MDATA2312 03FEC282H CAN0 message data byte 2 register 12 C0MDATA212 Undefined 03FEC283H CAN0 message data byte 3 register 12 C0MDATA312 Undefined 03FEC282H 03FEC284H Undefined Undefined CAN0 message data byte 45 register 12 C0MDATA4512 03FEC284H CAN0 message data byte 4 register 12 C0MDATA412 Undefined 03FEC285H CAN0 message data byte 5 register 12 C0MDATA512 Undefined CAN0 message data byte 67 register 12 C0MDATA6712 03FEC286H CAN0 message data byte 6 register 12 C0MDATA612 Undefined 03FEC287H CAN0 message data byte 7 register 12 C0MDATA712 Undefined 03FEC288H CAN0 message data length register 12 C0MDLC12 0000xxxxB 03FEC289H CAN0 message configuration register 12 C0MCONF12 Undefined 03FEC28AH CAN0 message identifier register 12 C0MIDL12 Undefined C0MIDH12 Undefined C0MCTRL12 00x00000 03FEC286H 03FEC28CH 03FEC28EH CAN0 message control register 12 Undefined Undefined 000xx000B 03FEC2A0H CAN0 message data byte 01 register 13 C0MDATA0113 03FEC2A0H CAN0 message data byte 0 register 13 C0MDATA013 Undefined 03FEC2A1H CAN0 message data byte 1 register 13 C0MDATA113 Undefined CAN0 message data byte 23 register 13 C0MDATA2313 03FEC2A2H CAN0 message data byte 2 register 13 C0MDATA213 03FEC2A3H CAN0 message data byte 3 register 13 C0MDATA313 CAN0 message data byte 45 register 13 C0MDATA4513 03FEC2A4H CAN0 message data byte 4 register 13 C0MDATA413 Undefined 03FEC2A5H CAN0 message data byte 5 register 13 C0MDATA513 Undefined CAN0 message data byte 67 register 13 C0MDATA6713 03FEC2A6H CAN0 message data byte 6 register 13 C0MDATA613 Undefined 03FEC2A7H CAN0 message data byte 7 register 13 C0MDATA713 Undefined 03FEC2A8H CAN0 message data length register 13 C0MDLC13 0000xxxxB 03FEC2A9H CAN0 message configuration register 13 C0MCONF13 03FEC2AAH CAN0 message identifier register 13 C0MIDL13 Undefined C0MIDH13 Undefined C0MCTRL13 00x00000 03FEC2A2H 03FEC2A4H 03FEC2A6H 03FEC2ACH 03FEC2AEH CAN0 message control register 13 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 878 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (9/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC2C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 14 C0MDATA0114 03FEC2C0H CAN0 message data byte 0 register 14 C0MDATA014 Undefined 03FEC2C1H CAN0 message data byte 1 register 14 C0MDATA114 Undefined CAN0 message data byte 23 register 14 C0MDATA2314 03FEC2C2H CAN0 message data byte 2 register 14 C0MDATA214 Undefined 03FEC2C3H CAN0 message data byte 3 register 14 C0MDATA314 Undefined 03FEC2C2H 03FEC2C4H Undefined Undefined CAN0 message data byte 45 register 14 C0MDATA4514 03FEC2C4H CAN0 message data byte 4 register 14 C0MDATA414 Undefined 03FEC2C5H CAN0 message data byte 5 register 14 C0MDATA514 Undefined CAN0 message data byte 67 register 14 C0MDATA6714 03FEC2C6H CAN0 message data byte 6 register 14 C0MDATA614 Undefined 03FEC2C7H CAN0 message data byte 7 register 14 C0MDATA714 Undefined 03FEC2C8H CAN0 message data length register 14 C0MDLC14 0000xxxxB 03FEC2C9H CAN0 message configuration register 14 C0MCONF14 Undefined 03FEC2CAH CAN0 message identifier register 14 C0MIDL14 Undefined C0MIDH14 Undefined C0MCTRL14 00x00000 03FEC2C6H 03FEC2CCH 03FEC2CEH CAN0 message control register 14 Undefined Undefined 000xx000B 03FEC2E0H CAN0 message data byte 01 register 15 C0MDATA0115 03FEC2E0H CAN0 message data byte 0 register 15 C0MDATA015 Undefined 03FEC2E1H CAN0 message data byte 1 register 15 C0MDATA115 Undefined CAN0 message data byte 23 register 15 C0MDATA2315 03FEC2E2H CAN0 message data byte 2 register 15 C0MDATA215 03FEC2E3H CAN0 message data byte 3 register 15 C0MDATA315 CAN0 message data byte 45 register 15 C0MDATA4515 03FEC2E4H CAN0 message data byte 4 register 15 C0MDATA415 Undefined 03FEC2E5H CAN0 message data byte 5 register 15 C0MDATA515 Undefined CAN0 message data byte 67 register 15 C0MDATA6715 03FEC2E6H CAN0 message data byte 6 register 15 C0MDATA615 Undefined 03FEC2E7H CAN0 message data byte 7 register 15 C0MDATA715 Undefined 03FEC2E8H CAN0 message data length register 15 C0MDLC15 0000xxxxB 03FEC2E9H CAN0 message configuration register 15 C0MCONF15 03FEC2EAH CAN0 message identifier register 15 C0MIDL15 Undefined C0MIDH15 Undefined C0MCTRL15 00x00000 03FEC2E2H 03FEC2E4H 03FEC2E6H 03FEC2ECH 03FEC2EEH CAN0 message control register 15 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 879 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (10/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC300H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 16 C0MDATA0116 03FEC300H CAN0 message data byte 0 register 16 C0MDATA016 Undefined 03FEC301H CAN0 message data byte 1 register 16 C0MDATA116 Undefined CAN0 message data byte 23 register 16 C0MDATA2316 03FEC302H CAN0 message data byte 2 register 16 C0MDATA216 Undefined 03FEC303H CAN0 message data byte 3 register 16 C0MDATA316 Undefined 03FEC302H 03FEC304H Undefined Undefined CAN0 message data byte 45 register 16 C0MDATA4516 03FEC304H CAN0 message data byte 4 register 16 C0MDATA416 Undefined 03FEC305H CAN0 message data byte 5 register 16 C0MDATA516 Undefined CAN0 message data byte 67 register 16 C0MDATA6716 03FEC306H CAN0 message data byte 6 register 16 C0MDATA616 Undefined 03FEC307H CAN0 message data byte 7 register 16 C0MDATA716 Undefined 03FEC308H CAN0 message data length register 16 C0MDLC16 0000xxxxB 03FEC309H CAN0 message configuration register 16 C0MCONF16 Undefined 03FEC30AH CAN0 message identifier register 16 C0MIDL16 Undefined C0MIDH16 Undefined C0MCTRL16 00x00000 03FEC306H 03FEC30CH 03FEC30EH CAN0 message control register 16 Undefined Undefined 000xx000B 03FEC320H CAN0 message data byte 01 register 17 C0MDATA0117 03FEC320H CAN0 message data byte 0 register 17 C0MDATA017 Undefined 03FEC321H CAN0 message data byte 1 register 17 C0MDATA117 Undefined CAN0 message data byte 23 register 17 C0MDATA2317 03FEC322H CAN0 message data byte 2 register 17 C0MDATA217 03FEC323H CAN0 message data byte 3 register 17 C0MDATA317 CAN0 message data byte 45 register 17 C0MDATA4517 03FEC324H CAN0 message data byte 4 register 17 C0MDATA417 Undefined 03FEC325H CAN0 message data byte 5 register 17 C0MDATA517 Undefined CAN0 message data byte 67 register 17 C0MDATA6717 03FEC326H CAN0 message data byte 6 register 17 C0MDATA617 Undefined 03FEC327H CAN0 message data byte 7 register 17 C0MDATA717 Undefined 03FEC328H CAN0 message data length register 17 C0MDLC17 0000xxxxB 03FEC329H CAN0 message configuration register 17 C0MCONF17 03FEC32AH CAN0 message identifier register 17 C0MIDL17 Undefined C0MIDH17 Undefined C0MCTRL17 00x00000 03FEC322H 03FEC324H 03FEC326H 03FEC32CH 03FEC32EH CAN0 message control register 17 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 880 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (11/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC340H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 18 C0MDATA0118 03FEC340H CAN0 message data byte 0 register 18 C0MDATA018 Undefined 03FEC341H CAN0 message data byte 1 register 18 C0MDATA118 Undefined CAN0 message data byte 23 register 18 C0MDATA2318 03FEC342H CAN0 message data byte 2 register 18 C0MDATA218 Undefined 03FEC343H CAN0 message data byte 3 register 18 C0MDATA318 Undefined 03FEC342H 03FEC344H Undefined Undefined CAN0 message data byte 45 register 18 C0MDATA4518 03FEC344H CAN0 message data byte 4 register 18 C0MDATA418 Undefined 03FEC345H CAN0 message data byte 5 register 18 C0MDATA518 Undefined CAN0 message data byte 67 register 18 C0MDATA6718 03FEC346H CAN0 message data byte 6 register 18 C0MDATA618 Undefined 03FEC347H CAN0 message data byte 7 register 18 C0MDATA718 Undefined 03FEC348H CAN0 message data length register 18 C0MDLC18 0000xxxxB 03FEC349H CAN0 message configuration register 18 C0MCONF18 Undefined 03FEC34AH CAN0 message identifier register 18 C0MIDL18 Undefined C0MIDH18 Undefined C0MCTRL18 00x00000 03FEC346H 03FEC34CH 03FEC34EH CAN0 message control register 18 Undefined Undefined 000xx000B 03FEC360H CAN0 message data byte 01 register 19 C0MDATA0119 03FEC360H CAN0 message data byte 0 register 19 C0MDATA019 Undefined 03FEC361H CAN0 message data byte 1 register 19 C0MDATA119 Undefined CAN0 message data byte 23 register 19 C0MDATA2319 03FEC362H CAN0 message data byte 2 register 19 C0MDATA219 03FEC363H CAN0 message data byte 3 register 19 C0MDATA319 CAN0 message data byte 45 register 19 C0MDATA4519 03FEC364H CAN0 message data byte 4 register 19 C0MDATA419 Undefined 03FEC365H CAN0 message data byte 5 register 19 C0MDATA519 Undefined CAN0 message data byte 67 register 19 C0MDATA6719 03FEC366H CAN0 message data byte 6 register 19 C0MDATA619 Undefined 03FEC367H CAN0 message data byte 7 register 19 C0MDATA719 Undefined 03FEC368H CAN0 message data length register 19 C0MDLC19 0000xxxxB 03FEC369H CAN0 message configuration register 19 C0MCONF19 03FEC36AH CAN0 message identifier register 19 C0MIDL19 Undefined C0MIDH19 Undefined C0MCTRL19 00x00000 03FEC362H 03FEC364H 03FEC366H 03FEC36CH 03FEC36EH CAN0 message control register 19 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 881 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (12/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC380H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 20 C0MDATA0120 03FEC380H CAN0 message data byte 0 register 20 C0MDATA020 Undefined 03FEC381H CAN0 message data byte 1 register 20 C0MDATA120 Undefined CAN0 message data byte 23 register 20 C0MDATA2320 03FEC382H CAN0 message data byte 2 register 20 C0MDATA220 Undefined 03FEC383H CAN0 message data byte 3 register 20 C0MDATA320 Undefined 03FEC382H 03FEC384H Undefined Undefined CAN0 message data byte 45 register 20 C0MDATA4520 03FEC384H CAN0 message data byte 4 register 20 C0MDATA420 Undefined 03FEC385H CAN0 message data byte 5 register 20 C0MDATA520 Undefined CAN0 message data byte 67 register 20 C0MDATA6720 03FEC386H CAN0 message data byte 6 register 20 C0MDATA620 Undefined 03FEC387H CAN0 message data byte 7 register 20 C0MDATA720 Undefined 03FEC388H CAN0 message data length register 20 C0MDLC20 0000xxxxB 03FEC389H CAN0 message configuration register 20 C0MCONF20 Undefined 03FEC38AH CAN0 message identifier register 20 C0MIDL20 Undefined C0MIDH20 Undefined C0MCTRL20 00x00000 03FEC386H 03FEC38CH 03FEC38EH CAN0 message control register 20 Undefined Undefined 000xx000B 03FEC3A0H CAN0 message data byte 01 register 21 C0MDATA0121 03FEC3A0H CAN0 message data byte 0 register 21 C0MDATA021 Undefined 03FEC3A1H CAN0 message data byte 1 register 21 C0MDATA121 Undefined CAN0 message data byte 23 register 21 C0MDATA2321 03FEC3A2H CAN0 message data byte 2 register 21 C0MDATA221 03FEC3A3H CAN0 message data byte 3 register 21 C0MDATA321 CAN0 message data byte 45 register 21 C0MDATA4521 03FEC3A4H CAN0 message data byte 4 register 21 C0MDATA421 Undefined 03FEC3A5H CAN0 message data byte 5 register 21 C0MDATA521 Undefined CAN0 message data byte 67 register 21 C0MDATA6721 03FEC3A6H CAN0 message data byte 6 register 21 C0MDATA621 Undefined 03FEC3A7H CAN0 message data byte 7 register 21 C0MDATA721 Undefined 03FEC3A8H CAN0 message data length register 21 C0MDLC21 0000xxxxB 03FEC3A9H CAN0 message configuration register 21 C0MCONF21 03FEC3AAH CAN0 message identifier register 21 C0MIDL21 Undefined C0MIDH21 Undefined C0MCTRL21 00x00000 03FEC3A2H 03FEC3A4H 03FEC3A6H 03FEC3ACH 03FEC3AEH CAN0 message control register 21 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 882 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (13/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC3C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 22 C0MDATA0122 03FEC3C0H CAN0 message data byte 0 register 22 C0MDATA022 Undefined 03FEC3C1H CAN0 message data byte 1 register 22 C0MDATA122 Undefined CAN0 message data byte 23 register 22 C0MDATA2322 03FEC3C2H CAN0 message data byte 2 register 22 C0MDATA222 Undefined 03FEC3C3H CAN0 message data byte 3 register 22 C0MDATA322 Undefined 03FEC3C2H 03FEC3C4H Undefined Undefined CAN0 message data byte 45 register 22 C0MDATA4522 03FEC3C4H CAN0 message data byte 4 register 22 C0MDATA422 Undefined 03FEC3C5H CAN0 message data byte 5 register 22 C0MDATA522 Undefined CAN0 message data byte 67 register 22 C0MDATA6722 03FEC3C6H CAN0 message data byte 6 register 22 C0MDATA622 Undefined 03FEC3C7H CAN0 message data byte 7 register 22 C0MDATA722 Undefined 03FEC3C8H CAN0 message data length register 22 C0MDLC22 0000xxxxB 03FEC3C9H CAN0 message configuration register 22 C0MCONF22 Undefined 03FEC3CAH CAN0 message identifier register 22 C0MIDL22 Undefined C0MIDH22 Undefined C0MCTRL22 00x00000 03FEC3C6H 03FEC3CCH 03FEC3CEH CAN0 message control register 22 Undefined Undefined 000xx000B 03FEC3E0H CAN0 message data byte 01 register 23 C0MDATA0123 03FEC3E0H CAN0 message data byte 0 register 23 C0MDATA023 Undefined 03FEC3E1H CAN0 message data byte 1 register 23 C0MDATA123 Undefined CAN0 message data byte 23 register 23 C0MDATA2323 03FEC3E2H CAN0 message data byte 2 register 23 C0MDATA223 03FEC3E3H CAN0 message data byte 3 register 23 C0MDATA323 CAN0 message data byte 45 register 23 C0MDATA4523 03FEC3E4H CAN0 message data byte 4 register 23 C0MDATA423 Undefined 03FEC3E5H CAN0 message data byte 5 register 23 C0MDATA523 Undefined CAN0 message data byte 67 register 23 C0MDATA6723 03FEC3E6H CAN0 message data byte 6 register 23 C0MDATA623 Undefined 03FEC3E7H CAN0 message data byte 7 register 23 C0MDATA723 Undefined 03FEC3E8H CAN0 message data length register 23 C0MDLC23 0000xxxxB 03FEC3E9H CAN0 message configuration register 23 C0MCONF23 03FEC3EAH CAN0 message identifier register 23 C0MIDL23 Undefined C0MIDH23 Undefined C0MCTRL23 00x00000 03FEC3E2H 03FEC3E4H 03FEC3E6H 03FEC3ECH 03FEC3EEH CAN0 message control register 23 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 883 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (14/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC400H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 24 C0MDATA0124 03FEC400H CAN0 message data byte 0 register 24 C0MDATA024 Undefined 03FEC401H CAN0 message data byte 1 register 24 C0MDATA124 Undefined CAN0 message data byte 23 register 24 C0MDATA2324 03FEC402H CAN0 message data byte 2 register 24 C0MDATA224 Undefined 03FEC403H CAN0 message data byte 3 register 24 C0MDATA324 Undefined 03FEC402H 03FEC404H Undefined Undefined CAN0 message data byte 45 register 24 C0MDATA4524 03FEC404H CAN0 message data byte 4 register 24 C0MDATA424 Undefined 03FEC405H CAN0 message data byte 5 register 24 C0MDATA524 Undefined CAN0 message data byte 67 register 24 C0MDATA6724 03FEC406H CAN0 message data byte 6 register 24 C0MDATA624 Undefined 03FEC407H CAN0 message data byte 7 register 24 C0MDATA724 Undefined 03FEC408H CAN0 message data length register 24 C0MDLC24 0000xxxxB 03FEC409H CAN0 message configuration register 24 C0MCONF24 Undefined 03FEC40AH CAN0 message identifier register 24 C0MIDL24 Undefined C0MIDH24 Undefined C0MCTRL24 00x00000 03FEC406H 03FEC40CH 03FEC40EH CAN0 message control register 24 Undefined Undefined 000xx000B 03FEC420H CAN0 message data byte 01 register 25 C0MDATA0125 03FEC420H CAN0 message data byte 0 register 25 C0MDATA025 Undefined 03FEC421H CAN0 message data byte 1 register 25 C0MDATA125 Undefined CAN0 message data byte 23 register 25 C0MDATA2325 03FEC422H CAN0 message data byte 2 register 25 C0MDATA225 03FEC423H CAN0 message data byte 3 register 25 C0MDATA325 CAN0 message data byte 45 register 25 C0MDATA4525 03FEC424H CAN0 message data byte 4 register 25 C0MDATA425 Undefined 03FEC425H CAN0 message data byte 5 register 25 C0MDATA525 Undefined CAN0 message data byte 67 register 25 C0MDATA6725 03FEC426H CAN0 message data byte 6 register 25 C0MDATA625 Undefined 03FEC427H CAN0 message data byte 7 register 25 C0MDATA725 Undefined 03FEC428H CAN0 message data length register 25 C0MDLC25 0000xxxxB 03FEC429H CAN0 message configuration register 25 C0MCONF25 03FEC42AH CAN0 message identifier register 25 C0MIDL25 Undefined C0MIDH25 Undefined C0MCTRL25 00x00000 03FEC422H 03FEC424H 03FEC426H 03FEC42CH 03FEC42EH CAN0 message control register 25 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 884 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (15/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC440H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 26 C0MDATA0126 03FEC440H CAN0 message data byte 0 register 26 C0MDATA026 Undefined 03FEC441H CAN0 message data byte 1 register 26 C0MDATA126 Undefined CAN0 message data byte 23 register 26 C0MDATA2326 03FEC442H CAN0 message data byte 2 register 26 C0MDATA226 Undefined 03FEC443H CAN0 message data byte 3 register 26 C0MDATA326 Undefined 03FEC442H 03FEC444H Undefined Undefined CAN0 message data byte 45 register 26 C0MDATA4526 03FEC444H CAN0 message data byte 4 register 26 C0MDATA426 Undefined 03FEC445H CAN0 message data byte 5 register 26 C0MDATA526 Undefined CAN0 message data byte 67 register 26 C0MDATA6726 03FEC446H CAN0 message data byte 6 register 26 C0MDATA626 Undefined 03FEC447H CAN0 message data byte 7 register 26 C0MDATA726 Undefined 03FEC448H CAN0 message data length register 26 C0MDLC26 0000xxxxB 03FEC449H CAN0 message configuration register 26 C0MCONF26 Undefined 03FEC44AH CAN0 message identifier register 26 C0MIDL26 Undefined C0MIDH26 Undefined C0MCTRL26 00x00000 03FEC446H 03FEC44CH 03FEC44EH CAN0 message control register 26 Undefined Undefined 000xx000B 03FEC460H CAN0 message data byte 01 register 27 C0MDATA0127 03FEC460H CAN0 message data byte 0 register 27 C0MDATA027 Undefined 03FEC461H CAN0 message data byte 1 register 27 C0MDATA127 Undefined CAN0 message data byte 23 register 27 C0MDATA2327 03FEC462H CAN0 message data byte 2 register 27 C0MDATA227 03FEC463H CAN0 message data byte 3 register 27 C0MDATA327 CAN0 message data byte 45 register 27 C0MDATA4527 03FEC464H CAN0 message data byte 4 register 27 C0MDATA427 Undefined 03FEC465H CAN0 message data byte 5 register 27 C0MDATA527 Undefined CAN0 message data byte 67 register 27 C0MDATA6727 03FEC466H CAN0 message data byte 6 register 27 C0MDATA627 Undefined 03FEC467H CAN0 message data byte 7 register 27 C0MDATA727 Undefined 03FEC468H CAN0 message data length register 27 C0MDLC27 0000xxxxB 03FEC469H CAN0 message configuration register 27 C0MCONF27 03FEC46AH CAN0 message identifier register 27 C0MIDL27 Undefined C0MIDH27 Undefined C0MCTRL27 00x00000 03FEC462H 03FEC464H 03FEC466H 03FEC46CH 03FEC46EH CAN0 message control register 27 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 885 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (16/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC480H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 28 C0MDATA0128 03FEC480H CAN0 message data byte 0 register 28 C0MDATA028 Undefined 03FEC481H CAN0 message data byte 1 register 28 C0MDATA128 Undefined CAN0 message data byte 23 register 28 C0MDATA2328 03FEC482H CAN0 message data byte 2 register 28 C0MDATA228 Undefined 03FEC483H CAN0 message data byte 3 register 28 C0MDATA328 Undefined 03FEC482H 03FEC484H Undefined Undefined CAN0 message data byte 45 register 28 C0MDATA4528 03FEC484H CAN0 message data byte 4 register 28 C0MDATA428 Undefined 03FEC485H CAN0 message data byte 5 register 28 C0MDATA528 Undefined CAN0 message data byte 67 register 28 C0MDATA6728 03FEC486H CAN0 message data byte 6 register 28 C0MDATA628 Undefined 03FEC487H CAN0 message data byte 7 register 28 C0MDATA728 Undefined 03FEC488H CAN0 message data length register 28 C0MDLC28 0000xxxxB 03FEC489H CAN0 message configuration register 28 C0MCONF28 Undefined 03FEC48AH CAN0 message identifier register 28 C0MIDL28 Undefined C0MIDH28 Undefined C0MCTRL28 00x00000 03FEC486H 03FEC48CH 03FEC48EH CAN0 message control register 28 Undefined Undefined 000xx000B 03FEC4A0H CAN0 message data byte 01 register 29 C0MDATA0129 03FEC4A0H CAN0 message data byte 0 register 29 C0MDATA029 Undefined 03FEC4A1H CAN0 message data byte 1 register 29 C0MDATA129 Undefined CAN0 message data byte 23 register 29 C0MDATA2329 03FEC4A2H CAN0 message data byte 2 register 29 C0MDATA229 03FEC4A3H CAN0 message data byte 3 register 29 C0MDATA329 CAN0 message data byte 45 register 29 C0MDATA4529 03FEC4A4H CAN0 message data byte 4 register 29 C0MDATA429 Undefined 03FEC4A5H CAN0 message data byte 5 register 29 C0MDATA529 Undefined CAN0 message data byte 67 register 29 C0MDATA6729 03FEC4A6H CAN0 message data byte 6 register 29 C0MDATA629 Undefined 03FEC4A7H CAN0 message data byte 7 register 29 C0MDATA729 Undefined 03FEC4A8H CAN0 message data length register 29 C0MDLC29 0000xxxxB 03FEC4A9H CAN0 message configuration register 29 C0MCONF29 03FEC4AAH CAN0 message identifier register 29 C0MIDL29 Undefined C0MIDH29 Undefined C0MCTRL29 00x00000 03FEC4A2H 03FEC4A4H 03FEC4A6H 03FEC4ACH 03FEC4AEH CAN0 message control register 29 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 886 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (17/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC4C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 30 C0MDATA0130 03FEC4C0H CAN0 message data byte 0 register 30 C0MDATA030 Undefined 03FEC4C1H CAN0 message data byte 1 register 30 C0MDATA130 Undefined CAN0 message data byte 23 register 30 C0MDATA2330 03FEC4C2H CAN0 message data byte 2 register 30 C0MDATA230 Undefined 03FEC4C3H CAN0 message data byte 3 register 30 C0MDATA330 Undefined 03FEC4C2H 03FEC4C4H Undefined Undefined CAN0 message data byte 45 register 30 C0MDATA4530 03FEC4C4H CAN0 message data byte 4 register 30 C0MDATA430 Undefined 03FEC4C5H CAN0 message data byte 5 register 30 C0MDATA530 Undefined CAN0 message data byte 67 register 30 C0MDATA6730 03FEC4C6H CAN0 message data byte 6 register 30 C0MDATA630 Undefined 03FEC4C7H CAN0 message data byte 7 register 30 C0MDATA730 Undefined 03FEC4C8H CAN0 message data length register 30 C0MDLC30 0000xxxxB 03FEC4C9H CAN0 message configuration register 30 C0MCONF30 Undefined 03FEC4CAH CAN0 message identifier register 30 C0MIDL30 Undefined C0MIDH30 Undefined C0MCTRL30 00x00000 03FEC4C6H 03FEC4CCH 03FEC4CEH CAN0 message control register 30 Undefined Undefined 000xx000B 03FEC4E0H CAN0 message data byte 01 register 31 C0MDATA0131 03FEC4E0H CAN0 message data byte 0 register 31 C0MDATA031 Undefined 03FEC4E1H CAN0 message data byte 1 register 31 C0MDATA131 Undefined CAN0 message data byte 23 register 31 C0MDATA2331 03FEC4E2H CAN0 message data byte 2 register 31 C0MDATA231 03FEC4E3H CAN0 message data byte 3 register 31 C0MDATA331 CAN0 message data byte 45 register 31 C0MDATA4531 03FEC4E4H CAN0 message data byte 4 register 31 C0MDATA431 Undefined 03FEC4E5H CAN0 message data byte 5 register 31 C0MDATA531 Undefined CAN0 message data byte 67 register 31 C0MDATA6731 03FEC4E6H CAN0 message data byte 6 register 31 C0MDATA631 Undefined 03FEC4E7H CAN0 message data byte 7 register 31 C0MDATA731 Undefined 03FEC4E8H CAN0 message data length register 31 C0MDLC31 0000xxxxB 03FEC4E9H CAN0 message configuration register 31 C0MCONF31 03FEC4EAH CAN0 message identifier register 31 C0MIDL31 Undefined C0MIDH31 Undefined C0MCTRL31 00x00000 03FEC4E2H 03FEC4E4H 03FEC4E6H 03FEC4ECH 03FEC4EEH CAN0 message control register 31 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000xx000B R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 887 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.5.3 Register bit configuration Table 19-17. CAN Global Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FEC000H C0GMCTRL (W) 0 0 0 0 0 0 0 Clear GOM 0 0 0 0 0 0 Set EFSD Set GOM 0 0 0 0 0 0 EFSD GOM MBON 0 0 0 0 0 0 0 CCP0 03FEC001H 03FEC000H C0GMCTRL (R) 03FEC001H 03FEC002H C0GMCS 0 0 0 0 CCP3 CCP2 CCP1 03FEC006H C0GMABT (W) 0 0 0 0 0 0 0 Clear ABTTRG 03FEC007H 03FEC006H 0 C0GMABT (R) 03FEC007H 03FEC008H C0GMABTD R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 0 0 0 0 Set Set ABTCLR ABTTRG 0 0 0 0 0 0 ABTCLR ABTTRG 0 0 0 0 0 0 0 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 Page 888 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-18. CAN Module Register Bit Configuration (1/2) Address 03FEC040H Symbol Bit 7/15 Bit 6/14 Bit 5/13 C0MASK1L 0 0 0 C0MASK2L C0MASK2H CMID23 to CMID16 0 0 0 CMID15 to CMID8 C0MASK3H CMID23 to CMID16 0 0 0 C0MASK4L CMID15 to CMID8 C0CTRL (W) 03FEC051H 03FEC050H CMID23 to CMID16 C0MASK4H 03FEC04FH 03FEC050H CMID28 to CMID24 CMID7 to CMID0 03FEC04DH 03FEC04EH CMID28 to CMID24 CMID7 to CMID0 C0MASK3L 03FEC04BH 03FEC04CH CMID28 to CMID24 CMID7 to CMID0 03FEC049H 03FEC04AH Bit 0/8 CMID15 to CMID8 03FEC047H 03FEC048H Bit 1/9 CMID23 to CMID16 C0MASK1H 03FEC045H 03FEC046H Bit 2/10 CMID15 to CMID8 03FEC043H 03FEC044H Bit 3/11 CMID7 to CMID0 03FEC041H 03FEC042H Bit 4/12 C0CTRL (R) 03FEC051H 0 0 0 0 Clear AL Clear Clear Clear Clear VALID PSMODE PSMODE OPMODE 1 0 2 Set Set CCERC AL CCERC AL 0 VALID CMID28 to CMID24 Set Set Set PSMODE PSMODE OPMODE 1 0 2 Clear Clear OPMODE OPMODE 1 0 Set Set OPMODE OPMODE 1 0 PS PS OP OP OP MODE1 MODE0 MODE2 MODE1 MODE0 0 0 0 0 0 0 RSTAT TSTAT 03FEC052H C0LEC (W) 0 0 0 0 0 0 0 0 03FEC052H C0LEC (R) 0 0 0 0 0 LEC2 LEC1 LEC0 03FEC053H C0INFO 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 03FEC054H C0ERC TEC7 to TEC0 03FEC055H 03FEC056H REC7 to REC0 C0IE (W) 03FEC057H 03FEC056H C0IE (R) 03FEC057H 03FEC058H C0INTS (W) 03FEC059H 03FEC058H 0 C0INTS (R) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Clear Clear Clear Clear Clear Clear CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 0 0 0 0 0 0 0 0 0 0 Clear Clear Clear Clear Clear Clear CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 0 0 0 0 0 0 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 0 0 0 0 0 0 0 0 0 03FEC059H 0 Page 889 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-18. CAN Module Register Bit Configuration (2/2) Address Symbol 03FEC05AH C0BRP 03FEC05CH C0BTR 03FEC05DH 03FEC05EH C0LIPT 03FEC060H C0RGPT (W) Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 TQPRS7 to TQPRS0 0 0 0 0 0 0 SJW1, SJW0 TSEG13 to TSEG10 0 TSEG22 to TSEG20 LIPT7 to LIPT0 0 0 0 0 0 0 0 Clear ROVF 03FEC061H 03FEC060H C0RGPT (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHPM ROVF 0 0 03FEC061H RGPT7 to RGPT0 03FEC062H C0LOPT 03FEC064H C0TGPT (W) LOPT7 to LOPT0 0 0 0 0 0 Clear TOVF 03FEC065H 03FEC064H C0TGPT (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THPM TOVF 03FEC065H 03FEC066H TGPT7 to TGPT0 C0TS (W) 03FEC067H 03FEC066H 0 C0TS (R) 03FEC067H 03FEC068H 0 - 0 0 0 0 0 0 0 0 Clear Clear Clear TSLOCK TSSEL TSEN Set Set Set TSLOCK TSSEL TSEN 0 0 0 0 0 TSLOCK TSSEL TSEN 0 0 0 0 0 0 0 0 Access prohibited (reserved for future use) to 03FEC0FFH R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 890 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-19. Message Buffer Register Bit Configuration Address 03FECxx0H Symbol Bit 7/15 Bit 6/14 Bit 5/13 C0MDATA01m Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 MDLC3 MDLC2 MDLC1 MDLC0 Message data (byte 0) 03FECxx1H Message data (byte 1) 03FECxx0H C0MDATA0m Message data (byte 0) 03FECxx1H C0MDATA1m Message data (byte 1) 03FECxx2H C0MDATA23m Message data (byte 2) 03FECxx3H 03FECxx2H Message data (byte 3) C0MDATA2m Message data (byte 2) 03FECxx3H C0MDATA3m Message data (byte 3) 03FECxx4H C0MDATA45m Message data (byte 4) 03FECxx5H Message data (byte 5) 03FECxx4H C0MDATA4m Message data (byte 4) 03FECxx5H C0MDATA5m Message data (byte 5) 03FECxx6H C0MDATA67m Message data (byte 6) 03FECxx7H Message data (byte 7) 03FECxx6H C0MDATA6m 03FECxx7H C0MDATA7m 03FECxx8H C0MDLCm 03FECxx9H C0MCONFm 03FECxxAH C0MIDLm 03FECxxBH 03FECxxCH C0MIDHm 03FECxxDH 03FECxxEH C0MCTRLm (W) 03FECxxFH 03FECxxEH C0MCTRLm (R) 03FECxxFH 03FECxx0 Message data (byte 6) Message data (byte 7) 0 OWS RTR MT2 MT1 MT0 0 0 MA0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE 0 0 ID28 ID27 ID26 ID25 ID24 0 0 0 Clear Clear Clear Clear Clear MOW IE DN TRQ RDY 0 0 0 0 Set IE 0 Set TRQ Set RDY 0 0 0 MOW IE DN TRQ RDY 0 0 MUC 0 0 0 0 0 - Access prohibited (reserved for future use) to 03FECxxFH Remark m = 00 to 31 xx = 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28, 2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 40, 42, 44, 46, 48, 4A, 4C, 4E R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 891 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.6 Registers Caution Accessing the CAN controller registers is prohibited in the following statuses. For details, refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 892 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (1) CAN0 global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. (1/2) After reset: 0000H R/W Address: 03FEC000H (a) Read C0GMCTRL 15 14 13 12 11 10 9 8 MBON 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 EFSD GOM 15 14 13 12 11 10 9 8 0 0 0 0 0 0 (b) Write C0GMCTRL Set Set EFSD GOM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear GOM (a) Read MBON 0 Bit enabling access to message buffer register, transmit/receive history registers Write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 Write access and read access to the message buffer register and the transmit/receive history list registers is enabled. Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers (C0MDATA0m, C0MDATA1m, C0MDATA01m, C0MDATA2m, C0MDATA3m, C0MDATA23m, C0MDATA4m, C0MDATA5m, C0MDATA45m, C0MDATA6m, C0MDATA7m, C0MDATA67m, C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm, and C0MCTRLm), or registers related to transmit history or receive history (C0LOPT, C0TGPT, C0LIPT, and C0RGPT) is disabled. 2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the MBON bit does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. Remark When the CAN sleep mode/CAN stop mode is entered, or when the GOM bit is cleared to 0, the MBON bit is cleared to 0. When the CAN sleep mode/CAN stop mode is released, or when the GOM bit is set to 1, the MBON bit is set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 893 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) EFSD Bit enabling forced shut down 0 Forced shut down by GOM bit = 0 disabled. 1 Forced shut down by GOM bit = 0 enabled. Caution To request forced shut down, clear the GOM bit to 0 immediately after the EFSD bit has been set to 1. If access to another register (including reading the C0GMCTRL register) is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut down request is invalid. GOM Global operation mode bit 0 CAN module is disabled from operating. 1 CAN module is enabled to operate. Caution The GOM bit is cleared to 0 only in the initialization mode or immediately after the EFSD bit is set to 1. (b) Write Set EFSD EFSD bit setting 0 No change in EFSD bit. 1 EFSD bit set to 1. Set GOM Clear GOM 0 1 GOM bit cleared to 0. 1 0 GOM bit set to 1. Other than above GOM bit setting No change in GOM bit. Caution Be sure to set the GOM bit and EFSD bit separately. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 894 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2) CAN0 global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock. After reset: 0FH R/W C0GMCS Address: 03FEC002H 7 6 5 4 3 2 1 0 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP0 0 0 0 0 fCAN/1 0 0 0 1 fCAN/2 0 0 1 0 fCAN/3 0 0 1 1 fCAN/4 0 1 0 0 fCAN/5 0 1 0 1 fCAN/6 0 1 1 0 fCAN/7 0 1 1 1 fCAN/8 1 0 0 0 fCAN/9 1 0 0 1 fCAN/10 1 0 1 0 fCAN/11 1 0 1 1 fCAN/12 1 1 0 0 fCAN/13 1 1 0 1 fCAN/14 1 1 1 0 fCAN/15 1 1 1 1 fCAN/16 (Default value) Caution Remark CAN module system clock (fCANMOD) Make sure that fXX = 32 to 48 MHz. fCAN = fXX/2 fCAN: CAN clock frequency fXX: Main clock frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 895 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (3) CAN0 global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. (1/2) After reset: 0000H R/W Address: 03FEC006H (a) Read C0GMABT 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ABTCLR ABTTRG 15 14 13 12 11 10 9 8 0 0 0 0 0 0 (b) Write C0GMABT Set Set ABTCLR ABTTRG 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the C0GMABT register to the default value (0000H). After setting, confirm that the C0GMABT register is initialized to 0000H. (a) Read ABTCLR Automatic block transmission engine clear status bit 0 Clearing the automatic transmission engine is completed. 1 The automatic transmission engine is being cleared. Remarks 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1. 2. When the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the ABTCLR bit is automatically cleared to 0 as soon as the requested clearing processing is complete. ABTTRG Automatic block transmission status bit 0 Automatic block transmission is stopped. 1 Automatic block transmission is under execution. Cautions 1. Do not set the ABTTRG bit to 1 in the initialization mode. If the ABTTRG bit is set to 1 in the initialization mode, the operation is not guaranteed after the CAN module has entered the normal operation mode with ABT. 2. Do not set the ABTTRG bit to 1 while the C0CTRL.TSTAT bit is set to 1. Directly confirm that the TSTAT bit = 0 before setting the ABTTRG bit to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 896 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set ABTCLR Automatic block transmission engine clear request bit 0 The automatic block transmission engine is in idle status or under operation. 1 Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1. Set ABTTRG Clear Automatic block transmission start bit ABTTRG 0 1 Request to stop automatic block transmission. 1 0 Request to start automatic block transmission. Other than above No change in ABTTRG bit. Caution Even if the ABTTRG bit is set (1), transmission is not immediately executed, depending on the situation such as when a message is received from another node or when a message other than the ABT message (message buffers 8 to 31) is transmitted. Even if the ABTTRG bit is cleared (0), transmission is not terminated midway. If transmission is under execution, it is continued until completed (regardless of whether transmission is successful or fails). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 897 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (4) CAN0 global automatic block transmission delay register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H C0GMABTD R/W Address: 03FEC008H 7 6 5 4 3 2 1 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 Data frame interval during automatic block transmission ABTD3 ABTD2 ABTD1 ABTD0 0 0 0 0 0 DBT (default value) 0 0 0 1 2 DBT 0 0 1 0 2 DBT 0 0 1 1 2 DBT 0 1 0 0 2 DBT 0 1 0 1 2 DBT 0 1 1 0 2 DBT 0 1 1 1 2 DBT 1 0 0 0 2 DBT Other than above (Unit: Data bit time (DBT)) 5 6 7 8 9 10 11 12 Setting prohibited Cautions 1. Do not change the contents of the C0GMABTD register while the ABTTRG bit is set to 1. 2. The timing at which the ABT message is actually transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message (message buffers 8 to 31) is made. 3. Be sure to set bits 4 to 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 898 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (5) CAN0 module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages in the same message buffer by masking part of the identifier (ID) of a message and invalidating the ID comparison of the masked part. (1/2) * CAN0 module mask 1 register (C0MASK1L, C0MASK1H) After reset: Undefined C0MASK1L C0MASK1H * R/W Address: C0MASK1L 03FEC040H, C0MASK1H 03FEC042H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CAN0 module mask 2 register (C0MASK2L, C0MASK2H) After reset: Undefined C0MASK2L C0MASK2H R/W Address: C0MASK2L 03FEC044H, C0MASK2H 03FEC046H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 899 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) * CAN0 module mask 3 register (C0MASK3L, C0MASK3H) After reset: Undefined C0MASK3L Address: C0MASK3L 03FEC048H, C0MASK3H 03FEC04AH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 C0MASK3H * R/W CAN0 module mask 4 register (C0MASK4L, C0MASK4H) After reset: Undefined C0MASK4L R/W 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 C0MASK4H CMID28 to CMID0 0 Address: C0MASK4L 03FEC04CH, C0MASK4H 03FEC04EH Mask pattern setting of ID bit The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with the ID bits of the received message frame. 1 The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared with the ID bits of the received message frame (they are masked). Caution Be sure to set bits 13 to 15 of the C0MASKaH register to 0. Remark Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message with a standard ID, the CMID17 to CMID0 bits are ignored. Therefore, only the CMID28 to CMID18 bits of the received ID are masked. The same mask can be used for both the standard and extended IDs. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 900 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (6) CAN0 module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. (1/4) After reset: 0000H R/W Address: 03FEC050H (a) Read C0CTRL 15 14 13 12 11 10 9 8 0 0 0 0 0 0 RSTAT TSTAT 7 6 5 4 3 2 1 0 CCERC AL VALID PSMODE PSMODE OPMODE OPMODE OPMODE 1 0 2 1 0 12 11 10 9 8 (b) Write C0CTRL 15 14 13 0 Set Set Set Set Set PSMODE 1 PSMODE 0 OPMODE 2 OPMODE 1 OPMODE 0 4 3 2 1 0 Set Set CCERC AL 7 6 0 Clear Clear Clear Clear Clear Clear Clear AL VALID PSMODE 1 PSMODE 0 OPMODE 2 OPMODE 1 OPMODE 0 5 (a) Read RSTAT Reception status bit 0 Reception is stopped. 1 Reception is in progress. Remark * The RSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a receive frame is detected * On occurrence of arbitration loss during a transmit frame * The RSTAT bit is cleared to 0 under the following conditions (timing) * When a recessive level is detected at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space TSTAT Transmission status bit 0 Transmission is stopped. 1 Transmission is in progress. Remark * The TSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a transmit frame is detected * The TSTAT bit is cleared to 0 under the following conditions (timing) * During transition to bus-off status * On occurrence of arbitration loss in transmit frame * On detection of recessive level at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 901 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/4) CCERC Error counter clear bit 0 The C0ERC and C0INFO registers are not cleared in the initialization mode. 1 The C0ERC and C0INFO registers are cleared in the initialization mode. Remarks 1. The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or forced recovery from the bus-off status. This bit can be set to 1 only in the initialization mode. 2. When the C0ERC and C0INFO registers have been cleared, the CCERC bit is also cleared to 0 automatically. 3. The CCERC bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. If the CCERC bit is set to 1 immediately after the INIT mode is entered in the self test mode, the receive data may be corrupted. AL Bit to set operation in case of arbitration loss 0 Re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 Re-transmission is executed in case of an arbitration loss in the single-shot mode. Remark The AL bit is valid only in the single-shot mode. VALID Valid receive message frame detection bit 0 A valid message frame has not been received since the VALID bit was last cleared to 0. 1 A valid message frame has been received since the VALID bit was last cleared to 0. Remarks 1. Detection of a valid receive message frame is not dependent upon the existence or non-existence of the storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. Clear the VALID bit (0) before changing the initialization mode to an operation mode. 3. If only two CAN nodes are connected to the CAN bus with one transmitting a message frame in the normal mode and the other in the receive-only mode, since no ACK is generated in the receiveonly mode, the VALID bit is not set to 1 before the transmitting node enters the error passive status. 4. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is cleared. If it is not cleared, perform clearing processing again. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 902 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (3/4) PSMODE1 PSMODE0 Power save mode 0 0 No power save mode is selected. 0 1 CAN sleep mode 1 0 Setting prohibited 1 1 CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored. 2. After releasing the power save mode, the C0GMCTRL.MBON flag must be checked before accessing the message buffer again. 3. A request for transition to the CAN sleep mode is held pending until it is canceled by software or until the CAN bus enters the bus idle state. The software can check transition to the CAN sleep mode by reading the PSMODE0 and PSMODE1 bits. OPMODE2 OPMODE1 OPMODE0 Operation mode 0 0 0 No operation mode is selected (CAN module is in the initialization mode). 0 0 1 Normal operation mode 0 1 0 Normal operation mode with automatic block transmission function (normal operation mode with ABT) 0 1 1 Receive-only mode 1 0 0 Single-shot mode 1 0 1 Self-test mode Other than above Setting prohibited Caution It may take time to change the mode to the initialization mode or power save mode. Therefore, be sure to check if the mode has been successfully changed, by reading the register value before executing the processing. Remark The OPMODE0 to OPMODE2 bits are read-only in the CAN sleep mode or CAN stop mode. (b) Write Set CCERC 1 Setting of CCERC bit CCERC bit is set to 1. Other than above CCERC bit is not changed. Set AL Clear AL 0 1 AL bit is cleared to 0. 1 0 AL bit is set to 1. Other than above Setting of AL bit AL bit is not changed. Clear VALID Setting of VALID bit 0 VALID bit is not changed. 1 VALID bit is cleared to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 903 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (4/4) Set PSMODE0 Clear PSMODE0 0 1 PSMODE0 bit is cleared to 0. 1 0 PSMODE bit is set to 1. Other than above Setting of PSMODE0 bit PSMODE0 bit is not changed. Set PSMODE1 Clear PSMODE1 0 1 PSMODE1 bit is cleared to 0. 1 0 PSMODE1 bit is set to 1. Other than above Setting of PSMODE1 bit PSMODE1 bit is not changed. Set OPMODE0 Clear OPMODE0 0 1 OPMODE0 bit is cleared to 0. 1 0 OPMODE0 bit is set to 1. Other than above Setting of OPMODE0 bit OPMODE0 bit is not changed. Set OPMODE1 Clear OPMODE1 0 1 OPMODE1 bit is cleared to 0. 1 0 OPMODE1 bit is set to 1. Other than above Setting of OPMODE1 bit OPMODE1 bit is not changed. Set OPMODE2 Clear OPMODE2 0 1 OPMODE2 bit is cleared to 0. 1 0 OPMODE2 bit is set to 1. Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Setting of OPMODE2 bit OPMODE2 bit is not changed. Page 904 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (7) CAN0 module last error information register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H R/W C0LEC Address: 03FEC052H 7 6 5 4 3 2 1 0 0 0 0 0 0 LEC2 LEC1 LEC0 LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0 0 Bit error. (The CAN module tried to transmit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the CAN bus is a dominant-level bit.) Bit error. (The CAN module tried to transmit a dominant-level bit as part of a 1 0 1 transmit message, ACK bit, error frame, or overload frame, but the value on the 1 1 0 CRC error 1 1 1 Undefined CAN bus is a recessive-level bit.) Caution Be sure to set bits 3 to 7 to "0". Remarks 1. The contents of the C0LEC register are not cleared when the CAN module changes from an operation mode to the initialization mode. 2. If an attempt is made to write a value other than 00H to the C0LEC register by software, the access is ignored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 905 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (8) CAN0 module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H C0INFO R Address: 03FEC053H 7 6 5 4 3 2 1 0 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off status bit 0 Not bus-off status (transmit error counter 255). (The value of the transmit counter is less than 256.) 1 Bus-off status (transmit error counter > 255). (The value of the transmit error counter is 256 or more.) TECS1 TECS0 Transmission error counter status bit 0 0 The value of the transmission error counter is less than that of the warning level (< 96). 0 1 The value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the transmission error counter is in the range of the error passive or bus-off status ( 128). RECS1 RECS0 Reception error counter status bit 0 0 The value of the reception error counter is less than that of the warning level (< 96). 0 1 The value of the reception error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the reception error counter is in the error passive range ( 128). Caution Be sure to set bits 5 to 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 906 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (9) CAN0 module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. After reset: 0000H C0ERC R Address: 03FEC054H 15 14 13 12 11 10 9 8 REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REPS Reception error passive status bit 0 The value of the reception error counter is not error passive (< 128) 1 The value of the reception error counter is in the error passive range ( 128) REC6 to REC0 0 to 127 Reception error counter bit Number of reception errors. These bits reflect the status of the reception error counter. The number of errors is defined by the CAN protocol. Remark The REC6 to REC0 bits of the reception error counter are invalid in the reception error passive status (C0INFO.RECS1, C0INFO.RECS0 bit = 11B). TEC7 to TEC0 0 to 255 Transmission error counter bit Number of transmission errors. These bits reflect the status of the transmission error counter. The number of errors is defined by the CAN protocol. Remark The TEC7 to TEC0 bits of the transmission error counter are invalid in the bus-off status (C0INFO.BOFF bit = 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 907 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (10) CAN0 module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. (1/2) After reset: 0000H R/W Address: 03FEC056H (a) Read C0IE 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 15 14 13 12 11 10 9 8 0 0 (b) Write C0IE Set Set Set Set Set Set CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 7 6 5 4 3 2 1 0 0 0 Clear Clear Clear Clear Clear Clear CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 (a) Read CIE5 to CIE0 CAN module interrupt enable bit 0 Output of the interrupt corresponding to interrupt status register CINTSx is disabled. 1 Output of the interrupt corresponding to interrupt status register CINTSx is enabled. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 908 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set CIE5 Clear CIE5 0 1 CIE5 bit is cleared to 0. 1 0 CIE5 bit is set to 1. Other than above Setting of CIE5 bit CIE5 bit is not changed. Set CIE4 Clear CIE4 0 1 CIE4 bit is cleared to 0. 1 0 CIE4 bit is set to 1. Other than above Setting of CIE4 bit CIE4 bit is not changed. Set CIE3 Clear CIE3 0 1 CIE3 bit is cleared to 0. 1 0 CIE3 bit is set to 1. Other than above Setting of CIE3 bit CIE3 bit is not changed. Set CIE2 Clear CIE2 0 1 CIE2 bit is cleared to 0. 1 0 CIE2 bit is set to 1. Other than above Setting of CIE2 bit CIE2 bit is not changed. Set CIE1 Clear CIE1 0 1 CIE1 bit is cleared to 0. 1 0 CIE1 bit is set to 1. Other than above Setting of CIE1 bit CIE1 bit is not changed. Set CIE0 Clear CIE0 0 1 CIE0 bit is cleared to 0. 1 0 CIE0 bit is set to 1. Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Setting of CIE0 bit CIE0 bit is not changed. Page 909 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (11) CAN0 module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module. After reset: 0000H R/W Address: 03FEC058H (a) Read C0INTS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 (b) Write C0INTS Clear Clear Clear Clear Clear Clear CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (a) Read CINTS5 to CAN interrupt status bit CINTS0 0 No related interrupt source event is generated. 1 A related interrupt source event is generated. Interrupt status Related interrupt source event bit Note CINTS5 Wakeup interrupt from CAN sleep mode CINTS4 Arbitration loss interrupt CINTS3 CAN protocol error interrupt CINTS2 CAN error status interrupt CINTS1 Interrupt on completion of reception of valid message frame to message buffer m CINTS0 Interrupt on normal completion of transmission of message frame from message buffer m Note The CINTS5 bit is set (1) only when the CAN module is woken up from the CAN sleep mode by a CAN bus operation. The CINTS5 bit is not set (1) when the CAN sleep mode has been released by software. (b) Write Clear Setting of CINTS5 to CINTS0 bits CINTS5 to CINTS0 0 CINTS5 to CINTS0 bits are not changed. 1 CINTS5 to CINTS0 bits are cleared to 0. Caution The status bit of this register is not automatically cleared. Clear it (0) by software if each status must be checked in the interrupt servicing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 910 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (12) CAN0 module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer base clock (fTQ). The communication baud rate is set to the C0BTR register. After reset: FFH C0BRP R/W Address: 03FEC05AH 7 6 5 4 3 2 1 0 TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 TQPRS7 to TQPRS0 CAN protocol layer base system clock (fTQ) 0 fCANMOD/1 1 fCANMOD/2 n fCANMOD/(n + 1) : : 255 fCANMOD/256 (default value) Figure 19-23. CAN Module Clock CAN0 global clock selection register (C0GMCS) 0 0 0 0 CCP3 CCP2 CCP1 CCP0 fCANMOD fCAN Prescaler Baud rate generator fTQ CAN0 bit-rate register (C0BTR) TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 CAN0 module bit-rate prescaler register (C0BRP) Remark fCAN: CAN clock frequency fCANMOD: CAN module system clock frequency fTQ: CAN protocol layer base system clock frequency Caution The C0BRP register can be write-accessed only in the initialization mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 911 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (13) CAN0 module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. Figure 19-24. Data Bit Time Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Phase segment 2 Time segment 2 (TSEG2) Sample point (SPT) Page 912 of 1442 V850ES/JC3-H, V850ES/JE3-H After reset: 370FH C0BTR R/W CHAPTER 19 CAN CONTROLLER Address: 03FEC05CH 15 14 13 12 11 10 9 8 0 0 SJW1 SJW0 0 TSEG22 TSEG21 TSEG20 7 6 5 4 3 2 1 0 0 0 0 0 TSEG13 TSEG12 TSEG11 TSEG10 SJW1 SJW0 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ (default value) TSEG22 TSEG21 TSEG20 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ (default value) TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 Setting prohibited 0 0 0 1 2TQ 0 0 1 0 3TQ 0 0 1 1 4TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1 0 7TQ 0 1 1 1 8TQ 1 0 0 0 9TQ 1 0 0 1 10TQ 1 0 1 0 11TQ 1 0 1 1 12TQ 1 1 0 0 13TQ 1 1 0 1 14TQ 1 1 1 0 15TQ 1 1 1 1 16TQ (default value) Note Length of synchronization jump width Length of time segment 2 Length of time segment 1 Note Note This setting must not be made when the C0BRP register = 00H. Remark TQ = 1/fTQ (fTQ: CAN protocol layer base system clock) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 913 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (14) CAN0 module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined C0LIPT Address: 03FEC05EH 7 6 5 4 3 2 1 0 LIPT7 LIPT6 LIPT5 LIPT4 LIPT3 LIPT2 LIPT1 LIPT0 LIPT7 to LIPT0 0 to 31 R Last in-pointer register (C0LIPT) When the C0LIPT register is read, the contents of the element indexed by the last in-pointer (LIPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. Remark The read value of the C0LIPT register is undefined if a data frame or a remote frame has never been stored in the message buffer. If the C0RGPT.RHPM bit is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the C0LIPT register is undefined. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 914 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (15) CAN0 module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list. (1/2) After reset: xx02H R/W Address: 03FEC060H (a) Read C0RGPT 15 14 13 12 11 10 9 8 RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RHPM ROVF 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 (b) Write C0RGPT Clear ROVF (a) Read RGPT7 to RGPT0 0 to 31 Receive history list read pointer When the C0RGPT register is read, the contents of the element indexed by the receive history list get pointer (RGPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. RHPM Note 1 Receive history list pointer match 0 The receive history list has at least one message buffer number that has not been read. 1 The receive history list has no message buffer numbers that have not been read. Note 2 ROVF 0 Receive history list overflow bit All the message buffer numbers that have not been read are preserved. All the numbers of the message buffers in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 At least 23 entries have been stored since the host processor serviced the RHL last time (i.e. read C0RGPT). The first 22 entries are sequentially stored whereas the last entry might have been overwritten by newly received messages a number of times because all buffer numbers are stored at position LIPT-1 when the ROVF bit is set to 1. As a consequence receptions cannot be completely recovered in the order that they were received. Notes 1. The read value of the RGPT0 to RGPT7 bits is invalid when the RHPM bit = 1. 2. If all the receive history is read by the C0RGPT register while the ROVF bit is set (1), the RHPM bit is not cleared (0) but kept set (1) even if newly received data is stored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 915 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Clear ROVF Setting of ROVF bit 0 ROVF bit is not changed. 1 ROVF bit is cleared to 0. (16) CAN0 module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. After reset: Undefined C0LOPT R Address: C0LOPT 03FEC062H, C1LOPT 03FEC662H 7 6 5 4 3 2 1 0 LOPT7 LOPT6 LOPT5 LOPT4 LOPT3 LOPT2 LOPT1 LOPT0 LOPT7 to LOPT0 0 to 31 Last out-pointer of transmit history list (LOPT) When the C0LOPT register is read, the contents of the element indexed by the last out-pointer (LOPT) of the receive history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Remark The value read from the C0LOPT register is undefined if a data frame or remote frame has never been transmitted from a message buffer. If the C0TGPT.THPM bit is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the C0LOPT register is undefined. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 916 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (17) CAN0 module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. (1/2) After reset: xx02H R/W Address: 03FEC064H (a) Read C0TGPT 15 14 13 12 11 10 9 8 TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 THPM TOVF 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 (b) Write C0TGPT Clear TOVF (a) Read TGPT7 to TGPT0 0 to 31 Transmit history list read pointer When the C0TGPT register is read, the contents of the element indexed by the read pointer (TGPT) of the transmit history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Note 1 THPM Transmit history pointer match 0 The transmit history list has at least one message buffer number that has not been read. 1 The transmit history list has no message buffer numbers that have not been read. Note 2 TOVF 0 Transmit history list overflow bit All the message buffer numbers that have not been read are preserved. All the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). 1 At least 7 entries have been stored since the host processor serviced the THL last time (i.e. read C0TGPT). The first 6 entries are sequentially stored whereas the last entry might have been overwritten by newly transmitted messages a number of times because all buffer numbers are stored at position LOPT-1 when TOVF bit is set to 1. As a consequence receptions cannot be completely recovered in the order that they were received. Notes 1. The read value of the TGPT0 to TGPT7 bits is invalid when the THPM bit = 1. 2. If all the transmit history is read by the C0TGPT register while the TOVF bit is set (1), the THPM bit is not cleared (0) but kept set (1), even if transmission of new data has been completed. Remark Transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with ABT. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 917 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Clear TOVF Setting of TOVF bit 0 TOVF bit is not changed. 1 TOVF bit is cleared to 0. (18) CAN0 module time stamp register (C0TS) The C0TS register is used to control the time stamp function. (1/2) After reset: 0000H R/W Address: 03FEC066H (a) Read C0TS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 TSLOCK TSSEL TSEN 15 14 13 12 11 10 9 8 0 0 0 0 0 (b) Write C0TS Remark 7 6 5 4 3 0 0 0 0 0 Set Set Set TSLOCK TSSEL TSEN 2 1 0 Clear Clear Clear TSLOCK TSSEL TSEN The lock function of the time stamp functions must not be used when the CAN module is in the normal operation mode with ABT. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 918 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) (a) Read TSLOCK Time stamp lock function enable bit Time stamp lock function stopped. 0 The TSOUT signal toggles each time the selected time stamp capture event occurs. Time stamp lock function enabled. 1 The TSOUT signal toggled each time the selected time stamp capture event occurred. However, the TSOUT output signal is locked when a data frame has been correctly received to message buffer 0 Note . Note The TSEN bit is automatically cleared to 0. TSSEL Time stamp capture event selection bit 0 The time stamp capture event is SOF. 1 The time stamp capture event is the last bit of EOF. TSEN TSOUT operation setting bit 0 TSOUT toggle operation is disabled. 1 TSOUT toggle operation is enabled. Remark The TSOUT signal is output from the CAN controller to a timer. For details, refer to CHAPTER 7 16-BIT TIMER/EVENT COUNTER A (TAA). (b) Write Set TSLOCK Clear TSLOCK 0 1 TSLOCK bit is cleared to 0. 1 0 TSLOCK bit is set to 1. Other than above Setting of TSLOCK bit TSLOCK bit is not changed. Set TSSEL Clear TSSEL 0 1 TSSEL bit is cleared to 0. 1 0 TSSEL bit is set to 1. Other than above Set TSEN Clear TSEN 0 1 1 0 Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Setting of TSSEL bit TSSEL bit is not changed. Setting of TSEN bit TSEN bit is cleared to 0. TSEN bit is set to 1. TSEN bit is not changed. Page 919 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (19) CAN0 message data byte register (C0MDATAxm, C0MDATAym) (x = 0 to 7, y = 01, 23, 45, 67) The C0MDATAxm register is used to store the data of a transmit/receive message, and can be accessed in 8-bit unit. The C0MDATAxm register can be accessed in 16-bit units by the C0MDATAym register. (1/2) After reset: Undefined C0MDATA01m C0MDATA0m C0MDATA1m C0MDATA23m C0MDATA2m C0MDATA3m R/W Address: See Table 19-16. 15 14 13 12 11 10 9 8 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 7 6 5 4 3 2 1 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 920 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) C0MDATA45m C0MDATA4m C0MDATA5m C0MDATA67m C0MDATA6m C0MDATA7m 15 14 13 12 11 10 9 8 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 7 6 5 4 3 2 1 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 921 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (20) CAN0 message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB C0MDLCm R/W Address: See Table 19-16. 7 6 5 4 3 2 1 0 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 MDLC3 MDLC2 MDLC1 MDLC0 Data length of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 Setting prohibited 1 0 1 0 (If these bits are set during transmission, 8-byte data is transmitted 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 regardless of the set DLC value when a data frame is transmitted. However, the DLC actually transmitted to the CAN bus is the DLC Note value set to this register.) Note The data and DLC value actually transmitted to CAN bus are as follows. Type of transmit frame Length of transmit data Number of bytes specified by DLC Data frame DLC transmitted MDLC3 to MDLC0 bits (However, 8 bytes if DLC 8) Remote frame 0 bytes Cautions 1. Be sure to set bits 7 to 4 to 0000B. 2. Receive data is stored in as many C0MDATAxm register as the number of bytes (however, the upper limit is 8) corresponding to DLC of receive frame. The C0MDATAxm register in which no data is stored is undefined. 3. Be sure to set bits 4 to 7 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 922 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (21) CAN0 message configuration register m (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. (1/2) After reset: Undefined C0MCONFm R/W Address: See Table 19-16. 7 6 5 4 3 2 1 0 OWS RTR MT2 MT1 MT0 0 0 MA0 OWS Overwrite control bit Note The message buffer 0 that has already received a data frame is not overwritten by a newly received data frame. The newly received data frame is discarded. The message buffer that has already received a data frame is overwritten by a newly received data 1 frame. Note The "message buffer that has already received a data frame" is a receive message buffer whose the C0MCTRLm.DN bit has been set to 1. Remark A remote frame is received and stored, regardless of the setting of the OWS and DN bits. A remote frame that satisfies the other conditions (ID matches, the RTR bit = 0, the C0MCTRLm.TRQ bit = 0) is always received and stored in the corresponding message buffer (interrupt generated, DN flag set, the C0MDLCm.MDLC0 to C0MDLCm.MDLC3 bits updated, and recorded to the receive history list). RTR Remote frame request bit 0 Transmit a data frame. 1 Transmit a remote frame. Note Note The RTR bit specifies the type of message frame that is transmitted from a message buffer defined as a transmit message buffer. Even if a valid remote frame has been received, the RTR bit of the transmit message buffer that has received the frame remains cleared to 0. Even if a remote frame whose ID matches has been received from the CAN bus with the RTR bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, DN flag set, the MDLC0 to MDLC3 bits updated, and recorded to the receive history list). MT2 MT1 MT0 0 0 0 Transmit message buffer 0 0 1 Receive message buffer (no mask setting) 0 1 0 Receive message buffer (mask 1 set) 0 1 1 Receive message buffer (mask 2 set) 1 0 0 Receive message buffer (mask 3 set) 1 0 1 Receive message buffer (mask 4 set) Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Message buffer type setting bit Setting prohibited Page 923 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/2) MA0 Message buffer assignment bit 0 Message buffer not used. 1 Message buffer used. Caution Be sure to set bits 2 and 1 to "0". (22) CAN0 message ID register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). After reset: Undefined C0MIDLm C0MIDHm R/W Address: See Table 19-16. 15 14 13 12 11 10 9 8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13 12 11 10 9 8 IDE 0 0 ID28 ID27 ID26 ID25 ID24 7 6 5 4 3 2 1 0 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE Format mode specification bit Note 0 Standard format mode (ID28 to ID18: 11 bits) 1 Extended format mode (ID28 to ID0: 29 bits) Note The ID17 to ID0 bits are not used. ID28 to ID0 Message ID ID28 to ID18 Standard ID value of 11 bits (when IDE = 0) ID28 to ID0 Extended ID value of 29 bits (when IDE = 1) Cautions 1. Be sure to write 0 to bits 14 and 13 of the C0MIDHm register. 2. Be sure to arrange the ID values to be registered in accordance with the bit positions of this register. For the standard ID, shift the bit positions of ID28 to ID18 of the ID value. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 924 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (23) CAN0 message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. (1/3) After reset: R/W Address: See Table 19-16. 00x000000 000xx000B (a) Read C0MCTRLm 15 14 13 12 11 10 9 8 0 0 MUC 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 MOW IE DN TRQ RDY 15 14 13 12 11 10 9 8 0 0 0 0 Set 0 (b) Write C0MCTRLm IE 7 6 5 0 0 0 Set Set TRQ RDY 4 3 2 1 0 Clear Clear Clear Clear Clear MOW IE DN TRQ RDY (a) Read Note MUC Bit indicating that message buffer data is being updated 0 The CAN module is not updating the message buffer (reception and storage). 1 The CAN module is updating the message buffer (reception and storage). Note The MUC bit is undefined until the first reception and storage is performed. MOW Message buffer overwrite status bit 0 The message buffer is not overwritten by a newly received data frame. 1 The message buffer is overwritten by a newly received data frame. Remark The MOW bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with the DN bit = 1. IE 0 Message buffer interrupt request enable bit Receive message buffer: Valid message reception completion interrupt disabled. Transmit message buffer: Normal message transmission completion interrupt disabled. 1 Receive message buffer: Valid message reception completion interrupt enabled. Transmit message buffer: Normal message transmission completion interrupt enabled. DN Message buffer data update bit 0 A data frame or remote frame is not stored in the message buffer. 1 A data frame or remote frame is stored in the message buffer. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 925 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2/3) TRQ Message buffer transmission request bit 0 No message frame transmitting request that is pending or being transmitted is in the message buffer. 1 The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Caution Do not set the TRQ bit and RDY bit to 1 at the same time. Be sure to set the RDY bit to 1 before setting the TRQ bit to 1. RDY Message buffer ready bit 0 The message buffer can be written by software. The CAN module cannot write to the message buffer. 1 Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW bits). The CAN module can write to the message buffer. Cautions 1. Do not clear the RDY bit (0) during message transmission. Follow transmission abort procedures in order to clear the RDY bit for redefinition. 2. If the RDY bit is not cleared (0) even when the processing to clear it is executed, execute the clearing processing again. 3. Confirm, by reading the RDY bit again, that the RDY bit has been cleared (0) before writing data to the message buffer. However, it is unnecessary to confirm that the TRQ or RDY bit has been set (1) or that the DN or MOW bit has been cleared (0). (b) Write Clear MOW Setting of MOW bit 0 MOW bit is not changed. 1 MOW bit is cleared to 0. Set IE Clear IE 0 1 IE bit is cleared to 0. 1 0 IE bit is set to 1. Other than above Setting of IE bit IE bit is not changed. Caution Be sure to set the IE and RDY bits separately. Clear DN Setting of DN bit 1 DN bit is cleared to 0. 0 DN bit is not changed. Caution Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 926 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (3/3) Set TRQ Clear TRQ 0 1 TRQ bit is cleared to 0. 1 0 TRQ bit is set to 1. Other than above Setting of TRQ bit TRQ bit is not changed. Caution Even if the TRQ bit is set (1), transmission may not be immediately executed depending on the situation such as when a message is received from another node or when a message is transmitted from the message buffer. Transmission under execution is not terminated midway even if the TRQ bit is cleared. Transmission is continued until it is completed (regardless of whether it is executed successfully or fails). Set RDY Clear RDY 0 1 RDY bit is cleared to 0. 1 0 RDY bit is set to 1. Other than above Setting of RDY bit RDY bit is not changed. Caution Be sure to set the TRQ and RDY bits separately. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 927 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. * CAN0 global control register (C0GMCTRL) * CAN0 global automatic block transmission control register (C0GMABT) * CAN0 module control register (C0CTRL) * CAN0 module interrupt enable register (C0IE) * CAN0 module interrupt status register (C0INTS) * CAN0 module receive history list register (C0RGPT) * CAN0 module transmit history list register (C0TGPT) * CAN0 module time stamp register (C0TS) * CAN0 message control register (C0MCTRLm) Remark m = 00 to 31 All the 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 19-25 below to set or clear the lower 8 bits in these registers. Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in Figure 19-26). Figure 19-25 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Figure 19-25. Example of Bit Setting/Clearing Operations 1 1 0 1 0 0 0 1 Write value 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 set 0 0 0 0 1 0 1 1 clear 1 1 0 1 1 0 0 0 Register's value after write operation R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 0 0 0 0 0 0 0 Set 0 Set 0 No change 0 No change 0 Clear 0 No change 0 Clear 0 Clear 0 Bit status Register's current value 0 0 0 0 0 0 0 1 1 Page 928 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-26. Bit Status After Bit Setting/Clearing Operations 15 14 13 12 11 10 9 Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Remark 8 7 6 5 4 3 2 1 0 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0 Set n Clear n Status of bit n after bit set/clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change n = 0 to 7 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 929 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.8 CAN Controller Initialization 19.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the C0GMCS.CCP0 to C0GMCS.CCP3 bits by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled. The CAN module is enabled by setting the C0GMCTRL.GOM bit. For the procedure of initializing the CAN module, see 19.16 Operation of CAN Controller. 19.8.2 Initialization of message buffer After the CAN module is enabled, the message buffers contain undefined values. A minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the CAN module from the initialization mode to one of the operation modes. * Clear the C0MCTRLm.RDY, C0MCTRLm.TRQ, and C0MCTRLm.DN bits to 0. * Clear the C0MCONFm.MA0 bit to 0. Remark m = 00 to 31 19.8.3 Redefinition of message buffer Redefining a message buffer means changing the ID and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) To redefine message buffer in initialization mode Place the CAN module in the initialization mode once and then change the ID and control information of the message buffer in the initialization mode. After changing the ID and control information, set the CAN module to an operation mode. (2) To redefine message buffer during reception Perform redefinition as shown in Figure 19-39. (3) To redefine message buffer during transmission To rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see 19.10.4 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT), 19.10.4 (2) Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT)). Confirm that transmission has been aborted or completed, and then redefine the message buffer. After redefining the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 930 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition Redefinition completed Execute transmission? No Yes Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer. If the procedure in Figure 19-39 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). If this happens, check that the ID and IDE received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. If no ID and IDE are stored after redefinition, redefine the message buffer again. 2. When a message is transmitted, the transmission priority is checked in accordance with the ID, IDE, and RTR bits set to each transmit message buffer to which a transmission request was set. The transmit message buffer having the highest priority is selected for transmission. If the procedure in Figure 19-27 is not observed, a message with an ID not having the highest priority may be transmitted after redefinition. 19.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. * Normal operation mode * Normal operation mode with ABT * Receive-only mode * Single-shot mode * Self-test mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 931 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H and CAN bus is busy. OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode with ABT] OPMODE[2:0]=02H OPMODE[2:0] = 03H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 04H OPMODE[2:0] = 02H OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode] OPMODE[2:0]=01H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 01H [Single-shot mode] OPMODE[2:0]=04H OPMODE[2:0] = 00H and interframe space INIT mode OPMODE[2:0] = 00H OPMODE[2:0] = 05H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and CAN bus is busy. [Self-test mode] OPMODE[2:0]=05H GOM = 1 All CAN modules are in INIT mode and GOM = 0 EFSD = 1 and GOM = 0 CAN module channel invalid RESET released RESET The transition from the initialization mode to an operation mode is controlled by the C0CTRL.OPMODE2 to C0CTRL.OPMODE0 bits. Changing from one operation mode into another requires shifting to the initialization mode in between. Do not change one operation mode to another directly; otherwise the operation will not be guaranteed. Requests for transition from an operation mode to the initialization mode are held pending when the CAN bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the CAN module enters the initialization mode at the first bit in the interframe space (the values of the OPMODE2 to OPMODE0 bits are changed to 000B). After issuing a request to change the mode to the initialization mode, read the OPMODE2 to OPMODE0 bits until their values become 000B to confirm that the module has entered the initialization mode (see Figure 19-37). 19.8.5 Resetting error counter C0ERC of CAN module If it is necessary to reset the C0ERC and C0INFO registers when re-initialization or forced recovery from the bus-off status is made, set the C0CTRL.CCERC bit to 1 in the initialization mode. When this bit is set to 1, the C0ERC and C0INFO registers are cleared to their default values. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 932 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9 Message Reception 19.9.1 Message reception All buffers satisfying the following conditions are searched in all the message buffer areas in all the operation modes in order to store newly receive messages. * Used as a message buffer (C0MCONFm.MA0 bit is set to 1.) * Set as a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits are set to 001B, 010B, 011B, 100B, or 101B.) * Ready for reception (C0MCTRLm.RDY bit is set to 1.) Remark m = 00 to 31 When two or more message buffers of the CAN module receive a message, the message is stored according to the priority explained below. The message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. For example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same ID, the received message is not stored in the message buffer linked to mask 1 that has not received a message, even if a message has already been received in the unmasked receive message buffer. In other words, when a condition has been set to store a message in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. This also applies when the message buffer with the highest priority is unable to receive and store a message (i.e., when the DN bit = 1 indicating that a message has already been received, but rewriting is disabled because the OWS bit = 0). In this case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. Priority 1 (high) Storing Condition If Same ID Is Set Unmasked message buffer DN bit = 0 DN bit = 1 and OWS bit = 1 2 Message buffer linked to mask 1 DN bit = 0 3 Message buffer linked to mask 2 DN bit = 0 DN bit = 1 and OWS bit = 1 DN bit = 1 and OWS bit = 1 4 Message buffer linked to mask 3 DN bit = 0 DN bit = 1 and OWS bit = 1 5 (low) Message buffer linked to mask 4 DN bit = 0 DN bit = 1 and OWS bit = 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 933 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9.2 Reading reception data If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended procedures shown in Figures 19-49 and 19-50. While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the processing to store data in the message buffer and at the end of this storing processing. During this storing processing, the C0MCTRLm.MUC bit of the message buffer is set (1) (refer to Figure 19-29). Before the data is completely stored, the receive history list is written. During this data storing period (MUC bit = 1), the CPU is prohibited from rewriting the C0MCTRLm.RDY bit of the message buffer in which the data is to be stored. Completion of this data storing processing may be delayed by a CPU's access to any message buffer. Remark m = 0 to 31 Figure 19-29. DN and MUC Bit Setting Period (in Standard ID Format) (11) R0 (1) IDE ID RTR SOF CAN standard ID format (1) (1) (1) Recessive DLC DATA0-DATA7 CRC (4) (0-64) (16) ACK EOF (2) IFS Dominant (7) Message stored DATA, DLC, ID Message buffer DN bit MUC bit C0INTS.CINTS1 bit INTC0REC signal Operation of CAN controller R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 The DN and MUC bits are set (1) at the same time. The DN bit is set (1) and the MUC bit is cleared (0) at the same time. Page 934 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register. The RHL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The C0LIPT register holds the contents of the RHL element indicated by the value of the LIPT pointer minus 1. By reading the C0LIPT register, therefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. The LIPT pointer is utilized as a write pointer that indicates to what part of the RHL a message buffer number is recorded. Any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the RHL element indicated by the LIPT pointer. Each time recording to the RHL has been completed, the LIPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL. This pointer indicates the first RHL element that the CPU has not read yet. By reading the C0RGPT register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. Each time a message buffer number is read from the C0RGPT register, the RGPT pointer is automatically incremented. If the value of the RGPT pointer matches the value of the LIPT pointer, the C0RGPT.RHPM bit (receive history list pointer match) is set to 1. This indicates that no message buffer number that has not been read remains in the RHL. If a new message buffer number is recorded, the LIPT pointer is incremented and because its value no longer matches the value of the RGPT pointer, the RHPM bit is cleared. In other words, the numbers of the unread message buffers exist in the RHL. If the LIPT pointer is incremented and matches the value of the RGPT pointer minus 1, the C0RGPT.ROVF bit (receive history list overflow) is set to 1. This indicates that the RHL is full of numbers of message buffers that have not been read. When further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the new message. After the ROVF bit has been set to 1, the recorded message buffer numbers in the RHL do not completely reflect chronological order. However the messages themselves are not lost and can be located by a CPU search in the message buffer memory with the help of the DN bit. Caution Even if the receive history list overflows (C0RGPT.ROVF bit = 1), the receive history can be read until no more history is left unread and the C0RGPT.RHPM bit is set (1). However, the ROVF bit is kept set (1) (= overflow occurs) until cleared (0) by software. In this status, the RHPM bit is not cleared (0), unless the ROVF bit is cleared (0), even if a new receive history is stored and written to the list. If ROVF bit = 1 and RHPM bit = 1 and the receive history list overflows, therefore, the RHPM bit indicates that no more history is left unread even if new history is received and stored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 935 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without the RHL being read by the host processor, a complete sequence of receptions can not be recovered. Figure 19-30. Receive History List Receive history list (RHL) Receive history list (RHL) 23 22 : : : Last inmessage pointer (LIPT) 7 6 5 4 3 2 1 0 23 22 Event: - Message buffer 6, 9, 2, and 7 are read by host processor. - Newly received messages are stored in message buffer 3, 4, and 8. Message buffer 7 Message buffer 2 Message buffer 9 Message buffer 6 Receive history list get pointer (RGPT) : : : Last inmessage pointer (LIPT) 7 6 5 4 3 2 1 0 Message buffer 1 Message buffer 9 : : : Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 6 Message buffer 11 Message buffer 10 ROVF bit = 1 LIPT is blocked Message buffer 8 Message buffer 4 Message buffer 3 Receive history list get pointer (RGPT) Event: - 20 other messages are received. Message buffer 6 carries last received message. - Upon reception in message buffer 6, RHL is full. - ROVF bit is set to 1. Receive history list (RHL) 23 22 7 6 5 4 3 2 1 0 Last inmessage pointer (LIPT) Receive history list (RHL) 23 22 Event: - Reception in message buffer 13, 14, and 15 occurs. - Overflow situation occurs. Receive history list get pointer (RGPT) Last inmessage pointer (LIPT) 7 6 5 4 3 2 1 0 Message buffer 1 Message buffer 9 : : : Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 15 Message buffer 11 Message buffer 10 Receive history list get pointer (RGPT) ROVF bit = 1 LIPT is blocked ROVF bit = 1 denotes that LIPT equals RGPT - 1 while message buffer number stored to element indicated by LIPT - 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 936 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9.4 Mask function For some message buffers that are used for reception, whether one of four global reception masks is applied can be selected. Load resulting from comparing message identifiers is reduced by masking some bits, and, as a result, some different identifiers can be received in a buffer. By using the mask function, the identifier of a message received from the CAN bus can be compared with the identifier set to a message buffer in advance. Regardless of whether the masked ID is set to 0 or 1, the received message can be stored in the defined message buffer. While the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. However, this comparison is performed for any bit whose value is defined as 0 by the mask. For example, let us assume that all messages that have a standard-format ID, in which bits ID27 to ID25 are 0 and bits ID24 and ID22 are 1, are to be stored in message buffer 14. The procedure for this example is shown below. <1> Identifier to be stored in message buffer ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x Remark x = don't care <2> Identifier to be configured in message buffer 14 (example) (Using C0MIDL14 and C0MIDH14 registers) ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x x x x ID6 ID5 ID4 ID3 ID2 ID1 ID0 x x x x x x x ID with the ID27 to ID25 bits cleared to 0 and the ID24 and ID22 bits set to 1 is registered (initialized) to message buffer 14. Remark x = don't care Remark Message buffer 14 is set as a standard format identifier that is linked to mask 1 (C0MCONF14.MT2 to C0MCONF14.MT0 bits are set to 010B). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 937 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASK1L and C1MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 1: Not compared (masked) 0: Compared The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to CMID0 bits are set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 938 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type. These message buffers can be allocated in any area in the message buffer memory, and they are not necessarily to be allocated adjacent to each other. Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is received, it is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting the message buffer. When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time a message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. Even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-ID data. Whether a data block has been received and stored can be checked by setting the C0MCTRLm.IE bit of each message buffer. For example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the IE bit in message buffer k-1 is set to 1 (interrupts enabled). In this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that MBRB has become full. Alternatively, by clearing the IE bit of message buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a warning that MBRB is about to overflow can be issued. The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions of storing data in a single message buffer. Cautions 1. MBRB can be configured for each of the same message buffer types. Therefore, even if a message buffer of another MBRB whose ID matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the message buffer having the highest number in the MBRB configuration, a newly received message will no longer be stored in the message buffer in the order from the lowest message buffer number. 3. MBRB operates based on the reception and storage conditions; there are no settings dedicated to MBRB, such as function enable bits. By setting the same message buffer type and ID to two or more message buffers, MBRB is automatically configured. 4. With MBRB, "matching ID" means "matching ID after mask". Even if the ID set to each message buffer is not the same, if the ID that is masked by the mask register matches, it is considered a matching ID and the buffer that has this ID is treated as the storage destination of a message. 5. Priority among each MBRB conforms to the priority shown in 19.9.1 Message reception. Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 939 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. * Used as a message buffer (C0MCONFm.MA0 bit set to 1.) * Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B) * Ready for reception (C0MCTRLm.RDY bit set to 1.) * Set to transmit message (C0MCONFm.RTR bit is cleared to 0.) * Transmission request is not set. (C0MCTRLm.TRQ bit is set to 0.) Upon acceptance of a remote frame, the following actions are executed if the ID of the received remote frame matches the ID of a message buffer that satisfies the above conditions. * The C0MDLCm.DLC3 to C0MDLCm.DLC0 bits store the received DLC value. * The C0MDATA0m to C0MDATA7m registers in the data area are not updated (data before reception is saved). * The C0MCTRLm.DN bit is set to 1. * The C0INTS.CINTS1 bit is set to 1 (if the C0MCTRLm.IE bit of the message buffer that receives and stores the frame is set to 1). * The receive completion interrupt (INTC0REC) is output (if the IE bit of the message buffer that receives and stores the frame is set to 1 and if the C0IE.CIE1 bit is set to 1). * The message buffer number is recorded in the receive history list. Caution When a message buffer is searched for receiving and storing a remote frame, overwrite control by the C0MCONFm.OWS bit of the message buffer and the DN bit are not affected. The setting of the OWS bit is ignored and the DN bit is set to 1 in every case. If more than one transmit message buffer has the same ID and the ID of the received remote frame matches that ID, the remote frame is stored in the transmit message buffer with the lowest message buffer number. Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 940 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.10 Message Transmission 19.10.1 Message transmission In all the operation modes, if the C0MCTRLm.TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. * Used as a message buffer (C0MCONFm.MA0 bit set to 1.) * Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B.) * Ready for transmission (C0MCTRLm.RDY bit is set to 1.) Remark m = 00 to 31 The CAN system is a multi-master communication system. In a system like this, the priority of message transmission is determined based on message identifiers (IDs). To facilitate transmission processing by software when there are several messages awaiting transmission, the CAN module uses hardware to check the ID of the message with the highest priority and automatically identifies that message. This eliminates the need for software-based priority control. Transmission priority is controlled by the identifier (ID). Figure 19-31. Message Processing Example Message No. Message waiting to be transmitted 0 1 ID = 120H 2 ID = 229H 3 4 5 ID = 223H 6 ID = 023H The CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3. Message 8 4. Message 5 5. Message 2 7 8 ID = 123H 9 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 941 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER After the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted. If a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. If the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. To solve this reversal of priorities, software can request that transmission of a message of low priority be stopped. The highest priority is determined according to the following rules. Priority 1 (high) Conditions Value of first 11 bits of ID [ID28 to ID18]: Description The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than a message frame with a 29-bit extended ID. 2 Frame type A data frame with an 11-bit standard ID (C0MCONFm.RTR bit is cleared to 0) has a higher priority than a remote frame with a standard ID and a message frame with an extended ID. 3 ID type A message frame with a standard ID (C0MIDHm.IDE bit is cleared to 0) has a higher priority than a message frame with an extended ID. 4 Value of lower 18 bits of ID If one or more transmission-pending extended ID message frame has equal [ID17 to ID0]: values in the first 11 bits of the ID and the same frame type (equal RTR bit values), the message frame with the lowest value in the lower 18 bits of its extended ID is transmitted first. 5 (low) Message buffer number If two or more message buffers request transmission of message frames with the same ID, the message from the message buffer with the lowest message buffer number is transmitted first. Remarks 1. If the automatic block transmission request bit C0GMABT.ABTTRG bit is set to 1 in the normal operation mode with ABT, the TRQ bit is set to 1 only for one message buffer in the ABT message buffer group. If the ABT mode was triggered by the ABTTRG bit (1), one TRQ bit is set to 1 in the ABT area (buffers 0 to 7). In addition to this TRQ bit, the application can request transmissions (set TRQ bit to 1) for other TXmessage buffers that do not belong to the ABT area. In that case an internal arbitration process (TXsearch) evaluates all of the TX-message buffers with the TRQ bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. If there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted first. Upon successful transmission of a message frame, the following operations are performed. - The TRQ bit of the corresponding transmit message buffer is automatically cleared to 0. - The transmission completion status bit CINTS0 of the C0INTS register is set to 1 (if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). - An interrupt request signal INTC0TRX is output (if the C0IE.CIE0 bit is set to 1 and if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). 2. Before changing the contents of the transmit message buffer, the RDY flag of this buffer must be cleared. Since the RDY flag may be temporarily locked while the internal processing is changed, it is necessary to check the status of the RDY flag by software after changing the buffer contents. 3. m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 942 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register. The THL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The C0LOPT register holds the contents of the THL element indicated by the value of the LOPT pointer minus 1. By reading the C0LOPT register, therefore, the number of the message buffer that transmitted a data frame or remote frame first can be checked. The LOPT pointer is utilized as a write pointer that indicates to what part of the THL a message buffer number is recorded. Any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the THL element indicated by the LOPT pointer. Each time recording to the THL has been completed, the LOPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The TGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the THL. This pointer indicates the first THL element that the CPU has not yet read. By reading the C0TGPT register by software, the number of a message buffer that has completed transmission can be read. Each time a message buffer number is read from the C0TGPT register, the TGPT pointer is automatically incremented. If the value of the TGPT pointer matches the value of the LOPT pointer, the C0TGPT.THPM bit (transmit history list pointer match) is set to 1. This indicates that no message buffer numbers that have not been read remain in the THL. If a new message buffer number is recorded, the LOPT pointer is incremented and because its value no longer matches the value of the TGPT pointer, the THPM bit is cleared. In other words, the numbers of the unread message buffers exist in the THL. If the LOPT pointer is incremented and matches the value of the TGPT pointer minus 1, the TOVF bit (transmit history list overflow) of the C0TGPT register is set to 1. This indicates that the THL is full of message buffer numbers that have not been read. If a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that received and stored the new message. After the TOVF bit has been set (1), therefore, the recorded message buffer numbers in the THL do not completely reflect chronological order. However the transmitted messages can be found by a CPU search applied to all transmit message buffers unless the CPU has not overwritten a transmit object in one of these buffers beforehand. In total up to six transmission completions can occur without overflowing the THL. Caution Even if the transmit history list overflows (C0TGPT.TOVF bit = 1), the transmit history can be read until no more history is left unread and the C0TGPT.THPM bit is set (1). However, the TOVF bit is kept set (1) (= overflow occurs) until cleared (0) by software. In this status, the THPM bit is not cleared (0), unless the TOVF bit is cleared (0), even if a new transmit history is stored and written to the list. If the TOVF bit = 1 and the THPM bit = 1 and the receive history list overflows, therefore, the THPM bit indicates that no more history is left unread even if new history is received and stored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 943 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-32. Transmit History List Transmit history list (THL) Transmit history list (THL) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Event: Message buffer Message buffer Message buffer Message buffer 7 2 9 6 - CPU confirms Tx completion of message buffer 6, 9, and 2. - Tx completion of message buffer 3, and 4. Transmit history list get pointer (TGPT) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Message buffer 4 Message buffer 3 Message buffer 7 Transmit history list get pointer (TGPT) Event: - Message buffer 8, 5, 6, and 10 completes transmission. - THL is full. - TOVF bit is set to 1. Transmit history list (THL) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Message buffer Message buffer Message buffer Message buffer Message buffer 5 8 4 3 7 Message buffer 10 Message buffer 6 TOVF bit = 1 LOPT is blocked Transmit history list (THL) Event: - Message buffer 11, 13, and 14 completes transmission. - Overflow situation occurs. Transmit history list get pointer (TGPT) 7 6 5 4 3 2 1 0 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Last outMessage buffer 14 message Message buffer 6 pointer (LOPT) TOVF bit = 1 LOPT is blocked Transmit history list get pointer (TGPT) TOVF bit = 1 denotes that LOPT equals TGPT - 1 while message buffer number stored to element indicated by LOPT - 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 944 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7). By setting the C0CTRL.OPMODE2 to C0CTRL.OPMODE0 bits to 010B, "normal operation mode with automatic block transmission function" (hereafter referred to as ABT mode) can be selected. To issue an ABT transmission request, define the message buffers by software first. Set the C0MCONFm.MA0 bit (1) in all the message buffers used for ABT, and define all the buffers as transmit message buffers by setting the C0MCONFm.MT2 to C0MCONFm.MT0 bits to 000B. Be sure to set the ID for the message buffers for ATB for each message buffer, even when that ID is being used for all the message buffers. To use two or more IDs, set the ID of each message buffer by using the C0MIDLm and C0MIDHm registers. Set the C0MDLCm and C0MDATA0m to C0MDATA7m registers before issuing a transmission request for the ABT function. After initialization of message buffers for ABT is finished, the C0MCTRLm.RDY bit needs to be set (1). In the ABT mode, the C0MCTRLm.TRQ bit does not have to be manipulated by software. After the data for the ABT message buffers has been prepared, set the C0GMABT.ABTTRG bit to 1. Automatic block transmission is then started. When ABT is started, the TRQ bit in the first message buffer (message buffer 0) is automatically set to 1. After transmission of the data of message buffer 0 is finished, the TRQ bit of the next message buffer, message buffer 1, is set automatically. In this way, transmission is executed successively. A delay time can be inserted by program in the interval in which the transmission request (TRQ bit) is automatically set while successive transmission is being executed. The delay time to be inserted is defined by the C0GMABTD register. The unit of the delay time is DBT (data bit time). DBT depends on the setting of the C0BRP and C0BTR registers. During ABT, the priority of the transmission ID is not searched in the ABT transmit message buffer. The data of message buffers 0 to 7 is sequentially transmitted. When transmission of the data frame from message buffer 7 has been completed, the ABTTRG bit is automatically cleared to 0 and the ABT operation is finished. If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that buffer, ABT is stopped, and the ABTTRG bit is cleared. After that, transmission can be resumed from the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not resume transmission from the message buffer where ABT stopped, the internal ABT engine can be reset by setting the C0GMABT.ABTCLR bit to 1 while ABT mode is stopped and the ABTTRG bit is cleared to 0. In this case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the ABTTRG bit is set to 1. An interrupt can be used to check if data frames have been transmitted from all the message buffers for ABT. To do so, the C0MCTRLm.IE bit of each message buffer except the last message buffer needs to be cleared (0). If a transmit message buffer other than those used by the ABT function (message buffers 8 to 31) is assigned to a transmit message buffer, the priority of the message to be transmitted is determined by the priority of the transmission message buffer of the ABT message buffer whose transmission is currently held pending and the transmission message buffer of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 945 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed. 2. Whether the automatic block transmission engine is cleared by setting the ABTCLR bit to 1 can be confirmed if the ABTCLR bit is automatically cleared to 0 immediately after the processing of the clearing request is completed. 3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the ABT mode. 4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode with ABT. Otherwise, the operation is not guaranteed. 5. The C0GMABTD register is used to set the delay time that is inserted in the period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when the transmission requests are set in the order of message numbers for each message for ABT that is successively transmitted in the ABT mode. The timing at which the messages are actually transmitted onto the CAN bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the ABT messages (message buffers 8 to 31). 6. If a transmission request is made for a message other than an ABT message and if no delay time is inserted in the interval in which transmission requests for ABT are automatically set (C0GMABTD register = 00H), messages other than ABT messages may be transmitted regardless of their priority in regards to the ABT message. 7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1. 8. If a message is received from another node in the normal operation mode with ABT, the message may be transmitted after the time of one frame has elapsed even when C0GMABTD register = 00H. Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 946 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.10.4 Transmission abort process Remark m = 00 to 31 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT) The user can clear the C0MCTRLm.TRQ bit to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the C0CTRL.TSTAT bit and the C0TGPT register, which indicate the transmission status on the CAN bus (for details, refer to the processing in Figure 19-46). (2) Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT) The user can clear the C0GMABT.ABTTRG bit to 0 to abort a transmission request. After checking the ABTTRG bit of the C0GMABT register = 0, clear the C0MCTRLm.TRQ bit to 0. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked by using the C0CTRL.TSTAT bit and the C0TGPT register, which indicate the transmission status on the CAN bus (for details, refer to the process in Figure 19-47). (3) Transmission abort in normal operation mode with automatic block transmission (ABT) To abort ABT that is already started, clear the C0GMABT.ABTTRG bit to 0. In this case, the ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. This aborts ABT. If the last transmission (before ABT) was successful, the normal operation mode with ABT is left with the internal ABT pointer pointing to the next message buffer to be transmitted. In the case of an erroneous transmission, the position of the internal ABT pointer depends on the status of the TRQ bit in the last transmitted message buffer. If the TRQ bit is set to 1 when clearing the ABTTRG bit is requested, the internal ABT pointer points to the last transmitted message buffer (for details, refer to the process in Figure 19-48 (a)). If the TRQ bit is cleared to 0 when clearing the ABTTRG bit is requested, the internal ABT pointer is increased in increments of 1 and indicates the next message buffer in the ABT area (for details, refer to the process in Figure 19-48 (b)). Caution Be sure to abort ABT by clearing the ABTTRG bit to 0. The operation is not guaranteed if aborting transmission is requested by clearing RDY. When the normal operation mode with ABT is resumed after ABT has been aborted and the ABTTRG bit is set to 1, the next ABT message buffer to be transmitted can be determined from the following table. Status of TRQ of ABT Message Buffer Set (1) Cleared (0) Abort After Successful Transmission Abort After Erroneous Transmission Next message buffer in the ABT area Note Same message buffer in the ABT area Next message buffer in the ABT area Note Next message buffer in the ABT area Note Note The above resumption operation can be performed only if a message buffer ready for ABT exists in the ABT area. For example, an abort request that is issued while ABT of message buffer 7 is in progress is regarded as completion of ABT, rather than abort, if transmission of message buffer 7 has been successfully completed, even if the ABTTRG bit is cleared to 0. If the C0MCTRLm.RDY bit in the next message buffer in the ABT area is cleared to 0, the internal ABT pointer is retained, but the resumption operation is not performed even if the ABTTRG bit is set to 1, and ABT ends immediately. Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 947 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.10.5 Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the C0MCONFm.RTR bit. Setting (1) the RTR bit sets remote frame transmission. Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 948 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.11 Power Saving Modes 19.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered. In the CAN sleep mode, the CAN module does not transmit messages, even when transmission requests are issued or pending. (1) Entering CAN sleep mode The CPU issues a CAN sleep mode transition request by writing 01B to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits. This transition request is only acknowledged only under the following conditions. (i) The CAN module is already in one of the following operation modes * * * * * * Normal operation mode Normal operation mode with ABT Receive-only mode Single-shot mode Self-test mode CAN stop mode in all the above operation modes Note (ii) The CAN bus state is bus idle (the 4th bit in the interframe space is recessive) Note If the CAN bus is fixed to dominant, the request for transition to the CAN sleep mode is held pending. Also the transition from CAN stop mode to CAN sleep mode is independent of the CAN bus state. (iii) No transmission request is pending If any one of the conditions mentioned above is not met, the CAN module will operate as follows. * If the CAN sleep mode is requested from the initialization mode, the CAN sleep mode transition request is ignored and the CAN module remains in the initialization mode. * If the CAN bus state is not bus idle (i.e., the CAN bus state is either transmitting or receiving) when the CAN sleep mode is requested in one of the operation modes, immediate transition to the CAN sleep mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive). In the time from the CAN sleep mode request to successful transition, the PSMODE1 and PSMODE0 bits remain 00B. When the module has entered the CAN sleep mode, the PSMODE1 and PSMODE0 bits are set to 01B. * If a request for transition to the initialization mode and a request for transition to the CAN sleep mode are made at the same time while the CAN module is in one of the operation modes, the request for the initialization mode is enabled. The CAN module enters the initialization mode at a predetermined timing. At this time, the CAN sleep mode request is not held pending and is ignored. * Even when the initialization mode and sleep mode are not requested simultaneously (i.e the first request was not granted when a second request was made), the request for initialization has priority over the CAN sleep mode request. The CAN sleep mode request is cancelled when the initialization mode is requested. When a pending request for the initialization mode is present, a subsequent request for the CAN sleep mode request is cancelled right at the point in time when it was submitted. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 949 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER (2) Status in CAN sleep mode The CAN module is in one of the following states after it enters the CAN sleep mode. * The internal operating clock is stopped and the power consumption is minimized. * The function to detect the falling edge of the CAN reception pin (CRXD0) remains in effect to wake up the CAN module from the CAN bus. * To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but nothing can be written to other CANn module registers or bits. * The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers. * The CAN0 message buffer registers cannot be written or read. * C0GMCTRL.MBON bit is cleared to 0. * A request for transition to the initialization mode is not acknowledged and is ignored. (3) Releasing CAN sleep mode The CAN sleep mode is released by the following events. * When the CPU writes 00B to the PSMODE1 and PSMODE0 bits * A falling edge at the CAN reception pin (CRXD0) (i.e. the CAN bus level shifts from recessive to dominant) Cautions1. Even if the falling edge belongs to the SOF of a receive message, this message will not be received and stored. If the CPU has turned off the clock to the CAN while the CAN was in sleep mode, later on the CAN sleep mode will not be released and PSMODE[1:0] bits will continue to be 01B unless the clock for the CAN is provided again. In addition to this, the receive message will not be received afterwards. Caution2. If a falling edge is detected at the CAN reception pin (CRXD0) while the CAN clock is supplied, the PSMODE0 bit must be cleared by software. (For details, refer to the processing in Figure 1953.) After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode was requested and the PSMODE1 and PSMODE0 bits are reset to 00B. If the CAN sleep mode is released by a change in the CAN bus state, the C0INTS.CINTS5 bit is set to 1, regardless of the C0IE.CIE bit. After the CAN module is released from the CAN sleep mode, it participates in the CAN bus again by automatically detecting 11 consecutive recessive-level bits on the CAN bus. After releasing the sleep mode and before accessing the message buffer by application again, confirm that C0GMCTRL.MBON bit = 1. When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode, that request is ignored; the CPU has to be released from sleep mode by software first before entering the initialization mode. Caution When the CAN sleep mode is released by an event of the CAN bus, a wakeup interrupt occurs even if the event of the CAN bus occurs immediately after the mode has been changed to the sleep mode. Note that the interrupt can occur at any time. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 950 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode. The CAN stop mode can only be released (shifting to CAN sleep mode) by writing 01B to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits and not by a change in the CAN bus state. No message is transmitted even when transmission requests are issued or pending. (1) Entering CAN stop mode A CAN stop mode transition request is issued by writing 11B to the PSMODE1 and PSMODE0 bits. A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode. In all other modes, the request is ignored. Caution To set the CAN module to the CAN stop mode, the module must be in the CAN sleep mode. To confirm that the module is in the sleep mode, check that the PSMODE1 and PSMODE0 bits = 01B, and then request the CAN stop mode. If a bus change occurs at the CAN reception pin (CRXD0) while this process is being performed, the CAN sleep mode is automatically released. In this case, the CAN stop mode transition request cannot be acknowledged (while the CAN clock is supplied, however, the PSMODE0 must be cleared by software after the bus level of the CAN reception pin (CRXD0) is changed). (2) Status in CAN stop mode The CAN module is in one of the following states after it enters the CAN stop mode. * The internal operating clock is stopped and the power consumption is minimized. * To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but nothing can be written to other CAN0 module registers or bits. * The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers. * The CAN0 message buffer registers cannot be written or read. * The C0GMCTRL.MBON bit is cleared to 0. * An initialization mode transition request is not acknowledged and is ignored. (3) Releasing CAN stop mode The CAN stop mode can only be released by writing 01B to the PSMODE1 and PSMODE0 bits. After releasing the CAN stop mode, the CAN module enters the CAN sleep mode. When the initialization mode is requested while the CAN module is in the CAN stop mode, that request is ignored; the CPU has to release the stop mode and subsequently the CAN sleep mode before entering into initialization mode. It is impossible to enter another operation mode directly from the CAN stop mode without entering the CAN sleep mode, the request will be ignored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 951 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus. Here is an example of using the power saving modes. First, put the CAN module in the CAN sleep mode (PSMODE1, PSMODE0 bits = 01B). Next, put the CPU in the power saving mode. If an edge transition from recessive to dominant is detected at the CRXD0 signal in this status, the CINTS5 bit in the CAN module is set to 1. If the C0CTRL.CIE5 bit is set to 1, a wakeup interrupt (INTC0WUP) is generated. The CAN module is automatically released from the CAN sleep mode (PSMODE1, PSMODE0 bits = 00B) and returns to normal operation mode (while the CAN clock is supplied, however, the PSMODE0 must be cleared by software after a bus level change is detected at the CAN reception pin (CRXD0).). The CPU, in response to INTC0WUP, can release its own power saving mode and return to normal operation mode. To further reduce the power consumption of the CPU, the internal clocks, including that of the CAN module, may be tuned off. In this case, the operating clock supplied to the CAN module is turned off after the CAN module is put in the CAN sleep mode. Then the CPU enters a power saving mode in which the clock supplied to the CPU is turned off. If an edge transition from recessive to dominant is detected at the CRXD0 signal in this status, the CAN module can set the CINTS5 bit to 1 and generate a wakeup interrupt (INTC0WUP) even if it is not supplied with a clock. The other functions, however, do not operate because the clock supply to the CAN module is shut off, and the module remains in the CAN sleep mode. The CPU, in response to INTC0WUP, releases its power saving mode, resumes supply of the internal clocks, including the clock to the CAN module, after oscillation stabilization time has elapsed, and starts instruction execution. The CAN module is immediately released from the CAN sleep mode when the clock supply is resumed, and returns to normal operation mode (PSMODE1, PSMODE0 bits = 00B). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 952 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. Table 19-20. List of CAN Module Interrupt Sources No. Interrupt Status Bit Name 1 Note 1 CINTS0 Register C0INTS Interrupt Enable Bit Name Note 1 CIE0 Register C0IE Interrupt Interrupt Source Description Request Signal INTC0TRX Message frame successfully transmitted from message buffer m Note 1 Note 1 2 CINTS1 C0INTS CIE1 C0IE INTC0REC Valid message frame reception in message buffer m 3 CINTS2 C0INTS CIE2 C0IE INTC0ERR CAN module error state interrupt 4 CINTS3 C0INTS CIE3 C0IE CAN module protocol error interrupt 5 CINTS4 C0INTS CIE4 C0IE CAN module arbitration loss interrupt 6 CINTS5 C0INTS CIE5 C0IE Note 2 Note 3 INTC0WUP CAN module wakeup interrupt from CAN sleep mode Note 4 Notes 1. The C0MCTRL.IE bit (message buffer interrupt enable bit) of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. 2. This interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 3. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs. 4. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a falling edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant). Remark m = 00 to 31 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 953 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 19.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes. For example, this mode can be used for automatic baud-rate detection. The baud rate in the CAN module is changed until "valid reception" is detected, so that the baud rates in the module match ("valid reception" means a message frame has been received in the CAN protocol layer without occurrence of an error and with an appropriate ACK between nodes connected to the CAN bus). A valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). The event of valid reception is indicated by setting the C0CTRL.VALID bit (1). Figure 19-33. CAN Module Terminal Connection in Receive-Only Mode CAN macro Tx Fixed to the recessive level CTXD0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Rx CRXD0 Page 954 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pending. In the receive-only mode, the CAN transmission pin (CTXD0) in the CAN module is fixed to the recessive level. Therefore, no active error flag can be transmitted from the CAN module to the CAN bus even when a CAN bus error is detected while receiving a message frame. Since no transmission can be issued from the CAN module, the transmission error counter the C0ERC.TEC7 to C0ERC.TEC0 bits are never updated. Therefore, a CAN module in the receive-only mode does not enter the bus-off state. Furthermore, ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus. Caution If only two CAN nodes are connected to the CAN bus and one of them is operating in the receive-only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. The transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). When the message frame is transmitted for the 17th time, the transmitting node generates a passive error flag. The receiving node in the receive-only mode detects the first valid message frame at this point, and the VALID bit is set to 1 for the first time. 19.13.2 Single-shot mode In the single-shot mode, automatic re-transmission as defined in the CAN protocol is switched off. (According to the CAN protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) All other behavior of single-shot mode is identical to normal operation mode. Features of single-shot mode can not be used in combination with normal mode with ABT. The single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the C0CTRL.AL bit. When the AL bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. If the AL bit is set to 1, re-transmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. As a consequence, the C0MCTRLm.TRQ bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events. * Successful transmission of the message frame * Arbitration loss while sending the message frame (AL bit = 0) * Error occurrence while sending the message frame The events arbitration loss and error occurrence can be distinguished by checking the C0INTS.CINTS4 and C0INTS.CINTS3 bits, and the type of the error can be identified by reading the C0LEC.LEC2 to C0LEC.LEC0 bits of the register. Upon successful transmission of the message frame, the transmit completion interrupt the CINTS0 bit of the C0INTS register is set to 1. If the C0IE.CIE0 bit is set to 1 at this time, an interrupt request signal is output. The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1). Caution The AL bit is only valid in single-shot mode. It does not affect the operation of re-transmission upon arbitration loss in other operation modes. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 955 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back. The CAN transmission pin (CTXD0) is fixed to the recessive level. If the falling edge on the CAN reception pin (CRXD0) is detected after the CAN module has entered the CAN sleep mode from the self-test mode, however, the module is released from the CAN sleep mode in the same manner as the other operation modes (when the sleep mode is released while the CAN clock is supplied, however, the PSMODE0 bit must be cleared by software after a falling edge is detected at the CAN reception pin (CRXD0).). To keep the module in the CAN sleep mode, use the CAN reception pin (CRXD0) as a port pin. Figure 19-34. CAN Module Terminal Connection in Self-Test Mode CAN macro Tx Fixed to the recessive level CTXD0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Rx CRXD0 Page 956 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.13.4 Transmission/reception operation in each operation mode Table 19-21 shows the transmission/reception operation in each operation mode. Table 19-21. Overview of Transmission/Reception Operation in Each Operation Mode Operation Mode Data Frame/ Remote Frame ACK Error Frame/ Retransmission Automatic Block Setting of VALID Storing Data in Transmission Overload Frame Transmission Transmission Transmission Bit Message Buffer (ABT) Initialization Mode - - - - - - - Normal operation mode - Normal operation mode Receive-only mode - - - Single-shot mode with ABT Self test mode Note 2 Note 2 Note 2 - - - - - Note 1 Note 2 Note 2 Note 2 Notes 1. If arbitration is lost, retransmission can be selected by the C0CTRL.AL bit. 2. Each signal is not output to the external circuit but is internally generated by the CAN module. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 957 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies). In some applications, however, a common time base over the network (= global time base) is needed. In order to build up a global time base, a time stamp function is used. The essential mechanism of a time stamp function is the capture of timer values triggered by signals on the CAN bus. 19.14.1 Time stamp function The CAN controller supports the capturing of timer values triggered by a specific frame. An on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the CAN controller. The 16-bit capture timer unit captures the timer value according to a trigger signal (TSOUT) for capturing that is output when a data frame is received from the CAN controller. The CPU can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the CAN bus, by reading the captured value. The TSOUT signal can be selected from the following two event sources and is specified by the C0TS.TSSEL bit. * SOF event (start of frame) * EOF event (last bit of end of frame) (TSSEL bit = 1) (TSSEL bit = 0) The TSOUT signal is enabled by setting the C0TS.TSEN bit to 1. Figure 19-35. Timing Diagram of Capture Signal TSOUT SOF SOF SOF SOF TSOUT t The TSOUT signal toggles its level upon occurrence of the selected event during data frame reception (in Figure 19-34, the SOF is used as the trigger event source). To capture a timer value by using the TSOUT signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. This time stamp function is controlled by the C0TS.TSLOCK bit. When the TSLOCK bit is cleared to 0, the TSOUT signal toggles upon occurrence of the selected event. If the TSLOCK bit is set to 1, the TSOUT signal toggles upon occurrence of the selected event, but the toggle is stopped as the TSEN bit is automatically cleared to 0 when a data frame starts to be received and stored in message buffer 0. This suppresses the subsequent toggle occurrence by the TSOUT signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 958 of 1442 V850ES/JC3-H, V850ES/JE3-H Caution CHAPTER 19 CAN CONTROLLER The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame. Toggle of the TSOUT signal does not stop when a data frame is received in a message buffer other than message buffer 0. For these reasons, a data frame cannot be received in message buffer 0 when the CAN module is in the normal operation mode with ABT, because message buffer 0 must be set as a transmit message buffer. In this operation mode, therefore, the function to stop toggle of the TSOUT signal by the TSLOCK bit cannot be used. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 959 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.15 Baud Rate Settings 19.15.1 Bit rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ SPT (sampling point) 17 TQ SPT = TSEG1 + 1TQ (b) 8 TQ DBT (data bit time) 25 TQ DBT = TSEG1 + TSEG2 + 1TQ = TSEG2 + SPT (c) 1 TQ SJW (synchronization jump width) 4TQ SJW DBT - SPT (d) 4TQ TSEG1 16TQ [3 Setting value of TSEG1[3:0] 15] (e) 1TQ TSEG2 8TQ [0 Setting value of TSEG2[2:0] 7] Remark TQ = 1/fTQ (fTQ: CAN protocol layer base system clock) TSEG1[3:0] (C0BTR.TSEG13 to C0BTR.TSEG10 bits) TSEG2[2:0] (C0BTR.TSEG22 to C0BTR.TSEG20 bits) Table 19-22 shows the combinations of bit rates that satisfy the above conditions. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 960 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 DBT Length R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 961 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 DBT Length R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 962 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 Note 1 2 2 2 0011 001 71.4 7 Note 1 4 1 1 0100 000 85.7 6 Note 1 1 2 2 0010 001 66.7 6 Note 1 3 1 1 0011 000 83.3 5 Note 1 2 1 1 0010 000 80.0 4 Note 1 1 1 1 0001 000 75.0 DBT Length Note Setting with a DBT value of 7 or less is valid only when the value of the C0BRP register is other than 00H. Caution The values in Table 19-22 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 963 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.15.2 Representative examples of baud rate settings Tables 19-23 and 19-24 show representative examples of baud rate settings. Table 19-23. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (1/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register C0BTR Register Setting Valid Bit Rate Setting (Unit: kbps) Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point Value TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-23 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 964 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-23. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register C0BTR Register Setting Valid Bit Rate Setting (Unit: kbps) Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point Value TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-23 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 965 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (1/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register C0BTR Register Setting Valid Bit Rate Setting (Unit: kbps) Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point Value TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-24 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 966 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Table 19-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register C0BTR Register Setting Valid Bit Rate Setting (Unit: kbps) Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point Value TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-24 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 967 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER 19.16 Operation of CAN Controller The processing procedure shown below is recommended to operate the CAN controller. Develop your program by referring to this recommended processing procedure. Remark m = 00 to 31 Figure 19-36. Initialization START Set C0GMCS register. Set C0GMCTRL register (set GOM bit = 1) Set C0BRP register, C0BTR register. Set C0IE register. Set C0MASK register. Initialize message buffers. Set C0CTRL register (set OPMODE bit). END Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 968 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-37. Re-initialization START Clear OPMODE. INIT mode? No Yes Set C0BRP register, C0BTR register. Set C0IE register. Set C0MASK register. Initialize message buffers. C0ERC and C0INFO register clear? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (set OPMODE bit) END Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after. If it is necessary to immediately set the module to another operation mode, be sure to access registers other than the C0CTRL and C0GMCTRL registers (e.g., set a message buffer). Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 969 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-38. Message Buffer Initialization START No RDY bit = 1? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Set C0MCONFm register. Set C0MIDHm register, C0MIDLm register. Transmit message buffer? No Yes Set C0MDLCm register. Clear C0MDATAm register. Set C0MCTRLm register. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 END Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2. Make the following settings for message buffers not used by the application. * Clear the C0MCTRLm.RDY, C0MCTRLm.TRQ, and C0MCTRLm.DN bits to 0. * Clear the C0MCONFm.MA0 bit to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 970 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-39 shows the processing for a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 001B to 101B). Figure 19-39. Message Buffer Redefinition START Clear VALID bit. C0CTRLCLEAR_VALID =1 No RDY = 1? Yes Clear RDY bit. C0MCTRLm.SET_RDY = 0 C0MCTRLm.CLEAR_RDY = 1 RDY = 0? No Yes RSTAT = 0 or Note 1 VALID = 1? No Yes Wait for a period of 4 CAN data Note 2 bits . Set message buffers. Set RDY bit. C0MCTRLm.SET_RDY = 1 C0MCTRLm.CLEAR_RDY = 0 END Notes 1. If redefinition is performed during a message reception, confirm that a message is being received because the RDY bit must be set after a message is completely received. 2. This 4-bit period may redefine the message buffer while a message is received and stored. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 971 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-40 shows the processing for a transmit message buffer during transmission (MT2 to MT0 bits of C0MCONFm register = 000B). Figure 19-40. Message Buffer Redefinition during Transmission START Transmit abort process Clear RDY bit. SET_RDY bit = 0 CLEAR_RDY bit = 1 RDY RDYbit= =0?0? No Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. SET_RDY bit = 1 CLEAR_RDY bit = 0 Transmit? No Yes Wait for a 1-bit perioddata of CAN Wait for 1CAN bits data. Set TRQ bit. SET_TRQ bit = 1 = 1 CLEAR_TRQ bit = 0 END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 972 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-41 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 19-41. Message Transmit Processing START No TRQ bit = 0? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Yes Data frame Data frame or remote frame? Remote frame Set RTR bit of C0MDLCm register and C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 973 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-42 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 19-42. ABT Message Transmit Processing START ABTTRG ABTTRGbit= =0?0? No Yes Clear RDY bit SET_RDY bit = 0 CLEAR_RDY bit = 1 RDY RDYbit == 0?0? No Yes Set C0MDATAxm register. Set C0MDLCm register. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. SetRDY RDYbit. bit Set SET_RDY bit = 1 CLEAR_RDY bit = 0 Set all ABT transmit messages? No Yes TSTAT TSTATbit= =0?0? No Yes Set ABTTRG bit. bit SET_ABTTRG = 1 CLEAR_ABTTRG = 0 END Caution The ABTTRG bit should be set to 1 after the TSTAT bit is cleared to 0. The checking of the TSTAT bit and the setting for the ABTTRG bit to 1 must be continuous. Remark This processing (message transmit processing with ABS) can only be applied to message buffers 0 to 7. For message buffers other than the ABT message buffers, refer to Figure 19-41. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 974 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-43. Transmission via Interrupt (Using C0LOPT Register) Start Transmit completion interrupt servicing Read C0LOPT register. Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing transmission interrupt servicing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 975 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-44. Transmission via Interrupt (Using C0TGPT Register) START Transmit completion interrupt servicing Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set TRQ bit. Set RDY bit = 1 Clear RDY bit = 0 THPM bit = 1? No Yes END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing transmission interrupt servicing. 2. If the TOVF bit is set (1) again, the transmit history list contradicts. Therefore, scan all the transmit message buffers that have completed transmission. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 976 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-45. Transmission via Software Polling START No CINTS0 bit = 1? Yes Clear CINTS0 bit. Clear CINTS0 bit = 1 Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Data frame or remote frame? Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 THPM bit = 1? No Yes END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. 2. If the TOVF bit is set (1) again, the transmit history list contradicts. Therefore, scan all the transmit message buffers that have completed transmission. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 977 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-46. Transmission Abort Processing (Other Than in Normal Operation Mode with ABT) START Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for a period of 11 CAN data bitsNote. TSTAT bit = 0? No Yes Read C0LOPT register. Message buffer to be aborted matches C0LOPT register? No Yes Transmission successful Transmit abort request was successful. END Note During a period of a total of 11 bits, 3 bits of interframe space and 8 bits of suspend transmission, the transmission request may have already been acknowledged by the protocol layer. Consequently, transmission may not be aborted but started even if the TRQ bit is cleared. Cautions 1. Execute transmission abort processing by clearing the TRQ bit, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute a new transmission request that includes other message buffers while transmission abort processing is in progress. 5. If data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmission has been successfully executed or failed may contradict. In such a case, make a judgment by using the history information of the C0TGPT register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 978 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-47. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit. SET_ABTTRG bit = 0 CLEAR_ABTTRG bit = 1 ABTTRG bit = 0? No Yes Clear TRQ bit. SET_TRQ bit = 0 CLEAR_TRQ bit = 1 Wait for a period of 11 CAN data Note bits. TSTAT bit = 0? No Yes Read C0LOPT register. Message buffer to be aborted matches C0LOPT register? No Yes Transmission successful Transmit abort request was successful. END Note During a period of a total of 11 bits, 3 bits of interframe space and 8 bits of suspend transmission, the transmission request may have already been acknowledged by the protocol layer. Consequently, transmission may not be aborted but started even if the TRQ bit is cleared. Cautions 1. Execute transmission abort processing by clearing the TRQ bit, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute a new transmission request including in the other message buffers while transmission abort processing is in progress. 5. If data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmission has been successfully executed or failed may contradict. In such a case, make a judgment by using the history information of the C0TGPT register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 979 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-48 (a) shows processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 19-48 (a). ABT Transmission Abort Processing (Normal Operation Mode with ABT) START No TSTAT bit = 0? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 No ABTTRG bit = 0? Yes Clear TRQ bit of message buffer whose transmission was aborted. Transmit abort Transmission start pointer clear? No Yes Set ABTCLR bit. Set ABTCLR bit = 1. END Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode transition request after the ABTTRG bit is cleared (after ABT mode is stopped) following the procedure shown in Figure 19-48 (a) or (b). When clearing a transmission request in an area other than the ABT area, follow the procedure shown in Figure 19-46. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 980 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-48 (b) shows the processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 19-48 (b). ABT Transmission Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission. Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 No ABTTRG bit = 0? Yes Transmit abort Transmission start pointer clear? No Yes Set ABTCLR bit. Set ABTCLR bit = 1 END Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode request after the ABTTRG bit is cleared (after ABT mode is stopped) following the procedure shown in Figure 19-48 (a) or (b). When clearing a transmission request in an area other than the ABT area, follow the procedure shown in Figure 19-46. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 981 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-49. Reception via Interrupt (Using C0LIPT Register) START Receive completion interrupt Read C0LIPT register. Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 and MUC bit = 0Note No Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 END Note Check the MUC and DN bits using one read access. Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing reception interrupt servicing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 982 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-50. Reception via Interrupt (Using C0RGPT Register) START Receive completion interrupt Read C0RGPT register. No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read normal data. Read illegal data. END Note Check the MUC and DN bits using one read access. Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing reception interrupt servicing. 2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the receive message buffers that have completed reception. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 983 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-51. Reception via Software Polling START No CINTS1 bit = 1? Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 Read C0RGPT register No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read normal data. Read illegal data. END Note Check the MUC and DN bits using one read access. Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. 2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the receive message buffers that have completed reception. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 984 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-52. Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit SET_PSMODE1 = 1 CLEAR_PSMODE1 = 0 PSMODE0 = 1? No Yes CAN sleep mode Set PSMODE1 bit. SET_PSMODE1 = 1 CLEAR_PSMODE1 = 0 PSMODE1 = 1? No No Request CAN sleep mode again? Yes CAN stop mode Yes END Clear OPMODE. No INIT mode? Yes Access to registers other than the C0CTRL and C0GMCTRL registers. Set C0CTRL register. (Set OPMODE) Clear CINTS5 bit. CLEAR_CINTS5 = 1 Caution To abort transmission before making a request for the CAN sleep mode, perform processing according to Figures 19-46 to 19-48. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 985 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-53. Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit. Set PSMODE1 bit = 0 Clear PSMODE1 bit = 1 CAN sleep mode CAN sleep mode release by user Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 (When CAN clock is not supplied) CAN sleep mode release when CAN bus becomes active (When CAN clock is suppliedNote) CAN sleep mode release when CAN bus becomes active After dominant edge detection, PSMODE0 bit = 0 CINTS5 bit = 1 After dominant edge detection, PSMODE0 bit = 0/1 CINTS5 bit = 1 Clear CINTS5 bit. Clear CINTS5 bit = 1 Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 Clear CINTS5 bit. Clear CINTS5 bit = 1 END Note The state in which the CAN clock is supplied means the state in which the CAN sleep mode is set without setting any of the following CPU standby modes. * STOP mode * IDLE1 and IDLE2 modes * The main clock has been stopped in subclock operation mode or sub-IDLE mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 986 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-54. Bus-off Recovery (Other Than in Normal Operation Mode with ABT) START No BOFF bit = 1? Yes Clear all TRQ bitsNote. Set C0CTRL register. (clear OPMODE bit) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (set OPMODE bit) Set C0CTRL register. (Set OPMODE bit) Wait for recovery from bus off. END Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence, clear all the TRQ bits. Caution If a request to change the mode from the initialization mode to any operation mode is made to execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11 contiguous recessive bits 128 times on the bus again. Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 987 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-55. Bus-off Recovery (Normal Operation Mode with ABT) START No BOFF bit = 1? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 Clear all TRQ bitNote Set C0CTRL register. (Clear OPMODE bit.) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (Set OPMODE.) Set C0CTRL register. (Set OPMODE bit.) Wait for recovery from bus off. END Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence, clear all the TRQ bits. Caution If a request to change the mode from the initialization mode to any operation mode is made to execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11 contiguous recessive bits 128 times on the bus again. Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 988 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-56. Normal Shutdown Process START INIT mode Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 Shutdown successful GOM bit = 0, EFSD bit = 0 END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 989 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-57. Forced Shutdown Process START Set EFSD bit. Set EFSD bit = 1 Must be a continuous write. Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 No GOM bit = 0? Yes Shutdown successful GOM bit = 0, EFSD bit = 0 End Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 990 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-58. Error Handling START Error interrupt CINTS2 bit = 1? No Yes Check CAN module state. (read C0INFO register) Clear CINTS2 bit. Clear CINTS2 bit = 1 CINTS3 bit = 1? No CINTS4 bit = 1? No Yes Yes Check CAN protocol error state. (read C0LEC register) Clear CINTS4 bit. Clear CINTS4 bit = 1 Clear CINTS3 bit. Clear CINTS3 bit = 1 END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 991 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-59. Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? No Yes CAN sleep mode MBON bit = 0? Yes Set CPU standby mode. No CINTS5 bit 1? No Yes Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 END Clear CINTS5 bit. Clear CINTS5 bit = 1 Note Check if the CPU is in the CAN sleep mode before setting it to the standby mode. The CAN sleep mode may be released by wakeup after it is checked if the CPU is in the CAN sleep mode and before the CPU is set in the standby mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 992 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 19 CAN CONTROLLER Figure 19-60. Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? No Yes CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 No Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 PSMODE1 bit = 1? Yes CAN stop mode Clear CINTS5 bitNote Clear CINTS5 bit = 1 MBON bit = 1? No Yes Set CPU standby mode. END Note During wakeup interrupts Caution The CAN stop mode can only be released by writing 01 to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits. The CAN stop mode cannot be released by changing the CAN bus. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 993 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) CHAPTER 20 USB FUNCTION CONTROLLER (USBF) The V850ES/JC3-H and V850ES/JE3-H have an internal USB function controller (USBF) conforming to the Universal Serial Bus Specification. Data communication using the polling method is performed between the USB function controller and external host device by using a token-based protocol. 20.1 Overview * Conforms to the Universal Serial Bus Specification * Supports 12 Mbps (full-speed) transfer * Endpoint for transfer incorporated Endpoint Name FIFO Size (Bytes) Transfer Type Remark Endpoint0 Read 64 Control transfer - Endpoint0 Write 64 Control transfer - Endpoint1 64 x 2 Bulk 1 transfer (IN) 2-buffer configuration Endpoint2 64 x 2 Bulk 1 transfer (OUT) 2-buffer configuration Endpoint3 64 x 2 Bulk 2 transfer (IN) 2-buffer configuration Endpoint4 64 x 2 Bulk 2 transfer (OUT) 2-buffer configuration Endpoint7 8 Interrupt transfer (IN) - * Bulk transfer (IN/OUT) can be executed as DMA transfer (2-cycle single-transfer mode) * Clock: Internal clock (6 MHz external clock x internal clock multiplied by 8 = 48 MHz internal clock) or external clock (external clock input to UCLK pin (fUSB = 48 MHz)) selectable Caution The registers listed in 20.6.2 USB function controller register list must be accessed after specifying that the internal clock or the external clock is to be used as the USB clock and supplying clock to the USB function controller. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 994 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.2 Configuration 20.2.1 Block diagram Figure 20-1. Block Diagram of USB Function Controller Bridge interrupt enable register (BRGINTE) Internal CPU Bridge circuit USBF interrupt (INTUSBF0) USBF controller Endpoint Endpoint0 Read (64 bytes) Endpoint0 Write (64 bytes) Endpoint1 (64 bytes x 2) Endpoint2 (64 bytes x 2) Endpoint3 (64 bytes x 2) Endpoint4 (64 bytes x 2) Endpoint7 (8 bytes) SIE I/O buffer UDMF UDPF USB resume interrupt (INTUSBF1) USB clock Remark Area enclosed with dashed line: These functions are included in the USB function controller. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 995 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.2.2 USB memory map The USB function controller seen from the CPU is assigned to the CS1 space in the microcontroller. The memory space is divided for use as follows. Table 20-1. Division of CPU Memory Space Address Area 00200000H to 00200092H EPC control register area 00200100H to 00200114H EPC data hold register area 00200144H to 002003C4H EPC request data register area 00200400H to 00200408H Bridge register area 00200500H to 0020050EH DMA register area 00201000H Bulk-in register area 00202000H 00210000H EP3 (Bulk-IN2) Bulk-out register area 00220000H 00240000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 EP1 (Bulk-IN1) EP2 (Bulk-Out1) EP4 (Bulk-Out2) Peripheral control register area Page 996 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.3 External Circuit Configuration 20.3.1 Outline In USB transmission, when communication is performed with the host controller and function controller facing each other, pull-up/pull-down resistors must be connected to the USB signal (D+/D-) to identify the communication partner. Moreover in the V850ES/JC3-H and V850ES/JE3-H, series resistors must also be connected. Because the V850ES/JC3-H and V850ES/JE3-H do not include these pull-up/pull-down resistors and series resistors, be sure to connect them externally. The following shows the outline configuration of the USB transmission line. For details of the external configuration, see the description provided in each section. Figure 20-2. Outline Configuration of Pull-up, Pull-down, Series Resistors in USB Transmission Line VDD VDD Host device Function device Connect series resistors when using the V850ES/JC3-H and V850ES/JE3-H D+ D- 15 k 5% 15 k 5% Low speed Full speed (USB function controller in the V850ES/JC3-H and V850ES/JE3-H is fixed to full speed) Mount either one in accordance with operation speed. Host side R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Function side Page 997 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.3.2 Connection configuration Figure 20-3. Example of USB Function Controller Connection UVDD V850ES/JC3-H, V850ES/JE3-H Determine the pull-up resistor value in accordance with the buffer type (pull-down/pull-up) of the port pin to be used. P42/INTP10 UVDD IC1 P41 IC2 Connect a pull-up resistor to D+. 1.5 k 5%. Schmitt buffer recommended R1 VBUS UDPF UDMF D+ 30 5% D- 30 5% Insert a series resistor adjacent to the V850ES/JC3-H or V850ES/JE3-H. Make the length of the wiring between resistors and D+/D- of the USB connector the same. R2 USB connector 50 k or more (floating protection) VBUS is resistancedivided at a ratio of R1:R2. (1) Series resistor connection to D+/D- Connect series resistors of 30 5% to the D+/D- pins (UFDP, UFDM) of the USB function controller in the V850ES/JC3-H and V850ES/JE3-H. If they are not connected, the impedance rating cannot be satisfied and the output waveform may be disturbed. Allocate the series resistors adjacent to the V850ES/JC3-H or V850ES/JE3-H, and make the length of the wiring between the series resistors and the USB connectors the same, to make the impedance of D+ and D- equal (a differential with 90 5% is recommended). (2) Pull-up control of D+ Because the function controller of the V850ES/JC3-H and V850ES/JE3-H is fixed to full speed (FS), be sure to pull up the D+ pin (UFDP) by 1.5 k 5% to UVDD. To disable a connection report (D+ pull up) to the USB host/HUB (such as during high priority servicing or initialization), control the pull-up resistor of D+ via a general-purpose port in the system. For a circuit such as the one shown in Figure 20-3, control the pull-up control signal and the VBUS input signal of the D+ pin by using a general-purpose port and the USB cable VBUS (AND circuit). In Figure 20-3, if the general-purpose port is low level, pulling up of D+ is prohibited. For the IC2 in Figure 20-3, use an IC to which voltage can be applied when the system power is off. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 998 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) Detection of USB cable connection/disconnection The USB function controller (USBF) requires a VBUS input signal to recognize whether the USB cable is connected or disconnected, because the state of the USBF is controlled by hardware. The voltage from the USB host or HUB (5 V) is applied as the VBUS input signal when the USB cable VBUS is connected to the USB host or HUB while the USBF power is off. Therefore, for IC1 in Figure 20-3, use an IC to which voltage can be applied when the system power is off. When disconnecting the USB cable in the circuit in Figure 20-3, the input signal to INTP10 may be unstable while the VBUS voltage is dropping. It is therefore recommended to use a Schmitt buffer for IC1 in Figure 20-3. (4) Floating protection during initialization or when USBF is unused When the USB function controller is initialized or unused, to avoid a floating status, pull the D+/D- pins down using a resistor of 50 k or higher. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 999 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.4 Cautions (1) Clock accuracy To operate the USB function controller, the internal clock (6 MHz external clock x internal clock multiplied by 8 = 48 MHz internal clock) or external clock (external clock input to UCLK pin (fUSB = 48 MHz)) must be used as the USB clock. When the internal clock is used as the USB clock, use a resonator with an accuracy of 6 MHz 500 ppm (max.). When the external clock is used, apply a clock with an accuracy of 48 MHz 500 ppm (max.) to the UCLK pin. If the USB clock accuracy drops, the transmission data cannot satisfy the USB rating. (2) Stopping the USB clock When the main clock (fXX) has been selected as the USB function controller clock and it is necessary to stop the USB function controller, be sure to stop the USB function controller (by setting bits 1 and 0 of the UFCKMSK register to 1) first before stopping the main clock (fXX). If the main clock (fXX) is stopped without first stopping the USB function controller, a malfunction might occur due to noise in the clock pulse when the main clock (fXX) is restarted. Similarly, when an external clock whose signal is input from the EXCLK pin is selected as the USB function controller clock, measures must be taken to prevent noise from being generated in the clock pulse by the external circuit. If this is not feasible, then the USB function controller must be stopped first before stopping the main clock (fXX). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1000 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.5 Requests The USB standard has a request command that reports requests from the host device to the function device to execute response processing. The requests are received in the SETUP stage of control transfer, and most can be automatically processed via the hardware of the USB function controller (USBF). 20.5.1 Automatic requests (1) Decode The following tables show the request format and the correspondence between requests and decoded values. Table 20-2. Request Format Offset Field Name 0 bmRequestType 1 bRequest 2 wValue 3 4 Higher side wIndex 5 6 7 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Lower side Lower side Higher side wLength Lower side Higher side Page 1001 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Table 20-3. Correspondence Between Requests and Decoded Values Offset Decoded Value bmRequestType bRequest Request GET_INTERFACE Data Response wValue wIndex wLength 0 1 3 2 5 4 7 6 81H 0AH 00H 00H 00H 0nH 00H 01H Df Ad STALL STALL Cf ACK Stage NAK GET_CONFIGURATION GET_DESCRIPTOR 80H 80H 08H 06H 00H 01H 00H 00H 00H 00H 00H 00H 00H XXH 01H XXHNote 1 Device GET_DESCRIPTOR 80H 06H 02H 00H 00H 00H XXH XXHNote 1 Configuration GET_STATUS 80H 00H 00H 00H 00H 00H 00H 02H Device GET_STATUS 82H 00H 00H 00H 00H 00H 00H 02H 80H Endpoint 0 GET_STATUS 82H 00H 00H 00H 00H $$H 00H 02H ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK STALL STALL Endpoint X ACK NAK CLEAR_FEATURE 00H 01H 00H 01H 00H 00H 00H 00H DeviceNote 2 CLEAR_FEATURE 02H 01H 00H 00H 00H Endpoint 0Note 2 00H 00H 00H 80H CLEAR_FEATURE 02H 01H 00H 00H 00H $$H 00H 00H ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK STALL STALL Endpoint XNote 2 ACK x x x NAK SET_FEATURE 00H 03H 00H 01H 00H 00H 00H 00H DeviceNote 3 SET_FEATURE 02H 03H 00H 00H 00H Endpoint 0Note 3 00H 00H 00H 80H SET_FEATURE 02H 03H 00H 00H 00H $$H 00H 00H ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK STALL STALL Endpoint XNote 3 ACK x x x NAK SET_INTERFACE 01H 0BH 00H 0#H 00H 0?H 00H 00H STALL STALL ACK x NAK SET_CONFIGURATIONNote 4 00H 09H 00H 00H 00H 00H 00H 00H 01H SET_ADDRESS Remark 00H 05H XXH XXH 00H 00H 00H 00H ACK ACK ACK NAK NAK NAK ACK ACK ACK NAK NAK NAK x x : Data stage x: No data stage Notes 1. If the wLength value is lower than the prepared value, the wLength value is returned; if the wLength value is the prepared value or higher, the prepared value is returned. 2. The CLEAR_FEATURE request clears UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7) when ACK is received in the status stage. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1002 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Notes 3. The SET_FEATURE request sets the UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7) when ACK is received in the status stage. If the E0HALT bit of the UF0E0SL register is set, a STALL response is made in the status stage or data stage of control transfer for a request other than the GET_STATUS Endpoint0 request, SET_FEATURE Endpoint0 request, and a request generated by the CPUDEC interrupt request, until the CLEAR_FEATURE Endpoint0 request is received. A STALL response to an unsupported request does not set the E0HALT bit of the UF0E0SL register to 1, and the STALL response is cleared as soon as the next SETUP token has been received. 4. If the wValue is not the default value, an automatic STALL response is made. Cautions 1. The sequence of control transfer defined by the Universal Serial Bus Specification is not satisfied under the following conditions. The operation is not guaranteed under these conditions. * If an IN/OUT token is suddenly received without a SETUP stage * If DATA PID1 is sent in the data phase of the SETUP stage * If a token of 128 addresses or more is received * If the request data transmitted in the SETUP stage is of less than 8 bytes 2. An ACK response is made even when the host transmits data other than a Null packet in the status stage. 3. If the wLength value is 00H during control transfer (read) of FW processing, a Null packet is automatically transmitted for control transfer (without data). The FW request does not automatically transmit a Null packet. Remarks 1. Df: Default state, Ad: Addressed state, Cf: Configured state 2. n = 0 to 4 It is determined by the setting of the UF0 active interface number register (UF0AIFN) whether a request with Interface number 1 to 4 is correctly responded to, depending on whether the Interface number of the target is valid or not. 3. $$: Valid endpoint number including transfer direction The valid endpoint is determined by the currently set Alternate Setting number (see 20.6.3 (36) UF0 active alternative setting register (UF0AAS), (38) UF0 endpoint 1 interface mapping register (UF0E1IM) to (42) UF0 endpoint 7 interface mapping register (UF0E7IM)). 4. ? and #: Value transmitted from host (information on Interface numbers 0 to 4) It is determined by the UF0 active interface number register (UF0AIFN) and UF0 active alternative setting register (UF0AAS) whether an Alternate Setting request corresponding to each Interface number is correctly responded to or not, depending on whether the Interface number and Alternate Setting of the target are valid or not. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1003 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) Processing The processing of an automatic request in the Default state, Addressed state, and Configured state is described below. Remark Default state: State in which an operation is performed with the Default address Addressed state: State after an address has been allocated Configured state: State after SET_CONFIGURATION wValue = 1 has been correctly received (a) CLEAR_FEATURE() request A STALL response is made in the status stage if the CLEAR_FEATURE() request cannot be cleared, if FEATURE does not exist, or if the target is an interface or an endpoint that does not exist. A STALL response is also made if the wLength value is other than 0. * Default state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for Endpoint0; otherwise a STALL response is made in the status stage. * Addressed state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for Endpoint0; otherwise a STALL response is made in the status stage. * Configured state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for an endpoint that exists; otherwise a STALL response is made in the status stage. When the CLEAR_FEATURE() request has been correctly processed, the corresponding bit of the UF0 CLR request register (UF0CLR) is set to 1, the EnHALT bit of the UF0 EPn status register L (UF0EnSL) is cleared to 0, and an interrupt is issued (n = 0 to 4, 7). If the CLEAR_FEATURE() request is received when the subject is an endpoint, the toggle bit (that controls switching between DATA0 and DATA1) of the corresponding endpoint is always re-set to DATA0. (b) GET_CONFIGURATION() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 20-3. * Default state: The value stored in the UF0 configuration register (UF0CNF) is returned when the GET_CONFIGURATION() request has been received. * Addressed state: The value stored in the UF0CNF register is returned when the GET_CONFIGURATION() request has been received. * Configured state: The value stored in the UF0CNF register is returned when the GET_CONFIGURATION() request has been received. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1004 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (c) GET_DESCRIPTOR() request If the subject descriptor has a length that is a multiple of wMaxPacketSize, a Null packet is returned to indicate the end of the data stage. If the length of the descriptor at this time is less than the wLength value, the entire descriptor is returned; if the length of the descriptor is greater than the wLength value, the descriptor up to the wLength value is returned. * Default state: The value stored in UF0 device descriptor register n (UF0DDn) and UF0 configuration/interface/endpoint descriptor register m (UF0CIEm) is returned (n = 0 to 17, m = 0 to 255) when the GET_DESCRIPTOR() request has been received. * Addressed state: The value stored in the UF0DDn register and UF0CIEm register is returned when the GET_DESCRIPTOR() request has been received. * Configured state: The value stored in the UF0DDn register and UF0CIEm register is returned when the GET_DESCRIPTOR() request has been received. A descriptor of up to 256 bytes can be stored in the UF0CIEm register. To return a descriptor of more than 256 bytes, set the CDCGDST bit of the UF0MODC register to 1 and process the GET_DESCRIPTOR() request by FW. Store the value of the total number of bytes of the descriptor set by the UF0CIEm register - 1 in the UF0 descriptor length register (UF0DSCL). The transfer data is controlled by the value of this data + 1 and wLength. (d) GET_INTERFACE() request If either of wValue and wLength is other than that shown in Table 20-3, or if wIndex is other than that set by the UF0 active interface number register (UF0AIFN), a STALL response is made in the data stage. * Default state: A STALL response is made in the data stage when the GET_INTERFACE() request has been received. * Addressed state: A STALL response is made in the data stage when the GET_INTERFACE() request has been received. * Configured state: The value stored in the UF0 interface n register (UF0IFn) corresponding to the wIndex value is returned (n = 0 to 4) when the GET_INTERFACE() request has been received. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1005 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (e) GET_STATUS() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 20-3. A STALL response is also made in the data stage if the target is an interface or an endpoint that does not exist. * Default state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or Endpoint0; otherwise a STALL response is made in the data stage. * Addressed state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or Endpoint0; otherwise a STALL response is made in the data stage. * Configured state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or an endpoint that exists; otherwise a STALL response is made in the data stage. Note The target status register is as follows. * If the target is a device: UF0 device status register L (UF0DSTL) * If the target is endpoint 0: UF0 EP0 status register L (UF0E0SL) * If the target is endpoint n: UF0 EPn status register L (UF0EnSL) (n = 1 to 4, 7) (f) SET_ADDRESS() request A STALL response is made in the status stage if either of wIndex or wLength is other than the values shown in Table 20-3. A STALL response is also made if the specified device address is greater than 127. * Default state: The device enters the Addressed state and changes the USB Address value to be input to SIE into a specified address value if the specified address is other than 0 when the SET_ADDRESS() request has been received. If the specified address is 0, the device remains in the Default state. * Addressed state: The device enters the Default state and returns the USB Address value to be input to SIE to the default address if the specified address is 0 when the SET_ADDRESS() request has been received. If the specified address is other than 0, the device remains in the Addressed state, and changes the USB Address value to be input to SIE into a specified new address value. * Configured state: The device remains in the Configured state and returns the USB Address value to be input to SIE to the default address if the specified address is 0 when the SET_ADDRESS() request has been received. In this case, the endpoints other than endpoint 0 remain valid, and control transfer (IN), control transfer (OUT), bulk transfer and interrupt transfer for an endpoint other than endpoint 0 are also acknowledged. If the specified address is other than 0, the device remains in the Configured state and changes the USB Address value to be input to SIE into a specified new address value. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1006 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (g) SET_CONFIGURATION() request If any of wValue, wIndex, or wLength is other than the values shown in Table 20-3, a STALL response is made in the status stage. * Default state: The CONF bit of the UF0 mode status register (UF0MODS) and the UF0 configuration register (UF0CNF) are set to 1 if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 0, the CONF bit of the UF0MODS register and UF0CNF register are cleared to 0. In other words, the device skips the Addressed state and moves to the Configured state in which it responds to the Default address. * Addressed state: The CONF bit of the UF0MODS register and UF0CNF register are set to 1 and the device enters the Configured state if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 0, the device remains in the Addressed state. * Configured state: The CONF bit of the UF0MODS register and UF0CNF register are set to 1 and the device returns to the Addressed state if the specified configuration value is 0 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 1, the device remains in the Configured state. If the SET_CONFIGURATION() request has been correctly processed, the target bit of the UF0 SET request register (UF0SET) is set to 1, and an interrupt is issued. All Halt Features are cleared after the SET_CONFIGURATION() request has been completed even if the specified configuration value is the same as the current configuration value. If the SET_CONFIGURATION() request has been correctly processed, the data toggle of all endpoints is always initialized to DATA0 again (it is defined that the default status, Alternative Setting 0, is set from when the SET_CONFIGURATION request is received to when the SET_INTERFACE request is received). (h) SET_FEATURE() request A STALL response is made in the status stage if the SET_FEATURE() request is for a Feature that cannot be set or does not exist, or if the target is an interface or an endpoint that does not exist. A STALL response is also made if the wLength value is other than 0. * Default state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or Endpoint0; otherwise a STALL response is made in the status stage. * Addressed state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or Endpoint0; otherwise a STALL response is made in the status stage. * Configured state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or an endpoint that exists; otherwise a STALL response is made in the status stage. When the SET_FEATURE() request has been correctly processed, the target bit of the UF0 SET request register (UF0SET) and the EnHALT bit of the UF0 EPn status register L (UF0EnSL) are set to 1, and an interrupt is issued (n = 0 to 4, 7). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1007 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (i) SET_INTERFACE() request If wLength is other than the values shown in Table 20-3, if wIndex is other than the value set to the UF0 active interface number register (UF0AIFN), or if wValue is other than the value set to the UF0 active alternative setting register (UF0AAS), a STALL response is made in the status stage. * Default state: A STALL response is made in the status stage when the SET_INTERFACE() request has been received. * Addressed state: A STALL response is made in the status stage when the SET_INTERFACE() request has been received. * Configured state: Null packet is transmitted in the status stage when the SET_INTERFACE() request has been received. When the SET_INTERFACE() request has been correctly processed, an interrupt is issued. All the Halt Features of the endpoint linked to the target Interface are cleared after the SET_INTERFACE() request has been cleared. The data toggle of all the endpoints related to the target Interface number is always initialized again to DATA0. When the currently selected Alternative Setting is to be changed by correctly processing the SET_INTERFACE() request, the FIFO of the endpoint that is affected is completely cleared, and all the related interrupt sources are also initialized. When the SET_INTERFACE() request has been completed, the FIFO of all the endpoints linked to the target Interface are cleared. At the same time, Halt Feature and Data PID are initialized, and the related UF0 INT status n register (UF0ISn) is cleared to 0 (n = 0 to 4). (Only Halt Feature and Data PID are cleared when the SET_CONFIGURATION request has been completed.) If the target Endpoint is not supported by the SET_INTERFACE() request during DMA transfer, the DMA request signal is immediately deasserted, and the FIFO of the Endpoint that has been linked when the SET_INTERFACE() request has been completed is completely cleared. As a result of this clearing of the FIFO, data transferred by DMA is not correctly processed. 20.5.2 Other requests (1) Response and processing The following table shows how other requests are responded to and processed. Table 20-4. Response and Processing of Other Requests Request Response and Processing GET_DESCRIPTOR String Generation of CPUDEC interrupt request GET_STATUS Interface Automatic STALL response CLEAR_FEATURE Interface Automatic STALL response SET_FEATURE Interface Automatic STALL response all SET_DESCRIPTOR Generation of CPUDEC interrupt request All other requests Generation of CPUDEC interrupt request R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1008 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6 Register Configuration 20.6.1 USB control registers (1) USB clock select register (UCKSEL) The UCKSEL register selects the operation clock of the USB controller. The UCKSEL register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H UCKSEL R/W Address: FFFFFF40H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 UUSEL1 0 UUSEL1 Caution Selection of USB controller operation clock 0 External clock input from UCLK pin (fUSB = 48 MHz) 1 Main clock (fXX = 48 MHz) Be sure to set bits 7 to 2, and 0 to ``0''. (2) USB function control register (UFCKMSK) The UFCKMSK register controls enable/disable of USB function controller operation. The UFCKMSK register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. After reset: 03H R/W Address: FFFFFF41H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 UFBUFMSK UFMSK UFBUFMSK UFMSK 0 0 Operation enabled 0 1 Operation stopped (set while USB is suspended) 1 1 Operation stopped UFCKMSK Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 USB function controller operation enable/stop Setting prohibited Page 1009 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) EPRAM mask register (EPRMK) The EPRMK register controls the operation of the endpoint RAM when the USB controller function is used. Even when the USB function controller is not being used, the endpoin RAM can be used by setting the EPRMK register. After reset: 00H EPRMK R/W Address: FFFFFF44H 7 6 5 4 3 2 1 0 0 RDRMK EP7MK EP4MK EP3MK EP2MK EP1MK EP0MK Setting RDRMK mask RDRMK 0 Do not mask (operation) 1 Mask (stop) EP7MK Setting EP7MK mask 0 Do not mask (operation) 1 Mask (stop) EP4MK Setting EP4MK mask 0 Do not mask (operation) 1 Mask (stop) EP3MK Setting EP3MK mask 0 Do not mask (operation) 1 Mask (stop) EP2MK Setting EP2MK mask 0 Do not mask (operation) 1 Mask (stop) EP1MK Setting EP1MK mask 0 Do not mask (operation) 1 Mask (stop) EP0MK Caution Setting EP0MK mask 0 Do not Mask (operation) 1 Mask (stop) Be sure to set bits 7 to 2 to ``0'', and bit 1 to ``1''. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1010 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.2 External bus control registers (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each USB space. The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data wait states are inserted for all the blocks. The DWC0 register can be read or written in 16-bit units. Reset sets this register to 7777H. Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are always accessed without a wait state. The on-chip peripheral I/O area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the DWC0 register are complete. After reset: 7777H Address: FFFFF484H 15 14 13 12 11 10 9 8 0 1 1 1 0 1 1 1 7 6 3 2 1 0 0 1 1 1 DWC0 0 Note R/W DW12 5 Note 4 Note DW11 Note DW10 Number of wait states inserted in USBn space DW12 DW11 DW10 0 0 0 None 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 The DW12 to DW10 bits set wait of access to the USB function area. It is recommended to set the DW12 to DW10 bits to 001B (1 wait). Caution Be sure to clear bits 15, 11, 7, and 3 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1011 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) Address wait control register (AWC) The AWC register can be read or written in 16-bit units. Reset sets this register to FFFFH. Cautions 1. Address-setup wait and address-hold wait cycles are not inserted when the internal ROM area, internal RAM area, and on-chip peripheral I/O areas are accessed. 2. Write to the AWC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the AWC register are complete. After reset: FFFFH AWC R/W 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 7 6 5 4 3 1 0 1 1 1 1 1 1 AHW1 2 Note Note ASW1 Specifies insertion of address-hold wait AHW1 0 Not inserted 1 Inserted Specifies insertion of address-setup wait ASW1 Note Address: FFFFF488H 15 0 Not inserted 1 Inserted It is recommended to clear the AHW1 bit and the ASW1 bit to 0. Caution Be sure to set bits 15 to 4, 1 and 0 to "1". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1012 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) Bus cycle control register (BCC) The BCC register can be read or written in 16-bit units. Reset sets this register to AAAAH. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state insertion. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BCC register are complete. After reset: AAAAH BCC R/W Address: FFFFF48AH 15 14 13 12 11 10 9 8 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 BC11 Note Specifies insertion of idle state BC11 0 Not inserted 1 Inserted Note It is recommended to clear the BC11 bit to 0. Caution Be sure to set bits 15, 13, 11, 9, 7, 5 and 1 to "1", and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1013 of 1442 V850ES/JC3-H, V850ES/JE3-H 20.6.3 CHAPTER 20 USB FUNCTION CONTROLLER (USBF) USB function controller register list (1) EPC control register (1/2) Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200000H UF0 EP0NAK register UF0E0N R/W 00H 00200002H UF0 EP0NAKALL register UF0E0NA R/W 00H 00200004H UF0 EPNAK register UF0EN R/W 00H 00200006H UF0 EPNAK mask register UF0ENM R/W 00H 00200008H UF0 SNDSIE register UF0SDS R/W 00H 0020000AH UF0 CLR request register UF0CLR R 00H 0020000CH UF0 SET request register UF0SET R 00H 0020000EH UF0 EP status 0 register UF0EPS0 R 00H 00200010H UF0 EP status 1 register UF0EPS1 R 00H 00200012H UF0 EP status 2 register UF0EPS2 R 00H 00200020H UF0 INT status 0 register UF0IS0 R 00H 00200022H UF0 INT status 1 register UF0IS1 R 00H 00200024H UF0 INT status 2 register UF0IS2 R 00H 00200026H UF0 INT status 3 register UF0IS3 R 00H 00200028H UF0 INT status 4 register UF0IS4 R 00H 0020002EH UF0 INT mask 0 register UF0IM0 R/W 00H 00200030H UF0 INT mask 1 register UF0IM1 R/W 00H 00200032H UF0 INT mask 2 register UF0IM2 R/W 00H 00200034H UF0 INT mask 3 register UF0IM3 R/W 00H 00200036H UF0 INT mask 4 register UF0IM4 R/W 00H 0020003CH UF0 INT clear 0 register UF0IC0 W FFH 0020003EH UF0 INT clear 1 register UF0IC1 W FFH 00200040H UF0 INT clear 2 register UF0IC2 W FFH 00200042H UF0 INT clear 3 register UF0IC3 W FFH 00200044H UF0 INT clear 4 register UF0IC4 W FFH 0020004CH UF0 INT & DMARQ register UF0IDR R/W 00H 0020004EH UF0 DMA status 0 register UF0DMS0 R 00H 00200050H UF0 DMA status 1 register UF0DMS1 R 00H 00200060H UF0 FIFO clear 0 register UF0FIC0 W 00H 00200062H UF0 FIFO clear 1 register UF0FIC1 W 00H 0020006AH UF0 data end register UF0DEND R/W 00H 0020006EH UF0 GPR register UF0GPR W 00H 00200074H UF0 mode control register UF0MODC R/W 00H 00200078H UF0 mode status register UF0MODS R 00H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1014 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200080H UF0 active interface number register UF0AIFN R/W 00H 00200082H UF0 active alternative setting register UF0AAS R/W 00H 00200084H UF0 alternative setting status register UF0ASS R 00H 00200086H UF0 endpoint 1 interface mapping register UF0E1IM R/W 00H 00200088H UF0 endpoint 2 interface mapping register UF0E2IM R/W 00H 0020008AH UF0 endpoint 3 interface mapping register UF0E3IM R/W 00H 0020008CH UF0 endpoint 4 interface mapping register UF0E4IM R/W 00H 00200092H UF0 endpoint 7 interface mapping register UF0E7IM R/W 00H (2) EPC data hold register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200100 H UF0 EP0 read register UF0E0R R Undefined 00200102H UF0 EP0 length register UF0E0L R 00H 00200104H UF0 EP0 setup register UF0E0ST R 00H 00200106H UF0 EP0 write register UF0E0W W Undefined 00200108H UF0 bulk-out 1 register UF0BO1 R Undefined 0020010AH UF0 bulk-out 1 length register UF0BO1L R 00H 0020010CH UF0 bulk-out 2 register UF0BO2 R Undefined 0020010EH UF0 bulk-out 2 length register UF0BO2L R 00H 00200110H UF0 bulk-in 1 register UF0BI1 W Undefined 00200112H UF0 bulk-in 2 register UF0BI2 W Undefined 00200114H UF0 interrupt 1 register UF0INT1 W Undefined R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1015 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) EPC request data register (1/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200144H UF0 device status register L UF0DSTL R/W 00H 0020014CH UF0 EP0 status register L UF0E0SL R/W 00H 00200150H UF0 EP1 status register L UF0E1SL R/W 00H 00200154H UF0 EP2 status register L UF0E2SL R/W 00H 00200158H UF0 EP3 status register L UF0E3SL R/W 00H 0020015CH UF0 EP4 status register L UF0E4SL R/W 00H 00200168H UF0 EP7 status register L UF0E7SL R/W 00H 00200180H UF0 address register UF0ADRS R 00H 00200182H UF0 configuration register UF0CNF R 00H 00200184H UF0 interface 0 register UF0IF0 R 00H 00200186H UF0 interface 1 register UF0IF1 R 00H 00200188H UF0 interface 2 register UF0IF2 R 00H 0020018AH UF0 interface 3 register UF0IF3 R 00H 0020018CH UF0 interface 4 register UF0IF4 R 00H 002001A0H UF0 descriptor length register UF0DSCL R/W 00H 002001A2H UF0 device descriptor register 0 UF0DD0 R/W Undefined 002001A4H UF0 device descriptor register 1 UF0DD1 R/W Undefined 002001A6H UF0 device descriptor register 2 UF0DD2 R/W Undefined 002001A8H UF0 device descriptor register 3 UF0DD3 R/W Undefined 002001AAH UF0 device descriptor register 4 UF0DD4 R/W Undefined 002001ACH UF0 device descriptor register 5 UF0DD5 R/W Undefined 002001AEH UF0 device descriptor register 6 UF0DD6 R/W Undefined 002001B0H UF0 device descriptor register 7 UF0DD7 R/W Undefined 002001B2H UF0 device descriptor register 8 UF0DD8 R/W Undefined 002001B4H UF0 device descriptor register 9 UF0DD9 R/W Undefined 002001B6H UF0 device descriptor register 10 UF0DD10 R/W Undefined 002001B8H UF0 device descriptor register 11 UF0DD11 R/W Undefined 002001BAH UF0 device descriptor register 12 UF0DD12 R/W Undefined 002001BCH UF0 device descriptor register 13 UF0DD13 R/W Undefined 002001BEH UF0 device descriptor register 14 UF0DD14 R/W Undefined 002001C0H UF0 device descriptor register 15 UF0DD15 R/W Undefined 002001C2H UF0 device descriptor register 16 UF0DD16 R/W Undefined 002001C4H UF0 device descriptor register 17 UF0DD17 R/W Undefined 002001C6H UF0 configuration/interface/endpoint descriptor UF0CIE0 R/W Undefined UF0CIE1 R/W Undefined UF0CIE2 R/W Undefined UF0CIE3 R/W Undefined register 0 002001C8H UF0 configuration/interface/endpoint descriptor register 1 002001CAH UF0 configuration/interface/endpoint descriptor register 2 002001CCH UF0 configuration/interface/endpoint descriptor register 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1016 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002001CEH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE4 R/W Undefined UF0CIE5 R/W Undefined UF0CIE6 R/W Undefined UF0CIE7 R/W Undefined UF0CIE8 R/W Undefined UF0CIE9 R/W Undefined UF0CIE10 R/W Undefined UF0CIE11 R/W Undefined UF0CIE12 R/W Undefined UF0CIE13 R/W Undefined UF0CIE14 R/W Undefined UF0CIE15 R/W Undefined UF0CIE16 R/W Undefined UF0CIE17 R/W Undefined UF0CIE18 R/W Undefined UF0CIE19 R/W Undefined UF0CIE20 R/W Undefined UF0CIE21 R/W Undefined UF0CIE22 R/W Undefined UF0CIE23 R/W Undefined UF0CIE24 R/W Undefined UF0CIE25 R/W Undefined register 4 002001D0H UF0 configuration/interface/endpoint descriptor register 5 002001D2H UF0 configuration/interface/endpoint descriptor register 6 002001D4H UF0 configuration/interface/endpoint descriptor register 7 002001D6H UF0 configuration/interface/endpoint descriptor register 8 002001D8H UF0 configuration/interface/endpoint descriptor register 9 002001DAH UF0 configuration/interface/endpoint descriptor register 10 002001DCH UF0 configuration/interface/endpoint descriptor register 11 002001DEH UF0 configuration/interface/endpoint descriptor register 12 002001E0H UF0 configuration/interface/endpoint descriptor register 13 002001E2H UF0 configuration/interface/endpoint descriptor register 14 002001E4H UF0 configuration/interface/endpoint descriptor register 15 002001E6H UF0 configuration/interface/endpoint descriptor register 16 002001E8H UF0 configuration/interface/endpoint descriptor register 17 002001EAH UF0 configuration/interface/endpoint descriptor register 18 002001ECH UF0 configuration/interface/endpoint descriptor register 19 002001EEH UF0 configuration/interface/endpoint descriptor register 20 002001F0H UF0 configuration/interface/endpoint descriptor register 21 002001F2H UF0 configuration/interface/endpoint descriptor register 22 002001F4H UF0 configuration/interface/endpoint descriptor register 23 002001F6H UF0 configuration/interface/endpoint descriptor register 24 002001F8H UF0 configuration/interface/endpoint descriptor register 25 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1017 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002001FAH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE26 R/W Undefined UF0CIE27 R/W Undefined UF0CIE28 R/W Undefined UF0CIE29 R/W Undefined UF0CIE30 R/W Undefined UF0CIE31 R/W Undefined UF0CIE32 R/W Undefined UF0CIE33 R/W Undefined UF0CIE34 R/W Undefined UF0CIE35 R/W Undefined UF0CIE36 R/W Undefined UF0CIE37 R/W Undefined UF0CIE38 R/W Undefined UF0CIE39 R/W Undefined UF0CIE40 R/W Undefined UF0CIE41 R/W Undefined UF0CIE42 R/W Undefined UF0CIE43 R/W Undefined UF0CIE44 R/W Undefined UF0CIE45 R/W Undefined UF0CIE46 R/W Undefined UF0CIE47 R/W Undefined register 26 002001FCH UF0 configuration/interface/endpoint descriptor register 27 002001FEH UF0 configuration/interface/endpoint descriptor register 28 00200200H UF0 configuration/interface/endpoint descriptor register 29 00200202H UF0 configuration/interface/endpoint descriptor register 30 00200204H UF0 configuration/interface/endpoint descriptor register 31 00200206H UF0 configuration/interface/endpoint descriptor register 32 00200208H UF0 configuration/interface/endpoint descriptor register 33 0020020AH UF0 configuration/interface/endpoint descriptor register 34 0020020CH UF0 configuration/interface/endpoint descriptor register 35 0020020EH UF0 configuration/interface/endpoint descriptor register 36 00200210H UF0 configuration/interface/endpoint descriptor register 37 00200212H UF0 configuration/interface/endpoint descriptor register 38 00200214H UF0 configuration/interface/endpoint descriptor register 39 00200216H UF0 configuration/interface/endpoint descriptor register 40 00200218H UF0 configuration/interface/endpoint descriptor register 41 0020021AH UF0 configuration/interface/endpoint descriptor register 42 0020021CH UF0 configuration/interface/endpoint descriptor register 43 0020021EH UF0 configuration/interface/endpoint descriptor register 44 00200220H UF0 configuration/interface/endpoint descriptor register 45 00200222H UF0 configuration/interface/endpoint descriptor register 46 00200224H UF0 configuration/interface/endpoint descriptor register 47 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1018 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200226H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE48 R/W Undefined UF0CIE49 R/W Undefined UF0CIE50 R/W Undefined UF0CIE51 R/W Undefined UF0CIE52 R/W Undefined UF0CIE53 R/W Undefined UF0CIE54 R/W Undefined UF0CIE55 R/W Undefined UF0CIE56 R/W Undefined UF0CIE57 R/W Undefined UF0CIE58 R/W Undefined UF0CIE59 R/W Undefined UF0CIE60 R/W Undefined UF0CIE61 R/W Undefined UF0CIE62 R/W Undefined UF0CIE63 R/W Undefined UF0CIE64 R/W Undefined UF0CIE65 R/W Undefined UF0CIE66 R/W Undefined UF0CIE67 R/W Undefined UF0CIE68 R/W Undefined UF0CIE69 R/W Undefined register 48 00200228H UF0 configuration/interface/endpoint descriptor register 49 0020022AH UF0 configuration/interface/endpoint descriptor register 50 0020022CH UF0 configuration/interface/endpoint descriptor register 51 0020022EH UF0 configuration/interface/endpoint descriptor register 52 00200230H UF0 configuration/interface/endpoint descriptor register 53 00200232H UF0 configuration/interface/endpoint descriptor register 54 00200234H UF0 configuration/interface/endpoint descriptor register 55 00200236H UF0 configuration/interface/endpoint descriptor register 56 00200238H UF0 configuration/interface/endpoint descriptor register 57 0020023AH UF0 configuration/interface/endpoint descriptor register 58 0020023CH UF0 configuration/interface/endpoint descriptor register 59 0020023EH UF0 configuration/interface/endpoint descriptor register 60 00200240H UF0 configuration/interface/endpoint descriptor register 61 00200242H UF0 configuration/interface/endpoint descriptor register 62 00200244H UF0 configuration/interface/endpoint descriptor register 63 00200246H UF0 configuration/interface/endpoint descriptor register 64 00200248H UF0 configuration/interface/endpoint descriptor register 65 0020024AH UF0 configuration/interface/endpoint descriptor register 66 0020024CH UF0 configuration/interface/endpoint descriptor register 67 0020024EH UF0 configuration/interface/endpoint descriptor register 68 00200250H UF0 configuration/interface/endpoint descriptor register 69 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1019 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (5/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200252H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE70 R/W Undefined UF0CIE71 R/W Undefined UF0CIE72 R/W Undefined UF0CIE73 R/W Undefined UF0CIE74 R/W Undefined UF0CIE75 R/W Undefined UF0CIE76 R/W Undefined UF0CIE77 R/W Undefined UF0CIE78 R/W Undefined UF0CIE79 R/W Undefined UF0CIE80 R/W Undefined UF0CIE81 R/W Undefined UF0CIE82 R/W Undefined UF0CIE83 R/W Undefined UF0CIE84 R/W Undefined UF0CIE85 R/W Undefined UF0CIE86 R/W Undefined UF0CIE87 R/W Undefined UF0CIE88 R/W Undefined UF0CIE89 R/W Undefined UF0CIE90 R/W Undefined UF0CIE91 R/W Undefined register 70 00200254H UF0 configuration/interface/endpoint descriptor register 71 00200256H UF0 configuration/interface/endpoint descriptor register 72 00200258H UF0 configuration/interface/endpoint descriptor register 73 0020025AH UF0 configuration/interface/endpoint descriptor register 74 0020025CH UF0 configuration/interface/endpoint descriptor register 75 0020025EH UF0 configuration/interface/endpoint descriptor register 76 00200260H UF0 configuration/interface/endpoint descriptor register 77 00200262H UF0 configuration/interface/endpoint descriptor register 78 00200264H UF0 configuration/interface/endpoint descriptor register 79 00200266H UF0 configuration/interface/endpoint descriptor register 80 00200268H UF0 configuration/interface/endpoint descriptor register 81 0020026AH UF0 configuration/interface/endpoint descriptor register 82 0020026CH UF0 configuration/interface/endpoint descriptor register 83 0020026EH UF0 configuration/interface/endpoint descriptor register 84 00200270H UF0 configuration/interface/endpoint descriptor register 85 00200272H UF0 configuration/interface/endpoint descriptor register 86 00200274H UF0 configuration/interface/endpoint descriptor register 87 00200276H UF0 configuration/interface/endpoint descriptor register 88 00200278H UF0 configuration/interface/endpoint descriptor register 89 0020027AH UF0 configuration/interface/endpoint descriptor register 90 0020027CH UF0 configuration/interface/endpoint descriptor register 91 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1020 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (6/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020027EH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE92 R/W Undefined UF0CIE93 R/W Undefined UF0CIE94 R/W Undefined UF0CIE95 R/W Undefined UF0CIE96 R/W Undefined UF0CIE97 R/W Undefined UF0CIE98 R/W Undefined UF0CIE99 R/W Undefined UF0CIE100 R/W Undefined UF0CIE101 R/W Undefined UF0CIE102 R/W Undefined UF0CIE103 R/W Undefined UF0CIE104 R/W Undefined UF0CIE105 R/W Undefined UF0CIE106 R/W Undefined UF0CIE107 R/W Undefined UF0CIE108 R/W Undefined UF0CIE109 R/W Undefined UF0CIE110 R/W Undefined UF0CIE111 R/W Undefined UF0CIE112 R/W Undefined UF0CIE113 R/W Undefined register 92 00200280H UF0 configuration/interface/endpoint descriptor register 93 00200282H UF0 configuration/interface/endpoint descriptor register 94 00200284H UF0 configuration/interface/endpoint descriptor register 95 00200286H UF0 configuration/interface/endpoint descriptor register 96 00200288H UF0 configuration/interface/endpoint descriptor register 97 0020028AH UF0 configuration/interface/endpoint descriptor register 98 0020028CH UF0 configuration/interface/endpoint descriptor register 99 0020028EH UF0 configuration/interface/endpoint descriptor register 100 00200290H UF0 configuration/interface/endpoint descriptor register 101 00200292H UF0 configuration/interface/endpoint descriptor register 102 00200294H UF0 configuration/interface/endpoint descriptor register 103 00200296H UF0 configuration/interface/endpoint descriptor register 104 00200298H UF0 configuration/interface/endpoint descriptor register 105 0020029AH UF0 configuration/interface/endpoint descriptor register 106 0020029CH UF0 configuration/interface/endpoint descriptor register 107 0020029EH UF0 configuration/interface/endpoint descriptor register 108 002002A0H UF0 configuration/interface/endpoint descriptor register 109 002002A2H UF0 configuration/interface/endpoint descriptor register 110 002002A4H UF0 configuration/interface/endpoint descriptor register 111 002002A6H UF0 configuration/interface/endpoint descriptor register 112 002002A8H UF0 configuration/interface/endpoint descriptor register 113 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1021 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (7/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002002AAH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE114 R/W Undefined UF0CIE115 R/W Undefined UF0CIE116 R/W Undefined UF0CIE117 R/W Undefined UF0CIE118 R/W Undefined UF0CIE119 R/W Undefined UF0CIE120 R/W Undefined UF0CIE121 R/W Undefined UF0CIE122 R/W Undefined UF0CIE123 R/W Undefined UF0CIE124 R/W Undefined UF0CIE125 R/W Undefined UF0CIE126 R/W Undefined UF0CIE127 R/W Undefined UF0CIE128 R/W Undefined UF0CIE129 R/W Undefined UF0CIE130 R/W Undefined UF0CIE131 R/W Undefined UF0CIE132 R/W Undefined UF0CIE133 R/W Undefined UF0CIE134 R/W Undefined UF0CIE135 R/W Undefined register 114 002002ACH UF0 configuration/interface/endpoint descriptor register 115 002002AEH UF0 configuration/interface/endpoint descriptor register 116 002002B0H UF0 configuration/interface/endpoint descriptor register 117 002002B2H UF0 configuration/interface/endpoint descriptor register 118 002002B4H UF0 configuration/interface/endpoint descriptor register 119 002002B6H UF0 configuration/interface/endpoint descriptor register 120 002002B8H UF0 configuration/interface/endpoint descriptor register 121 002002BAH UF0 configuration/interface/endpoint descriptor register 122 002002BCH UF0 configuration/interface/endpoint descriptor register 123 002002BEH UF0 configuration/interface/endpoint descriptor register 124 002002C0H UF0 configuration/interface/endpoint descriptor register 125 002002C2H UF0 configuration/interface/endpoint descriptor register 126 002002C4H UF0 configuration/interface/endpoint descriptor register 127 002002C6H UF0 configuration/interface/endpoint descriptor register 128 002002C8H UF0 configuration/interface/endpoint descriptor register 129 002002CAH UF0 configuration/interface/endpoint descriptor register 130 002002CCH UF0 configuration/interface/endpoint descriptor register 131 002002CEH UF0 configuration/interface/endpoint descriptor register 132 002002D0H UF0 configuration/interface/endpoint descriptor register 133 002002D2H UF0 configuration/interface/endpoint descriptor register 134 002002D4H UF0 configuration/interface/endpoint descriptor register 135 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1022 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (8/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002002D6H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE136 R/W Undefined UF0CIE137 R/W Undefined UF0CIE138 R/W Undefined UF0CIE139 R/W Undefined UF0CIE140 R/W Undefined UF0CIE141 R/W Undefined UF0CIE142 R/W Undefined UF0CIE143 R/W Undefined UF0CIE144 R/W Undefined UF0CIE145 R/W Undefined UF0CIE146 R/W Undefined UF0CIE147 R/W Undefined UF0CIE148 R/W Undefined UF0CIE149 R/W Undefined UF0CIE150 R/W Undefined UF0CIE151 R/W Undefined UF0CIE152 R/W Undefined UF0CIE153 R/W Undefined UF0CIE154 R/W Undefined UF0CIE155 R/W Undefined UF0CIE156 R/W Undefined UF0CIE157 R/W Undefined register 136 002002D8H UF0 configuration/interface/endpoint descriptor register 137 002002DAH UF0 configuration/interface/endpoint descriptor register 138 002002DCH UF0 configuration/interface/endpoint descriptor register 139 002002DEH UF0 configuration/interface/endpoint descriptor register 140 002002E0H UF0 configuration/interface/endpoint descriptor register 141 002002E2H UF0 configuration/interface/endpoint descriptor register 142 002002E4H UF0 configuration/interface/endpoint descriptor register 143 002002E6H UF0 configuration/interface/endpoint descriptor register 144 002002E8H UF0 configuration/interface/endpoint descriptor register 145 002002EAH UF0 configuration/interface/endpoint descriptor register 146 002002ECH UF0 configuration/interface/endpoint descriptor register 147 002002EEH UF0 configuration/interface/endpoint descriptor register 148 002002F0H UF0 configuration/interface/endpoint descriptor register 149 002002F2H UF0 configuration/interface/endpoint descriptor register 150 002002F4H UF0 configuration/interface/endpoint descriptor register 151 002002F6H UF0 configuration/interface/endpoint descriptor register 152 002002F8H UF0 configuration/interface/endpoint descriptor register 153 002002FAH UF0 configuration/interface/endpoint descriptor register 154 002002FCH UF0 configuration/interface/endpoint descriptor register 155 002002FEH UF0 configuration/interface/endpoint descriptor register 156 00200300H UF0 configuration/interface/endpoint descriptor register 157 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1023 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (9/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200302H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE158 R/W Undefined UF0CIE159 R/W Undefined UF0CIE160 R/W Undefined UF0CIE161 R/W Undefined UF0CIE162 R/W Undefined UF0CIE163 R/W Undefined UF0CIE164 R/W Undefined UF0CIE165 R/W Undefined UF0CIE166 R/W Undefined UF0CIE167 R/W Undefined UF0CIE168 R/W Undefined UF0CIE169 R/W Undefined UF0CIE170 R/W Undefined UF0CIE171 R/W Undefined UF0CIE172 R/W Undefined UF0CIE173 R/W Undefined UF0CIE174 R/W Undefined UF0CIE175 R/W Undefined UF0CIE176 R/W Undefined UF0CIE177 R/W Undefined UF0CIE178 R/W Undefined UF0CIE179 R/W Undefined register 158 00200304H UF0 configuration/interface/endpoint descriptor register 159 00200306H UF0 configuration/interface/endpoint descriptor register 160 00200308H UF0 configuration/interface/endpoint descriptor register 161 0020030AH UF0 configuration/interface/endpoint descriptor register 162 0020030CH UF0 configuration/interface/endpoint descriptor register 163 0020030EH UF0 configuration/interface/endpoint descriptor register 164 00200310H UF0 configuration/interface/endpoint descriptor register 165 00200312H UF0 configuration/interface/endpoint descriptor register 166 00200314H UF0 configuration/interface/endpoint descriptor register 167 00200316H UF0 configuration/interface/endpoint descriptor register 168 00200318H UF0 configuration/interface/endpoint descriptor register 169 0020031AH UF0 configuration/interface/endpoint descriptor register 170 0020031CH UF0 configuration/interface/endpoint descriptor register 171 0020031EH UF0 configuration/interface/endpoint descriptor register 172 00200320H UF0 configuration/interface/endpoint descriptor register 173 00200322H UF0 configuration/interface/endpoint descriptor register 174 00200324H UF0 configuration/interface/endpoint descriptor register 175 00200326H UF0 configuration/interface/endpoint descriptor register 176 00200328H UF0 configuration/interface/endpoint descriptor register 177 0020032AH UF0 configuration/interface/endpoint descriptor register 178 0020032CH UF0 configuration/interface/endpoint descriptor register 179 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1024 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (10/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020032EH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE180 R/W Undefined UF0CIE181 R/W Undefined UF0CIE182 R/W Undefined UF0CIE183 R/W Undefined UF0CIE184 R/W Undefined UF0CIE185 R/W Undefined UF0CIE186 R/W Undefined UF0CIE187 R/W Undefined UF0CIE188 R/W Undefined UF0CIE189 R/W Undefined UF0CIE190 R/W Undefined UF0CIE191 R/W Undefined UF0CIE192 R/W Undefined UF0CIE193 R/W Undefined UF0CIE194 R/W Undefined UF0CIE195 R/W Undefined UF0CIE196 R/W Undefined UF0CIE197 R/W Undefined UF0CIE198 R/W Undefined UF0CIE199 R/W Undefined UF0CIE200 R/W Undefined UF0CIE201 R/W Undefined register 180 00200330H UF0 configuration/interface/endpoint descriptor register 181 00200332H UF0 configuration/interface/endpoint descriptor register 182 00200334H UF0 configuration/interface/endpoint descriptor register 183 00200336H UF0 configuration/interface/endpoint descriptor register 184 00200338H UF0 configuration/interface/endpoint descriptor register 185 0020033AH UF0 configuration/interface/endpoint descriptor register 186 0020033CH UF0 configuration/interface/endpoint descriptor register 187 0020033EH UF0 configuration/interface/endpoint descriptor register 188 00200340H UF0 configuration/interface/endpoint descriptor register 189 00200342H UF0 configuration/interface/endpoint descriptor register 190 00200344H UF0 configuration/interface/endpoint descriptor register 191 00200346H UF0 configuration/interface/endpoint descriptor register 192 00200348H UF0 configuration/interface/endpoint descriptor register 193 0020034AH UF0 configuration/interface/endpoint descriptor register 194 0020034CH UF0 configuration/interface/endpoint descriptor register 195 0020034EH UF0 configuration/interface/endpoint descriptor register 196 00200350H UF0 configuration/interface/endpoint descriptor register 197 00200352H UF0 configuration/interface/endpoint descriptor register 198 00200354H UF0 configuration/interface/endpoint descriptor register 199 00200356H UF0 configuration/interface/endpoint descriptor register 200 00200358H UF0 configuration/interface/endpoint descriptor register 201 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1025 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (11/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 0020035AH UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE202 R/W Undefined UF0CIE203 R/W Undefined UF0CIE204 R/W Undefined UF0CIE205 R/W Undefined UF0CIE206 R/W Undefined UF0CIE207 R/W Undefined UF0CIE208 R/W Undefined UF0CIE209 R/W Undefined UF0CIE210 R/W Undefined UF0CIE211 R/W Undefined UF0CIE212 R/W Undefined UF0CIE213 R/W Undefined UF0CIE214 R/W Undefined UF0CIE215 R/W Undefined UF0CIE216 R/W Undefined UF0CIE217 R/W Undefined UF0CIE218 R/W Undefined UF0CIE219 R/W Undefined UF0CIE220 R/W Undefined UF0CIE221 R/W Undefined UF0CIE222 R/W Undefined UF0CIE223 R/W Undefined register 202 0020035CH UF0 configuration/interface/endpoint descriptor register 203 0020035EH UF0 configuration/interface/endpoint descriptor register 204 00200360H UF0 configuration/interface/endpoint descriptor register 205 00200362H UF0 configuration/interface/endpoint descriptor register 206 00200364H UF0 configuration/interface/endpoint descriptor register 207 00200366H UF0 configuration/interface/endpoint descriptor register 208 00200368H UF0 configuration/interface/endpoint descriptor register 209 0020036AH UF0 configuration/interface/endpoint descriptor register 210 0020036CH UF0 configuration/interface/endpoint descriptor register 211 0020036EH UF0 configuration/interface/endpoint descriptor register 212 00200370H UF0 configuration/interface/endpoint descriptor register 213 00200372H UF0 configuration/interface/endpoint descriptor register 214 00200374H UF0 configuration/interface/endpoint descriptor register 215 00200376H UF0 configuration/interface/endpoint descriptor register 216 00200378H UF0 configuration/interface/endpoint descriptor register 217 0020037AH UF0 configuration/interface/endpoint descriptor register 218 0020037CH UF0 configuration/interface/endpoint descriptor register 219 0020037EH UF0 configuration/interface/endpoint descriptor register 220 00200380H UF0 configuration/interface/endpoint descriptor register 221 00200382H UF0 configuration/interface/endpoint descriptor register 222 00200384H UF0 configuration/interface/endpoint descriptor register 223 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1026 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (12/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 00200386H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE224 R/W Undefined UF0CIE225 R/W Undefined UF0CIE226 R/W Undefined UF0CIE227 R/W Undefined UF0CIE228 R/W Undefined UF0CIE229 R/W Undefined UF0CIE230 R/W Undefined UF0CIE231 R/W Undefined UF0CIE232 R/W Undefined UF0CIE233 R/W Undefined UF0CIE234 R/W Undefined UF0CIE235 R/W Undefined UF0CIE236 R/W Undefined UF0CIE237 R/W Undefined UF0CIE238 R/W Undefined UF0CIE239 R/W Undefined UF0CIE240 R/W Undefined UF0CIE241 R/W Undefined UF0CIE242 R/W Undefined UF0CIE243 R/W Undefined UF0CIE244 R/W Undefined UF0CIE245 R/W Undefined register 224 00200388H UF0 configuration/interface/endpoint descriptor register 225 0020038AH UF0 configuration/interface/endpoint descriptor register 226 0020038CH UF0 configuration/interface/endpoint descriptor register 227 0020038EH UF0 configuration/interface/endpoint descriptor register 228 00200390H UF0 configuration/interface/endpoint descriptor register 229 00200392H UF0 configuration/interface/endpoint descriptor register 230 00200394H UF0 configuration/interface/endpoint descriptor register 231 00200396H UF0 configuration/interface/endpoint descriptor register 232 00200398H UF0 configuration/interface/endpoint descriptor register 233 0020039AH UF0 configuration/interface/endpoint descriptor register 234 0020039CH UF0 configuration/interface/endpoint descriptor register 235 0020039EH UF0 configuration/interface/endpoint descriptor register 236 002003A0H UF0 configuration/interface/endpoint descriptor register 237 002003A2H UF0 configuration/interface/endpoint descriptor register 238 002003A4H UF0 configuration/interface/endpoint descriptor register 239 002003A6H UF0 configuration/interface/endpoint descriptor register 240 002003A8H UF0 configuration/interface/endpoint descriptor register 241 002003AAH UF0 configuration/interface/endpoint descriptor register 242 002003ACH UF0 configuration/interface/endpoint descriptor register 243 002003AEH UF0 configuration/interface/endpoint descriptor register 244 002003B0H UF0 configuration/interface/endpoint descriptor register 245 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1027 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (13/13) Address Function Register Name Symbol R/W Manipulatable Bits 1 002003B2H UF0 configuration/interface/endpoint descriptor 8 Default Value 16 UF0CIE246 R/W Undefined UF0CIE247 R/W Undefined UF0CIE248 R/W Undefined UF0CIE249 R/W Undefined UF0CIE250 R/W Undefined UF0CIE251 R/W Undefined UF0CIE252 R/W Undefined UF0CIE253 R/W Undefined UF0CIE254 R/W Undefined UF0CIE255 R/W Undefined register 246 002003B4H UF0 configuration/interface/endpoint descriptor register 247 002003B6H UF0 configuration/interface/endpoint descriptor register 248 002003B8H UF0 configuration/interface/endpoint descriptor register 249 002003BAH UF0 configuration/interface/endpoint descriptor register 250 002003BCH UF0 configuration/interface/endpoint descriptor register 251 002003BEH UF0 configuration/interface/endpoint descriptor register 252 002003C0H UF0 configuration/interface/endpoint descriptor register 253 002003C2H UF0 configuration/interface/endpoint descriptor register 254 002003C4H UF0 configuration/interface/endpoint descriptor register 255 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1028 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) Bridge register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200400H Bridge interrupt control register BRGINTT R/W 0000H 00200402H Bridge interrupt enable register BRGINTE R/W 0000H 00200404H EPC macro control register EPCCLT R/W 0000H 00200408H CPU I/F bus control register CPUBCTL R/W 0000H (5) DMA register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00200500H EP1 DMA control register 1 UF0E1DC1 R/W 0000H 00200502H EP1 DMA control register 2 UF0E1DC2 R/W 0000H 00200504H EP2 DMA control register 1 UF0E2DC1 R/W 0000H 00200506H EP2 DMA control register 2 UF0E2DC2 R/W 0000H 00200508H EP3 DMA control register 1 UF0E3DC1 R/W 0000H 0020050AH EP3 DMA control register 2 UF0E3DC2 R/W 0000H 0020050CH EP4 DMA control register 1 UF0E4DC1 R/W 0000H 0020050EH EP4 DMA control register 2 UF0E4DC2 R/W 0000H (6) Bulk-in register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 Default Value 16 00201000H UF0 EP1 bulk-in transfer data register UF0EP1BI W 0000H 00202000H UF0 EP3 bulk-in transfer data register UF0EP3BI W 0000H (7) Bulk-out register Address Function Register Name Symbol R/W Manipulatable Bits 1 8 16 Default Value 00210000H UF0 EP2 bulk-out transfer data register UF0EP2BO R 0000H 00220000H UF0 EP4 bulk-out transfer data register UF0EP4BO R 0000H (8) Peripheral control register Address Function Register Name Symbol R/W Manipulatable Bits 1 00240000H USBF DMA request enable register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 UFDRQEN R/W 8 16 Default Value 0000H Page 1029 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.4 EPC control registers (1) UF0 EP0NAK register (UF0E0N) This register controls NAK of Endpoint0 (except an automatically executed request). This register can be read or written in 8-bit units (however, bit 0 can only be read). It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the EP0NKR bit is ignored. UF0E0N Bit position 1 7 6 5 4 3 2 0 0 0 0 0 0 Bit name EP0NKR 1 0 EP0NKR EP0NKW Address After reset 00200000H 00H Function This bit controls NAK to the OUT token to Endpoint0 (except an automatically executed request). It is automatically set to 1 by hardware when Endpoint0 has correctly received data. It is also cleared to 0 by hardware when the data of the UF0E0R register has been read by FW (counter value = 0). 1: Transmit NAK. 0: Do not transmit NAK (default value). Set this bit to 1 by FW when data should not be received from the USB bus for some reason even when USBF is ready for receiving data. In this case, USBF continues transmitting NAK until this bit is cleared to 0 by FW. This bit is also cleared to 0 as soon as the UF0E0R register has been cleared. 0 EP0NKW This bit indicates how NAK to the IN token to Endpoint0 is controlled (except an automatically executed request). This bit is automatically cleared to 0 by hardware when the data of Endpoint0 is transmitted and the host correctly receives the transmitted data. The data of the UF0E0W register is retained until this bit is cleared. Therefore, it is not necessary to rewrite this bit even in the case of a retransmission request that is made if the host could not receive data correctly. To send a short packet, be sure to set the E0DED bit of the UF0DEND register to 1. This bit is automatically set to 1 when the FIFO is full. As soon as the E0DED bit of the UF0DEND register is set to 1, the EP0NKW bit is automatically set to 1 at the same time. 1: Do not transmit NAK. 0: Transmit NAK (default value). If control transfer enters the status stage while ACK cannot be correctly received in the data stage, this bit is cleared to 0 as soon as the UF0E0W register is cleared. This bit is also cleared to 0 when UF0E0W is cleared by FW. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1030 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Next, the procedure of a SETUP transaction that uses IN/OUT tokens is explained below. (a) When IN token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register to 0 after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register. Next, perform processing in accordance with the request and, if it is necessary to return data by an IN token, write data to the UF0E0W register. Confirm that the PROT bit of the UF0IS1 register is 0 after writing has been completed, and set the E0DED bit of the UF0DEND register to 1. The hardware sends out data at the first IN token after the EP0NKW bit has been set to 1. If the PROT bit of the UF0IS1 register is 1, it indicates that a SETUP transaction has occurred again before completion of control transfer. In this case, clear the PROT bit of the UF0IS1 register to 0 by clearing the PROTC bit of the UF0IC1 register to 0, and then read data from the UF0E0ST register again. A request received later can be read. (b) When OUT token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register. Confirm that the PROT bit of the UF0IS1 register is 0 before reading data from the UF0E0R register. If the PROT bit is 1, it means that invalid data is retained. Clear the FIFO by FW (the EP0NKR bit is automatically cleared to 0). If the PROT bit of the UF0IS1 register is 0, read the data of the UF0E0L register and read as many data from the UF0E0R register as set. When reading data from the UF0E0R register has been completed (when the counter of the UF0E0R register has been cleared to 0), the hardware automatically clears the EP0NKR bit to 0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1031 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0NAKALL register (UF0E0NA) This register controls NAK to all the requests of Endpoint0. It is also valid for automatically executed requests. This register can be read or written in 8-bit units. UF0E0NA Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 EP0NKA 00200002H 00H Bit name EP0NKA Function This bit controls NAK to a transaction other than a SETUP transaction to Endpoint0 (including an automatically executed request). This bit is manipulated by FW. 1: Transmit NAK. 0: Do not transmit NAK (default value). This register is used to prevent a conflict between a write access by FW and a read access from SIE when the data used for an automatically executed request is to be changed. It postpones reflecting a write access on this bit from FW while an access from SIE is being made. Before rewriting the request data register from FW, confirm that this bit has been correctly set to 1. Setting this bit to 1 is reflected only in the following cases. * Immediately after USBF has been reset and a SETUP token has never been received * Immediately after reception of Bus Reset and a SETUP token has never been received * PID of a SETUP token has been detected * The stage has been changed to the status stage Clearing this bit to 0 is reflected immediately, except while an IN token is being received and a NAK response is being made. Setting the EP0NKA bit to 1 is reflected in the above four cases during Endpoint0 transfer, but it is reflected immediately after data has been written to the bit while Endpoint0 is transferring no data. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1032 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) UF0 EPNAK register (UF0EN) This register controls NAK of endpoints other than Endpoint0. This register can be read or written in 8-bit units (however, bits 4, 1, and 0 can only be read). The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit can be written only when the BKO1NKM bit of the UF0ENM register is 1. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the BKO1NK and BKO2NK bits is ignored. Be sure to clear bits 7 to 5 to "0". If it is set to 1, the operation is not guaranteed. (1/4) UF0EN Bit position 4 7 6 5 4 0 0 0 IT1NK 3 2 BKO2NK BKO1NK Bit name IT1NK 1 0 Address After reset BKI2NK BKI1NK 00200004H 00H Function This bit controls NAK to Endpoint7 (interrupt 1 transfer). It is automatically set to 1 and transmission is started when the UF0INT1 register has become full as a result of writing data to it. To send a short packet that does not make the FIFO full, set the IT1DEND bit of the UF0DEND register to 1. As soon as the IT1DEND bit has been set to 1, this bit is automatically set to 1. 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is also cleared to 0 when the UF0INT1 register has been cleared. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1033 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/4) Bit position 3 Bit name BKO2NK Function This bit controls NAK to Endpoint4 (bulk 2 transfer (OUT)). 1: Transmit NAK. 0: Do not transmit NAK (default value). This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO2 register (64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle operation is performed. The bank is changed (toggle operation) when the following conditions are satisfied. * Data correctly received is stored in the FIFO connected to the SIE side. * The value of the FIFO counter connected to the CPU side is 0 (completion of reading). FW should be used to read data of the UF0BO2L register when it has received the BLKO2DT interrupt request and read as many data from the UF0BO2 register as the value of that data. To not receive data from the USB bus for some reason even if USBF is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO2 register has been cleared. 2 BKO1NK This bit controls NAK to Endpoint2 (bulk 1 transfer (OUT)). 1: Transmit NAK. 0: Do not transmit NAK (default value). This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO1 register (64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle operation is performed. The bank is changed (toggle operation) when the following conditions are satisfied. * Data correctly received is stored in the FIFO connected to the SIE side. * The value of the FIFO counter connected to the CPU side is 0 (completion of reading). FW should be used to read data of the UF0BO1L register when it has received the BLKO1DT interrupt request and read as many data from the UF0BO1 register as the value of that data. To not receive data from the USB bus for some reason even if USBF is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO1 register has been cleared. Cautions 1. If DMA is enabled while data is being read from the UF0BO2 register in the PIO mode, a DMA request is immediately issued. 2. If the last data of the FIFO on the CPU side is read in the DMA transfer mode, the DMA request signal becomes inactive. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1034 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3/4) Bit position 1 Bit name BKI2NK Function This bit controls NAK to Endpoint3 (bulk 2 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI2 register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a toggle operation is performed (the data of the UF0BI2 register is retained until transmission has been correctly completed). The bank is changed (toggle operation) when the following conditions are satisfied. * Data is correctly written to the FIFO connected to the CPU bus side (writing has been completed and the FIFO is full or the UF0DEND register is set). * The value of the FIFO counter connected to the SIE side is 0. This bit is automatically set to 1 and data transmission is started when the FIFO on the CPU side becomes full and a FIFO toggle operation is performed as a result of writing data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing data to it by DMA while the BKI2T bit of the UF0DEND register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the BKI2DED bit of the UF0DEND register is set to 1. To send a short packet that does not make the FIFO on the CPU side full, set the BKI2DED bit to 1 after completing writing data. When the BKI2DED bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the UF0BI2 register has been cleared. Cautions 1. If DMA is enabled while data is being written to the UF0BI2 register in the PIO mode, a DMA request is immediately issued. 2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes inactive. If the BKI2NK bit is then set to 1, data is transmitted in synchronization with an IN token. The DMA request signal becomes active again as long as the DMA request is not masked as soon as the FIFO is toggled. If the BKI2NK bit is not set, data is not transmitted even if an IN token has been received. In this case, set the BKI2DED bit of the UF0DEND register to 1. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. At the same time, the DMA request is masked. If the BKI2NK bit is not set to 1, data is not transmitted even if an IN token is received. When the BKI2DED bit of the UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN token. To execute DMA transfer again, unmask the DMA request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1035 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4/4) Bit position 0 Bit name BKI1NK Function This bit controls NAK to Endpoint1 (bulk 1 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI1 register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a toggle operation is performed (the data of the UF0BI1 register is retained until transmission has been correctly completed). The bank is changed (toggle operation) when the following conditions are satisfied. * Data is correctly written to the FIFO connected to the CPU bus side (writing has been completed and the FIFO is full or the UF0DEND register is set). * The value of the FIFO counter connected to the SIE side is 0. This bit is automatically set to 1 and data transmission is started when the FIFO on the CPU side becomes full and a FIFO toggle operation is performed as a result of writing data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing data to it by DMA while the BKI1T bit of the UF0DEND register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the BKI1DED bit of the UF0DEND register is set to 1. To send a short packet that does not make the FIFO on the CPU side full, set the BKI1DED bit to 1 after completing writing data. When the BKI1DED bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the UF0BI1 register has been cleared. Cautions 1. If DMA is enabled while data is being written to the UF0BI1 register in the PIO mode, a DMA request is immediately issued. 2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes inactive. If the BKI1NK bit is then set to 1, data is transmitted in synchronization with an IN token. The DMA request signal becomes active again as long as the DMA request is not masked as soon as the FIFO is toggled. If the BKI1NK bit is not set, data is not transmitted even if an IN token has been received. In this case, set the BKI1DED bit of the UF0DEND register to 1. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. At the same time, the DMA request is masked. If the BKI1NK bit is not set to 1, data is not transmitted even if an IN token is received. When the BKI1DED bit of the UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN token. To execute DMA transfer again, unmask the DMA request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1036 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) UF0 EPNAK mask register (UF0ENM) This register controls masking a write access to the UF0EN register. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 4, 1, and 0 to "0". If it is set to 1, the operation is not guaranteed. UF0ENM Bit position 3 7 6 5 4 0 0 0 0 3 BKO2NKM BKO1NKM Bit name BKO2NKM 2 1 0 Address After reset 0 0 00200006H 00H Function This bit specifies whether a write access to bit 3 (BKO2NK) of the UF0EN register is masked or not. 1: Do not mask. 0: Mask (default value). 2 BKO1NKM This bit specifies whether a write access to bit 2 (BKO1NK) of the UF0EN register is masked or not. 1: Do not mask. 0: Mask (default value). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1037 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (5) UF0 SNDSIE register (UF0SDS) This register performs manipulation such as no handshake. It can directly manipulate the pins of SIE. This register can be read or written in 8-bit units. Be sure to clear bit 2 to "0". If it is set to 1, the operation is not guaranteed. UF0SDS Bit position 3 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 SNDSTL 0 0 RSUMIN 00200008H 00H Bit name SNDSTL Function This bit makes Endpoint0 issue a STALL handshake. Setting this bit to 1 if a request for CPUDEC processing is not supported by the system results in a STALL handshake response. If an unsupported wValue is sent by the SET_CONFIGURATION or SET_INTERFACE request, the hardware sets this bit to 1. If a problem occurs in Endpoint0 due to overrun of an automatically executed request, this bit is also set to 1. However, the E0HALT bit of the UF0E0SL register is not set to 1. 1: Respond with STALL handshake. 0: Do not respond with STALL handshake (default value). This bit is cleared to 0 and the handshake response to the bus is other than STALL when the next SETUP token is received. To set the SNDSTL bit to 1 by FW, do not write data to the UF0E0W register. Depending on the timing of setting this bit, the STALL response is not made in time, and it may be made to the next transfer after a NAK response has been made. Setting this bit is valid only while an FW-executed request is under execution when this bit is set to 1. It is automatically cleared to 0 when the next SETUP token is received. Remark The SNDSTL bit is valid only for an FW-executed request. 0 RSUMIN This bit outputs the Resume signal onto the USB bus. Writing this bit is invalid unless the RMWK bit of the UF0DSTL register is set to 1. 1: Generate the Resume signal. 0: Do not generate the Resume signal (default value). While this bit is set to 1, the Resume signal continues to be generated. Clear this bit to 0 by FW after a specific time has elapsed. Because the signal is internally sampled at the clock, the operation is guaranteed only while CLK is supplied. Care must be exercised when CLK of the system is stopped. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1038 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (6) UF0 CLR request register (UF0CLR) This register indicates the target of the received CLEAR_FEATURE request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. 7 UF0CLR 0 Bit position 6 to 1 6 4 5 3 2 1 0 CLREP7 CLREP4 CLREP3 CLREP2 CLREP1 CLREP0 CLRDEV Bit name CLREPn Address After reset 0020000AH 00H Function These bits indicate that a CLEAR_FEATURE Endpoint n request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 0 CLRDEV This bit indicates that a CLEAR_FEATURE Device request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) Remark n = 0 to 4, 7 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1039 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (7) UF0 SET request register (UF0SET) This register indicates the target of the automatically processed SET_XXXX (except SET_INTERFACE) request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. 7 UF0SET SETCON Bit position 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 SETEP 0 SETDEV 0020000CH 00H Bit name SETCON Function This bit indicates that a SET_CONFIGURATION request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 2 SETEP This bit indicates that a SET_FEATURE Endpoint n request (n = 0 to 4, 7) is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 0 SETDEV This bit indicates that a SET_FEATURE Device request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1040 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (8) UF0 EP status 0 register (UF0EPS0) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate writing to the UF0FIC0 and UF0FIC1 registers from reading from the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. (1/2) UF0EPS0 7 6 0 IT1 Bit position 6 5 4 BKOUT2 BKOUT1 3 2 1 0 Address After reset BKIN2 BKIN1 EP0W EP0R 0020000EH 00H Bit name IT1 Function These bits indicate that data is in the UF0INT1 register (FIFO). By setting the IT1DEND bit of the UF0DEND register to 1, the status in which data is in the UF0INT1 register can be created even if data is not written to the register (Null data transmission). As soon as the IT1DEND bit of the UF0DEND register is set to 1 even when the counter of the UF0INT1 register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct transmission. 1: Data is in the register. 0: No data is in the register (default value). 5, 4 BKOUTn These bits indicate that data is in the UF0BOn register (FIFO) connected to the CPU side. When the FIFO configuring the UF0BOn register is toggled, this bit is automatically set to 1 by hardware. It is automatically cleared to 0 by hardware when reading the UF0BOn register (FIFO) connected to the CPU side has been completed (counter value = 0). It is not set to 1 when Null data is received (toggling the FIFO does not take place either). 1: Data is in the register. 0: No data is in the register (default value). 3, 2 BKINn These bits indicate that data is in the UF0BIn register (FIFO) connected to the CPU side. By setting the BKInDED bit of the UF0DEND register to 1, the status in which data is in the UF0BIn register can be created even if data is not written to the register (Null data transmission). As soon as the BKInDED bit of the UF0DEND register has been set to 1 while the counter of the UF0BIn register is 0, this bit is set to 1 by hardware. It is cleared to 0 when a toggle operation is performed. 1: Data is in the register. 0: No data is in the register (default value). Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1041 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1 Bit name EP0W Function This bit indicates that data is in the UF0E0W register (FIFO). By setting the E0DED bit of the UF0DEND register to 1, the status in which data is in the UF0E0W register can be created even if data is not written to the register (Null data transmission). As soon as the E0DED bit of the UF0DEND register is set to 1 even when the counter of the UF0E0W register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct transmission. 1: Data is in the register. 0: No data is in the register (default value). 0 EP0R This bit indicates that data is in the UF0E0R register (FIFO). It is automatically cleared to 0 by hardware when reading the UF0E0R register (FIFO) has been completed (counter value = 0). It is not set to 1 if Null data is received. 1: Data is in the register. 0: No data is in the register (default value). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1042 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (9) UF0 EP status 1 register (UF0EPS1) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. UF0EPS1 7 6 5 4 3 2 1 0 Address After reset RSUM 0 0 0 0 0 0 0 00200010H 00H Bit position 7 Bit name RSUM Function This bit indicates that the USB bus is in the Resume status. This bit is meaningful only when an interrupt request is generated. 1: Suspend status 0: Resume status (default value) Because sampling is internally performed with the clock, the operation is guaranteed only when CLK is supplied. Care must be exercised when CLK of the system is stopped. The INTUSBF1 signal of SIE operates even when CLK is stopped. It can therefore be supported by making the interrupt control register (UFIC1) valid or lowering the frequency of CLK to the USBF. This bit is automatically cleared to 0 when it is read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1043 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (10) UF0 EP status 2 register (UF0EPS2) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. UF0EPS2 Bit position 5 to 0 7 6 5 4 3 2 1 0 Address After reset 0 0 HALT7 HALT4 HALT3 HALT2 HALT1 HALT0 00200012H 00H Bit name HALTn Function These bits indicate that Endpoint n is currently stalled. They are set to 1 when a stall condition, such as occurrence of an overrun and reception of an undefined request, is satisfied. These bits are automatically set to 1 by hardware. 1: Endpoint is stalled. 0: Endpoint is not stalled (default value). The SNDSTL bit is set to 1 as soon as the HALT0 bit has been set to 1 as a result of occurrence of an overrun or reception of an undefined request. If the next SETUP token is received in this status, the SNDSTL bit is cleared to 0 and, therefore, the HALT0 bit is also cleared to 0. If Endpoint0 is stalled by the SET_FEATURE Endpoint0 request, this bit is not cleared to 0 until the CLEAR_FEATURE Endpoint0 request is received or Halt Feature is cleared by FW. If the GET_STATUS Endpoint0, CLEAR_FEATURE Endpoint0, or SET_FEATURE Endpoint0 request is received, or if a request to be processed by FW is received due to the CPUDEC interrupt request, the HALT0 bit is masked and cleared to 0, until the next SETUP token is received. The HALTn bit is not cleared to 0 until Endpoint n receives the CLEAR_FEATURE Endpoint request, Halt Feature is cleared by the SET_INTERFACE or SET_CONFIGURATION request to the interface to which the endpoint is linked, or Halt Feature is cleared by FW. When the SET_INTERFACE or SET_CONFIGURATION request is correctly processed, the Halt Feature of all the target endpoints, except Endpoint0, is cleared after the request has been processed, even if the wValue is the same as the currently set value, and these bits are also cleared to 0. Halt Feature of Endpoint0 cannot be cleared if it is set because the STALL response is made in response to the SET_INTERFACE and SET_CONFIGURATION requests. Remark n = 0 to 4, 7, 8 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1044 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (11) UF0 INT status 0 register (UF0IS0) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC0 register. Caution In the USBF, multiple interrupt sources, such as Bus Reset, Resume, and Short, are ORed internally and are issued as a single interrupt request (INTUSBF0). Therefore, in the case of the occurrence of multiple interrupt sources, they are ORed and issued as an INTUSBF0 interrupt request. For example, if a Bus Reset interrupt source and Resume interrupt source occur, the two sources are ORed and an INTUSBF0 interrupt request is issued. Under these conditions, if the Bus Reset interrupt source is cleared to 0 (UF0IC0.BUSRSTC = 0), the V850ES/JC3-H or V850ES/JE3-H internal INTUSBF0 interrupt request may remain set to 1 since the Resume interrupt source will still remain. The new interrupt request flag (US0BIC.US0BIF), therefore, might not be set to 1. In this case, after performing clear processing for each interrupt request with the INTUSBF0 interrupt servicing routine, confirm the flag status for the UF0IS0 and UF0IS1 registers again, and if there are any interrupt sources with flags set to 1, perform flag clearing (only the applicable bits need to be cleared (do not perform a batch clearing)). (1/2) 7 6 UF0IS0 BUSRST RSUSPD Bit position 7 5 4 3 2 1 0 Address After reset 0 SHORT DMAED SETRQ CLRRQ EPHALT 00200020H 00H Bit name BUSRST Function This bit indicates that Bus Reset has occurred. 1: Bus Reset has occurred (interrupt request is generated). 0: Not Bus Reset status (default value) 6 RSUSPD This bit indicates that the Resume or Suspend status has occurred. Reference bit 7 of the UF0EPS1 register by FW. 1: Resume or Suspend status has occurred (interrupt request is generated). 0: Resume or Suspend status has not occurred (default value). 4 SHORT This bit indicates that data is read from the FIFO of either the UF0BO1 or UF0BO2 register and that the USBSPnB signal (n = 2, 4) is active. It is valid only when the FIFO is full in the DMA mode. 1: USBSPnB signal is active (interrupt request is generated). 0: USBSPnB signal is not active (default value). Identify on which endpoint the operation is performed, by using the UF0DMS1 register. This bit is not automatically cleared to 0 even when the UF0DMS1 register is read by FW. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1045 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 3 Bit name DMAED Function This bit indicates that the DMA end (TC) signal for Endpoint n (n = 1 to 4, 7) is active. 1: DMA end signal for Endpoint n has been input (interrupt request is generated). 0: DMA end signal for Endpoint n has not been input (default value). When this bit is set to 1, the DMA request signal for Endpoint n becomes inactive. The DMA request signal for Endpoint n does not become active unless FW enables DMA transfer. Use the UF0DMS0 register to confirm on which endpoint the operation is actually performed. However, this bit is not automatically cleared to 0 even if the UF0DMS0 register is read by FW. 2 SETRQ This bit indicates that the SET_XXXX request to be automatically processed has been received and automatically processed (XXXX = CONFIGURATION or FEATURE). 1: SET_XXXX request to be automatically processed has been received (interrupt request is generated). 0: SET_XXXX request to be automatically processed has not been received (default value). This bit is set to 1 after completion of the status stage. Reference the UF0SET register to identify what is the target of the request. This bit is not automatically cleared to 0 even if the UF0SET register is read by FW. The EPHALT bit is also set to 1 when the SET_FEATURE Endpoint request has been received. 1 CLRRQ This bit indicates that the CLEAR_FEATURE request has been received and automatically processed. 1: CLEAR_FEATURE request has been received (interrupt request is generated). 0: CLEAR_FEATURE request has not been received (default value). This bit is set to 1 after completion of the status stage. Reference the UF0CLR register to identify what is the target of the request. This bit is not automatically cleared to 0 even if the UF0CLR register is read by FW. 0 EPHALT This bit indicates that an endpoint has stalled. 1: Endpoint has stalled (interrupt request is generated). 0: Endpoint has not stalled (default value). This bit is also set to 1 when an endpoint has stalled by setting FW. Identify the endpoint that has stalled, by referencing the UF0EPS2 register. This bit is not automatically cleared to 0 even when the CLEAR_FEATURE Endpoint, SET_INTERFACE, or SET_CONFIGURATION request is received. It is not automatically cleared to 0, either, if the next SETUP token is received in case of overrun of Endpoint0. Caution Even if Halt Feature of Endpoint0 is set and this interrupt request is generated, bit 0 of the UF0EPS2 register is masked and cleared to 0 between when a SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0, or GET_STATUS Endpoint0 request, or FW-processed request is received and when a SETUP token other than the above is received. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1046 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (12) UF0 INT status 1 register (UF0IS1) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC1 register. However, the SUCES and STG bits of the UF0IS1 register are automatically cleared to 0 when the next SETUP token has been received. Caution In the USBF, multiple interrupt sources, such as Bus Reset, Resume, and Short, are ORed internally and are issued as a single interrupt request (INTUSBF0). Therefore, in the case of the occurrence of multiple interrupt sources, they are ORed and issued as an INTUSBF0 interrupt request. For example, if a Bus Reset interrupt source and Resume interrupt source occur, the two sources are ORed and an INTUSBF0 interrupt request is issued. Under these conditions, if the Bus Reset interrupt source is cleared to 0 (UF0IC0.BUSRSTC = 0), the V850ES/JC3-H or V850ES/JE3-H internal INTUSBF0 interrupt request may remain set to 1 since the Resume interrupt source will still be remaining. The new interrupt request flag (US0BIC.US0BIF), therefore, might not be set to 1. In this case, after performing clear processing for each interrupt request with the INTUSBF0 interrupt servicing routine, confirm the flag status for the UF0IS0 and UF0IS1 registers again, and if there are any interrupt sources with flags set to 1, perform flag clearing (only the applicable bits need to be cleared (do not perform a batch clearing)). (1/2) UF0IS1 Bit position 6 7 6 5 4 3 2 1 0 Address After reset 0 E0IN E0INDT E0ODT SUCES STG PROT CPU 00200022H 00H DEC Bit name E0IN Function This bit indicates that an IN token for Endpoint0 has been received and that the hardware has automatically transmitted NAK. 1: IN token is received and NAK is transmitted (interrupt request is generated). 0: IN token is not received (default value). 5 E0INDT This bit indicates that data has been correctly transmitted from the UF0E0W register. 1: Transmission from UF0E0W register is completed (interrupt request is generated). 0: Transmission from UF0E0W register is not completed (default value). Data is transmitted in synchronization with the IN token next to the one that set the EP0NKW bit of the UF0E0N register to 1. This bit is automatically set to 1 by hardware when the host correctly receives that data. It is also set to 1 even if the data is a Null packet. This bit is automatically cleared to 0 by hardware when the first write access is made to the UF0E0W register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1047 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 4 Bit name E0ODT Function This bit indicates that data has been correctly received in the UF0E0R register. 1: Data is in UF0E0R register (interrupt request is generated). 0: Data is not in UF0E0R register (default value). This bit is automatically set to 1 by hardware when data has been correctly received. At the same time, the EP0R bit of the UF0EPS0 register is also set to 1. If a Null packet has been received, this bit is not set to 1. It is automatically cleared to 0 by hardware when the FW reads the UF0E0R register and the value of the UF0E0L register becomes 0. 3 SUCES This bit indicates that either an FW-processed or hardware-processed request has been received and that the status stage has been correctly completed. 1: Control transfer has been correctly processed (interrupt request is generated). 0: Control transfer has not been processed correctly (default value). This bit is set to 1 upon completion of the status stage. It is automatically cleared to 0 by hardware when the next SETUP token is received. This bit is also set to 1 when data with Data PID of 0 (Null data) is received in the status stage of control transfer. 2 STG This bit is set to 1 when the stage of control transfer has changed to the status stage. It is valid for both FW-processed and hardware-processed requests. This bit is also set to 1 when the stage of control transfer (without data) has changed to the status stage. 1: Status stage (interrupt request is generated) 0: Not status stage (default value) This bit is automatically cleared to 0 by hardware when the next SETUP token is received. It is also set to 1 when the stage of control transfer has changed to the status stage while ACK cannot be correctly received in the data stage. In this case, the EP0NKW bit of the UF0E0N register is also cleared to 0 as soon as the UF0E0W register has been cleared, if the FW is processing control transfer (read). 1 PROT This bit indicates that a SETUP token has been received. It is valid for both FWprocessed and hardware-processed requests. 1: SETUP token is correctly received (interrupt request is generated). 0: SETUP token is not received (default value). This bit is set to 1 when data has been correctly received in the UF0E0ST register. Clear this bit to 0 by FW when the first read access is made to the UF0E0ST register. If it is not cleared to 0 by FW, reception of the next SETUP token cannot be correctly recognized. This bit is used to accurately recognize that a SETUP transaction has been executed again during control transfer. If the SETUP transaction is re-executed during control transfer and if a second request is executed by hardware, the CPUDEC bit is not set to 1, but the PROT bit can be used for recognition of the re-execution. 0 CPUDEC This bit indicates that the UF0E0ST register has a request that is to be decoded by FW. 1: Data is in UF0E0ST register (interrupt request is generated). 0: Data is not in UF0E0ST register (default value). This bit is automatically cleared to 0 by hardware when all the data of the UF0E0ST register is read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1048 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (13) UF0 INT status 2 register (UF0IS2) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC2 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7) and the current setting of the interface. UF0IS2 7 6 5 4 3 2 1 0 Address After reset BKI2IN BKI2DT BKI1IN BKI1DT 0 0 0 IT1DT 00200024H 00H Bit position 7, 5 Bit name BKInIN Function These bits indicate that an IN token has been received in the UF0BIn register (Endpoint m) and that NAK has been returned. 1: IN token is received and NAK is transmitted (interrupt request is generated). 0: IN token is not received (default value). 6, 4 BKInDT These bits indicate that the FIFO of the UF0BIn register (Endpoint m) has been toggled. This means that data can be written to Endpoint m. 1: FIFO has been toggled (interrupt request is generated). 0: FIFO has not been toggled (default value). The data written to Endpoint m is transmitted in synchronization with the IN token next to the one that set the BKInNK bit of the UF0EN register to 1. When the FIFO has been toggled and then data can be written from the CPU, this bit is automatically set to 1 by hardware. It is also set to 1 when the FIFO has been toggled, even if the data is a Null packet. This bit is automatically cleared to 0 by hardware when the first write access is made to the UF0BIn register. 0 IT1DT These bits indicate that data has been correctly received from the UF0INT1 register (Endpoint x). 1: Transmission is completed (interrupt request is generated). 0: Transmission is not completed (default value). Data is transmitted in synchronization with the IN token next to the one that set the ITnNK bit of the UF0EN register to 1. This bit is automatically set to 1 by hardware when the host has correctly received that data. It is automatically cleared to 0 by hardware when the first write access is made to the UF0INT1 register. This bit is also set to 1 even when the data is a Null packet. Remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 where n = 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1049 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (14) UF0 INT status 3 register (UF0IS3) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC3 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. (1/2) 7 UF0IS3 6 BKO2FL BKO2NL 4 5 BKO2 3 BKO2DT BKO1FL BKO1NL NAK Bit position 7, 3 1 0 Address After reset BKO1 BKO1DT 00200026H 00H NAK Bit name BKOnFL 2 Function These bits indicate that data has been correctly received in the UF0BOn register (Endpoint m) and that both the FIFOs of the CPU and SIE hold the data. 1: Received data is in both the FIFOs of the UF0BOn register (interrupt request is generated). 0: Received data is not in the FIFO on the SIE side of the UF0BOn register (default value). If data is held in both the FIFOs of the CPU and SIE, these bits are automatically set to 1 by hardware. They are automatically cleared to 0 by hardware when the FIFO is toggled. 6, 2 BKOnNL These bits indicate that a Null packet (packet with a length of 0) has been received in the UF0BOn register (Endpoint m). 1: Null packet is received (interrupt request is generated). 0: Null packet is not received (default value). These bits are set to 1 immediately after reception of a Null packet when the FIFO is empty. They are set to 1 when the FIFO on the CPU side has been completely read if data is in that FIFO. 5, 1 BKOnNAK These bits indicate that an OUT token has been received to the UF0BOn register (Endpoint m) and that NAK has been returned. 1: OUT token is received and NAK is transmitted (interrupt request is generated). 0: OUT token is not received (default value). Remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1050 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 4, 0 Bit name BKOnDT Function These bits indicate that data has been correctly received in the UF0BOn register (Endpoint m). 1: Reception has been completed correctly (interrupt request is generated). 0: Reception has not been completed (default value). These bits are automatically set to 1 by hardware when data has been correctly received and the FIFO has been toggled. At the same time, the corresponding bits of the UF0EPS0 register are also set to 1. They are not set to 1 when the data is a Null packet. These bits are automatically cleared to 0 by hardware when the value of the UF0BOnL register becomes 0 as a result of reading the UF0BOn register by FW. These bits are automatically cleared to 0 when all the contents of the FIFO on the CPU side have been read. However, the interrupt request is not cleared if data is in the FIFO on the SIE side at this time, and the INTUSBF1 signal does not become inactive. The signal is kept active if data is successively received. Remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1051 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (15) UF0 INT status 4 register (UF0IS4) This register indicates the interrupt source. If the contents of this register are changed, the EPCINT2B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC4 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. UF0IS4 Bit position 5 7 6 5 4 3 2 1 0 Address After reset 0 0 SETINT 0 0 0 0 0 00200028H 00H Bit name SETINT Function This bit indicates that the SET_INTERFACE request has been received and automatically processed. 1: The request has been automatically processed (interrupt request is generated). 0: The request has not been automatically processed (default value). The current setting of this bit can be identified by reading the UF0ASS or UF0IFn register (n = 0 to 4). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1052 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (16) UF0 INT mask 0 register (UF0IM0) This register controls masking of the interrupt sources indicated by the UF0IS0 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register. UF0IM0 7 6 5 4 3 2 1 0 Address After reset BUS RSU 0 SHORTM DMA SET CLR EP 0020002EH 00H RSTM SPDM EDM RQM RQM HALTM Bit position 7 Bit name BUSRSTM Function This bit masks the Bus Reset interrupt. 1: Mask 0: Do not mask (default value) 6 RSUSPDM This bit masks the Resume/Suspend interrupt. 1: Mask 0: Do not mask (default value) 4 SHORTM This bit masks the Short interrupt. 1: Mask 0: Do not mask (default value) 3 DMAEDM This bit masks the DMA_END interrupt. 1: Mask 0: Do not mask (default value) 2 SETRQM This bit masks the SET_RQ interrupt. 1: Mask 0: Do not mask (default value) 1 CLRRQM This bit masks the CLR_RQ interrupt. 1: Mask 0: Do not mask (default value) 0 EPHALTM This bit masks the EP_Halt interrupt. 1: Mask 0: Do not mask (default value) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1053 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (17) UF0 INT mask 1 register (UF0IM1) This register controls masking of the interrupt sources indicated by the UF0IS1 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register. UF0IM1 Bit position 6 7 6 5 4 3 2 1 0 Address After reset 0 E0INM E0 E0 SUCESM STGM PROTM CPU 00200030H 00H INDTM ODTM Bit name E0INM DECM Function This bit masks the EP0IN interrupt. 1: Mask 0: Do not mask (default value) 5 E0INDTM This bit masks the EP0INDT interrupt. 1: Mask 0: Do not mask (default value) 4 E0ODTM This bit masks the EP0OUTDT interrupt. 1: Mask 0: Do not mask (default value) 3 SUCESM This bit masks the Success interrupt. 1: Mask 0: Do not mask (default value) 2 STGM This bit masks the Stg interrupt. 1: Mask 0: Do not mask (default value) 1 PROTM This bit masks the Protect interrupt. 1: Mask 0: Do not mask (default value) 0 CPUDECM This bit masks the CPUDEC interrupt. 1: Mask 0: Do not mask (default value) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1054 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (18) UF0 INT mask 2 register (UF0IM2) This register controls masking of the interrupt sources indicated by the UF0IS2 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7) and the current setting of the interface. UF0IM2 7 6 5 4 3 2 1 0 Address After reset BKI2INM BKI2 BKI1INM BKI1 0 0 0 IT1DTM 00200032H 00H DTM Bit position 7, 5 DTM Bit name BKInINM Function These bits mask the BLKInIN interrupt. 1: Mask 0: Do not mask (default value) 6, 4 BKInDTM These bits mask the BLKInDT interrupt. 1: Mask 0: Do not mask (default value) 0 IT1DTM These bits mask the INTnDT interrupt. 1: Mask 0: Do not mask (default value) Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1055 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (19) UF0 INT mask 3 register (UF0IM3) This register controls masking of the interrupt sources indicated by the UF0IS3 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. UF0IM3 7 6 5 4 3 2 1 0 Address After reset BKO2 BKO2 BKO2 BKO2 BKO1 BKO1 BKO1 BKO1 00200034H 00H NAKM DTM FLM NLM NAKM DTM FLM NLM Bit position 7, 3 Bit name BKOnFLM Function These bits mask the BLKOnFL interrupt. 1: Mask 0: Do not mask (default value) 6, 2 BKOnNLM These bits mask the BLKOnNL interrupt. 1: Mask 0: Do not mask (default value) 5, 1 BKOnNAKM These bits mask the BLKOnNK interrupt. 1: Mask 0: Do not mask (default value) 4, 0 BKOnDTM These bits mask the BLKOnDT interrupt. 1: Mask 0: Do not mask (default value) Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1056 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (20) UF0 INT mask 4 register (UF0IM4) This register controls masking of the interrupt sources indicated by the UF0IS4 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. UF0IM4 Bit position 5 7 6 5 4 3 2 1 0 Address After reset 0 0 SETINTM 0 0 0 0 0 00200036H 00H Bit name SETINTM Function This bit masks the SET_INT interrupt. 1: Mask 0: Do not mask (default value) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1057 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (21) UF0 INT clear 0 register (UF0IC0) This register controls clearing the interrupt sources indicated by the UF0IS0 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. UF0IC0 7 6 5 4 3 2 1 0 Address After reset BUS RSU 1 SHORTC DMA SET CLR EP 0020003CH FFH RSTC SPDC EDC RQC RQC HALTC Bit position 7 Bit name BUSRSTC Function This bit clears the Bus Reset interrupt. 0: Clear 6 RSUSPDC This bit clears the Resume/Suspend interrupt. 0: Clear 4 SHORTC This bit clears the Short interrupt. 3 DMAEDC This bit clears the DMA_END interrupt. 0: Clear 0: Clear 2 SETRQC This bit clears the SET_RQ interrupt. 0: Clear 1 CLRRQC This bit clears the CLR_RQ interrupt. 0: Clear 0 EPHALTC This bit clears the EP_Halt interrupt. 0: Clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1058 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (22) UF0 INT clear 1 register (UF0IC1) This register controls clearing the interrupt sources indicated by the UF0IS1 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. UF0IC1 7 6 5 1 E0INC E0 4 2 1 0 Address After reset STGC PROTC CPU 0020003EH FFH 3 E0ODTC SUCESC INDTC Bit position 6 Bit name E0INC DECC Function This bit clears the EP0IN interrupt. 0: Clear 5 E0INDTC This bit clears the EP0INDT interrupt. 0: Clear 4 E0ODTC This bit clears the EP0OUTDT interrupt. 3 SUCESC This bit clears the Success interrupt. 0: Clear 0: Clear 2 STGC This bit clears the Stg interrupt. 0: Clear 1 PROTC This bit clears the Protect interrupt. 0: Clear 0 CPUDECC This bit clears the CPUDEC interrupt. 0: Clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1059 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (23) UF0 INT clear 2 register (UF0IC2) This register controls clearing the interrupt sources indicated by the UF0IS2 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7) and the current setting of the interface. UF0IC2 7 6 5 4 3 2 1 0 Address After reset BKI2INC BKI2 BKI1INC BKI1 1 1 1 IT1DTC 00200040H FFH DTC Bit position 7, 5 DTC Bit name BKInINC Function These bits clear the BLKInIN interrupt. 0: Clear 6, 4 BKInDTC These bits clear the BLKInDT interrupt. 0: Clear 0 IT1DTC These bits clear the INTnDT interrupt. 0: Clear Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1060 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (24) UF0 INT clear 3 register (UF0IC3) This register controls clearing the interrupt sources indicated by the UF0IS3 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. UF0IC3 7 6 5 4 3 2 1 0 Address After reset BKO2 BKO2 BKO2 BKO2 BKO1 BKO1 BKO1 BKO1 00200042H FFH FLC NLC NAKC DTC FLC NLC NAKC DTC Bit position 7, 3 Bit name BKOnFLC Function These bits clear the BLKOnFL interrupt. 0: Clear 6, 2 BKOnNLC These bits clear the BLKOnNL interrupt. 0: Clear 5, 1 BKOnNAKC These bits clear the BLKOnNK interrupt. 0: Clear 4, 0 BKOnDTC These bits clear the BLKOnDT interrupt. 0: Clear Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1061 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (25) UF0 INT clear 4 register (UF0IC4) This register controls clearing the interrupt sources indicated by the UF0IS4 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7) and the current setting of the interface. UF0IC4 Bit position 5 7 6 5 4 3 2 1 0 Address After reset 1 1 SETINTC 1 1 1 1 1 00200044H FFH Bit name SETINTC Function This bit clears the SET_INT interrupt. 0: Clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1062 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (26) UF0 INT & DMARQ register (UF0IDR) This register selects reporting via an interrupt request or starting DMA. This register can be read or written in 8-bit units. If data exists in either the UF0BO1 or UF0BO1 register, or if data can be written to the UF0BI1 or UF0BI2 register, this register selects whether it is reported to the FW by an interrupt request, or whether starting DMA is requested. If starting DMA is requested, the DMA transfer mode can be selected according to the setting of bits 0 and 1. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. Be sure to clear bits 3 and 2 to "0". If they are set to 1, the operation is not guaranteed. Caution If the target endpoint is not supported by the SET_INTERFACE request under DMA transfer, the DMA request signal becomes inactive immediately, and the corresponding bit is automatically cleared to 0 by hardware. (1/2) UF0IDR 7 6 5 4 3 2 1 0 Address After reset DQBI2 DQBI1 DQBO2 DQBO1 0 0 MODE1 MODE0 0020004CH 00H MS MS MS MS Bit position 7, 6 Bit name DQBInMS Function These bits enable (mask) a write DMA transfer request (DMA request signal for Endpoint m) to the UF0BIn register. When these bits are set to 1, the DMA request signal for Endpoint m becomes active while writing data can be acknowledged. If the DMA end signal for Endpoint m is input (if the DMA controller issues TC), these bits are automatically cleared to 0 by hardware. To continue DMA transfer, re-set these bits to 1 by FW. 1: Enables active DMA request signal for Endpoint m (masks BKInDT interrupt). 0: Disables active DMA request signal for Endpoint m (default value). 5, 4 DQBOnMS These bits enable (mask) a read DMA transfer request (DMA request signal for Endpoint x) to the UF0BOn register. When these bits are set to 1, the DMA request signal for Endpoint x becomes active if the data to be read is prepared in the UF0BOn register. If the DMA end signal for Endpoint x is input (if the DMA controller issues TC), these bits are automatically cleared to 0 by hardware. They are also cleared to 0 when the USBSPxB signal is active. To continue DMA transfer, re-set these bits to 1 by FW. 1: Enables active DMA request signal for Endpoint x (masks BKOnDT interrupt). 0: Disables active DMA request signal for Endpoint x (default value). Remark n = 1, 2 m = 1 and x = 2 where n = 1 m = 3 and x = 4 where n = 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1063 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1, 0 Bit name MODE1, MODE0 Function These bits select the DMA transfer mode. MODE1 MODE0 1 0 Mode Remark Demand DMA request signal becomes active as mode long as there is data. It becomes inactive if there is no more data. Other than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Setting prohibited Page 1064 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (27) UF0 DMA status 0 register (UF0DMS0) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. UF0DMS0 Bit position 5 7 6 5 4 3 2 1 0 Address After reset 0 0 DQE4 DQE3 DQE2 DQE1 0 0 0020004EH 00H Bit name DQE4 Function This bit indicates that a DMA read request is being issued from Endpoint4 to memory. 1: DMA read request from Endpoint4 is being issued. 0: DMA read request from Endpoint4 is not being issued (default value). 4 DQE3 This bit indicates that a DMA write request is being issued from memory to Endpoint3. Note that, even if data is in Endpoint3 (when the FIFO is not full and after the BKI2DED bit has been set to 1), the DMA request signal becomes active immediately and DMA transfer is started when the DQBI2MS bit of the UF0IDR register is set to 1. 1: DMA write request for Endpoint3 is being issued. 0: DMA write request for Endpoint3 is not being issued (default value). 3 DQE2 This bit indicates that a DMA read request is being issued from Endpoint2 to memory. 1: DMA read request from Endpoint2 is being issued. 0: DMA read request from Endpoint2 is not being issued (default value). 2 DQE1 This bit indicates that a DMA write request is being issued from memory to Endpoint1. Note that, even if data is in Endpoint1 (when the FIFO is not full and after the BKI1DED bit has been set to 1), the DMA request signal becomes active immediately and DMA transfer is started when the DQBI1MS bit of the UF0IDR register is set to 1. 1: DMA write request for Endpoint1 is being issued. 0: DMA write request for Endpoint1 is not being issued (default value). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1065 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (28) UF0 DMA status 1 register (UF0DMS1) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. Each bit is automatically cleared to 0 when this register is read. Even when this register is read, however, bits 4 and 3 of the UF0IS0 register are not cleared to 0. If the target endpoint is no longer supported by the SET_INTERFACE request, each bit is automatically cleared to 0 by hardware (however, the DMA_END interrupt request and Short interrupt request are not cleared). UF0DMS1 7 6 5 4 3 2 1 0 Address After reset DEDE4 DSPE4 DEDE3 DEDE2 DSPE2 DEDE1 0 0 00200050H 00H Bit position 7, 5, 4, 2 Bit name DEDEn Function These bits indicate that the DMA end (TC) signal for Endpoint n becomes active and DMA is stopped while a DMA read request is being issued from Endpoint n to memory. 1: DMA end signal for Endpoint n is active. 0: DMA end signal for Endpoint n is inactive (default value). 6, 3 DSPEm These bits indicate that, although a DMA read request was being issued from Endpoint m to memory, DMA has been stopped because the received data is a short packet and there is no more data to be transferred. 1: DMASTOP_EPm signal is active. 0: DMASTOP_EPm signal is inactive (default value). Remark n = 1 to 4 m = 2, 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1066 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (29) UF0 FIFO clear 0 register (UF0FIC0) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7) and the current setting of the interface. UF0FIC0 7 6 5 4 3 2 1 0 Address After reset BKI2SC BKI2CC BKI1SC BKI1CC ITR2C ITR1C EP0WC EP0RC 00200060H 00H Bit position 7, 5 Bit name BKInSC Function These bits clear only the FIFO on the SIE side of the UF0BIn register (reset the counter). 1: Clear Writing these bits is invalid while an IN token for Endpoint m is being processed with the BKInNK bit set to 1. The BKInNK bit is automatically cleared to 0 by clearing the FIFO. Make sure that the FIFO on the CPU side is empty when these bits are used. 6, 4 BKInCC These bits clear only the FIFO on the CPU side of the UF0BIn register (reset the counter). 1: Clear 2 ITR1C These bits clear the UF0INT1 register (reset the counter). 1: Clear Writing these bits is invalid while an IN token for Endpoint 7 is being processed with the IT1NK bit set to 1. The IT1NK bit is automatically cleared to 0 by clearing the FIFO. 1 EP0WC This bit clears the UF0E0W register (resets the counter). 1: Clear Writing this bit is invalid while an IN token for Endpoint0 is being processed with the EP0NKW bit set to 1. The EP0NKW bit is automatically cleared to 0 by clearing the FIFO. 0 EP0RC This bit clears the UF0E0R register (resets the counter). 1: Clear When the EP0NKR bit is set to 1 (except when it has been set by FW), the EP0NKR bit is automatically cleared to 0 by clearing the FIFO. Remark n = 1, 2 m = 1 where n = 1 m = 3 where n = 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1067 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (30) UF0 FIFO clear 1 register (UF0FIC1) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. UF0FIC1 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 BKO2C BKO2CC BKO1C BKO1CC 00200062H 00H Bit position 3, 1 Bit name BKOnC Function These bits clear the FIFOs on both the SIE and CPU sides of the UF0BOn register (reset the counter). 1: Clear When the BKOnNK bit is set to 1 (except when it has been set by FW), the BKOnNK bit is automatically cleared to 0 by clearing the FIFO. 2, 0 BKOnCC These bits clear only the FIFO on the CPU side of the UF0BOn register (reset the counter). 1: Clear When the BKOnNK bit is set to 1 (except when it has been set by FW), the BKOnNK bit is automatically cleared to 0 by clearing the FIFO. Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1068 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (31) UF0 data end register (UF0DEND) This register reports the end of writing to the transmission system. This register is write-only, in 8-bit units (however, bits 7 and 6 can be read and written). If this register is read, 00H is read. FW can start data transfer of the target endpoint by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7) and the current setting of the interface. (1/2) UF0DEND 7 6 5 4 BKI2T BKI1T 0 0 Bit position 7, 6 3 1 0 IT1DEND BKI2DED BKI1DED E0DED Bit name BKInT 2 Address After reset 0020006AH 00H Function These bits specify whether toggling the FIFO is automatically executed if the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA. 1: Automatically execute a toggle operation of the FIFO as soon as the FIFO has become full. 0: Do not automatically execute a toggle operation of the FIFO even if the FIFO becomes full (default value). 3 IT1DEND Set these bits to 1 to transmit the data of the UF0INT1 register. When these bits are set to 1, the IT1NK bit is set to 1 and data transfer is executed. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). If the ITR1C bit of the UF0FIC0 register is set to 1 and then these bits are set to 1 (counter of UF0INT1 register = 0 and the corresponding bit of the UF0EPS1 register = 1), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0INT1 register and if these bits are set to 1 (counter of UF0INT1 register 0 and the corresponding bit of the UF0EPS0 register = 1), a short packet is transmitted. These bits are automatically controlled by hardware when the FIFO is full. Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1069 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 2, 1 Bit name BKInDED Function Set these bits to 1 when writing transmit data to the UF0BIn register has been completed. When these bits are set to 1, the FIFO is toggled as soon as possible, the BKInNK bit is set to 1, and data is transferred. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). These bits control the FIFO on the CPU side. If the BKInCC bit of the UF0FIC0 register is set to 1 and then these bits are set to 1 (counter of UF0BIn register = 0), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0BIn register and if these bits are set to 1 (counter of UF0BIn register 0), and if the FIFO is not full, a short packet is transmitted. If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with the PIO or BKInT bit set to 1, the hardware starts data transmission even if these bits are not set to 1. If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with the BKInT bit cleared to 0, be sure to set these bits to 1 (see 20.6.3 (3) UF0 EPNAK register (UF0EN)). 0 E0DED Set this bit to 1 to transmit data of the UF0E0W register. When this bit is set to 1, the EP0NKW bit is set to 1 and data is transferred. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). If the EP0WC bit of the UF0FIC0 register is set to 1 and if this bit is set to 1 (counter of UF0E0W register = 0 and bit 1 of UF0EPS0 register = 1), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0E0W register and if this bit is set to 1 (counter of UF0E0W register 0 and bit 1 of the UF0EPS0 register = 1), and if the FIFO is not full, a short packet is transmitted. Remark n = 1, 2 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1070 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (32) UF0 GPR register (UF0GPR) This register controls USBF and the USB interface. This register is write-only, in 8-bit units. If this register is read, 00H is read. Be sure to clear bits 7 to 1 to "0". FW can reset the USBF by writing 1 to bit 0 of this register. This bit is automatically cleared to 0 after 1 has been written to it. Writing 0 to this bit is invalid. UF0GPR Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 MRST 0020006EH 00H Bit name MRST Function Set this bit to 1 to reset USBF. 1: Reset Actually, USBF is reset two USB clocks after this bit has been set to 1 by FW and the write signal has become inactive. Resetting USBF by the MRST bit while the system clock is operating has the same result as resetting by the RESET pin (hardware reset) (register value back to default value). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1071 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (33) UF0 mode control register (UF0MODC) This register controls CPUDEC processing. This register can be read or written in 8-bit units. By setting each bit of this register, the setting of the UF0MODS register can be changed. The bit of this register is automatically cleared to 0 only at hardware reset and when the MRST bit of the UF0GRP register has been set to 1. Even if the bit of this register has automatically been set to 1 by hardware, the setting by FW takes precedence. Be sure to clear bits 7 and 5 to 2 to "0". If they are set to 1, the operation is not guaranteed. Caution This register is provided for debugging purposes. Usually, do not set this register except for verifying the operation or when a special mode is used. 7 UF0MODC 0 6 5 4 3 2 1 0 Address After reset CDC 0 0 0 0 0 0 00200074H 00H GDST Bit position 6 Bit name CDCGDST Function Set this bit to 1 to switch the GET_DESCRIPTOR Configuration request to CPUDEC processing. By setting this bit to 1, the CDCGD bit of the UF0MODS register can be forcibly set to 1. 1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC processing (sets the CDCGD bit of the UF0MODS register to 1). 0: Automatically process the GET_DESCRIPTOR Configuration request (default value). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1072 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (34) UF0 mode status register (UF0MODS) This register indicates the configuration status. This register is read-only, in 8-bit units. UF0MODS Bit position 6 7 6 5 4 3 2 1 0 Address After reset 0 CDCGD 0 MPACK DFLT CONF 0 0 00200078H 00H Bit name CDCGD Function This bit specifies whether CPUDEC processing is performed for the GET_DESCRIPTOR Configuration request. 1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC processing. 0: Automatically process the GET_DESCRIPTOR Configuration request (default value). 4 MPACK This bit indicates the transmit packet size of Endpoint0. 1: Transmit a packet of other than 8 bytes. 0: Transmit a packet of 8 bytes (default value). This bit is automatically set to 1 by hardware after the GET_DESCRIPTOR Device request has been processed (on normal completion of the status stage). It is not cleared to 0 until the USBF has been reset (it is not cleared to 0 by Bus Reset). If this bit is not set to 1, the hardware transfers only the automatically-executed request in 8-byte units. Therefore, even if data of more than 8 bytes is sent by the OUT token to be processed by FW before completion of the GET_DESCRIPTOR Device request, the data is correctly received. This bit is ignored if the size of Endpoint0 is 8 bytes. 3 DFLT This bit indicates the default status (DFLT bit = 1). 1: Enables response. 0: Disables response (always no response) (default value). This bit is automatically set to 1 by Bus Reset. The transaction for all the endpoints is not responded to until this bit is set to 1. 2 CONF This bit indicates whether the SET_CONFIGURATION request has been completed. 1: SET_CONFIGURATION request has been completed. 0: SET_CONFIGURATION request has not been completed (default value). This bit is set to 1 when Configuration value = 1 is received by the SET_CONFIGURATION request. Unless this bit is set to 1, access to an endpoint other than Endpoint0 is ignored. This bit is cleared to 0 when Configuration value = 0 is received by the SET_CONFIGURATION request. It is also cleared to 0 when Bus Reset is detected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1073 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (35) UF0 active interface number register (UF0AIFN) This register sets the valid Interface number that correctly responds to the GET/SET_INTERFACE request. Because Interface 0 is always valid, Interfaces 1 to 4 can be selected. This register can be read or written in 8-bit units. UF0AIFN 7 6 5 4 3 2 1 0 Address After reset ADDIF 0 0 0 0 0 IFNO1 IFNO0 00200080H 00H Bit position 7 Bit name ADDIF Function This bit allows use of Interfaces numbered other than 0. 1: Support up to the Interface number specified by the IFNO1 and IFNO0 bits. 0: Support only Interface 0 (default value). Setting bits 1 and 0 of this register is invalid when this bit is not set to 1. 1, 0 IFNO1, IFNO0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 These bits specify the range of Interface numbers to be supported. IFNO1 IFNO0 Valid Interface No. 1 1 0, 1, 2, 3, 4 1 0 0, 1, 2, 3 0 1 0, 1, 2 0 0 0, 1 Page 1074 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (36) UF0 active alternative setting register (UF0AAS) This register specifies a link between the Interface number and Alternative Setting. This register can be read or written in 8-bit units. USBF of the V850ES/JC3-H and V850ES/JE3-H can set a five-series Alternative Setting (Alternate Setting 0, 1, 2, 3, and 4 can be defined) and a two-series Alternative Setting (Alternative Setting 0 and 1 can be defined) for one Interface. UF0AAS 7 6 5 4 3 2 1 0 Address After reset ALT2 IFAL21 IFAL20 ALT2EN ALT5 IFAL51 IFAL50 ALT5EN 00200082H 00H Bit position 7, 3 Bit name ALTn Function These bits specify whether an n-series Alternative Setting is linked with Interface 0. When these bits are set to 1, the setting of the IFALn1 and IFALn0 bits is invalid. 1: Link n-series Alternative Setting with Interface 0. 0: Do not link n-series Alternative Setting with Interface 0 (default value). 6, 5, IFALn1, IFALn0 2, 1 These bits specify the Interface number to be linked with the n-series Alternative Setting. If the linked Interface number is outside the range specified by the UF0AIFN register, the n-series Alternative Setting is invalid (ALTnEN bit = 0). IFALn1 IFALn0 Interface number to be linked 1 1 Links Interface 4. 1 0 Links Interface 3. 0 1 Links Interface 2. 0 0 Links Interface 1. Do not link a five-series Alternative Setting and a two-series Alternative Setting with the same Interface number. 4, 0 ALTnEN These bits validate the n-series Alternative Setting. Unless these bits are set to 1, the setting of the ALTn, IFALn1, and IFALn0 bits is invalid. 1: Validate the n-series Alternative Setting. 0: Do not validate the n-series Alternative Setting (default value). Remark n = 2, 5 For example, when the UF0AIFN register is set to 82H and the UF0AAS register is set to 15H, Interfaces 0, 1, 2, and 3 are valid. Interfaces 0 and 2 support only Alternative Setting 0. Interface 1 supports Alternative Setting 0 and 1, and Interface 3 supports Alternative Setting 0, 1, 2, 3, and 4. With this setting, requests GET_INTERFACE wIndex = 0/1/2/3, SET_INTERFACE wValue = 0 & wIndex = 0/2, SET_INTERFACE wValue = 0/1 & wIndex = 1, and SET_INTERFACE wValue = 0/1/2/3/4 & wIndex = 3 are automatically responded to, and a STALL response is made to the other GET/SET_INTERFACE requests. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1075 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (37) UF0 alternative setting status register (UF0ASS) This register indicates the current status of the Alternative Setting. This register is read-only, in 8-bit units. Check this register when the SET_INT interrupt request has been issued. The value received by the SET_INTERFACE request is reflected on the UF0IFn register (n = 0 to 4) as well as on this register. UF0ASS Bit position 3 to 1 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 AL5ST3 AL5ST2 AL5ST1 AL2ST 00200084H 00H Bit name AL5ST3 to AL5ST1 0 AL2ST Function These bits indicate the current status of the five-series Alternative Setting. AL5ST3 AL5ST2 AL5ST1 Selected Alternative Setting number 1 0 0 Alternative Setting 4 0 1 1 Alternative Setting 3 0 1 0 Alternative Setting 2 0 0 1 Alternative Setting 1 0 0 0 Alternative Setting 0 This bit indicates the current status of the two-series Alternative Setting (selected Alternative Setting number). 1: Alternative Setting 1 0: Alternative Setting 0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1076 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (38) UF0 endpoint 1 interface mapping register (UF0E1IM) This register specifies for which Interface and Alternative Setting Endpoint1 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint1 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint1 request and the IN transaction to Endpoint1 are responded to, and whether the related bits are valid or invalid. UF0E1IM 7 6 5 4 3 2 1 0 Address After reset E1EN2 E1EN1 E1EN0 E12AL1 E15AL4 E15AL3 E15AL2 E15AL1 00200086H 00H Bit position 7 to 5 Bit name Function E1EN2 to These bits set a link between the Interface of Endpoint1 and the two-/five-series E1EN0 Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E1EN2 E1EN1 E1EN0 Link status 1 1 1 1 1 0 1 0 1 Linked with Interface 4 and Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Linked with Interface 0 and Alternative Setting 0 0 0 0 Not linked with Interface (default value) Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E12AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint1 is valid. 4 E12AL1 This bit validates Endpoint1 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E15AL4 to E15AL1 bits are 0000. 3 to 0 E15ALn These bits validate Endpoint1 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1077 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (39) UF0 endpoint 2 interface mapping register (UF0E2IM) This register specifies for which Interface and Alternative Setting Endpoint2 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint2 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint2 request and the OUT transaction to Endpoint2 are responded to, and whether the related bits are valid or invalid. UF0E2IM 7 6 5 4 3 2 1 0 Address After reset E2EN2 E2EN1 E2EN0 E22AL1 E25AL4 E25AL3 E25AL2 E25AL1 00200088H 00H Bit position 7 to 5 Bit name Function E2EN2 to These bits set a link between the Interface of Endpoint2 and the two-/five-series E2EN0 Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E2EN2 E2EN1 E2EN0 Link status 1 1 1 1 1 0 1 0 1 Linked with Interface 4 and Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Linked with Interface 0 and Alternative Setting 0 0 0 0 Not linked with Interface (default value) Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E22AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint2 is valid. 4 E22AL1 This bit validates Endpoint2 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E25AL4 to E25AL1 bits are 0000. 3 to 0 E25ALn These bits validate Endpoint2 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1078 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (40) UF0 endpoint 3 interface mapping register (UF0E3IM) This register specifies for which Interface and Alternative Setting Endpoint3 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint3 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint3 request and the IN transaction to Endpoint3 are responded to, and whether the related bits are valid or invalid. UF0E3IM 7 6 5 4 3 2 1 0 Address After reset E3EN2 E3EN1 E3EN0 E32AL1 E35AL4 E35AL3 E35AL2 E35AL1 0020008AH 00H Bit position 7 to 5 Bit name Function E3EN2 to These bits set a link between the Interface of Endpoint3 and the two-/five-series E3EN0 Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E3EN2 E3EN1 E3EN0 Link status 1 1 1 1 1 0 1 0 1 Linked with Interface 4 and Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Linked with Interface 0 and Alternative Setting 0 0 0 0 Not linked with Interface (default value) Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E32AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint3 is valid. 4 E32AL1 This bit validates Endpoint3 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E35AL4 to E35AL1 bits are 0000. 3 to 0 E35ALn These bits validate Endpoint3 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1079 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (41) UF0 endpoint 4 interface mapping register (UF0E4IM) This register specifies for which Interface and Alternative Setting Endpoint4 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint4 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint4 request and the OUT transaction to Endpoint4 are responded to, and whether the related bits are valid or invalid. UF0E4IM 7 6 5 4 3 2 1 0 Address After reset E4EN2 E4EN1 E4EN0 E42AL1 E45AL4 E45AL3 E45AL2 E45AL1 0020008CH 00H Bit position 7 to 5 Bit name Function E4EN2 to These bits set a link between the Interface of Endpoint4 and the two-/five-series E4EN0 Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E4EN2 E4EN1 E4EN0 Link status 1 1 1 1 1 0 1 0 1 Linked with Interface 4 and Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Linked with Interface 0 and Alternative Setting 0 0 0 0 Not linked with Interface (default value) Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E42AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint4 is valid. 4 E42AL1 This bit validates Endpoint4 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E45AL4 to E45AL1 bits are 0000. 3 to 0 E45ALn These bits validate Endpoint4 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1080 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (42) UF0 endpoint 7 interface mapping register (UF0E7IM) This register specifies for which Interface and Alternative Setting Endpoint7 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint7 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint7 request and the IN transaction to Endpoint7 are responded to, and whether the related bits are valid or invalid. UF0E7IM 7 6 5 4 3 2 1 0 Address After reset E7EN2 E7EN1 E7EN0 E72AL1 E75AL4 E75AL3 E75AL2 E75AL1 00200092H 00H Bit position 7 to 5 Bit name Function E7EN2 to These bits set a link between the Interface of Endpoint7 and the two-/five-series E7EN0 Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E7EN2 E7EN1 E7EN0 Link status 1 1 1 1 1 0 1 0 1 Linked with Interface 4 and Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Linked with Interface 0 and Alternative Setting 0 0 0 0 Not linked with Interface (default value) Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E72AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint7 is valid. 4 E72AL1 This bit validates Endpoint7 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E75AL4 to E75AL1 bits are 0000. 3 to 0 E75ALn These bits validate Endpoint7 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1081 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.4 Data hold registers (1) UF0 EP0 read register (UF0E0R) The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. This register is read-only, in 8-bit units. A write access to this register is ignored. The hardware automatically transfers data to the UF0E0R register when it has received the data from the host. When the data has been correctly received, the E0ODT bit of the UF0IS1 register is set to 1. The UF0E0L register holds the quantity of the received data, and an interrupt request (INTUSBF0) is issued. The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is correct reception, the interrupt request is generated. If the reception is abnormal, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The data held by the UF0E0R register must be read by FW up to the value of the amount of data read by the UF0E0L register. Check that all data has been read by using the EP0R bit of the UF0EPS0 register (EP0R bit = 0 when all data has been read). If the value of the UF0E0L register is 0, the EP0NKR bit of the UF0E0N register is cleared to 0, and the UF0E0R register is ready for reception. The UF0E0R register is cleared when the next SETUP token has been received. Caution UF0E0R Read all the data stored. Clear the FIFO to discard some data. 7 6 5 4 3 2 1 0 Address After reset E0R7 E0R6 E0R5 E0R4 E0R3 E0R2 E0R1 E0R0 00200100H Undefined Bit position Bit name 7 to 0 E0R7 to E0R0 Function These bits store the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. The operation of the UF0E0R register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1082 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-4. Operation of UF0E0R Register FIFO hardAbnormal ware reception clear Normal completion of reception Normal completion of reception Status of UF0E0R register EP0NKR bit of UF0E0N register Hardware clear EP0R bit of UF0EPS0 register Hardware clear E0ODT bit of UF0IS1 register Hardware clear Reading FIFO starts Reading FIFO completed (2) UF0 EP0 length register (UF0E0L) The UF0E0L register stores the data length held by the UF0E0R register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is abnormal reception, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The interrupt request is generated only when the reception is normal, and the FW can read as many data from the UF0E0R register as the value read from the UF0E0L register. The value of the UF0E0L register is decremented each time the UF0E0R register has been read. UF0E0L 7 6 5 4 3 2 1 0 Address After reset E0L7 E0L6 E0L5 E0L4 E0L3 E0L2 E0L1 E0L0 00200102H 00H Bit position 7 to 0 Bit name E0L7 to E0L0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Function These bits store the data length held by the UF0E0R register. Page 1083 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP0 setup register (UF0E0ST) The UF0E0ST register holds the SETUP data sent from the host. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0ST register always writes data when a SETUP transaction has been received. The hardware sets the PROT bit of the UF0IS1 register when it has correctly received the SETUP transaction. It sets the CPUDEC bit of the UF0IS1 register in the case of an FW-processed request. Then an interrupt request (INTUSBF0) is issued. In the case of an FW-processed request, be sure to read the request in 8-byte units. If it is not read in 8-byte units, the subsequent requests cannot be correctly decoded. The read counter of the UF0E0ST register is not cleared even when Bus Reset is received. Always read this counter in 8-byte units regardless of whether Bus Reset is received or not. Because the UF0E0ST register always enables writing, the hardware overwrites data to this register even if a SETUP transaction is received while the data of the register is being read. Even if the SETUP transaction cannot be correctly received, the CPUDEC interrupt request and Protect interrupt request are not generated, but the previous data is discarded. If a SETUP token of less than 8 bytes is received, however, the received SETUP token is discarded, and the previously received SETUP data is retained. If the SETUP token is received more than once when control transfer is executed once, be sure to check the PROT bit of the UF0IS1 register under the conditions below. If PROT bit = 1, read the UF0E0ST register again because the SETUP transaction has been received more than once. <1> If a request is decoded by FW and the UF0E0R register is read or the UF0E0W register is written <2> When preparing for a STALL response for the request to which the decode result does not correspond Caution Be sure to read all the stored data. The UF0E0ST register is always updated by the request in the SETUP transaction. UF0E0ST Bit position 7 to 0 7 6 5 4 3 2 1 0 Address After reset E0S7 E0S6 E0S5 E0S4 E0S3 E0S2 E0S1 E0S0 00200104H 00H Bit name E0S7 to E0S0 Function These bits hold the SETUP data sent from the host. The operation of the UF0E0ST register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1084 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-5. Operation of UF0E0ST Register (a) Normal Completion of normal reception of SETUP token Completion of normal reception of SETUP token Status of UF0E0ST register FW processing CPUDEC bit of UF0IS1 register Hardware processing Hardware clear INT clear (FW clear) PROT bit of UF0IS1 register Completion of decoding request INT clear (FW clear) Start Completion of decoding of reading FIFO request Completion of reading FIFO (b) When SETUP transaction is received more than once Completion of normal reception of SETUP token Completion Start of of normal reception reception of second of second SETUP token SETUP token Status of UF0E0ST register Hardware clear on completion of reading 8 bytes Hardware clear CPUDEC bit of UF0IS1 register INT clear (FW clear) PROT bit of UF0IS1 register Completion of decoding request R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 INT clear (FW clear) Completion of decoding request Completion of reading FIFO Page 1085 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP0 write register (UF0E0W) The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data stage to Endpoint0. This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of the UF0E0N register is set to 1 (when NAK is not transmitted). When data is transmitted and when the host correctly receives the data, the EP0NKW bit of the UF0E0N register is automatically cleared to 0 by hardware. A short packet is transmitted when data is written to the UF0E0W register and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0E0W register is cleared and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). The UF0E0W register is cleared to 0 when the next SETUP token is received while transmission has not been completed yet. If the stage of control transfer (read) changes to the status stage while ACK has not been correctly received in the data stage, the UF0E0W register is automatically cleared to 0. At the same time, it is also cleared to 0 if the EP0NKW bit of the UF0E0N register is 1. If the UF0E0W register is read while no data is in it, 00H is read. UF0E0W 7 6 5 4 3 2 1 0 Address After reset E0W7 E0W6 E0W5 E0W4 E0W3 E0W2 E0W1 E0W0 00200106H Undefined Bit position Bit name 7 to 0 E0W7 to E0W0 Function These bits store the IN data sent to the host in the data stage to Endpoint0. The operation of the UF0E0W register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1086 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-6. Operation of UF0E0W Register (a) 16-byte transmission ReTranstransmission mission completed ACK starts Transcannot be ACK mission received reception starts Transmission completed Transmission starts ACK reception Status of UF0E0W register 16-byte transfer EP0NKW bit of UF0E0N register 16-byte transfer Hardware clear FIFO full Re-transfer FIFO full Hardware clear EP0W bit of UF0EPS0 register INT clear (FW clear) E0INDT bit of UF0IS1 register Hardware clear Writing Writing FIFO FIFO starts completed Writing Writing FIFO FIFO starts completed Counter reloaded (b) When Null packet or short packet is transmitted Transmission starts Transmission completed ACK Transmission starts reception Transmission completed ACK reception Status of UF0E0W register Transfer of Null packet E0DED bit of UF0DEND register is set. EP0NKW bit of UF0E0N register Hardware clear E0DED bit of UF0DEND register is set. Hardware clear INT clear (FW clear) EP0W bit of UF0EPS0 register E0INDT bit of UF0IS1 register Hardware clear FIFO FW clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Short packet transfer Writing Writing FIFO FIFO starts completed Page 1087 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (5) UF0 bulk-out 1 register (UF0BO1) The UF0BO1 register is a 64-byte x 2 FIFO that stores data for Endpoint2. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0). This register is read-only, in 8-bit units. A write access to this register is ignored. When the hardware receives data for Endpoint2 from the host, it automatically transfers the data to the UF0BO1 register. When the register correctly receives the data, a FIFO toggle operation occurs. As a result, the BKO1DT bit of the UF0IS3 register is set to 1, the quantity of the received data is held by the UF0BO1L register, and an interrupt request or DMA request is issued to the CPU. Whether the interrupt request or DMA request is issued can be selected by using the DQBO1MS bit of the UF0IDR register. Read the data held by the UF0BO1 register by FW, up to the value of the amount of data read by the UF0BO1L register. When the correct received data is held by the FIFO connected to the SIE side and the value of the UF0BO1L register reaches 0, the toggle operation of the FIFO occurs, and the BKO1NK bit of the UF0EN register is automatically cleared to 0. If data greater than the value of the UF0BO1L register is read and if the FIFO toggle condition is satisfied, the toggle operation of the FIFO occurs. As a result, the next packet may be read by mistake. Note that, if the toggle condition is not satisfied, the first data is repeatedly read. If overrun data is received while data is held by the FIFO connected to the CPU side, Endpoint2 stalls, and the FIFO on the CPU side is cleared. When the UF0BO1 register is read while no data is in it, an undefined value is read. Caution UF0BO1 7 6 5 4 3 2 1 0 Address After reset BKO17 BKO16 BKO15 BKO14 BKO13 BKO12 BKO11 BKO10 00200108H Undefined Bit position 7 to 0 Be sure to read all the data stored in this register. Bit name BKO17 to Function These bits store data for Endpoint2. BKO10 The operation of the UF0BO1 register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1088 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-7. Operation of UF0BO1 Register (1/2) (a) Operation example 1 Reception completed ACK transmission Status of UF0BO1 register Reception completed FIFO toggle FIFO toggle ACK transmission Reception starts SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Reading FIFO starts Reading FIFO completed 64-byte transfer Reading FIFO starts Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer BKO1NK bit of UF0EN register BKO1FL bit of UF0IS3 register BKOUT1 bit of UF0EPS0 register BKO1DT bit of UF0IS3 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Hardware clear Hardware clear FW clear Hardware clear Page 1089 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-7. Operation of UF0BO1 Register (2/2) (b) Operation example 2 Reception Null starts reception Status of completed UF0BO1 register Reception completed Reception Null starts reception completed FIFO toggle ACK transmission Reception completed FIFO toggle ACK transmission SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Reading FIFO starts 0-byte transfer BKO1NL bit of UF0IS3 register 64-byte transfer 0-byte transfer Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer FW clear BKOUT1 bit of UF0EPS0 register BKO1DT bit of UF0IS3 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 FW clear Page 1090 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (6) UF0 bulk-out 1 length register (UF0BO1L) The UF0BO1L register stores the length of the data held by the UF0BO1 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO1L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO1L register is cleared to 00H, and an interrupt request is not generated. Only if the reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO1 register as the value read from the UF0BO1L register. The value of the UF0BO1L register is decremented each time the UF0BO1 register has been read. UF0BO1L 7 6 5 4 3 2 1 0 Address After reset BKO1L7 BKO1L6 BKO1L5 BKO1L4 BKO1L3 BKO1L2 BKO1L1 BKO1L0 0020010AH 00H Bit position 7 to 0 Bit name BKO1L7 to Function These bits store the length of the data held by the UF0BO1 register. BKO1L0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1091 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (7) UF0 bulk-out 2 register (UF0BO2) The UF0BO2 register is a 64-byte x 2 FIFO that stores data for Endpoint4. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0). This register is read-only, in 8-bit units. A write access to this register is ignored. When the hardware receives data for Endpoint4 from the host, it automatically transfers the data to the UF0BO2 register. When the register correctly receives the data, a FIFO toggle operation occurs. As a result, the BKO2DT bit of the UF0IS3 register is set to 1, the quantity of the received data is held by the UF0BO2L register, and an interrupt request or DMA request is issued to the CPU. Whether the interrupt request or DMA request is issued can be selected by using the DQBO2MS bit of the UF0IDR register. Read the data held by the UF0BO2 register by FW, up to the value of the amount of data read by the UF0BO2L register. When the correct received data is held by the FIFO connected to the SIE side and the value of the UF0BO2L register reaches 0, the toggle operation of the FIFO occurs, and the BKO2NK bit of the UF0EN register is automatically cleared to 0. If data greater than the value of the UF0BO2L register is read and if the FIFO toggle condition is satisfied, the toggle operation of the FIFO occurs. As a result, the next packet may be read by mistake. Note that, if the toggle condition is not satisfied, the first data is repeatedly read. If overrun data is received while data is held by the FIFO connected to the CPU side, Endpoint4 stalls, and the FIFO on the CPU side is cleared. When the UF0BO2 register is read while no data is in it, an undefined value is read. Caution UF0BO2 7 6 5 4 3 2 1 0 Address After reset BKO27 BKO26 BKO25 BKO24 BKO23 BKO22 BKO21 BKO20 0020010CH Undefined Bit position 7 to 0 Be sure to read all the data stored in this register. Bit name BKO27 to Function These bits store data for Endpoint4. BKO20 The operation of the UF0BO2 register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1092 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-8. Operation of UF0BO2 Register (1/2) (a) Operation example 1 Reception completed FIFO toggle ACK Reception transmission starts Status of UF0BO2 register Reception completed FIFO toggle ACK transmission SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Reading FIFO starts Reading FIFO completed 64-byte transfer Reading FIFO starts Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer BKO2NK bit of UF0EN register BKO2FL bit of UF0IS3 register BKOUT2 bit of UF0EPS0 register BKO2DT bit of UF0IS3 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Hardware clear Hardware clear FW clear Hardware clear Page 1093 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-8. Operation of UF0BO2 Register (2/2) (b) Operation example 2 Null reception completed Status of UF0BO2 register Reception starts Reception completed Null reception completed FIFO toggle ACK transmission Reception starts Reception completed FIFO toggle ACK transmission SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Reading FIFO starts 0-byte transfer BKO2NL bit of UF0IS3 register 64-byte transfer 0-byte transfer Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer FW clear BKOUT2 bit of UF0EPS0 register BKO2DT bit of UF0IS3 register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 FW clear Page 1094 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (8) UF0 bulk-out 2 length register (UF0BO2L) The UF0BO2L register stores the length of the data held by the UF0BO2 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO2L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO2L register is cleared to 00H, and an interrupt request is not generated. Only if the reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO2 register as the value read from the UF0BO2L register. The value of the UF0BO2L register is decremented each time the UF0BO2 register has been read. UF0BO2L 7 6 5 4 3 2 1 0 Address After reset BKO2L7 BKO2L6 BKO2L5 BKO2L4 BKO2L3 BKO2L2 BKO2L1 BKO2L0 0020010EH 00H Bit position Bit name BKO2L7 to 7 to 0 Function These bits store the length of the data held by the UF0BO2 register. BKO2L0 (9) UF0 bulk-in 1 register (UF0BI1) The UF0BI1 register is a 64-byte x 2 FIFO that stores data for Endpoint1. This register consists of two banks of 64byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when the FIFO on the CPU side is correctly written (FIFO full or BKI1DED bit = 1). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint1 only when the BKI1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to the UF0BI1 register sequentially. A short packet is transmitted when data is written to the UF0BI1 register and the BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0BI1 register is cleared and the BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of the UF0EPS0 register = 1 (data exists)). When the data is transmitted correctly, a FIFO toggle operation occurs. The BKI1DT bit of the UF0IS2 register is set to 1, and an interrupt request is generated for the CPU. An interrupt request or DMA request can be selected by using the DQBI1MS bit of the UF0IDR register. UF0BI1 7 6 5 4 3 2 1 0 Address After reset BKI17 BKI16 BKI15 BKI14 BKI13 BKI12 BKI11 BKI10 00200110H Undefined Bit position Bit name 7 to 0 BKI17 to BKI10 Function These bits store data for Endpoint1. The operation of the UF0BI1 register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1095 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-9. Operation of UF0BI1 Register (1/3) (a) Operation example 1 Transmission FIFO toggle completed ACK Transmission reception starts Status of UF0BI1 register Transmission completed ACK reception FIFO toggle SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed Writing FIFO starts 64-byte transfer Writing FIFO completed 64-byte transfer BKI1NK bit of UF0EN register BKI1DED bit of UF0DEND register is set or hardware set BKI1DT bit of UF0IS2 register 64-byte transfer BKI1DED bit of UF0DEND register is set or hardware set Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1096 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-9. Operation of UF0BI1 Register (2/3) (b) Operation example 2 ACK reception FIFO toggle Status of UF0BI1 register Transmission completed ACK cannot be received Transmission starts Transmission completed ACK reception Retransmission starts SIE side FIFO_0 FIFO_1 FIFO_1 FIFO_0 CPU side Writing Writing FIFO FIFO starts completed Writing FIFO starts 64-byte transfer 64-byte transfer Writing FIFO completed Re-transfer BKI1NK bit of UF0EN register BKI1DT bit of UF0IS2 register Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1097 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-9. Operation of UF0BI1 Register (3/3) (c) Operation example 3 Transmission completed FIFO toggle ACK reception Status of UF0BI1 register Transmission completed Transmission starts FIFO toggle ACK reception SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side FIFO clear Writing FIFO completed Writing FIFO starts 64-byte transfer Transfer of Null packet BKI1NK bit of UF0EN register BKI1DED bit of UF0DEND register is set. BKI1DT bit of UF0IS2 register Short packet transfer BKI1DED bit of UF0DEND register is set. Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1098 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (10) UF0 bulk-in 2 register (UF0BI2) The UF0BI2 register is a 64-byte x 2 FIFO that stores data for Endpoint3. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when the FIFO on the CPU side is correctly written (FIFO full or BKI2DED bit = 1). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint3 only when the BKI2NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to the UF0BI2 register sequentially. A short packet is transmitted when data is written to the UF0BI2 register and the BKI2DED bit of the UF0DEND register is set to 1 (BKIN2 bit of UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0BI2 register is cleared and the BKI2DED bit of the UF0DEND register is set to 1 (BKIN2 bit of the UF0EPS0 register = 1 (data exists)). When the data is transmitted correctly, a FIFO toggle operation occurs. The BKI2DT bit of the UF0IS2 register is set to 1, and an interrupt request is generated for the CPU. An interrupt request or DMA request can be selected by using the DQBI2MS bit of the UF0IDR register. UF0BI2 7 6 5 4 3 2 1 0 Address After reset BKI27 BKI26 BKI25 BKI24 BKI23 BKI22 BKI21 BKI20 00200112H Undefined Bit position Bit name 7 to 0 BKI27 to BKI20 Function These bits store data for Endpoint3. The operation of the UF0BI2 register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1099 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-10. Operation of UF0BI2 Register (1/3) (a) Operation example 1 Transmission FIFO toggle completed ACK Transmission reception starts Status of UF0BI2 register Transmission completed ACK reception FIFO toggle SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed Writing FIFO starts 64-byte transfer Writing FIFO completed 64-byte transfer BKI2NK bit of UF0EN register BKI2DED bit of UF0DEND register is set or hardware set. BKI2DT bit of UF0IS2 register 64-byte transfer BKI2DED bit of UF0DEND register is set or hardware set. Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1100 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-10. Operation of UF0BI2 Register (2/3) (b) Operation example 2 Status of UF0BI2 register Transmission FIFO toggle completed ACK Transmission reception starts ACK cannot be received Transmission completed ACK Re- reception transmission starts SIE side FIFO_0 FIFO_1 FIFO_1 FIFO_0 CPU side Writing Writing FIFO FIFO starts completed Writing FIFO starts 64-byte transfer 64-byte transfer Writing FIFO completed Re-transfer BKI2NK bit of UF0EN register BKI2DT bit of UF0IS2 register Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1101 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-10. Operation of UF0BI2 Register (3/3) (c) Operation example 3 Transmission Transmission FIFO toggle completed completed ACK ACK Transmission reception reception starts Status of UF0BI2 register FIFO toggle SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Writing FIFO completed Writing FIFO starts FIFO clear 64-byte transfer Transfer of Null packet BKI2NK bit of UF0EN register BKI2DED bit of UF0DEND register is set. BKI2DT bit of UF0IS2 register Short packet transfer BKI2DED bit of UF0DEND register is set. Hardware clear INT clear (FW clear) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1102 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (11) UF0 interrupt 1 register (UF0INT1) The UF0INT1 register is an 8-byte FIFO that stores data for Endpoint7 (to be passed to SIE). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint7 only when the IT1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). When the data is transmitted and the host correctly receives it, the IT1NK bit of the UF0EN register is automatically cleared to 0 by hardware. A short packet is transmitted when data is written to the UF0INT1 register and the IT1DEND bit of the UF0DEND register is set to 1 (IT1 bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0INT1 register is cleared and the IT1DEND bit of the UF0DEND register is set to 1 (IT1 bit of the UF0EPS0 register = 1 (data exists)). UF0INT1 Bit position 7 to 0 7 6 5 4 3 2 1 0 Address After reset IT17 IT16 IT15 IT14 IT13 IT12 IT11 IT10 00200114H Undefined Bit name IT17 to IT10 Function These bits store data for Endpoint7. The operation of the UF0INT1 register is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1103 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-11. Operation of UF0INT1 Register (a) 8-byte transfer Transmission Re-transmission completed starts ACK Transmission ACK cannot be received reception starts Transmission completed Transmission ACK starts reception Status of UF0INT1 register 8-byte transfer IT1NK bit of UF0EN register 8-byte transfer FIFO full Re-transfer FIFO full IT1 bit of UF0EPS0 register INT clear (FW clear) IT1DT bit of UF0IS2 register Hardware clear Writing Writing FIFO FIFO starts completed Writing Writing FIFO FIFO starts completed Counter reloaded (b) When Null packet or short packet is transmitted Transmission completed Transmission ACK starts reception Transmission completed ACK Transmission reception starts Status of UF0INT1 register Transfer of Null packet IT1NK bit of UF0EN register Short packet transfer IT1DEND bit of UF0DEND register is set. IT1DEND bit of UF0DEND register is set. IT1 bit of UF0EPS0 register INT clear (FW clear) IT1DT bit of UF0IS2 register Hardware clear FIFO FW clear R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Writing Writing FIFO FIFO starts completed Page 1104 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.5 EPC request data registers (1) UF0 device status register L (UF0DSTL) This register stores the value that is to be returned in response to the GET_STATUS Device request. This register can be read or written in 8-bit units. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Device request. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0DSTL Bit position 1 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 RMWK SFPW 00200144H 00H Bit name RMWK Function This bit specifies whether the remote wakeup function of the device is used. 1: Enabled 0: Disabled If the device supports a remote wakeup function, this bit is set to 1 by hardware when the SET_FEATURE Device request has been received, and is cleared to 0 by hardware when the CLEAR_FEATURE Device request has been received. If the device does not support a remote wakeup function, make sure that the SET_FEATURE Device request is not issued from the host. 0 SFPW This bit indicates whether the device is self-powered or bus-powered. 1: Self-powered 0: Bus-powered R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1105 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0 status register L (UF0E0SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint0 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in USBF, the E0HALT bit is set to 1 by FW. A write access to this register is ignored while a USBside access to Endpoint0 is being received. When the E0HALT bit is set to 1 by FW, it is not reflected until the next SETUP token is received if the control transfer immediately before is for the SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0, GET_STATUS Endpoint0 request, or an FW-processed request. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint0 request. If Endpoint0 has stalled, the UF0E0W and UF0E0R registers are cleared, and the EP0NKW and EP0NKR bits of the UF0E0N register are cleared to 0. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E0SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E0HALT 0020014CH 00H Bit name E0HALT Function This bit indicates the status of Endpoint0. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint0 request has been received, and cleared to 0 by hardware when the CLEAR_FEATURE Endpoint0 request has been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1106 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP1 status register L (UF0E1SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint1 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint1, the E1HALT bit is set to 1. A write access to this register is ignored while a USBside access to Endpoint1 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint1 request. If Endpoint1 has stalled, the UF0BI1 register is cleared and the BKI1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint1, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E1SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E1HALT 00200150H 00H Bit name E1HALT Function This bit indicates the status of Endpoint1. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint1 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint1 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint1 is linked has correctly been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1107 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP2 status register L (UF0E2SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint2 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint2, the E2HALT bit is set to 1. A write access to this register is ignored while a USBside access to Endpoint2 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint2 request. If Endpoint2 has stalled, the UF0BO1 register is cleared and the BKO1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint2, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E2SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E2HALT 00200154H 00H Bit name E2HALT Function This bit indicates the status of Endpoint2. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint2 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint2 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint2 is linked has correctly been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1108 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (5) UF0 EP3 status register L (UF0E3SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint3 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint3, the E3HALT bit is set to 1. A write access to this register is ignored while a USBside access to Endpoint3 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint3 request. If Endpoint3 has stalled, the UF0BI2 register is cleared and the BKI2NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint3, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E3SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E3HALT 00200158H 00H Bit name E3HALT Function This bit indicates the status of Endpoint3. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint3 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint3 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint3 is linked has correctly been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1109 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (6) UF0 EP4 status register L (UF0E4SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint4 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint4, the E4HALT bit is set to 1. A write access to this register is ignored while a USBside access to Endpoint4 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint4 request. If Endpoint4 has stalled, the UF0BO2 register is cleared and the BKO2NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint4, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E4SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E4HALT 0020015CH 00H Bit name E4HALT Function This bit indicates the status of Endpoint4. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint4 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint4 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint4 is linked has correctly been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1110 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (7) UF0 EP7 status register L (UF0E7SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint7 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint7, the E7HALT bit is set to 1. A write access to this register is ignored while a USBside access to Endpoint7 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint7 request. If Endpoint7 has stalled, the UF0INT1 register is cleared and the IT1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint7, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0E7SL Bit position 0 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 0 E7HALT 00200168H 00H Bit name E7HALT Function This bit indicates the status of Endpoint7. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint7 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint7 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint7 is linked has correctly been received. DATA PID is initialized to DATA0. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1111 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (8) UF0 address register (UF0ADRS) This register stores the device address. This register is read-only, in 8-bit units. The device address sent by the SET_ADDRESS request is analyzed and the resultant value is automatically written to this register. If the SET_ADDRESS request is processed by FW, the value of this register is reflected as the device address when the SUCCESS signal is received in the status stage. Caution UF0ADRS Bit position 6 to 0 Do not execute a write access to this register. If written, the operation is not guaranteed. 7 6 5 4 3 2 1 0 Address After reset 0 ADRS6 ADRS5 ADRS4 ADRS3 ADRS2 ADRS1 ADRS0 00200180H 00H Bit name ADRS6 to Function These bits hold the device address of SIE. ADRS0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1112 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (9) UF0 configuration register (UF0CNF) This register stores the value that is to be returned in response to the GET_CONFIGURATION request. This register is read-only, in 8-bit units. When the SET_CONFIGURATION request is received, its wValue is automatically written to this register. When a change of the value of this register from 00H to other than 00H is detected, the CONF bit of the UF0MODS register is set to 1. If the SET_CONFIGURATION request is processed by FW, the status of this register is immediately reflected on the UF0MODS register as soon as data has been written to this register (CONF bit = 1 before completion of the status stage). Caution UF0CNF Bit position 1, 0 Do not execute a write access to this register. If written, the operation is not guaranteed. 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 0 CONF1 CONF0 00200182H 00H Bit name Function CONF1, These bits hold the data to be returned in response to the GET_CONFIGURATION CONF0 request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1113 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (10) UF0 interface 0 register (UF0IF0) This register stores the value that is to be returned in response to the GET_INTERFACE wIndex = 0 request. This register is read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to this register. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed. At this time, the status bit of the target endpoint and DPID are automatically cleared to 0, depending on the setting. The FIFO is not cleared automatically. Caution UF0IF0 Bit position 2 to 0 Do not execute a write access to this register. If written, the operation is not guaranteed. 7 6 5 4 3 2 1 0 Address After reset 0 0 0 0 0 IF02 IF01 IF00 00200184H 00H Bit name IF02 to IF00 Function These bits hold the data to be returned in response to GET_INTERFACE wIndex = 0 request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1114 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (11) UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4) These registers store the value that is to be returned in response to the GET_INTERFACE wIndex = n request (n = 1 to 4). These registers are read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to these registers. These registers are invalidated according to the setting of the UF0AIFN and UF0AAS registers. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed. At this time, the status bit of the target endpoint and DPID are automatically cleared to 0, depending on the setting. The FIFO is not cleared automatically. Caution Do not execute a write access to this register. If written, the operation is not guaranteed. 7 6 5 4 3 2 1 0 Address After reset UF0IF1 0 0 0 0 0 IF12 IF11 IF10 00200186H 00H UF0IF2 0 0 0 0 0 IF22 IF21 IF20 00200188H 00H UF0IF3 0 0 0 0 0 IF32 IF31 IF30 0020018AH 00H UF0IF4 0 0 0 0 0 IF42 IF41 IF40 0020018CH 00H Bit position 2 to 0 Bit name IFn2 to IFn0 Function These bits hold the data to be returned in response to GET_INTERFACE wIndex = n request. Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1115 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (12) UF0 descriptor length register (UF0DSCL) This register stores the length of the value that is to be returned in response to the GET_DESCRIPTOR Configuration request. The value of this register is the number of bytes of all the descriptors set by the UF0CIEn register minus 1 (n = 0 to 255). The total descriptor length that is to be returned in response to the GET_DESCRIPTOR Configuration request is determined according to the value of this register. This register can be read or written in 8-bit units. However, data can be written to this register only when the EP0NKA bit is set to 1. Processing of wLength is automatically controlled. If this register is set to 00H, it means that the descriptor to be returned is 1 byte long. If the register is set to FFH, a descriptor length of 256 bytes is returned. When a descriptor exceeding 256 bytes in length is used, set the CDCGDST bit of the UF0MODC register to 1 and process the GET_DESCRIPTOR request by FW (at this time, the CDCGD bit of the UF0MODS register is also set to 1). Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. UF0DSCL 7 6 5 4 3 2 1 0 Address After reset DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 002001A0H 00H Bit position Bit name 7 to 0 DPL7 to DPL0 Function These bits set the value of the number of bytes of all the descriptors to be returned in response to the GET_DESCRIPTOR Configuration request minus 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1116 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (13) UF0 device descriptor registers 0 to 17 (UF0DD0 to UF0DD17) These registers store the value to be returned in response to the GET_DESCRIPTOR Device request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Cautions 1. To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. Use the value defined by USB Specification Ver. 2.0 and the latest Class Specification as the set value. 7 6 4 5 3 2 1 0 Address After reset See Table 21-5. Undefined UF0DDn (n = 0 to 17) Table 20-5. Mapping and Data of UF0 Device Descriptor Registers Symbol Address Field Name Contents UF0DD0 002001A2H bLength Size of this descriptor UF0DD1 002001A4H bDescriptorType Device descriptor type UF0DD2 002001A6H bcdUSB Value below decimal point of Rev. number of USB specification UF0DD3 002001A8H UF0DD4 002001AAH bDeviceClass Class code UF0DD5 002001ACH bDeviceSubClass Subclass code UF0DD6 002001AEH bDeviceProtocol Protocol code UF0DD7 002001B0H bMaxPacketSize0 Maximum packet size of Endpoint0 UF0DD8 002001B2H idVendor Lower value of vendor ID UF0DD9 002001B4H UF0DD10 002001B6H Value above decimal point of Rev. number of USB specification Higher value of vendor ID idProduct Lower value of product ID bcdDevice Lower value of device release number UF0DD11 002001B8H UF0DD12 002001BAH UF0DD13 002001BCH UF0DD14 002001BEH iManufacturer Index of string descriptor describing manufacturer UF0DD15 002001C0H iProduct Index of string descriptor describing product UF0DD16 002001C2H lSerialNumber Index of string descriptor describing device serial number UF0DD17 002001C4H BNumConfigurations Number of settable configurations R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Higher value of product ID Higher value of device release number Page 1117 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (14) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255) These registers store the value to be returned in response to the GET_DESCRIPTOR Configuration request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Descriptor information of up to 256 bytes can be stored in these registers. Store each descriptor in the order of Configuration, Interface, and Endpoint (see Table 20-6). If there are two or more Interfaces, repeatedly store the data following the Interface descriptor. Table 20-6. Mapping of UF0CIEn Register Address Descriptor Stored 002001C6H Configuration descriptor (9 bytes) 002001D8H Interface descriptor (9 bytes) 002001EAH Endpoint1 descriptor (7 bytes) 002001F8H Endpoint2 descriptor (7 bytes) 00200206H Endpoint3 descriptor (7 bytes) : : 002002xxH Interface descriptor (9 bytes) 002002xxH+9 Endpoint1 descriptor (7 bytes) 002002xxH+16 Endpoint2 descriptor (7 bytes) 002002xxH+23 Endpoint3 descriptor (7 bytes) : : The range of the valid data that can be set to these registers varies according to the setting of the UF0DSCL register. In addition to the descriptors listed in Table 20-7, descriptors peculiar to classes and vendors can also be stored. If all the values are fixed, they can be stored in ROM. Cautions 1. To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. Use the value defined by USB Specification Ver. 2.0 and the latest Class Specification as the set value. 7 6 UF0CIEn 5 4 3 2 1 0 Address After reset 002001C6H to Undefined 002003C4H (n = 0 to 255) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1118 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Table 20-7. Data of UF0CIEn Register (a) Configuration descriptor (9 bytes) Offset Field Name Contents 0 bLength Size of this descriptor 1 bDescriptorType Descriptor type 2 wTotalLength Lower value of the total number of bytes of Configuration, all Interface, and all Endpoint descriptors Higher value of the total number of bytes of Configuration, all Interface, and 3 all Endpoint descriptors 4 bNumInterface Number of Interfaces 5 bConfigurationValue Value to select this Configuration 6 iConfiguration Index of string descriptor describing this Configuration 7 bmAttributes Features of this Configuration (self-powered, without remote wakeup) 8 MaxPower Maximum power consumption of this Configuration (unit: mA) Note Note Shown in 2 mA units. (example: 50 = 100 mA) (b) Interface descriptor (9 bytes) Offset Field Name Contents 0 bLength Size of this descriptor 1 bDescriptorType Descriptor type 2 bInterfaceNumber Value of this Interface 3 bAlternateSetting Value to select alternative setting of Interface 4 bNumEndpoints Number of usable Endpoints 5 bInterfaceClass Class code 6 bInterfaceSubClass Subclass code 7 bInterfaceProtocol Protocol code 8 Interface Index of string descriptor describing this Interface (c) Endpoint descriptor (7 bytes) Offset Field Name Contents 0 bLength Size of this descriptor 1 bDescriptorType Descriptor type 2 bEndpointAddress Address/transfer direction of this Endpoint 3 bmAttributes Transfer type 4 wMaxPaketSize Lower value of maximum number of transfer data 5 6 Higher value of maximum number of transfer data bInterval R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Transfer interval Page 1119 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.6 Bridge register (1) Bridge interrupt control register (BRGINTT) The BRGINTT register controls the DMA transfer status of the interrupt generate status, and each end point (EP1 to EP4) from EPC to bridge circuit. The BRGINTT register can be read or written in 16-bit units. After reset: 0000H BRGINTT Bit position 11 R/W Address: 00200400H 15 14 13 12 11 10 9 8 0 0 0 0 EP4INT EP3INT EP2INT EP1INT 7 6 5 4 3 2 1 0 0 0 0 0 0 EPCINT2B EPCINT1B EPCINT0B Bit name EP4INT Function In EP4, when the DMA transfer is normal terminate, or the error finished in the DMA transferring, this bit is setting. Clearing to "0" by writing "1". 0: DMA transfer not completion 1: DMA transfer completion 10 EP3NT In EP3, when the DMA transfer is normal terminate, or the error finished in the DMA transferring, this bit is setting. Clearing to "0" by writing "1". 0: DMA transfer not completion 1: DMA transfer completion 9 EP2NT In EP2, when the DMA transfer is normal terminate, or the error finished in the DMA transferring, this bit is setting. Clearing to "0" by writing "1". 0: DMA transfer not completion 1: DMA transfer completion 8 EP1NT In EP1, when the DMA transfer is normal terminate, or the error finished in the DMA transferring, this bit is setting. Clearing to "0" by writing "1". 0: DMA transfer not completion 1: DMA transfer completion 2 EPCINT2B Showing the status of the interrupt signal "EPC_INT2B" from EPC. Clear controlling from the request of EPC register 0: Interrupt not issued 1: Interrupt issued 1 EPCINT1B Showing the status of the interrupt signal "EPC_INT1B" from EPC. Clear controlling from the request of EPC register 0: Interrupt not issued 1: Interrupt issued 0 EPCINT0B Showing the status of the interrupt signal "EPC_INT0B" from EPC. Clear controlling from the request of EPC register 0: Interrupt not issued 1: Interrupt issued R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1120 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) Bridge interrupt enable register (BRGINTE) The BRGINTE register controls whether the interrupt generated in the bridge circuit is enabled or disabled. The BRGINTE register can be read or written in 16-bit units. After reset: 0000H BRGINTE Bit position 11 R/W Address: 00200402H 15 14 13 12 11 10 9 8 0 0 0 0 EP4INTN EP3INTN EP2INTN EP1INTN 7 6 5 4 3 2 1 0 0 0 0 0 0 Bit name EP4INTN EPC EPC EPC INT2BEN INT1BEN INT0BEN Function Setting the interrupt occur enable or disable when EP4INT bit is setting. 0: Interrupt disabled 1: Interrupt enabled 10 EP3NTN Setting the interrupt occur enable or disable when EP3INT bit is setting. 0: Interrupt disabled 1: Interrupt enabled 9 EP2NTN Setting the interrupt occur enable or disable when EP2INT bit is setting. 0: Interrupt disabled 1: Interrupt enabled 8 EP1NTN Setting the interrupt occur enable or disable when EP1INT bit is setting. 0: Interrupt disabled 1: Interrupt enabled 2 EPCINT2BEN Setting the interrupt occur enable or disable when EPCINT2BEN bit is setting. 0: Interrupt disabled 1: Interrupt enabled 1 EPCINT1BEN Setting the interrupt occur enable or disable when EPCINT1BEN bit is setting. 0: Interrupt disabled 1: Interrupt enabled 0 EPCINT0BEN Setting the interrupt occur enable or disable when EPCINT0BEN bit is setting. 0: Interrupt disabled 1: Interrupt enabled R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1121 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) EPC macro control register (EPCCLT) The EPCCLT register controls the reset generator to the EPC macro. The EPCCLT register can be read or written in 16-bit units. After reset: 0000H EPCCLT Bit position 0 R/W Address: 00200404H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EPCRST Bit name EPCRST Function Setting the reset occurs to EPC. 0: Reset released 1: Reset issued R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1122 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) CPU I/F bus control register (CPUBCTL) The CPUBCTL register controls the interface between bridge circuit and CPU. The CPUBCTL register can be read or written in 16-bit units. After reset: Undefined CPUBCTL Bit position 2 R/W Address: 00200408H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 BULKWAIT DATAWAIT NOWAIT Bit name BULKWAIT Function Forcibly inserting the 1 wait (bulk wait) when the bulk register is accessed. Note 0: No forcibly insert the bulk wait (default value) 1: Forcibly insert the bulk wait Note The setting is invalid in write accessing, the bulk wait is forcibly inserted. 1 DATAWAIT Forcibly inserting the 1 wait (data wait) after the CPU bus cycle. 0: No forcibly insert the data wait (default value) 1: Forcibly insert the data wait 0 NOWAIT Setting enables/disable the no wait operation of CPU bus cycle. Note 0: No wait disables (default value) 1: No wait enables Note 1 wait or more is inserted. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1123 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.7 DMA register (1) EPn DMA control register 1 (UF0E1DC1 to UF0E4DC1) The UF0E1DC1 to UF0E4DC1 register controls the DMA transfer of end point n (EPn). (n = 1 to 4) The UF0E1DC1 to UF0E4DC1 register can be read or written in 16-bit units. (1/2) After reset: 0000H UF0E1DC1 R/W 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 EP1BULK2 EP1BULK1 EP1BULK0 EP1STOP EP1REQ EP1DMAEN After reset: 0000H UF0E2DC1 R/W 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 EP2BULK2 EP2BULK1 EP2BULK0 EP2STOP EP2REQ EP2DMAEN R/W Address: 00200508H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 EP3BULK2 EP3BULK1 EP3BULK0 EP3STOP EP3REQ EP3DMAEN After reset: 0000H UF0E4DC1 Address: 00200504H 15 After reset: 0000H UF0E3DC1 Address: 00200500H 15 R/W Address: 0020050CH 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 EP4BULK2 EP4BULK1 EP4BULK0 EP4STOP EP4REQ EP4DMAEN R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1124 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 5 to 3 Bit name EPnBULK2, Function Shown the status the state machine "BIN_STATE" for bulk transfer of the internal bridge EPnBULK1, EPnBULK0 2 EPnSTOP EPnBULK2 EPnBULK1 EPnBULK0 "BIN_STATE" status 0 0 0 BIN_IDLE 0 0 1 BIN_CPU 0 1 0 BIN_EPC 0 1 1 BIN_CMP 1 0 0 BIN_END Showing the status (end factor of DMA transfer) of DMA transfer end from EPC 0: End of DMA transfer by EPn_TCNT value "0" 1: End of DMA transfer by negate of "EPC_DMARQ_EPnB" Automatically clear (0) by setting next EP1_DMAEN to "1". 1 EPnREQ Showing the status of "EPC_DMARQ_EPnB" signal from EPC 0: No DMA request signal 1: DMA request signal 0 EPnDMAEN Setting the control of DMA request from EPC 0: Masks DMA request 1: Enables DMA request Automatically clear (0) by complete number of packet transfer setting in EPn_TCNT, or complete the DMA transfer by the negate of DMARQ_EPnB. Caution The setting value is not guaranteed in forcibly end. Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1125 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) EPn DMA control register 2 (UF0E1DC2 to UF0E4DC2) The UF0E1DC2 to UF0E4DC2 register controls the DMA transfer of end point n (EPn). (n = 1 to 4) The UF0E1DC2 to UF0E4DC2 register can be read or written in 16-bit units. (1/2) After reset: 0000H R/W Address: 00200502H 15 14 12 11 10 9 8 EP1 EP1 EP1 EP1 EP1 EP1 EP1 EP1 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 7 6 5 4 3 2 1 0 UF0E1DC2 EP1 EP1 EP1 EP1 EP1 EP1 EP1 EP1 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 12 11 10 9 8 After reset: 0000H R/W Address: 00200506H 15 14 13 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 7 6 5 4 3 2 1 0 UF0E2DC2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 12 11 10 9 8 After reset: 0000H R/W Address: 0020050AH 15 14 13 EP3 EP3 EP3 EP3 EP3 EP3 EP3 EP3 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 7 6 5 4 3 2 1 0 UF0E3DC2 EP3 EP3 EP3 EP3 EP3 EP3 EP3 EP3 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 12 11 10 9 8 After reset: 0000H R/W Address: 0020050EH 15 UF0E4DC2 13 14 13 EP4 EP4 EP4 EP4 EP4 EP4 EP4 EP4 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 7 6 5 4 3 2 1 0 EP4 EP4 EP4 EP4 EP4 EP4 EP4 EP4 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1126 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 15 to 0 Bit name Function EPnTCNT15 to Setting the number of byte to DMA transfer in EPn. EPnTCNT0 End the DMA transfer after the value of EPn_TCNT is "0" to decrement each transfer. Cautions 1. Set this register when EPn_DMAEN = 0. 2. Setting this register to "0" is prohibited. Be sure to set this register +1 value for the value of DMA transfer count register DBC0 to DBC3. 3. The setting value of this register is reflected the counter BIN_TCNT for bulk transfer of the bridge inside. And the value of BIN_TCNT is "0", EPn_TCN is "0", too. 4. Update the value of the counter BIN_TCNT for bulk transfer is stopped when forcibly terminated. Remark n = 1 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1127 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.8 Bulk-in register (1) UF0 EP1 bulk-in transfer data register (UF0EP1BI) The UF0EP1BI register writes the bulk-in transfer data of EP1. The UF0EP1BI register can be read or written in 8-bit or 16-bit units. After reset: 0000H 7 to 0 Address: 00201000H 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EP1BI7 EP1BI6 EP1BI5 EP1BI4 EP1BI3 EP1BI2 EP1BI1 EP1BI0 UF0EP1BI Bit position R/W 15 Bit name Function EP1BI7 to Writing the bulk-out transfer data of EP1. EP1BI0 Data outputting to the EPC macro by writing data to this register. If using this register, setting the address (00201000H) in DMA destination address register (DDAn (n = 0 to 3)) of DMAC. In addition, set the RQnUR1E (n = 0 to 3) bit of the UFDRQEN register to 1 to assign a DMA channel. (2) UF0 EP3 bulk-in transfer data register (UF0EP3BI) The UF0EP3BI register writes the bulk-in transfer data of EP1. The UF0EP3BI register can be read or written in 8-bit or 16-bit units. After reset: 0000H UF0EP3BI Bit position 7 to 0 R/W Address: 00202000H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EP3BI7 EP3BI6 EP3BI5 EP3BI4 EP3BI3 EP3BI2 EP3BI1 EP3BI0 Bit name Function EP3BI7 to Writing the bulk-out transfer data of EP3. EP3BI0 Data outputting to the EPC macro by writing data to this register. If using this register, setting the address (00202000H) in DMA destination address register (DDAn (n = 0 to 3)) of DMAC. In addition, set the RQnUR3E (n = 0 to 3) bit of the UFDRQEN register to 1 to assign a DMA channel. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1128 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.9 Bulk-out register (1) UF0 EP2 bulk-out transfer data register (UF0EP2BO) The UF0EP2BO register writes the bulk-out transfer data of EP2. The UF0EP2BO register can be read or written in 8-bit or 16-bit units. After reset: 0000H UF0EP2BO Bit position 7 to 0 R Address: 00210000H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EP2BO7 EP2BO6 EP2BO5 EP2BO4 EP2BO3 EP2BO2 EP2BO1 EP2BO0 Bit name Function EP2BO7 to Reading the bulk-out transfer data of EP2. EP2BO0 Reading the input data from the EPC macro from this register. If using this register, setting the address (00210000H) in DMA source address register (DSAn (n = 0 to 3)) of DMAC. In addition, set the RQnUR0E (n = 0 to 3) bit of the UFDRQEN register to 1 to assign a DMA channel. Caution If either of the following operations is performed, the data stored in this register is read out and the next bulk-out transfer data is stored into this register. * The UF0EP2BO register is read during program execution. * The UF0EP2BO register is monitored on the memory window while the debugger is being used. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1129 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP4 bulk-out transfer data register (UF0EP4BO) The UF0EP4BO register writes the bulk-out transfer data of EP4. The UF0EP4BO register can be read or written in 8-bit or 16-bit units. After reset: 0000H UF0EP4BO Bit position 7 to 0 R Address: 00220000H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EP4BO7 EP4BO6 EP4BO5 EP4BO4 EP4BO3 EP4BO2 EP4BO1 EP4BO0 Bit name Function EP4BO7 to Reading the bulk-out transfer data of EP4. EP4BO0 Reading the input data from the EPC macro from this register. If using this register, setting the address (00220000H) in DMA source address register (DSAn (n = 0 to 3)) of DMAC. In addition, set the RQnUR2E (n = 0 to 3) bit of the UFDRQEN register to 1 to assign a DMA channel. Caution If either of the following operations is performed, the data stored in this register is read out and the next bulk-out transfer data is stored into this register. * The UF0EP4BO register is read during program execution. * The UF0EP4BO register is monitored on the memory window while the debugger is being used. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1130 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.6.10 Peripheral control registers (1) USBF DMA request enable register (UFDRQEN) The UFDRQEN register specifies the DMA channel to be used and the endpoint to be transferred. The UFDRQEN register can be read or written in 8-bit or 16-bit units. (1/2) After reset: 0000H UFDRQEN Bit position 15, 11, 7, 3 R/W Address: 00240000H 15 14 13 12 11 10 9 8 RQ3UR3E RQ2UR3E RQ1UR3E RQ0UR3E RQ3UR2E RQ2UR2E RQ1UR2E RQ0UR2E 7 6 5 4 3 2 1 0 RQ3UR1E RQ2UR1E RQ1UR1E RQ0UR1E RQ3UR0E RQ2UR0E RQ1UR0E RQ0UR0E Bit name Function RQ3UR3E, Specify the endpoint n (EPn) to be transferred by DMA channel 3. RQ3UR2E, (n = 1 to 4) RQ3UR1E, RQ3UR0E RQ3UR3E RQ3UR2E RQ3UR1E RQ3UR0E EP transferred by DMA3 1 0 0 0 EP4 0 1 0 0 EP3 0 0 1 0 EP2 0 0 0 1 EP1 DMA3 does not transfer EPn Other than above (DMA3 not used) 14, 10, 6, 2 RQ2UR3E, Specify the endpoint n (EPn) to be transferred by DMA channel 2. RQ2UR2E, (n = 1 to 4) RQ2UR1E, RQ2UR0E RQ2UR3E RQ2UR2E RQ2UR1E RQ2UR0E EP transferred by DMA2 1 0 0 0 EP4 0 1 0 0 EP3 0 0 1 0 EP2 0 0 0 1 EP1 Other than above DMA2 does not transfer EPn (DMA2 not used) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1131 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position Bit name 13, 9, 5, 1 RQ1UR3E, Specify the endpoint n (EPn) to be transferred by DMA channel 1. RQ1UR2E, (n = 1 to 4) RQ1UR1E, RQ1UR0E Function RQ1UR3E RQ1UR2E RQ1UR1E RQ1UR0E EP transferred by DMA2 1 0 0 0 EP4 0 1 0 0 EP3 0 0 1 0 EP2 0 0 0 1 EP1 DMA1 does not transfer EPn Other than above (DMA1 not used) 12, 8, 4, 0 RQ0UR3E, Specify the endpoint n (EPn) to be transferred by DMA channel 0. RQ0UR2E, (n = 1 to 4) RQ0UR1E, RQ0UR0E RQ0UR3E RQ0UR2E RQ0UR1E RQ0UR0E EP transferred by DMA0 1 0 0 0 EP4 0 1 0 0 EP3 0 0 1 0 EP2 0 0 0 1 EP1 Other than above DMA0 does not transfer EPn (DMA0 not used) Cautions 1. Setting the same DMA transfer target to multiple DMA channels, and setting multiple DMA transfer targets to the same DMA channel are prohibited. 2. If using the function of this register, set the DMA trigger factor register (DTFRn (n = 0 to 3)) to disable DMA requests by interrupt (00H). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1132 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) The following flowcharts illustrate the program execution when the host is disconnected and then reconnected, and the program execution when power is supplied. Figure 20-12. Flowchart of Program When Host Is Disconnected and Then Reconnected START Checks status of pin interrupt detecting host connection status Host disconnected? No Yes Masks INTUSBF0 and INTUSBF1 interrupts Disables USB bus, enables measures against floating Checks status of pin interrupt detecting host connection status Host connected? No Yes Unmasks USB-related interrupts and discards interrupts Initialization processing of register area Automatic device setup by Plug&Play END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1133 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-13. Flowchart of Program When Power Is Supplied START Masks INTUSBF0 and INTUSBF1 interrupts Starts USBF clock supply Initializes register area, enables measures against floating Checks status of pin interrupt detecting host connection status Host connected? No Yes Unmasks USB-related interrupts and discards interrupts Enables USB bus, disables measures against floating Automatic device setup by Plug&Play END R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1134 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.7 STALL Handshake or No Handshake Errors of USBF are defined to be handled as follows. Transfer Type Transaction Target Function Error Type Control transfer/ Processing Response Packet Endpoint not supported No response None bulk transfer/ Endpoint transfer No response None interrupt transfer direction mismatch CRC error No response None Bit stuffing error No response None Timeout No response None PID check error No response None Unsupported PID (other No response None Control transfer/ IN/OUT/SETUP OUT/SETUP Token Data bulk transfer than Data PID) Control transfer CRC error No response Discard received data Bit stuffing error No response Discard received data OUT Data Data PID mismatch ACK Discard received data SETUP Data Overrun No response Discard received data OUT Data Overrun No response (SETUP stage) Control transfer Note 1 Set SNDSTL bit of UF0SDS register to 1 and discard (data stage) received data Control transfer OUT Data Overrun ACK or Set SNDSTL bit of UF0SDS no response (status stage) Note 2 register to 1 and discard received data Bulk transfer OUT Data Overrun No response Note 1 Set EnHALT bit of UF0EnSL register (n = 0 to 4, 7) to 1 Control transfer/ IN Handshake PID check error - bulk transfer/ Hold transferred data and re-transfer data interrupt transfer Unsupported PID - (other than ACK PID) Timeout Hold transferred data and re-transfer data - Note 3 Note 3 Hold transferred data and re-transfer data Note 3 Notes 1. A STALL response is made to re-transfer by the host. 2. An ACK response is made if the transfer data is of less than MaxPacketSize and the data received in the status stage is discarded. If MaxPacketSize is exceeded, no response is made, the SNDSTL bit of the UF0SDS register is set to 1, and the received data is discarded. 3. If an OUT transaction indicating a change from the data stage to the status stage is received during control transfer, an error is not handled and it is assumed that reception has been correctly completed. Cautions 1. It is judged by the Alternative Setting number currently set whether the target Endpoint is valid or invalid. 2. For the response to the request included in control transfer to/from Endpoint0, see 20.5 Requests. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1135 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.8 Register Values in Specific Status Table 20-8. Register Values in Specific Status (1/2) Register Name After CPU Reset (RESET) After Bus Reset UF0E0N register 00H Value is held. UF0E0NA register 00H Value is held. UF0EN register 00H Value is held. UF0ENM register 00H Value is held. UF0SDS register 00H Value is held. UF0CLR register 00H Value is held. UF0SET register 00H Value is held. UF0EPS0 register 00H Value is held. UF0EPS1 register 00H Value is held. UF0EPS2 register 00H Value is held. UF0IS0 register 00H Value is held. UF0IS1 register 00H Value is held. UF0IS2 register 00H Value is held. UF0IS3 register 00H Value is held. UF0IS4 register 00H Value is held. UF0IM0 register 00H Value is held. UF0IM1 register 00H Value is held. UF0IM2 register 00H Value is held. UF0IM3 register 00H Value is held. UF0IM4 register 00H Value is held. UF0IC0 register FFH Value is held. UF0IC1 register FFH Value is held. UF0IC2 register FFH Value is held. UF0IC3 register FFH Value is held. UF0IC4 register FFH Value is held. UF0IDR register 00H Value is held. UF0DMS0 register 00H Value is held. UF0DMS1 register 00H Value is held. UF0FIC0 register 00H Value is held. UF0FIC1 register 00H Value is held. UF0DEND register 00H Value is held. UF0GPR register 00H Value is held. UF0MODC register 00H Value is held. UF0MODS register 00H Bit 2 (CONF): Cleared (0), Other bits: Value is held. UF0AIFN register 00H Value is held. UF0AAS register 00H Value is held. UF0ASS register 00H 00H UF0E1IM register 00H Value is held. UF0E2IM register 00H Value is held. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1136 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Table 20-8. Register Values in Specific Status (2/2) Register Name After CPU Reset (RESET) After Bus Reset UF0E3IM register 00H Value is held. UF0E4IM register 00H Value is held. UF0E7IM register 00H UF0E0R register Undefined UF0E0L register 00H UF0E0ST register 00H UF0E0W register Undefined Value is held. Note 1 Value is held. Value is held. 00H Note 1 Value is held. Note 1 UF0BO1 register Undefined Value is held. UF0BO1L register 00H Value is held. Note 1 UF0BO2 register Undefined Value is held. UF0BO2L register 00H Value is held. Undefined Note 1 Value is held. UF0BI2 register Undefined Note 1 Value is held. UF0INT1 register Undefined Value is held. UF0DSTL register 00H 00H UF0E0SL register 00H 00H UF0E1SL register 00H 00H UF0E2SL register 00H 00H UF0E3SL register 00H 00H UF0E4SL register 00H 00H UF0E7SL register 00H 00H UF0ADRS register 00H 00H UF0CNF register 00H 00H UF0IF0 register 00H 00H UF0IF1 register 00H 00H UF0IF2 register 00H 00H UF0IF3 register 00H 00H UF0IF4 register 00H 00H UF0DSCL register 00H Value is held. UF0DDn register (n = 0 to 17) Note 2 Note 2 UF0CIEn register (n = 0 to 255) Note 2 Note 2 UF0BI1 register Notes 1. This register can be cleared to 0 by the RESET signal because its write pointer, counter, and read pointer are cleared to 0 when the RESET signal becomes active, in the same manner as clearing by the UF0FICn register, as the register is controlled by FIFO. 2. This register cannot be cleared to 0. Because data can be written to it by FW, however, any value can be written to the register (before doing so, however, be sure to set the EP0NKA bit of the UF0E0NA register to 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1137 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9 FW Processing The following FW processing is performed. * Setting processing on device side for the SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE requests during enumeration processing * Analysis and processing of XXXXStandard, XXXXClass, and XXXXVendor requests not subject to automatic processing * Reading data following bulk-transferred OUT token from receive buffer * Writing data to be returned in response to bulk-transferred IN token * Writing data to be returned in response to interrupt-transferred token The following table lists the requests supported by FW. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1138 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Table 20-9. FW-Supported Standard Requests Request CLEAR_FEATURE Reception Processing/ Side Frequency Interface Explanation Automatic STALL It is considered that this request does not come to Interface response because there is no function selector value, though it is reserved for bmRequestType. When this request is received, the hardware makes an automatic STALL response. SET_FEATURE Interface Automatic STALL It is considered that this request does not come to Interface response because there is no function selector value, though it is reserved for bmRequestType. When this request is received, the hardware makes an automatic STALL response. GET_DESCRIPTOR String FW Returns the string descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and writes the data to be returned to the host, to the UF0E0W register. SET_DESCRIPTOR Device FW Rewrites the device descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and the writes the data for the next control transfer (OUT) to the UF0DDn register (n = 0 to 17). SET_DESCRIPTOR Configuration FW Rewrites the configuration descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and the writes the data for the next control transfer (OUT) to the UF0CIEn register (n = 0 to 255). SET_DESCRIPTOR String FW Rewrites the string descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and loads the data for the next control transfer (OUT). Other NA FW When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and performs the necessary processing. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1139 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.1 Initialization processing Initialization processing is executed in the following two ways. * Initialization of request data register * Setting of interrupt When a request data register is initialized, data for the GET_XXXX request to which a value is to be automatically returned is written and an endpoint is allocated to an interface. In the interrupt settings, the interrupt sources that do not have to be checked can be masked by using the UF0IMn register (n = 0 to 4). The following flowcharts illustrate the above processing. Figure 20-14. Initializing Request Data Register START UF0E0NA register = 01H EP0NKA = 1? (UF0E0NA) No Yes Initialization of request data register UF0MODC register = 40H or 00H Setting of interface and endpoint UF0E0NA register = 00H : See Figure 21-15 Initialization of Request Data Register. If the total number of bytes of the UF0CIEn register exceeds 256, set the UF0MODC register to 40H. No data has to be written to the UF0CIEn register. : See Figure21-16 Setting of Interface and Endpoint. Cancels NAK response to Endpoint0. END Remark n = 0 to 255 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1140 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-15. Initialization Settings of Request Data Register UF0DSTL register = 0XH The value of 0XH depends on the power supply method. * SFPW = 1: Self-powered * SFPW = 0: Bus-powered UF0EnSL register = 00H n = 0 to 4, or 7. Setting is unnecessary if the target endpoint is not used. Setting of UF0DSCL register Input the total number of bytes of the UF0CIEa register. Inputting UF0DDm register Inputting UF0CIEa register Remark If the total number of bytes of the UF0CIEa register exceeds 256, set the UF0MODC register to 40H. No data has to be written to the UF0CIEa register. m = 0 to 17 a = 0 to 255 Figure 20-16. Setting of Interface and Endpoint Setting of UF0AIFN register ADDIF, IFNO1, IFNO0 = 000: Interface number 0 is valid. ADDIF, IFNO1, IFNO0 = 100: Interface numbers 0 and 1 are valid. ADDIF, IFNO1, IFNO0 = 101: Interface numbers 0 to 2 are valid. ADDIF, IFNO1, IFNO0 = 110: Interface numbers 0 to 3 are valid. ADDIF, IFNO1, IFNO0 = 111: Interface numbers 0 to 4 are valid. Setting of UF0AAS register Set Interface number(s) and a link with the 5- or 2-series Alternative Setting. Setting of UF0EnIM register Set a link between the target Interface of endpoint n and Alternative Setting. Set 00H if the target endpoint is not used. Remark n = 1 to 4, 7 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1141 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-17. Setting of Interrupt START Setting of UF0IMn register Mask the interrupt source to avoid issuance of an unnecessary interrupt request (INTUSBF0). END Remark n = 0 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1142 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.2 Interrupt servicing The following flowchart illustrates how an interrupt is serviced. Figure 20-18. Interrupt Servicing START INTUSBF0 active (n = 0 to 4) Reading UF0ISn register Target bit of UF0ICn register = 0 Servicing interrupt END Remark : Processing by hardware The following bits of the UF0ISn register are automatically cleared by hardware when a given condition is satisfied (n = 0 to 4). * E0INDT, E0ODT, SUCES, STG, and CPUDEC bits of UF0IS1 register * BKI2DT, BKI1DT, and IT1DT bits of UF0IS2 register * BKO2FL, BKO2DT, BKO1FL, and BKO1DT bits of UF0IS3 register Because clearing an interrupt source by the UF0ICn register is given a lower priority than setting an interrupt source by hardware, the interrupt source may not be cleared depending on the timing (n = 0 to 4). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1143 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.3 USB main processing USB main processing involves processing USB transactions. The types of transactions to be processed are as follows. * Fully automatically processed request for control transfer * Automatically processed requests for control transfer (SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, CLEAR_FEATURE) * CPUDEC request for control transfer * Processing for bulk transfer (IN) * Processing for bulk transfer (OUT) * Processing for interrupt transfer (IN) Processing for endpoint n involves writing or reading for data transfer. The flowchart shown below is for PIO. (1) Fully automatically processed request for control transfer Because the fully automatically processed request for control transfer is executed by hardware, it cannot be referenced by FW. Therefore, FW does not have to perform any special processing for this request. (2) Automatically processed requests for control transfer (SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, CLEAR_FEATURE) Processing to write a register for automatically processed requests for control transfer, such as SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE requests, is automatically executed by hardware, but an interrupt request is issued for recognition on the device side. This processing may be ignored if there is no special processing to be executed. The flowcharts are shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1144 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-19. Automatically Processed Requests for Control Transfer START Receiving SETUP token Decoding request CLEAR_FEATURE? Yes CLEAR_FEATURE processing No : See Figure 21-20 CLEAR_FEATURE Processing. Yes SET_FEATURE? SET_FEATURE processing No : See Figure 21-21 SET_FEATURE Processing. Yes SET_CONFIGURATION? SET_CONFIGURATION processing No SET_INTERFACE? : See Figure 21-22 SET_CONFIGURATION Processing. Yes SET_INTERFACE processing No Other automatically processed request? : See Figure 21-23 SET_INTERFACE Processing. No Yes Automatic processing CPUDEC processing END END INTUSBF0 active (n = 0, 1) Reading UF0ISn register Reading UF0IS4 register SETINT = 1? (UF0IS4) No CLRRQ = 1? (UF0IS0) Yes No Yes Illegal processing FW processing for SET_INTERFACE SETRQ = 1? (UF0IS0) No Yes Illegal processing SETINTC = 0 (UF0IC4) Reading UF0SET register Reading UF0CLR register FW processing for each request FW processing for each request END END END Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1145 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-20. CLEAR_FEATURE Processing UF0CLR register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is cleared to 0 only when all Halt Features are cleared. CLRRQ = 1 (UF0IS0) Clearing UF0DSTL register Clearing UF0EnSL register HALTn = 0 (UF0EPS2) Remarks 1. n = 0 to 4, 7 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1146 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-21. SET_FEATURE Processing UF0SET register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is not set to 1 by setting the UF0DSTL register. SETRQ = 1 (UF0IS0) Setting UF0DSTL register Setting UF0EnSL register HALTn = 1 (UF0EPS2) EPHALT = 1 (UF0IS0) Remarks 1. n = 0 to 4, 7 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1147 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-22. SET_CONFIGURATION Processing SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) Setting UF0CNF register Remark : Processing by hardware Figure 20-23. SET_INTERFACE Processing SETINT = 1 (UF0IS4) Setting UF0ASS register Setting UF0IFn register Remarks 1. n = 0 to 4 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1148 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (3) CPUDEC request for control transfer The CPUDEC request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). Control transfer (write) indicates a request that uses the OUT transaction in the data stage (e.g., SET_DESCRIPTOR), and control transfer (read) indicates a request that uses the IN transaction in the data stage (e.g., GET_DESCRIPTOR). Control transfer (without data) indicates a request that has no data stage (e.g., SET_CONFIGURATION). The flowcharts are shown below. Figure 20-24. CPUDEC Request for Control Transfer (1/12) (a) Token phase (1/2) START INTUSBF0 active G E Reading UF0ISn register CPUDEC = 1? (UF0IS1) Yes No Appropriate interrupt servicing PROTC = 0 (UF0IC1) STGM = 0 (UF0IM1) CPUDECM = 1 (UF0IM1) Reading UF0E0ST register x 8 times CPUDEC = 0 (UF0IS1) Decoding FW request A Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1149 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (2/12) (a) Token phase (2/2) A It is judged whether the request decoded by the device is supported. Supported request? No Yes Request that uses control transfer (IN), such as GET_DESCRIPTOR String Reading UF0ISn register Yes Control transfer (read)? B No Request that uses control transfer (OUT), such as SET_DESCRIPTOR String Control transfer (write)? No D PROT = 1? (UF0IS1) Yes E No Yes C SNDSTL = 1 (UF0SDS) EP0RC = 1 (UF0FIC0) In the case of an unsupported request for control transfer (write), clear the FIFO because data may be written to the FIFO as a result of OUT transfer before the STALL response is made. STGM = 1 (UF0IM1) CPUDECM = 0 (UF0IM1) STALL handshake response SETUP token received? No Yes SNDSTL = 0 (UF0SDS) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1150 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (3/12) (b) Control transfer (read) (1/4) B CPUDEC = 1? (UF0IS1) No Yes Transmitting NAK E0IN = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register E0IN = 1? (UF0IS1) Yes No Illegal processing E0INM = 1 (UF0IM1) I FW request decode If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte. F Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1151 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24 CPUDEC Request for Control Transfer (4/12) (b) Control transfer (read) (2/4) F No FIFO full? E0DED = 1 (UF0DEND) Yes EP0NKW = 1 (UF0E0N) PROT = 1? (UF0IS1) Yes EP0WC = 1 (UF0FIC0) No G No IN token received? Yes Transmitting data of UF0E0W register No ACK received? Yes H Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1152 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (5/12) (b) Control transfer (read) (3/4) H E0INDT = 1 (UF0IS1) EP0NKW = 0 (UF0E0N) INTUSBF0 active Reading UF0ISn register E0INDT = 1? (UF0IS1) No Yes No transmit data? Illegal processing No I Yes E0INDTC = 0 (UF0IC1) Data of Null packet received? No Yes STG = 1 (UF0IS1) J Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1153 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (6/12) (b) Control transfer (read) (4/4) J INTUSBF0 active Reading UF0ISn register STG = 1? (UF0IS1) No Yes Illegal processing STGM = 1 (UF0IM1) Transmitting ACK SUCES = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes No Illegal processing SUCESC = 0 (UF0IC1) E0INC = 0 (UF0IC1) CPUDECM = 0 (UF0IM1) E0INM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1154 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (7/12) (c) Control transfer (write) (1/4) C OUT token received? No Yes Writing UF0E0R register Normal reception? No Yes Clearing UF0E0R register E0ODT = 1 (UF0IS1) EP0R = 1 (UF0EPS0) EP0NKR = 1 (UF0E0N) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) No K Yes EP0RC = 1 (UF0FIC0) G Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1155 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (8/12) (c) Control transfer (write) (2/4) K E0ODT = 1? (UF0IS1) No Yes Illegal processing Updating data length of UF0E0L register Reading UF0E0R register UF0E0L register data is read up to the value read by the UF0E0R register. Data length other than 0? Yes Data length = Data length - 1 No E0ODT = 0 (UF0IS1) EP0R = 0 (UF0EPS0) EP0NKR = 0 (UF0E0N) Updating data length of UF0E0L register Data length other than 0? Yes C No Data length other than 0? No Yes L Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1156 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (9/12) (c) Control transfer (write) (3/4) L STG = 1 (UF0IS1) E0IN = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) Yes No Clearing read data G STG = 1? (UF0IS1) No Yes Illegal processing Request processing EP0WC = 1 (UF0FIC0) E0DED = 1 (UF0DEND) M Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1157 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (10/12) (c) Control transfer (write) (4/4) M STGM = 1 (UF0IM1) E0INM = 1 (UF0IM1) IN token received? No Yes Transmitting data of Null packet ACK received? No Yes SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes No Illegal processing SUCESC = 0 (UF0IC1) E0INDTC = 0 (UF0IC1) E0INC = 0 (UF0IC1) CPUDECM = 0 (UF0IM1) E0INM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1158 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (11/12) (d) Control transfer (without data stage) (1/2) D IN token of status phase IN token received? No Yes E0IN = 1 (UF0IS1) STG = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register PROT = 1? (UF0IS1) Yes No Request processing aborted G STG = 1? (UF0IS1) Yes No Illegal processing EP0WC = 1 (UF0FIC0) E0DED = 1 (UF0DEND) N Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1159 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-24. CPUDEC Request for Control Transfer (12/12) (d) Control transfer (without data stage) (2/2) N E0INM = 1 (UF0IM1) STGM = 1 (UF0IM1) IN token received? No Yes Transmitting data of Null packet ACK received? No Yes SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) INTUSBF0 active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes No Illegal processing SUCESC = 0 (UF0IC1) E0INC = 0 (UF0IC1) E0INDTC = 0 (UF0IC1) Request processing E0INM = 0 (UF0IM1) CPUDECM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1160 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (4) Processing for bulk transfer (IN) Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1161 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-25. Processing for Bulk Transfer (IN) (Endpoint1) START IN token received? No Yes BKI1IN = 1 (UF0IS2) Returning NAK INTUSBF0 active Reading UF0ISn register BKI1IN = 1? (UF0IS2) No Yes Illegal processing BKI1INM = 1 (UF0IM2) Writing UF0BI1 register Yes If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte. FIFO full? No Yes Data error? BKI1CC = 1 (UF0FIC0) No BKI1DED = 1 (UF0DEND) BKI1NK = 1 (UF0EN) BKI1DT = 1 (UF0IS2) Parallel processing by hardware The timing of the bit value varies depending on the situation on the SIE side. : See Figure 21-26 Parallel Processing by Hardware. END INTUSBF0 active Reading UF0ISn register BKI1DT = 1? (UF0IS2) No Yes No transmit data? Illegal processing No Yes BKI1INC = 0 (UF0IC2) BKI1DTC = 0 (UF0IC2) BKI1INM = 0 (UF0IM2) END Remarks 1. n = 2, 3 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1162 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-26. Parallel Processing by Hardware IN token received? No Yes Transmitting data of UF0BI1 register ACK received? No Yes BKI1NK = 0 (UF0EN) No transmit data? No Yes Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1163 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (5) Processing for bulk transfer (OUT) Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1164 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-27. Normal Processing for Bulk Transfer (OUT) (Endpoint2) START OUT token received? No Yes Writing UF0BO1 register No Normal reception? Yes Clearing UF0BO1 register BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) INTUSBF0 active Reading UF0ISn register BKO1DT = 1? (UF0IS3) No Yes Illegal processing Updating data length of UF0BO1L register Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes Data length = Data length - 1 No BKO1DT = 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) Updating data length of UF0BO1L register Data length = 0? No Yes OUT token received? Illegal processing Yes No END Remarks 1. n = 2, 3 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1165 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) During bulk transfer (OUT), more data may be transmitted from the host than expected by the system. Endpoint2 and Endpoint4 for bulk transfer (OUT) of the V850ES/JC3-H and V850ES/JE3-H consist of two 64-byte buffers so that NAK responses are suppressed as much as possible and data can be read from the CPU side even while the bus side is being accessed as the transfer rate of the USB bus increases. Consequently, if the host sends more data than expected by the system, up to 128 bytes of extra data may be automatically received in the worst case. In this case, change the control flow from that of the normal processing of Endpoint2 and Endpoint4 to the flow illustrated below when the quantity of data expected by the system has decreased to two packets. This flowchart illustrates how Endpoint2 is controlled. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1166 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-28. Processing If More Data Than Expected by System Is Transmitted (Endpoint2) (1/2) START OUT token received? No Yes Writing UF0BO1 register Normal reception? No Yes Clearing UF0BO1 register BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) INTUSBF0 active OUT token received? No Yes Writing UF0BO1 register Normal reception? No Yes Clearing UF0BO1 register BKO1FL = 1 (UF0IS3) BKO1NK = 1 (UF0EN) Reading UF0ISn register BKO1FL = 1? (UF0IS3) Yes No Illegal processing BKO1NKM = 1 (UF0ENM) BKO1NK = 1 (UF0EN) Updating data length of UF0BO1L register I Remarks 1. n = 2, 3 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1167 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-28. Processing If More Data Than Expected by System Is Transmitted (Endpoint2) (2/2) I Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes No Data length = Data length - 1 BKO1FL = 0 (UF0IS3) Updating data length of UF0BO1L register Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes No Data length = Data length - 1 BKO1DT= 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) OUT token received? No Yes Next system sequence? BKO1NAK = 1 (UF0IS3) Yes NAK response BKO1NKM = 0 (UF0ENM) INTUSBF0 active BKO1NK = 0 (UF0EN) BKO1NAK = 1? (UF0IS3) Yes No Expected system sequence processing No Illegal processing END Expected processing such as Endpoint STALL BKO1NKM = 0 (UF0ENM) BKO1NK = 0 (UF0EN) BKO1NAKC = 0 (UF0IC3) END Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1168 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (6) Processing for interrupt transfer (IN) Interrupt transfer (IN) is allocated to Endpoint7. The flowchart is shown in Figure 20-29. Figure 20-29. Processing for Interrupt Transfer (IN) (Endpoint7) START Reading UF0EPS0 register IT1 = 0? (UF0EPS0) No Yes Writing UF0INT1 register FIFO full? No Yes Data error? Yes No IT1DEND = 1 (UF0DEND) ITR1C = 1 (UF0FIC0) IT1NK = 1 (UF0EN) IN token received? No Yes Transmitting data of UF0INT1 register ACK received? No Yes IT1DT = 1 (UF0IS2) IT1 = 0 (UF0EPS0) IT1NK = 0 (UF0EN) INTUSBF0 active Reading UF0ISn register IT1DT = 1? (UF0IS2) No Yes No transmit data? Illegal processing No Yes IT1DTC = 0 (UF0IC2) END Remarks 1. n = 2, 3 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1169 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.4 Suspend/Resume processing How Suspend/Resume processing is performed differs depending on the configuration of the system. One example is given below. Figure 20-30. Example of Suspend/Resume Processing (1/3) (a) Example of Suspend processing START Suspend detected? No Yes RSUSPD = 1 (UF0IS0) RSUM = 1 (UF0EPS1) INTUSBF0 active Reading UF0ISn register RSUSPD = 1? (UF0IS0) No Yes Illegal processing Reading UF0EPS1 register RSUM = 1? (UF0EPS1) Yes No Illegal processing FW Suspend processing RSUSPDC = 0 (UF0IC0) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1170 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-30. Example of Suspend/Resume Processing (2/3) (b) Example of Resume processing START Resume detected? No Yes RSUSPD = 1 (UF0IS0) RSUM = 0 (UF0EPS1) INTUSBF0 active Reading UF0ISn register RSUSPD = 1? (UF0IS0) No Yes Illegal processing Reading UF0EPS1 register RSUM = 0? (UF0EPS1) Yes No Illegal processing FW Resume processing RSUSPDC = 0 (UF0IC0) END Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1171 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-30. Example of Suspend/Resume Processing (3/3) (c) Example of Resume processing (when supply of USB clock to USBF is stopped) START Resume detected? No Yes INTUSBF1 active Executing interrupt servicing Supplying USB clock FW Resume processing END Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1172 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.5 Processing after power application The processing to be performed after power application differs depending on the configuration of the system. One example is given below. Figure 20-31. Example of Processing After Power Application/Power Failure (1/3) (a) Processing after power application (1/2) START START Pull-up processing of D+ inactiveNote 1 Initialization of request data register Initialization of request data register : See Figure 21-15 Initialization Settings of Request Data Register. : See Figure 21-15 Initialization Settings of Request Data Register. Controlling portNote 2 Controlling portNote 2 Pull-up processing of D+ activeNote 1 Connection Resume detected? No Yes BUSRST = 1 (UF0IS0) DFLT = 1 (UF0MODS) (a) Notes 1. Use one general-purpose port pin for the signal that controls switching of the pull-up resistor of the USB bus. 2. The input mode or control mode of the general-purpose port pin allocated in Note 1 may be selected as the default value. Note the active level of pull-up processing of D+ on power application. Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1173 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-31. Example of Processing After Power Application/Power Failure (2/3) (a) Processing after power application (2/2) (a) Receiving GET_DESCRIPTOR Device request MPACK = 1 (UF0MODS) Receiving SET_ADDRESS request Writing UF0ADRS register Receiving SET_CONFIGURATION 1 request SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) UF0CNF register = 01H Valid endpoint = DATA0 Receiving SET_INTERFACE request SETINT = 1 (UF0IS4) Setting of UF0ASS register Setting of UF0IFm register Valid endpoint = DATA0 Processing continues Remarks 1. m = 0 to 4 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1174 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-31. Example of Processing After Power Application/Power Failure (3/3) (b) Processing on power failure START Power failure INTPxx activeNote? No Yes Interrupt servicing Processing such as clearing FIFO or MRST = 1 (UF0GPR) END Note INTPxx indicates the external interrupt pins of the V850ES/JC3-H and V850ES/JE3-H (INTP00 to INTP18), and also indicates interrupts input by the external trigger pins (TIAA00, TAA01, TIAA10, TIAA11, TIAA20, TIAA21, TIAB10, TRGAB1, TIT00) of the timer. Allocate one external interrupt pin to the following applications. * Detecting disconnection of the connector in the case of self-powered mode (SFPW bit of UF0DSTL register = 1). In this case, monitor the VDD line of the USB connector, and input the result to the external interrupt pin at the edge. Note that the noise elimination time is that of the interrupt input pin, and that of each timer. * Detecting turning off power from the HUB when the device is mounted on the same board as a HUB chip. Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1175 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.6 Receiving data for bulk transfer (OUT) in DMA mode Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled when DMA is used. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. The control flowchart shown below illustrates how remaining data is read by the CPU. If data for bulk transfer (OUT) has been correctly received by setting the DQBO1MS bit of the UF0IDR register to 1, the DMA request signal for Endpoint2, instead of an interrupt request (INTUSBF0), becomes active. This DMA request signal for Endpoint2 operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data stored in the UF0BO1 register has been read by DMA, the DMA request signal for Endpoint2 becomes inactive. In this status, if data for the next bulk transfer (OUT) has been correctly received, the DMA request signal for Endpoint2 becomes active again. If the data for bulk transfer (OUT) that has been received is equal to or less than the FIFO size, a Short interrupt request is issued and the INTUSBF0 (EP2_ENDINT) signal becomes active, as soon as reading the data by DMA is completed. To read data by DMA again, set the DQBO1MS bit to 1 again. If DMA is completed by the DMA end signal for Endpoint2, the DQBO1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint2 becomes inactive. At the same time, the DMA_END interrupt request is issued. If data remains in the UF0BO1 register at this time, DMA can be started again by setting the DQBO1MS bit of the UF0IDR register again. However, the data for bulk transfer (OUT) is always equal to or less than the FIFO size. Consequently, a Short interrupt request is issued, the INTUSBF0 (EP2_ENDINT) signal becomes active, the DQBO1MS bit is cleared, and the DMA request signal for Endpoint2 becomes inactive, as soon as the data is read by DMA. Cautions 1. The DMA request signal for Endpoint n (n = 2, 4) becomes active in the demand mode (MODE1 and MODE0 bits of the UF0IDR register = 10), as long as there is data to be transferred. 2. For a DMA transfer for which the data for a bulk transfer (OUT) is a Short packet (63 bytes or less), after the transfer finishes, clear the UF0IC0.SHORTC and UF0IS0.SHORT bits. If the SHORT bits are not cleared, the DMASTOP_EPnB signal is asserted and the next DMA transfer operation is not performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1176 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) (1) Initial settings for a bulk transfer (OUT: EP2, EP4) (a) Initial settings for DMAC - The DSAn registers (n = 0 to 3) are set to 00210000H (for EP2) or 00220000H (for EP4). - The DADCn registers (n = 0 to 3) are set to 0080H. (8-bit transfer, transfer source address: fixed, transfer destination address: incremental) - The DTFRn registers (n = 0 to 3) are set to 0000H. - The UFDRQEN register is set up according to the DMA channel to be used. (For details, see 20.6.10 (1) USBF DMA request enable register (UFDRQEN).) (b) Initial settings for EPC - The UF0IDR register is set to 12H (for EP2) or 22H (for EP4) (demand mode). - The UF0IM0.DMAEDM bit = 0 - The UF0IM3.BKO1NLM bit = 0 (for EP2) - The UF0IM3.BKO1DTM bit = 0 (for EP2) - The UF0IM3.BKO2NLM bit = 0 (for EP4) - The UF0IM3.BKO2DTM bit = 0 (for EP4) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1177 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-32. DMA Processing by Bulk Transfer (OUT) (1/3) START Specifying DMA channel and transfer destination endpoint using UFDRQEN register UF0IDR register = 02H (setting demand mode) Setting DMA channel 2 Setting address (DDA2) of transfer destination (internal data RAM) Setting address (DSA2) of transfer source (Endpoint2 (UF0BO1)) DBC2 DADC2 register = 0080H Setting DMA channel 3 Setting address (DDA3) of transfer destination (Endpoint1 (UF0BI1)) Setting address (DSA3) of transfer source (internal data RAM) DBC3L register = 003FH* DADC3 register = 0020H *: When transferring less than 64 bytes, change the set value. USB setting (DMA related) * DMAEDM = 0 (UF0IM0)* * BKI1NM = 0 (UF0IM2) * BKI1DTM = 0 (UF0IM2) * BKO1NLM = 0 (UF0IM3) * BKO1DTM = 0 (UF0IM3) *: Release the mask setting of the necessary interrupts Setting DMA channel 2 E22 = 1 (DCHC2) DTFR2 register = 00H The use of an interrupt request signal as the DMA start trigger is disabled. DQBO1MS = 1(UF0IDR) UF0E2DC1 = 0001H Setting DMA channel 3 E33 = 1 (DCHC3) DTFR3 register = 00H The use of an interrupt request signal as the DMA start trigger is disabled. DQBI1MS = 1 (UF0IDR) UF0E1DC1 = 0001H (4) (3) Transfer of DMA channel 3 is completed? Yes No (2) (1) Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1. 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1178 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-32. DMA Processing by Bulk Transfer (OUT) (2/3) (1) DMA channel 3 transfer completion TC3 = 1 (DCHC3) DQBI1MS = 0 (UF0IDR) Moving to INTDMA3 interrupt vector Clearing DMA channel 3 transfer request Each bit cleared by reading UF0DMSI TC3 bit cleared by reading DCHC3 Setting DMA channel 3 E33 = 1 (DCHC3) DQBI1MS = 1 (UF0IDR)* The number of DMA channel 3 transfers has been changed? Yes *: Re-set DMA channel 3 No (3) Changing the set value of DBC3L register (3) Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1. 2. n = 0, 1 3. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1179 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-32. DMA Processing by Bulk Transfer (OUT) (3/3) (2) DMA channel 2 transfer completed? No Yes INTUSBF0 interrupt occurred? DMA channel 2 transfer completion TC2 = 1 (DCHC2) DQBO1MS = 0 (UF0IDR) No An interrupt occurred when receiving Endpoint2 data. Yes Moving to INTUSBF0 interrupt vector Moving to INTDMA2 interrupt vector Reading UF0IS3 register Clearing DMA channel 2 transfer request Each bit cleared by reading UF0DMSI TC2 bit cleared by reading DCHC2 BKO1DT = 1 (UF0IS3)? (4) BKO1NL = 1? (UF0IS3) No Confirm data reception. Yes No Cancel transfer when NULL packet is received. Yes Reading UF0BO1 register Setting DMA channel 2 *: After setting the number of DMA channel 2 transfers DBC2L = UF0BO1L - 1* E22 = 1 (DCHC2) DQBO1MS = 1 (UF0IDR) Starting transfer of DMA channel 2 (4) Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1. 2. n = 0, 1 m = 2, 3 3. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1180 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) 20.9.7 Transmitting data for bulk transfer (IN) in DMA mode Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled when DMA is used. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3. If data for bulk transfer (IN) can be written by setting the DQBI1MS bit of the UF0IDR register to 1, the DMA request signal for Endpoint1, instead of an interrupt request (INTUSBF0), becomes active. This DMA request signal for Endpoint1 operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data that can be written to the UF0BI1 register has been written by DMA, the DMA request signal for Endpoint1 becomes inactive. In this status, the toggle operation of the FIFO takes place and, if data for bulk transfer (IN) can be written, the DMA request signal for Endpoint1 becomes active again. The automatic toggle operation of the FIFO is not executed even if the FIFO has become full as a result of DMA transfer, unless the BKI1T bit of the UF0DEND register is set to 1. Therefore, be sure to set the BKI1DED bit of the UF0DEND register to 1 to transfer data. If DMA is completed by the DMA end signal for Endpoint1, the DQBI1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint1 becomes inactive. At the same time, the DMA_END interrupt request is issued. To transmit a short packet at this time when the FIFO is not full, set the BKI1DED bit of the UF0DEND register to 1. Caution The DMA request signal for Endpoint n (n = 1, 3) becomes active in the demand mode (MODE1 and MODE0 bits of the UF0IDR register = 10), as long as data can be transferred. (1) Initial settings for a bulk transfer (IN: EP1, EP3) (a) Initial settings for DMAC - The DSAn registers (n = 0 to 3) are set to 00201000H (for EP1) or 00202000H (for EP3). - The DADCn registers (n = 0 to 3) are set to 0020H. (8-bit transfer, transfer source address: incremental, transfer destination address: fixed) - The DTFRn registers (n = 0 to 3) are set to 0000H. - The UFDRQEN register is set up according to the DMA channel to be used. (For details, see 20.6.10 (1) USBF DMA request enable register (UFDRQEN).) (b) Initial settings for EPC - The UF0IDR register is set to 42H (for EP1) or 82H (for EP3) (demand mode). - The UF0IM0.DMAEDM bit = 0 - The UF0IM2.BKI1NLM bit = 0 (for EP1) - The UF0IM2.BKI1DTM bit = 0 (for EP1) - The UF0IM2.BKI2NLM bit = 0 (for EP3) - The UF0IM2.BKI2DTM bit = 0 (for EP3) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1181 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-33. DMA Processing by Bulk Transfer (IN) (1/4) START (5) Setting MODEx (UF0IDR) DQBI1MS = 1 (UF0IDR) MODE1, MODE0 = 10: Demand mode (3) FIFO on CPU side full? Yes No DQE1 = 1 (UF0DMS0) DMA request for Endpoint1 active If return data greater than the FIFO size exists, it is divided into FIFO size units, and sequentially written, starting from the lowest data byte. Writing UF0BI1 register by DMA TC signal received? Yes (1) No FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes (2) Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1182 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-33. DMA Processing by Bulk Transfer (IN) (2/4) (2) BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DQE1 = 0 (UF0DMS0) DMA request for Endpoint1 inactive (3) Parallel processing by hardware : See Figure 21-26 Parallel Processing by Hardware. END Note The timing of the bit value changes depending on the status on the SIE side. Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1183 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-33. DMA Processing by Bulk Transfer (IN) (3/4) (1) FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DQE1 = 0 (UF0DMS0) DEDE1 = 1 (UF0DMS1) DMAED = 1 (UF0IS0) DQBI1MS = 0 (UF0IDR) DQE1 = 0 (UF0DMS0) DEDE1 = 1 (UF0DMS1) DMAED = 1 (UF0IS0) DQBI1MS = 0 (UF0IDR) INTUSBF0 active DMA request for Endpoint1 inactive Reading UF0ISn register DMAED = 1? (UF0IS0) No Yes Illegal processing Reading UF0DMSn register DEDE1 = 1? (UF0DMS1) Yes No Illegal processing (4) Note The timing of the bit value changes depending on the status on the SIE side. Remarks 1. n = 0, 1 2. : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1184 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 20 USB FUNCTION CONTROLLER (USBF) Figure 20-33 DMA Processing by Bulk Transfer (IN) (4/4) (4) FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes Data error? No DMAEDC = 0 (UF0IC0) (5) Parallel processing by hardware Yes : See Figure 21-26 Parallel Processing by Hardware. BKI1DED = 1 (UF0DEND) BKI1CC = 1 (UF0FIC0) BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DMAEDC = 0 (UF0IC0) END (5) Note The timing of the bit value changes depending on the status on the SIE side. Remark : Processing by hardware R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1185 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) The V850ES/JC3-H and V850ES/JE3-H include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory). 21.1 Features * 4 independent DMA channels * Transfer unit: 8/16 bits * Maximum transfer count: 65,536 (216) * Transfer type: Two-cycle transfer * Transfer mode: Single transfer mode * Transfer requests * Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts from external input pin * Requests by software trigger * Transfer targets * Internal RAM Peripheral I/O * Peripheral I/O Peripheral I/O R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1186 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.2 Configuration On-chip peripheral I/O Internal RAM Internal bus On-chip peripheral I/O bus CPU Data control Address control DMA source address register n (DSAnH/DSAnL) DMA destination address register n (DDAnH/DDAnL) Count control DMA transfer count register n (DBCn) DMA channel control register n (DCHCn) DMA addressing control register n (DADCn) Channel control DMA trigger factor register n (DTFRn) DMAC Bus interface V850ES/JC3-H, V850ES/JE3-H Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1187 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DSA0H FFFFF082H, DSA1H FFFFF08AH, DSA2H FFFFF092H, DSA3H FFFFF09AH, DSA0L FFFFF080H, DSA1L FFFFF088H, DSA2L FFFFF090H, DSA3L FFFFF098H DSAnH (n = 0 to 3) DSAnL (n = 0 to 3) IR 0 0 0 0 0 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 IR Specification of DMA transfer source 0 External memory or on-chip peripheral I/O 1 Internal RAM SA25 to SA16 Set the address (A25 to A16) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. SA15 to SA0 Set the address (A15 to A0) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0. 2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are read. If reading and updating conflict, the value being updated may be read (see 21.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1188 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DDA0H FFFFF086H, DDA1H FFFFF08EH, DA2H FFFFF096H, DDA3H FFFFF09EH, DDA0L FFFFF084H, DDA1L FFFFF08CH, DDA2L FFFFF094H, DDA3L FFFFF09CH DDAnH (n = 0 to 3) DDAnL (n = 0 to 3) IR 0 0 0 0 0 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 IR Specification of DMA transfer destination 0 External memory or on-chip peripheral I/O 1 Internal RAM DA25 to DA16 Set an address (A25 to A16) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. DA15 to DA0 Set an address (A15 to A0) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0. 2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are read. If reading and updating conflict, a value being updated may be read (see 21.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1189 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer. These registers are decremented by 1 per transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H, DBC2 FFFFF0C4H, DBC3 FFFFF0C6H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBCn BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 (n = 0 to 3) BC15 to BC0 Transfer count setting or remaining transfer count during DMA transfer 0000H Transfer count of 1st transfer or remaining transfer count 0001H Transfer count of 2nd transfer or remaining transfer count : FFFFH : Transfer count of 65,536 (216)th transfer or remaining transfer count The number of transfer data set first is held when DMA transfer is complete. Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1190 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units. Reset sets these registers to 0000H. After reset: 0000H R/W Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H, DADC2 FFFFF0D4H, DADC3 FFFFF0D6H DADCn 15 14 13 12 11 10 9 8 0 DS0 0 0 0 0 0 0 (n = 0 to 3) 7 6 5 4 3 2 1 0 SAD1 SAD0 DAD1 DAD0 0 0 0 0 Setting of transfer data size DS0 0 8 bits 1 16 bits SAD1 SAD0 0 0 Increment Setting of count direction of the transfer source address 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited DAD1 DAD0 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited Setting of count direction of the destination address Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to 0. 2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit data (DS0 bit = 0) is set, therefore, the lower data bus is not always used. 4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an odd address. Transfer is always started from an address with the first bit of the lower address aligned to 0. 5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or destination), be sure to specify the same transfer size as the register size. For example, to execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1191 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are writeonly. If bit 1 or 2 is read, the read value is always 0.) Reset sets these registers to 00H. After reset: 00H R/W Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H, DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H DCHCn <7> 6 5 4 3 TCnNote 1 0 0 0 0 <2> <1> INITnNote 2 STGnNote 2 <0> Enn (n = 0 to 3) TCnNote 1 Status flag indicates whether DMA transfer through DMA channel n has completed or not 0 DMA transfer had not completed. 1 DMA transfer had completed. It is set to 1 on the last DMA transfer and cleared to 0 when it is read. INITnNote 2 If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the DMA transfer status can be initialized. When re-setting the DMA transfer status (re-setting the DDAnH, DDAnL, DSAnH, DSAnL, DBCn, and DADCn registers) before DMA transfer is completed (before the TCn bit is set to 1), be sure to initialize the DMA channel. When initializing the DMA controller, however, be sure to observe the procedure described in 21.13 Cautions. STGnNote 2 This is a software startup trigger of DMA transfer. If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA transfer is started. Enn Setting of whether DMA transfer through DMA channel n is to be enabled or disabled 0 DMA transfer disabled 1 DMA transfer enabled DMA transfer is enabled when the Enn bit is set to 1. When DMA transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. To abort DMA transfer, clear the Enn bit to 0 by software. To resume, set the Enn bit to 1 again. When aborting or resuming DMA transfer, however, be sure to observe the procedure described in 22.13 Cautions. Notes 1. The TCn bit is read-only. 2. The INITn and STGn bits are write-only. Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to 0. 2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are being updated, a value indicating "transfer not completed and transfer is disabled" (TCn bit = 0 and Enn bit = 0) may be read. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1192 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units. Reset sets these registers to 00H. (1/2) After reset: 00H R/W Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H, DTFR2 FFFFF814H, DTFR3 FFFFF816H DTFRn <7> 6 5 4 3 2 1 0 DFn 0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 (n = 0 to 3) DFnNote DMA transfer request status flag 0 No DMA transfer request 1 DMA transfer request Note Do not set the DFn bit to 1 by software. Write 0 to this bit to clear a DMA transfer request if an interrupt that is specified as the DMA transfer start factor occurs while DMA transfer is disabled. Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 2. Be sure to follow the steps below when changing the DTFRn register settings. * When the values to be set to bits IFCn5 to IFCn0 are not set to bits IFCm5 to IFCm0 of another channel. <1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0). <2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the settings in the 8-bit manipulation.) <3> Confirm that DFn bit = 0. (Stop the interrupt generation source operation beforehand.) <4> Enable the DMAn operation (Enn bit = 1). * When the values to be set to bits IFCn5 to IFCn0 are set to bits IFCm5 to IFCm0 of another channel. <1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0). <2> Stop the DMAm operation of the channel where the same values are set to bits IFCm5 to IFCm0 as the values to be used to rewrite bits IFCn5 to IFCn0 (DCHCm.Emm bit = 0). <3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the settings in the 8-bit manipulation.) <4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation source operation beforehand.) <5> Enable the DMAn operation (bits Enn and Emm = 1). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1193 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (2/2) Cautions 3. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or subIDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1). 4. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA transfer is enabled or disabled. If DMA is enabled in this status, DMA transfer is immediately started. Remark For the IFCn5 to IFCn0 bits, see Table 21-1 DMA Start Factors. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1194 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) Table 21-1. DMA Start Factors (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source 0 0 0 0 0 0 DMA request by interrupt disabled 0 0 0 0 0 1 INTP02 0 0 0 0 1 0 INTP05 0 0 0 0 1 1 INTP09 0 0 0 1 0 0 INTP10 0 0 0 1 1 0 INTP16 0 0 1 1 0 0 INTTAB1OV_BASE 0 0 1 1 0 1 INTTAB1CC0 0 0 1 1 1 0 INTTAB1CC1 0 0 1 1 1 1 INTTAB1CC2 0 1 0 0 0 0 INTTAB1CC3 0 1 0 0 0 1 INTTT0OV 0 1 0 0 1 0 INTTT0CC0 0 1 0 0 1 1 INTTT0CC1 0 1 0 1 0 0 INTTAA0OV 0 1 0 1 0 1 INTTAA0CC0 0 1 0 1 1 0 INTTAA0CC1 0 1 0 1 1 1 INTTAA1OV 0 1 1 0 0 0 INTTAA1CC0 0 1 1 0 0 1 INTTAA1CC1 0 1 1 0 1 0 INTTAA2CC0 0 1 1 0 1 1 INTTAA2CC1 0 1 1 1 1 0 INTTAA4CC0 0 1 1 1 1 1 INTTAA4CC1 1 0 0 0 1 0 INTTM0EQ0 1 0 0 0 1 1 INTTM1EQ0 1 0 0 1 0 0 INTTM2EQ0 1 0 0 1 0 1 INTTM3EQ0 1 0 0 1 1 0 INTCF0R/INTIIC1 1 0 0 1 1 1 INTCF0T Note Note INTTAB1OV_BASE is the interrupt signal from before the overflow interrupt of TAB1 (INTTAB1OV) was culled by TMQOP. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1195 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) Table 21-1. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source 1 0 1 0 1 0 INTCF2R 1 0 1 0 1 1 INTCF2T 1 0 1 1 0 0 INTCF3R 1 0 1 1 0 1 INTCF3T 1 0 1 1 1 0 INTCF4R 1 0 1 1 1 1 INTCF4T 1 1 0 0 0 0 INTUC0R 1 1 0 0 0 1 INTUC0T 1 1 0 1 0 0 INTUC2R 1 1 0 1 0 1 INTUC2T 1 1 0 1 1 0 INTUC3R Note /INTIIC0 Note 1 1 0 1 1 1 INTUC3T 1 1 1 0 0 0 INTUC4R 1 1 1 0 0 1 INTUC4T 1 1 1 0 1 0 INTAD 1 1 1 0 1 1 INTKR 1 1 1 1 0 0 INTRTC1 Note V850ES/JC3-H (48 pin), V850ESJE3-H only. Remark n = 0 to 3 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1196 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.4 Transfer Targets Table 21-2 shows the relationship between the transfer targets (: Transfer enabled, x: Transfer disabled). Table 21-2. Relationship Between Transfer Targets Transfer Destination Internal ROM On-Chip Internal RAM Source Peripheral I/O Caution On-chip peripheral I/O x Internal RAM x x Internal ROM x x x The operation is not guaranteed for combinations of transfer destination and source marked with "x" in Table 21-2. 21.5 Transfer Modes Single transfer is supported as the transfer mode. In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. If a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the CPU (the new transfer request of the same channel is ignored in the transfer cycle). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1197 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination. An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows. <16-bit data transfer> <1> Transfer from 32-bit bus 16-bit bus A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a write cycle (16 bits). <2> Transfer from 16-/32-bit bus to 8-bit bus A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> Transfer from 8-bit bus to 16-/32-bit bus An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> Transfer between 16-bit bus and 32-bit bus A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. Remark The bus width of each transfer target (transfer source/destination) is as follows. * On-chip peripheral I/O: 16-bit bus width * Internal RAM: R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 32-bit bus width Page 1198 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 21.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below. Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note 1 + Transfer destination memory access (<2>) DMA Cycle Minimum Number of Execution Clocks Note 2 <1> DMA request response time 4 clocks (MIN.) + Noise elimination time <2> Memory access Internal RAM access 2 clocks Peripheral I/O register access 3 clocks + Number of wait cycles specified by VSWC register USB register access 4 clocks Data-only RAM access 4 clocks Note 3 Note 4 Note 5 Note 5 Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer. 2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is added (n = 00 to 18). 3. Two clocks are required for a DMA cycle. 4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.9 (2)). 5. This is the number of clocks required when the following wait specifications have been made: 1 data wait (set by the DWC0 register), 0 address waits (set by the AWC register), and 0 idle waits (set by the BCC register). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1199 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3). TCn bit = 0, Enn bit = 1 STGn bit = 1 ... Starts the first DMA transfer. Confirm that the contents of the DBCn register have been updated. STGn bit = 1 ... Starts the second DMA transfer. : Generation of terminal count ... Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated. (2) Request by on-chip peripheral I/O If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA channel. If two start factors are simultaneously generated for one DMA channel, only one of them is valid. The start factor that is valid cannot be identified. 2. A new transfer request that is generated after the preceding DMA transfer request was generated or in the preceding DMA transfer cycle is ignored (cleared). 3. The transfer request interval of the same DMA channel varies depending on the setting of bus wait in the DMA transfer cycle, the start status of the other channels, or the external bus hold request. In particular, as described in Caution 2, a new transfer request that is generated for the same channel before the DMA transfer cycle or during the DMA transfer cycle is ignored. Therefore, the transfer request intervals for the same DMA channel must be sufficiently separated by the system. When the software trigger is used, completion of the DMA transfer cycle that was generated before can be checked by updating the DBCn register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1200 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) 21.10 DMA Abort Factors DMA transfer is aborted if a bus hold occurs. The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/onchip peripheral I/O. When the bus hold is cleared, DMA transfer is resumed. 21.11 End of DMA Transfer When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). The V850ES/JC3-H and V850ES/JE3-H do not output a terminal count signal to external devices. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit. 21.12 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.9 (1) (a) System wait control register (VSWC)). (2) Caution for reading DCHCn.TCn bit (n = 0 to 3) The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing. To accurately clear the TCn bit, add the following processing. (a) When waiting for completion of DMA transfer by polling TCn bit Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more times. (b) When reading TCn bit in interrupt servicing routine Execute reading the TCn bit three times. (3) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels Initialize the channel executing DMA transfer using the procedure in <1> to <7> below. Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other processing programs do not expect that the TCn bit is 1. <1> Disable interrupts (DI). <2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA transfer (transfer source/destination) is the internal RAM, execute the instruction three times. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1201 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal RAM). * Clear DCHC0.E00 bit to 0. * Clear DCHC1.E11 bit to 0. * Clear DCHC2.E22 bit to 0. * Clear DCHC2.E22 bit to 0 again. <4> Set the INITn bit of the channel to be forcibly terminated to 1. <5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0. <6> After the operation in <5>, write the Enn bit value to the DCHCn register. <7> Enable interrupts (EI). Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels whose DMA transfer has been normally completed between <2> and <3>. (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the pending request is completed. <3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held pending, clear the Enn bit to 0. <4> Again, clear the Enn bit of the channel to be forcibly terminated. If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal RAM, execute this operation once more. <5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register. <6> Set the INITn bit of the channel to be forcibly terminated to 1. <7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. If the two values do not match, repeat operations <6> and <7>. Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. If not, the remaining number of transfers is read. 2. Note that method (b) may take a long time if the application frequently uses DMA transfer for a channel other than the DMA channel to be forcibly terminated. (4) Procedure of temporarily stopping DMA transfer (clearing Enn bit) Stop and resume the DMA transfer under execution using the following procedure. <1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral I/O). <2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0). If a request is pending, wait until execution of the pending DMA transfer request is completed. <3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this operation stops DMA transfer). <4> Set the Enn bit to 1 to resume DMA transfer. <5> Resume the operation of the DMA request source that has been stopped (start the operation of the on-chip peripheral I/O). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1202 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (5) Memory boundary The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the DMA target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (6) Transferring misaligned data DMA transfer of misaligned data with a 16-bit bus width is not supported. If an odd address is specified as the transfer source or destination, the least significant bit of the address is forcibly assumed to be 0. (7) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU. However, the CPU can access the external memory, internal peripheral I/O, and internal RAM for which DMA transfer is not being executed. * The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the external memory and on-chip peripheral I/O. * The CPU can access the internal ROM, and internal peripheral I/O when DMA transfer is being executed between external memories. (8) Registers/bits that must not be rewritten during DMA operation Set the following registers at the following timing when a DMA operation is not under execution. [Registers] * DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers * DTFRn.IFCn5 to DTFRn.IFCn0 bits [Settable timing] * Period from after reset to start of the first DMA transfer * Time after channel initialization to start of DMA transfer * Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer (9) Be sure to set the following register bits to 0. * Bits 14 to 10 of DSAnH register * Bits 14 to 10 of DDAnH register * Bits 15, 13 to 8, and 3 to 0 of DADCn register * Bits 6 to 3 of DCHCn register (10) DMA start factor Do not start two or more DMA channels with the same start factor. If two or more channels are started with the same factor, DMA for which a channel has already been set may be started or a DMA channel with a lower priority may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot be guaranteed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1203 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 21 DMA FUNCTION (DMA CONTROLLER) (11) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately after the DSAnH register is read. (a) If DMA transfer does not occur while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Read value of DSAnL register: DSAnL = FFFFH (b) If DMA transfer occurs while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Occurrence of DMA transfer <3> Incrementing DSAn register: DSAn = 00100000H <4> Read value of DSAnL register: DSAnL = 0000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1204 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/JC3-H and V850ES/JE3-H are provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 86 to 93 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/JC3-H and V850ES/JE3-H can process interrupt request signals from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 22.1 Features Interrupts Table 22-1. Interrupts of V850ES/JC3-H and V850ES/JE3-H Internal External Non-maskable Maskable Total Non-maskable Maskable Total V850ES/JC3-H PD70F3809 1 51 52 - 10 10 (40 pin) PD70F3810 1 51 52 - 10 10 PD70F3811 1 51 52 - 10 10 PD70F3812 1 51 52 - 10 10 PD70F3813 1 51 52 - 10 10 V850ES/JC3-H PD70F3814 1 52 53 - 10 10 (48 pin) PD70F3815 1 52 53 - 10 10 PD70F3816 1 52 53 - 10 10 PD70F3817 1 52 53 - 10 10 PD70F3818 1 52 53 - 10 10 PD70F3819 1 56 57 - 10 10 PD70F3820 1 52 53 1 10 11 PD70F3821 1 52 53 1 10 11 PD70F3822 1 52 53 1 10 11 PD70F3823 1 52 53 1 10 11 PD70F3824 1 52 53 1 10 11 PD70F3825 1 56 57 1 10 11 V850ES/JE3-H * 8 levels of programmable priorities (maskable interrupts) * Multiple interrupt control according to priority * Masks can be specified for each maskable interrupt request. * Noise elimination, edge detection, and valid edge specification for external interrupt request signals. Exceptions * Software exceptions: 32 sources * Exception trap: 2 sources (illegal opcode exception) Interrupt/exception sources of the V850ES/JC3-H and V850ES/JE3-H are listed in Tables 22-2 and 22-3, respectively. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1205 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Sources (1/4) Classification Default Type Name Trigger Generating Exception Handler Unit Code Address Priority Reset Interrupt - RESET pin input/reset RESET Restored Interrupt Control PC Register RESET 0000H 00000000H Undefined - Pin 0010H 00000010H nextPC - WDT2 0020H input by internal source Non- Interrupt - NMI Note 1 NMI pin valid edge maskable input - Software Exception - exception - Exception Exception - trap INTWDT2 WDT2 overflow 00000020H Note 2 - Note 3 00000040H nextPC - Note 3 TRAP instruction - TRAP1n TRAP instruction - 005nH 00000050H nextPC - ILGOP/ Illegal - 0060H 00000060H nextPC - DBG0 opcode/DBTRAP Note 3 TRAP0n Note 3 004nH instruction Maskable Interrupt 0 INTLVI Low voltage detection POCLVI 0080H 00000080H nextPC LVIIC 3 INTP02 External interrupt pin Pin 00B0H 000000B0H nextPC PIC02 Pin 00E0H 000000E0H nextPC PIC05 Pin 0100H 00000100H nextPC PIC07 Pin 0110H 00000110H nextPC PIC08 Pin 0120H 00000120H nextPC PIC09 Pin 0130H 00000130H nextPC PIC10 Pin 0140H 00000140H nextPC PIC11 Pin 0170H 00000170H nextPC PIC14 Pin 0180H 00000180H nextPC PIC15 Pin 0190H 00000190H nextPC PIC16 input edge detection (INTP02) 6 INTP05 External interrupt pin input edge detection (INTP05) 8 INTP07 External interrupt pin input edge detection (INTP07) 9 INTP08 External interrupt pin input edge detection (INTP08) 10 INTP09 External interrupt pin input edge detection (INTP09) 11 INTP10 External interrupt pin input edge detection (INTP10) 12 INTP11 External interrupt pin input edge detection (INTP11) 15 INTP14 External interrupt pin input edge detection (INTP14) 16 INTP15 External interrupt pin input edge detection (INTP15) 17 INTP16 External interrupt pin input edge detection (INTP16) Notes 1. V850ES/JE3-H only 2. For restoring in the case of INTWDT2, see 22.2.2 (2) From INTWDT2 signal. 3. n = 0 to FH Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1206 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Sources (2/4) Type Classification Default Name Trigger Generating Exception Handler Restored Unit Code Address PC Priority Interrupt Control Register Maskable Interrupt 25 26 INTTAB1OVNote 1 INTTAB1CC0 Note 2 TAB1 overflow TAB1 0210H 00000210H nextPC TAB1OVIC TAB1 capture 0/ TAB1 0220H 00000220H nextPC TAB1CCIC0 TAB1 0230H 00000230H nextPC TAB1CCIC1 TAB1 0240H 00000240H nextPC TAB1CCIC2 TAB1 0250H 00000250H nextPC TAB1CCIC3 compare 0 match 27 INTTAB1CC1 TAB1 capture 1/ compare 1 match 28 INTTAB1CC2 TAB1 capture 2/ compare 2 match 29 INTTAB1CC3 TAB1 capture 3/ compare 3 match 30 INTTT0OV TMT0 overflow TMT0 0260H 00000260H nextPC TT0OVIC 31 INTTT0CC0 TMT0 capture 0/ TMT0 0270H 00000270H nextPC TT0CCIC0 TMT0 0280H 00000280H nextPC TT0CCIC1 compare 0 match 32 INTTT0CC1 TMT0 capture 1/ compare 1 match 33 INTTT0EC TMT0 encoder input TMT0 0290H 00000290H nextPC TT0ECIC 34 INTTAA0OV TAA0 overflow TAA0 02A0H 000002A0H nextPC TAA0OVIC 35 INTTAA0CC0 TAA0 capture 0/ TAA0 02B0H 000002B0H nextPC TAA0CCIC0 TAA0 02C0H 000002C0H nextPC TAA0CCIC1 compare 0 match 36 INTTAA0CC1 TAA0 capture 1/ compare 1 match 37 INTTAA1OV TAA1 overflow TAA1 02D0H 000002D0H nextPC TAA1OVIC 38 INTTAA1CC0 TAA1 capture 0/ TAA1 02E0H 000002E0H nextPC TAA1CCIC0 TAA1 02F0H 000002F0H nextPC TAA1CCIC1 compare 0 match 39 INTTAA1CC1 TAA1 capture 1/ compare 1 match 40 INTTAA2OV TAA2 overflow TAA2 0300H 00000300H nextPC TAA2OVIC 41 INTTAA2CC0 TAA2 capture 0/ TAA2 0310H 00000310H nextPC TAA2CCIC0 TAA2 0320H 00000320H nextPC TAA2CCIC1 compare 0 match 42 INTTAA2CC1 TAA2 capture 1/ compare 1 match 52 INTTM0EQ0 TMM0 compare match TMM0 03C0H 000003C0H nextPC TM0EQIC0 53 INTTM1EQ0 TMM1 compare match TMM1 03D0H 000003D0H nextPC TM1EQIC0 54 INTTM2EQ0 TMM2 compare match TMM2 03E0H 000003E0H nextPC TM2EQIC0 55 INTTM3EQ0 TMM3 compare match TMM3 03F0H 000003F0H nextPC TM3EQIC0 56 INTCF0R CSIF0 reception completion/ CSIF0/ 0400H 00000400H nextPC CF0RIC/ /INTIIC1 CSIF0 reception error/ IIC1 IICIC1 IIC1 transfer completion 57 INTCF0T CSIF0 consecutive CSIF0 0410H 00000410H nextPC CF0TIC transmission write enable Notes 1. When using TAB1 in the 6-phase PWM output mode, functions as the zero match interrupt (TAB1TIOD) request from TMQOP. 2. When using TAB1 in the 6-phase PWM output mode, functions as the compare match interrupt (TAB1TICD0) request from TMQOP. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1207 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Sources (3/4) Classification Default Type Name Trigger Generating Exception Unit Priority Code Handler Restored Address PC Interrupt Control Register Maskable Interrupt 58 INTCF1R CSIF1 reception completion/ CSIF1 0420H 00000420H nextPC CF1RIC CSIF1 0430H 00000430H nextPC CF1TIC CSIF2 0440H 00000440H nextPC CF2RIC CSIF2 0450H 00000450H nextPC CF2TIC CSIF3 0460H 00000460H nextPC CF3RIC CSIF3 0470H 00000470H nextPC CF3TIC CSIF4 0480H 00000480H nextPC CF4RIC CSIF4 0490H 00000490H nextPC CF4TIC UARTC0 04A0H 000004A0H nextPC UC0RIC UARTC0 04B0H 000004B0H nextPC UC0TIC UARTC2 04E0H 000004E0H nextPC UC2RIC UARTC2 04F0H 000004F0H nextPC UC2TIC 0500H 00000500H nextPC UC3RIC/ CSIF1 reception error 59 INTCF1T CSIF1 consecutive transmission write enable 60 INTCF2R CSIF2 reception completion/ CSIF2 reception error 61 INTCF2T CSIF2 consecutive transmission write enable 62 INTCF3R CSIF3 reception completion/ CSIF3 reception error 63 INTCF3T CSIF3 consecutive transmission write enable 64 INTCF4R CSIF4 reception completion/ CSIF4 reception error 65 INTCF4T CSIF4 consecutive transmission write enable 66 INTUC0R UARTC0 reception completion/UARTC0 reception error 67 INTUC0T UARTC0 consecutive transmission enable 70 INTUC2R UARTC2 reception completion/UARTC2 reception error 71 INTUC2T UARTC2 consecutive transmission enable 72 73 INTUC3R Note UARTC3 reception UARTC3/ / completion/UARTC0 reception IIC0 INTIIC0 error/IIC0 transfer completion INTUC3T Note UARTC3 consecutive transmission IICIC0 UARTC3 0510H 00000510H nextPC UC3TIC UARTC4 0520H 00000520H nextPC UC4RIC UARTC4 0530H 00000530H nextPC UC4TIC enable 74 INTUC4R UARTC4 reception completion/UARTC4 reception error 75 INTUC4T UARTC4 consecutive transmission enable Note 76 INTAD A/D conversion completion A/D 0540H 00000540H nextPC ADIC 77 INTDMA0 DMA0 transfer completion DMA 0550H 00000550H nextPC DMAIC0 78 INTDMA1 DMA1 transfer completion DMA 0560H 00000560H nextPC DMAIC1 79 INTDMA2 DMA2 transfer completion DMA 0570H 00000570H nextPC DMAIC2 80 INTDMA3 DMA3 transfer completion DMA 0580H 00000580H nextPC DMAIC3 81 INTKR Key return interrupt KR 0590H 00000590H nextPC KRIC 82 INTRTC0 RTC constant cycle signal RTC 05A0H 000005A0H nextPC RTC0IC 83 INTRTC1 RTC alarm match RTC 05B0H 000005B0H nextPC RTC1IC 84 INTRTC2 RTC interval signal RTC 05C0H 000005C0H nextPC RTC2IC V850ES/JC3-H (48 pin), V850ES/JE3-H only. Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1208 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Sources (4/4) Type Classification Default Name Trigger Priority Generating Exception Handler Restored Unit Code Address PC Interrupt Control Register Maskable Interrupt 85 86 87 INTC0ERRNote1 Note INTC0WUP1 CAN0 error CAN0 05D0H 000005D0H nextPC ERRIC0 CAN0 wake up CAN0 05E0H 000005E0H nextPC WUPIC0 Note CAN0 reception CAN0 05F0H 000005F0H nextPC RECIC0 Note INTC0REC 88 INTC0TRX CAN0 transmission CAN0 0600H 00000600H nextPC TRXIC0 92 INTUSBF0 USBF interrupt USBF 0640H 00000640H nextPC UFIC0 93 INTUSBF1 USBF resume interrupt USBF 0650H 00000650H nextPC UFIC1 Note PD70F3819, 70F3825 only Remarks 1. JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H 2. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started. Note, however, that the restored PC when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Division instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack pointer is updated) nextPC: The PC value that starts the processing following interrupt/exception processing. 3. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1209 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. This product has the following two non-maskable interrupt request signals. * NMI pin input (NMI) * Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2) The valid edge of the NMI pin can be selected from four types: "rising edge", "falling edge", "both edges", and "no edge detection". The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when the WDTM2.WDM21 and WDTM2.WDM20 bits are set to "01". If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). INTWDT2 > NMI If a new NMI or INTWDT2 request signal is issued while an NMI is being serviced, it is serviced as follows. (1) If new NMI request signal is issued while NMI is being serviced The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). (2) If INTWDT2 request signal is issued while NMI is being serviced The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is executed (the NMI servicing is stopped). Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request signal (INTWDT2), see 22.2.2 (2) From INTWDT2 signal. Figure 22-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2) (a) NMI and INTWDT2 request signals generated at the same time Main routine INTWDT2 servicing NMI and INTWDT2 requests (generated simultaneously) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 System reset Page 1210 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable interrupt being serviced NMI Non-maskable interrupt request signal generated during non-maskable interrupt servicing NMI INTWDT2 * NMI request generated during NMI servicing * INTWDT2 request generated during NMI servicing (NP bit = 1 retained before INTWDT2 request) Main routine NMI servicing Main routine NMI servicing NMI request NMI (Held pending) request Servicing of pending NMI INTWDT2 request NMI request (Held pending) INTWDT2 servicing System reset * INTWDT2 request generated during NMI servicing (NP bit = 0 set before INTWDT2 request) Main routine NMI servicing INTWDT2 servicing NP = 0 NMI request INTWDT2 request System reset * INTWDT2 request generated during NMI servicing (NP = 0 set after INTWDT2 request) Main routine NMI request INTWDT2 request NP = 0 NMI INTWDT2 servicing servicing (Held pending) System reset INTWDT2 * NMI request generated during INTWDT2 servicing Main routine * INTWDT2 request generated during INTWDT2 servicing Main routine INTWDT2 servicing INTWDT2 request NMI request (Invalid) System reset R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 INTWDT2 servicing INTWDT2 request INTWDT2 request (Invalid) System reset Page 1211 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0. <5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC, and transfers control. The servicing configuration of a non-maskable interrupt is shown below. Figure 22-2. Servicing Configuration of Non-Maskable Interrupt NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW.NP 1 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restored PC PSW 0010H, 0020H 1 0 1 00000010H, 00000020H Interrupt request held pending Interrupt servicing R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1212 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 1. <2> Transfers control back to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 22-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1213 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 22-4. Software Reset Processing INTWDT2 occurs. FEPC Software reset processing address FEPSW Value that sets NP bit = 1, EP bit = 0 INTWDT2 servicing routine RETI RETI 10 times (FEPC and FEPSWNote must be set.) Software reset processing routine PSW PSW default value setting Initialization processing Note FEPSW Value that sets NP bit = 1, EP bit = 0 22.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. After reset: 00000020H PSW 0 NP ID SAT CY OV S Z NMI interrupt servicing status NP 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 EP Page 1214 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JC3-H and V850ES/JE3H have 61 to 71 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and EIPSW. 22.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0. <5> Sets the handler address corresponding to each interrupt to the PC, and transfers control. The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the NP and ID bits are set to 0 by using the RETI or LDSR instruction. How maskable interrupts are serviced is illustrated below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1215 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-5. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 No Interrupt requested? Yes xxMK = 0 Yes Priority higher than that of interrupt currently being serviced? No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request Interrupt request held pending CPU processing PSW.NP 1 0 PSW.ID 1 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Interrupt request held pending Handler address Interrupt servicing Note For the ISPR register, see 22.3.6 In-service priority register (ISPR). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1216 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is 0. <2> Transfers control back to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 22-6. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW Restores original processing Note For the ISPR register, see 22.3.6 In-service priority register (ISPR). Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1217 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, see Table 22-2 and Table 22-3. The programmable priority control customizes interrupt request signals into eight levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (see Table 22-4 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-4 Interrupt Control Register (xxICn)). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1218 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Servicing of b EI Interrupt request b (level 2) Interrupt request a (level 3) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of d Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Servicing of h Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1219 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Interrupt request i (level 2) Servicing of k EI Interrupt request j (level 3) Interrupt request k (level 1) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request l (level 2) Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request s (level 1) Interrupt request t (level 2) Interrupt request u (level 2) Note 1 Note 2 Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u Servicing of t Caution Notes 1. Lower default priority 2. Higher default priority To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1220 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Default priority a>b>c Servicing of interrupt request b Servicing of interrupt request c . . Interrupt request b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Servicing of interrupt request a Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1221 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H. Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read while interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. After reset: 47H xxICn R/W <7> <6> xxIFn xxMKn Address: FFFFF112H to FFFFF184H 0 0 0 xxPRn2 xxPRn1 xxPRn0 Interrupt request flagNote xxIFn 0 Interrupt request not issued 1 Interrupt request issued xxMKn Interrupt mask flag 0 Interrupt servicing enabled 1 Interrupt servicing disabled (pending) xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 (highest). 0 0 1 Specifies level 1. 0 1 0 Specifies level 2. 0 1 1 Specifies level 3. 1 0 0 Specifies level 4. 1 0 1 Specifies level 5. 1 1 0 Specifies level 6. 1 1 1 Specifies level 7 (lowest). Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged. Remark xx: Identification name of each peripheral unit (see Table 22-4 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-4 Interrupt Control Register (xxICn)). The addresses and bits of the interrupt control registers are as follows. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1222 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-3. Interrupt Control Register (xxICn) (1/2) Address Register Bit <7> <6> 5 4 3 2 1 0 FFFFF110H LVIIC LVIIF LVIMK 0 0 0 LVIPR2 LVIPR1 LVIPR0 FFFFF116H PIC02 PIF02 PMK02 0 0 0 PPR022 PPR021 PPR020 FFFFF11CH PIC05 PIF05 PMK05 0 0 0 PPR052 PPR051 PPR050 FFFFF120H PIC07 PIF07 PMK07 0 0 0 PPR072 PPR071 PPR070 FFFFF122H PIC08 PIF08 PMK08 0 0 0 PPR082 PPR081 PPR080 FFFFF124H PIC09 PIF09 PMK09 0 0 0 PPR092 PPR091 PPR090 FFFFF126H PIC10 PIF10 PMK10 0 0 0 PPR102 PPR101 PPR100 FFFFF128H PIC11 PIF11 PMK11 0 0 0 PPR112 PPR111 PPR110 FFFFF12EH PIC14 PIF14 PMK14 0 0 0 PPR142 PPR141 PPR140 FFFFF130H PIC15 PIF15 PMK15 0 0 0 PPR152 PPR151 PPR150 FFFFF132H PIC16 PIF16 PMK16 0 0 0 PPR162 PPR161 PPR160 FFFFF142H TAB1OVIC Note TAB1OVIF TAB1OVMK 0 0 0 TAB1OVPPR2 TAB1OVPPR1 TAB1OVPPR0 FFFFF144H TAB1CCIC0 Note TAB1CCIF0 TAB1CCMK0 0 0 0 TAB1CCPPR02 TAB1CCPPR01 TAB1CCPPR00 FFFFF146H TAB1CCIC1 Note TAB1CCIF1 TAB1CCMK1 0 0 0 TAB1CCPPR12 TAB1CCPPR11 TAB1CCPPR10 FFFFF148H TAB1CCIC2 Note TAB1CCIF2 TAB1CCMK2 0 0 0 TAB1CCPPR22 TAB1CCPPR21 TAB1CCPPR20 FFFFF14AH TAB1CCIC3 Note TAB1CCIF3 TAB1CCMK3 0 0 0 TAB1CCPPR32 TAB1CCPPR31 TAB1CCPPR30 TT0OVIF TT0OVMK 0 0 0 TT0OVPPR2 TT0OVPPR1 TT0OVPPR0 FFFFF14CH TT0OVIC Note FFFFF14EH TT0CCIC0 TT0CCIF0 TT0CCMK0 0 0 0 TT0CCPPR02 TT0CCPPR01 TT0CCPPR00 FFFFF150H TT0CCIC1 TT0CCIF1 TT0CCMK1 0 0 0 TT0CCPPR12 TT0CCPPR11 TT0CCPPR10 FFFFF152H TT0IECIC TT0IECIF TT0IECMK 0 0 0 TT0IECPPR2 TT0IECPPR1 TT0IECPPR0 FFFFF154H TAA0OVIC TAA0OVIF TAA0OVMK 0 0 0 TAA0OVPPR2 TAA0OVPPR1 TAA0OVPPR0 FFFFF156H TAA0CCIC0 TAA0CCIF0 TAA0CCMK0 0 0 0 TAA0CCPPR02 TAA0CCPPR01 TAA0CCPPR00 FFFFF158H TAA0CCIC1 TAA0CCIF1 TAA0CCMK1 0 0 0 TAA0CCPPR12 TAA0CCPPR11 TAA0CCPPR10 FFFFF15AH TAA1OVIC TAA1OVIF TAA1OVMK 0 0 0 TAA1OVPPR2 TAA1OVPPR1 TAA1OVPPR0 FFFFF15CH TAA1CCIC0 TAA1CCIF0 TAA1CCMK0 0 0 0 TAA1CCPPR02 TAA1CCPPR01 TAA1CCPPR00 FFFFF15EH TAA1CCIC1 TAA1CCIF1 TAA1CCMK1 0 0 0 TAA1CCPPR12 TAA1CCPPR11 TAA1CCPPR10 FFFFF160H TAA2OVIC TAA2OVIF TAA2OVMK 0 0 0 TAA2OVPPR2 TAA2OVPPR1 TAA2OVPPR0 FFFFF162H TAA2CCIC0 TAA2CCIF0 TAA2CCMK0 0 0 0 TAA2CCPPR02 TAA2CCPPR01 TAA2CCPPR00 FFFFF164H TAA2CCIC1 TAA2CCIF1 TAA2CCMK1 0 0 0 TAA2CCPPR12 TAA2CCPPR11 TAA2CCPPR10 FFFFF178H TM0EQIC0 TM0EQIF0 TM0EQMK0 0 0 0 TM0EQPR02 TM0EQPR01 TM0EQPR00 FFFFF17AH TM1EQIC0 TM1EQIF0 TM1EQMK0 0 0 0 TM1EQPR02 TM1EQPR01 TM1EQPR00 FFFFF17CH TM2EQIC0 TM2EQIF0 TM2EQMK0 0 0 0 TM2EQPR02 TM2EQPR01 TM2EQPR00 FFFFF17EH TM3EQIC0 TM3EQIF0 TM3EQMK0 0 0 0 TM3EQPR02 TM3EQPR01 TM3EQPR00 FFFFF180H CF0RIC/ CF0RIF/ CF0RMK/ 0 0 0 CF0RPPR2/ CF0RPPR1/ CF0RPPR0/ IICIC1 IICIF1 IICMK1 IICPPR12 IICPPR11 IICPPR10 CF0TIC CF0TIF CF0TMK 0 0 0 CF0TPPR2 CF0TPPR1 CF0TPPR0 FFFFF182H FFFFF188H CF2RIC CF2RIF CF2RMK 0 0 0 CF2RPPR2 CF2RPPR1 CF2RPPR0 FFFFF18AH CF2TIC CF2TIF CF2TMK 0 0 0 CF2TPPR2 CF2TPPR1 CF2TPPR0 FFFFF18CH CF3RIC CF3RIF CF3RMK 0 0 0 CF3RPPR2 CF3RPPR1 CF3RPPR0 FFFFF18EH CF3TIC CF3TIF CF3TMK 0 0 0 CF3TPPR2 CF3TPPR1 CF3TPPR0 FFFFF190H CF4RIC CF4RIF CF4RMK 0 0 0 CF4RPPR2 CF4RPPR1 CF4RPPR0 FFFFF192H CF4TIC CF4TIF CF4TMK 0 0 0 CF4TPPR2 CF4TPPR1 CF4TPPR0 Note V850ES/JE3-H only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1223 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-3. Interrupt Control Register (xxICn) (2/2) Address Register Bit <7> <6> 5 4 3 2 1 0 FFFFF194H UC0RIC UC0RIF UC0RMK 0 0 0 UC0RPPR2 UC0RPPR1 UC0RPPR0 FFFFF196H UC0TIC UC0TIF UC0TMK 0 0 0 UC0TPPR2 UC0TPPR1 UC0TPPR0 FFFFF19CH UC2RIC UC2RIF UC2RMK 0 0 0 UC2RPPR2 UC2RPPR1 UC2RPPR0 FFFFF19EH UC2TIC UC2TIF UC2TMK 0 0 0 UC2TPPR2 UC2TPPR1 UC2TPPR0 UC3RIF/ UC3RMK/ 0 0 0 UC3RPPR2/ UC3RPPR1/ UC3RPPR0/ IICIF0 IICMK0 IICPPR02 IICPPR01 IICPPR00 UC3TIF UC3TMK 0 0 0 UC3TPPR2 UC3TPPR1 UC3TPPR0 Note1 / UC3RIC FFFFF1A0H IICIC0 Note1 FFFFF1A2H UC3TIC FFFFF1A4H UC4RIC UC4RIF UC4RMK 0 0 0 UC4RPPR2 UC4RPPR1 UC4RPPR0 FFFFF1A6H UC4TIC UC4TIF UC4TMK 0 0 0 UC4TPPR2 UC4TPPR1 UC4TPPR0 FFFFF1A8H ADIC ADIF ADMK 0 0 0 ADPPR2 ADPPR1 ADPPR0 FFFFF1AAH DMAIC0 DMAIC0 DMAMK0 0 0 0 DMAPPR02 DMAPPR01 DMAPPR00 FFFFF1ACH DMAIC1 DMAIC1 DMAMK1 0 0 0 DMAPPR12 DMAPPR11 DMAPPR10 FFFFF1AEH DMAIC2 DMAIC2 DMAMK2 0 0 0 DMAPPR22 DMAPPR21 DMAPPR20 FFFFF1B0H DMAIC3 DMAIC3 DMAMK3 0 0 0 DMAPPR32 DMAPPR31 DMAPPR30 FFFFF1B2H KRIC KRIF KRMK 0 0 0 KRPPR2 KRPPR1 KRPPR0 FFFFF1B4H RTC0IC RTC0IF RTC0MK 0 0 0 RTC0PPR2 RTC0PPR1 RTC0PPR0 FFFFF1B6H RTC1IC RTC1IF RTC1MK 0 0 0 RTC1PPR2 RTC1PPR1 RTC1PPR0 FFFFF1B8H RTC2IC RTC2IF RTC2MK 0 0 0 RTC2PPR2 RTC2PPR1 RTC2PPR0 ERRIF0 ERRMK0/ 0 0 0 ERRPPR02 ERRPPR01 ERRPPR00 FFFFF1BAH FFFFF1BCH FFFFF1BEH FFFFF1C0H ERRIC0 Note2 Note2 WUPIC0 WUPIF0 WUPMK0 0 0 0 WUPPPR02 WUPPPR01 WUPPPR00 Note2 RECIF0 RECMK0 0 0 0 RECPPR02 RECPPR01 RECPPR00 Note TRXIF0 TRXMK0/ 0 0 0 TRXPPR02/ TRXPPR01/ TRXPPR00/ IEPPR22 IEPPR21 IEPPR20 RECIC0 TRXIC0 IEMK2 FFFFF1C8H UFIC0 UFIC0 UFMK0 0 0 0 UFPPR02 UFPPR01 UFPPR00 FFFFF1CAH UFIC1 UFIC1 UFMK1 0 0 0 UFPPR12 UFPPR11 UFPPR10 Notes1. Except the V850ES/JC3-H (40 pin) 2. PD70F3819, 70F3825 Remark JC3-H: V850ES/JC3-H, JE3-H: V850ES/JE3-H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1224 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) The IMR0 to IMR5 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR5 registers is equivalent to the xxICn.xxMKn bit. The IMRm register can be read or written in 16-bit units. If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 5). Reset sets these registers to FFFFH. Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a result, the contents of the IMRm register are also rewritten). (1/2) After reset: FFFFH IMR5 (IMR5H Note 1 ) R/W Address: IMR5 FFFFF10AH, IMR5L FFFFF10AH, IMR5H FFFFF10BH 15 14 13 12 11 10 9 8 1 1 UFMK1 UFMK0 1 1 1 TRXMK0Note 2 7 6 5 4 3 2 RECMK0Note 2 WUPMK0Note 2 ERRMK0Note 2 RTC2MK RTC1MK RTC0MK IMR5L After reset: FFFFH 15 R/W 14 13 12 ADMK 7 5 4 1 1 UC2TMK UC2RMK IMR4L After reset: FFFFH 15 Note 1 IMR3 (IMR3H R/W 14 7 6 11 10 9 8 UC4TMK UC4RMK UC3TMK UC3RMK/ IICMK0 3 2 1 0 UC0TMK UC0RMK CF3TMK CF3RMK Address: IMR3 FFFFF106H, IMR3L FFFFF106H, IMR3H FFFFF107H 13 12 ) CF3TMK CF3RMK CF2TMK CF2RMK IMR3L 0 DMAMK3 Address: IMR4 FFFFF108H, IMR4L FFFFF108H, IMR4H FFFFF109H IMR4 (IMR4HNote 1) DMAMK2 DMAMK1 DMAMK0 6 1 KRMK 5 4 TM3EQMK0 TM2EQMK0 TM1EQMK0 TM0EQMK0 11 10 9 8 CF0RMK/ CF0TMK IICMK1 1 1 3 2 1 0 1 1 1 TAA4CCMK1 Notes 1. To read bits 8 to 15 of the IMR3 to IMR5 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of IMR3H to IMR5H registers. 2. PD70F3819, 70F3815 only Caution Set bits 9 to 11, 14, 15 of the IMR5 register to 1. If the setting of these bits is changed, the operation is not guaranteed. Remark xx: Identification name of each peripheral unit (see Table 22-4 Interrupt Control Register (xxICn)). n: Peripheral unit number (see Table 22-4 Interrupt Control Register (xxICn)) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1225 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) After reset: FFFFH 15 R/W 14 IMR2 (IMR2HNote) TAA4CCMK0 TAA4OVMK 7 6 After reset: FFFFH 15 IMR1 (IMR1H 13 12 11 1 1 1 5 4 3 10 9 8 TAA2CCMK1 TAA2CCMK0 TAA2OVMK 2 1 0 TAA1CCMK1 TAA1CCMK0 TAA1OVMK TAA0CCMK1 TAA0CCMK0 TAA0OVMK TMTIECMK TMT0CCMK1 IMR2L Note Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H R/W 14 Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H 13 12 11 10 9 8 ) TT0CCMK0 TT0OVMK TAB1CCMK3 TAB1CCMK2 TAB1CCMK1 TAB1CCMK0 TAB1OVMK IMR1L 7 6 5 4 3 2 1 0 1 1 1 1 1 1 PMK16 PMK15 After reset: FFFFH IMR0 (IMR0HNote) IMR0L 1 R/W Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H 15 14 13 12 11 10 9 8 PMK14 1 1 PMK11 PMK10 PMK09 PMK08 PMK07 7 6 5 4 3 2 1 0 1 PMK05 1 1 PMK02 1 1 LVIMK xxMKn Setting of interrupt mask flag 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note To read bits 8 to 15 of the IMR0 to IMR2 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of IMR0H to IMR2H registers. Remark xx: Identification name of each peripheral unit (see Table 22-4 Interrupt Control Register (xxICn)). n: Peripheral unit number (see Table 22-4 Interrupt Control Register (xxICn)) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1226 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI). After reset: 00H ISPR R Address: FFFFF1FAH <7> <6> <5> <4> <3> <2> <1> <0> ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 ISPRn Remark Priority of interrupt currently acknowledged 0 Interrupt request signal with priority n not acknowledged 1 Interrupt request signal with priority n acknowledged n = 0 to 7 (priority level) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1227 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.7 ID flag This flag controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z Specification of maskable interrupt servicingNote ID 0 Maskable interrupt request signal acknowledgment enabled 1 Maskable interrupt request signal acknowledgment disabled Note Interrupt disable flag (ID) function This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0. 22.3.8 Watchdog timer mode register 2 (WDTM2) This register can be read or written in 8-bit units (for details, see CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2). Reset sets this register to 67H. After reset: 67H WDTM2 R/W Address: FFFFF6D0H 0 WDM21 WDM21 WDM20 0 0 Stops operation 0 1 Non-maskable interrupt request mode 1 x Reset mode (initial value) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 WDM20 0 0 0 0 0 Selection of watchdog timer operation mode Page 1228 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 22.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.EP and PSW.ID bits to 1. <5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and transfers control. The processing of a software exception is shown below. Figure 22-9. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address Exception processing Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1229 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.2 Restore Restoration from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 22-10. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 1 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1230 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 EP NP ID SAT CY OV S Z Exception processing status 0 Exception processing not in progress. 1 Exception processing in progress. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 EP Page 1231 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JC3-H and V850ES/JE3-H, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 22.5.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is generated. 15 11 10 5 4 0 31 27 26 23 22 16 0 1 1 1 to x x x x x 1 1 1 1 1 1 x x x x x x x x x x x x x x x x 0 1 1 1 1 x: Arbitrary Caution It is recommended not to use an illegal opcode because instructions may newly be assigned in the future. (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. The processing of the exception trap is shown below. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1232 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing (2) Restoration Restoration from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Caution DBPC and DBPSW can be accessed only during the interval between the execution of an illegal opcode and DBRET instruction. Processing for restoring from an exception trap is shown below. Figure 22-12. Processing for Restoring from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1233 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1> Saves restored PC to DBPC. <2> Saves current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets handler address (00000060H) for debug trap to PC and transfers control. The debug trap processing format is shown below. Figure 22-13. Debug Trap Processing Format DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1234 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2> Control is transferred to the fetched address of the restored PC and PSW. Caution DBPC and DBPSW can be accessed only during the interval between the execution of the DBTRAP instruction and DBRET instruction. The processing format for restoration from a debug trap is shown below. Figure 22-14. Processing Format of Restoration from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1235 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.6 External Interrupt Request Input Pins (NMI and INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP18) 22.6.1 Noise elimination (1) Eliminating noise on NMI pin (V850ES/JE3-H only) The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. The NMI pin can be used to release the STOP mode. In the STOP mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) Eliminating noise on INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP18 pins The INTP00, INTP01, and INTP03 to INTP18 pins have an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. (3) Eliminating noise on INTP02 The INTP02 pin has an internal noise elimination circuit that uses analog delay and an internal digital noise elimination circuit. Either can be selected by using the noise elimination control register (INTNFC) (see 22.6.2 (7)). 22.6.2 Edge detection The valid edge of each of the NMI and INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP18 pins can be selected from the following four. * Rising edge * Falling edge * Both rising and falling edges * No edge detected The edge of the NMI pin is not detected after reset. Therefore, the interrupt request signal is not acknowledged unless a valid edge is enabled by using the INTF0 and INTR0 register (the NMI pin functions as a normal port pin). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1236 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pin (INTP02) via bits 0, 1, 3 to 5. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, set the INTF0n and INTR0n bits to 00, and then set the port mode. After reset: 00H INTF0 INTR0 R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H 7 6 5 4 0 0 0 0 7 6 5 4 0 0 0 0 3 2 INTF03 INTF02Note INTP02 NMI 3 2 INTR03 INTR02Note INTP02 1 0 0 0 1 0 0 0 NMI Note V850ES/JE3-H only Remark For how to specify a valid edge, see Table 22-5. Table 22-4. Valid Edge Specification Caution INTF0n INTR0n Valid Edge Specification (n = 2, 3) 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Be sure to set the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI or INTP02 pins. Remark n = 2: Control of NMI pin n = 3: Control of INTP02 pin R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1237 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP07 to INTP09). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, set the INTF3n and INTR3n bits to 00, and then set the port mode. After reset: 00H INTF3 R/W Address: INTF3 FFFFFC06H, INTR3 FFFFFC26H 7 6 5 4 3 2 1 0 0 0 0 INTF34 0 0 INTF31 INTF30 INTP08 INTP07 INTP09 INTR3 7 6 5 4 3 2 1 0 0 0 0 INTR34 0 0 INTR31 INTR30 INTP08 INTP07 INTP09 Remark For how to specify a valid edge, see Table 22-7. Table 22-5. Valid Edge Specification INTF3n INTR3n 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Caution Valid Edge Specification Be sure to set the INTF3n and INTR3n bits to 00 when these registers are not used as the INTP07 to INTP09 pin. Remark n = 0, 1, 4: Control of INTP07 to INTP09 pins R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1238 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification registers 4 (INTF4, INTR4) The INTF4 and INTR4 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP10). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, set the INTF42 and INTR42 bits to 00, and then set the port mode. After reset: 00H INTF4 R/W Address: INTF4 FFFFFC08H, INTR4 FFFFFC28H 7 6 5 4 3 2 1 0 0 0 0 0 0 INTF42 0 0 INTP10 INTR4 7 6 5 4 3 2 1 0 0 0 0 0 0 INTR42 0 0 INTP10 Remark For the valid edge specification combinations, see Table 22-8. Table 22-6. Valid Edge Specification Caution INTF42 INTR42 Valid Edge Specification 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Be sure to set the INTF42 and INTR42 bits to 00 if the corresponding pin is not used as the INTP10 pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1239 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) External interrupt falling, rising edge specification registers 5 (INTF5, INTR5) The INTF5 and INTR5 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP05). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, set the INTF56 and INTR56 bits to 00, and then set the port mode. After reset: 00H INTF5 R/W Address: INTF5 FFFFFC0AH, INTR5 FFFFFC2AH 7 6 5 4 3 2 1 0 0 INTF56 0 0 0 0 0 0 INTP05 INTR5 7 6 5 4 3 2 1 0 0 INTR56 0 0 0 0 0 0 INTP05 Remark For the valid edge specification combinations, see Table 22-9. Table 22-7. Valid Edge Specification Caution INTF56 INTR56 Valid Edge Specification 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Be sure to set the INTF56 and INTR56 bits to 00 if the corresponding pin is not used as the INTP05 pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1240 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (5) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 16-bit or 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP11, INTP14 to INTP16). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 0000H/00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0, and then set the port mode. After reset: 0000H INTF9 (INTF9HNote) R/W Address: INTF9 FFFFFC12H, INTF9H FFFFFC12H, INTF9L FFFFFC13H 15 14 13 12 0 0 INTF913 0 INTP16 (INTF9L) INTP15 INTP14 9 8 0 0 7 6 5 4 3 2 1 0 INTF96 0 0 0 0 0 0 INTP11 R/W Address: INTR9 FFFFFC32H, INTR9H FFFFFC32H, INTR9L FFFFFC33H 15 14 13 12 0 0 INTF913 0 INTP16 (INTR9L) 10 0 After reset: 0000H INTR9 (INTR9HNote) 11 INTF911 INTF910 11 10 INTR911 INTR910 INTP15 INTP14 9 8 0 0 7 6 5 4 3 2 1 0 0 INTR96 0 0 0 0 0 0 INTP11 Note To read bits 8 to 15 of the INTF9 and INTR9 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of the INTF9H and INTR9H registers. Remark For how to specify a valid edge, see Table 22-10. Table 22-8. Valid Edge Specification INTF9n INTR9n 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Caution Valid Edge Specification (n = 11,14 to 16) Be sure to clear the INTF9n and INTR9n bits to 00 when these registers are not used as the INTP11, INTP14 to INTP16 pins. Remark n = 6, 10, 11, 13: Control of INTP11, INTP14 to INTP16 pins R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1241 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (6) Noise elimination control register (INTNFC) Analog noise elimination and digital noise elimination can be selected for the INTP02 pin. The noise elimination settings are performed using the INTNFC register. When analog noise elimination is selected, the input level of the pin is detected as an edge by maintaining it for a specific time or longer. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed 3 times. Even when digital noise elimination is selected, using fXT as the sampling clock makes it possible to use the INTP02 interrupt request signal to release the IDLE1, IDLE2, and STOP modes. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. Therefore, if an INTP02 valid edge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. Therefore, be careful about the following points when using the interrupt and DMA functions. * When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (PIC2.PIF2 bit) has been cleared. * When using the DMA function (started by INTP02), enable DMA after 3 sampling clocks have elapsed. After reset: 00H INTNFC INTNFEN R/W Address: FFFFF728H 0 0 INTNFEN 0 0 INTNFC2 INTNFC1 INTNFC0 Settings of INTP02 pin noise elimination 0 Analog noise elimination (60 ns (TYP.)) 1 Digital noise elimination INTNFC2 INTNFC1 INTNFC0 Digital sampling clock 0 0 0 fXX/64 0 0 1 fXX/128 0 1 0 fXX/256 0 1 1 fXX/512 1 0 0 fXX/1,024 1 0 1 fXT (subclock) Other than above Setting prohibited Remarks 1. Since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1242 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. * In IDLE1/IDLE2/STOP mode * When the external bus is accessed * When interrupt request non-sampling instructions are successively executed (see 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU.) * When the interrupt control register is accessed Figure 22-15. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline) (1) Minimum interrupt response time 4 system clocks Internal clock Interrupt request Instruction 1 IF Instruction 2 ID EX MEM WB IFX IDX INT1 INT2 INT3 INT4 Interrupt acknowledgment operation IF Instruction (first instruction of interrupt servicing routine) ID EX (2) Maximum interrupt response time 6 system clocks Internal clock Interrupt request Instruction 1 IF Instruction 2 ID EX MEM MEM MEM WB IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 Interrupt acknowledgment operation IF Instruction (first instruction of interrupt servicing routine) Remark ID EX INT1 to INT4: Interrupt acknowledgment processing IFX: Invalid instruction fetch IDX: Invalid instruction decode Condition Interrupt acknowledge time (internal system clock) Internal interrupt Minimum 4 External interrupt 4+ Analog delay time Maximum 6 6+ Analog delay time The following cases are exceptions. * In IDLE1/IDLE2/STOP mode * External bus access * Two or more interrupt request non-sample instructions are executed in succession * Access to peripheral I/O register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1243 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the PRCMD register * The store, SET1, NOT1, or CLR1 instructions for the following registers. * Interrupt-related registers: Interrupt control register (xxICn), interrupt mask registers 0 to 5 (IMR0 to IMR5) * Power save control register (PSC) * On-chip debug mode register (OCDM) Remark xx: Identification name of each peripheral unit (see Table 22-4 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-4 Interrupt Control Register (xxICn)). 22.9 Cautions The NMI pin alternately functions as the P02 pin, and functions as a normal port pin after being reset. To enable the NMI pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using the INTF0 and INTR0 registers. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1244 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 23 KEY INTERRUPT FUNCTION CHAPTER 23 KEY INTERRUPT FUNCTION 23.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the six key input pins (KR2 to KR5) by setting the KRM register. Table 23-1. Assignment of Key Return Detection Pins Flag Pin Description KRM2 Controls KR2 signal in 1-bit units KRM3 Controls KR3 signal in 1-bit units KRM4 Controls KR4 signal in 1-bit units KRM5 Controls KR5 signal in 1-bit units Figure 23-1. Key Return Block Diagram KR5 INTKR KR4 KR3 KR2 KRM5 KRM4 KRM3 KRM2 Key return mode register (KRM) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1245 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 23 KEY INTERRUPT FUNCTION 23.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM2 to KRM5 bits using the KR2 to KR5 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H KRM 0 R/W 0 Address: FFFFF300H KRM5 KRMn Caution Remark KRM4 KRM3 KRM2 0 0 Control of key return mode 0 Does not detect key return signal 1 Detects key return signal Rewrite the KRM register after once setting the KRM register to 00H. For the alternate-function pin settings, see Table 4-17 Settings When Port Pins Are Used for Alternate Functions. 23.3 Cautions (1) If a low level is input to any of the KR2 to KR5 pins, the INTKR signal is not generated even if the falling edge of another pin is input. (2) If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this, change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag (KRIC.KRIF bit) to 0, and enable interrupts (EI) or clear the mask. (3) To use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the KRM register. To switch from the key return pin to the port pin, disable the operation with the KRM register and then set the port pin. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1246 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION CHAPTER 24 STANDBY FUNCTION 24.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 24-1. Table 24-1. Standby Modes Mode Functional Outline HALT mode Mode in which only the operating clock of the CPU is stopped IDLE1 mode Mode in which all the operations of the internal circuits except the oscillator, PLL Note , and flash memory are stopped IDLE2 mode Mode in which all the operations of internal circuits except the oscillator are stopped STOP mode Mode in which all the operations of internal circuits except the subclock oscillator are stopped Subclock operation mode Mode in which the subclock is used as the internal system clock Sub-IDLE mode Mode in which all the operations of internal circuits except the oscillator are stopped, in the subclock operation mode Note The PLL holds the previous operating status. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1247 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Figure 24-1. Status Transition Reset Internal oscillation clock operation Sub-IDLE mode (fx operates, PLL operates) WDT overflow Oscillation stabilization wait Normal operation mode Subclock operation mode (fx operates, PLL operates) Clock through mode (PLL operates) PLL lockup time wait HALT mode (fx operates, PLL operates) PLL mode (PLL operates) Oscillation stabilization waitNote Clock through mode (PLL stops) IDLE1 mode (fx operates, PLL operates) Subclock operation mode (fx stops, PLL stops) Sub-IDLE mode (fx stops, PLL stops) Oscillation stabilization waitNote IDLE2 mode (fx operates, PLL stops) HALT mode (fx operates, PLL stops) Oscillation stabilization waitNote IDLE1 mode (fx operates, PLL stops) STOP mode (fx stops, PLL stops) Note If a WDT overflow occurs during an oscillation stabilization time, the CPU operates on the internal oscillation clock. Remark fX: Main clock oscillation frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1248 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W < > < > < > PSC NMI1M NMI0M INTM 0 NMI1M Address: FFFFF1FEH < > 0 0 0 Control of releasing standby mode by INTWDT2 signal 0 Releasing standby mode by INTWDT2 signal enabled 1 Releasing standby mode by INTWDT2 signal disabled NMI0M Control of releasing standby mode by NMI pin input 0 Releasing standby mode by NMI pin input enabled 1 Releasing standby mode by NMI pin input disabled INTM STP Control of releasing standby mode by maskable interrupt request signals 0 Releasing standby mode by maskable interrupt request signals enabled 1 Releasing standby mode by maskable interrupt request signals disabled Standby modeNote setting STP 0 Normal mode 1 Standby mode Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1 and PSMR.PSM0 bits and then set the STP bit. 2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is released. 3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an unmasked interrupt request signal being held pending when the IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1249 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H PSMR 0 R/W 0 Address: FFFFF820H 0 0 PSM1 PSM0 0 0 IDLE1, sub-IDLE modes 0 1 STOP mode 1 0 IDLE2, sub-IDLE modes 1 1 STOP mode 0 0 < > < > PSM1 PSM0 Specification of operation in software standby mode Cautions 1. Be sure to set bits 2 to 7 to "0". 2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1. Remark IDLE1: In this mode, all operations except the oscillator operation and some other circuits (flash memory and PLL) are stopped. After the IDLE1 mode is released, the normal operation mode is restored without needing to secure the oscillation stabilization time, like the HALT mode. IDLE2: In this mode, all operations except the oscillator operation are stopped. After the IDLE2 mode is released, the normal operation mode is restored following the lapse of the setup time specified by the OSTS register (flash memory and PLL). STOP: In this mode, all operations except the subclock oscillator operation are stopped. After the STOP mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the OSTS register. Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1250 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. This register can be read or written in 8-bit units. Reset sets this register to 06H. After reset: 06H OSTS R/W 0 0 OSTS2 OSTS1 Address: FFFFF6C0H 0 0 0 OSTS2 OSTS1 OSTS0 OSTS0 Selection of oscillation stabilization time/setup timeNote fX 0 0 0 3 MHz 6 MHz 10 0.341 ms 0.171 ms 11 2 /fX 0 0 1 2 /fX 0.683 ms 0.341 ms 0 1 0 212/fX 1.365 ms 0.683 ms 13 2.730 ms 1.365 ms 14 5.461 ms 2.731 ms 15 0 1 1 0 1 0 2 /fX 2 /fX 1 0 1 2 /fX 10.923 ms 5.461 ms 1 1 0 216/fX 21.85 ms 10.92 ms 1 1 1 Setting prohibited Note The oscillation stabilization time and setup time are required when the STOP mode and IDLE2 mode are released, respectively. Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the STOP mode, regardless of whether the STOP mode is released by reset or the occurrence of an interrupt request signal. STOP mode release Voltage waveform of X1 pin a VSS 2. Be sure to set bits 3 to 7 to "0". 3. The oscillation stabilization time following reset release is 216/fX (because the initial value of the OSTS register = 06H). Remark fX = Main clock oscillation frequency R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1251 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.3 HALT Mode 24.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 24-3 shows the operating status in the HALT mode. The average current consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the pending interrupt request. 24.3.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 pin input), unmasked internal interrupt request signal from a peripheral function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). After the HALT mode has been released, the normal operation mode is restored. (1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 24-2. Operation After Releasing HALT Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed. or the next instruction is executed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1252 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 24-3. Operating Status in HALT Mode Setting of HALT Mode Operating Status Item When Subclock Is Not Used Main clock oscillator (fX) Oscillation enabled - Subclock oscillator (fXT) Internal oscillator (fR) Oscillation enabled PLL Operable CPU Stops operation DMA controller Operable Interrupt controller Operable Timer TAA0 to TAA2, TAA4 TAB1 When Subclock Is Used Note1 Oscillation enabled Operable Operable TMM0 to TMM3 Operable when a clock other than fXT is Operable selected as the count clock TMT0 Operable Operable when fX (divided BRG) is Real-time counter (RTC) Operable selected as the count clock Operable when a clock other than fXT is Watchdog timer (WDT2) Operable selected as the count clock Serial interface CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note2 UARTC0, Operable Operable Operable UARTC2 to UARTC4 A/D converter Operable Note2 Operable Real-time output function (RTO) Operable Key interrupt function (KR) Operable CRC operation circuit Operable (No data input to the CRCIN register because the CPU is stopped) Port function Retains status before HALT mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents D/A converter of the internal RAM are retained as they were before the HALT mode was set. Note3 CAN Operable USB function Operable Notes1. V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only 3. PD70F3819, 70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1253 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.4 IDLE1 Mode 24.4.1 Setting and operation status The IDLE1 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 24-5 shows the operating status in the IDLE1 mode. The IDLE1 mode can reduce the power consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE1 mode has been released, in the same manner as when the HALT mode is released. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE1 mode. 2. If the IDLE1 mode is set while an unmasked interrupt request signal is being held pending, the IDLE1 mode is released immediately by the pending interrupt request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1254 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.4.2 Releasing IDLE1 mode The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 pin input), unmasked internal interrupt request signal from a peripheral function operable in the IDLE1 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). After the IDLE1 mode has been released, the normal operation mode is restored. (1) Releasing IDLE1 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE1 mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE1 mode is released and that interrupt request signal is acknowledged. Caution An interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not released. Table 24-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the prescribed setup time. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed after or the next instruction is executed after securing the prescribed setup time. securing the prescribed setup time. (2) Releasing IDLE1 mode by reset The same operation as the normal reset operation is performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1255 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-5. Operating Status in IDLE1 Mode Setting of IDLE1 Mode Operating Status Item When Subclock Is Not Used Main clock oscillator (fX) When Subclock Is Used Oscillation enabled - Subclock oscillator (fXT) Oscillation enabled Internal oscillator (fR) Oscillation enabled PLL Operable CPU Stops operation DMA controller Stops operation Interrupt controller Stops operation (but standby mode release is possible) Timer TAA0 to TAA2, TAA4 TAB1 Note1 Stops operation Stops operation TMM0 to TMM3 TMT0 Operable when fR/8 is selected as the count clock Operable when fR/8 or fXT is selected as the count clock Stops operation Real-time counter (RTC) Operable when fX (divided BRG) is selected as the count clock Operable Watchdog timer (WDT2) Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface Operable when the SCKFn input clock is selected as the count clock (n = 0, 2 to 4) CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note2 UARTC0, UARTC2 to UARTC4 A/D converter D/A converter Stops operation Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected) Holds operation (conversion result held) Note2 Holds operation (output held Note 3 Note 3 Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC operation circuit Stops operation ) Port function Retains status before IDLE1 mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE1 mode was set. Note 4 CAN Stops operation USB function Operable when the UCLK input is selected as the operation clock or when the PLL Note 3 is operating. Notes 1. V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only. 3. To lower the power consumption, stop the A/D converter, D/A converter, and USB function controller before shifting to the IDLE1 mode. 4. PD70F3819, 70F3825 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1256 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.5 IDLE2 Mode 24.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 24-7 shows the operating status in the IDLE2 mode. The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped, a setup time for the PLL and flash memory is required when IDLE2 mode is released. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE2 mode. 2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending, the IDLE2 mode is released immediately by the pending interrupt request. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1257 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.5.2 Releasing IDLE2 mode The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the IDLE2 mode was set. After the IDLE2 mode has been released, the normal operation mode is restored. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and that interrupt request signal is acknowledged. Caution The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released. Table 24-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the prescribed setup time. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed after or the next instruction is executed after securing the prescribed setup time. securing the prescribed setup time. (2) Releasing IDLE2 mode by reset The same operation as the normal reset operation is performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1258 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-7. Operating Status in IDLE2 Mode Setting of IDLE2 Mode Item Operating Status When Subclock Is Not Used Main clock oscillator (fX) Oscillation enabled Subclock oscillator (fXT) - Internal oscillator (fR) Oscillation enabled PLL Stops operation CPU Stops operation DMA controller Stops operation Interrupt controller Timer When Subclock Is Used Oscillation enabled Stops operation TAA0 to TAA2, TAA4 TAB1 Note1 Stops operation Stops operation TMM0 to TMM3 TMT0 Operable when fR/8 is selected as the count clock Operable when fR/8 or fXT is selected as the count clock Stops operation Real-time counter (RTC) Operable when fX (divided BRG) is selected as the count clock Operable Watchdog timer (WDT2) Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface Operable when the SCKFn input clock is selected as the count clock (n = 0, 2 to 4) CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note2 UARTC0, UARTC2 to UARTC4 A/D converter D/A converter Stops operation Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected) Holds operation (conversion result held) Note2 Holds operation (output held Note 3 Note 3 Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable ) CRC operation circuit Stops operation Port function Retains status before IDLE2 mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE2 mode was set. Note 4 CAN Stops operation USB function Operable when the UCLK input is selected as the operation clock or when the Note 3 PLL is operating. Notes 1. V850ES/JE3-H only 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only. 3. To lower the power consumption, stop the A/D converter, D/A converter, and USB function controller before shifting to the IDLE2 mode. 4. PD70F3819, 70F3825 only. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1259 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock IDLE mode status Interrupt request ROM circuit stopped Setup time count (2) Release by reset (RESET pin input, WDT2RES generation) This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1260 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.6 STOP Mode 24.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 24-9 shows the operating status in the STOP mode. Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. 2. If the STOP mode is set while an unmasked interrupt request signal is being held pending, the STOP mode is released immediately by the pending interrupt request. 24.6.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset signal (reset by RESET pin input, WDT2RES signal, or low-voltage detector (LVI)). After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt request signal is acknowledged. Caution The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and STOP mode is not released. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1261 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the oscillation stabilization time. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed after or the next instruction is executed after securing the oscillation stabilization time. securing the oscillation stabilization time. (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1262 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-9. Operating Status in STOP Mode Setting of STOP Mode Item Operating Status When Subclock Is Not Used Main clock oscillator (fX) Stops oscillation - Subclock oscillator (fXT) Internal oscillator (fR) Oscillation enabled PLL Stops operation CPU Stops operation DMA controller Stops operation Interrupt controller Stops operation Timer TAA0 to TAA2, TAA4 TAB1 When Subclock Is Used Note1 Oscillation enabled Stops operation Stops operation TMM0 to TMM3 Operable when fR/8 is selected as the count clock TMT0 Stops operation Real-time counter (RTC) Stops operation Operable when fXT is selected as the count clock Watchdog timer (WDT2) Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface Operable when the SCKFn input clock is selected as the count clock (n = 0, 2 to 4) CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note2 UARTC0, UARTC2 to UARTC4 A/D converter D/A converter Operable when fR/8 or fXT is selected as the count clock Stops operation Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected) Stops operation (conversion result undefined) Note2 Stops operation Notes 5, 6 Notes 3, 4 (high impedance is output) Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC operation circuit Stops operation Port function Retains status before STOP mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set. CAN Note 7 Stops operation USB function Stops operation Notes 1. V850ES/JE3-H only. 2. V850ES/JC3-H (48 pin), V850ES/JE3-H only. 3. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and starts operating again after the STOP mode is released. However, in that case, the A/D conversion results after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are invalid. 4. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced equivalently to when the A/D converter is stopped before the STOP mode is set. 5. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped and the pin status becomes high impedance. After the STOP mode is released, D/A conversion resumes, the setting time elapses, and the status returns to the output level before the STOP mode was set. 6. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced equivalently to when the D/A converter is stopped before the STOP mode is set. 7. PD70F3819, 70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1263 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock STOP status Interrupt request ROM circuit stopped Setup time count (2) Release by reset This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1264 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.7 Subclock Operation Mode 24.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only on the subclock. In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the power consumption can be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator. Table 24-10 shows the operating status in subclock operation mode. Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 6.3 (1) Processor clock control register (PCC). 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied and set the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT = 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from main clock (fXX) in accordance with the settings of the CK2 to CK0 bits 24.7.2 Releasing subclock operation mode The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is set to 0. If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and set the CK3 bit to 0. The normal operation mode is restored when the subclock operation mode is released. Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 5.3 (1) Processor clock control register (PCC). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1265 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-10. Operating Status in Subclock Operation Mode Setting of Subclock Operating Status Operation Mode When Main Clock Is Oscillating When Main Clock Is Stopped Item Subclock oscillator (fXT) Oscillation enabled Internal oscillator (fR) Oscillation enabled PLL Operable CPU Operable DMA controller Operable Interrupt controller Timer Stops operation Note 1 Operable TAA0 to TAA2, TAA4 Operable Stops operation Operable Stops operation TMM0 to TMM3 Operable Operable when fR/8 or fXT is selected as the count clock TMT0 Operable Stops operation Real-time counter (RTC) Operable Operable when fXT is selected as the count clock Watchdog timer (WDT2) Operable Operable when fR or fXT is selected as the count clock Serial interface Operable Operable when the SCKFn input clock is selected as the count clock (n = 0, 2 to 4) Operable Stops operation Operable Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected) Operable Stops operation TAB1 Note2 CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note3 UARTC0, UARTC2 to UARTC4 A/D converter Note3 Operable Real-time output function (RTO) Operable Key interrupt function (KR) Operable CRC operation circuit Operable Port function Settable Internal data Settable D/A converter Stops operation (output held) CAN Note 4 Operable Stops operation USB function Operable Stops operation Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock. 2. V850ES/JE3-H only. 3. V850ES/JC3-H (48 pin), V850ES/JE3-H only. 4. PD70F3819, 70F3825 only Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset (see 3.4.9 (2)). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1266 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION 24.8 Sub-IDLE Mode 24.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-chip peripheral functions is stopped. As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode. Table 24-12 shows the operating status in the sub-IDLE mode. Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode, insert the five or more NOP instructions. 2. If the sub-IDLE mode is set while an unmasked interrupt request signal is being held pending, the sub-IDLE mode is then released immediately by the pending interrupt request. 24.8.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP02, INTP05, INTP07 to INTP11, INTP14 to INTP16 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the sub-IDLE mode was set. When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. (1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the sub-IDLE mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt request signal is acknowledged. Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released. 2. When the sub-IDLE mode is released, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-IDLE mode is generated to when the mode is released. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1267 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 24 STANDBY FUNCTION Table 24-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Non-maskable interrupt request Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed. or the next instruction is executed. (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed. Table 24-12. Operating Status in Sub-IDLE Mode Setting of Sub-IDLE Mode Item Operating Status When Main Clock Is Oscillating Subclock oscillator (fXT) Oscillation enabled Internal oscillator (fR) Oscillation enabled PLL Operable CPU Stops operation DMA controller Stops operation Interrupt controller Stops operation TAA0 to TAA2, TAA4 Timer TAB1 When Main Clock Is Stopped Note2 Stops operation Note 1 Stops operation Stops operation TMM0 to TMM3 Operable when fR/8 or fXT is selected as the count clock TMT0 Stops operation Real-time counter (RTC) Operable Watchdog timer (WDT2) Operable when fR or fXT is selected as the count clock Serial interface Operable when the SCKFn input clock is selected as the count clock (n = 0, 2 to 4) CSIF0, CSIF2 to CSIF4 2 2 I C00, I C01 Note3 UARTC0, Operable when fXT is selected as the count clock Stops operation Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected) UARTC2 to UARTC4 A/D converter Holds operation (conversion result held) D/A converter Holds operation (output held Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable Note 4 Note 4 ) CRC operation circuit Stops operation Port function Retains status before sub-IDLE mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set. CAN Note 5 Stops operation USB function Stops operation Notes 1. 2. 3. 4. 5. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock. V850ES/JE3-H only. V850ES/JC3-H (48 pin), V850ES/JE3-H only To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE mode. PD70F3819, 70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1268 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS CHAPTER 25 RESET FUNCTIONS 25.1 Overview The following reset functions are available. (1) Four kinds of reset sources * External reset input via the RESET pin * Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) * System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage * System reset via the detecting clock monitor (CLM) oscillation stop After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF). (2) Emergency operation mode If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock. Caution In emergency operation mode, do not access on-chip peripheral I/O registers other than registers used for interrupts, port function, WDT2, or timer M, each of which can operate with the internal oscillation clock. In addition, operation of CSIF0, CSIF2 to CSIF4 and UARTC0 using the externally input clock is also prohibited in this mode. Figure 25-1. Block Diagram of Reset Function Internal bus Reset source flag register (RESF) WDT2RF WDT2 reset signal CLMRF LVIRF Set Set Set Clear Clear Clear CLM reset signal Reset signal RESET Reset signal to LVIM/LVIS register LVI reset signal Caution Reset signal An LVI circuit internal reset does not reset the LVI circuit. Remarks1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level select register R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1269 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.2 Registers to Check Reset Source The V850ES/JC3-H and V850ES/JE3-H have four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF). (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.8 Special registers). The RESF register indicates the source from which a reset signal is generated. This register can be read or written in 8-bit or 1-bit units. RESET pin input sets this register to 00H. The initial value differs if the source of reset is other than the RESET pin signal. After reset: 00HNote RESF 0 R/W 0 Address: FFFFF888H 0 WDT2RF 0 0 CLMRF LVIRF Reset signal from WDT2 WDT2RF 0 Not generated 1 Generated Reset signal from CLM CLMRF 0 Not generated 1 Generated Reset signal from LVI LVIRF 0 Not generated 1 Generated Note The value of the RESF register is set to 00H when a reset is executed via the RESET pin. When a reset is executed by the watchdog timer 2 (WDT2), low-voltage detector (LVI), or clock monitor (CLM), the reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other sources are retained. Caution Only "0" can be written to each bit of this register. If writing "0" conflicts with setting the flag (occurrence of reset), setting the flag takes precedence. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1270 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.3 Operation 25.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 25-1. Hardware Status on RESET Pin Input Item During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fX to fX/1,024) Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fCLK), Operation starts after securing oscillation Operation stops stabilization time (initialized to fXX/8) CPU clock (fCPU) CPU Program execution starts after securing Initialized oscillation stabilization time Watchdog timer 2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged). I/O lines (ports/alternate-function High impedance Otherwise value immediately after reset input is retained. Note pins) On-chip peripheral I/O registers Initialized to specified status, OCDM register is set (01H). Other on-chip peripheral functions Operation stops Operation can be started after securing oscillation stabilization time Note When the power is turned on, the following pin may output an undefined level temporarily, even during reset. * P10/ANO0 pin * DDO pin * P53/SIF2/KR3/RTP03/DDO pin Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a high level is input to the P56/INTP05/DRST pin after a reset release before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1271 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS Figure 25-2. Timing of Reset Operation by RESET Pin Input fX fCLK Initialized to fXX/8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 25-3. Timing of Power-on Reset Operation VDD fX fCLK Initialized to fXX/8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Must be on-chip regulator stabilization time (1 ms (max.)) or longer. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Overflow of timer for oscillation stabilization Page 1272 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released. The main clock oscillator is stopped during the reset period. Table 25-2. Hardware Status During Watchdog Timer 2 Reset Operation Item During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fXX), Operation stops CPU Operation starts after securing oscillation stabilization time (initialized to fXX/8) CPU clock (fCPU) Initialized Program execution after securing oscillation stabilization time Watchdog timer 2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Otherwise value immediately after reset input is retained. I/O lines (ports/alternate-function High impedance pins) On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value. On-chip peripheral functions other Operation stops than above R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Operation can be started after securing oscillation stabilization time. Page 1273 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS Figure 25-4. Timing of Reset Operation by WDT2RES Signal Generation fX fCLK Initialized to fXX/8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1274 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status. The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI detection voltage. The main clock oscillator is stopped during the reset period. When the LVIMD bit = 0, an interrupt request signal (INTLVI) is generated if a low voltage is detected. Table 25-3. Hardware Status During Reset Operation by Low-Voltage Detector Item During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fXX), Operation stops CPU clock (fCPU) CPU Operation starts after securing oscillation stabilization time (initialized to fXX/8) Initialized Program execution starts after securing oscillation stabilization time WDT2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Internal RAM Otherwise value immediately after reset input is retained. I/O lines (ports/alternate-function High impedance pins) On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value. LVI Operation stops On-chip peripheral functions other Operation stops Remark Operation can be started after securing oscillation stabilization time. than above For the reset timing of the low-voltage detector, see CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1275 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.3.4 Operation after reset release After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value: 216/fX) is secured, and the CPU starts program execution. WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. Figure 25-5. Operation After Reset Release Main clock Internal oscillation clock V850ES/JC3-H, V850ES/JE3-H WDT2 Reset Counting of oscillation stabilization time Operation stops Normal operation (fCPU = Main clock) Operation in progress Operation stops Operation in progress Clock monitor (1) Emergent operation mode If an anomaly occurs in the main clock before oscillation stabilization time is secured, WDT2 overflows before executing the CPU program. At this time, the CPU starts program execution by using the internal oscillation clock as the source clock. Figure 25-6. Operation After Reset Release Main clock Internal oscillation clock V850ES/JC3-H, V850ES/JE3-H WDT2 Reset Operation stops Counting of oscillation stabilization time Operation in progress Emergency mode (fCPU = internal oscillation clock) Operation in progress (re-count) Operation stops Clock monitor WDT overflows The CPU operation clock states can be checked with the CPU operation clock status register (CCLS). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1276 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 25 RESET FUNCTIONS 25.3.5 Reset function operation flow Start (reset source occurs) Set RESF registerNote 1 Reset occurs reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization time secured? No Yes (in normal operation mode) No WDT2 overflow? Yes (in emergent operation mode) fCPU = fRNote 2 CCLS.CCLSF bit 1 WDT2 restart fCPU = fX Firmware operation CPU operation starts from reset address (fCPU = fX/8, fR) Software processing No CCLS.CCLSF bit = 1? Yes Emergent operation Normal operation No (in emergent operation mode) No (in normal operation mode) Reset source generated? Yes Notes 1. Bit to be set differs depending on the reset source. Reset Source WDT2RF Bit CRMRF Bit LVIRF Bit RESET pin 0 0 0 WDT2 1 Value before reset is retained. Value before reset is retained. CLM Value before reset is retained. 1 Value before reset is retained. LVI Value before reset is retained. Value before reset is retained. 1 2. The internal oscillator cannot be stopped. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1277 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 26 CLOCK MONITOR CHAPTER 26 CLOCK MONITOR 26.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 25.2 Registers to Check Reset Source. The clock monitor automatically stops under the following conditions. * During oscillation stabilization time after STOP mode is released * When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit = 0 during main clock operation) * When the sampling clock (internal oscillation clock) is stopped * When the CPU operates with the internal oscillation clock 26.2 Configuration The clock monitor includes the following hardware. Table 26-1. Configuration of Clock Monitor Item Control register Configuration Clock monitor mode register (CLM) Figure 26-1. Timing of Reset via RESET Pin Input Main clock Internal reset signal Internal oscillation clock Enable/disable CLME Clock monitor mode register (CLM) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1278 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 26 CLOCK MONITOR 26.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H CLM R/W Address: FFFFF870H 7 6 5 4 3 2 1 <0> 0 0 0 0 0 0 0 CLME CLME Clock monitor operation enable or disable 0 Disable clock monitor operation. 1 Enable clock monitor operation. Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other than reset. 2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the RESF.CLMRF bit is set to 1. 3. Be sure to set bits 7 to 1 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1279 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 26 CLOCK MONITOR 26.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> Enabling operation by setting the CLM.CLME bit to 1 <Stop conditions> * While oscillation stabilization time is being counted after STOP mode is released * When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.CLS bit = 0 during main clock operation) * When the sampling clock (internal oscillation clock) is stopped * When the CPU operates using the internal oscillation clock Table 26-2. Operation Status of Clock Monitor (When CLM.CLME Bit = 1, During Internal Oscillation Clock Operation) CPU Operating Clock Operation Mode Status of Main Clock Status of Internal Status of Clock Monitor Oscillation Clock Main clock Subclock Note 1 Operates Note 1 Operates Note 1 Stops Note 1 Operates Note 1 Stops Note 3 HALT mode Oscillates Oscillates IDLE1, IDLE2 modes Oscillates Oscillates STOP mode Stops Oscillates Sub-IDLE mode Oscillates Oscillates Sub-IDLE mode Stops Oscillates Note 2 Note 2 Note 2 (PCC.MCK = 0) Subclock (PCC.MCK = 1) Internal oscillation clock - Stops Oscillates Stops During reset - Stops Stops Stops Notes 1. The internal oscillator can be stopped by setting the RCM.RSTOP bit to 1. 2. The clock monitor is stopped while the internal oscillator is stopped. 3. The internal oscillator cannot be stopped by software. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1280 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 26 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 26-2. Figure 26-2. Reset Period Due to That Oscillation of Main Clock Is Stopped Four internal oscillation clocks Main clock Internal oscillation clock Internal reset signal CLM.CLME bit RESF.CLMRF bit (2) Clock monitor status after RESET input RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by software at the end of the oscillation stabilization time of the main clock, monitoring is started. Figure 26-3. Clock Monitor Status After RESET Input (CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time) CPU operation Normal operation Reset Clock supply stopped Normal operation Main clock Oscillation stabilization time Internal oscillation clock RESET Set to 1 by software CLME Clock monitor status Monitoring R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Monitoring stopped Monitoring Page 1281 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 26 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started. Figure 26-4. Operation in STOP Mode or After STOP Mode Is Released CPU Normal operation operation STOP Oscillation stabilization time Normal operation Main clock Oscillation stops Oscillation stabilization time (set by OSTS register) Internal oscillation clock CLME Clock monitor status During monitor Monitor stops During monitor (4) Operation when main clock is stopped (arbitrary) During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation is automatically started when the main clock operation is started. Figure 26-5. Operation When Main Clock Is Stopped (Arbitrary) Subclock operation CPU operation PCC.MCK bit = 1 Main clock operation Oscillation stabilization time count by software Main clock Oscillation stops Oscillation stabilization time (set by OSTS register) Internal oscillation clock CLME Clock monitor status During monitor Monitor stops Monitor stops During monitor (5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1) The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1282 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) 27.1 Functions The low-voltage detector (LVI) has the following functions. * If the interrupt occurrence at low voltage detection is selected, the low-voltage detector continuously compares the supply voltage (VDD) and the detected voltage (VLVI), and generates an internal interrupt signal when the supply voltage drops or rises across the detected voltage. * If the reset occurrence at low voltage detection is selected, the low-voltage detector generates an interrupt reset signal when the supply voltage (VDD) drops across the detected voltage (VLVI). * Interrupt or reset signal can be selected by software. * Can operate in STOP mode. If the low-voltage detector is used to generate a reset signal, the RESF.LVIRF bit is set to 1 when the reset signal is generated. For details of RESF register, see 25.2 Registers to Check Reset Source. 27.2 Configuration The block diagram of the low-voltage detector is shown below. Figure 27-1. Block Diagram of Low-Voltage Detector VDD Lowvoltage detection level selector N-ch Internal reset signal + - Selector VDD INTLVI Detected voltage source (VLVI) LVION LVIMD LVIF Low-voltage detection register (LVIM) Internal bus R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1283 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) 27.3 Registers The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Internal RAM data status register (RAMS) (1) Low-voltage detection register (LVIM) The LVIM register is a special register. This can be written only in the special combination of the sequences (see 3.4.8 Special registers). The LVIM register is used to enable or disable low-voltage detection, and to set the operation mode of the lowvoltage detector. This register can be read or written in 8-bit or 1-bit units. However, the LVIF bit is read-only. After reset: 00H LVIM Note 1 R/W Address: FFFFF890H <7> 6 5 4 3 2 <1> <0> LVION 0 0 0 0 0 LVIMD LVIF LVION Low-voltage detection operation enable or disable 0 Disable operation. 1 Enable operation. LVIMD Selection of operation mode of low-voltage detection Generates interrupt signal INTLVI when the supply voltage drops or rises across 0 the detection voltage value. Generates internal reset signal LVIRES when the supply voltage drops across the 1 detected voltage value. Note 2 LVIF Low-voltage detection flag 0 When supply voltage > detected voltage, or when operation is disabled 1 Supply voltage of connected power supply < detected voltage Notes 1. Reset by low-voltage detection: 82H Reset due to other source: 00H 2. After the LVI operation has started (LVION bit = 1) or when INTLVI has occurred, confirm the supply voltage state using the LVIF bit. Cautions 1. When the LVION and LVIMD bits to 1, the low-voltage detector cannot be stopped until the reset request due to other than the low-voltage detection is generated. 2. When the LVION bit is set to 1, the comparator in the LVI circuit starts operating. Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after the LVION bit is set. 3. Be sure to set bits 6 to 2 to "0". R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1284 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) (2) Internal RAM data status register (RAMS) The RAMS register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is a flag register that indicates whether the internal RAM is valid or not. This register can be read or written in 8-bit or 1-bit units. The set/clear conditions for the RAMF bit are shown below. * Setting conditions: Detection of voltage lower than specified level Set by instruction * Clearing condition: Writing of 0 in specific sequence After reset: 01H RAMS Note R/W Address: FFFFF892H 7 6 5 4 3 2 1 <0> 0 0 0 0 0 0 0 RAMF RAMF Internal RAM voltage detection 0 Voltage lower than RAM retention voltage is not detected. 1 Voltage lower than RAM retention voltage is detected. Note This register is reset only when a voltage drop below the RAM retention voltage is detected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1285 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) 27.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 27.4.1 To use for internal reset signal <To start operation> <1> Mask the interrupt of LVI. <2> Set the LVIM.LVION bit to 1 (to enable operation). <3> Insert a wait cycle of 0.2 ms (max.) or more by software. <4> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <5> Set the LVIMD bit to 1 (to generate an internal reset signal). Caution If the LVIMD bit is set to 1, the contents of the LVIM register cannot be changed until a reset request other than LVI is generated. Figure 27-2. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1) Supply voltage (VDD) LVI detected voltage (2.95 V (TYP.)) Time LVION bit Clear Delay Delay LVI detected signal LVI reset request signal Internal reset signal (active low) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1286 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) 27.4.2 To use for interrupt <To start operation> <1> Mask the interrupt of LVI. <2> Set the LVIM.LVION bit to 1 (to enable operation). <3> Insert a wait cycle of 0.2 ms (max.) or more by software. <4> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <5> Clear the interrupt request flag of LVI. <6> Unmask the interrupt of LVI. <To stop operation> Clear the LVION bit to 0. Figure 27-3. Operation Timing of Low-Voltage Detector (LVIMD Bit = 0) Supply voltage (VDD) LVI detected voltage (2.95 V (TYP.)) External RESET IC detected voltage Time LVION bit Delay Clear Delay LVI detected signal Note INTLVI signal Delay RESET pin Internal reset signal (active low) Note Since the LVION bit is the initial value (operation disabled) due to the external reset input, no INTLVI interrupts occur. Caution When the INTLVI signal is generated, confirm, using the LVIM.LVIF bit, whether the INTLVI signal is generated due to a supply voltage drop or rise across the detected voltage. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1287 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) 27.5 RAM Retention Voltage Detection Operation The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMS.RAMF bit is set to 1. Figure 27-4. Operation Timing of RAM Retention Voltage Detection Function Initialize RAM (RAMF bit is also cleared) VDD < 2.0 V detected Set RAMF bit Initialize RAM (RAMF bit is also cleared) Supply voltage (VDD) 2.0 V (minimum RAM retention voltage) RESET pin RAMS.RAMF bit RAM data is not retained When power application, RAMF bit is set RAM data is not retained RAMF bit = 0 is retained regardless of RESET pin if VDD > 2.0 V Remarks 1. The RAMF bit is set to 1 if the supply voltage drops under the minimum RAM retention voltage (2.0 V (TYP.)). 2. The RAMF bit operates regardless of the RESET pin status. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1288 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 28 CRC FUNCTION CHAPTER 28 CRC FUNCTION 28.1 Functions * CRC operation circuit for detection of data block errors * Generation of 16-bit CRC code using a CRC-CCITT (X16 + X12 + X5 + 1) generation polynomial for blocks of data of any length in 8-bit units * CRC code is set to the CRCD data register each time 1-byte data is transferred to the CRCIN register, after the initial value is set to the CRCD register. 28.2 Configuration The CRC function includes the following hardware. Table 28-1. CRC Configuration Item Control registers Configuration CRC input register (CRCIN) CRC data register (CRCD) Figure 28-1. Block Diagram of CRC Register Internal bus CRC input register (CRCIN) (8 bits) CRC code generator CRC data register (CRCD) (16 bits) Internal bus R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1289 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 28 CRC FUNCTION 28.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF310H 6 7 5 4 3 2 1 0 CRCIN (2) CRC data register (CRCD) The CRCD register is a 16-bit register that stores the CRC-CCITT operation results. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the CRCD register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: FFFFF312H 11 10 9 8 7 6 5 4 3 2 1 0 CRCD R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1290 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 28 CRC FUNCTION 28.4 Operation An example of the CRC operation circuit is shown below. Figure 28-2. CRC Operation Circuit Operation Example (LSB First) b7 b0 (1) Setting of CRCIN = 01H b15 b0 (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000). Therefore, the CRC code from generation polynomial X16 + X12 + 5 X + 1 becomes the remainder when (1000 0000) X16 is divided by (1 0001 0000 0010 0001) using the modulo-2 operation formula. The modulo-2 operation is performed based on the following formula. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 LSB 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 0000 0000 0000 0001 0001 1000 0000 1 1000 0000 1000 1000 0000 MSB 0 1 1000 LSB MSB 9 8 1 1 Therefore, the CRC code becomes 1001 0001 1000 1000 . Since LSB first is used, this corresponds to 1189H in hexadecimal notation. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1291 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 28 CRC FUNCTION 28.5 Usage Method How to use the CRC logic circuit is described below. Figure 28-3. CRC Operation Flow Start Write of 0000H to CRCD register Input data exists? Yes No CRCD register read CRCIN register write End [Basic usage method] <1> Write 0000H to the CRCD register. <2> Write the required quantity of data to the CRCIN register. <3> Read the CRCD register. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1292 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 28 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example. Figure 28-4. CRC Transmission Example 78 56 34 12 Transmit/receive data (12345678H) F6 08 CRC code (08F6H) Setting procedure on transmitting side <1> Write the initial value 0000H to the CRCD register. <2> Write the 1 byte of data to be transmitted first to the transmit buffer register. (At this time, also write the same data to the CRCIN register.) <3> When transmitting several bytes of data, write the same data to the CRCIN register each time transmit data is written to the transmit buffer register. <4> After all the data has been transmitted, write the contents of the CRCD register (CRC code) to the transmit buffer register and transmit them. (Since this is LSB first, transmit the data starting from the lower bytes, then the higher bytes.) Setting procedure on receiving side <1> Write the initial value 0000H to the CRCD register. <2> When reception of the first 1 byte of data is complete, write that receive data to the CRCIN register. <3> If receiving several bytes of data, write the receive data to the CRCIN register upon every reception completion. (In the case of normal reception, when all the receive data has been written to the CRCIN register, the contents of the CRCD register on the receiving side and the contents of the CRCD register on the transmitting side are the same.) <4> Next, the CRC code is transmitted from the transmitting side, so write this data to the CRCIN register similarly to receive data. <5> When reception of all the data, including the CRC code, has been completed, reception was normal if the contents of the CRCD register are 0000H. If the contents of the CRCD register are other than 0000H, this indicates a communication error, so transmit a resend request to the transmitting side. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1293 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 29 REGULATOR CHAPTER 29 REGULATOR 29.1 Overview The V850ES/JC3-H and V850ES/JE3-H include a regulator to reduce power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers). Figure 29-1. Regulator AVREF0 AVREF1 D/A converter FLMD0 VDD EVDD I/O buffer A/D converter Regulator EVDD Flash memory REGC Sub Main oscillator oscillator Internal digital circuits 2.5 V (TYP.) USB I/O buffer EVDD Caution Bidirectional level shifter Be sure to use in VDD = UVDD = VREF0 = AVREF1. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1294 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 29 REGULATOR 29.2 Operation The regulators of the V850ES/JC3-H and V850ES/JE3-H always operate in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, subclock operation mode, sub IDLE mode, or during reset). Be sure to connect a capacitor (4.7 F (Recommend value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below. Figure 29-2. REGC Pin Connection VDD Input voltage 2.85 to 3.6 V REG Voltage supply to oscillator/internal logic REGC 4.7 F (Recommend value) VSS R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1295 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY CHAPTER 30 FLASH MEMORY The V850ES/JC3-H and V850ES/JE3-H incorporate a flash memory. * PD70F3809, 70F3814, 70F3820: 16 KB flash memory * PD70F3810, 70F3815, 70F3821: 32 KB flash memory * PD70F3811, 70F3816, 70F3822: 64 KB flash memory * PD70F3812, 70F3817, 70F3823: 128 KB flash memory * PD70F3813, 70F3818, 70F3819, 70F3824, 70F3825: 256 KB flash memory Flash memory versions offer the following advantages for development environments and mass production applications. { For altering software after the V850ES/JC3-H and V850ES/JE3-H are soldered onto the target system. { For data adjustment when starting mass production. { For differentiating software according to the specification in small scale production of various models. { For facilitating inventory management. { For updating software after shipment. 30.1 Features { 4-byte/1-clock access (when instruction is fetched) { Capacity: 16/32/64/128/256 KB { Rewrite voltage: Erase/write with a single power supply { Rewriting method * Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) { Flash memory rewrite prohibit function supported (security function) { Safe rewriting of entire flash memory area by self programming using boot swap function { Interrupts can be acknowledged during self programming. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1296 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.2 Memory Configuration The internal flash memory area of the V850ES/JC3-H and V850ES/JE3-H is divided into 4, 8, 16, 32 or 64 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory located at the addresses of blocks 0 to 15 is replaced by the physical memory located at the addresses of blocks 16 to 31. For details of the boot swap function, see 30.5 Rewriting by Self Programming. Figure 30-1. Flash Memory Mapping (1/2) Block 15 (4 KB) Block 14 (4 KB) : Block 3 (4 KB) Block 2 (4 KB) Block 7 (4 KB) Block 7 (4 KB) Block 6 (4 KB) Block 6 (4 KB) Block 5 (4 KB) Block 5 (4 KB) Block 3 (4 KB) Block 3 (4 KB) Block 2 (4 KB) Block 2 (4 KB) Block 1 (4 KB) Block 1 (4 KB) Block 1 (4 KB) Block 0 (4 KB) Block 0 (4 KB) Block 0 (4 KB) PD70F3809, 70F3814, 70F3820 (16 KB) PD70F3810, 70F3815, 70F3821 (32 KB) PD70F3811, 70F3816, 70F3822 (64 KB) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 00010000H 0000FFFFH 0000F000H 0000EFFFH 0000E000H 0000DFFFH 00008000H 00007FFFH 00006000H 00005FFFH 00005000H 00004FFFH 00004000H 00003FFFH 00003000H 00002FFFH 00002000H 00001FFFH 00001000H 00000FFFH 00000000H Page 1297 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-1. Flash Memory Mapping (2/2) Block 63 (4 KB) Block 62 (4 KB) Block 31 (4 KB) Block 30 (4 KB) Block 31 (4 KB) Block 30 (4 KB) Note 1 Block 16 (4 KB) Note 2 00040000H 0003FFFFH 0003F000H 0003EFFFH 0003E000H 0003DFFFH 00020000H 0001FFFFH 0001F000H 0001EFFFH 0001E000H 0001DFFFH Block 16 (4 KB) Block 15 (4 KB) Block 15 (4 KB) Block 14 (4 KB) Block 14 (4 KB) Block 7 (4 KB) Block 7 (4 KB) Block 6 (4 KB) Block 6 (4 KB) Block 2 (4 KB) Block 2 (4 KB) Block 1 (4 KB) Block 1 (4 KB) Block 0 (4 KB) Block 0 (4 KB) 00010000H 0000FFFFH 0000F000H 0000EFFFH 0000E000H 0000DFFFH 00008000H 00007FFFH 00007000H 00006FFFH 00006000H 00005FFFH 00003000H 00002FFFH 00002000H 00001FFFH 00001000H 00000FFFH 00000000H PD70F3812, 70F3817, 70F3823 (128 KB) PD70F3813, 70F3818, 70F3819, 70F3824, 70F3825 (256 KB) Notes 1. Area to be replaced with the boot area by the boot swap function 2. Boot area R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1298 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.3 Functional Overview The internal flash memory of the V850ES/JC3-H and V850ES/JE3-H can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/JC3-H and V850ES/JE3-H have already been mounted on the target system or not (off-board/on-board programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed after production/shipment of the target system. A boot swap function that rewrites the entire flash memory area safely is also supported. In addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. Table 30-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Overview Operation Mode Flash memory can be rewritten after the device is mounted on the target Flash memory system, by using a dedicated flash programmer. programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has Normal operation mode been written to the flash memory in advance by means of off-board/onboard programming. (During self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. Therefore, the rewrite program must be transferred to the internal RAM or external memory in advance). Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1299 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-2. Basic Functions Function Functional Outline Support (: Supported, x: Not supported) On-Board/Off-Board Self Programming Programming Block erasure The contents of specified memory blocks x are erased. Chip erasure The contents of the entire memory area are erased all at once. Writing to specified addresses, and a verify Write check to see if write level is secured are performed. Verify/checksum Data read from the flash memory is x compared with data transferred from the (Can be read by user program) flash programmer. Blank check erase command, program command, and x (Supported only when setting read command is prohibited, and rewriting is changed from enable to The erasure status of the entire memory is checked. Security setting Use of the block erase command, chip of the boot area is prohibited. disable) The following table lists the security functions. The block erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via onboard/off-board programming. Each security function can be used in combination with the others at the same time. Table 30-3. Security Functions Function Block erase command prohibit Function Outline Execution of a block erase command on all blocks is prohibited. Setting of prohibition can be initialized by execution of a chip erase command. Chip erase command prohibit Execution of block erase and chip erase commands on all the blocks is prohibited. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Program command prohibit Execution of program and block erase commands on all the blocks is prohibited. Setting of prohibition can be initialized by execution of the chip erase command. Read command prohibit Execution of a read command on all of the blocks is prohibited. Setting of the prohibition can be initialized by execution of a chip erase command. Boot area rewrite prohibit Execution of write, block erase, and chip erase commands on the boot area is prohibited. Setting of the prohibition of rewriting the boot area cannot be initialized after it is once set. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1300 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-4. Security Setting Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (: Executable, x: Not Executable, -: Not Supported) On-Board/ On-Board/ Self Programming Off-Board Programming Self Programming Off-Board Programming Block erase Block erase command: x Block erasure (FlashBlockErase): Setting of Supported only command Chip erase command: Chip erasure: - prohibition can be when setting is prohibit Program command: Write (FlashWordWrite): initialized by chip changed from Read command: Read (FlashWordRead): erase command. enable to prohibit Chip erase Block erase command: x Block erasure (FlashBlockErase): Setting of command Chip erase command: x Chip erasure: - prohibition cannot prohibit Program command: Write (FlashWordWrite): be initialized. Read command: Read (FlashWordRead): Program Block erase command: x Block erasure (FlashBlockErase): Setting of command Chip erase command: Chip erasure: - prohibition can be prohibit Program command: x Write (FlashWordWrite): initialized by chip Read command: Read (FlashWordRead): erase command. Read Block erase command: Block erasure (FlashBlockErase): Setting of command Chip erase command: Chip erasure: - prohibition can be prohibit Program command: Write (FlashWordWrite): initialized by chip Read command: x Read (FlashWordRead): Note 1 erase command. Boot area Block erase command: x Block erasure (FlashBlockErase): x Setting of Supported only rewrite Chip erase command: x Chip erasure: - prohibition cannot when setting is prohibit Program command: x Write (FlashWordWrite): x be initialized. changed from Read command: Read (FlashWordRead): Note 2 Note 2 Note 2 Note 2 enable to Note 3 prohibit Notes 1. In this case, since the erase command is invalid, data different from the data already written in the flash memory cannot be written. 2. Executable except in boot area. 3. The boot area rewrite prohibit function becomes effective after the reset input. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1301 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/JC3-H and V850ES/JE3-H are mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 30.4.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850ES/JC3-H and V850ES/JE3-H. Figure 30-2. Environment Required for Writing Programs to Flash Memory FLMD0 FLMD1Note RS-232C VDD USB Host machine VSS Dedicated flash programmer RESET UARTC0/CSIF0/CSIF3 V850ES/JC3-H, V850ES/JE3-H Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board. A host machine is required for controlling the dedicated flash programmer. UARTC0, CSIF0, or CSIF3 is used for the interface between the dedicated flash programmer and the V850ES/JC3-H and V850ES/JE3-H to perform writing, erasing, etc. A dedicated program adapter (FA series) required for off-board writing. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1302 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/JC3-H or V850ES/JE3-H is performed by serial communication using the UARTC0, CSIF0, or CSIF3 interface of the V850ES/JC3-H or V850ES/JE3-H. (1) UARTC0 Transfer rate: 9,600 to 153,600 bps Figure 30-3. Communication with Dedicated Flash Programmer (UARTC0) Dedicated flash programmer FLMD0 FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS RESET RESET RxD TXDC0 TxD RXDC0 V850ES/JC3-H, V850ES/JE3-H Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board. (2) CSIF0, CSIF3 Serial clock: 5 MHz or less (MSB first) Figure 30-4. Communication with Dedicated Flash Programmer (CSIF0, CSIF3) FLMD0 FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS RESET Dedicated flash programmer SI SO SCK RESET SOF0, SOF3 SIF0, SIF3 V850ES/JC3-H, V850ES/JE3-H SCKF0, SCKF3 Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1303 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY (3) CSIF0 + HS, CSIF3 + HS Serial clock: 5 MHz or less (MSB first) Figure 30-5. Communication with Dedicated Flash Programmer (CSIF0 + HS, CSIF3 + HS) FLMD0 FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS RESET Dedicated flash programmer SI SO SCK HS RESET SOF0, SOF3 SIF0, SIF3 SCKF0, SCKF3 V850ES/JC3-H, V850ES/JE3-H P913 Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board. The dedicated flash programmer outputs the transfer clock, and the V850ES/JC3-H and V850ES/JE3-H operate as a slave. When the PG-FP5 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JC3-H and V850ES/JE3-H. For details, refer to the PG-FP5 User's Manual (U18865E). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1304 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-5. Signal Connections of Dedicated Flash Programmer (PG-FP5) V850ES/JC3-H, PG-FP5 Processing for Connection V850ES/JE3-H Signal Name I/O Pin Function Pin Name FLMD0 Output Write enable/disable FLMD0 FLMD1 Output Write enable/disable FLMD1 VDD - VDD voltage generation/voltage monitor VDD GND - Ground VSS Clock output to V850ES/JC3-H and X1, X2 CLK Output UARTC0 CSIF0, CSIF0 + HS, CSIF3 CSIF3 + HS Note 1 x Note 2 Note 1 x Note 2 Note 1 x Note 2 V850ES/JE3-H RESET Output Reset signal RESET SI/RxD Input Receive signal SOF0, SOF3/ SO/TxD Output Transmit signal TXDC0 SIF0, SIF3/ RXDC0 SCK Output Transfer clock SCKF0, SCKF3 x HS Input Handshake signal for CSIF0 + HS, CSIF3 P913 x x + HS communication Notes 1. Wire these pins as shown in Figures 30-6 and 31-7, or connect then to GND via pull-down resistor on board. 2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and supply the clock. Remark : Must be connected. x: Does not have to be connected. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1305 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-6. Wiring of V850ES/JC3-H (40 pin) Flash Writing Adapters (1/2) Pin No. Pin Name Recommended Connection 1 AVREF0 Connect to VDD pin of the programmer 2 AVSS Connect to GND pin of the programmer 3 VDD Connect to VDD pin of the programmer 4 REGC Connect the REGC pin to GND via 4.7 F capacitor 5 VSS Connect to GND pin of the programmer 6 X1 Connect to 3 to 6 MHz Resonator 7 X2 Connect to 3 to 6 MHz Resonator 8 RESET Connect to RESET (output) pin of the programmer 9 XT1 Connect to GND pin of the programmer 10 XT2 - 11 P03/INTP02/ADTRG/UCLK - 12 UDMF - 13 UDPF - 14 EVDD Connect to VDD pin of the programmer 15 VSS Connect to GND pin of the programmer 16 P34/TIAA10/TOAA10/TOAA1OFF/INTP09 - 17 P30/TXDC0/SOF4/INTP07 When UART (UARTC0) is used : connect to RxD (input) pin of the programmer When UART (UARTC0) is not used : pull-down 18 P31/RXDC0/SIF4/INTP08 Note When UART (UARTC0) is used : connect to TxD (output) pin of the programmer When UART (UARTC0) is not used : pull-down Note 19 P32/ASCKC0/SCKF4/TIAA00/TOAA00 - 20 P40/SIF0/TXDC4/SDA01 When CSI (CSIF0) is used : connect to SO (output) pin of the programmer When CSI (CSIF0)is not used : pull-down 21 P41/SOF0/RXDC4/SCL01 Note When CSI (CSIF0)is used : connect to SI (input) pin of the programmer When CSI (CSIF0)is not used : pull-down 22 P42/SCKF0/INTP10 Note When CSI(CSIF0)is used : connect to SCK (output) pin of the programmer When CSI (CSIF0)is not used : pull-down Note 23 P52/RTP02/DDI - 24 P53/SIF2/KR3/RTP03/DDO - 25 P54/SOF2/KR4/RTP04/DCK - 26 P55/SCKF2/KR5/RTP05/DMS - 27 P56/INTP05/DRST - 28 FLMD0 Connect to FLMD0 (output) pin of the programmer Note Independently connect to VSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1306 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-6. Wiring of V850ES/JC3-H (40 pin) Flash Writing Adapters (2/2) Pin No. Pin Name Recommended Connection 29 P96/TIAA21/TOAA21/INTP11 - 30 P97/SIF1/TIAA20/TOAA20 - 31 PDL5/FLMD1 Connect to FLMD1 (output) pin of the programmer 32 P910/SIF3/TXDC2/INTP14 When CSI (CSIF3) is used : connect to SO (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 33 P911/SOF3/RXDC2/INTP15 Note When CSI (CSIF3) is used : connect to SI (input) pin of the programmer When CSI (CSIF3) is not used : pull-down 34 P912/SCKF3 Note When CSI (CSIF3) is used : connect to SCK (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 35 P913/TOAB1OFF/INTP16 (HS) Note When CSI-HS (CSIF3) is used : connect to H/S (input) pin of the programmer When CSI-HS (CSIF3) is not used : pull-down 36 P74/ANI4 - 37 P73/ANI3 - 38 P72/ANI2 - 39 P71/ANI1 - 40 P70/ANI0 - Note Note Independently connect to VSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1307 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-6. Wiring Example of V850ES/JC3-H (40 pin) Flash Writing Adapter (In CSIF0 + HS Mode) (1/2) D VD D N G D VD D N G 30 31 21 25 Note 2 20 Note 4 Note 1 35 V850ES/JC3-H 40 pin 15 Connect this pin to GND. Connect this pin to VDD. 40 11 Note 3 1 5 D N G D VD D N G 4.7 F 10 RFU-3 SI R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 SO SCK RFU-2 RFU-1 VDE CLKOUT /RESET D VD FLMD1 FLMD0 VPP RESERVE/HS Page 1308 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-6. Wiring Example of V850ES/JC3-H (40 pin) Flash Writing Adapter (In CSIF0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIF3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTC0 is used. Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with the handling of unused pins (see 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins). 2. This adapter is for the 100-pin plastic LQFP package. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1309 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-7. Wiring of V850ES/JC3-H (48 pin) Flash Writing Adapters (1/2) Pin No. Pin Name Recommended Connection 1 AVREF0 Connect to VDD pin of the programmer 2 AVSS Connect to GND pin of the programmer 3 P10/ANO0 - 4 AVREF1 Connect to VDD pin of the programmer 5 VDD Connect to VDD pin of the programmer 6 REGC Connect the REGC pin to GND via 4.7 F capacitor 7 VSS Connect to GND pin of the programmer 8 X1 Connect to 3 to 6 MHz Resonator 9 X2 Connect to 3 to 6 MHz Resonator 10 RESET Connect to RESET (output) pin of the programmer 11 XT1 Connect to GND pin of the programmer 12 XT2 - 13 P03/INTP02/ADTRG/UCLK - 14 UDMF - 15 UDPF - 16 EVDD Connect to VDD pin of the programmer 17 VSS Connect to GND pin of the programmer 18 P34/TIAA10/TOAA10/TOAA1OFF/INTP09 19 P36/TXDC3/SCL00/CTXD0 Note1 20 P37/RXDC3/SDA00/CRXD0 21 P30/TXDC0/SOF4/INTP07 Note1 When UART (UARTC0) is used : connect to RxD (input) pin of the programmer When UART (UARTC0) is not used : pull-down 22 P31/RXDC0/SIF4/INTP08 Note When UART (UARTC0) is used : connect to TxD (output) pin of the programmer When UART (UARTC0) is not used : pull-down Note 23 P32/ASCKC0/SCKF4/TIAA00/TOAA00 - 24 P40/SIF0/TXDC4/SDA01 When CSI (CSIF0) is used : connect to SO (output) pin of the programmer When CSI (CSIF0)is not used : pull-down 25 P41/SOF0/RXDC4/SCL01 Note When CSI (CSIF0)is used : connect to SI (input) pin of the programmer When CSI (CSIF0)is not used : pull-down 26 P42/SCKF0/INTP10 Note When CSI(CSIF0)is used : connect to SCK (output) pin of the programmer When CSI (CSIF0)is not used : pull-down Note Notes1. PD70F3819 only 2. Independently connect to VSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1310 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-7. Wiring of V850ES/JC3-H (48 pin) Flash Writing Adapters (2/2) Pin No. Pin Name Recommended Connection 27 P52/KR2/RTP02/DDI - 28 P53/SIF2/KR3/ RTP03/DDO - 29 P54/SOF2/KR4/RTP04/DCK - 30 P55/SCKF2/KR5/RTP05/DMS - 31 P56/INTP05/DRST - 32 FLMD0 Connect to FLMD0 (output) pin of the programmer 33 P96/TIAA21/TOAA21/INTP11 - 34 P97/TIAA20/TOAA20 - 35 P92/TENC01/TIT01/TOT01 - 36 P93/TECR0/TIT00/TOT00 - 37 PDL5/FLMD1 Connect to FLMD1 (output) pin of the programmer 38 P94/TENC00/EVTT00 - 39 P910/SIF3/TXDC2/INTP14 When CSI (CSIF3) is used : connect to SO (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 40 P911/SOF3/RXDC2/INTP15 Note When CSI (CSIF3) is used : connect to SI (input) pin of the programmer When CSI (CSIF3) is not used : pull-down 41 P912/SCKF3 Note When CSI (CSIF3) is used : connect to SCK (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 42 P913/TOAB1OFF/INTP16/A13 (HS) Note When CSI-HS (CSIF3) is used : connect to H/S (input) pin of the programmer When CSI-HS (CSIF3) is not used : pull-down 43 P75/ANI5 - 44 P74/ANI4 - 45 P73/ANI3 - 46 P72/ANI2 - 47 P71/ANI1 - 48 P70/ANI0 - Note Note Independently connect toVSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1311 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-7. Wiring Example of V850ES/JC3-H (48 pin) Flash Writing Adapter (In CSIF0 + HS Mode) (1/2) VD D G D ND N D VD G 36 37 35 25 30 Note 2 24 Note 4 40 Note 1 20 V850ES/JC3-H 48 pin 45 Connect this pin to GND. 15 Connect this pin to VDD. 48 13 Note 3 5 10 12 D N G D VD D VD D N G 4.7 F 1 RFU-3 SI R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 SO SCK RFU-2 RFU-1 VDE CLKOUT /RESET FLMD1 FLMD0 VPP RESERVE/HS Page 1312 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-7. Wiring Example of V850ES/JC3-H (48 pin) Flash Writing Adapter (In CSIF0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIF3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTC0 is used. Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with the handling of unused pins (see 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins). 2. This adapter is for the 100-pin plastic LQFP package. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1313 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-8. Wiring of V850ES/JE3-H Flash Writing Adapters (1/3) Pin No. Pin Name Recommended Connection 1 AVREF0 Connect to VDD pin of the programmer 2 AVSS Connect to GND pin of the programmer 3 P10/ANO0 - 4 AVREF1 Connect to VDD pin of the programmer 5 VDD Connect to VDD pin of the programmer 6 REGC Connect the REGC pin to GND via 4.7 F capacitor 7 VSS Connect to GND pin of the programmer 8 X1 Connect to 3 to 6 MHz Resonator 9 X2 Connect to 3 to 6 MHz Resonator 10 RESET Connect to RESET (output) pin of the programmer 11 XT1 Connect to GND pin of the programmer 12 XT2 - 13 P60/TOAB1T1/TOAB11/TIAB11 - 14 P61/TOAB1B1/TIAB10/TOAB10 - 15 P62/TOAB1T2/TOAB12/TIAB12 - 16 P63/TOAB1B2/TRGAB1 - 17 P64/TOAB1T3/TOAB13/TIAB13 - 18 P65/TOAB1B3/EVTAB1 Connect to GND pin of the programmer 19 P02/NMI - 20 P03/INTP02/ADTRG/UCLK - 21 UDMF - 22 UDPF - 23 UVDD Connect to VDD pin of the programmer 24 EVDD Connect to VDD pin of the programmer 25 VSS Connect to GND pin of the programmer 26 P34/TIAA10/TOAA10/TOAA1OFF/INTP09 27 P36/TXDC3/SCL00/CTXD0 Note2 28 P37/RXDC3/SDA00/CRXD0 29 P30/TXDC0/SOF4/INTP07 Note2 When UART (UARTC0) is used : connect to RxD (input) pin of the programmer When UART (UARTC0) is not used : pull-down 30 P31/RXDC0/SIF4/INTP08 Note1 When UART (UARTC0) is used : connect to TxD (output) pin of the programmer When UART (UARTC0) is not used : pull-down Note1 31 P32/ASCKC0/SCKF4/TIAA00/TOAA00 - 32 P40/SIF0/TXDC4/SDA01 When CSI (CSIF0) is used : connect to SO (output) pin of the programmer When CSI (CSIF0)is not used : pull-down Note Notes1. Independently connect to VSS or VDD via a resistor. 2. PD70F3825 only R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1314 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-8. Wiring of V850ES/JE3-H Flash Writing Adapters (2/3) Pin No. 33 Pin Name P41/SOF0/RXDC4/SCL01 Recommended Connection When CSI (CSIF0)is used : connect to SI (input) pin of the programmer When CSI (CSIF0)is not used : pull-down 34 P42/SCKF0/INTP10 Note When CSI(CSIF0)is used : connect to SCK (output) pin of the programmer When CSI (CSIF0)is not used : pull-down 35 P33/TIAA01/TOAA01/RTCDIV/RTCCL - 36 P35/TIAA11/TOAA11/RTC1HZ - 37 P52/KR2/RTP02/DDI - 38 P53/SIF2/KR3/RTP03/DDO - 39 P54/SOF2/KR4/RTP04/DCK - Note 40 P55/SCKF2/KR5/RTP05/DMS - 41 P56/INTP05/DRST - 42 FLMD0 Connect to FLMD0 (output) pin of the programmer 43 VSS Connect to GND pin of the programmer 44 EVDD Connect to VDD pin of the programmer 45 P96/TIAA21/TOAA21/INTP11 - 46 P97/SIF1/TIAA20/TOAA20 - 47 P92/TENC01/TIT01/TOT01 - 48 P93/TECR0/TIT00/TOT00 - 49 PDL5/FLMD1 Connect to FLMD1 (output) pin of the programmer 50 P94/ TENC00/EVTT00 - 51 P910/SIF3/TXDC2/INTP14 When CSI (CSIF3) is used : connect to SO (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 52 P911/SOF3/RXDC2/INTP15 Note When CSI (CSIF3) is used : connect to SI (input) pin of the programmer When CSI (CSIF3) is not used : pull-down 53 P912/SCKF3 Note When CSI (CSIF3) is used : connect to SCK (output) pin of the programmer When CSI (CSIF3) is not used : pull-down 54 P913/TOAB1OFF/INTP16 (HS) Note When CSI-HS (CSIF3) is used : connect to H/S (input) pin of the programmer When CSI-HS (CSIF3) is not used : pull-down Note Note Independently connect to VSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1315 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-8. Wiring of V850ES/JE3-H Flash Writing Adapters (3/3) Pin No. Pin Name Recommended Connection 55 P79/ANI9 - 56 P78/ANI8 - 57 P77/ANI7 - 58 P76/ANI6 - 59 P75/ANI5 - 60 P74/ANI4 - 61 P73/ANI3 - 62 P72/ANI2 - 63 P71/ANI1 - 64 P70/ANI0 - Note Independently connect to VSS or VDD via a resistor. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1316 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-8. Wiring Example of V850ES/JE3-H Flash Writing Adapter (In CSIF0 + HS Mode) (1/2) D VD D N G D VD D N G 48 49 45 40 35 33 Note 2 32 50 30 Note 4 Note 1 55 V850ES/JE3-H 25 60 20 Connect this pin to GND. Connect this pin to VDD. 64 17 Note 3 5 10 15 16 D N G D VD D N G 4.7 F 1 RFU-3 SI R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 SO SCK RFU-2 RFU-1 VDE CLKOUT /RESET D VD FLMD1 FLMD0 VPP RESERVE/HS Page 1317 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Figure 30-8. Wiring Example of V850ES/JE3-H Flash Writing Adapter (In CSIF0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIF3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTC0 is used. Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with the handling of unused pins (see 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins). 2. This adapter is for the 128-pin plastic LQFP package. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1318 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 30-9. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? No Yes End R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1319 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4.4 Selection of communication mode In the V850ES/JC3-H and V850ES/JE3-H, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 30-10. Selection of Communication Mode VDD VDD VSS VDD RESET (input) VSS VDD FLMD1 (input) VSS VDD FLMD0 (input) VSS (Note) VDD RXDC0 (input) VSS VDD TXDC0 (output) Oscillation stabilized VSS Power on Communication mode selected Flash control command communication (erasure, write, etc.) Reset released Note The number of clocks is as follows depending on the communication mode. FLMD0 Pulse Communication Mode Remarks 0 UARTC0 Communication rate: 9,600 bps (after reset), LSB first 8 CSIF0 V850ES/Jx3-H performs slave operation, MSB first 9 CSIF3 V850ES/Jx3-H performs slave operation, MSB first 11 CSIF0 + HS V850ES/Jx3-H performs slave operation, MSB first 12 CSIF3 + HS V850ES/Jx3-H performs slave operation, MSB first Other RFU Setting prohibited Caution When UARTC0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1320 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4.5 Communication commands The V850ES/JC3-H and V850ES/JE3-H communicate with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/JC3-H and V850ES/JE3-H are called "commands". The response signals sent from the V850ES/JC3-H and V850ES/JE3-H to the dedicated flash programmer are called "response commands". Figure 30-11. Communication Commands Command Response command Dedicated flash programmer V850ES/JC3-H, V850ES/JE3-H The following shows the commands for flash memory control in the V850ES/JC3-H and V850ES/JE3-H. All of these commands are issued from the dedicated flash programmer, and the V850ES/JC3-H and V850ES/JE3-H perform the processing corresponding to the commands. Table 30-9. Flash Memory Control Commands Classification Blank check Command Name Support Function CSIF0, CSIF0 + HS, CSIF3 CSIF3 + HS Checks if the contents of the memory in the Chip erase command Erases the contents of the entire memory. Block erase command Erases the contents of the memory of the Block blank check UARTC0 command Erase specified block have been correctly erased. specified block. Write Program command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash programmer. Checksum command Reads the checksum in the specified address range. System setting, Silicon signature control command Security setting command Reads silicon signature information. Prohibits the chip erase command, block erase command, program command, read command, and boot area rewrite. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1321 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS level to the FLMD0 pin. In the flash memory programming mode, supply a write voltage of VDD level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 30.5.5 (1) FLMD0 pin. Figure 30-12. FLMD0 Pin Connection Example V850ES/JC3-H and V850ES/JE3-H Dedicated flash programmer connection pin FLMD0 Pull-down resistor (RFLMD0) (2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 30-13. FLMD1 Pin Connection Example V850ES/JC3-H and V850ES/JE3-H FLMD1 Other device Pull-down resistor (RFLMD1) Caution If the VDD signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1322 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY Table 30-10. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 FLMD1 0 Don't care VDD 0 VDD VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface. Table 30-11. Pins Used by Serial Interfaces Serial Interface Pins Used UARTC0 TXDC0, RXDC0 CSIF0 SOF0, SIF0, SCKF0 CSIF3 SOF3, SIF3, SCKF3 CSIF0 + HS SOF0, SIF0, SCKF0, P913 CSIF3 + HS SOF3, SIF3, SCKF3, P913 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device onboard, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 30-14. Conflict of Signals (Serial Interface Input Pin) V850ES/JC3-H and V850ES/JE3-H Conflict of signals Dedicated flash programmer connection pins Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1323 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 30-15. Malfunction of Other Device V850ES/JC3-H and V850ES/JE3-H Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal that the V850ES/JC3-H and V850ES/JE3-H output affects the other device, isolate the signal on the other device side. V850ES/JC3-H and V850ES/JE3-H Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal that the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1324 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 30-16. Conflict of Signals (RESET Pin) V850ES/JC3-H and V850ES/JE3-H Conflict of signals Dedicated flash programmer connection pin RESET Reset signal generator Output pin In the flash memory programming mode, the signal that the reset signal generator outputs conflicts with the signal that the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. (5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. (6) Other signal pins Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode. During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level. (7) Power supply Supply the same power (VDD, VSS, EVDD, UVDD, AVREF0, AVREF1, AVSS) as in normal operation mode. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1325 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.5 Rewriting by Self Programming 30.5.1 Overview The V850ES/JC3-H and V850ES/JE3-H support a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant dataNote can be rewritten in the field. Note Be sure not to allocate the program code to the block where the constant data of rewriting target is allocated. See 30.2 Memory Configuration for the block configuration. Figure 30-17. Concept of Self Programming Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1326 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.5.2 Features (1) Secure self programming (boot swap function) The V850ES/JC3-H and V850ES/JE3-H support a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. By writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 to 15. Figure 30-18. Rewriting Entire Memory Area (Boot Swap) Last block Last block Last block : : : Block 32 Block 32 Block 31 Block 31 Block 31 : : : Block 17 Block 17 Block 16 Block 16 Block 15 Block 15 Block 15 : : : Block 1 Block 1 Block 1 Block 0 Block 0 Block 0 Block 17 Block 16 Rewriting blocks 16 to 31 Boot swap Block 32 (2) Interrupt support Instructions cannot be fetched from the flash memory during self-programming. Consequently, a user handler written to the flash memory could not be used even if an interrupt has occurred. Therefore, in the V850ES/JC3-H and V850ES/JE3-H, to use an interrupt during self-programming, processing transits to the specific addressNote in the internal RAM. Allocate the jump instruction that transits processing to the user interrupt servicing at the specific addressNote in the internal RAM. Note NMI interrupt: Start address of internal RAM Maskable interrupt: Start address of internal RAM + 4 addresses R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1327 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 30-19. Standard Self Programming Flow Flash memory manipulation Flash environment initialization processing * Disable accessing flash area * Disable stopping clock * Disable setting of an standby mode other than the HALT mode * Disable DMA transfer Erase processing Write processing Internal verify processing All blocks end? No Yes Flash environment end processing End of processing R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1328 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.5.4 Flash functions Table 30-12. Flash Function List Function Name Outline Support FlashInit Self-programming library initialization FlashEnv Flash environment start/end FlashFLMDCheck FLMD pin check FlashStatusCheck Hardware processing execution status check FlashBlockErase Block erase FlashWordWrite Data write FlashBlockIVerify Internal verification of block FlashBlockBlankCheck Blank check of block FlashSetInfo Flash information setting FlashGetInfo Flash information acquisition FlashBootSwap Boot swap execution 30.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0 V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD level to the FLMD0 pin during the self programming mode period via port control before the memory is rewritten. When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V. Figure 30-20. Mode Change Timing RESET signal VDD 0V Self programming mode VDD FLMD0 pin 0V Normal operation mode Caution Normal operation mode Make sure that the FLMD0 pin is at 0 V when reset is released. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1329 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 30-13. Internal Resources Used Resource Name Description An extension of the stack used by the user is used by the library (can be used in both the Stack area internal RAM and external RAM). Library code Note Program entity of library (can be used anywhere other than the flash memory block to be manipulated). Application program Executed as user application. Calls flash functions. Maskable interrupt Can be used in the user application execution status or self-programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal RAM start address + 4 addresses in advance. NMI interrupt Can be used in the user application execution status or self-programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal RAM start address in advance. Note About resources used, refer to the Flash Memory Self-Programming Library User's Manual. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1330 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 30 FLASH MEMORY 30.6 Creating ROM code to place order for previously written product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). The HCU is a software tool that includes functions required for creating ROM code. The HCU can be downloaded at the Renesas Electronics website. (1) Website http://www2.renesas.com/micro/en/ods/ Click Version-up Service. (2) Downloading the HCU To download the HCU, click Software for previously written flash products and then HCU_GUI. Remark For details about how to install and use the HCU, see the materials (the user's manual) that comes with the HCU at the above website. 30.6.1 Procedure for using ROM code to place an order Use the HCU to create the ROM code by following the procedure below, and then place your order with Renesas Electronics. For details, see the ROM Code Ordering Method Information (C10302J). Customer Renesas Electronics Decide which product to order. Send the order information. Renesas Electronics processes the product name and number and creates a record of the transaction. Create the ROM codeNote Check the ROM order details and generate the required data. Renesas Electronics sends the order number and other order-related information. Send the data required for the ROM order. Renesas Electronics processes the ROM code. Note Use the HCU to create the ROM code for the order. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1331 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H CHAPTER 31 ON-CHIP DEBUG FUNCTION The on-chip debug function of the V850ES/JC3-H and V850ES/JE3-H can be implemented by the following two methods. * Using the DCU (debug control unit) On-chip debug function is implemented by the on-chip DCU in the V850ES/JC3-H and V850ES/JE3-H, with using the DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins. * Not using the DCU On-chip debug function is implemented by MINICUBE2 or the like, using the user resources, instead of the DCU. The following table shows the features of the two on-chip debug functions. Table 31-1. On-Chip Debug Function Features Debugging Using DCU Debug interface pins DRST, DCK, DMS, DDI, DDO Debugging Without Using DCU * When UARTC0 is used RXDC0, TXDC0 * When CSIF0 is used SIF0, SOF0, SCKF0, HS (P913) * When CSIF3 is used SIF3, SOF3, SCKF3, HS (P913) Securement of user resources Not required Required Hardware break function 2 points 2 points Software break Internal ROM area 4 points 4 points function 2000 points 2000 points Available Available Available Available Reset, NMI, INTWDT2, HLDRQ, RESET pin Internal RAM area Real-time RAM monitor function Note 1 Dynamic memory modification (DMM) function Note 2 Mask function WAIT ROM security function 10-byte ID code authentication 10-byte ID code authentication Hardware used MINICUBE, etc. MINICUBE2, etc. Trace function Not supported. Not supported. Debug interrupt interface function Not supported. Not supported. (DBINT) Notes 1. This is a function which reads out memory contents during program execution. 2. This is a function which rewrites RAM contents during program execution. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1332 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.1 Debugging with DCU Programs can be debugged using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip debug emulator (MINICUBE). 31.1.1 Connection circuit example Figure 31-1. Circuit Connection Example When Debug Interface Pins Are Used for Communication Interface VDD EVDD STATUS DCK DCK DMS DMS DDI DDI DDO DDO POWER TARGET Note 1 DRST DRSTNote 2 RESET RESET FLMD0 FLMD0Note 3 FLMD1/PDL5 GND MINICUBE VSS V850ES/JC3-H, V850ES/JE3-H Notes 1. Example of pin connection when MINICUBE is not connected 2. A pull-down resistor is provided on chip. 3. For flash memory rewriting 31.1.2 Interface signals The interface signals are described below. (1) DRST This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously initializes the debug control unit. MINICUBE raises the DRST signal when it detects VDD of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. When the DRST signal goes high, a reset signal is also generated in the CPU. When starting debugging by starting the integrated debugger, a CPU reset is always generated. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1333 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 31 ON-CHIP DEBUG FUNCTION (2) DCK This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge. (3) DMS This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the DMS signal. (4) DDI This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK. (5) DDO This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal. (6) EVDD This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the signals output from MINICUBE (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a high-impedance state. (7) FLMD0 The flash self programming function is used for the function to download data to the flash memory via the integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a pulldown resistor to the FLMD0 pin. The FLMD0 pin can be controlled in either of the following two ways. <1> To control from MINICUBE Connect the FLMD0 signal of MINICUBE to the FLMD0 pin. In the normal mode, nothing is driven by MINICUBE (high impedance). During a break, MINICUBE raises the FLMD0 pin to the high level when the download function of the integrated debugger is executed. <2> To control from port Connect any port of the device to the FLMD0 pin. The same port as the one used by the user program to realize the flash self programming function may be used. On the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. For details, refer to the ID850QB Ver. 3.40 Integrated Debugger Operation User's Manual (U18604E). (8) RESET This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM0 bit of the OCDM register set by the user program, on-chip debugging cannot be executed. Therefore, reset is effected by MINICUBE, using the RESET pin, to make the DRST pin valid (initialization). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1334 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.1.3 Maskable functions Reset, NMI, INTWDT2 signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JC3-H and V850ES/JE3-H functions are listed below. Table 31-2. Maskable Functions Maskable Functions with ID850QB Corresponding V850ES/JC3-H and V850ES/JE3-H Functions NMI NMI pin input RESET Reset signal generation by RESET pin input, low-voltage detector, clock monitor, or watchdog timer (WDT2) overflow 31.1.4 Register (1) On-chip debug mode register (OCDM) The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a special register and can be written only in a combination of specific sequences (see 3.4.8 Special registers). This register is also used to specify whether a pin provided with an on-chip debug function is used as an on-chip debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-down resistor of the P56/INTP05/DRST pin. The OCDM register can be written only while a low level is input to the DRST pin. This register can be read or written in 8-bit or 1-bit units. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1335 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H After reset: 01HNote R/W Address: FFFFF9FCH < > OCDM 0 0 0 0 0 0 0 OCDM0 OCDM0 Operation mode 0 Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P56/INTP05/DRST pin. 1 When DRST pin is low: Normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) When DRST pin is high: On-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) Note RESET input sets this register to 01H. After reset by the WDT2RES signal, clock monitor (CLM), or lowvoltage detector (LVI), however, the value of the OCDM register is retained. Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins after external reset, any of the following actions must be taken. * Input a low level to the P56/INTP05/DRST pin. * Set the OCDM0 bit. In this case, take the following actions. <1> Clear the OCDM0 bit to 0. <2> Fix the P56/INTP05/DRST pin to low level until <1> is completed. 2. The DRST pin has an on-chip pull-down resistor. This resistor is disconnected when the OCDM0 flag is set to 0. DRST OCDM0 flag (1: Pull-down ON, 0: Pull-down OFF) 10 to 100 k (30 k (TYP.)) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1336 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag 0 1 L Invalid Invalid H Invalid Valid DRST Pin Remark L: Low-level input H: High-level input Figure 31-2. Timing When On-Chip Debug Function Is Not Used Releasing reset RESET Clearing OCDM0 bit OCDM0 P56/INTP05/DRST Low-level input After OCDM0 bit is cleared, high level can be input/output. 31.1.6 Cautions (1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction. (2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is input from a pin. (3) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset is generated as soon as the flash memory is rewritten by DMM or read by the RAM monitor function while the user program is being executed, the CPU and peripheral I/O may not be correctly reset. (4) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1337 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.2 Debugging Without Using DCU The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTC0 (RXDC0 and TXDC0), pins for CSIF0 (SIF0, SOF0, SCKF0, and HS (P913)), or pins for CSIF3 (SIF3, SOF3, SCKF3, and HS (P913)) as debug interfaces, without using the DCU. 31.2.1 Circuit connection examples Figure 31-3. Circuit Connection Example When UARTC0/CSIF0/CSIF3 Is Used for Communication Interface VDD VDD VDD VDD 1 to 10 k 3 to 10 k VSS GND RESET_OUT RESET RXD/SINote 1 TXDC0/SOF0/SOF3 VDD VDD TXD/SONote 1 RXDC0/SIF0/SIF3 SCK SCKF0/SCKF3 HS M IN IC U B E 2 HS (P913) CLKNote 2 1 to 10 k 1 to 10 k FLMD1Note 3 FLMD1 FLMD0Note 3 FLMD0 1 to 10 k RESET_INNote 4 10 k 100 Note 5 Port X VDD QB-MINI2 V850ES/JC3-H, V850ES/JE3-H 10 k 1 k RESET signal Notes 1. 2. 3. 4. 5. Remark Reset circuit Connect TXDC0/SOF0/SOF3 (transmit side) of the V850ES/JC3-H or V850ES/JE3-H to RXD/SI (receive side) of the target connector, and TXD/SO (transmit side) of the target connector to RXDC0/SIF0/SIF3 (receive side) of the V850ES/JC3-H or V850ES/JE3-H. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For details, refer to CHAPTER 30 FLASH MEMORY. Because this pin is an (unused) input during debugging, its alternate function can be used. Note that, within MINICUBE2, a 100 k pull-down resistor is connected. This connection is designed assuming that the RESET signal is output from the N-ch open-drain buffer (output resistance: 100 or less). The circuit enclosed by a dashed line is designed for flash self programming, which controls the FLMD0 pin via ports. Use the port for inputting or outputting the high level. When flash self programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 k. Refer to Table 31-3 for pins used when UARTC0, CSIF0, or CSIF3 is used for communication interface. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1338 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H Table 31-3. Wiring Between V850ES/JC3-H (40 pin) and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIF0-HS Pin Name Pin With CSIF3-HS Pin Name No. SI/RxD Input Pin to receive commands and data from Pin With UARTC0 Pin Name No. Pin No. P41/SOF0 21 P911/SOF3 33 P30/TXDC0 17 P40/SIF0 20 P910/SIF3 32 P31/RXDC0 18 P42/SCKF0 22 P912/SCKF3 34 Not needed - Not - Not - Not - V850ES/JC3-H SO/TxD Output Pin to transmit commands and data to V850ES/JC3-H SCK Output Clock output pin for 3-wire serial communication CLK Note Output Clock output pin to V850ES/JC3-H needed Note needed Note Note needed RESET_OUT Output Reset output pin to V850ES/JC3-H RESET 8 RESET 8 RESET 8 FLMD0 Output pin to set V850ES/JC3-H to FLMD0 28 FLMD0 28 FLMD0 28 Output debug mode or programming mode FLMD1 Output Output pin to set programming mode PDL5/FLMD1 31 PDL5/FLMD1 31 PDL5/FLMD1 31 HS Input Handshake signal for CSI0 + HS P913 35 P913 35 Not needed - VSS 5 VSS 5 VSS 5 AVSS 2 AVSS 2 AVSS 2 communication - GND RESET_IN Input Ground Reset input pin on the target system Note It is used as the clock output of the flash programmer for MINICUBE2. For details, refer to CHAPTER 30 FLASH MEMORY. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1339 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H Table 31-4. Wiring Between V850ES/JC3-H (48 pin) and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIF0-HS Pin Name Pin With CSIF3-HS Pin Name Input Pin to receive commands and data from Pin Name Pin No. No. No. SI/RxD Pin With UARTC0 P41/SOF0 25 P911/SOF3 40 P30/TXDC0 21 P40/SIF0 24 P910/SIF3 39 P31/RXDC0 22 P42/SCKF0 26 P912/SCKF3 41 Not needed - Not - Not - Not - V850ES/JC3-H SO/TxD Output Pin to transmit commands and data to V850ES/JC3-H SCK Output Clock output pin for 3-wire serial communication CLK Note Output Clock output pin to V850ES/JC3-H needed Note needed Note Note needed RESET_OUT Output Reset output pin to V850ES/JC3-H RESET 10 RESET 10 RESET 10 FLMD0 Output pin to set V850ES/JC3-H to FLMD0 32 FLMD0 32 FLMD0 32 Output debug mode or programming mode FLMD1 Output Output pin to set programming mode PDL5/FLMD1 37 PDL5/FLMD1 37 PDL5/FLMD1 37 HS Input Handshake signal for CSI0 + HS P913 42 P913 42 Not needed - VSS 7 VSS 7 VSS 7 AVSS 2 AVSS 2 AVSS 2 communication - GND RESET_IN Input Ground Reset input pin on the target system Note It is used as the clock output of the flash programmer for MINICUBE2. For details, refer to CHAPTER 30 FLASH MEMORY. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1340 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H Table 31-5. Wiring Between V850ES/JE3-H and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) Signal Name I/O Pin Function With CSIF0-HS Pin Name Pin With CSIF3-HS Pin Name Input Pin to receive commands and data from Pin Name Pin No. No. No. SI/RXD Pin With UARTC0 P41/SOF0 33 P911/SOF3 52 P30/TXDC0 29 P40/SIF0 32 P910/SIF3 51 P31/RXDC0 30 P42/SCKF0 34 P912/SCKF3 53 Not needed - Not - Not - Not - V850ES/JE3-H SO/TXD Output Pin to transmit commands and data to V850ES/JE3-H SCK Output Clock output pin for 3-wire serial communication CLK Note Output Clock output pin to V850ES/JE3-H needed Note needed Note needed Note RESET_OUT Output Reset output pin to V850ES/JE3-H RESET 10 RESET 10 RESET 10 FLMD0 Output pin to set V850ES/JE3-H to FLMD0 42 FLMD0 42 FLMD0 42 Output debug mode or programming mode FLMD1 Output Output pin to set programming mode PDL5/FLMD1 49 PDL5/FLMD1 49 PDL5/FLMD1 49 HS Input Handshake signal for CSI0 + HS P913 54 P913 54 Not needed - VSS 7 VSS 7 VSS 7 AVSS 2 AVSS 2 AVSS 2 communication - GND RESET_IN Input Ground Reset input pin on the target system Note It is used as the clock output of the flash programmer for MINICUBE2. For details, refer to CHAPTER 30 FLASH MEMORY. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1341 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.2.2 Maskable functions Only reset signals can be masked. The functions that can be masked in the debugger (ID850QB) and the corresponding functions of the V850ES/JC3-H and V850ES/JE3-H are listed below. Table 31-6. Maskable Functions Functions Maskable in ID850QB Corresponding Functions of V850ES/JC3-H and V850ES/JE3-H NMI - STOP - HOLD - RESET WAIT R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Reset signal generation by RESET pin input - Page 1342 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.2.3 Securement of user resources The user must prepare the following to perform communication between MINICUBE2 and the target device and implement each debug function. These items need to be set in the user program or using the compiler options. (1) Securement of memory space The shaded portions in Figure 31-4 are the areas reserved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces. These spaces must be secured so as not to be used by the user program. (2) Security ID setting The ID code must be embedded in the area between 0000070H and 0000079H in Figure 31-4, to prevent the memory from being read by an unauthorized person. For details, refer to 31.3 ROM Security Function. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1343 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H Figure 31-4. Memory Spaces Where Debug Monitor Programs Are Allocated Internal RAM Internal ROM 3FFEFFFH 3FFEFF0H Note 1 (16 bytes) (2 KB) Internal RAM area Note 3 0000400HNote 2 0000070H CSI0/UART receive interrupt vector (4 bytes) Access-prohibited area Internal ROM area Security ID area (10 bytes) 0000060H Interrupt vector for debugging (4 bytes) 0000000H Reset vector (4 bytes) : Debugging area Notes 1. Address values vary depending on the product. Internal ROM Size Address Value 16 KB 00037FFH to 0003FFFH PD70F3809, 70F3814, 70F3820 PD70F3810, 70F3815, 70F3821 32 KB 00077FFH to 0007FFFH PD70F3811, 70F3816, 70F3822 64 KB 000F7FFH to 000FFFFH PD70F3812, 70F3817, 70F3823 128 KB 001F7FFH to 001FFFFH PD70F3813, 70F3818, 70F3819, 256 KB 003F7FFH to 003FFFFH 70F3824,70F3825 2. This is the address when CSIF0 is used. It starts at 0000406H when CSIF3 is used, and at 00004A0H when UARTC0 is used. 3. Address values vary depending on the product. Internal RAM Size Address Value PD70F3809, 70F3814, 70F3820 8 KB 3FFD000H PD70F3810, 70F3815, 70F3821 16 KB 3FFB000H PD70F3811, 70F3816, 70F3822 24 KB 3FF9000H PD70F3812, 70F3813, 70F3817, 70F3818, 70F3819, 70F3823, 70F3824, 70F3825 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1344 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H (3) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases. If the rewritten pattern does not match the following cases, the debugger generates an error (F0C34 when using the ID850QB). (a) When two nop instructions are placed in succession from address 0 Before rewriting 0x0 nop 0x2 nop After rewriting Jumps to debug monitor program at 0x0 0x4 xxxx 0x4 xxxx (b) When two 0xFFFF are successively placed from address 0 (already erased device) Before rewriting 0x0 0xFFFF 0x2 0xFFFF After rewriting Jumps to debug monitor program at 0x0 0x4 xxxx 0x4 xxxx (c) The jr instruction is placed at address 0 (when using CA850) Before rewriting 0x0 jr disp22 After rewriting Jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using IAR compiler ICCV850) Before rewriting After rewriting 0x0 mov imm32,reg1 Jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) The jump instruction for the debug monitor program is placed at address 0 Before rewriting Jumps to debug monitor program at 0x0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 After rewriting No change Page 1345 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H (4) Securement of area for debug monitor program The shaded portions in Figure 31-4 are the areas where the debug monitor program is allocated. The monitor program performs initialization processing for debug communication interface and RUN or break processing for the CPU. The internal ROM area must be filled with 0xFF. This area must not be rewritten by the user program. [How to secure areas] It is not necessarily required to secure this area if the user program does not use this area. To avoid problems that may occur during the debugger startup, however, it is recommended to secure this area in advance, using the compiler. The following shows examples for securing the area, using the Renesas Electronics compiler CA850. Add the assemble source file and link directive code, as shown below. * Assemble source (Add the following code as an assemble source file.) -- Secures 2 KB space for monitor ROM section .section "MonitorROM", const .space 0x800, 0xff -- Secures interrupt vector for debugging .section "DBG0" .space 4, 0xff -- Secures interrupt vector for serial communication -- Change the section name according to the serial communication mode used .section "INTCF0R" .space 4, 0xff -- Secures 16-byte space for monitor RAM section .section "MonitorRAM", bss .lcomm monitorramsym, 16, 4 -- defines symbol monitorramsym * Link directive (Add the following code to the link directive file.) The following shows an example when the internal ROM has 512 KB (end address is 007FFFFH) and internal RAM has 56 KB (end address is 3FFEFFFH). MROMSEG : !LOAD ?R V0x07f800{ MonitorROM = $PROGBITS ?A MonitorROM; }; MRAMSEG : !LOAD ?RW V0x03ffeff0{ MonitorRAM = $NOBITS ?AW MonitorRAM; }; R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1346 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H (5) Securement of communication serial interface UARTC0, CSIF0, or CSIF3 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur. To prevent such a problem from occurring, communication serial interface must be secured in the user program. [How to secure communication serial interface] * On-chip debug mode register (OCDM) For the on-chip debug function using the UARTC0, CSIF0, or CSIF3, set the OCDM register functions to normal mode. Be sure to set as follows. * Input low level to the P56/INTP05/DRST pin. * Set the OCDM0 bit as shown below. <1> Clear the OCDM0 bit to 0. <2> Fix the P56/INTP05/DRST pin input to low level until the processing of <1> is complete. * Serial interface registers Do not set the registers related to CSIF0, CSIF3, or UARTC0 in the user program. * Interrupt mask register When CSIF0 is used, do not mask the transfer end interrupt (INTCF0R). When CSIF3 is used, do not mask the transfer end interrupt (INTCF3R). When UARTC0 is used, do not mask the reception completion interrupt (INTUC0R). (a) When CSIF0 is used CF0RIC 7 6 5 4 3 2 1 0 x 0 x x x x x x (b) When CSIF3 is used CF3RIC 7 6 5 4 3 2 1 0 x 0 x x x x x x (C) When UARTC0 is used UC0RIC Remark 7 6 5 4 3 2 1 0 x 0 x x x x x x x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1347 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H * Port registers when UARTC0 is used When UARTC0 is used, port registers are set to make the TXDC0 and RXDC0 pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.) 7 6 5 4 3 2 1 0 PFC3 x x x x x x 0 0 7 6 5 4 3 2 1 0 PFCE3 x x x x x x 0 0 7 6 5 4 3 2 1 0 PMC3 x x x x x x 1 1 Remark x: don't care * Port registers when CSIF0 is used When CSIF0 is used, port registers are set to make the SIF0, SOF0, SCKF0, and HS (P913) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.) (a) SIF0, SOF0, and SCKF0 settings 7 6 5 4 3 2 1 0 PMC4 x x x x x 1 1 1 7 6 5 4 3 2 1 0 PFC4 x x x x x 0 0 0 7 6 5 4 3 2 1 0 PFCE4 x x x x x x 0 0 15 14 13 12 11 10 9 8 x x 0 x x x x x 15 14 13 12 11 10 9 8 x x Note x x x x x (b) HS (P913 pin) settings PM9H P9H Note Writing to this bit is prohibited. The port values corresponding to the HS pin are changed by the monitor program according to the debugger status. To perform port register settings in 8-bit units, the user program can usually use read-modify-write. If an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. Remark x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1348 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H * Port registers when CSIF3 is used When CSIF3 is used for communication, port registers are set to make the SIF3, SOF3, SCKF3, and HS (P913) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.) (a) SIF3, SOF3, and SCKF3 settings PMC9H PFC9H PFCE9H 15 14 13 12 11 10 9 8 x x x 1 1 1 x x 15 14 13 12 11 10 9 8 x x x 0 0 0 x x 15 14 13 12 11 10 9 8 x x x x 0 0 x x 15 14 13 12 11 10 9 8 x x 0 x x x x x 15 14 13 12 11 10 9 8 x x Note2 x x x x x Note1 (b) HS (P913 pin) settings PM9H P9H Notes1. V850ES/JE3-H only 2. Writing to this bit is prohibited. The port values corresponding to the HS pin are changed by the monitor program according to the debugger status. To perform port register settings in 8-bit units, the user program can usually use read-modify-write. If an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. Remark x: don't care R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1349 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.2.4 Cautions (1) Handling of device that was used for debugging Do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed. Moreover, do not embed the debug monitor program into mass-produced products. (2) When breaks cannot be executed Forced breaks cannot be executed if one of the following conditions is satisfied. * Interrupts are disabled (DI) * Interrupts issued for the serial interface, which is used for communication between MINICUBE2 and the target device, are masked * Standby mode is entered while standby release by a maskable interrupt is prohibited * Mode for communication between MINICUBE2 and the target device is UARTC0, and the main clock has been stopped (3) When pseudo real-time RAM monitor (RRM) function and DMM function do not operate The pseudo RRM function and DMM function do not operate if one of the following conditions is satisfied. * Interrupts are disabled (DI) * Interrupts issued for the serial interface, which is used for communication between MINICUBE2 and the target device, are masked * Standby mode is entered while standby release by a maskable interrupt is prohibited * Mode for communication between MINICUBE2 and the target device is UARTC0, and the main clock has been stopped * Mode for communication between MINICUBE2 and the target device is UARTC0, and a clock different from the one specified in the debugger is used for communication (4) Standby release with pseudo RRM and DMM functions enabled The standby mode is released by the pseudo RRM function and DMM function if one of the following conditions is satisfied. * Mode for communication between MINICUBE2 and the target device is CSIF0 or CSIF3 * Mode for communication between MINICUBE2 and the target device is UARTC0, and the main clock has been supplied. (5) Rewriting to peripheral I/O registers that requires a specific sequence, using DMM function Peripheral I/O registers that requires a specific sequence cannot be rewritten with the DMM function. (6) Flash self programming If a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1350 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.3 ROM Security Function 31.3.1 Security ID The flash memory versions of the V850ES/JC3-H and V850ES/JE3-H perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the onchip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication. If the IDs match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. * Set the 10-byte ID code to 0000070H to 0000079H. * Bit 7 of 0000079H is the on-chip debug emulator enable flag. (0: Disable, 1: Enable) * When the on-chip debug emulator is started, the debugger requests ID input. When the ID code input on the debugger and the ID code set in 0000070H to 0000079H match, the debugger starts. * Debugging cannot be performed if the on-chip debug emulator enable flag is 0, even if the ID codes match. Figure 31-5. Security ID Area 0000079H Security ID (10 bytes) 0000070H 0000000H Caution After the flash memory is erased, 1 is written to the entire area. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1351 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H 31.3.2 Setting The following shows how to set the ID code as shown in Table 31-6. When the ID code is set as shown in Table 31-6, the ID code input in the configuration dialog box of the ID850QB is "123456789ABCDEF123D4" (the ID code is case-insensitive). Table 31-6. ID Code Address Value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9A 0x75 0xBC 0x76 0xDE 0x77 0XF1 0x78 0x23 0x79 0xD4 The ID code can be specified for the device file that supports CA850 Ver. 3.10 or later and the security ID using the PM+ compiler common option setting. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1352 of 1442 CHAPTER 31 ON-CHIP DEBUG FUNCTION V850ES/JC3-H, V850ES/JE3-H [Program example (when using CA850 Ver. 3.10 or later)] #-------------------------------------# SECURITYID #-------------------------------------.section "SECURITY_ID" --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1353 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.1 Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD VDD = EVDD = UVDD = AVREF0 = AVREF1 -0.5 to +4.6 V EVDD VDD = EVDD = UVDD = AVREF0 = AVREF1 -0.5 to +4.6 V UVDD VDD = EVDD = UVDD = AVREF0 = AVREF1 -0.5 to +4.6 V AVREF0 VDD = EVDD = UVDD = AVREF0 = AVREF1 -0.5 to +4.6 V AVREF1 VDD = EVDD = UVDD = AVREF0 = AVREF1 -0.5 to +4.6 V VSS VSS = AVSS -0.5 to +0.5 V AVSS VSS = AVSS -0.5 to +0.5 VI1 P60 to P65, P92 to P94, P96, P97, P910 to P913, PDL5, V -0.5 to EVDD + 0.5 Note 1 V RESET, FLMD0 VI2 VI3 VI4 UDMF, UDPF -0.5 to UVDD + 0.5 P10 -0.5 to AVREF1 + 0.5 X1, X2, XT1, XT2 -0.5 to VRO Note 2 Note 1 V Note 1 V Note V + 0.5 1 VI5 Analog input voltage VIAN P02, P03, P30 to P37, P40 to P42, P52 to P56 P70 to P79 -0.5 to +6.0 V -0.5 to AVREF0 + 0.5 Note 1 V Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage. Therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 2. On-chip regulator output voltage (2.5 V (TYP.)) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1354 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P02, P03, P30 to P37, P40 to P42, Per pin P52 to P56, P60 to P65, P92 to P94, Total of all pins P96, P97, P910 to P913, PDL5 UDMF, UDPF 8 mA Per pin 4 mA Total of all pins 4 mA Per pin 4 mA Total of all pins 20 mA P02, P03, P30 to P37, P40 to P42, Per pin -4 mA P52 to P56, P60 to P65, P92 to P94, Total of all pins -40 (V850ES/JC3-H) mA P70 to P79 -60 (V850ES/JE3-H) Per pin -4 mA Total of all pins -8 mA Per pin -4 mA Total of all pins -4 mA Per pin -4 mA Total of all pins -20 mA -40 to +85 C -40 to +85 C -40 to +125 C In normal operation In flash memory programming Storage temperature mA Total of all pins P10 TA 40 (V850ES/JC3-H) mA UDMF, UDPF temperature mA 60 (V850ES/JE3-H) P96, P97, P910 to P913, PDL5 Operating ambient 4 4 P70 to P79 IOH Unit Per pin P10 Output current, high Ratings Tstg Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage. Therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1355 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.2 Capacitance (TA = 25C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter I/O capacitance Symbol CIO Conditions MIN. TYP. fX = 1 MHz MAX. Unit 10 pF Measured pins returned to 0 V 32.3 Operating Conditions (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Internal System Clock Frequency Conditions Supply voltage VDD EVDD UVDD Unit AVREF0, AVREF1 fXX = 3 to 6 MHz (during clock- C = 4.7 F, through operation) A/D converter stopped, fXX = 24 to 48 MHz (during PLL D/A converter stopped, operation) USB stopped C = 4.7 F, 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 V 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 V A/D converter operating, D/A converter operating, USB operating fXT = 32.768 kHz C = 4.7 F, Note Note When the system is operating on the subclock (fXT = 32.768 kHz), the A/D converter, D/A converter, and USB controller do not operate. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1356 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.4 Oscillator Characteristics 32.4.1 Main clock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Resonator Ceramic Circuit Example X1 X2 Parameter Oscillation frequency MIN. TYP. 3 MAX. Unit 6 MHz Note 1 resonator/ (fX) crystal Oscillation resonator Conditions stabilization time After reset is released 16 2 /fX s Note 3 ms Note 3 s Note 2 After STOP mode is released After IDLE2 mode is released Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JC3-H and V850ES/JE3-H so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from start of oscillation until the resonator stabilizes. 3. The value varies depending on the setting of the OSTS register. Cautions 1. When using the USB controller, be sure to use a ceramic resonator or crystal resonator with an accuracy of 6 MHz 500 ppm or less when using the internal clock as the USB clock. When using the external clock input by the UCLK pin, be sure to supply a clock with an accuracy of 48 MHz 500 ppm or less. If the USB clock accuracy drops, the transmission/reception data cannot satisfy the USB specification. 2. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1357 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (1) KYOCERA KINSEKI CORPORATION: Crystal resonator Type Circuit Example Part Number Oscillation Recommended Circuit Oscillation Voltage Oscillation Frequency Constant Range Stabilization fX (MHz) Time C1 (pF) C2 (pF) Rd () MIN. (V) MAX. (V) Surface X1 X2 mounting MAX. (ms) CX49GFWB04000D0PPTZ1 4.000 10 10 1000 2.85 3.6 14.86 CX49GFWB05000D0PPTZ1 5.000 10 10 1000 2.85 3.6 13.98 CX49GFWB06000D0PPTZ1 6.000 10 10 1000 2.85 3.6 12.8 Rd C1 Caution C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/Jx3-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. (2) KYOCERA CORPORATION: Ceramic resonator Type Circuit Example Part Number Oscillation Recommended Circuit Oscillation Voltage Oscillation Frequency Constant Range stabilization fX (MHz) time C1 (pF) C2 (pF) Rd () MIN. (V) MAX. (V) Surface mounting X1 MAX. (ms) PBRC3.00HR10X000 3.000 30 30 1000 2.85 3.6 0.01 PBRC4.00MR10X000 4.000 15 15 1000 2.85 3.6 0.01 PBRC5.00MR10X000 5.000 15 15 1000 2.85 3.6 0.01 PBRC6.00MR10X000 6.000 15 15 1000 2.85 3.6 0.01 X2 Rd C1 Caution C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/Jx3-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. (3) Toyama Murata Mfg. Co. Ltd.: Ceramic resonator Type Circuit Example Part Number Oscillation Recommended Circuit Oscillation Voltage Oscillation Frequency Constant Range Stabilization fX (MHz) Time C1 (pF) C2 (pF) Rd () MIN. (V) MAX. (V) Surface X1 X2 mounting CSTCR4M00GH5L99 4.000 (39) (39) 1000 2.85 3.6 0.01 CSTCR5M00GH5L99 5.000 (39) (39) 1000 2.85 3.6 0.01 CSTCR6M00GH5L99 6.000 (39) (39) 680 2.85 3.6 0.01 Rd C1 Caution MAX. (ms) C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1358 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/Jx3-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. Remark Figures in parentheses in columns C1 and C2 indicate the capacitance incorporated in the resonator. 32.4.2 Subclock oscillator characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Resonator Circuit Example Crystal XT1 XT2 Parameter Conditions Oscillation frequency MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s Note 1 resonator (fXT) Oscillation stabilization time Note 2 Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JC3-H and V850ES/JE3-H so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from when VDD reaches the oscillation voltage range (2.85 V (MIN.)) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 3. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1359 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (1) Seiko Instruments Inc.: Crystal resonator Oscillation frequency: fXT = 32.768 kHz Type Circuit Example Part Number Recommended Circuit Oscillation Oscillation Constant Voltage Range Stabilization Time C1 (pF) C2 (pF) Rd () MIN. (V) MAX. (V) Surface mounting SSP-T7 XT1 7 7 0 2.85 3.6 MAX. (ms) 1.4 XT2 Rd C1 Caution C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/Jx3-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1360 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.4.3 PLL characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Symbol Input frequency fX Output frequency fXX Lock time Conditions MIN. MAX. Unit 3 TYP. 6 MHz Clock-through mode 3 6 MHz PLL mode (x8) 24 48 MHz 800 s tPLL 32.4.4 Internal oscillator characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Output frequency Symbol fR R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Conditions MIN. TYP. MAX. Unit 100 220 400 kHz Page 1361 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.5 DC Characteristics 32.5.1 I/O level (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Input voltage, high Symbol VIH1 Conditions MIN. RESET, FLMD0, P60 to P65, P92 to P94, TYP. MAX. Unit 0.8EVDD EVDD V P96, P97, P910 to P913 Input voltage, low VIH2 P02, P03, P30 to P35, P42, P52 to P56 0.8EVDD 5.5 V VIH3 P36, P37, P40, P41 0.7EVDD 5.5 V VIH4 PDL5 0.7EVDD EVDD V VIH5 UDPF, UDMF 2.0 UVDD V VIH6 P70 to P79 0.7AVREF0 AVREF0 V VIH7 P10 0.7AVREF1 AVREF1 V VIL1 RESET, FLMD0, P60 to P65, P92 to P94, VSS 0.2EVDD V P96, P97, P910 to P913 VIL2 P02, P03, P30 to P35, P42, P52 to P56 VSS 0.2EVDD V VIL3 P36, P37, P40, P41 VSS 0.3EVDD V VIL4 PDL5 VSS 0.3EVDD V VIL5 UDPF, UDMF VSS 0.8 V VIL6 P70 to P79 AVSS 0.3AVREF0 V VIL7 P10 AVSS 0.3AVREF1 V Input leakage current, high ILIH VI = VDD = EVDD = UVDD = AVREF0 = AVREF1 5 A Input leakage current, low ILIL VI = 0 V -5 A VO = VDD = EVDD = UVDD = AVREF0 = 5 A -5 A Output leakage current, high ILOH AVREF1 Output leakage current, low Remark ILOL VO = 0 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1362 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH1 Conditions Note 1 Per pin MIN. TYP. MAX. Unit EVDD - 1.0 EVDD V EVDD - 0.5 EVDD V AVREF0 - 1.0 AVREF0 V AVREF0 - 0.5 AVREF0 V AVREF1 - 1.0 AVREF1 V AVREF1 - 0.5 AVREF1 V IOH = -1.0 mA Per pin IOH = -100 A VOH2 P70 to P79 Per pin IOH = -0.4 mA Per pin IOH = -100 A VOH3 P10 Per pin IOH = -0.4 mA Per pin IOH = -100 A VOH4 UDPF, UDMF RL = 15 k V 2.8 (Connect to UVDD) Output voltage, low VOL1 Note 2 Per pin 0 0.4 V 0 0.4 V 0 0.4 V 0 0.4 V 0 0.3 V 100 k IOL = 0.4 mA VOL2 VOL3 P36, P37, P40, Per pin P41 IOL = 3.0 mA P70 to P79 Per pin IOL = 0.4 mA VOL4 P10 Per pin IOL = 0.4 mA VOL5 UDPF, UDMF RL = 1.5 k (Connect to VSS) Software pull-down resistor R1 P56 VI = VDD 10 30 Notes 1. P02, P03, P30 to P37, P40 to P42, P52 to P56, P60 to P65, P92 to P94, P96, P97, P910 to P913, PDL5 2. P02, P03, P30 to P35, P42, P52 to P56, P60 to P65, P92 to P94, P96, P97, P910 to P913, PDL5 Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. When the IOH and IOL conditions are not satisfied for one pin but the total value of all pins is satisfied, only that pin is deemed to not satisfy the DC characteristics. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1363 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.5.2 Supply current (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Supply current Notes 1, 2 Symbol IDD1 Conditions Normal fXX = 48 MHz (fX = 6 MHz) operation Peripheral function operating <R> fXX = 48 MHz (fX = 6 MHz) MIN. TYP. MAX. Unit 60 mA 42 mA USBF operating <R> IDD2 HALT mode fXX = 48 MHz (fX = 6 MHz) 33 42 mA 4 7 mA 0.5 0.8 mA 120 600 A 13 95 A 10 90 A 13 95 A 65 70 mA Peripheral function operating IDD3 IDD4 IDD5 IDD6 IDLE1 fXX = 48 MHz (fX = 6 MHz), mode PLL on IDLE2 fXX = 6 MHz (fX = 6 MHz), mode PLL off Subclock fXT = 32.768 kHz, operation main clock stopped, mode internal oscillator stopped Sub-IDLE fXT = 32.768 kHz, mode main clock stopped, internal oscillator stopped IDD7 STOP Subclock stopped, mode internal oscillator stopped Subclock operating, internal oscillator stopped IDD8 Flash memory fXX = 48 MHz (fX = 6 MHz) programming mode Notes 1. Total of VDD, EVDD, and UVDD currents. Currents flowing through the output buffers, A/D converter, D/A converter, and on-chip pull-down resistor are not included. 2. The VDD of the TYP. value is 3.3 V. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1364 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.6 Data Retention Characteristics (1) In STOP mode (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Symbol Data retention voltage VDDDR Conditions MIN. STOP mode (all functions TYP. 1.9 MAX. Unit 3.6 V 90 A stopped) Data retention current IDDDR STOP mode (all functions 10 stopped), VDDDR = 2.0 V Supply voltage rise time tRVD 200 s Supply voltage fall time tFVD 200 s Supply voltage retention time tHVD After STOP mode setting 0 ms STOP release signal input time tDREL After VDD reaches 2.85 V (MIN.) 0 ms Data retention input voltage, high VIHDR VDD = EVDD = UVDD = VDDDR 0.9VDDDR VDDDR V Data retention input voltage, low VILDR VDD = EVDD = UVDD = VDDDR 0 0.1VDDDR V Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD/EVDD/UVDD tHVD tFVD tRVD VDDDR STOP release signal input tDREL VIHDR RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 VIHDR VILDR Page 1365 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.7 AC Characteristics (1) AC test input measurement points (VDD, AVREF0, AVREF1, EVDD) VDD VIH VIH Measurement points 0V VIL VIL (2) AC test output measurement points VOH VOH Measurement points VOL VOL (3) Load conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1366 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.8 Basic Operation (1) Power on/power off/reset timing (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Time from EVDD, UVDD to VDD tREL <1> Time from EVDD, UVDD to AVREF0, AVREF1 tREA <2> Time from VDD to RESET tRER <3> RESET low-level width tWRSL <4> Conditions MIN. MAX. 0 ns 0 500 + tREG Analog noise elimination (during Unit tREL Note ns ns 500 ns 500 ns flash erase/writing) Analog noise elimination Time from RESET to VDD tFRE <5> 500 ns Time from VDD to EVDD, UVDD tFEL <6> 0 ns Time from AVREF0, AVREF1 to EVDD, UVDD tFEA <7> 0 tFEL ns Note Depends on the on-chip regulator characteristics. VDD <1> <6> <2> <7> EVDD, UVDD AVREF0, AVREF1 <4> <3> RESET (input) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 VI VI <5> VI VI Page 1367 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (2) Reset, interrupt timing (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter RESET input low-level width Symbol Conditions tWRSL MIN. MAX. 500 Unit ns NMI high-level width tWNIH Analog noise elimination 500 ns NMI low-level width tWNIL Analog noise elimination 500 ns INTPn high-level width tWITH n = 5, 7 to 11, 14 to 16 (Analog noise 500 ns 3TSMP + 20 ns 500 ns 3TSMP + 20 ns elimination) n = 2 (Digital noise elimination) INTPn low-level width tWITL n = 5, 7 to 11, 14 to 16 (Analog noise elimination) n = 2 (Digital noise elimination) FLMD0 high-level width tWMDH 500 ns FLMD0 low-level width tWMDL 500 ns Remark TSMP: Set by the noise elimination control register (INTNFC). Selectable from fXX/64, fXX/128, fXX/256, fXX/512, and fXX/1024. (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit KRn high-level width tWKRH Analog noise elimination 500 ns KRn low-level width tWKRL Analog noise elimination 500 ns Remark n = 2 to 5 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1368 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (4) Timer timing (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter TI high-level width Symbol tTIH Conditions MIN. TAB10 to TAB13, EVTAB1, TRGAB1 TIAA00, TIAA01, TIAA10, TIAA11, MAX. Unit 12T + 20 ns 3TSMP1 + 20 ns 12T + 20 ns 3TSMP1 + 20 ns TIAA20, TIAA21 TI low-level width tTIL TAB10 to TAB13, EVTAB1, TRGAB1 TIAA00, TIAA01, TIAA10, TIAA11, TIAA20, TIAA21 TENCn high-level width tWENCHn n = 0, 1 3TSMP2 + 20 ns TENCn low-level width tWENCLn n = 0, 1 3TSMP2 + 20 ns TECR0 high-level width tWCRH0 3TSMP2 + 20 ns TECR0 low-level width tWCRL0 3TSMP2 + 20 ns TITn high-level width tWTITHn n = 0, 1 3TSMP2 + 20 ns TITn low-level width tWTITLn n = 0, 1 3TSMP2 + 20 ns EVTT0 high-level width tWTITH0 3TSMP2 + 20 ns 3TSMP2 + 20 ns 3TSMP2 + 20 ns EVTT0 low-level width tWTITL0 TENCn input time difference tPHUD n = 0, 1 Remarks 1. T = 1/fXX 2. TSMP1: Set by the noise elimination control register (TANFC). Selectable from fXX and fXX/4. 3. TSMP2: Set by the noise elimination control register (TTNFC). Selectable from fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. 4. The specifications above show the pulse widths that can be accurately detected as valid edges. Therefore, even if a pulse width less than the above specifications is input, it may be detected as a valid edge. <tWTIHn>/<tWTITHn> <tWTILn>/<tWTITLn> <tWUDH00> <tWUDL00> TIn (input) TENC00 (input) <tPHUD> <tWUDH01> <tWUDL01> TENC01 (input) <tWTCH0> <tWTCL0> TECR0 (input) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1369 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (5) UARTC timing (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) MAX. Unit Transmit rate Parameter 3.0 Mbps ASCK0 cycle time 10 MHz R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Symbol Conditions MIN. Page 1370 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (6) CSIF timing (a) Master mode [When using CSIF0, CSIF2, CSIF4] (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKFn cycle time tKCY1 <8> 125 ns SCKFn high-level width tKH1 <9> tKCY1/2 - 8 ns SCKFn low-level width tKL1 tKCY1/2 - 8 ns SIFn setup time (to SCKFn) tSIK1 27 ns 27 ns 27 ns 27 ns <10> SIFn setup time (to SCKFn) SIFn hold time (from SCKFn) tKSI1 <11> SIFn hold time (from SCKFn) SOFn output delay time (from SCKFn) tKSO1 <12> SOFn output delay time (from SCKFn) SOFn output hold time (from SCKFn) tHSO1 <13> SOFn output hold time (from SCKFn) 27 ns 27 ns tKCY1/2 - 10 ns tKCY1/2 - 10 ns Remark n = 0, 2, 4 [When using CSIF3] (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKF3 cycle time tKCYM <8> 83.3 ns SCKF3 high-level width tKHM <9> tKCYM/2 - 8 ns tKCYM/2 - 8 ns 16 ns 16 ns 16 ns 16 ns SCKF3 low-level width SIF3 setup time (to SCKF3) tSIKM <10> SIF3 setup time (to SCKF3) SIF3 hold time (from SCKF3) tKSIM <11> SIF3 hold time (from SCKF3) SOF3 output delay time (from SCKF3) tKSOM <12> SOF3 output delay time (from SCKF3) SOF3 output hold time (from SCKF3) SOF3 output hold time (from SCKF3) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 tHSOM <13> 16 ns 16 ns tKCYM/2 - 10 ns tKCYM/2 - 10 ns Page 1371 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (b) Slave mode [When using CSIF0, CSIF2 to CSIF4] (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKFn cycle time tKCY2 <8> 125 ns SCKFn high-level width tKH2 <9> tKCYn/2 - 8 ns SCKFn low-level width tKL2 tKCYn/2 - 8 ns SIFn setup time (to SCKFn) tSIK2 27 ns 27 ns 27 ns 27 ns <10> SIFn setup time (from SCKFn) SIFn hold time (to SCKFn) tKSI2 <11> SIFn hold time (from SCKFn) SOFn output delay time (to SCKFn) tKSO2 <12> SOFn output delay time (from SCKFn) SOFn output delay time (to SCKFn) SOFn output delay time (from SCKFn) Remark1. tHSO2 <13> 27 ns 27 ns tKCYn/2 - 10 ns tKCYn/2 - 10 ns n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1372 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (a) CFnCTL1.CFnCKP, CFnDAP bits = 00 or 11 <8> <9> <9> SCKFn (I/O) <13> <10> SIFn (input) <11> Input data <12> Output data SOFn (output) (b) CFnCTL1.CFnCKP, CFnDAP bits = 10 or 01 <8> <9> <9> SCKFn (I/O) <13> <10> SIFn (input) <11> Input data <12> SOFn (output) Remark Output data n = 0, 2 to 4 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1373 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 2 (7) I C bus mode (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V) Parameter Symbol Normal Mode High-Speed Mode MIN. MAX. Unit MIN. MAX. SCL0n clock frequency fCLK 0 100 0 400 kHz Bus free time tBUF <14> 4.7 - 1.3 - s tHD:STA <15> 4.0 - 0.6 - s SCL0n clock low-level width tLOW <16> 4.7 - 1.3 - s SCL0n clock high-level width tHIGH <17 4.0 - 0.6 - s Setup time for start/restart conditions tSU:STA <18> 4.7 - 0.6 - s Data hold tHD:DAT <19> 5.0 - - - s (Between start and stop conditions) Hold time Note 1 time CBUS compatible master 2 I C mode 0 - Note 2 Note 2 0 0.9 Data setup time tSU:DAT <20> 250 - 100 SDA0n and SCL0n signal rise time tR <21> - 1000 20 + 0.1Cb SDA0n and SCL0n signal fall time tF <22> - 300 20 + 0.1Cb Stop condition setup time tSU:STO <23> 4.0 - Pulse width of spike suppressed by tSP <24> - - Note 3 s - ns Note 5 300 ns Note 5 300 ns 0.6 - s - 0 50 ns 400 - 400 pF Note 4 input filter Capacitive load of each bus line Cb Notes 1. When the start condition is satisfied, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at VIHmin. of the SCL0n signal) in order to occupy the undefined area at the falling edge of SCL0n. 3. If the system does not extend the SCL0n signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in a normal-mode I2C bus system. In this case, set the high-speed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCL0n signal low hold time: tSU:DAT 250 ns * If the system extends the SCL0n signal low hold time: Output the next data bit to the SDA0n line before the SCL0n line is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1374 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H <16> <17> SCL0n (I/O) <22> <21> <19> <20> <18> <15> <24> <23> <15> SDA0n (I/O) <14> Stop Start condition condition Remark <21> <22> Restart condition Stop condition n = 0, 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1375 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (8) CAN timing (CAN controller versions only) (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transmit rate Internal delay time tNODE MAX. Unit 1 Mbps 100 ns CAN internal clock (fCAN) tOUTPUT CTXD0 pin (transmit data) tINTPUT CRXD0 pin (receive data) Remark CAN internal clock (fCAN): CAN baud rate clock Internal delay time (tNODE) = Internal transmission delay time (tOUTPUT) + Internal reception delay time (tINPUT) V850ES/JC3-H, V850ES/JE3-H Internal transmission delay time (tOUTPUT) CTXD0 pin CAN controller Internal reception delay time (tINPUT) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 CRXD0 pin Page 1376 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (9) High-impedance control timing (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Time from oscillator stop to timer output high impedance tCLM Conditions MIN. Clock monitor MAX. Unit 65 s operating Time from TOAB1OFF input timer output high impedance tHTQn 300 ns Time from TOAA1OFF input timer output high impedance tHTP2 300 ns (10) A/D converter (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, 3.0 V AVREF0 3.6 V, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 bit 0.6 %FSR 24 s Zero scale error 0.5 %FSR Full scale error 0.5 %FSR Non-linearity error 4.0 LSB Differential linearity error 4.0 LSB AVSS AVREF0 V 3.0 3.6 V Resolution Overall error 3.0 AVREF0 3.6 V Note Conversion time tCONV Analog input voltage VIAN Reference voltage AVREF0 AVREF0 current AIREF0 2.17 Normal conversion mode 3 6.5 mA High-speed conversion mode 4 10 mA 5 A When A/D converter unused Note Excluding quantization error (0.05 %FSR). Caution Do not set (read/write) alternate-function ports during A/D conversion; otherwise the conversion resolution may be degraded. Remark LSB: Least Significant Bit FSR: Full Scale Range R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1377 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (11) D/A converter (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, 3.0 V AVREF1 3.6 V, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 bit R = 2 M 1.2 %FSR C = 20 pF 3 s Resolution Overall error Note 1 Settling time Output resistor RO Reference voltage AVREF1 AVREF1 current Note 2 AIREF1 Output data 55H 6.42 3.0 D/A conversion operating 1 D/A conversion stopped k 3.6 V 2.5 mA 5 A Notes 1. Excluding quantization error (0.5 %LSB). 2. Value of 1 channel of D/A converter Remark R is the output pin load resistance and C is the output pin load capacitance. (12) LVI circuit characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Detection voltage Note Response time Symbol Conditions VLVI0 tLD MIN. TYP. MAX. Unit 2.85 2.95 3.05 V 0.2 2.0 ms After VDD reaches VLVI0 (MAX.), or after VDD has dropped to VLVI0 (MAX.) Minimum pulse width tLW Reference voltage tLWAIT 0.2 After VDD reaches 2.85 V(MIN.) ms 0.1 0.2 ms stabilization wait time Note Time required to detect the detection voltage and output an interrupt or reset signal. Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) Operating voltage (MIN.) tLW tLWAIT LVION bit = 0 1 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 tLD tLD Time Page 1378 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H (13) RAM retention detection (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Detection voltage VRAMH Supply voltage rise time tRAMHTH VDD = 0 to 2.85 V Response time tRAMHD After VDD reaches 2.1 V Minimum pulse width tRAMHW Note MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 0.002 ms 0.2 3.0 ms 0.2 ms Note Time required to detect the detection voltage and set the RAMS.RAMF bit. Supply voltage (VDD) Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHW tRAMHD tRAMHD Time RAMS.RAMF bit Cleared by instruction R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1379 of 1442 CHAPTER 32 ELECTRICAL SPECIFICATIONS V850ES/JC3-H, V850ES/JE3-H 32.9 Flash Memory Programming Characteristics (TA = -40 to +85C, VDD = EVDD = UVDD = AVREF0 = AVREF1, VSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics Parameter <R> Symbol Conditions MIN. TYP. MAX. Unit Operating frequency fCPU 24 48 MHz Supply voltage VDD 2.85 3.6 V Number of rewrites CWRT Used for updating programs Retained When using flash memory for programmer and Renesas 15 years 1,000 times 10,000 times Electronics self programming library Used for updating data Retained When using Renesas for Electronics EEPROM 5 years emulation library (usable ROM size: 12 KB of 3 consecutive blocks) Programming temperature -40 tPRG +85 C (2) Serial write operation characteristics Parameter Symbol FLMD0, FLMD1 setup time tMDSET FLMD0 count start time from RESET tRFCF FLMD0 counter high-level width/ tCH/tCL Conditions MIN. TYP. 2 fX = 3 to 6 MHz MAX. Unit 3000 ms s 800 10 100 s 1 s low-level width FLMD0 counter rise time/fall time tR/tF Flash write mode setup timing VDD RESET (input) 0V tCH VDD FLMD0 0V tMDSET tRFCF tF VDD tR tCL FLMD1 0V R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1380 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 33 PACKAGE DRAWINGS CHAPTER 33 PACKAGE DRAWINGS + R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1381 of 1442 CHAPTER 33 PACKAGE DRAWINGS V850ES/JC3-H, V850ES/JE3-H 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) HD D detail of lead end 36 A3 25 37 c 24 L Lp E L1 HE (UNIT:mm) 13 48 1 12 ZE e ZD b x M S A S A2 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 A1 DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 +0.07 0.20 -0.03 b S y ITEM D c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 P48GA-50-GAM Page 1382 of 1442 CHAPTER 33 PACKAGE DRAWINGS V850ES/JC3-H, V850ES/JE3-H 48-PIN PLASTIC WQFN(7x7) D DETAIL OF A PART E S A c A1 A S y S D2 A 1 (UNIT:mm ) 12 ITEM 13 48 B E2 D 7.00 0.05 E 7.00 0.05 D2 5.50 E2 5.50 A 0.75 0.05 A1 0.00 to 0.02 + 0.25 0.05 0.07 0.20 0.05 b 37 24 36 25 Lp e b R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 x M S AB DIMENSIONS c e Lp 0.50 0.40 0.10 x 0.05 y 0.05 P48K8-50-5B4 Page 1383 of 1442 CHAPTER 33 PACKAGE DRAWINGS V850ES/JC3-H, V850ES/JE3-H 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 A3 33 49 c 32 L Lp E L1 HE (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A2 S S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 +0.07 0.20 -0.03 b A y ITEM D A1 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-GAH Page 1384 of 1442 V850ES/JC3-H, V850ES/JE3-H CHAPTER 33 PACKAGE DRAWINGS 64-PIN PRASTIC WQFN (9 x 9) T.B.D 64-PIN PRASTIC FBGA (6 x 6) T.B.D R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1385 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JC3-H or V850ES/JE3-H. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 98, 2000 * Windows Me * Windows XP * Windows NTTM Ver. 4.0 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1386 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Debugging software Language processing software * Integrated debugger * C compiler package * System simulator * Device file Control software * Project manager Embedded software (Windows only)Note 1 * Real-time OS * Network library * File system Host machine (PC or EWS) Interface adapterNote 2 Flash memory write environment Flash programmer Flash memory write adapter On-chip debug emulator (QB-V850MINI)Note 3 (QB-MINI2)Note 4 In-circuit emulator (QB-V850ESJX3H)Notes 5 Flash memory Conversion socket or conversion adapter Target system Notes 1. Project manager PM+ is included in the C compiler package. PM+ is only used in Windows. 2. The QB-V850MINI, QB-MINI2, and QB-V850ESJX3H (under development) support the USB interface 3. The QB-V850MINI is supplied with the ID850QB, USB interface cable, OCD cable, self-check board, 4. The QB-MINI2 is supplied with USB interface cable, 16-pin target cable, 10-pin target cable, and 78K0- 5. The QB-V850ESJX3H is supplied with the ID850QB, flash memory programmer (MINICUBE2), power only. KEL adapter, and KEL connector. All other products are optional. OCD board (integrated debugger is not supplied.) All other products are optional. supply unit, and USB interface adapter. All other products are optional. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1387 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package. microcontrollers Part number: SxxxxSP850 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP850 xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software CA850 This compiler converts programs written in C into object codes executable with a C compiler package microcontroller. This compiler is started from project manager PM+. Part number: SxxxxCA703000 DF703771 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (CA850 or ID850QB). The corresponding OS and host machine differ depending on the tool to be used. Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxCA703000 xxxx Host Machine AB17 PC-9800 series, BB17 IBM PC/AT compatibles 3K17 SPARCstation TM OS Windows (Japanese version) Supply Medium CD-ROM Windows (English version) TM (Rel. 4.1.4), TM (Rel. 2.5.1) SunOS Solaris A.3 Control Software PM+ This is control software designed to enable efficient user program development in the Project manager Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from PM+. <Caution> PM+ is included in C compiler package CA850. It can only be used in Windows. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1388 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using IECUBE QB-V850ESJX3H The system configuration when connecting the QB-V850ESJX3H to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-2. System Configuration (When Using QB-V850ESJX3H) (1/2) System configuration <1> Accessories <5> IECUBE <3> USB cable Required Optional <6> Check pin adapter Enables signal monitoring (S and T types) <4> Power supply <2> CD-ROM Simple flash programmer <7> Extension probe Flexible type (S and T types) <8> Extension probe Coaxial type (S and T types) <9> Exchange adapter Exchanges pins among different microcontroller types <9> Exchange adapter Exchanges pins among different microcontroller types <10> Check pin adapter (S type only) Enables signal monitoring <11> Space adapter Each adapter can adjust height by 5.6 mm. <13> Mount adapter For device mounting <14> Target connector For mounting on target system <15> Target system R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 <11> Space adapter Each adapter can adjust height by 3.2 mm. <12> YQ connector Connector for connecting to emulator <13> Mount adapter For device mounting <14> Target connector For mounting on target system <15> Target system S-type socket configuration T-type socket configuration Page 1389 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS Figure A-2. System Configuration (When Using QB-V850ESJX3H) (2/2) <1> Host machine (PC-9821 series, IBM-PC/AT compatibles) <2> Debugger, USB driver, manuals, etc. (ID850QB Disk, Accessory DiskNote 1) <3> USB interface cable <4> AC adapter <5> In-circuit emulator (QB-V850ESJX3H) <6> Check pin adapter (S and T types) (QB-144-CA-01) (optional) <7> Extension probe (flexible type) (S and T types) (QB-144-EP-02S) (optional) <8> Extension probe (coaxial type) (S and T types) (QB-144-EP-01S) (optional) <9> Exchange adapterNote 2 (S type: QB-100GC-EA-04S (GC package), QB-128GF-EA-01S (GF package), T type: QB-100GC-EA-05T (GC package), QB-128GF-EA-02T (GF package)) <10> Check pin adapterNote 3 (S type only: QB-100-CA-01S (GC package), QB-128GF-CA-01S (GF package)) (optional) <11> Space adapterNote 3 (S type: QB-100-SA-01S (GC package), QB-144-SA-01S (GF package), T type: QB100GC-YS-01T (GC package), QB-128GF-YS-01T (GF package) (optional) <12> YQ connectorNote 2 (T type only) (QB-100GC-YQ-01T) (GC package), QB-128GF-YQ-01T (GF package) <13> Mount adapter (S type: QB-100GC-MA-01S (GC package), QB-128GF-MA-01S (GF package), T type: QB-100GC-HQ-01T (GC package), QB-128GF-HQ-01T (GF package)) (optional) <14> Target connectorNote 2 (S type: QB-100GC-TC-01S (GC package), QB-128GF-TC-01S (GF package), T type: QB-100GC-NQ-01T (GC package), QB-128GF-NQ-01T (GF package)) <15> Target system Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/en/ods/ 2. Supplied with the device depending on the ordering number. * When QB-V850ESJX3H-ZZZ is ordered The exchange adapter and the target connector are not supplied. * When QB-V850ESJX3H-S100GC is ordered The QB-100GC-EA-04S and QB-100GC-TC-01S are supplied. * When QB-V850ESJX3H-S128GF is ordered The QB-128GF-EA-01S and QB-128GF-TC-01S are supplied. * When QB-V850ESJX3H-T100GC is ordered The QB-100GC-EA-05T, QB-100GC-YQ-01T, and QB-100GC-NQ-01T are supplied. * When QB-V850ESJX3H-T128GF is ordered The QB-1028GF-EA-02T, QB-128GF-YQ-01T, and QB-128GF-NQ-01T are supplied. 3. When using both <9> and <10>, the order between <9> and <10> is not cared. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1390 of 1442 V850ES/JC3-H, V850ES/JE3-H <5> Note APPENDIX A DEVELOPMENT TOOLS QB-V850ESJX3H The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the V850ES/JC3-H or V850ES/JE3-H. It supports the integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine. <3> USB interface cable Cable to connect the host machine and the QB-V850ESJX3H. <4> AC adapter 100 to 240 V can be supported by replacing the AC plug. <9> Exchange adapter Adapter to perform pin conversion. <10> Check pin adapter Adapter used in waveform monitoring using the oscilloscope, etc <11> Space adapter Adapter to adjust the height. <12> YQ connector Conversion adapter to connect target connector and exchange adapter . <13> Mount adapter Adapter to mount the V850ES/JC3-H or V850ES/JE3-H on a socket. <14> Target connector Connector to solder on the target system. Note The QB-V850ESJX3H is supplied with a power supply unit, USB interface cable, and flash memory programmer (MINICUBE2). It is also supplied with integrated debugger ID850QB as control software. Remark The numbers in the angle brackets correspond to the numbers in Figure A-2. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1391 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS A.4.2When using MINICUBE QB-V850MINI (1) On-chip emulation using MINICUBE The system configuration when connecting MINICUBE to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-3. On-Chip Emulation System Configuration <1> <3> <4> STATUS TARGET POWER <2> <5> V850ES/JC3-H, V850ES/JE3-H <6> <7> Target system <1> Host machine <2> CD-ROM PC with USB ports Note 1 Contents such as integrated debugger ID850QB, N-Wire Checker, device driver, and documents are included in CD-ROM. It is supplied with MINICUBE. <3> USB interface cable USB cable to connect the host machine and MINICUBE. It is supplied with <4> MINICUBE This on-chip debug emulator serves to debug hardware and software when MINICUBE. The cable length is approximately 2 m. On-chip debug emulator developing application systems using the V850ES/JC3-H or V850ES/JE3-H. It supports integrated debugger ID850QB. Cable to connect MINICUBE and the target system. <5> OCD cable It is supplied with MINICUBE. The cable length is approximately 20 cm. <6> Connector conversion board This conversion board is supplied with MINICUBE. KEL adapter <7> MINICUBE connector KEL connector Note 2 8830E-026-170S (supplied with MINICUBE) 8830E-026-170L (sold separately) Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/en/ods/ 2. Product of KEL Corporation Remark The numbers in the angular brackets correspond to the numbers in Figure A-3. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1392 of 1442 V850ES/JC3-H, V850ES/JE3-H A.4.3 APPENDIX A DEVELOPMENT TOOLS When using MINICUBE2 QB-MINI2 The system configuration when connecting MINICUBE2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-4. System Configuration of On-Chip Emulation System <4> <3> <1> <5> V850ES/JC3-H, V850ES/JE3-H M IN IC U BE 2 <6> <2> Software Target system <1> Host machine PC with USB ports <2> Software The integrated debugger ID850QB, device file, etc. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/en/ods/ USB cable to connect the host machine and MINICUBE. It is supplied with <3> USB interface cable MINICUBE. The cable length is approximately 2 m. <4> MINICUBE2 This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/JC3-H or V850ES/JE3-H. It supports integrated debugger ID850QB. Cable to connect MINICUBE2 and the target system. <5> 16-pin target cable It is supplied with MINICUBE. The cable length is approximately 15 cm. <6> Target connector (sold separately) Remark Use a 16-pin general-purpose connector with 2.54 mm pitch. The numbers in the angular brackets correspond to the numbers in Figure A-4. A.5 Debugging Tools (Software) ID850QB This debugger supports the in-circuit emulators for V850 microcontrollers. The Integrated debugger ID850QB is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using a window integration function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file. Part number: Sxxxx ID703000-QB (ID850QB) Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxID703000-QB xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Supply Medium CD-ROM Page 1393 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than the RX850. Part number: SxxxxRX703000- (RX850) SxxxxRX703100- (RX850 Pro) RX-FS850 This is a FAT file system function. (File system) It is a file system that supports the CD-ROM file system function. This file system is used with the real-time OS RX850 Pro. Caution To purchase the RX850 or RX850 Pro, first fill in the purchase application form and sign the license agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX703000- SxxxxRX703100- Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Do not use for mass-produced product. 100K Mass-production object 0.1 million units 001M 1 million units 010M S01 10 million units Source program xxxx Host Machine Object source program for mass production OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) 3K17 SPARCstation Solaris (Rel. 2.5.1) Supply Medium CD-ROM A.7 Flash Memory Writing Tools Flashpro V (part number: PG-FP5) Flash programmer dedicated to microcontrollers with internal flash memory. Flash programmer QB-MINI2 (MINICUBE2) On-chip debug emulator with programming function. FA-100GC-UEU-B Flash memory writing adapter (not wired) used by connecting to the Flashpro V, FA-128GF-GAT-B etc. Flash memory writing adapter * FA-100GC-UEU-B: 100-pin plastic LQFP (GC-UEU type) * FA-128GF-GAT-B: 100-pin plastic LQFP (GF-GAT type) Remark FA-100GC-UEU-B and FA-128GF-GAT-B are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-42-750-4172 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1394 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX APPENDIX B REGISTER INDEX (1/34) Symbol Name Unit Page ADA0CR0 A/D conversion result register 0 ADC 642 ADA0CR0H A/D conversion result register 0H ADC 642 ADA0CR1 A/D conversion result register 1 ADC 642 ADA0CR1H A/D conversion result register 1H ADC 642 ADA0CR2 A/D conversion result register 2 ADC 642 ADA0CR2H A/D conversion result register 2H ADC 642 ADA0CR3 A/D conversion result register 3 ADC 642 ADA0CR3H A/D conversion result register 3H ADC 642 ADA0CR4 A/D conversion result register 4 ADC 642 ADA0CR4H A/D conversion result register 4H ADC 642 ADA0CR5 A/D conversion result register 5 ADC 642 ADA0CR5H A/D conversion result register 5H ADC 642 ADA0CR6 A/D conversion result register 6 ADC 642 ADA0CR6H A/D conversion result register 6H ADC 642 ADA0CR7 A/D conversion result register 7 ADC 642 ADA0CR7H A/D conversion result register 7H ADC 642 ADA0CR8 A/D conversion result register 8 ADC 642 ADA0CR8H A/D conversion result register 8H ADC 642 ADA0CR9 A/D conversion result register 9 ADC 642 ADA0CR9H A/D conversion result register 9H ADC 642 ADA0M0 A/D converter mode register 0 ADC 635 ADA0M1 A/D converter mode register 1 ADC 637 ADA0M2 A/D converter mode register 2 ADC 640 ADA0PFM Power-fail compare mode register ADC 644 ADA0PFT Power-fail compare threshold value register ADC 645 ADA0S A/D converter channel specification register ADC 641 ADIC Interrupt control register INTC 1222 AWC Address wait control register USBF 1012 BCC Bus cycle control register USBF 1013 BPC Peripheral I/O area select control register USBF 90 BRGINTE Bridge interrupt enable register USBF 1121 BRGINTT Bridge interrupt control register USBF 1120 C0BRP CAN0 module bit rate prescaler register CAN 911 C0BTR CAN0 module bit rate register CAN 912 C0CTRL CAN0 module control register CAN 901 C0ERC CAN0 module error counter register CAN 907 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1395 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (2/34) Symbol Name Unit Page C0GMABT CAN0 global automatic block transmission control register CAN 896 C0GMABTD CAN0 global automatic block transmission delay setting register CAN 898 C0GMCS CAN0 global clock selection register CAN 895 C0GMCTRL CAN0 global control register CAN 893 C0IE CAN0 module interrupt enable register CAN 908 C0INFO CAN0 module information register CAN 904 C0INTS CAN0 module interrupt status register CAN 910 C0LEC CAN0 module last error information register CAN 905 C0LIPT CAN0 module last in-pointer register CAN 914 C0LOPT CAN0 module last out-pointer register CAN 916 C0MASK1H CAN0 module mask 1 register H CAN 899 C0MASK1L CAN0 module mask 1 register L CAN 899 C0MASK2H CAN0 module mask 2 register H CAN 899 C0MASK2L CAN0 module mask 2 register L CAN 899 C0MASK3H CAN0 module mask 3 register H CAN 899 C0MASK3L CAN0 module mask 3 register L CAN 899 C0MASK4H CAN0 module mask 4 register H CAN 899 C0MASK4L CAN0 module mask 4 register L CAN 899 C0MCONF00 CAN0 message configuration register 00 CAN 923 C0MCONF01 CAN0 message configuration register 01 CAN 923 C0MCONF02 CAN0 message configuration register 02 CAN 923 C0MCONF03 CAN0 message configuration register 03 CAN 923 C0MCONF04 CAN0 message configuration register 04 CAN 923 C0MCONF05 CAN0 message configuration register 05 CAN 923 C0MCONF06 CAN0 message configuration register 06 CAN 923 C0MCONF07 CAN0 message configuration register 07 CAN 923 C0MCONF08 CAN0 message configuration register 08 CAN 923 C0MCONF09 CAN0 message configuration register 09 CAN 923 C0MCONF10 CAN0 message configuration register 10 CAN 923 C0MCONF11 CAN0 message configuration register 11 CAN 923 C0MCONF12 CAN0 message configuration register 12 CAN 923 C0MCONF13 CAN0 message configuration register 13 CAN 923 C0MCONF14 CAN0 message configuration register 14 CAN 923 C0MCONF15 CAN0 message configuration register 15 CAN 923 C0MCONF16 CAN0 message configuration register 16 CAN 923 C0MCONF17 CAN0 message configuration register 17 CAN 923 C0MCONF18 CAN0 message configuration register 18 CAN 923 C0MCONF19 CAN0 message configuration register 19 CAN 923 C0MCONF20 CAN0 message configuration register 20 CAN 923 C0MCONF21 CAN0 message configuration register 21 CAN 923 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1396 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (3/34) Symbol Name Unit Page C0MCONF22 CAN0 message configuration register 22 CAN 923 C0MCONF23 CAN0 message configuration register 23 CAN 923 C0MCONF24 CAN0 message configuration register 24 CAN 923 C0MCONF25 CAN0 message configuration register 25 CAN 923 C0MCONF26 CAN0 message configuration register 26 CAN 923 C0MCONF27 CAN0 message configuration register 27 CAN 923 C0MCONF28 CAN0 message configuration register 28 CAN 923 C0MCONF29 CAN0 message configuration register 29 CAN 923 C0MCONF30 CAN0 message configuration register 30 CAN 923 C0MCONF31 CAN0 message configuration register 31 CAN 923 C0MCTRL00 CAN0 message control register 00 CAN 925 C0MCTRL01 CAN0 message control register 01 CAN 925 C0MCTRL02 CAN0 message control register 02 CAN 925 C0MCTRL03 CAN0 message control register 03 CAN 925 C0MCTRL04 CAN0 message control register 04 CAN 925 C0MCTRL05 CAN0 message control register 05 CAN 925 C0MCTRL06 CAN0 message control register 06 CAN 925 C0MCTRL07 CAN0 message control register 07 CAN 925 C0MCTRL08 CAN0 message control register 08 CAN 925 C0MCTRL09 CAN0 message control register 09 CAN 925 C0MCTRL10 CAN0 message control register 10 CAN 925 C0MCTRL11 CAN0 message control register 11 CAN 925 C0MCTRL12 CAN0 message control register 12 CAN 925 C0MCTRL13 CAN0 message control register 13 CAN 925 C0MCTRL14 CAN0 message control register 14 CAN 925 C0MCTRL15 CAN0 message control register 15 CAN 925 C0MCTRL16 CAN0 message control register 16 CAN 925 C0MCTRL17 CAN0 message control register 17 CAN 925 C0MCTRL18 CAN0 message control register 18 CAN 925 C0MCTRL19 CAN0 message control register 19 CAN 925 C0MCTRL20 CAN0 message control register 20 CAN 925 C0MCTRL21 CAN0 message control register 21 CAN 925 C0MCTRL22 CAN0 message control register 22 CAN 925 C0MCTRL23 CAN0 message control register 23 CAN 925 C0MCTRL24 CAN0 message control register 24 CAN 925 C0MCTRL25 CAN0 message control register 25 CAN 925 C0MCTRL26 CAN0 message control register 26 CAN 925 C0MCTRL27 CAN0 message control register 27 CAN 925 C0MCTRL28 CAN0 message control register 28 CAN 925 C0MCTRL29 CAN0 message control register 29 CAN 925 C0MCTRL30 CAN0 message control register 30 CAN 925 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1397 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (4/34) Symbol Name Unit Page C0MCTRL31 CAN0 message control register 31 CAN 925 C0MDATA000 CAN0 message data byte 0 register 00 CAN 920 C0MDATA001 CAN0 message data byte 0 register 01 CAN 920 C0MDATA002 CAN0 message data byte 0 register 02 CAN 920 C0MDATA003 CAN0 message data byte 0 register 03 CAN 920 C0MDATA004 CAN0 message data byte 0 register 04 CAN 920 C0MDATA005 CAN0 message data byte 0 register 05 CAN 920 C0MDATA006 CAN0 message data byte 0 register 06 CAN 920 C0MDATA007 CAN0 message data byte 0 register 07 CAN 920 C0MDATA008 CAN0 message data byte 0 register 08 CAN 920 C0MDATA009 CAN0 message data byte 0 register 09 CAN 920 C0MDATA010 CAN0 message data byte 0 register 10 CAN 920 C0MDATA0100 CAN0 message data byte 01 register 00 CAN 920 C0MDATA0101 CAN0 message data byte 01 register 01 CAN 920 C0MDATA0102 CAN0 message data byte 01 register 02 CAN 920 C0MDATA0103 CAN0 message data byte 01 register 03 CAN 920 C0MDATA0104 CAN0 message data byte 01 register 04 CAN 920 C0MDATA0105 CAN0 message data byte 01 register 05 CAN 920 C0MDATA0106 CAN0 message data byte 01 register 06 CAN 920 C0MDATA0107 CAN0 message data byte 01 register 07 CAN 920 C0MDATA0108 CAN0 message data byte 01 register 08 CAN 920 C0MDATA0109 CAN0 message data byte 01 register 09 CAN 920 C0MDATA011 CAN0 message data byte 0 register 11 CAN 920 C0MDATA0110 CAN0 message data byte 01 register 10 CAN 920 C0MDATA0111 CAN0 message data byte 01 register 11 CAN 920 C0MDATA0112 CAN0 message data byte 01 register 12 CAN 920 C0MDATA0113 CAN0 message data byte 01 register 13 CAN 920 C0MDATA0114 CAN0 message data byte 01 register 14 CAN 920 C0MDATA0115 CAN0 message data byte 01 register 15 CAN 920 C0MDATA0116 CAN0 message data byte 01 register 16 CAN 920 C0MDATA0117 CAN0 message data byte 01 register 17 CAN 920 C0MDATA0118 CAN0 message data byte 01 register 18 CAN 920 C0MDATA0119 CAN0 message data byte 01 register 19 CAN 920 C0MDATA012 CAN0 message data byte 0 register 12 CAN 920 C0MDATA0120 CAN0 message data byte 01 register 20 CAN 920 C0MDATA0121 CAN0 message data byte 01 register 21 CAN 920 C0MDATA0122 CAN0 message data byte 01 register 22 CAN 920 C0MDATA0123 CAN0 message data byte 01 register 23 CAN 920 C0MDATA0124 CAN0 message data byte 01 register 24 CAN 920 C0MDATA0125 CAN0 message data byte 01 register 25 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1398 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (5/34) Symbol Name Unit Page C0MDATA0126 CAN0 message data byte 01 register 26 CAN 920 C0MDATA0127 CAN0 message data byte 01 register 27 CAN 920 C0MDATA0128 CAN0 message data byte 01 register 28 CAN 920 C0MDATA0129 CAN0 message data byte 01 register 29 CAN 920 C0MDATA013 CAN0 message data byte 0 register 13 CAN 920 C0MDATA0130 CAN0 message data byte 01 register 30 CAN 920 C0MDATA0131 CAN0 message data byte 01 register 31 CAN 920 C0MDATA014 CAN0 message data byte 0 register 14 CAN 920 C0MDATA015 CAN0 message data byte 0 register 15 CAN 920 C0MDATA016 CAN0 message data byte 0 register 16 CAN 920 C0MDATA017 CAN0 message data byte 0 register 17 CAN 920 C0MDATA018 CAN0 message data byte 0 register 18 CAN 920 C0MDATA019 CAN0 message data byte 0 register 19 CAN 920 C0MDATA020 CAN0 message data byte 0 register 20 CAN 920 C0MDATA021 CAN0 message data byte 0 register 21 CAN 920 C0MDATA022 CAN0 message data byte 0 register 22 CAN 920 C0MDATA023 CAN0 message data byte 0 register 23 CAN 920 C0MDATA024 CAN0 message data byte 0 register 24 CAN 920 C0MDATA025 CAN0 message data byte 0 register 25 CAN 920 C0MDATA026 CAN0 message data byte 0 register 26 CAN 920 C0MDATA027 CAN0 message data byte 0 register 27 CAN 920 C0MDATA028 CAN0 message data byte 0 register 28 CAN 920 C0MDATA029 CAN0 message data byte 0 register 29 CAN 920 C0MDATA030 CAN0 message data byte 0 register 30 CAN 920 C0MDATA031 CAN0 message data byte 0 register 31 CAN 920 C0MDATA100 CAN0 message data byte 1 register 00 CAN 920 C0MDATA101 CAN0 message data byte 1 register 01 CAN 920 C0MDATA102 CAN0 message data byte 1 register 02 CAN 920 C0MDATA103 CAN0 message data byte 1 register 03 CAN 920 C0MDATA104 CAN0 message data byte 1 register 04 CAN 920 C0MDATA105 CAN0 message data byte 1 register 05 CAN 920 C0MDATA106 CAN0 message data byte 1 register 06 CAN 920 C0MDATA107 CAN0 message data byte 1 register 07 CAN 920 C0MDATA108 CAN0 message data byte 1 register 08 CAN 920 C0MDATA109 CAN0 message data byte 1 register 09 CAN 920 C0MDATA110 CAN0 message data byte 1 register 10 CAN 920 C0MDATA111 CAN0 message data byte 1 register 11 CAN 920 C0MDATA112 CAN0 message data byte 1 register 12 CAN 920 C0MDATA113 CAN0 message data byte 1 register 13 CAN 920 C0MDATA114 CAN0 message data byte 1 register 14 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1399 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (6/34) Symbol Name Unit Page C0MDATA115 CAN0 message data byte 1 register 15 CAN 920 C0MDATA116 CAN0 message data byte 1 register 16 CAN 920 C0MDATA117 CAN0 message data byte 1 register 17 CAN 920 C0MDATA118 CAN0 message data byte 1 register 18 CAN 920 C0MDATA119 CAN0 message data byte 1 register 19 CAN 920 C0MDATA120 CAN0 message data byte 1 register 20 CAN 920 C0MDATA121 CAN0 message data byte 1 register 21 CAN 920 C0MDATA122 CAN0 message data byte 1 register 22 CAN 920 C0MDATA123 CAN0 message data byte 1 register 23 CAN 920 C0MDATA124 CAN0 message data byte 1 register 24 CAN 920 C0MDATA125 CAN0 message data byte 1 register 25 CAN 920 C0MDATA126 CAN0 message data byte 1 register 26 CAN 920 C0MDATA127 CAN0 message data byte 1 register 27 CAN 920 C0MDATA128 CAN0 message data byte 1 register 28 CAN 920 C0MDATA129 CAN0 message data byte 1 register 29 CAN 920 C0MDATA130 CAN0 message data byte 1 register 30 CAN 920 C0MDATA131 CAN0 message data byte 1 register 31 CAN 920 C0MDATA200 CAN0 message data byte 2 register 00 CAN 920 C0MDATA201 CAN0 message data byte 2 register 01 CAN 920 C0MDATA202 CAN0 message data byte 2 register 02 CAN 920 C0MDATA203 CAN0 message data byte 2 register 03 CAN 920 C0MDATA204 CAN0 message data byte 2 register 04 CAN 920 C0MDATA205 CAN0 message data byte 2 register 05 CAN 920 C0MDATA206 CAN0 message data byte 2 register 06 CAN 920 C0MDATA207 CAN0 message data byte 2 register 07 CAN 920 C0MDATA208 CAN0 message data byte 2 register 08 CAN 920 C0MDATA209 CAN0 message data byte 2 register 09 CAN 920 C0MDATA210 CAN0 message data byte 2 register 10 CAN 920 C0MDATA211 CAN0 message data byte 2 register 11 CAN 920 C0MDATA212 CAN0 message data byte 2 register 12 CAN 920 C0MDATA213 CAN0 message data byte 2 register 13 CAN 920 C0MDATA214 CAN0 message data byte 2 register 14 CAN 920 C0MDATA215 CAN0 message data byte 2 register 15 CAN 920 C0MDATA216 CAN0 message data byte 2 register 16 CAN 920 C0MDATA217 CAN0 message data byte 2 register 17 CAN 920 C0MDATA218 CAN0 message data byte 2 register 18 CAN 920 C0MDATA219 CAN0 message data byte 2 register 19 CAN 920 C0MDATA220 CAN0 message data byte 2 register 20 CAN 920 C0MDATA221 CAN0 message data byte 2 register 21 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1400 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (7/34) Symbol Name Unit Page C0MDATA222 CAN0 message data byte 2 register 22 CAN 920 C0MDATA223 CAN0 message data byte 2 register 23 CAN 920 C0MDATA224 CAN0 message data byte 2 register 24 CAN 920 C0MDATA225 CAN0 message data byte 2 register 25 CAN 920 C0MDATA226 CAN0 message data byte 2 register 26 CAN 920 C0MDATA227 CAN0 message data byte 2 register 27 CAN 920 C0MDATA228 CAN0 message data byte 2 register 28 CAN 920 C0MDATA229 CAN0 message data byte 2 register 29 CAN 920 C0MDATA230 CAN0 message data byte 2 register 30 CAN 920 C0MDATA2300 CAN0 message data byte 23 register 00 CAN 920 C0MDATA2301 CAN0 message data byte 23 register 01 CAN 920 C0MDATA2302 CAN0 message data byte 23 register 02 CAN 920 C0MDATA2303 CAN0 message data byte 23 register 03 CAN 920 C0MDATA2304 CAN0 message data byte 23 register 04 CAN 920 C0MDATA2305 CAN0 message data byte 23 register 05 CAN 920 C0MDATA2306 CAN0 message data byte 23 register 06 CAN 920 C0MDATA2307 CAN0 message data byte 23 register 07 CAN 920 C0MDATA2308 CAN0 message data byte 23 register 08 CAN 920 C0MDATA2309 CAN0 message data byte 23 register 09 CAN 920 C0MDATA231 CAN0 message data byte 2 register 31 CAN 920 C0MDATA2310 CAN0 message data byte 23 register 10 CAN 920 C0MDATA2311 CAN0 message data byte 23 register 11 CAN 920 C0MDATA2312 CAN0 message data byte 23 register 12 CAN 920 C0MDATA2313 CAN0 message data byte 23 register 13 CAN 920 C0MDATA2314 CAN0 message data byte 23 register 14 CAN 920 C0MDATA2315 CAN0 message data byte 23 register 15 CAN 920 C0MDATA2316 CAN0 message data byte 23 register 16 CAN 920 C0MDATA2317 CAN0 message data byte 23 register 17 CAN 920 C0MDATA2318 CAN0 message data byte 23 register 18 CAN 920 C0MDATA2319 CAN0 message data byte 23 register 19 CAN 920 C0MDATA2320 CAN0 message data byte 23 register 20 CAN 920 C0MDATA2321 CAN0 message data byte 23 register 21 CAN 920 C0MDATA2322 CAN0 message data byte 23 register 22 CAN 920 C0MDATA2323 CAN0 message data byte 23 register 23 CAN 920 C0MDATA2324 CAN0 message data byte 23 register 24 CAN 920 C0MDATA2325 CAN0 message data byte 23 register 25 CAN 920 C0MDATA2326 CAN0 message data byte 23 register 26 CAN 920 C0MDATA2327 CAN0 message data byte 23 register 27 CAN 920 C0MDATA2328 CAN0 message data byte 23 register 28 CAN 920 C0MDATA2329 CAN0 message data byte 23 register 29 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1401 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (8/34) Symbol Name Unit Page C0MDATA2330 CAN0 message data byte 23 register 30 CAN 920 C0MDATA2331 CAN0 message data byte 23 register 31 CAN 920 C0MDATA300 CAN0 message data byte 3 register 00 CAN 920 C0MDATA301 CAN0 message data byte 3 register 01 CAN 920 C0MDATA302 CAN0 message data byte 3 register 02 CAN 920 C0MDATA303 CAN0 message data byte 3 register 03 CAN 920 C0MDATA304 CAN0 message data byte 3 register 04 CAN 920 C0MDATA305 CAN0 message data byte 3 register 05 CAN 920 C0MDATA306 CAN0 message data byte 3 register 06 CAN 920 C0MDATA307 CAN0 message data byte 3 register 07 CAN 920 C0MDATA308 CAN0 message data byte 3 register 08 CAN 920 C0MDATA309 CAN0 message data byte 3 register 09 CAN 920 C0MDATA310 CAN0 message data byte 3 register 10 CAN 920 C0MDATA311 CAN0 message data byte 3 register 11 CAN 920 C0MDATA312 CAN0 message data byte 3 register 12 CAN 920 C0MDATA313 CAN0 message data byte 3 register 13 CAN 920 C0MDATA314 CAN0 message data byte 3 register 14 CAN 920 C0MDATA315 CAN0 message data byte 3 register 15 CAN 920 C0MDATA316 CAN0 message data byte 3 register 16 CAN 920 C0MDATA317 CAN0 message data byte 3 register 17 CAN 920 C0MDATA318 CAN0 message data byte 3 register 18 CAN 920 C0MDATA319 CAN0 message data byte 3 register 19 CAN 920 C0MDATA320 CAN0 message data byte 3 register 20 CAN 920 C0MDATA321 CAN0 message data byte 3 register 21 CAN 920 C0MDATA322 CAN0 message data byte 3 register 22 CAN 920 C0MDATA323 CAN0 message data byte 3 register 23 CAN 920 C0MDATA324 CAN0 message data byte 3 register 24 CAN 920 C0MDATA325 CAN0 message data byte 3 register 25 CAN 920 C0MDATA326 CAN0 message data byte 3 register 26 CAN 920 C0MDATA327 CAN0 message data byte 3 register 27 CAN 920 C0MDATA328 CAN0 message data byte 3 register 28 CAN 920 C0MDATA329 CAN0 message data byte 3 register 29 CAN 920 C0MDATA330 CAN0 message data byte 3 register 30 CAN 920 C0MDATA331 CAN0 message data byte 3 register 31 CAN 920 C0MDATA400 CAN0 message data byte 4 register 00 CAN 920 C0MDATA401 CAN0 message data byte 4 register 01 CAN 920 C0MDATA402 CAN0 message data byte 4 register 02 CAN 920 C0MDATA403 CAN0 message data byte 4 register 03 CAN 920 C0MDATA404 CAN0 message data byte 4 register 04 CAN 920 C0MDATA405 CAN0 message data byte 4 register 05 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1402 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (9/34) Symbol Name Unit Page C0MDATA406 CAN0 message data byte 4 register 06 CAN 920 C0MDATA407 CAN0 message data byte 4 register 07 CAN 920 C0MDATA408 CAN0 message data byte 4 register 08 CAN 920 C0MDATA409 CAN0 message data byte 4 register 09 CAN 920 C0MDATA410 CAN0 message data byte 4 register 10 CAN 920 C0MDATA411 CAN0 message data byte 4 register 11 CAN 920 C0MDATA412 CAN0 message data byte 4 register 12 CAN 920 C0MDATA413 CAN0 message data byte 4 register 13 CAN 920 C0MDATA414 CAN0 message data byte 4 register 14 CAN 920 C0MDATA415 CAN0 message data byte 4 register 15 CAN 920 C0MDATA416 CAN0 message data byte 4 register 16 CAN 920 C0MDATA417 CAN0 message data byte 4 register 17 CAN 920 C0MDATA418 CAN0 message data byte 4 register 18 CAN 920 C0MDATA419 CAN0 message data byte 4 register 19 CAN 920 C0MDATA420 CAN0 message data byte 4 register 20 CAN 920 C0MDATA421 CAN0 message data byte 4 register 21 CAN 920 C0MDATA422 CAN0 message data byte 4 register 22 CAN 920 C0MDATA423 CAN0 message data byte 4 register 23 CAN 920 C0MDATA424 CAN0 message data byte 4 register 24 CAN 920 C0MDATA425 CAN0 message data byte 4 register 25 CAN 920 C0MDATA426 CAN0 message data byte 4 register 26 CAN 920 C0MDATA427 CAN0 message data byte 4 register 27 CAN 920 C0MDATA428 CAN0 message data byte 4 register 28 CAN 920 C0MDATA429 CAN0 message data byte 4 register 29 CAN 920 C0MDATA430 CAN0 message data byte 4 register 30 CAN 920 C0MDATA431 CAN0 message data byte 4 register 31 CAN 920 C0MDATA4500 CAN0 message data byte 45 register 00 CAN 920 C0MDATA4501 CAN0 message data byte 45 register 01 CAN 920 C0MDATA4502 CAN0 message data byte 45 register 02 CAN 920 C0MDATA4503 CAN0 message data byte 45 register 03 CAN 920 C0MDATA4504 CAN0 message data byte 45 register 04 CAN 920 C0MDATA4505 CAN0 message data byte 45 register 05 CAN 920 C0MDATA4506 CAN0 message data byte 45 register 06 CAN 920 C0MDATA4507 CAN0 message data byte 45 register 07 CAN 920 C0MDATA4508 CAN0 message data byte 45 register 08 CAN 920 C0MDATA4509 CAN0 message data byte 45 register 09 CAN 920 C0MDATA4510 CAN0 message data byte 45 register 10 CAN 920 C0MDATA4511 CAN0 message data byte 45 register 11 CAN 920 C0MDATA4512 CAN0 message data byte 45 register 12 CAN 920 C0MDATA4513 CAN0 message data byte 45 register 13 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1403 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (10/34) Symbol Name Unit Page C0MDATA4514 CAN0 message data byte 45 register 14 CAN 920 C0MDATA4515 CAN0 message data byte 45 register 15 CAN 920 C0MDATA4516 CAN0 message data byte 45 register 16 CAN 920 C0MDATA4517 CAN0 message data byte 45 register 17 CAN 920 C0MDATA4518 CAN0 message data byte 45 register 18 CAN 920 C0MDATA4519 CAN0 message data byte 45 register 19 CAN 920 C0MDATA4520 CAN0 message data byte 45 register 20 CAN 920 C0MDATA4521 CAN0 message data byte 45 register 21 CAN 920 C0MDATA4522 CAN0 message data byte 45 register 22 CAN 920 C0MDATA4523 CAN0 message data byte 45 register 23 CAN 920 C0MDATA4524 CAN0 message data byte 45 register 24 CAN 920 C0MDATA4525 CAN0 message data byte 45 register 25 CAN 920 C0MDATA4526 CAN0 message data byte 45 register 26 CAN 920 C0MDATA4527 CAN0 message data byte 45 register 27 CAN 920 C0MDATA4528 CAN0 message data byte 45 register 28 CAN 920 C0MDATA4529 CAN0 message data byte 45 register 29 CAN 920 C0MDATA4530 CAN0 message data byte 45 register 30 CAN 920 C0MDATA4531 CAN0 message data byte 45 register 31 CAN 920 C0MDATA500 CAN0 message data byte 5 register 00 CAN 920 C0MDATA501 CAN0 message data byte 5 register 01 CAN 920 C0MDATA502 CAN0 message data byte 5 register 02 CAN 920 C0MDATA503 CAN0 message data byte 5 register 03 CAN 920 C0MDATA504 CAN0 message data byte 5 register 04 CAN 920 C0MDATA505 CAN0 message data byte 5 register 05 CAN 920 C0MDATA506 CAN0 message data byte 5 register 06 CAN 920 C0MDATA507 CAN0 message data byte 5 register 07 CAN 920 C0MDATA508 CAN0 message data byte 5 register 08 CAN 920 C0MDATA509 CAN0 message data byte 5 register 09 CAN 920 C0MDATA510 CAN0 message data byte 5 register 10 CAN 920 C0MDATA511 CAN0 message data byte 5 register 11 CAN 920 C0MDATA512 CAN0 message data byte 5 register 12 CAN 920 C0MDATA513 CAN0 message data byte 5 register 13 CAN 920 C0MDATA514 CAN0 message data byte 5 register 14 CAN 920 C0MDATA515 CAN0 message data byte 5 register 15 CAN 920 C0MDATA516 CAN0 message data byte 5 register 16 CAN 920 C0MDATA517 CAN0 message data byte 5 register 17 CAN 920 C0MDATA518 CAN0 message data byte 5 register 18 CAN 920 C0MDATA519 CAN0 message data byte 5 register 19 CAN 920 C0MDATA520 CAN0 message data byte 5 register 20 CAN 920 C0MDATA521 CAN0 message data byte 5 register 21 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1404 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (11/34) Symbol Name Unit Page C0MDATA522 CAN0 message data byte 5 register 22 CAN 920 C0MDATA523 CAN0 message data byte 5 register 23 CAN 920 C0MDATA524 CAN0 message data byte 5 register 24 CAN 920 C0MDATA525 CAN0 message data byte 5 register 25 CAN 920 C0MDATA526 CAN0 message data byte 5 register 26 CAN 920 C0MDATA527 CAN0 message data byte 5 register 27 CAN 920 C0MDATA528 CAN0 message data byte 5 register 28 CAN 920 C0MDATA529 CAN0 message data byte 5 register 29 CAN 920 C0MDATA530 CAN0 message data byte 5 register 30 CAN 920 C0MDATA531 CAN0 message data byte 5 register 31 CAN 920 C0MDATA600 CAN0 message data byte 6 register 00 CAN 920 C0MDATA601 CAN0 message data byte 6 register 01 CAN 920 C0MDATA602 CAN0 message data byte 6 register 02 CAN 920 C0MDATA603 CAN0 message data byte 6 register 03 CAN 920 C0MDATA604 CAN0 message data byte 6 register 04 CAN 920 C0MDATA605 CAN0 message data byte 6 register 05 CAN 920 C0MDATA606 CAN0 message data byte 6 register 06 CAN 920 C0MDATA607 CAN0 message data byte 6 register 07 CAN 920 C0MDATA608 CAN0 message data byte 6 register 08 CAN 920 C0MDATA609 CAN0 message data byte 6 register 09 CAN 920 C0MDATA610 CAN0 message data byte 6 register 10 CAN 920 C0MDATA611 CAN0 message data byte 6 register 11 CAN 920 C0MDATA612 CAN0 message data byte 6 register 12 CAN 920 C0MDATA613 CAN0 message data byte 6 register 13 CAN 920 C0MDATA614 CAN0 message data byte 6 register 14 CAN 920 C0MDATA615 CAN0 message data byte 6 register 15 CAN 920 C0MDATA616 CAN0 message data byte 6 register 16 CAN 920 C0MDATA617 CAN0 message data byte 6 register 17 CAN 920 C0MDATA618 CAN0 message data byte 6 register 18 CAN 920 C0MDATA619 CAN0 message data byte 6 register 19 CAN 920 C0MDATA620 CAN0 message data byte 6 register 20 CAN 920 C0MDATA621 CAN0 message data byte 6 register 21 CAN 920 C0MDATA622 CAN0 message data byte 6 register 22 CAN 920 C0MDATA623 CAN0 message data byte 6 register 23 CAN 920 C0MDATA624 CAN0 message data byte 6 register 24 CAN 920 C0MDATA625 CAN0 message data byte 6 register 25 CAN 920 C0MDATA626 CAN0 message data byte 6 register 26 CAN 920 C0MDATA627 CAN0 message data byte 6 register 27 CAN 920 C0MDATA628 CAN0 message data byte 6 register 28 CAN 920 C0MDATA629 CAN0 message data byte 6 register 29 CAN 920 C0MDATA630 CAN0 message data byte 6 register 30 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1405 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (12/34) Symbol Name Unit Page C0MDATA631 CAN0 message data byte 6 register 31 CAN 920 C0MDATA6700 CAN0 message data byte 67 register 00 CAN 920 C0MDATA6701 CAN0 message data byte 67 register 01 CAN 920 C0MDATA6702 CAN0 message data byte 67 register 02 CAN 920 C0MDATA6703 CAN0 message data byte 67 register 03 CAN 920 C0MDATA6704 CAN0 message data byte 67 register 04 CAN 920 C0MDATA6705 CAN0 message data byte 67 register 05 CAN 920 C0MDATA6706 CAN0 message data byte 67 register 06 CAN 920 C0MDATA6707 CAN0 message data byte 67 register 07 CAN 920 C0MDATA6708 CAN0 message data byte 67 register 08 CAN 920 C0MDATA6709 CAN0 message data byte 67 register 09 CAN 920 C0MDATA6710 CAN0 message data byte 67 register 10 CAN 920 C0MDATA6711 CAN0 message data byte 67 register 11 CAN 920 C0MDATA6712 CAN0 message data byte 67 register 12 CAN 920 C0MDATA6713 CAN0 message data byte 67 register 13 CAN 920 C0MDATA6714 CAN0 message data byte 67 register 14 CAN 920 C0MDATA6715 CAN0 message data byte 67 register 15 CAN 920 C0MDATA6716 CAN0 message data byte 67 register 16 CAN 920 C0MDATA6717 CAN0 message data byte 67 register 17 CAN 920 C0MDATA6718 CAN0 message data byte 67 register 18 CAN 920 C0MDATA6719 CAN0 message data byte 67 register 19 CAN 920 C0MDATA6720 CAN0 message data byte 67 register 20 CAN 920 C0MDATA6721 CAN0 message data byte 67 register 21 CAN 920 C0MDATA6722 CAN0 message data byte 67 register 22 CAN 920 C0MDATA6723 CAN0 message data byte 67 register 23 CAN 920 C0MDATA6724 CAN0 message data byte 67 register 24 CAN 920 C0MDATA6725 CAN0 message data byte 67 register 25 CAN 920 C0MDATA6726 CAN0 message data byte 67 register 26 CAN 920 C0MDATA6727 CAN0 message data byte 67 register 27 CAN 920 C0MDATA6728 CAN0 message data byte 67 register 28 CAN 920 C0MDATA6729 CAN0 message data byte 67 register 29 CAN 920 C0MDATA6730 CAN0 message data byte 67 register 30 CAN 920 C0MDATA6731 CAN0 message data byte 67 register 31 CAN 920 C0MDATA700 CAN0 message data byte 7 register 00 CAN 920 C0MDATA701 CAN0 message data byte 7 register 01 CAN 920 C0MDATA702 CAN0 message data byte 7 register 02 CAN 920 C0MDATA703 CAN0 message data byte 7 register 03 CAN 920 C0MDATA704 CAN0 message data byte 7 register 04 CAN 920 C0MDATA705 CAN0 message data byte 7 register 05 CAN 920 C0MDATA706 CAN0 message data byte 7 register 06 CAN 920 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1406 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (13/34) Symbol Name Unit Page C0MDATA707 CAN0 message data byte 7 register 07 CAN 920 C0MDATA708 CAN0 message data byte 7 register 08 CAN 920 C0MDATA709 CAN0 message data byte 7 register 09 CAN 920 C0MDATA710 CAN0 message data byte 7 register 10 CAN 920 C0MDATA711 CAN0 message data byte 7 register 11 CAN 920 C0MDATA712 CAN0 message data byte 7 register 12 CAN 920 C0MDATA713 CAN0 message data byte 7 register 13 CAN 920 C0MDATA714 CAN0 message data byte 7 register 14 CAN 920 C0MDATA715 CAN0 message data byte 7 register 15 CAN 920 C0MDATA716 CAN0 message data byte 7 register 16 CAN 920 C0MDATA717 CAN0 message data byte 7 register 17 CAN 920 C0MDATA718 CAN0 message data byte 7 register 18 CAN 920 C0MDATA719 CAN0 message data byte 7 register 19 CAN 920 C0MDATA720 CAN0 message data byte 7 register 20 CAN 920 C0MDATA721 CAN0 message data byte 7 register 21 CAN 920 C0MDATA722 CAN0 message data byte 7 register 22 CAN 920 C0MDATA723 CAN0 message data byte 7 register 23 CAN 920 C0MDATA724 CAN0 message data byte 7 register 24 CAN 920 C0MDATA725 CAN0 message data byte 7 register 25 CAN 920 C0MDATA726 CAN0 message data byte 7 register 26 CAN 920 C0MDATA727 CAN0 message data byte 7 register 27 CAN 920 C0MDATA728 CAN0 message data byte 7 register 28 CAN 920 C0MDATA729 CAN0 message data byte 7 register 29 CAN 920 C0MDATA730 CAN0 message data byte 7 register 30 CAN 920 C0MDATA731 CAN0 message data byte 7 register 31 CAN 920 C0MDLC00 CAN0 message data length register 00 CAN 922 C0MDLC01 CAN0 message data length register 01 CAN 922 C0MDLC02 CAN0 message data length register 02 CAN 922 C0MDLC03 CAN0 message data length register 03 CAN 922 C0MDLC04 CAN0 message data length register 04 CAN 922 C0MDLC05 CAN0 message data length register 05 CAN 922 C0MDLC06 CAN0 message data length register 06 CAN 922 C0MDLC07 CAN0 message data length register 07 CAN 922 C0MDLC08 CAN0 message data length register 08 CAN 922 C0MDLC09 CAN0 message data length register 09 CAN 922 C0MDLC10 CAN0 message data length register 10 CAN 922 C0MDLC11 CAN0 message data length register 11 CAN 922 C0MDLC12 CAN0 message data length register 12 CAN 922 C0MDLC13 CAN0 message data length register 13 CAN 922 C0MDLC14 CAN0 message data length register 14 CAN 922 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1407 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (14/34) Symbol Name Unit Page C0MDLC15 CAN0 message data length register 15 CAN 922 C0MDLC16 CAN0 message data length register 16 CAN 922 C0MDLC17 CAN0 message data length register 17 CAN 922 C0MDLC18 CAN0 message data length register 18 CAN 922 C0MDLC19 CAN0 message data length register 19 CAN 922 C0MDLC20 CAN0 message data length register 20 CAN 922 C0MDLC21 CAN0 message data length register 21 CAN 922 C0MDLC22 CAN0 message data length register 22 CAN 922 C0MDLC23 CAN0 message data length register 23 CAN 922 C0MDLC24 CAN0 message data length register 24 CAN 922 C0MDLC25 CAN0 message data length register 25 CAN 922 C0MDLC26 CAN0 message data length register 26 CAN 922 C0MDLC27 CAN0 message data length register 27 CAN 922 C0MDLC28 CAN0 message data length register 28 CAN 922 C0MDLC29 CAN0 message data length register 29 CAN 922 C0MDLC30 CAN0 message data length register 30 CAN 922 C0MDLC31 CAN0 message data length register 31 CAN 922 C0MIDH00 CAN0 message identifier register 00H CAN 924 C0MIDH01 CAN0 message identifier register 01H CAN 924 C0MIDH02 CAN0 message identifier register 02H CAN 924 C0MIDH03 CAN0 message identifier register 03H CAN 924 C0MIDH04 CAN0 message identifier register 04H CAN 924 C0MIDH05 CAN0 message identifier register 05H CAN 924 C0MIDH06 CAN0 message identifier register 06H CAN 924 C0MIDH07 CAN0 message identifier register 07H CAN 924 C0MIDH08 CAN0 message identifier register 08H CAN 924 C0MIDH09 CAN0 message identifier register 09H CAN 924 C0MIDH10 CAN0 message identifier register 10H CAN 924 C0MIDH11 CAN0 message identifier register 11H CAN 924 C0MIDH12 CAN0 message identifier register 12H CAN 924 C0MIDH13 CAN0 message identifier register 13H CAN 924 C0MIDH14 CAN0 message identifier register 14H CAN 924 C0MIDH15 CAN0 message identifier register 15H CAN 924 C0MIDH16 CAN0 message identifier register 16H CAN 924 C0MIDH17 CAN0 message identifier register 17H CAN 924 C0MIDH18 CAN0 message identifier register 18H CAN 924 C0MIDH19 CAN0 message identifier register 19H CAN 924 C0MIDH20 CAN0 message identifier register 20H CAN 924 C0MIDH21 CAN0 message identifier register 21H CAN 924 C0MIDH22 CAN0 message identifier register 22H CAN 924 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1408 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (15/34) Symbol Name Unit Page C0MIDH23 CAN0 message identifier register 23H CAN 924 C0MIDH24 CAN0 message identifier register 24H CAN 924 C0MIDH25 CAN0 message identifier register 25H CAN 924 C0MIDH26 CAN0 message identifier register 26H CAN 924 C0MIDH27 CAN0 message identifier register 27H CAN 924 C0MIDH28 CAN0 message identifier register 28H CAN 924 C0MIDH29 CAN0 message identifier register 29H CAN 924 C0MIDH30 CAN0 message identifier register 30H CAN 924 C0MIDH31 CAN0 message identifier register 31H CAN 924 C0MIDL00 CAN0 message identifier register 00L CAN 924 C0MIDL01 CAN0 message identifier register 01L CAN 924 C0MIDL02 CAN0 message identifier register 02L CAN 924 C0MIDL03 CAN0 message identifier register 03L CAN 924 C0MIDL04 CAN0 message identifier register 04L CAN 924 C0MIDL05 CAN0 message identifier register 05L CAN 924 C0MIDL06 CAN0 message identifier register 06L CAN 924 C0MIDL07 CAN0 message identifier register 07L CAN 924 C0MIDL08 CAN0 message identifier register 08L CAN 924 C0MIDL09 CAN0 message identifier register 09L CAN 924 C0MIDL10 CAN0 message identifier register 10L CAN 924 C0MIDL11 CAN0 message identifier register 11L CAN 924 C0MIDL12 CAN0 message identifier register 12L CAN 924 C0MIDL13 CAN0 message identifier register 13L CAN 924 C0MIDL14 CAN0 message identifier register 14L CAN 924 C0MIDL15 CAN0 message identifier register 15L CAN 924 C0MIDL16 CAN0 message identifier register 16L CAN 924 C0MIDL17 CAN0 message identifier register 17L CAN 924 C0MIDL18 CAN0 message identifier register 18L CAN 924 C0MIDL19 CAN0 message identifier register 19L CAN 924 C0MIDL20 CAN0 message identifier register 20L CAN 924 C0MIDL21 CAN0 message identifier register 21L CAN 924 C0MIDL22 CAN0 message identifier register 22L CAN 924 C0MIDL23 CAN0 message identifier register 23L CAN 924 C0MIDL24 CAN0 message identifier register 24L CAN 924 C0MIDL25 CAN0 message identifier register 25L CAN 924 C0MIDL26 CAN0 message identifier register 26L CAN 924 C0MIDL27 CAN0 message identifier register 27L CAN 924 C0MIDL28 CAN0 message identifier register 28L CAN 924 C0MIDL29 CAN0 message identifier register 29L CAN 924 C0MIDL30 CAN0 message identifier register 30L CAN 924 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1409 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (16/34) Symbol Name Unit Page C0MIDL31 CAN0 message identifier register 31L CAN 924 C0RGPT CAN0 module receive history list register CAN 915 C0TGPT CAN0 module transmit history list register CAN 917 C0TS CAN0 module time stamp register CAN 918 CCLS CPU operation clock status register CG 160 CF0CTL0 CSIF0 control register 0 CSIF 720 CF0CTL1 CSIF0 control register 1 CSIF 723 CF0CTL2 CSIF0 control register 2 CSIF 724 CF0RIC Interrupt control register INTC 1222 CF0RX CSIF0 receive data register CSIF 718 CF0RXL CSIF0 receive data register L CSIF 718 CF0STR CSIF0 status register CSIF 726 CF0TIC Interrupt control register INTC 1222 CF0TX CSIF0 transmit data register CSIF 719 CF0TXL CSIF0 transmit data register L CSIF 719 CF2CTL0 CSIF2 control register 0 CSIF 720 CF2CTL1 CSIF2 control register 1 CSIF 723 CF2CTL2 CSIF2 control register 2 CSIF 724 CF2RIC Interrupt control register INTC 1222 CF2RX CSIF2 receive data register CSIF 718 CF2RXL CSIF2 receive data register L CSIF 718 CF2STR CSIF2 status register CSIF 726 CF2TIC Interrupt control register INTC 1222 CF2TX CSIF2 transmit data register CSIF 719 CF2TXL CSIF2 transmit data register L CSIF 719 CF3CTL0 CSIF3 control register 0 CSIF 720 CF3CTL1 CSIF3 control register 1 CSIF 723 CF3CTL2 CSIF3 control register 2 CSIF 724 CF3RIC Interrupt control register INTC 1222 CF3RX CSIF3 receive data register CSIF 718 CF3RXL CSIF3 receive data register L CSIF 718 CF3STR CSIF3 status register CSIF 726 CF3TIC Interrupt control register INTC 1222 CF3TX CSIF3 transmit data register CSIF 719 CF3TXL CSIF3 transmit data register L CSIF 719 CF4CTL0 CSIF4 control register 0 CSIF 720 CF4CTL1 CSIF4 control register 1 CSIF 723 CF4CTL2 CSIF4 control register 2 CSIF 724 CF4RIC Interrupt control register INTC 1222 CF4RX CSIF4 receive data register CSIF 718 CF4RXL CSIF4 receive data register L CSIF 718 CF4STR CSIF4 status register CSIF 726 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1410 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (17/34) Symbol Name Unit Page CF4TIC Interrupt control register INTC 1222 CF4TX CSIF4 transmit data register CSIF 719 CF4TXL CSIF4 transmit data register L CSIF 719 CKC Clock control register CG 163 CLM Clock monitor mode register CLM 1279 CPUBCTL CPU I/F bus control register USBF 1123 CRCD CRC data register CRC 1290 CRCIN CRC input register CRC 1290 CTBP CALLT base pointer CPU 64 CTPC CALLT execution status saving register CPU 63 CTPSW CALLT execution status saving register CPU 63 DA0CS0 D/A conversion value setting register 0 DAC 669 DA0M D/A converter mode register DAC 668 DADC0 DMA addressing control register 0 DMAC 1191 DADC1 DMA addressing control register 1 DMAC 1191 DADC2 DMA addressing control register 2 DMAC 1191 DADC3 DMA addressing control register 3 DMAC 1191 DBC0 DMA transfer count register 0 DMAC 1190 DBC1 DMA transfer count register 1 DMAC 1190 DBC2 DMA transfer count register 2 DMAC 1190 DBC3 DMA transfer count register 3 DMAC 1190 DBPC Exception/debug trap status saving register CPU 64 DBPSW Exception/debug trap status saving register CPU 64 DCHC0 DMA channel control register 0 DMAC 1192 DCHC1 DMA channel control register 1 DMAC 1192 DCHC2 DMA channel control register 2 DMAC 1192 DCHC3 DMA channel control register 3 DMAC 1192 DDA0H DMA destination address register 0H DMAC 1189 DDA0L DMA destination address register 0L DMAC 1189 DDA1H DMA destination address register 1H DMAC 1189 DDA1L DMA destination address register 1L DMAC 1189 DDA2H DMA destination address register 2H DMAC 1189 DDA2L DMA destination address register 2L DMAC 1189 DDA3H DMA destination address register 3H DMAC 1189 DDA3L DMA destination address register 3L DMAC 1189 DMAIC0 Interrupt control register INTC 1222 DMAIC1 Interrupt control register INTC 1222 DMAIC2 Interrupt control register INTC 1222 DMAIC3 Interrupt control register INTC 1222 DSA0H DMA source address register 0H DMAC 1188 DSA0L DMA source address register 0L DMAC 1188 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1411 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (18/34) Symbol Name Unit Page DSA1H DMA source address register 1H DMAC 1188 DSA1L DMA source address register 1L DMAC 1188 DSA2H DMA source address register 2H DMAC 1188 DSA2L DMA source address register 2L DMAC 1188 DSA3H DMA source address register 3H DMAC 1188 DSA3L DMA source address register 3L DMAC 1188 DTFR0 DMA trigger factor register 0 DMAC 1193 DTFR1 DMA trigger factor register 1 DMAC 1193 DTFR2 DMA trigger factor register 2 DMAC 1193 DTFR3 DMA trigger factor register 3 DMAC 1193 DWC0 Data wait control register 0 BCU 1011 ECR Interrupt source register CPU 61 EIPC Interrupt status saving register CPU 60 EIPSW Interrupt status saving register CPU 60 EPCCLT EPC macro control register USBF 1122 EPRMK EPRAM mask register USBF 1010 ERRIC0 Interrupt control register INTC 12225 FEPC NMI status saving register CPU 61 FEPSW NMI status saving register CPU 61 HZA0CTL0 High-impedance output control register 0 Motor 538 HZA0CTL1 High-impedance output control register 1 Motor 538 IIC0 IIC1 IICC0 IICC1 IICCL0 IICCL1 IIC shift register 0 IIC shift register 1 IIC control register 0 IIC control register 1 IIC clock select register 0 IIC clock select register 1 2 786 2 786 2 773 2 773 2 783 2 783 2 781 2 IC IC IC IC IC IC IICF0 IIC flag register 0 IC IICF1 IIC flag register 1 IC 781 IICIC0 Interrupt control register INTC 1222 IICIC1 Interrupt control register INTC 1222 IICS0 IICS1 IICX0 IICX1 IIC status register 0 IIC status register 1 IIC function expansion register 0 IIC function expansion register 1 2 778 2 778 2 784 2 784 IC IC IC IC IMR0 Interrupt mask register 0 INTC 1225 IMR0H Interrupt mask register 0H INTC 1225 IMR0L Interrupt mask register 0L INTC 1225 IMR1 Interrupt mask register 1 INTC 1225 IMR1H Interrupt mask register 1H INTC 1225 IMR1L Interrupt mask register 1L INTC 1225 IMR2 Interrupt mask register 2 INTC 1225 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1412 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (19/34) Symbol IMR2H Name Interrupt mask register 2H Unit INTC Page 1225 IMR2L Interrupt mask register 2L INTC 1225 IMR3 Interrupt mask register 3 INTC 1225 IMR3H Interrupt mask register 3H INTC 1225 IMR3L Interrupt mask register 3L INTC 1225 IMR4 Interrupt mask register 4 INTC 1225 IMR4H Interrupt mask register 4H INTC 1225 IMR4L Interrupt mask register 4L INTC 1225 IMR5 Interrupt mask register 5 INTC 1225 IMR5H Interrupt mask register 5H INTC 1225 IMR5L Interrupt mask register 5L INTC 1225 INTF0 External falling edge specification register 0 INTC 1237 INTF3 External falling edge specification register 3 INTC 1238 INTF4 External falling edge specification register 4 INTC 1239 INTF5 External falling edge specification register 5 INTC 1240 INTF9 External falling edge specification register 9 INTC 1241 INTF9H External falling edge specification register 9H INTC 1241 INTF9L External falling edge specification register 9L INTC 1241 INTNFC Noise elimination control register INTC 1242 INTR0 External rising edge specification register 0 INTC 1237 INTR3 External rising edge specification register 3 INTC 1238 INTR4 External rising edge specification register 4 INTC 1239 INTR5 External rising edge specification register 5 INTC 1240 INTR9 External rising edge specification register 9 INTC 1241 INTR9H External rising edge specification register 9H INTC 1241 INTR9L External rising edge specification register 9L INTC 1241 ISPR In-service priority register INTC 1222 KRIC Interrupt control register INTC 1222 KRM Key return mode register KR 1246 LOCKR Lock register CG 164 LVIIC Interrupt control register INTC 1222 LVIM Low-voltage detection register LVI 1284 OCDM On-chip debug mode register DCU 1335 2 786 2 OCKS0 IIC division clock select register 0 IC OCKS1 IIC division clock select register 1 IC 786 OSTS Oscillation stabilization time select register Standby 1251 P0 Port 0 register Port 108 P1 Port 1 register Port 113 P3 Port 3 register Port 115 P4 Port 4 register Port 121 P5 Port 5 register Port 125 P6 Port 6 register Port 130 P7H Port 7 register H Port 133 P7L Port 7 register L Port 133 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1413 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (20/34) Symbol P9 Name Unit Page Port 9 register Port 136 P9H Port 9 register H Port 136 P9L Port 9 register L Port 136 PDL Port DL register Port 143 PDLH Port DL register H Port 143 PDLL Port DL register L Port 143 PF0 Port 0 function register Port 112 PF3 Port 3 function register Port 120 PF4 Port 4 function register Port 123 PF5 Port 5 function register Port 129 PFC0 Port 0 function control register Port 111 PFC3 Port 3 function control register Port 117 PFC4 Port 4 function control register Port 122 PFC5 Port 5 function control register Port 127 PFC6 Port 6 function control register Port 132 PFC9 Port 9 function control register Port 138 PFC9H Port 9 function control register H Port 138 PFC9L Port 9 function control register L Port 138 PFCE0 Port 0 function control expansion register Port 111 PFCE3 Port 3 function control expansion register Port 117 PFCE4 Port 4 function control expansion register Port 122 PFCE5 Port 5 function control expansion register Port 127 PFCE6 Port 6 function control expansion register Port 132 PFCE9 Port 9 function control expansion register Port 139 PFCE9H Port 9 function control expansion register H Port 139 PFCE9L Port 9 function control expansion register L Port 139 PIC02 Interrupt control register INTC 1222 PIC05 Interrupt control register INTC 1222 PIC07 Interrupt control register INTC 1222 PIC08 Interrupt control register INTC 1222 PIC09 Interrupt control register INTC 1222 PIC10 Interrupt control register INTC 1222 PIC11 Interrupt control register INTC 1222 PIC14 Interrupt control register INTC 1222 PIC15 Interrupt control register INTC 1222 PIC16 Interrupt control register INTC 1222 PLLCTL PLL control register CG 162 PLLS PLL lockup time specification register CG 165 PM0 Port 0 mode register Port 109 PM1 Port 1 mode register Port 113 PM3 Port 3 mode register Port 115 PM4 Port 4 mode register Port 121 PM5 Port 5 mode register Port 125 PM6 Port 6 mode register Port 131 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1414 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (21/34) Symbol PM7H Name Port 7 mode register H Unit Port Page 134 PM7L Port 7 mode register L Port 134 PM9 Port 9 mode register Port 137 PM9H Port 9 mode register H Port 137 PM9L Port 9 mode register L Port 137 PMC0 Port 0 mode control register Port 110 PMC3 Port 3 mode control register Port 116 PMC4 Port 4 mode control register Port 122 PMC5 Port 5 mode control register Port 126 PMC6 Port 6 mode control register Port 131 PMC9 Port 9 mode control register Port 137 PMC9H Port 9 mode control register H Port 137 PMC9L Port 9 mode control register L Port 137 PMDL Port DL mode register Port 143 PMDLH Port DL mode register H Port 143 PMDLL Port DL mode register L Port 143 PRCMD Command register CPU 93 PRSCM0 Prescaler compare register 0 BRG 606 PRSCM1 Prescaler compare register 1 BRG 763 PRSCM2 Prescaler compare register 2 BRG 763 PRSCM3 Prescaler compare register 3 BRG 763 PRSM0 Prescaler mode register 0 BRG 605 PRSM1 Prescaler mode register 1 BRG 762 PRSM2 Prescaler mode register 2 BRG 762 PRSM3 Prescaler mode register 3 BRG 762 PSC Power save control register CG 1249 PSMR Power save mode register CG 1250 PSW Program status word CPU 62 r0-r31 General-purpose registers CPU 58 RAMS Internal RAM data status register LVI 1285 RC1ALH Alarm hour setting register RTC 603 RC1ALM Alarm minute setting register RTC 603 RC1ALW Alarm day-of week setting register RTC 604 RC1CC0 Real-time counter control register 0 RTC 592 RC1CC1 Real-time counter control register 1 RTC 592 RC1CC2 Real-time counter control register 2 RTC 594 RC1CC3 Real-time counter control register 3 RTC 595 RC1DAY Day count register RTC 599 RC1HOUR Hour count register RTC 597 RC1MIN Minute count register RTC 597 RC1MONTH Month count register RTC 601 RC1SEC Second count register RTC 596 RC1SUBC Sub-count register RTC 596 RC1SUBU Watch error correction register RTC 602 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1415 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (22/34) Symbol Name Unit Page RC1WEEK Day-of-week count register RTC 600 RC1YEAR Year count register RTC 601 RCM Internal oscillation mode register CG 160 RECIC0 Interrupt control register INTC 1222 RESF Reset source flag register Reset 1270 RTBH0 Real-time output buffer register 0H RTO 626 RTBL0 Real-time output buffer register 0L RTO 626 RTC0IC Interrupt control register INTC 1222 RTC1IC Interrupt control register INTC 1222 RTC2IC Interrupt control register INTC 1222 RTPC0 Real-time output port control register 0 RTO 628 RTPM0 Real-time output port mode register 0 RTO 627 SELCNT0 Selector operation control register 0 Timer 280 SVA0 Slave address register 0 2 IC 2 787 SVA1 Slave address register 1 IC 787 SYS System status register CPU 787 TAA0CCIC0 Interrupt control register INTC 1222 TAA0CCIC1 Interrupt control register INTC 1222 TAA0CCR0 TAA0 capture/compare register 0 Timer 181 TAA0CCR1 TAA0 capture/compare register 1 Timer 183 TAA0CNT TAA0 counter read buffer register Timer 185 TAA0CTL0 TAA0 control register 0 Timer 172 TAA0CTL1 TAA0 control register 1 Timer 173 TAA0IOC0 TAA0 I/O control register 0 Timer 175 TAA0IOC1 TAA0 I/O control register 1 Timer 176 TAA0IOC2 TAA0 I/O control register 2 Timer 177 TAA0IOC4 TAA0 I/O control register 4 Timer 178 TAA0OPT0 TAA0 option register 0 Timer 179 TAA0OPT1 TAA0 option register 1 Timer 180 TAA0OVIC Interrupt control register INTC 1222 TAA1CCIC0 Interrupt control register INTC 1222 TAA1CCIC1 Interrupt control register INTC 1222 TAA1CCR0 TAA1 capture/compare register 0 Timer 181 TAA1CCR1 TAA1 capture/compare register 1 Timer 183 TAA1CNT TAA1 counter read buffer register Timer 185 TAA1CTL0 TAA1 control register 0 Timer 172 TAA1CTL1 TAA1 control register 1 Timer 173 TAA1IOC0 TAA1I/O control register 0 Timer 175 TAA1IOC1 TAA1I/O control register 1 Timer 176 TAA1IOC2 TAA1I/O control register 2 Timer 177 TAA1IOC4 TAA1I/O control register 4 Timer 178 TAA1OPT0 TAA1 option register 0 Timer 179 TAA1OVIC Interrupt control register INTC 1222 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1416 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (23/34) Symbol TAA2CCIC0 Name Interrupt control register Unit Page INTC 1222 TAA2CCIC1 Interrupt control register INTC 1222 TAA2CCR0 TAA2 capture/compare register 0 Timer 181 TAA2CCR1 TAA2 capture/compare register 1 Timer 183 TAA2CNT TAA2 counter read buffer register Timer 185 TAA2CTL0 TAA2 control register 0 Timer 172 TAA2CTL1 TAA2 control register 1 Timer 173 TAA2IOC0 TAA2 I/O control register 0 Timer 175 TAA2IOC1 TAA2 I/O control register 1 Timer 176 TAA2IOC2 TAA2 I/O control register 2 Timer 177 TAA2IOC4 TAA2 I/O control register 4 Timer 178 TAA2OPT0 TAA2 option register 0 Timer 179 TAA2OPT1 TAA2 option register 1 Timer 180 TAA2OVIC Interrupt control register INTC 1222 TAA4CCIC0 Interrupt control register INTC 1222 TAA4CCIC1 Interrupt control register INTC 1222 TAA4CCR0 TAA4 capture/compare register 0 Timer 181 TAA4CCR1 TAA4 capture/compare register 1 Timer 183 TAA4CNT TAA4 counter read buffer register Timer 185 TAA4CTL0 TAA4 control register 0 Timer 172 TAA4CTL1 TAA4 control register 1 Timer 173 TAA4OVIC Interrupt control register INTC 1222 TAB1CCIC0 Interrupt control register INTC 1222 TAB1CCIC1 Interrupt control register INTC 1222 TAB1CCIC2 Interrupt control register INTC 1222 TAB1CCIC3 Interrupt control register INTC 1222 TAB1CCR0 TAB1 capture/compare register 0 Timer 294 TAB1CCR1 TAB1 capture/compare register 1 Timer 296 TAB1CCR2 TAB1 capture/compare register 2 Timer 298 TAB1CCR3 TAB1 capture/compare register 3 Timer 300 TAB1CNT TAB1 counter read buffer register Timer 302 TAB1CTL0 TAB1 control register 0 Timer 287 TAB1CTL1 TAB1 control register 1 Timer 288 TAB1DTC TAB1 dead time compare register 1 Timer 532 TAB1IOC0 TAB1 I/O control register 0 Timer 289 TAB1IOC1 TAB1 I/O control register 1 Timer 290 TAB1IOC2 TAB1 I/O control register 2 Timer 291 TAB1IOC3 TAB1 I/O control register 3 Timer 536 TAB1IOC4 TAB1 I/O control register 4 Timer 292 TAB1OPT0 TAB1 option register 0 Timer 293 TAB1OPT1 TAB1 option register 1 Timer 533 TAB1OPT2 TAB1 option register 2 Timer 534 TAB1OVIC Interrupt control register INTC 1222 TANFC Noise elimination control register Timer 186 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1417 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (24/34) Symbol Name Unit Page TM0CMP0 TMM0 compare register 0 Timer 520 TM0CTL0 TMM0 control register 0 Timer 521 TM0EQIC0 Interrupt control register INTC 1222 TM1CMP0 TMM1 compare register 0 Timer 520 TM1CTL0 TMM1 control register 0 Timer 521 TM1EQIC0 Interrupt control register INTC 1222 TM2CMP0 TMM2 compare register 0 Timer 520 TM2CTL0 TMM2 control register 0 Timer 521 TM2EQIC0 Interrupt control register INTC 1222 TM3CMP0 TMM3 compare register 0 Timer 520 TM3CTL0 TMM3 control register 0 Timer 521 TM3EQIC0 Interrupt control register INTC 1222 TTNFC Noise elimination control register Timer 410 TRXIC0 Interrupt control register INTC 1222 TT0CCIC0 Interrupt control register INTC 1222 TT0CCIC1 Interrupt control register INTC 1222 TT0CCR0 TMT0 capture/compare register 0 Timer 405 TT0CCR1 TMT0 capture/compare register 1 Timer 407 TT0CNT TMT0 counter read buffer register Timer 409 TT0CTL0 TMT0 control register 0 Timer 391 TT0CTL1 TMT0 control register 1 Timer 392 TT0CTL2 TMT0 control register 2 Timer 394 TT0IECIC Interrupt control register INTC 1222 TT0IOC0 TMT0 I/O control register 0 Timer 396 TT0IOC1 TMT0 I/O control register 1 Timer 398 TT0IOC2 TMT0 I/O control register 2 Timer 399 TT0IOC3 TMT0 I/O control register 3 Timer 400 TT0OPT0 TMT0 option register 0 Timer 402 TT0OPT1 TMT0 option register 1 Timer 403 TT0OVIC Interrupt control register INTC 1222 TT0TCW TMT0 count write register Timer 409 UC0CTL0 UARTC0 control register 0 UARTC 679 UC0CTL1 UARTC0 control register 1 UARTC 707 UC0CTL2 UARTC0 control register 2 UARTC 708 UC0OPT0 UARTC0 option control register 0 UARTC 681 UC0OPT1 UARTC0 option control register 1 UARTC 683 UC0RIC Interrupt control register INTC 1222 UC0RX UARTC0 receive data register UARTC 687 UC0RXL UARTC0 receive data register L UARTC 687 UC0STR UARTC0 status register UARTC 685 UC0TIC Interrupt control register INTC 1222 UC0TX UARTC0 transmit data register UARTC 688 UC0TX UARTC0 transmit data register L UARTC 688 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1418 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (25/34) Symbol Name Unit Page UC2CTL0 UARTC2 control register 0 UARTC 679 UC2CTL1 UARTC2 control register 1 UARTC 707 UC2CTL2 UARTC2 control register 2 UARTC 708 UC2OPT0 UARTC2 option control register 0 UARTC 681 UC2OPT1 UARTC2 option control register 1 UARTC 683 UC2RIC Interrupt control register INTC 1222 UC2RX UARTC2 receive data register UARTC 687 UC2RXL UARTC2 receive data register L UARTC 687 UC2STR UARTC2 status register UARTC 685 UC2TIC Interrupt control register INTC 1222 UC2TX UARTC2 transmit data register UARTC 688 UC2TXL UARTC2 transmit data register L UARTC 688 UC4CTL0 UARTC4 control register 0 UARTC 679 UC4CTL1 UARTC4 control register 1 UARTC 707 UC4CTL2 UARTC4 control register 2 UARTC 708 UC4OPT0 UARTC4 option control register 0 UARTC 681 UC4OPT1 UARTC4 option control register 1 UARTC 683 UC4RIC Interrupt control register INTC 1222 UC4RX UARTC4 receive data register UARTC 687 UC4RXL UARTC4 receive data register L UARTC 687 UC4STR UARTC4 status register UARTC 685 UC4TIC Interrupt control register INTC 1222 UC4TX UARTC4 transmit data register UARTC 688 UC4TXL UARTC4 transmit data register L UARTC 688 UCKSEL USB clock select register USBF 1009 UF0AAS UF0 active alternative setting register USBF 1075 UF0ADRS UF0 address register USBF 1112 UF0AIFN UF0 active interface number register USBF 1074 UF0ASS UF0 alternative setting status register USBF 1076 UF0BI1 UF0 bulk-in 1 register USBF 1095 UF0BI2 UF0 bulk-in 2 register USBF 1099 UF0BO1 UF0 bulk-out 1 register USBF 1088 UF0BO1L UF0 bulk-out 1 length register USBF 1091 UF0BO2 UF0 bulk-out 2 register USBF 1092 UF0BO2L UF0 bulk-out 2 length register USBF 1095 UF0CIE0 UF0 configuration/interface/endpoint descriptor register 0 USBF 1118 UF0CIE1 UF0 configuration/interface/endpoint descriptor register 1 USBF 1118 UF0CIE2 UF0 configuration/interface/endpoint descriptor register 2 USBF 1118 UF0CIE3 UF0 configuration/interface/endpoint descriptor register 3 USBF 1118 UF0CIE4 UF0 configuration/interface/endpoint descriptor register 4 USBF 1118 UF0CIE5 UF0 configuration/interface/endpoint descriptor register 5 USBF 1118 UF0CIE6 UF0 configuration/interface/endpoint descriptor register 6 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1419 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (26/34) Symbol Name Unit Page UF0CIE8 UF0 configuration/interface/endpoint descriptor register 8 USBF 1118 UF0CIE9 UF0 configuration/interface/endpoint descriptor register 9 USBF 1118 UF0CIE10 UF0 configuration/interface/endpoint descriptor register 10 USBF 1118 UF0CIE11 UF0 configuration/interface/endpoint descriptor register 11 USBF 1118 UF0CIE12 UF0 configuration/interface/endpoint descriptor register 12 USBF 1118 UF0CIE13 UF0 configuration/interface/endpoint descriptor register 13 USBF 1118 UF0CIE14 UF0 configuration/interface/endpoint descriptor register 14 USBF 1118 UF0CIE15 UF0 configuration/interface/endpoint descriptor register 15 USBF 1118 UF0CIE16 UF0 configuration/interface/endpoint descriptor register 16 USBF 1118 UF0CIE17 UF0 configuration/interface/endpoint descriptor register 17 USBF 1118 UF0CIE18 UF0 configuration/interface/endpoint descriptor register 18 USBF 1118 UF0CIE19 UF0 configuration/interface/endpoint descriptor register 19 USBF 1118 UF0CIE20 UF0 configuration/interface/endpoint descriptor register 20 USBF 1118 UF0CIE21 UF0 configuration/interface/endpoint descriptor register 21 USBF 1118 UF0CIE22 UF0 configuration/interface/endpoint descriptor register 22 USBF 1118 UF0CIE23 UF0 configuration/interface/endpoint descriptor register 23 USBF 1118 UF0CIE24 UF0 configuration/interface/endpoint descriptor register 24 USBF 1118 UF0CIE25 UF0 configuration/interface/endpoint descriptor register 25 USBF 1118 UF0CIE26 UF0 configuration/interface/endpoint descriptor register 26 USBF 1118 UF0CIE27 UF0 configuration/interface/endpoint descriptor register 27 USBF 1118 UF0CIE28 UF0 configuration/interface/endpoint descriptor register 28 USBF 1118 UF0CIE29 UF0 configuration/interface/endpoint descriptor register 29 USBF 1118 UF0CIE30 UF0 configuration/interface/endpoint descriptor register 30 USBF 1118 UF0CIE31 UF0 configuration/interface/endpoint descriptor register 31 USBF 1118 UF0CIE32 UF0 configuration/interface/endpoint descriptor register 32 USBF 1118 UF0CIE33 UF0 configuration/interface/endpoint descriptor register 33 USBF 1118 UF0CIE34 UF0 configuration/interface/endpoint descriptor register 34 USBF 1118 UF0CIE35 UF0 configuration/interface/endpoint descriptor register 35 USBF 1118 UF0CIE36 UF0 configuration/interface/endpoint descriptor register 36 USBF 1118 UF0CIE37 UF0 configuration/interface/endpoint descriptor register 37 USBF 1118 UF0CIE38 UF0 configuration/interface/endpoint descriptor register 38 USBF 1118 UF0CIE39 UF0 configuration/interface/endpoint descriptor register 39 USBF 1118 UF0CIE40 UF0 configuration/interface/endpoint descriptor register 40 USBF 1118 UF0CIE41 UF0 configuration/interface/endpoint descriptor register 41 USBF 1118 UF0CIE42 UF0 configuration/interface/endpoint descriptor register 42 USBF 1118 UF0CIE43 UF0 configuration/interface/endpoint descriptor register 43 USBF 1118 UF0CIE44 UF0 configuration/interface/endpoint descriptor register 44 USBF 1118 UF0CIE45 UF0 configuration/interface/endpoint descriptor register 45 USBF 1118 UF0CIE46 UF0 configuration/interface/endpoint descriptor register 46 USBF 1118 UF0CIE47 UF0 configuration/interface/endpoint descriptor register 47 USBF 1118 UF0CIE48 UF0 configuration/interface/endpoint descriptor register 48 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1420 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (27/34) Symbol Name Unit Page UF0CIE49 UF0 configuration/interface/endpoint descriptor register 49 USBF 1118 UF0CIE50 UF0 configuration/interface/endpoint descriptor register 50 USBF 1118 UF0CIE51 UF0 configuration/interface/endpoint descriptor register 51 USBF 1118 UF0CIE52 UF0 configuration/interface/endpoint descriptor register 52 USBF 1118 UF0CIE53 UF0 configuration/interface/endpoint descriptor register 53 USBF 1118 UF0CIE54 UF0 configuration/interface/endpoint descriptor register 54 USBF 1118 UF0CIE55 UF0 configuration/interface/endpoint descriptor register 55 USBF 1118 UF0CIE56 UF0 configuration/interface/endpoint descriptor register 56 USBF 1118 UF0CIE57 UF0 configuration/interface/endpoint descriptor register 57 USBF 1118 UF0CIE58 UF0 configuration/interface/endpoint descriptor register 58 USBF 1118 UF0CIE59 UF0 configuration/interface/endpoint descriptor register 59 USBF 1118 UF0CIE60 UF0 configuration/interface/endpoint descriptor register 60 USBF 1118 UF0CIE61 UF0 configuration/interface/endpoint descriptor register 61 USBF 1118 UF0CIE62 UF0 configuration/interface/endpoint descriptor register 62 USBF 1118 UF0CIE63 UF0 configuration/interface/endpoint descriptor register 63 USBF 1118 UF0CIE64 UF0 configuration/interface/endpoint descriptor register 64 USBF 1118 UF0CIE65 UF0 configuration/interface/endpoint descriptor register 65 USBF 1118 UF0CIE66 UF0 configuration/interface/endpoint descriptor register 66 USBF 1118 UF0CIE67 UF0 configuration/interface/endpoint descriptor register 67 USBF 1118 UF0CIE68 UF0 configuration/interface/endpoint descriptor register 68 USBF 1118 UF0CIE69 UF0 configuration/interface/endpoint descriptor register 69 USBF 1118 UF0CIE70 UF0 configuration/interface/endpoint descriptor register 70 USBF 1118 UF0CIE71 UF0 configuration/interface/endpoint descriptor register 71 USBF 1118 UF0CIE72 UF0 configuration/interface/endpoint descriptor register 72 USBF 1118 UF0CIE73 UF0 configuration/interface/endpoint descriptor register 73 USBF 1118 UF0CIE74 UF0 configuration/interface/endpoint descriptor register 74 USBF 1118 UF0CIE75 UF0 configuration/interface/endpoint descriptor register 75 USBF 1118 UF0CIE76 UF0 configuration/interface/endpoint descriptor register 76 USBF 1118 UF0CIE77 UF0 configuration/interface/endpoint descriptor register 77 USBF 1118 UF0CIE78 UF0 configuration/interface/endpoint descriptor register 78 USBF 1118 UF0CIE79 UF0 configuration/interface/endpoint descriptor register 79 USBF 1118 UF0CIE80 UF0 configuration/interface/endpoint descriptor register 80 USBF 1118 UF0CIE81 UF0 configuration/interface/endpoint descriptor register 81 USBF 1118 UF0CIE82 UF0 configuration/interface/endpoint descriptor register 82 USBF 1118 UF0CIE83 UF0 configuration/interface/endpoint descriptor register 83 USBF 1118 UF0CIE84 UF0 configuration/interface/endpoint descriptor register 84 USBF 1118 UF0CIE85 UF0 configuration/interface/endpoint descriptor register 85 USBF 1118 UF0CIE86 UF0 configuration/interface/endpoint descriptor register 86 USBF 1118 UF0CIE87 UF0 configuration/interface/endpoint descriptor register 87 USBF 1118 UF0CIE88 UF0 configuration/interface/endpoint descriptor register 88 USBF 1118 UF0CIE89 UF0 configuration/interface/endpoint descriptor register 89 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1421 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (28/34) Symbol Name Unit Page UF0CIE90 UF0 configuration/interface/endpoint descriptor register 90 USBF 1118 UF0CIE91 UF0 configuration/interface/endpoint descriptor register 91 USBF 1118 UF0CIE92 UF0 configuration/interface/endpoint descriptor register 92 USBF 1118 UF0CIE93 UF0 configuration/interface/endpoint descriptor register 93 USBF 1118 UF0CIE94 UF0 configuration/interface/endpoint descriptor register 94 USBF 1118 UF0CIE95 UF0 configuration/interface/endpoint descriptor register 95 USBF 1118 UF0CIE96 UF0 configuration/interface/endpoint descriptor register 96 USBF 1118 UF0CIE97 UF0 configuration/interface/endpoint descriptor register 97 USBF 1118 UF0CIE98 UF0 configuration/interface/endpoint descriptor register 98 USBF 1118 UF0CIE99 UF0 configuration/interface/endpoint descriptor register 99 USBF 1118 UF0CIE100 UF0 configuration/interface/endpoint descriptor register 100 USBF 1118 UF0CIE101 UF0 configuration/interface/endpoint descriptor register 101 USBF 1118 UF0CIE102 UF0 configuration/interface/endpoint descriptor register 102 USBF 1118 UF0CIE103 UF0 configuration/interface/endpoint descriptor register 103 USBF 1118 UF0CIE104 UF0 configuration/interface/endpoint descriptor register 104 USBF 1118 UF0CIE105 UF0 configuration/interface/endpoint descriptor register 105 USBF 1118 UF0CIE106 UF0 configuration/interface/endpoint descriptor register 106 USBF 1118 UF0CIE107 UF0 configuration/interface/endpoint descriptor register 107 USBF 1118 UF0CIE108 UF0 configuration/interface/endpoint descriptor register 108 USBF 1118 UF0CIE109 UF0 configuration/interface/endpoint descriptor register 109 USBF 1118 UF0CIE110 UF0 configuration/interface/endpoint descriptor register 110 USBF 1118 UF0CIE111 UF0 configuration/interface/endpoint descriptor register 111 USBF 1118 UF0CIE112 UF0 configuration/interface/endpoint descriptor register 112 USBF 1118 UF0CIE113 UF0 configuration/interface/endpoint descriptor register 113 USBF 1118 UF0CIE114 UF0 configuration/interface/endpoint descriptor register 114 USBF 1118 UF0CIE115 UF0 configuration/interface/endpoint descriptor register 115 USBF 1118 UF0CIE116 UF0 configuration/interface/endpoint descriptor register 116 USBF 1118 UF0CIE117 UF0 configuration/interface/endpoint descriptor register 117 USBF 1118 UF0CIE118 UF0 configuration/interface/endpoint descriptor register 118 USBF 1118 UF0CIE119 UF0 configuration/interface/endpoint descriptor register 119 USBF 1118 UF0CIE120 UF0 configuration/interface/endpoint descriptor register 120 USBF 1118 UF0CIE121 UF0 configuration/interface/endpoint descriptor register 121 USBF 1118 UF0CIE122 UF0 configuration/interface/endpoint descriptor register 122 USBF 1118 UF0CIE123 UF0 configuration/interface/endpoint descriptor register 123 USBF 1118 UF0CIE124 UF0 configuration/interface/endpoint descriptor register 124 USBF 1118 UF0CIE125 UF0 configuration/interface/endpoint descriptor register 125 USBF 1118 UF0CIE126 UF0 configuration/interface/endpoint descriptor register 126 USBF 1118 UF0CIE127 UF0 configuration/interface/endpoint descriptor register 127 USBF 1118 UF0CIE128 UF0 configuration/interface/endpoint descriptor register 128 USBF 1118 UF0CIE129 UF0 configuration/interface/endpoint descriptor register 129 USBF 1118 UF0CIE130 UF0 configuration/interface/endpoint descriptor register 130 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1422 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (29/34) Symbol Name Unit Page UF0CIE131 UF0 configuration/interface/endpoint descriptor register 131 USBF 1118 UF0CIE132 UF0 configuration/interface/endpoint descriptor register 132 USBF 1118 UF0CIE133 UF0 configuration/interface/endpoint descriptor register 133 USBF 1118 UF0CIE134 UF0 configuration/interface/endpoint descriptor register 134 USBF 1118 UF0CIE135 UF0 configuration/interface/endpoint descriptor register 135 USBF 1118 UF0CIE136 UF0 configuration/interface/endpoint descriptor register 136 USBF 1118 UF0CIE137 UF0 configuration/interface/endpoint descriptor register 137 USBF 1118 UF0CIE138 UF0 configuration/interface/endpoint descriptor register 138 USBF 1118 UF0CIE139 UF0 configuration/interface/endpoint descriptor register 139 USBF 1118 UF0CIE140 UF0 configuration/interface/endpoint descriptor register 140 USBF 1118 UF0CIE141 UF0 configuration/interface/endpoint descriptor register 141 USBF 1118 UF0CIE142 UF0 configuration/interface/endpoint descriptor register 142 USBF 1118 UF0CIE143 UF0 configuration/interface/endpoint descriptor register 143 USBF 1118 UF0CIE144 UF0 configuration/interface/endpoint descriptor register 144 USBF 1118 UF0CIE145 UF0 configuration/interface/endpoint descriptor register 145 USBF 1118 UF0CIE146 UF0 configuration/interface/endpoint descriptor register 146 USBF 1118 UF0CIE147 UF0 configuration/interface/endpoint descriptor register 147 USBF 1118 UF0CIE148 UF0 configuration/interface/endpoint descriptor register 148 USBF 1118 UF0CIE149 UF0 configuration/interface/endpoint descriptor register 149 USBF 1118 UF0CIE150 UF0 configuration/interface/endpoint descriptor register 150 USBF 1118 UF0CIE151 UF0 configuration/interface/endpoint descriptor register 151 USBF 1118 UF0CIE152 UF0 configuration/interface/endpoint descriptor register 152 USBF 1118 UF0CIE153 UF0 configuration/interface/endpoint descriptor register 153 USBF 1118 UF0CIE154 UF0 configuration/interface/endpoint descriptor register 154 USBF 1118 UF0CIE155 UF0 configuration/interface/endpoint descriptor register 155 USBF 1118 UF0CIE156 UF0 configuration/interface/endpoint descriptor register 156 USBF 1118 UF0CIE157 UF0 configuration/interface/endpoint descriptor register 157 USBF 1118 UF0CIE158 UF0 configuration/interface/endpoint descriptor register 158 USBF 1118 UF0CIE159 UF0 configuration/interface/endpoint descriptor register 159 USBF 1118 UF0CIE160 UF0 configuration/interface/endpoint descriptor register 160 USBF 1118 UF0CIE161 UF0 configuration/interface/endpoint descriptor register 161 USBF 1118 UF0CIE162 UF0 configuration/interface/endpoint descriptor register 162 USBF 1118 UF0CIE163 UF0 configuration/interface/endpoint descriptor register 163 USBF 1118 UF0CIE164 UF0 configuration/interface/endpoint descriptor register 164 USBF 1118 UF0CIE165 UF0 configuration/interface/endpoint descriptor register 165 USBF 1118 UF0CIE166 UF0 configuration/interface/endpoint descriptor register 166 USBF 1118 UF0CIE167 UF0 configuration/interface/endpoint descriptor register 167 USBF 1118 UF0CIE168 UF0 configuration/interface/endpoint descriptor register 168 USBF 1118 UF0CIE169 UF0 configuration/interface/endpoint descriptor register 169 USBF 1118 UF0CIE170 UF0 configuration/interface/endpoint descriptor register 170 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1423 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (30/34) Symbol Name Unit Page UF0CIE171 UF0 configuration/interface/endpoint descriptor register 171 USBF 1118 UF0CIE172 UF0 configuration/interface/endpoint descriptor register 172 USBF 1118 UF0CIE173 UF0 configuration/interface/endpoint descriptor register 173 USBF 1118 UF0CIE174 UF0 configuration/interface/endpoint descriptor register 174 USBF 1118 UF0CIE175 UF0 configuration/interface/endpoint descriptor register 175 USBF 1118 UF0CIE176 UF0 configuration/interface/endpoint descriptor register 176 USBF 1118 UF0CIE177 UF0 configuration/interface/endpoint descriptor register 177 USBF 1118 UF0CIE178 UF0 configuration/interface/endpoint descriptor register 178 USBF 1118 UF0CIE179 UF0 configuration/interface/endpoint descriptor register 179 USBF 1118 UF0CIE180 UF0 configuration/interface/endpoint descriptor register 180 USBF 1118 UF0CIE181 UF0 configuration/interface/endpoint descriptor register 181 USBF 1118 UF0CIE182 UF0 configuration/interface/endpoint descriptor register 182 USBF 1118 UF0CIE183 UF0 configuration/interface/endpoint descriptor register 183 USBF 1118 UF0CIE184 UF0 configuration/interface/endpoint descriptor register 184 USBF 1118 UF0CIE185 UF0 configuration/interface/endpoint descriptor register 185 USBF 1118 UF0CIE186 UF0 configuration/interface/endpoint descriptor register 186 USBF 1118 UF0CIE187 UF0 configuration/interface/endpoint descriptor register 187 USBF 1118 UF0CIE188 UF0 configuration/interface/endpoint descriptor register 188 USBF 1118 UF0CIE189 UF0 configuration/interface/endpoint descriptor register 189 USBF 1118 UF0CIE190 UF0 configuration/interface/endpoint descriptor register 190 USBF 1118 UF0CIE191 UF0 configuration/interface/endpoint descriptor register 191 USBF 1118 UF0CIE192 UF0 configuration/interface/endpoint descriptor register 192 USBF 1118 UF0CIE193 UF0 configuration/interface/endpoint descriptor register 193 USBF 1118 UF0CIE194 UF0 configuration/interface/endpoint descriptor register 194 USBF 1118 UF0CIE195 UF0 configuration/interface/endpoint descriptor register 195 USBF 1118 UF0CIE196 UF0 configuration/interface/endpoint descriptor register 196 USBF 1118 UF0CIE197 UF0 configuration/interface/endpoint descriptor register 197 USBF 1118 UF0CIE198 UF0 configuration/interface/endpoint descriptor register 198 USBF 1118 UF0CIE199 UF0 configuration/interface/endpoint descriptor register 199 USBF 1118 UF0CIE200 UF0 configuration/interface/endpoint descriptor register 200 USBF 1118 UF0CIE201 UF0 configuration/interface/endpoint descriptor register 201 USBF 1118 UF0CIE202 UF0 configuration/interface/endpoint descriptor register 202 USBF 1118 UF0CIE203 UF0 configuration/interface/endpoint descriptor register 203 USBF 1118 UF0CIE204 UF0 configuration/interface/endpoint descriptor register 204 USBF 1118 UF0CIE205 UF0 configuration/interface/endpoint descriptor register 205 USBF 1118 UF0CIE206 UF0 configuration/interface/endpoint descriptor register 206 USBF 1118 UF0CIE207 UF0 configuration/interface/endpoint descriptor register 207 USBF 1118 UF0CIE208 UF0 configuration/interface/endpoint descriptor register 208 USBF 1118 UF0CIE209 UF0 configuration/interface/endpoint descriptor register 209 USBF 1118 UF0CIE210 UF0 configuration/interface/endpoint descriptor register 210 USBF 1118 UF0CIE211 UF0 configuration/interface/endpoint descriptor register 211 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1424 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (31/34) Symbol Name Unit Page UF0CIE212 UF0 configuration/interface/endpoint descriptor register 212 USBF 1118 UF0CIE213 UF0 configuration/interface/endpoint descriptor register 213 USBF 1118 UF0CIE214 UF0 configuration/interface/endpoint descriptor register 214 USBF 1118 UF0CIE215 UF0 configuration/interface/endpoint descriptor register 215 USBF 1118 UF0CIE216 UF0 configuration/interface/endpoint descriptor register 216 USBF 1118 UF0CIE217 UF0 configuration/interface/endpoint descriptor register 217 USBF 1118 UF0CIE218 UF0 configuration/interface/endpoint descriptor register 218 USBF 1118 UF0CIE219 UF0 configuration/interface/endpoint descriptor register 219 USBF 1118 UF0CIE220 UF0 configuration/interface/endpoint descriptor register 220 USBF 1118 UF0CIE221 UF0 configuration/interface/endpoint descriptor register 221 USBF 1118 UF0CIE222 UF0 configuration/interface/endpoint descriptor register 222 USBF 1118 UF0CIE223 UF0 configuration/interface/endpoint descriptor register 223 USBF 1118 UF0CIE224 UF0 configuration/interface/endpoint descriptor register 224 USBF 1118 UF0CIE225 UF0 configuration/interface/endpoint descriptor register 225 USBF 1118 UF0CIE226 UF0 configuration/interface/endpoint descriptor register 226 USBF 1118 UF0CIE227 UF0 configuration/interface/endpoint descriptor register 227 USBF 1118 UF0CIE228 UF0 configuration/interface/endpoint descriptor register 228 USBF 1118 UF0CIE229 UF0 configuration/interface/endpoint descriptor register 229 USBF 1118 UF0CIE230 UF0 configuration/interface/endpoint descriptor register 230 USBF 1118 UF0CIE231 UF0 configuration/interface/endpoint descriptor register 231 USBF 1118 UF0CIE232 UF0 configuration/interface/endpoint descriptor register 232 USBF 1118 UF0CIE233 UF0 configuration/interface/endpoint descriptor register 233 USBF 1118 UF0CIE234 UF0 configuration/interface/endpoint descriptor register 234 USBF 1118 UF0CIE235 UF0 configuration/interface/endpoint descriptor register 235 USBF 1118 UF0CIE236 UF0 configuration/interface/endpoint descriptor register 236 USBF 1118 UF0CIE237 UF0 configuration/interface/endpoint descriptor register 237 USBF 1118 UF0CIE238 UF0 configuration/interface/endpoint descriptor register 238 USBF 1118 UF0CIE239 UF0 configuration/interface/endpoint descriptor register 239 USBF 1118 UF0CIE240 UF0 configuration/interface/endpoint descriptor register 240 USBF 1118 UF0CIE241 UF0 configuration/interface/endpoint descriptor register 241 USBF 1118 UF0CIE242 UF0 configuration/interface/endpoint descriptor register 242 USBF 1118 UF0CIE243 UF0 configuration/interface/endpoint descriptor register 243 USBF 1118 UF0CIE244 UF0 configuration/interface/endpoint descriptor register 244 USBF 1118 UF0CIE245 UF0 configuration/interface/endpoint descriptor register 245 USBF 1118 UF0CIE246 UF0 configuration/interface/endpoint descriptor register 246 USBF 1118 UF0CIE247 UF0 configuration/interface/endpoint descriptor register 247 USBF 1118 UF0CIE248 UF0 configuration/interface/endpoint descriptor register 248 USBF 1118 UF0CIE249 UF0 configuration/interface/endpoint descriptor register 249 USBF 1118 UF0CIE250 UF0 configuration/interface/endpoint descriptor register 250 USBF 1118 UF0CIE251 UF0 configuration/interface/endpoint descriptor register 251 USBF 1118 UF0CIE252 UF0 configuration/interface/endpoint descriptor register 252 USBF 1118 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1425 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (32/34) Symbol Name Unit Page UF0CIE253 UF0 configuration/interface/endpoint descriptor register 253 USBF 1118 UF0CIE254 UF0 configuration/interface/endpoint descriptor register 254 USBF 1118 UF0CIE255 UF0 configuration/interface/endpoint descriptor register 255 USBF 1118 UF0CLR UF0 CLR request register USBF 1039 UF0CNF UF0 configuration register USBF 1113 UF0DD0 UF0 device descriptor register 0 USBF 1117 UF0DD1 UF0 device descriptor register 1 USBF 1117 UF0DD2 UF0 device descriptor register 2 USBF 1117 UF0DD3 UF0 device descriptor register 3 USBF 1117 UF0DD4 UF0 device descriptor register 4 USBF 1117 UF0DD5 UF0 device descriptor register 5 USBF 1117 UF0DD6 UF0 device descriptor register 6 USBF 1117 UF0DD7 UF0 device descriptor register 7 USBF 1117 UF0DD8 UF0 device descriptor register 8 USBF 1117 UF0DD9 UF0 device descriptor register 9 USBF 1117 UF0DD10 UF0 device descriptor register 10 USBF 1117 UF0DD11 UF0 device descriptor register 11 USBF 1117 UF0DD12 UF0 device descriptor register 12 USBF 1117 UF0DD13 UF0 device descriptor register 13 USBF 1117 UF0DD14 UF0 device descriptor register 14 USBF 1117 UF0DD15 UF0 device descriptor register 15 USBF 1117 UF0DD16 UF0 device descriptor register 16 USBF 1117 UF0DD17 UF0 device descriptor register 17 USBF 1117 UF0DEND UF0 data end register USBF 1069 UF0DMS0 UF0 DMA status 0 register USBF 1065 UF0DMS1 UF0 DMA status 1 register USBF 1066 UF0DSCL UF0 descriptor length register USBF 1116 UF0DSTL UF0 device status register L USBF 1105 UF0E0L UF0 EP0 length register USBF 1083 UF0E0N UF0 EP0NAK register USBF 1030 UF0E0NA UF0 EP0NAKALL register USBF 1032 UF0E0R UF0 EP0 read register USBF 1082 UF0E0SL UF0 EP0 status register L USBF 1106 UF0E0ST UF0 EP0 setup register USBF 1084 UF0E0W UF0 EP0 write register USBF 1096 UF0E1DC1 EP1 DMA control register 1 USBF 1124 UF0E1DC2 EP1 DMA control register 2 USBF 1126 UF0E1IM UF0 endpoint 1 interface mapping register USBF 1078 UF0E1SL UF0 EP1 status register L USBF 1108 UF0E2DC1 EP2 DMA control register 1 USBF 1124 UF0E2DC2 EP2 DMA control register 2 USBF 1126 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1426 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (33/34) Symbol Name Unit Page UF0E2IM UF0 endpoint 2 interface mapping register USBF 1079 UF0E2SL UF0 EP2 status register L USBF 1109 UF0E3DC1 EP3 DMA control register 1 USBF 1124 UF0E3DC2 EP3 DMA control register 2 USBF 1126 UF0E3IM UF0 endpoint 3 interface mapping register USBF 1079 UF0E3SL UF0 EP3 status register L USBF 1109 UF0E4DC1 EP4 DMA control register 1 USBF 1124 UF0E4DC2 EP4 DMA control register 2 USBF 1126 UF0E4IM UF0 endpoint 4 interface mapping register USBF 1080 UF0E4SL UF0 EP4 status register L USBF 1100 UF0E7IM UF0 endpoint 7 interface mapping register USBF 1081 UF0E7SL UF0 EP7 status register L USBF 1111 UF0EN UF0 EPNAK register USBF 1033 UF0ENM UF0 EPNAK mask register USBF 1037 UF0EP1BI UF0 EP1 bulk-in transfer data register USBF 1128 UF0EP2BO UF0 EP2 bulk-out transfer data register USBF 1129 UF0EP3BI UF0 EP3 bulk-in transfer data register USBF 1128 UF0EP4BO UF0 EP4 bulk-out transfer data register USBF 1130 UF0EPS0 UF0 EP status 0 register USBF 1041 UF0EPS1 UF0 EP status 1 register USBF 1043 UF0EPS2 UF0 EP status 2 register USBF 1044 UF0FIC0 UF0 FIFO clear 0 register USBF 1067 UF0FIC1 UF0 FIFO clear 1 register USBF 1068 UF0GPR UF0 GPR register USBF 1071 UF0IC0 UF0 INT clear 0 register USBF 1058 UF0IC1 UF0 INT clear 1 register USBF 1059 UF0IC2 UF0 INT clear 2 register USBF 1060 UF0IC3 UF0 INT clear 3 register USBF 1061 UF0IC4 UF0 INT clear 4 register USBF 1062 UF0IDR UF0 INT & DMARQ register USBF 1063 UF0IF0 UF0 interface 0 register USBF 1114 UF0IF1 UF0 interface 1 register USBF 1115 UF0IF2 UF0 interface 2 register USBF 1115 UF0IF3 UF0 interface 3 register USBF 1115 UF0IF4 UF0 interface 4 register USBF 1115 UF0IM0 UF0 INT mask 0 register USBF 1053 UF0IM1 UF0 INT mask 1 register USBF 1054 UF0IM2 UF0 INT mask 2 register USBF 1055 UF0IM3 UF0 INT mask 3 register USBF 1056 UF0IM4 UF0 INT mask 4 register USBF 1057 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1427 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX B REGISTER INDEX (34/34) Symbol Name Unit Page UF0INT1 UF0 interrupt 1 register USBF 1103 UF0IS0 UF0 INT status 0 register USBF 1045 UF0IS1 UF0 INT status 1 register USBF 1047 UF0IS2 UF0 INT status 2 register USBF 1049 UF0IS3 UF0 INT status 3 register USBF 1050 UF0IS4 UF0 INT status 4 register USBF 1052 UF0MODC UF0 mode control register USBF 1072 UF0MODS UF0 mode status register USBF 1073 UF0SDS UF0 SNDSIE register USBF 1038 UF0SET UF0 SET request register USBF 1040 UFCKMSK USB function control register USBF 1009 UFDRQEN USBF DMA request enable register USBF 1131 UFIC0 Interrupt control register INTC 1222 UFIC1 Interrupt control register INTC 1222 VSWC System wait control register CPU 95 WDTE Watchdog timer enable register WDT 623 WDTM2 Watchdog timer mode register 2 WDT 1233 WUPIC0 Interrupt control register INTC 1222 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1428 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST APPENDIX C INSTRUCTION SET LIST C.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immX X bit immediate data dispX X bit displacement data regID System register number vector 5-bit data that specifies the trap vector (00H to 1FH) cccc 4-bit data that shows the conditions code sp Stack pointer (r3) ep Element pointer (r30) listX X item register list (2) Register symbols used to describe opcodes Register Symbol Explanation R 1-bit data of a code that specifies reg1 or regID r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data I 1-bit immediate data (indicates the higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes CCCC 4-bit data that shows the condition codes of Bcond instruction bbb 3-bit data for specifying the bit number L 1-bit data that specifies a program register in the register list R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1429 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a. store-memory (a, b, c) Write data b into address a in size c. load-memory-bit (a, b) Read bit b of address a. store-memory-bit (a, b, c) Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). saturated (n) If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Reflects the results in a flag. Byte Byte (8 bits) Halfword Half word (16 bits) Word Word (32 bits) + Addition - Subtraction ll Bit concatenation x Multiplication / Division % Remainder from division results AND Logical product OR Logical sum XOR Exclusive OR NOT Logical negation logically shift left by Logical shift left logically shift right by Logical shift right arithmetically shift right by Arithmetic shift right (4) Register symbols used in execution clock Register Symbol Explanation i If executing another instruction immediately after executing the first instruction (issue). r If repeating execution of the same instruction immediately after executing the first instruction (repeat). l If using the results of instruction execution in the instruction immediately after the execution (latency). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1430 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change 0 Clear to 0 X Set or cleared in accordance with the results. R Previously saved values are restored. (6) Condition codes Condition Code Condition Formula Explanation (cccc) 0 0 0 0 OV = 1 Overflow 1 0 0 0 OV = 0 No overflow 0 0 0 1 CY = 1 Carry Lower (Less than) 1 0 0 1 CY = 0 No carry Not lower (Greater than or equal) 0 0 1 0 Z=1 Zero 1 0 1 0 Z=0 Not zero 0 0 1 1 (CY or Z) = 1 Not higher (Less than or equal) 1 0 1 1 (CY or Z) = 0 Higher (Greater than) 0 1 0 0 S=1 Negative 1 1 0 0 S=0 Positive 0 1 0 1 - Always (Unconditional) 1 1 0 1 SAT = 1 Saturated 0 1 1 0 (S xor OV) = 1 Less than signed 1 1 1 0 (S xor OV) = 0 Greater than or equal signed 0 1 1 1 ((S xor OV) or Z) = 1 Less than or equal signed 1 1 1 1 ((S xor OV) or Z) = 0 Greater than signed R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1431 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Execution Operation Flags Clock ADD ADDI i r l CY OV S Z SAT reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]GR[reg2]+GR[reg1] 1 1 1 x x x x imm5,reg2 rrrrr010010iiiii GR[reg2]GR[reg2]+sign-extend(imm5) 1 1 1 x x x x imm16,reg1,reg2 r r rr r1 10 00 0 R RRR R GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 x x x x i i i i i i i i i i i i i i i i AND reg1,reg2 r r rr r0 01 01 0 RRRRR GR[reg2]GR[reg2]AND GR[reg1] 1 1 1 0 x x ANDI imm16,reg1,reg2 r r rr r1 10 11 0 R RRR R GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 0 x x 2 2 2 i i i i i i i i i i i i i i i i Bcond disp9 ddddd1011dddcccc Note 1 if conditions are satisfied When conditions then PCPC+sign-extend(disp9) are satisfied When conditions Note 2 Note 2 Note 2 1 1 1 1 1 1 x 0 x x 1 1 1 x 0 x x 4 4 4 3 3 3 are not satisfied BSH BSW CALLT reg2,reg3 reg2,reg3 imm6 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3,disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) x Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,0) reg2,[reg1] r r rr r1 11 11 1 R RRR R adrGR[reg1] 0000000011100100 Z flagNot(Load-memory-bit(adr,reg2)) rrrrr111111iiiii if conditions are satisfied wwwww011000cccc0 then GR[reg3]sign-extended(imm5) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,0) CMOV cccc,imm5,reg2,reg3 1 1 1 1 1 1 else GR[reg3]GR[reg2] cccc,reg1,reg2,reg3 r r rr r1 11 11 1 R RRR if conditions are satisfied wwwww011001cccc0 then GR[reg3]GR[reg1] else GR[reg3]GR[reg2] CMP CTRET DBRET reg1,reg2 r r rr r0 01 11 1 RRRRR resultGR[reg2]-GR[reg1] 1 1 1 x x x x imm5,reg2 rrrrr010011iiiii resultGR[reg2]-sign-extend(imm5) 1 1 1 x x x x 0000011111100000 PCCTPC 3 3 3 R R R R R 0000000101000100 PSWCTPSW 0000011111100000 PCDBPC 3 3 3 R R R R R 0000000101000110 PSWDBPSW R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1432 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock DBTRAP 1111100001000000 DBPCPC+2 (restored PC) i r l 3 3 3 1 1 1 CY OV S Z SAT DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H 0000011111100000 DI PSW.ID1 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+1 n+1 n+1 LLLLLLLLLLL00000 GR[reg in list12]Load-memory(sp,Word) Note 4 Note 4 Note 4 spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3 LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) Note 4 Note 4 Note 4 Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV DIVH reg1,reg2,reg3 reg1,reg2 reg1,reg2,reg3 DIVHU DIVU reg1,reg2,reg3 reg1,reg2,reg3 EI 35 35 35 x x x GR[reg2]GR[reg2]/GR[reg1]Note 6 35 35 35 x x x Note 6 35 35 35 x x x 34 34 34 x x x 34 34 34 x x x 0 x x r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2]/GR[reg1] wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] r r rr r0 00 01 0 RRRRR r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2]/GR[reg1] wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2]/GR[reg1] wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] 1000011111100000 PSW.ID0 1 1 1 Stop 1 1 1 GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 rrrrr11110dddddd GR[reg2]PC+4 2 2 2 ddddddddddddddd0 PCPC+sign-extend(disp22) 0000000101100000 0000011111100000 HALT 0000000100100000 HSW reg2,reg3 rrrrr11111100000 x wwwww01101000100 JARL disp22,reg2 Note 7 JMP [reg1] 00000000011RRRRR PCGR[reg1] 3 3 3 JR disp22 0000011110dddddd PCPC+sign-extend(disp22) 2 2 2 r r rr r1 11 00 0 R RRR R adrGR[reg1]+sign-extend(disp16) 1 1 Note dddddddddddddddd GR[reg2]sign-extend(Load-memory(adr,Byte)) r r rr r1 11 10 b R RRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddd1 GR[reg2]zero-extend(Load-memory(adr,Byte)) ddddddddddddddd0 Note 7 LD.B LD.BU disp16[reg1],reg2 disp16[reg1],reg2 11 1 1 Note 11 Notes 8, 10 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1433 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock LD.H disp16[reg1],reg2 rrrrr111001RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 GR[reg2]sign-extend(Load-memory(adr,Halfword)) i r l 1 1 Note CY OV S Z SAT x x x 0 x x 11 Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]GR[reg2] 0000000000100000 Other than regID = PSW 1 1 1 regID = PSW 1 1 1 1 1 Note x x Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 R RRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 GR[reg2]zero-extend(Load-memory(adr,Halfword) 11 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 R RRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 GR[reg2]Load-memory(adr,Word) 1 1 Note 11 Note 8 MOV reg1,reg2 r r rr r0 00 00 0 RRRRR GR[reg2]GR[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii GR[reg2]sign-extend(imm5) 1 1 1 imm32,reg1 00000110001RRRRR GR[reg1]imm32 2 2 2 GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 GR[reg2]GR[reg1]+(imm16 ll 016) 1 1 1 r r rr r1 11 11 1 R RRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 wwwww01000100000 Note 14 rrrrr111111iiiii GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9) 1 4 5 GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 i i i i i i i i i i i i i i i i IIIIIIIIIIIIIIII MOVEA imm16,reg1,reg2 r r rr r1 10 00 1 R RRRR i i i i i i i i i i i i i i i i MOVHI imm16,reg1,reg2 r r rr r1 10 01 0 R RRRR i i i i i i i i i i i i i i i i MUL reg1,reg2,reg3 imm9,reg2,reg3 wwwww01001IIII 00 Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 R RRRR 1 1 2 GR[reg2]GR[reg2] Note 6 1 1 2 GR[reg2]GR[reg1] Note 6 1 1 2 1 4 5 1 4 5 xsign-extend(imm5) ximm16 i i i i i i i i i i i i i i i i MULU reg1,reg2,reg3 imm9,reg2,reg3 r r rr r1 11 11 1 R RRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] wwwww01000100010 Note 14 rrrrr111111iiiii GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) wwwww01001IIII 10 Note 13 NOP 0000000000000000 Pass at least one clock cycle doing nothing. 1 1 1 NOT reg1,reg2 r r rr r0 00 00 1 RRRRR GR[reg2]NOT(GR[reg1]) 1 1 1 NOT1 bit#3,disp16[reg1] 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) 3 3 3 dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) x Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,Z flag) reg2,[reg1] r r rr r1 11 11 1 RRRRR adrGR[reg1] 0000000011100010 Z flagNot(Load-memory-bit(adr,reg2)) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,Z flag) R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1434 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT OR reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]GR[reg2]OR GR[reg1] 1 1 1 0 x x ORI imm16,reg1,reg2 r r rr r1 10 10 0 R RRRR GR[reg2]GR[reg1]OR zero-extend(imm16) 1 1 1 0 x x i i i i i i i i i i i i i i i i PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) LLLLLLLLLLL00001 spsp-4 n+1 n+1 n+1 Note 4 Note 4 Note 4 repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) sp/immNote 15 L L L L L L L L L L L f f 0 1 1i spsp+4 mm16/imm32 repeat 1 step above until all regs in list12 is stored Note 16 n+2 n+2 n+2 Note 4 Note 4 Note 4 spsp-zero-extend (imm5) Note17 Note17 Note17 epsp/imm RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC 3 3 3 R R R R 1 1 1 x 0 x x 1 1 1 x 0 x x 1 1 1 R EIPC PSW EIPSW else if PSW.NP=1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW SAR reg1,reg2 imm5,reg2 r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2]arithmetically shift right 0000000010100000 by GR[reg1] rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc if conditions are satisfied 0000001000000000 then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H reg1,reg2 r r rr r0 00 11 0 RRRRR GR[reg2]saturated(GR[reg2]+GR[reg1]) 1 1 1 x x x x x imm5,reg2 rrrrr010001iiiii GR[reg2]saturated(GR[reg2]+sign-extend(imm5) 1 1 1 x x x x x SATSUB reg1,reg2 r r rr r0 00 10 1 RRRRR GR[reg2]saturated(GR[reg2]-GR[reg1]) 1 1 1 x x x x x SATSUBI imm16,reg1,reg2 r r rr r1 10 01 1 R RRRR GR[reg2]saturated(GR[reg1]-sign-extend(imm16) 1 1 1 x x x x x x x x x x SATADD i i i i i i i i i i i i i i i i SATSUBR reg1,reg2 r r rr r0 00 10 0 RRRRR GR[reg2]saturated(GR[reg1]-GR[reg2]) 1 1 1 SETF cccc,reg2 rrrrr1111110cccc If conditions are satisfied 1 1 1 0000000000000000 then GR[reg2]00000001H else GR[reg2]00000000H R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1435 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) i r l 3 3 3 CY OV S Z SAT x Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 R RRRR adrGR[reg1] 0000000011100000 Z flagNot(Load-memory-bit(adr,reg2)) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 R RRRR GR[reg2]GR[reg2] logically shift left by GR[reg1] 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift left 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift right by GR[reg1] 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift right 1 1 1 x 0 x x 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000000011000000 imm5,reg2 rrrrr010110iiiii by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 R RRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 rrrrr0000110dddd Note 18 SLD.H disp8[ep],reg2 rrrrr1000ddddddd Note 19 SLD.HU disp5[ep],reg2 rrrrr0000111dddd Notes 18, 20 SLD.W disp8[ep],reg2 rrrrr1010dddddd0 Note 21 SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp4) GR[reg2]zero-extend(Load-memory(adr,Byte)) adrep+zero-extend(disp8) GR[reg2]sign-extend(Load-memory(adr,Halfword)) adrep+zero-extend(disp5) GR[reg2]zero-extend(Load-memory(adr,Halfword)) adrep+zero-extend(disp8) GR[reg2]Load-memory(adr,Word) adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] rrrrr1001ddddddd Note 19 SST.W reg2,disp8[ep] rrrrr1010dddddd1 Note 21 ST.B ST.H reg2,disp16[reg1] reg2,disp16[reg1] adrep+zero-extend(disp8) Store-memory(adr,GR[reg2],Halfword) adrep+zero-extend(disp8) Store-memory(adr,GR[reg2],Word) r r rr r1 11 01 0 R RRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Store-memory(adr,GR[reg2],Byte) r r rr r1 11 01 1 R RRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8 STSR regID,reg2 r r rr r1 11 11 1 R RRRR GR[reg2]SR[regID] 0000000001000000 R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1436 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock i r l CY OV S Z SAT SUB reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]GR[reg2]-GR[reg1] 1 1 1 x x x x SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]GR[reg1]-GR[reg2] 1 1 1 x x x x SWITCH reg1 00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) 5 5 5 1 1 1 1 1 1 3 3 3 1 1 1 0 x x 3 3 3 PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1 SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) TRAP vector 00000111111iiiii EIPC PC+4 (Restored PC) 0000000100000000 EIPSW PSW ECR.EICC Interrupt code PSW.EP 1 PSW.ID 1 PC 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) TST reg1,reg2 r r rr r0 01 01 1 RRRRR resultGR[reg2] AND GR[reg1] TST1 bit#3,disp16[reg1] 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) r r rr r1 11 11 1 R RRRR adrGR[reg1] 0000000011100110 Z flagNot (Load-memory-bit (adr,reg2)) reg2, [reg1] x Note 3 Note 3 Note 3 3 3 x 3 Note 3 Note 3 Note 3 XOR reg1,reg2 r r rr r0 01 00 1 RRRRR GR[reg2]GR[reg2] XOR GR[reg1] 1 1 1 0 x x XORI imm16,reg1,reg2 r r rr r1 10 10 1 R RRRR GR[reg2]GR[reg1] XOR zero-extend (imm16) 1 1 1 0 x x i i i i i i i i i i i i i i i i ZXB reg1 00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 1 1 1 ZXH reg1 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0)) 1 1 1 Notes 1. dddddddd: Higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the PSW immediately before. 3. If there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) 5. RRRRR: other than 00000. 6. The lower halfword data only are valid. 7. ddddddddddddddddddddd: The higher 21 bits of disp22. 8. ddddddddddddddd: The higher 15 bits of disp16. 9. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1437 of 1442 V850ES/JC3-H, V850ES/JE3-H APPENDIX C INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. IIII: Higher 4 bits of imm9. 14. Do not specify the same register for general-purpose registers reg1 and reg3. 15. sp/imm: Specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign-expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically-left-shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8. R01UH0288EJ0100 Rev.1.00 Sep 20, 2011 Page 1438 of 1442 REVISION HISTORY Rev. V850ES/JC3-H, V850ES/JE3-H User's Manual: Hardware Date Description Page 0.01 1.00 February 2, 2010 Summary First Edition issued September 20, p.23 Modification of Table 1-2. V850ES/JC3-H (48 pin) Product List 2011 p.24 Modification of Table 1-3. V850ES/JE3-H Product List p.44 Modification of 2.1 (1)Port pin pp.46 to Modification of 2.1 (2)Non-Port pin 49 p.1364 Modification of 32. 5. 2 p.1380 Modification of 32. 9. (1) Basic characteristics Supply current C-1 V850ES/JC3-H, V850ES/JE3-H User's Manual: Hardware Publication Date: Rev.1.00 Sep 20, 2011 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. 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