Product Brief
May 2003
MARS2G5 T-LT (TSOT042G52) SONET/SDH
155/622/2488 Mbits/s Overhead and Path Processor
Features
■One of the next generation system on a chip
devices of Agere Systems’ multiapplication & rate
solutions MARSTM family of framers.
■Transmission convergence and SONET/SDH ter-
minal/ADM functionality for linear and ring net-
works.
■Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH overhead and path processor solu-
tions.
■Low-power 1.6/3.3 V operation.
SONET/SDH Interface
■Termination of quad STS-3/STM-1,
quad STS-12/STM-4, or single STS-48/STM-16.
■Supports overhead processing for transport and
path overhead bytes.
■Optional insertion and extraction of overhead bytes
via serial overhead interface.
■STS pointer processing to align the receive frame
to the system frame.
■STS-1 granularity cross connect between receive,
mate, STM, and data payloads.
■Support for 1 + 1 and 1:1 linear networks; UPSR
and BLSR ring netwo rks.
■Full path termination and SPE extraction/insertion.
■SONET/SDH compliant condition and alarm
reporting.
■Handles all concatenation levels of STS-3c to
STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
■Built-in diagnostic loopback modes.
■Compliant with the following Telcordia Technolo-
gies®, ANSI®, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Net-
works Based on the Synchronous Digital Hierar-
chy.
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-
tions.
— T1. 105.07 SO NET-Sub- STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-
Physical Layer Specif ication.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Interfaces
■Built-in redundant STS/STM backplane interface
using 622 MHz LVDS technology.
■Mate-to-mate backplane interface using 622 MHz
LVDS technology for 1 + 1, 1:1, BLSR, and UPSR
network su pport.
■Optional 78 MHz bus (32-bit) for STS/STM inter-
face.
■IEEE® 1149.1 port with BIST, scan, and boundry
scan.
Micropro cessor Interface
■Up to 66 MHz synchronous.
■16-bit address and 16-bit data interface.
■Synchronous or asynchronous modes available.
■Configurable to operate with most commercial
microprocessors.
MARS2G5 T-LT (TSOT042G52) SONET/SDH Product Brief
155/622/2488 Mbits/ s Overhead and Path Pr ocessor May 2003
2Agere Systems Inc.
Description
The MARS2G5 T-LT SONET/SDH overhead and path processor provides a versatile solution for quad OC-3, quad
OC-12, and for single OC-48 linear and ring datacom/telecom applications. Constructed using COM2 CMOS mod-
ular process, this device incorporates integrated SONET/SDH section/line/path termination, pointer processing,
and cross connect blocks.
Communication with the MARS2G5 T-LT device is accomplished through a generic microprocessor interface. The
device su ppo rts separate addres s and data buses .
With this device, support for different types of applications for OC-3/OC-12/OC-48 data equipment is possible,
enabling dramatic system cost reduction and the ease of development of extremely competitive solutions.
The interface rates supported are STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1. The concatena-
tion levels supported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-45c, and
STS-48c.
Note: PT = path terminator.
* An STM low-speed interface (STMLSI) is available.
Figure 1. MARS2G5 T- LT Block Diagram
OVERHEAD
PROCESSOR
MONITOR
OVERHEAD
PROCESSOR
INSERT
TRANSPORT
OVERHEAD
INTERFACE BLOCK
POINTER
PROCESSOR
CONNECTION
MEMORY
CONTROL
TSI STM INTERFACE*
SWITCHING
MPU INTERFACE
MISCELLANEOUS
GPIO/STMDCC
TOAC INTERFACE
TERMINATION
TXCLK
PATH
SWITCH
LINE
SWITCH
TXTOAC RXTOAC
3
3
PT
(PTR
INTER)
LINE
SINGLE
STM-16/STS-48
INTERFACE
MATE
INTERFACE
DUAL STM
BACKPLANE
INTERFACE
OR QUAD
STM-4/STS-12
OR QUAD
STM-1/STS-3
SINGLE
STM-16/STS-48
OR QUAD
STM-4/STS-12
OR QUAD
STM-1/STS-3
STMLSI
78 M Hz
Product Brief MARS2G5 T-LT (TSOT042G52) SONET/SDH
May 2003 155/622/2488 Mbits/s Overhead and Path Processor
3Agere Systems Inc.
Target Applications Supported
MARS2G5 T-LT (792-Pin PBGA and 600-Pin LBGA)
This multirate/multiprotocol/multimode SONET/SDH add/drop multiplexer device targets the following applications.
See Figure 2 for device interface speed/rate information:
■PON.
■Access/core router.
* An STM low-speed interface (STMLSI) is available.
Figure 2. MARS2G5 T-LT Device Interface Speed/Rate Diagram
OVERHEAD
PROCESSOR
MONITOR
OVERHEAD
PROCESSOR
INSERT
TRANSPORT
OVERHEAD
INTERFACE BLOCK
POINTER
PROCESSOR
CONNECTION
MEMORY
CONTROL
TSI STM INTERFACE*
SWITCHING
MPU INTERFACE
MISCELLANEOUS
GPIO/STMDCC
TERMINATION
TXCLK
PATH
SWITCH
LINE
SWITCH
TXTOAC RXTOAC
3
3
PT
(PTR
INTER)
LINE
SINGLE
(16 x 155 Mbits/s
LVPECL)
or
QUAD
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
INTERFACE
SINGLE
(16 x 155 Mbits/s
LVPECL)
or
QUAD
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
MATE
INTERFACE
(4 x 622 Mbits/s
LVDS)
DUAL STM
BACKPLANE
INTERFACE
(DUAL
4 x 622 Mbits/s
LVDS)
STMLSI
78 MHz
Copyright © 2003 Agere Systems Inc.
All Rights Reserved
May 2003
PB03-085SONT (Replaces PB03-002SO NT-1)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. MARS is a trademark of Agere Systems Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-71 2-4106 )
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5 047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767- 1850 (Seoul), SINGAPORE: (65) 6778-883 3, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE: Tel. (44 ) 1344 296 400
Telcordia Technologies is a trademark of Telcordia Technologies, Inc.
ANSI is a registered trademark of American National St andards Institute, Inc.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
