AN82527F8 S T125 - INTEL

82527 SERIAL COMMUNICATIONS

CONTROLLER AREA NETWORK

PROTOCOL

Express

Advance Information Datasheet

Product Feat ures

■Supports CAN Specification 2 .0

—St andard Dat a an d Remote Fram es

—Extended Data and Remo te Frames

■Programmable Glob al Ma sk

—St andard Mess age ldentifier

—Extended Mes sag e ldentifier

■15 Message Objects of 8-Byte Data Length

—14 Tx/Rx Buffers

—1 Rx Buffer with Programmable Mask

■Flexible CPU Interface

—8-Bit Multiplexed

—1 6- Bit Multiplexe d

—8-Bit Non-Multiplexed (Synchronous/

Asynchronous)

—Serial Interface

■Programmable Bit Rate

■Programmable Clock Output

■Flexible Interr upt Stru cture

■Flexible Status Interface

■Conf igurable Output Driver

■Conf igurable Input Comp arator

■Two 8-Bit Bidirectional I/O Ports

■44-Lead PLCC Package

■Pinout Compatibility with the 82526

Order No: 273150-0 02

August 2004

Notice : This document contains information on products in t he sam pling and init ial production

phases of development. The specifications are subject to change without notice. Verify with your

local Intel sales off ice that you have the l atest datasheet before finali zing a design.

82527 -

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ii Advance Informa tion Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no res ponsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82527 -

Express

may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Cur rent characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

PO Box 5937

Denver CO 80217-9808

call 1-800-548-4725

*Third-party brands and names are the property of their respective owners.

Advance Information Datash eet iii

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Contents

1.0 INTRODUCTION.....................................................................................................1

2.0 PIN DESCRIPTIONS.............................................................................................3

3.0 ELECTRICAL CHARACTERISTICS.................................................................5

3.1 DC CHARACTERIST ICS................................................................................ 5

3.2 PHYSICAL LAYER SPECIFICATIONS........................................................... 6

3.3 CLOCKO UT SPECIFICATIONS ..................................................................... 6

3.4 AC CHARACTERISTICS ........................... ........................... .......................... 7

3.4.1 8/16-Bit Multiplexed Intel Modes (Modes 0, 1)........... ....... ....... .. ........ 7

3.4.2 8-Bit Multiplex ed Non-I ntel Mode (Mode 2).................. ....... ....... ..... . 10

3.4.3 8-Bit Non-Multiplexed Asynchronou s Mode (Mod e 3). ................ . .... 12

3.4.4 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)......... .. ....... ...... 14

3.4.5 Serial Interface Mode....................................................................... 16

3.4.6 AC Testing Input.............. ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... . 18

4.0 DATASHEET REVISION HISTORY................................................................18

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iv Advance Informa tion Datasheet

Figures 1 xx82527 Block Diagram..................................................................................2

2 xx82527 44-Pin PLCC Package ..................................................................... 2

3 82527 System Timings (Modes 0, 1) ............................... ................... .............8

4 Ready Output Timing for a Write Cycle if No Previous Write

is Pending (Modes 0, 1) ................... . ...............................................................9

5 Ready Output Timing for Write Cycle if Previous Write Cycle

is Active (Modes 0, 1....................... ....... ....... ..... ....... ....... .......... .. ....... ....... ..... .9

6 Ready Output Timing for Read Cycle (Modes 0, 1)...................... . ............. . ....9

7 82527 System Bus Timing (Mode 2)............................................. . ................11

8 Timing of the Asynchronous Mode Read Cycle (Mode 3) .. .................. . .........13

9 Timing of the Asynchronous Mode Write Cycle (Mode 3)..............................13

10 Timing of the Synchronous Read Cycle (Mode 3) . ..................... ...................15

11 Timing of the Sy nchronous Write Cycle (Mode 3)... ....... ....... ....... ..... ....... .. ....15

12 Serial Interface Mode (Priority = 0, Phase = 0)..............................................17

13 Serial Interface Mode (Priority = 1, Phase = 1)..............................................17

Tables 1 Pin Type Legend... .............. ................... ................... ................... .............. ......3

2 P in Des cr iptions......... .......................... .......................... .......................... ........3

3 DC Characteri stics................. .......................... .......................... ......................5

4 DC Characteri stics................. .......................... .......................... ......................6

5 Cl o cko u t Sp e cifications........................ .......................... .......................... ........6

6 AC Characteristics 8/16-Bit Multiplexed Intel Mode s (Modes 0, 1).... ..............7

7 AC Characteristics 8-Bit M ultiple xed Non-Intel Mode (Mode 2)........... . .........10

8 AC Characteristics 8-Bit Non-M ultipl exed Asynchronous Mode (Mode 3).....12

9 AC Characteristics 8-Bit Non-M ultipl exed Synchronous Mode (Mode 3)....... 14

10 AC Characteristics fo r Serial Interface Mode.................................................16

ADVANCE INFORMATION Datasheet 1

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1.0 INTRODUCTION

The 8252 7 se rial communicat ions controller is a highly integrated devic e that performs serial

communication accord ing to t he CAN protocol. It performs all se rial communicat ion functions

such as trans mi ssi on and re cepti on of me ssa ges, messa ge filteri ng , transm it searc h, and interru pt

sea r ch wi th minimal interact ion from the host mi cr ocontroller, or CP U.

The 8252 7 is Intel’s first device to support the standard and ext ended message frames in CAN

Specification 2.0 Part B. It has the capability to transmit, rece ive, and perform message filtering on

extended message frames. Due to the backwardly compa tible nature of CAN Speci fication 2 .0, the

82527 also fully supports the standard m essage frames in CAN Specification 2.0 Part A.

The 82527 features a powerful CPU interface that offers flexibility to dire ctly interface to many

different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit

multiplexed, or 8-bit non-multiplexed address /data bus for Intel and non-Intel architectures. A

flexible serial interface (SPI) is also available when a parallel CPU interface is not required.

The 82527 provides storage for 15 message objects of 8-byte data length. Each m es sage object ca n

be configured as either transmit or receive except for the la st me ssage object. The las t message

object is a receive-only buffer with a special mask design to allow select groups of different

message identifiers to be received.

The 82 527 also impleme nts a g lobal masking fea ture for message filtering. T his feature allows the

use r to globally mask any identifier bits of the incoming message. The program mable global mask

can be used for both standard and extende d message s.

The 8252 7 PLCC offers ha rdware, or pinout, comp atibilit y with t he 82526. It is pin-to-pin

comp atible with the 82526 except for pins 9, 30, and 44. These pins are used a s c hip s elects on t he

82526 and are used as CPU interface mode se lection pins on the 82527.

The 82 527 is fa bricat ed using Int el ’s relia ble CHMOS III 5V te chnology and i s availa ble in 44 -le ad

PLCC for the express temperature range (–40°C to +85°C).

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2 ADVANCE INFORMATION Datashee t

Figure 1. xx8 2527 -

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Block Diagram

Figure 2. xx82527 44-P in PLCC Packa ge

A4577-01

CPU

Interface

Logic

CAN

Controller

CLKOUT

CLKOUTMode 1

TX1

TX0

RAM

Port 2Port 1

RX1

RX0

Mode 0

Address/

Data Bus

Control Bus

A4578-01

AD7

P1.0 / AD8

P1.1 / AD9

P1.2 / AD10

P1.3 / AD11

P1.4 / AD12

P1.5 / AD13

P1.6 / AD14

P1.7 / AD15

MODE1

RESET#

RD# / E

ALE / AS

AD0

AD1

AD2



MODE0

AD3

AD4 / MOSI

AD5

AD6 / SCLK

(WR# / WRL#)/(R/W#)

CS#

DSACK0

P2.7 / WRH#

P2.6 / INT#

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

39

38

37

36

35

34

33

32

31

30

xx82527

View of component as

mounted on PC board

7

8

9

10

11

12

13

14

15

16

XTAL1

XTAL2

SS2



RX1

RX0

SS1



INT#(V

CC/2

)

TX1

TX0

CLKOUT

READY/MISO

18

19

20

21

22

23

24

25

26

27

6

5

4

3

2

1

44

43

42

41

ADVANCE INFORMATION Datasheet 3

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2.0 PIN DES CRIPTIONS

The 82527 - Express pins are described in this section. Table 1 presents the le gend for interp r eting the

pin types.

Ta bl e 1 . Pin Ty pe Legen d

Symbol Description

I Input Only Pin

O Output Only Pin

I/O Pin can be either Input or Output

Table 2. Pin Descriptions (Sheet 1 of 2)

Name Type Description

VSS1 Ground GROUND connection must be connected externally to a VSS board

plane. Provi de s dig ital groun d.

VSS2 Ground GROUND connec tion must be connected externally to a VSS board

plane. Provi de s groun d for anal og com pa rator.

VCC Power POWER connection must b e connected externally t o +5 V DC. Provides

power for entire device.

XTAL1 IIn put for an external clock. XTA L1 ( along with XTAL2) are the crystal

connections to an internal oscillator.

XTAL2 O

Push-pull o utput from the internal oscillator. XTAL2 (along with XTAL1)

are the c rysta l connections to an internal oscillator. If an ex ternal

oscillator is used, XTAL2 must be floated, or not be connected. XTAL2

m ust not be used as a c lock output to drive other CPUs .

CLKOUT O Programmable clock output. Thi s output may be used to drive the

oscillator of the host microcontroller.

RESET# I

Warm Reset: (VCC remains valid while RESET# is asserted), RESET#

m ust be dr iven to a valid low level for 1 ms minimum.

Cold Reset: (VCC is driven to a valid level while RESET# is asserted),

RESET# must be driven low for 1 ms minimum measured from a valid VCC

level. No falling edge on the reset pin is required during a cold reset event.

CS ## I A low level on this pin enab les CPU access to the 82527 device.

INT#

(VCC/2) O

The interrupt pin is an op en-drain output to the host micr ocontroller.

VCC/2 is the power supply for the ISO low speed physical laye r. The

function of this pin is determined by the MUX bit in the CPU Interface

Regist er (Address 02H) as follows:

MUX e 1: pin 24 (PLCC) = VCC/2, pin 11 = INT#

MUX e 0: pin 24 (PLCC) = INT#

RX0

RX1 I

In pu ts fr om t he CA N bu s l in e(s ) t o the in pu t c om para t or. A rece ss ive l eve l

is read when RX0 > RX1. A dominant level is read when RX1 > RX0.

When the CoBy bi t (Bus Configuration regist er) is progr ammed as a “1”,

the input comparator is bypassed and RX0 is the CAN bus line input.

TX0

TX1 O

OSerial data push-pull output to the CAN bus line. Dur ing a recessive bit TX0

is high and TX1 is low. During a dominant bit TX0 is low and TX1 is high.

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4 ADVANCE INFORMATION Datashee t

AD0/A0/ICP

AD1/A1/CP

AD2/A2/CSAS

AD3/A3/STE

AD4/A4/MOSI

AD5/A5

AD6/A6/SCLK

AD7/A7

I/O-I-I

I/O-I

I/O-I-I

I/O-I

I/O-I-I

I/O-I

Address/Data bus in 8-bit multiplexed mode.

Address bus in 8-bit non-multiplexed mode.

Low byte of A/D bus in 16-bit multiplexed mode.

In Serial Interface mode, the following pins have the following meaning:

A D0: ICP Idle C lock Pola rit y

AD1: CP Clock Phase

AD2: CSAS Ch ip Select Acti ve State

A D3: STE Sy nc Tran sm it En ab le

A D6: SC LK Ser ial Cl oc k Inp ut

AD4: MOSI Serial Data Input

AD8/D0/P1.0

AD9/D1/P1.1

AD10/D2/P1.2

AD11/D3/P1.3

AD12/D4/P1.4

AD13/D5/P1.5

AD14/D6/P1.6

AD15/D7/P1.7

I/O-O-I/O

High byte of A/D bus in 16-bit multi plexed mode.

Data bus in 8-bit non-multiplexed mode.

Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode.

Port pins have weak pullups until the port is configured by writing to 9FH

and AFH.

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6/INT#

P2.7/WRH#

I/O

I/O-O

I/O-I

P2 in all modes.

P2.6 is INT# when MUX = 1 and is open-drain.

P2.7 is WRH# in 16-bit multiplexed mode.

Mode0

Mode1 I

T he se pin s se le ct one of the fou r para lle l interfac es . The s e pin s are

weakly held low during reset.

Mode 1 Mo de 0

008-bit multiplexed — Intel

0 0 Serial Interfac e mode entered when RD# = 0,

WR# = 0 upon reset.

0 1 16-bit multiplexed — Intel

1 0 8-bit multiplexed — non-Intel

1 1 8-bit non-multiplexed

ALE/AS I-I ALE used for Intel modes.

AS used fo r n on-Intel m odes, except Mode 3 this pin must be tied high.

RD#

RD#used for Intel modes.

E used for non-I ntel modes, e xcept Mode 3 Asynchronous t his pin must

be tied high.

WR#/WRL#

R/W# I

IWR#in 8-bit Intel mode and WR L# in 16-bit Intel mode.

R/W # used for non-Intel modes.

READY

MISO O

READ Y is an o utput to synchroni z e accesses from the host

microcontroller to the 82527. READY is an open-drain output to the host

microcontro ller. MISO is the serial data output for the serial interface

mode.

DSACK0# O DSACK0# is an open-drain output to synchronize accesses from the host

microcontroller to the 82527.

Table 2. Pin Description s (Sheet 2 of 2)

Name Type Description

ADVANCE INFORMATION Datasheet 5

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3.0 ELECTRICAL CHARACTERISTICS

3.1 DC CHARACTERISTI CS

Operating Conditions :

•VCC = 5 V ±10%

•TA = –40°C to +85°C

ABSOLUTE MAXIMUM RATINGS*

Storage Temperatu re –6 0°C to +150 °C

Voltage from Any Pin to

VSS .... .... ....... .... .... .... ....... .... .... .... ... –0.5 V to +7 .0 V

Laboratory testing shows the 82527 will withstand up to 10

mA of in je cte d cu r re nt in to bo th R X0 and R X1 pins for a

total of 20 days without sustaining permanent damage. This

high current con dition may be the result of sh orted signal

lines. The 82527 will not function properly if the RX0/RX1

in p ut voltag e ex ce ed s VCC+0.5 V.

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice. Verify with

your local Intel sales office that you have the latest

datasheet before finalizing a design.

*WARNIN G: Stressing the device beyo nd the

“Absolute Maximum Ratings” may cause

permanent damage. T hese are stress ratings

only. Operation beyond the “Operating

Conditi ons” is not recommended and extend ed

exposure beyond the “Operating Conditions”

may affect device reliability.

Table 3. DC Characteristics

Sym Parameter Min Max Conditions

VIL Input Low Voltage (All except RX0, RX1, AD0±AD7

in Mode 3) –0.5 0.8 V

VIL1 Input Low Voltage for AD00–D7 in Mode 3 –0.5 0.5 V

VIL2 Input Low Voltage (R X0) for Com parator Bypass

Mode 0.5 V

VIL3 Input Low Voltage for Port 1 and Port 2 Pins Not

Used for Interface to Host CPU 0.3 VCC

VIH I nput High Voltage (All except RX0, RX1, RES ET#) 3.0 V VCC + 0.5 V

VIH1 I nput High Voltag e (RESE T#) Hysteresis on

RESET# 3.0 V

200 mV VCC + 0.5 V

VIH2 I nput H igh Voltag e (RX0) for C omparator Bypass

Mode 4.0 V

VIH3 I nput High Voltage for Port 1 and Port 2 Pins Not

Used for Interface to Host CPU 0.7 VCC

VOL Output Low Voltage (All Outputs except TX0, TX1) 0.45 V IOL = 1.6 mA

VOH Ou tput High Voltage (All Outputs except TX0, TX1 ,

CLOCKOUT) VCC – 0.8 V IOH = –200 µA

VOHR1 Outpu t High Voltage (CLOCK OUT) 0.8 V IOH = –80 µA

ILK Input Leakage Current ±10 µA VSS < VIN < VCC

CIN PIN Capacitance** 10 pF FXTAL = 1 KHz

ICC Supply Current 50 mA FXTAL = 16 KHz(1)

ISLEEP Sl eep Current

with VCC/2 Output Enabled, No Load

with VCC/2 Output Disabled 700 µA

100 µA (1)

IPD Powerdown Curre nt 25 µA XTAL1 Clocked (1)

NOTES:

**Typical value based on characterization data. Port pins are weakly held after reset until the port

configuration registers are written (9FH, AFH).

1. All pins are driven to VSS or VCC i ncluding RX0 and RX1.

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6 ADVANCE INFORMATION Datashee t

3.2 PH YSICAL LAYER SPECIFICATIONS

Operating Conditions:

•Load = 100 pF

•VCC = 5 V ±1 0%

•TA = –40°C to +85°C

3.3 CLOCKOUT SPECIFICATI ONS

Operating Conditions:

•Load = 50 pF

Table 4. DC Characteristics

RX0/RX1 and TX0/TX1 Min Max Conditions

Input Voltage –0.5 V VCC + 0.5 V

Common Mode Range VSS + 1 V VCC – 1 V

Differential Input Threshold ±100 mV

Intern al Delay 1: Sum of the Comparator

Input Delay and the TX0/TX1 Output Driver

Delay 60 ns L oa d on TX 0, TX1 = 100 pF,

+100 mV to –100 mV RX0/RX1

differential

Internal Delay 2: Sum of the RX0 Pin Delay

(if the Comparator is Bypassed) and the

TX0/TX 1 Output Driver Delay 50 ns L oa d on TX 0, TX1 = 100 pF

Source Current on Each TX0 , T X1 –10 mA VOUT = VCC – 1 V

Sink Current on Each TX0, TX1 10 mA VOUT = 1 V

I np ut Hys te r es is for R X0/ R X12 0 V

VCC/2

VCC/2 2.38 V 2.62 V IOUT ≤ 75 µA, VCC = 5 V

Table 5. Clockout Specifications

Parameter Min Max

CLOCKOUT Frequency XTAL/15 XTAL

ADVANCE INFORMATION Datasheet 7

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3.4 AC CHARACTERISTI CS

3.4.1 8/16-Bit Multiplexed Intel Modes (Modes 0, 1)

Operating Conditions :

•V

CC = 5 V ±10% • VSS = 0 V • T A = –40°C to +85ºC • CL = 100 pF

Table 6. AC Characteristics 8/16-Bit Multiplexe d Intel Modes (Modes 0, 1) (Sheet 1 of 2)

Symbol Parameter Min Max Conditions

1/TXTAL Oscillator Frequency 8 MHZ 16 MHz

1/TSCLK System Clock Frequency 4 MHZ 10 MHZ

1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ

TAVLL Address Valid to ALE Low 7.5 ns

TLLAX Address Hold after ALE Low 10 ns

TLHLL ALE High Time 30 ns

TLLRL ALE Low to RD# Low 20 ns

TCLLL CS# Low to ALE Low 10 ns

TQVWH Data Setup to WR# High 27 ns

TWHQX Input Data Hold after WR# High 10 ns

TWLWH WR# Pulse Width 30 ns

TWHLH WR# High to Next ALE High 8 ns

TWHCH WR# High to CS# High 0 ns

TRLRH

RD# Pulse Width

This time is long enough to initiate a double

read cycle by loading the High Speed

Registers (04H, 05H), but is too short to

READ from 04H and 05H (See t RLDV )

40 ns

TRLDV RD# Low to Data Valid (Only for Registers

02H, 04H, 05H) 0 ns 55 ns

TRLDV1

RD# Low Data to Data Valid (for Registers

except 02H, 04H, 05H)

for Read Cycle without a Previous Write (1)

for Read Cycle with a Previous Write (1)

1.5 TMCLK + 100 ns

3.5 TMCLK + 100 ns

TRHDZ Data Float after RD# High 0 ns 45 ns

TCLYV CS# Low to READY Setup Condition:

Load Capacitance on the READY Output: 50

32 ns

40 ns VOL=1 V

VOL=0.45 V

TWLYZ WR# Low to READY Float for a Write Cycle if

No Previous Write is Pending (2) 145 ns

TWHYZ End of Last Write to READY Float for a Write

Cycle if a Previous Write Cycle is Active (2) 2 TMCLK + 100 ns

NOTES:

References to WR# also pertain to WRH#.

1. Definition of “read cycle without a previous write”: The time between the rising edge of WR#/WRH# (for the

previous write cycle) and the falling ed ge of RD# (for the current r ead cycle) is greater than 2 TMCLK.

2. Definition of “write cycle with a previous write'”. The time between the rising edge of WR#/WRH# (for the

previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 TMCLK.

3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.

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8 ADVANCE INFORMATION Datashee t

TRLYZ

RD# Low to READY Float

(for registers except 02H, 04H, 05H)

for Read Cycle without a Previous Write (1)

for Read Cycle with a Previous Write (1)

2 TMCLK + 100 ns

4 TMCLK + 100 ns

TWHDV WR# High ti Output Data Valid on Port 1/2 TMCLK 2 TMCLK + 100 ns

TCOPO CLKOUT Period (CDV+1) * TOSC (3)

TCHCL CLKOUT High Per iod (CDV+1) * ½TOSC –10 (CDV+1) * ½TOSC –15

Figure 3. 82527 -

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System Timings (Modes 0, 1)

Table 6. AC Characteristics 8/16-B it Multiplexed Intel Modes (Mode s 0, 1) (S hee t 2 of 2)

Symbol Parameter Min Max Conditions

NOTES:

References to WR# also pertain to WRH#.

1. Definition of “read cycle without a previous write”: The time between the rising edge of WR#/WRH# (for the

previous wr ite cycle) and the falling edge of RD# ( for the current rea d cycle) is greater than 2 TMCLK.

2. Definition of “write cycle with a previous write'”. The time between the rising edge of WR#/WRH# (for the

previous wr ite cycle) and the rising edge of WR#/WRH# (for the current write cy cle) is less than 2 TMCLK.

3. Definition of CDV is the value loaded in the C LKOUT register representing the CLKOUT divisor.

A4580-01

ALE

CS#

WR#

BUS

RD#

LHLL

AVLL

CLLL

LLAX

LLRL

RLRH

WHCH

RLDV

RHDZ

WHLH

WHQX

WHDV

QVWH

WLWH

Address Data Out

BUS

Address

PORT 1 / 2

Data In

ADVANCE INFORMATION Datasheet 9

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Figure 4. Ready Output Tim ing for a Write Cycle if No Previous Write is Pend ing (Modes 0, 1)

Figure 5. Ready Output Tim ing for Write Cycle if Previous Writ e Cycle is Active (Modes 0, 1)

Figure 6. Ready Output Tim ing for Read Cycle (Modes 0, 1)

CS#

WR#

Ready

CLYV

WLYZ

CS#

WR#

Ready

tWHYZ

CLYV

CS#

ALE

RD#

Ready

RLYZ

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10 ADVANCE INFORMATION Datashee t

3.4.2 8-Bit Multiplexed Non-Intel Mode (Mode 2)

Operating Conditions::

•V

CC = 5 V ±10% • VSS = 0 V • TA = –40°C to +85ºC • CL = 100 pF

Table 7. AC Characteristics 8-Bit Multiplexed Non-Intel Mode (Mode 2)

Symbol Parameter Min Max

1/TXTAL Oscillator Frequency 8 MHZ 16 MHz

1/TSCLK System Clock Frequency 4 MHZ 10 MHZ

1/TMCLK M emor y Clock Frequency 2 MHZ 8 MHZ

TAVLL Address Valid to AS Low 7.5 ns

TSLAX Address Hold after AS Low 10 ns

TELDZ Data Float after E Low 0 ns 45 ns

TEHDV

E High to Data Valid for Registers 02H, 04H, 05H 0 ns 45 ns

for Read Cycle without a Previous Write (1)

for Read Cycle with a Previous Write (for Registers except for

02H, 04H, 05H)

1.5 TMCLK + 100 ns

3.5 TMCLK + 100 ns

TQVEL Data Setup to E Low 30 ns

TELQX Input Data Hold after E Low 20 ns

TELDV E Low to Output Data Valid on Port 1/2 TMCLK 2 TMCLK + 500 ns

TEHEL E High Time 45 ns

TELEL End of Previous Write (Last E Low) to E Low for a Write Cycle 2 TMCLK

TSHSL AS High Time 30 ns

TRSEH Setup Time of R/W# to E High 30 ns

TSLEH AS Low to E High 20 ns

TCLSL CS# Low to AS Low 20 ns

TELCH E Low to CS# High 0 ns

TCOPD CLKOUT Period (CDV+1) * TOSC (3)

TCHCL CLKOUT High Per iod (CDV+1) * ½TOSC – 1 0 (CDV+1) * ½TOSC + 15

NOTES:

1. Definition of “Read Cycle without a Previous Write”: The time between the falling edge of E (for the

previous wr ite cycle) and the rising edge of E (for the current read cycle) is greater t han 2 TMCLK.

2. Definition of “Write Cycle with a Previous Write'”. The time between the falling edge of E (for the previous

wr ite cycle) and the fallin g edge of E ( for the current wri te cycle) is less than 2 TMCLK.

3. Definition of CDV is the value loaded in the C LKOUT register representing the CLKOUT divisor.

ADVANCE INFORMATION Datasheet 11

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Figure 7. 82527 -

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System Bus Timing (Mode 2)

A4588-01

EHDV

Bus

R/W#

SHSL

ELDZ

AVSL

SLEH

Address Data Out

CS#

Bus

Port 1/2

RSEH

EHEL

ELDV

ELQX

QVEL

ELCH

CLSL

SLAX

Address Data In

82527 -

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12 ADVANCE INFORMATION Datashee t

3.4.3 8-Bit Non-Multiplexed Asynchro nous Mode (Mode 3)

Operating Conditions:

•V

CC = 5 V ±10% • VSS = 0 V • TA = –40°C to +85ºC • CL = 100 pF

Table 8. AC Characteristi cs 8-Bit Non-Multiplex ed Asynchronous Mode (Mode 3)

Sym Parameter Min Max

1/TXTAL Oscillator Frequency 8 MHZ 16 MHz

1/TSCLK System Clock Frequency 4 MHZ 10 MHZ

1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ

TAVLL Address or R/W# Valid to CS# Low Setup 3 ns

TCLDV

CS# Low to Data Valid for High Speed Registers (02H, 04H, 05H) 0 ns 55 ns

For Low Speed Registers (Read Cycle without Previous Write) (1) 0 ns 1.5 TMCLK + 100 ns

For Low Speed Registers (Read Cycle with Previous Write) ( 1) 0 ns 3.5 TMCLK + 100 ns

TKLDV

DSACK0# Low to Output Data Valid for High Speed Read

For Low Speed Read Register < 0 ns

TCHDV 82527 Input Data Hold after CS# High 15 ns

TCHDH 82527 Output Data Hold after CS# High 0 ns

TCHDZ CS# High to Output Data Float 35 ns

TCHKH1 CS# High to DSACK0# = 2.4V (3) 0 ns 55 ns

TCHKH2 CS# High to DSACK0# = 2.8V 150 ns

TCHKZ CS# High to DSACK0# Float 0 ns 100 ns

TCHCL CS# Width between Succes sive Cycles 25 ns

TCHAI CS# High to Address Invalid 7 ns

TCHRI CS# High to R/W# Invalid 5 ns

TCLCH CS# Width Low 65 ns

TDVCH CPU Write Data Valid to CS# High 20 ns

TCLKL CS# Low to DSACK0# Low for High Speed Registers and Low

Speed Registers Write Access without Previous Write (2) 0 ns 67 ns

TCHKL End of Previous Write (CS# High) to DSACK0# Low for a Write

Cycle with a Previous Write (2) 0 ns 2 TMCLK + 145 ns

TCOPD CLKOUT Period (CDV+1) * TOSC (4)

TCHCL CLKOUT High Period (CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15

NOTES:

E and AS must be tied high in this mode.

1. Definition of “Read Cycle without a Previous Write”: The time between the rising edge of CS# (for the

previous write cycle) and the falling edge of CS# (f or the current read cycle) is greater than 2 TMCLK.

2. Defin i tion of “Wri te C ycl e wit h a Pr evi ous Wr i te' ”. The ti me bet wee n th e ris in g ed ge of CS# (for the pr e vi ou s

wr ite cycle) and the ri sing edge of CS# (for the current write cycle) is less than 2 TMCLK.

3. An on-chip pullup will drive DSACK0# to approximately 2.4 V. An external pullup is required to drive this

signal to a higher volt age.

4. Definition of CDV is the value loaded in the C LKOUT register representing the CLKOUT divisor.

ADVANCE INFORMATION Datasheet 13

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Figure 8. Timing of the Asynchronous Mode Read Cycle (Mode 3)

Figure 9. Ti ming of the Asynchronous Mode Write Cycle (Mode 3)

A4589-01

Address

R/W#

CHAI

CS#

Data

DSACK0#

AVCL

CHDH

CHKZ

CHKH

CHDZ

CLDV

KLDV

CHCL

CLKL

CLCH

A4590-01

Address

R/W#

CHAI

CS#

Data

DSACK0#

AVCL

CHKZ

CHKH

CHDV

DVCH

CHCL

CLKL

CLCH

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14 ADVANCE INFORMATION Datashee t

3.4.4 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)

Operating Conditions:

•V

CC = 5 V ±10% • VSS = 0 V • TA = –40°C to +85ºC • CL = 100 pF

Table 9. AC Characteristi cs 8-Bit Non-Multiplex ed Synchronous Mode (Mode 3)

Sym Parameter Min Max

1/TXTAL Oscillator Frequency 8 MHZ 16 MHz

1/TSCLK System Clock Frequency 4 MHZ 10 MHZ

1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ

TEHDV

E High to Data Valid out of High Speed Register (02H, 04H, 05H) 55 ns

Read Cycle without Previous Write for Low Speed Registers(1) 1.5 TMCLK + 100 ns

Read Cycle with Previous Write for Low Speed Registers(1) 3.5 TMCLK + 100 ns

TELDH Data Hold after E Low for a Read Cycle 5 ns

TELDZ Data Float after E Low 35 ns

TELDV Data Hold after E Low for a Write Cycle 15 ns

TAVEH Address and R/W# to E Setup 25 ns

TELAV Address and R/W# Valid after E Falls 15 ns

TCVEH CS# Valid to E High 0 ns

TELCV CS# Valid after E Low 0 ns

TDVEL Data Setup to E Low 55 ns

TEHEL E Active Width 100 ns

TAVAV Start of a Write Cycle after a Previous Write Access 2 TMCLK

TAVCL Address or R/W# to CS# Low Setup 3 ns

TCHAI CS# High to Address Invalid 7 ns

TCOPD CLKOUT Period (CDV+1) * TOSC (2)

TCHCL CLKOUT High Period (CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15

NOTES:

1. Def in iti on of “Re ad C ycl e wi t hout a P revi ou s Wr it e” : Th e t im e be tw een the f al l in g edge of E (f or t he pr ev ious

wr ite cycle) and the ri sing edge of E (for the current read cycle) is great er than 2 TMCLK.

2. Definition of CDV is the value loaded in the C LKOUT register representing the CLKOUT divisor.

ADVANCE INFORMATION Datasheet 15

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Figure 10. Timing of the Synchronous Read Cycle (Mode 3)

Figure 11. Timing of the Synchron ous Write Cycle (Mode 3)

A4592-01

Address

R/W#

ELAV

CS#

AVEH

ELCV

DVEL

ELDV

EHEL

CHAI

AVCL

CVEH

AVAV

Data

A4591-01

Address

R/W#

ELAV

CS#

AVEH

ELCV

DVEL

ELDV

EHEL

CHAI

AVCL

CVEH

AVAV

Data

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16 ADVANCE INFORMATION Datashee t

3.4.5 Serial Interface Mode

Operating Conditions:

•VCC = 5.0 V ±1 0%

•VSS = 0 V

•TA = –40°C +85°C

•CL = 100 pF

Ta ble 1 0. AC Characteristics fo r S eri al Inter face Mode

Sym Parameter Min Max

1/TMCLK SPI Clock 0.5 MHZ 8 MHZ

TELDH 1/SCLK 125 ns 2000 ns

TELDZ Minimum Clock High Time 84 ns

TELDV Minimum Clock Low Time 84 ns

TAVEH ENABLE Lead Time 70 ns

TELAV Enable Lag Time 109 ns

TCVEH Access Time 60 ns

TELCV Maximum Data Out Delay Time 59 ns

TDVEL Minimum Data Out Hold Time 0 ns

TEHEL Maximum Data Out Disable Time 665 ns

TAVAV Minimum Data Setup Time 35 ns

TAVCL Mi nimu m Data Hold Ti me 84 ns

TCHAI Maximum Time for Input to go from VOL to VOH 100 ns

TCHAI Maximum Time for Input to go from VOH to VOL 100 ns

TCHAI Minimum Time between Consecutive CS# Assertions 670 ns

TCOPD CLKOUT Period (CDV+1) * TOSC(1)

TCHCL CLKOUT High Period (CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15

NOTE:

1. Definition of CDV is the value loaded in the C LKOUT register representing the CLKOUT divisor .

ADVANCE INFORMATION Datasheet 17

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Figure 12. Se ri al Interface Mode ( P ri o ri ty = 0, P hase = 0 )

Figure 13. Se ri al Interface Mode ( P ri o ri ty = 1, P hase = 1 )

A4593-01

SCLK

CS#

MIS0

MOSI

DIS

LEAD

PD0

LAG

FALL

CYC

SKL0

SKHI

RISE

SETUP

ACC

HOLD

NOTE: Polarity = 0, Phase = 0

A4594-01

SCLK

CS#

MIS0

MOSI

DIS

LEAD

PD0

LAG

RISE

CYC

SKHI

SKLO

FALL

SETUP

ACC

HOLD

NOTE: Polarity = 1, Phase = 1

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18 ADVANCE INFORMATION Datashee t

3.4.6 AC Testing Input

4.0 DATASHEET REVISION HISTORY

Package prefix variables in this document are now indicated with an "x".

Figu re 1. Input, Out put Wav eforms

A4598-01

NOTE:

AC inputs during testing are driven at V

– 0.5V for a Logic "1" and 0.1V for a Logic "0".

Timing measurements are made at V

Min for a Logic "1" and V

Max for a Logic "0".



0.1 V

– 0.5 V

– 0.8V

0.45V