TFDU6300
www.vishay.com Vishay Semiconductors
Rev. 2.1, 13-Jul-12 6Document Number: 84763
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RECOMMENDED CIRCUIT DIAGRAM
Operated at a clean low impedance power supply the
TFDU6300 needs no additional external components.
However, depending on the entire system design and board
layout, additional components may be required
(see figure 3).
Fig. 3 - Recommended Application Circuit
The capacitor C1 is buffering the supply voltage and
eliminates the inductance of the power supply line. This one
should be a tantalum or other fast capacitor to guarantee the
fast rise time of the IRED current. The resistor R1 is only
necessary for high operating voltages and elevated
temperatures.
Vishay transceivers integrate a sensitive receiver and a
built-in power driver. The combination of both needs a
careful circuit board layout. The use of thin, long, resistive
and inductive wiring should be avoided. The inputs (TXD,
SD) and the output RXD should be directly (DC) coupled to
the I/O circuit.
The capacitor C2 combined with the resistor R2 is the low
pass filter for smoothing the supply voltage.
R2, C1 and C2 are optional and dependent on the quality of
the supply voltages VCCx and injected noise. An unstable
power supply with dropping voltage during transmission
may reduce the sensitivity (and transmission range) of the
transceiver.
The placement of these parts is critical. It is strongly
recommended to position C2 as close as possible to the
transceiver power supply pins. A tantalum capacitor should
be used for C1 while a ceramic capacitor is used for C2.
In addition, when connecting the described circuit to the
power supply, low impedance wiring should be used.
When extended wiring is used the inductance of the power
supply can cause dynamically a voltage drop at VCC2. Often
some power supplies are not able to follow the fast current
rise time. In that case another 4.7 μF (type, see table under
C1) at VCC2 will be helpful.
Keep in mind that basic RF-design rules for circuit design
should be taken into account. Especially longer signal lines
should not be used without termination. See e.g. “The Art of
Electronics” Paul Horowitz, Winfield Hill, 1989, Cambridge
University Press, ISBN: 0521370957.
I/O AND SOFTWARE
In the description, already different I/Os are mentioned.
Different combinations are tested and the function verified
with the special drivers available from the I/O suppliers. In
special cases refer to the I/O manual, the Vishay application
notes, or contact directly Vishay Sales, Marketing or
Application.
MODE SWITCHING
The TFDU6300 is in the SIR mode after power on as a
default mode, therefore the FIR data transfer rate has to be
set by a programming sequence using the TXD and SD
inputs as described below. The low frequency mode covers
speeds up to 115.2 kbit/s. Signals with higher data rates
should be detected in the high frequency mode. Lower
frequency data can also be received in the high frequency
mode but with reduced sensitivity. To switch the
transceivers from low frequency mode to the high frequency
mode and vice versa, the programming sequences
described below are required.
SETTING TO THE HIGH BANDWIDTH MODE
(0.576 Mbit/s to 4 Mbit/s)
1. Set SD input to logic “high”.
2. Set TXD input to logic “high”. Wait ts ≥ 200 ns.
3. Set SD to logic “low” (this negative edge latches state of
TXD, which determines speed setting).
4. After waiting th ≥ 200 ns TXD can be set to logic “low”.
The hold time of TXD is limited by the maximum allowed
pulse length.
TXD is now enabled as normal TXD input for the high
bandwidth mode.