LMH0387SL/NOPB - NATIONAL SEMICONDUCTOR

LMH0387

LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable

Driver

Literature Number: SNLS315F

LMH0387

June 7, 2011

3 Gbps HD/SD SDI Configurable I/O Adaptive Cable

Equalizer / Cable Driver

General Description

The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive

Cable Equalizer / Cable Driver provides a single chip interface

to a BNC. The device can be configured either in the input

mode as an equalizer to receive data over coaxial cable or in

the output mode as a cable driver to transmit data over coaxial

cable. The same I/O pin is used both for the input and the

output functions of the device, allowing the system designer

the flexibility to use a BNC attached to the device as either an

input or an output.

The LMH0387 offers designers flexibility in system design

and quicker time to market. The device operates over a wide

range of data rates from 125 Mbps to 2.97 Gbps (DC to

2.97 Gbps when driving cable) and supports SMPTE 424M,

SMPTE 292M, SMPTE 344M, and SMPTE 259M. The return

loss network is integrated within the device so no external

components are required to meet the SMPTE return loss

specification.

In the input mode, the LMH0387 features include a power-

saving sleep mode, programmable output common mode

voltage and swing, cable length indication, launch amplitude

optimization, input signal detection, and an SPI interface. In

the output mode, the LMH0387 features include two se-

lectable slew rates for SMPTE 424M / 292M and SMPTE

259M compliance, and output driver power down control.

The device is available in a 7 x 7 mm 48-pin laminate Thin

Chip Scale Package (TCSP).

Features

■SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE

259M compliant

■Supports DVB-ASI at 270 Mbps

■Data rates: 125 Mbps to 2.97 Gbps when receiving (DC to

2.97 Gbps when driving cable)

■Equalizes up to 120 meters of Belden 1694A at 2.97 Gbps,

up to 200 meters of Belden 1694A at 1.485 Gbps, or up to

400 meters of Belden 1694A at 270 Mbps

■Integrated return loss network (no external components

required)

■Power saving modes

■Cable driver selectable slew rate

■Internally terminated 100Ω LVDS receiver outputs with

programmable common mode voltage and swing

■Programmable launch amplitude optimization for receiver

■Cable length indication

■Single 3.3V supply operation

■48-pin laminate TCSP package

■Industrial temperature range: −40°C to +85°C

Applications

■SMPTE 424M, SMPTE 292M, and SMPTE 259M serial

digital interfaces

■Digital video servers and modular equipment

■Video encoders and decoders

■Distribution amplifiers

Typical Application

30104423

LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver

Typical Application Circuit

30104401

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LMH0387

Connection Diagram

30104403

48-Pin Laminate TCSP

Order Number LMH0387SL

NS Package Number SLD48A

Ordering Information

Part Number Package Quantity

LMH0387SL 48-Pin Laminate TCSP, 7.0 x 7.0 x 0.8 mm, 0.5 mm pitch Reel of 1000

LMH0387SLE 48-Pin Laminate TCSP, 7.0 x 7.0 x 0.8 mm, 0.5 mm pitch Reel of 250

LMH0387SLX 48-Pin Laminate TCSP, 7.0 x 7.0 x 0.8 mm, 0.5 mm pitch Reel of 2500

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LMH0387

Pin Descriptions

Pin Name I/O, Type Description

1, 4-7, 9–16,

42, 46-48

RSVD N/A Do not connect.

2, 3, 43 VCCTX Power Positive power supply for transmitter (+3.3V).

8 BNC_IO I/O, SDI Serial digital interface input or output for connection to a BNC. Connect this pin

to the BNC via an AC coupling capacitor (nominally 4.7μF).

17 TERMRX I, SDI Termination for unused receiver (equalizer) input. This network should consist

of a 1.0 µF capacitor followed by a 220Ω resistor to ground.

18 SPI_EN I, LVCMOS SPI register access enable (equalizer). This pin should always be high; it must

be pulled high while operating in the input mode and may optionally be pulled

high while operating in the output mode. This pin has an internal pulldown.

19, 24, 25, 31,

32, 35, 37, 41

VEE Power Negative power supply (ground).

20, 21 AEC+, AEC- I/O, Analog AEC loop filter external capacitor for equalizer (1.0 µF connected between

AEC+ and AEC-).

22 CD O, LVCMOS Carrier detect for BNC_IO pin.

H = No input signal detected on BNC_IO pin.

L = Input signal detected on BNC_IO pin.

23 CDTHRESH I, Analog Carrier detect threshold input. Sets the threshold for CD. CDTHRESH may be

either unconnected or connected to ground for normal CD operation.

26 SS (SPI) I, LVCMOS SPI slave select. This pin has an internal pullup.

27, 28 SDO, SDO O, LVDS Serial data differential output from receiver (equalizer).

29 MISO (SPI) O, LVCMOS SPI Master Input / Slave Output. LMH0387 control data transmit.

30 VCCRX Power Positive power supply for receiver (+3.3V).

33, 34 SDI, SDI I, SDI Serial data differential input for transmitter (cable driver).

36 RREF I, Analog BNC_IO output driver level control. Connect a resistor (nominally 715Ω) to

VCC to set the output voltage swing for the BNC_IO pin.

38 SCK (SPI) I, LVCMOS SPI serial clock input.

39 MOSI (SPI) I, LVCMOS SPI Master Output / Slave Input. LMH0387 control data receive.

40 TX_EN I, LVCMOS Transmitter output driver enable. TX_EN has an internal pullup.

H = BNC_IO output driver is enabled.

L = BNC_IO output driver is powered off.

To configure the LMH0387 as a receiver, the BNC_IO output driver must be

disabled by tying TX_EN low. To configure the LMH0387 as a transmitter, the

output driver must be enabled by tying TX_EN high and the receiver may be

powered down using the sleep mode setting via the SPI.

44 SD/HD I, LVCMOS BNC_IO output slew rate control. SD/HD has an internal pulldown.

H = BNC_IO output rise/fall time complies with SMPTE 259M (SD).

L = BNC_IO output rise/fall time complies with SMPTE 424M / 292M (3G/HD).

45 TERMTX O, SDI Termination for unused transmitter (cable driver) output. This network should

consist of a 4.7 µF capacitor followed by a 75Ω resistor to ground.

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LMH0387

Absolute Maximum Ratings (Note 1)

Supply Voltage 4.0V

Input Voltage (all inputs) −0.3V to VCC+0.3V

Storage Temperature Range −65°C to +150°C

Junction Temperature +125°C

Package Thermal Resistance

θJA 48-pin TCSP

θJC 48-pin TCSP

65°C/W

36°C/W

ESD Rating (HBM) ≥±6 kV

ESD Rating (MM) ≥±300V

ESD Rating (CDM) ≥±2.5 kV

Recommended Operating

Conditions

Supply Voltage (VCC – VEE) 3.3V ±5%

BNC_IO Input / Output Coupling

Capacitance 4.7 µF

AEC Capacitor (Connected between

AEC+ and AEC-) 1.0 µF

Operating Free Air Temperature (TA) −40°C to +85°C

Control Pin Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 2, Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

VIH Input Voltage High Level Logic Inputs 2.0 VCC V

VIL Input Voltage Low Level VEE 0.8 V

VOH Output Voltage High Level IOH = -2 mA Logic Outputs 2.4 V

VOL Output Voltage Low Level IOL = +2 mA 0.4 V

Input Mode (Equalizer) DC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 2, Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

VIN Input Voltage Swing 0m cable length, (Note 5) BNC_IO 720 800 950 mVP−P

VSSP-P Differential Output Voltage, P-P 100Ω load, default register

settings (Note 6), Figure 1

SDO, SDO 500 700 900 mVP-P

VOD Differential Output Voltage 250 350 450 mV

ΔVOD Change in Magnitude of VOD for

Complimentary Output States 50 mV

VOS Offset Voltage 1.125 1.25 1.375 V

ΔVOS Change in Magnitude of VOS for

Complimentary Output States 50 mV

IOS Output Short Circuit Current 30 mA

CDTHRESH DC Voltage (floating) CDTHRESH 1.3 V

CDTHRESH Range 0.8 V

ICC Supply Current Equalizing cable > 120m

(Belden 1694A), TX_EN = 0

91 113 mA

Equalizing cable ≤ 120m

(Belden 1694A), TX_EN = 0,

(Note 7)

71 mA

Power save mode (equalizer in

sleep mode, TX_EN = 0)

11 mA

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LMH0387

Output Mode (Cable Driver) DC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 2, Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

VCMOUT Output Common Mode Voltage BNC_IO VCC –

VOUT

VOUT Output Voltage Swing RREF = 715Ω 1% 720 800 880 mVP-P

VCMIN Input Common Mode Voltage SDI, SDI 0.9 +

VID/2 VCC –

VID/2 V

VID Input Voltage Swing Differential 100 2200 mVP-P

ICC Supply Current SD/HD = 0, equalizer in sleep

mode

57 71 mA

SD/HD = 1, equalizer in sleep

mode

50 mA

Power save mode (TX_EN = 0,

equalizer in sleep mode)

11 mA

Loopback mode (Tx and Rx

both enabled), SD/HD = 0

117 mA

Input Mode (Equalizer) AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

DRMIN Minimum Input Data Rate BNC_IO 125 Mbps

DRMAX Maximum Input Data Rate 2970 Mbps

tjit Equalizer Jitter for Various Cable

Lengths

270 Mbps, Belden 1694A,

0-350 meters, (Note 8, Note 9)

SDO, SDO 0.2 UI

270 Mbps, Belden 1694A,

350-400 meters, (Note 9) 0.2 UI

1.485 Gbps, Belden 1694A,

0-170 meters, (Note 8, Note 9) 0.25 UI

1.485 Gbps, Belden 1694A,

170-200 meters, (Note 9) 0.3 UI

2.97 Gbps, Belden 1694A,

0-100 meters, (Note 8, Note 9) 0.3 UI

2.97 Gbps, Belden 1694A,

100-120 meters, (Note 9) 0.35 UI

tr, tfOutput Rise Time, Fall Time 20% – 80%, 100Ω load,

(Note 4), Figure 1 80 130 ps

Δtr, ΔtfMismatch in Rise/Fall Time (Note 4) 2 15 ps

tOS Output Overshoot (Note 4) 1 5 %

RLIN Input Return Loss 5 MHz - 1.5 GHz,

(Note 4, Note 10)

BNC_IO 15 dB

1.5 GHz - 3.0 GHz,

(Note 4, Note 10)10 dB

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LMH0387

Output Mode (Cable Driver) AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

DRMAX Maximum Input Data Rate SDI, SDI 2970 Mbps

tjit Additive Jitter 2.97 Gbps, (Note 11) BNC_IO 20 psP-P

1.485 Gbps, (Note 11) 18 psP-P

270 Mbps, (Note 11) 15 psP-P

tr, tfOutput Rise Time, Fall Time SD/HD = 0, 20% – 80% 65 130 ps

SD/HD = 1, 20% – 80% 400 800 ps

Δtr, ΔtfMismatch in Rise/Fall Time SD/HD = 0 30 ps

SD/HD = 1 50 ps

Duty Cycle Distortion SD/HD = 0, (Note 4) 30 ps

SD/HD = 1, (Note 4) 100 ps

tOS Output Overshoot SD/HD = 0, (Note 4) 10 %

SD/HD = 1, (Note 4) 8 %

RLOUT Output Return Loss 5 MHz - 1.5 GHz,

(Note 4, Note 10)15 dB

1.5 GHz - 3.0 GHz,

(Note 4, Note 10)10 dB

Input Mode (Equalizer) SPI Interface AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).

Symbol Parameter Conditions Reference Min Typ Max Units

Recommended Input Timing Requirements

fSCK SCK Frequency SCK 20 MHz

tPH SCK Pulse Width High Figure 2, Figure 3 40 % SCK

period

tPL SCK Pulse Width Low 40 % SCK

period

tSU MOSI Setup Time Figure 2, Figure 3 MOSI 4 ns

tHMOSI Hold Time 4 ns

tSSSU SS Setup Time Figure 2, Figure 3 SS 4 ns

tSSH SS Hold Time 4 ns

tSSOF SS Off Time 10 ns

Switching Characteristics

tODZ MISO Driven-to-Tristate Time Figure 3 MISO 15 ns

tOZD MISO Tristate-to-Driven Time 15 ns

tOD MISO Output Delay Time 15 ns

Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of

these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics"

specifies acceptable device operating conditions.

Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to

VEE = 0 Volts.

Note 3: Typical values are stated for VCC = +3.3V and TA = +25°C.

Note 4: Specification is guaranteed by characterization.

Note 5: The LMH0387 equalizer can be optimized for different launch amplitudes via the SPI.

Note 6: The differential output voltage and offset voltage are adjustable via the SPI.

Note 7: The equalizer automatically shifts equalization stages at cable lengths less than or equal to 120m (Belden 1694A) to reduce power consumption. This

power savings is also achieved by setting Extended 3G Reach Mode = 1 via the SPI. (Note: Forcing the Extended 3G Reach Mode in this way increases the

cable reach for 3G data rates but also limits the achievable cable lengths at HD and SD data rates).

Note 8: Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in accordance with

SMPTE RP 184, SMPTE RP 192, and the applicable serial data transmission standard: SMPTE 424M, SMPTE 292M, or SMPTE 259M.

Note 9: LMH0387 equalizer launch amplitude fine tuning set to nominal via the SPI by writing 30h (“00110000 binary”) to SPI register 02h.

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LMH0387

Note 10: Return loss is dependent on board design. The LMH0387 exceeds this specification on the SD387 evaluation board.

Note 11: Cable driver additive jitter is measured with the input AC coupled.

Timing Diagrams

30104408

FIGURE 1. LVDS Output Voltage, Offset, and Timing Parameters

30104409

FIGURE 2. SPI Write

30104410

FIGURE 3. SPI Read

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LMH0387

Device Description

The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive

Cable Equalizer / Cable Driver is used at the input or output

port of digital video equipment. It is designed to allow the

sharing of a single BNC connector for either input or output.

CONFIGURING THE INPUT (EQUALIZER) OR OUTPUT

(CABLE DRIVER) MODE

The LMH0387 must be configured in either the input mode as

an equalizer, or the output mode as a cable driver.

Input Mode (Equalizer)

To configure the LMH0387 in the input mode, the equalizer

must be enabled and the cable driver must be disabled as

described in the following steps:

1. Disable the cable driver by pulling the TX_EN pin low.

2. Enable the equalizer by setting the sleep mode via the

SPI to either auto sleep or disabled (never sleep). To do

this, write either “01” (auto sleep – default) or “00” (never

sleep) to bits [4:3] of SPI register 00h.

3. Set the equalizer launch amplitude fine tuning to the

nominal setting via the SPI. To do this, write 30h

(“00110000” binary) to SPI register 02h.

Output Mode (Cable Driver)

To configure the LMH0387 in the output mode, the cable driv-

er must be enabled. The equalizer may either be disabled for

power savings or enabled to provide a loopback path for the

data being transmitted. For the normal output mode (equal-

izer disabled for power savings) follow these steps:

1. Disable the equalizer by forcing it to sleep via the SPI. To

do this, write “10” (force sleep) to bits [4:3] of SPI register

00h.

2. Enable the cable driver by pulling the TX_EN pin high.

To configure the LMH0387 for the output mode with the loop-

back path, the equalizer can be enabled in output mode by

writing either “01” (auto sleep – default) or “00” (never sleep)

to bits [4:3] of SPI register 00h. In this case, the LMH0387

input/output mode may be configured simply by toggling the

TX_EN pin since the equalizer remains active in either mode

(TX_EN set low for input mode and high for output mode).

Input Mode (Equalizer) Description

SPI register access is required while operating the LMH0387

in the input mode. The equalizer launch amplitude fine tuning

must be set to nominal via the SPI for correct equalizer op-

eration. To do this, write 30h (“00110000 binary”) to SPI

useful LMH0387 features while in the input mode. Refer to the

Input Mode (Equalizer) SPI Register Access section for de-

tails.

INPUT INTERFACING

The LMH0387 accepts single-ended input at the BNC_IO pin.

The input must be AC coupled. The Typical Application Cir-

cuit diagram shows the typical configuration. The TERMRX

input must be properly terminated with a 1.0 µF capacitor fol-

lowed by a 220Ω resistor to ground as shown.

The LMH0387 BNC_IO input can be optimized for different

launch amplitudes via the SPI (see LAUNCH AMPLITUDE

OPTIMIZATION (REGISTER 02h) in the Input Mode (Equal-

izer) SPI Register Access section).

The LMH0387 correctly handles equalizer pathological sig-

nals for standard definition and high definition serial digital

video, as described in SMPTE RP 178 and RP 198, respec-

tively.

OUTPUT INTERFACING

The LMH0387 equalizer outputs, SDO and SDO, are inter-

nally terminated 100Ω LVDS outputs. These outputs can be

DC coupled to most common differential receivers.

The default output common mode voltage (VOS) is 1.25V. The

output common mode voltage may be adjusted via the SPI in

200 mV increments, from 1.05V to 1.85V (see OUTPUT

DRIVER ADJUSTMENTS (REGISTER 01h) in the Input

Mode (Equalizer) SPI Register Access section). This ad-

justable output common mode voltage offers flexibility for

interfacing to many types of receivers.

The default differential output swing (VSSP-P) is 700 mVP-P.

The differential output swing may be adjusted via the SPI in

100 mV increments from 400 mVP-P to 800 mVP-P (see OUT-

PUT DRIVER ADJUSTMENTS (REGISTER 01h) in the Input

Mode (Equalizer) SPI Register Access section).

The LMH0387 equalizer output should be DC coupled to the

input of the receiving device as long as the common mode

ranges of both devices are compatible. 100Ω differential

transmission lines should be used to connect between the

LMH0387 outputs and the input of the receiving device where

possible.

The LMH0387 allows flexibility when interfacing to low voltage

crosspoint switches (i.e. 1.8V) and other devices with limited

input ranges. The LMH0387 equalizer outputs can be DC

coupled to these devices in most cases, avoiding the need to

AC couple.

The LMH0387 may be AC coupled to the receiving device

when necessary. For example, the LMH0387 equalizer out-

puts are not strictly compatible with 3.3V CML and thus should

not be connected via 50Ω resistors to 3.3V. If the input com-

mon mode range of the receiving device is not compatible with

the output common mode range of the LMH0387, then AC

coupling is required. Following the AC coupling capacitors,

the signal may have to be biased at the input of the receiving

device.

CARRIER DETECT (CD)

Carrier detect CD indicates if a valid signal is present at the

LMH0387 BNC_IO pin. If CDTHRESH is used, the carrier detect

threshold will be altered accordingly. CD provides a high volt-

age when no signal is present at the LMH0387 BNC_IO pin.

CD is low when a valid input signal is detected.

CARRIER DETECT THRESHOLD (CDTHRESH)

The CDTHRESH pin sets the threshold for the carrier detect.

The carrier detect threshold is set by applying a voltage in-

versely proportional to the length of cable to equalize before

loss of carrier is triggered. The applied voltage must be

greater than the CDTHRESH floating voltage (typically 1.3V) in

order to change the CD threshold. As the applied CDTHRESH

voltage is increased, the amount of cable that will be equal-

ized before carrier detect is de-asserted is decreased.

CDTHRESH may be left unconnected or connected to ground

for normal CD operation.

Figure 4 shows the minimum CDTHRESH input voltage required

to force carrier detect to inactive vs. Belden 1694A cable

length. The results shown are valid for Belden 1694A cable

lengths of 0-120m at 2.97 Gbps, 0-200m at 1.485 Gbps, and

0-400m at 270 Mbps.

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LMH0387

30104412

FIGURE 4. CDTHRESH vs. Belden 1694A Cable Length

AUTO SLEEP

The LMH0387 equalizer is set for auto sleep operation by de-

fault. The equalizer portion of the LMH0387 powers down

when no input signal is detected on the BNC_IO pin. The

equalizer powers on again once an input signal is detected.

The auto sleep functionality can be changed to force sleep or

turned off completely via the SPI registers.

In auto sleep mode, the time to power down the equalizer

when the input signal is removed is less than 200 µs and

should not have any impact on the system timing require-

ments. The equalizer will wake up automatically once an input

signal is detected, and the delay between signal detection and

full functionality of the equalizer is negligible. The overall sys-

tem will be limited only by the settling time constant of the

equalizer adaptation loop.

Input Mode (Equalizer) SPI Register

Access

SPI register access is required for correct input mode (equal-

izer) operation. The SPI registers provide access to all of the

equalizer features along with a cable length indicator, pro-

grammable output common mode voltage and swing, and

launch amplitude optimization. There are four supported 8-bit

registers in the device (see Table 1).

Note: The SPI_EN pin must always be pulled high while using

the LMH0387 in the input mode (equalizer), and may option-

ally be pulled high while using the LMH0387 in the output

mode (cable driver) as well.

SPI Write

The SPI write is shown in Figure 2. The MOSI payload con-

sists of a “0” (write command), seven address bits, and eight

data bits. The SS signal is driven low, and the 16 bits are sent

to the LMH0387's MOSI input. Data is latched on the rising

edge of SCK. The MISO output is normally tri-stated during

this operation. After the SPI write, SS must return high.

SPI Read

The SPI read is shown in Figure 3. The MOSI payload con-

sists of a “1” (read command) and seven address bits. The

SS signal is driven low, and the eight bits are sent to the

LMH0387's MOSI input. The addressed location is accessed

immediately after the rising edge of the 8th clock and the eight

data bits are shifted out on MISO starting with the falling edge

of the 8th clock. MOSI must be tri-stated immediately after the

rising edge of the 8th clock. After the SPI read, SS must return

high.

GENERAL CONTROL (REGISTER 00h)

SPI Register 00h, General Control, provides access to many

basic features of the equalizer, including the carrier detect

status and the mute, sleep mode, and extended 3G reach

mode controls.

Carrier Detect

This bit shows the status of the carrier detect for the BNC_IO

pin.

Mute

The mute control can be used to manually mute or enable

SDO and SDO. Setting this bit to “1” will mute the equalizer

outputs by forcing them to logic zero. Setting the mute bit to

“0” will force the equalizer outputs to be active.

Sleep Mode

The sleep mode is used to automatically or selectively power

down the equalizer for power savings when it is not needed.

The auto sleep mode allows the equalizer to power down

when no input signal is detected, and is activated by default

or by writing “01” to bits [4:3] of SPI register 00h. If the auto

sleep mode is active, the equalizer goes into a deep power

save mode when no input signal is detected on the BNC_IO

pin. The device powers on again once an input signal is de-

tected. The sleep functionality can be turned off completely

(equalizer will never sleep) by writing “00” to bits [4:3] of SPI

er down regardless of whether there is an input signal or not

by writing “10” to bits [4:3] of SPI register 00h. The sleep mode

has precedence over the mute mode.

Extended 3G Reach Mode

The LMH0387 equalizer provides a mode to extend the 3G

cable reach in systems which have margin in the jitter budget.

This allows for additional cable reach at 2.97 Gbps at the ex-

pense of slightly higher output jitter. The extended 3G reach

mode provides 10m of additional Belden 1694A cable reach,

with an increase of output jitter at this longer cable length of

0.05 to 0.1 UI. (Note: In Extended 3G Reach Mode, the max-

imum equalizable cable lengths for HD and SD data rates will

be limited to less than what can be achieved in normal mode).

OUTPUT DRIVER ADJUSTMENTS (REGISTER 01h)

The equalizer output driver swing (amplitude) and offset volt-

age (common mode voltage) are adjustable via SPI register

01h.

Output Swing

The output swing is adjustable via bits [7:5] of SPI register

01h. The default value for these register bits is “011” for a

peak to peak differential output voltage of 700 mVP-P. The

output swing can be adjusted in 100 mV increments from 400

mVP-P to 800 mVP-P.

Offset Voltage

The offset voltage is adjustable via bits [4:2] of SPI register

01h. The default value for these register bits is “001” for an

output offset of 1.25V. The output common mode voltage may

be adjusted in 200 mV increments, from 1.05V to 1.85V. It can

also be set to “101” for the maximum offset voltage. At this

maximum offset voltage setting, the outputs are referenced to

the positive supply and the offset voltage is around 2.1V.

LAUNCH AMPLITUDE OPTIMIZATION (REGISTER 02h)

The LMH0387 can compensate for attenuation of the input

signal prior to the equalizer. This compensation is useful for

applications with a passive splitter at the equalizer input or a

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LMH0387

non-ideal input termination network, and is controlled by SPI

For correct equalizer operation with the default SMPTE

800 mVP-P launch amplitude and no external attenuation,

the equalizer launch amplitude fine tuning must be set to

the “nominal” setting via the SPI. To do this, write 30h

(“00110000” binary) to SPI register 02h.

Coarse Control

Bit 7 of SPI register 02h is used for coarse control of the

launch amplitude setting. At the default setting of “0”, the

equalizer operates normally and expects a launch amplitude

of 800 mVP-P. Bit 7 may be set to “1” to optimize the equalizer

for input signals with 6 dB of attenuation (400 mVP-P).

Fine Control

Once the coarse control is set, the equalizer input compen-

sation may be further fine tuned by bits [6:3] of SPI register

02h. These bits may be used to tweak the input gain stage

-2% to +60% around the coarse control setting. For typical

equalizer operation, bits [6:3] of SPI register 02h should be

changed from the default setting of “0000” to the nominal set-

ting of “0110”.

CABLE LENGTH INDICATOR (CLI) (REGISTER 03h)

The Cable Length Indicator (CLI) provides an indication of the

length of cable attached to the equalizer input. CLI is acces-

sible via bits [7:3] of SPI register 03h. The 5-bit CLI ranges in

decimal value from 0 to 25 (“00000” to “11001” binary) and

increases as the cable length is increased. Figure 5 shows

typical CLI values vs. Belden 1694A cable length. CLI is valid

for Belden 1694A cable lengths of 0-120m at 2.97 Gbps,

0-200m at 1.485 Gbps, and 0-400m at 270 Mbps.

30104411

FIGURE 5. CLI vs. Belden 1694A Cable Length

Output Mode (Cable Driver)

Description

INPUT INTERFACING

The LMH0387 cable driver accepts differential input signals

which can be DC or AC coupled.

OUTPUT INTERFACING

The LMH0387 cable driver uses 75Ω internally terminated

current mode outputs. The output level is 800 mVP-P with an

RREF resistor of 715Ω. The RREF resistor is connected be-

tween the RREF pin and VCC, and should be placed as close

as possible to the RREF pin.

The output should be AC coupled as shown in the Typical

Application Circuit diagram. The TERMTX output must be

properly terminated with a 4.7 µF capacitor followed by a

75Ω resistor to ground as shown.

OUTPUT SLEW RATE CONTROL

The LMH0387 cable driver output rise and fall times are se-

lectable for either SMPTE 259M or SMPTE 424M / 292M

compliance via the SD/HD pin. For slower rise and fall times,

or SMPTE 259M compliance, SD/HD is set high. For faster

rise and fall times, or SMPTE 424M and SMPTE 292M com-

pliance, SD/HD is set low. SD/HD has an internal pulldown.

OUTPUT ENABLE

The LMH0387 cable driver can be enabled or disabled with

the TX_EN pin. When set low, the cable driver is powered off.

TX_EN has an internal pullup to enable the cable driver by

default. When using the LMH0387 in the input mode (as an

equalizer), the cable driver must be disabled by setting the

TX_EN pin low.

11 www.national.com

LMH0387

Application Information

PCB LAYOUT RECOMMENDATIONS

For information on layout and soldering of the laminate TCSP

package, pease refer to the following application note:

AN-1125, “Laminate CSP/FBGA.”

For a CSP package, it is a general requirement not to have

any metal (traces or vias) on the top layer in the area di-

rectly underneath the device, other than the footprint.

This is intended to provide a flat planar surface for the

package.

The SMPTE 424M, 292M, and 259M standards have strin-

gent requirements for the input and output return loss of

receivers and transmitters, which essentially specify how

closely they must resemble a 75Ω network. Any non-idealities

in the network between the BNC and the LMH0387 will de-

grade the return loss. Care must be taken to minimize

impedance discontinuities both for the BNC footprint and for

the trace between the BNC and the LMH0387 to ensure that

the characteristic impedance is 75Ω. Best return loss perfor-

mance is achieved with the LMH0387 placed closely to the

BNC to minimize the trace length between the BNC and the

LMH0387's BNC_IO pin. Please consider the following PCB

recommendations:

•Place the LMH0387 in close proximity to the BNC.

•Use surface mount components, and use the smallest

components available. In addition, use the smallest size

component pads.

•Select trace widths that minimize the impedance

mismatch between the BNC and the LMH0387.

•Select a board stack up that supports both 75Ω single-

ended traces and 100Ω loosely-coupled differential

traces.

•Maintain symmetry on the complimentary signals.

•Route 100Ω traces uniformly (keep trace widths and trace

spacing uniform along the trace).

•Avoid sharp bends in the signal path; use 45° or radial

bends.

•Place bypass capacitors close to each power pin, and use

the shortest path to connect device power and ground pins

to the respective power or ground planes.

•Remove ground plane under input/output components to

minimize parasitic capacitance.

www.national.com 12

LMH0387

Typical Performance

Characteristics

Equalizer Output at 2.97 Gbps with 120m Belden 1694A

30104421

H: 100 ps / div, V: 50 mV / div

(SDO output shown)

Cable Driver Output at 2.97 Gbps

30104420

H: 62.5 ps / div, V: 100 mV / div

(BNC_IO output shown)

Output Return Loss

30104422

13 www.national.com

LMH0387

SPI Registers

TABLE 1. SPI Registers

Address R/W Name Bits Field Default Description

00h R/W General Control 7 Carrier Detect Read only.

0: No carrier detected on BNC_IO pin.

1: Carrier detected on BNC_IO pin.

6 Mute 0 0: Normal operation.

1: Equalizer outputs muted.

5 Reserved 0 Reserved as 0. Always write 0 to this bit.

4:3 Sleep Mode 01 Equalizer sleep mode control. Sleep has precedence over

Mute.

00: Never sleep. Disable sleep mode (force equalizer to stay

enabled).

01: Auto sleep. Sleep mode active when no input signal

detected.

10: Force sleep. Force equalizer into sleep mode (powered

down) regardless of whether there is an input signal or not.

11: Reserved.

2 Extended 3G

Reach Mode

0 Extended 3G reach mode to extend the equalizable cable

length for 2.97 Gbps applications.

0: Normal operation.

1: Extended 3G reach mode.

1:0 Reserved 00 Reserved as 00. Always write 00 to these bits.

01h R/W Output Driver 7:5 Output Swing 011 Equalizer output driver swing (VSSP-P).

000: VSSP-P = 400 mVP-P.

001: VSSP-P = 500 mVP-P.

010: VSSP-P = 600 mVP-P.

011: VSSP-P = 700 mVP-P.

100: VSSP-P = 800 mVP-P.

101, 110, 111: Reserved.

4:2 Offset Voltage 001 Equalizer output driver offset voltage (common mode

voltage).

000: VOS = 1.05V.

001: VOS = 1.25V.

010: VOS = 1.45V.

011: VOS = 1.65V.

100: VOS = 1.85V.

101: VOS referenced to positive supply.

110, 111: Reserved.

1:0 Reserved 00 Reserved as 00. Always write 00 to these bits.

www.national.com 14

LMH0387

Address R/W Name Bits Field Default Description

02h R/W Launch

Amplitude

7 Coarse Control 0 Coarse launch amplitude optimization for equalizer input.

0: Normal optimization with no external attenuation (800

mVP-P launch amplitude).

1: Optimized for 6 dB external attenuation (400 mVP-P

launch amplitude).

6:3 Fine Control 0000 Launch amplitude optimization fine tuning for equalizer

input.

0000: +20% from nominal.

0001: +16% from nominal.

0010: +12% from nominal.

0011: +9% from nominal.

0100: +6% from nominal.

0101: +3% from nominal.

0110: Nominal. (The default setting must be changed to this

nominal setting for most applications).

0111: -2% from nominal.

1001: +24% from nominal.

1010: +29% from nominal.

1011: +34% from nominal.

1100: +40% from nominal.

1101: +46% from nominal.

1110: +53% from nominal.

1111: +60% from nominal.

1000: Reserved.

2:0 Reserved 000 Reserved as 000. Always write 000 to these bits.

03h R CLI 7:3 CLI Cable Length Indicator. Provides an indication of the length

of cable attached to the equalizer input. CLI increases as

the cable length increases.

2:0 Reserved 000 Reserved.

15 www.national.com

LMH0387

Physical Dimensions inches (millimeters) unless otherwise noted

48-Pin Laminate TCSP

Order Number LMH0387SL

NS Package Number SLD48A

www.national.com 16

LMH0387

Notes

17 www.national.com

LMH0387

Notes

LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver

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