
W olfson Microelectronics 11
WM0831, WM0832
Initiating Conversion and the Digital Interface
WM0831 and WM0832 are controlled from a processor
via a Chip Select (CS) input and a serial interface
comprising Data Out (DO) and additionally for WM0832 a
Data In (DI) input.
For WM0831 conversion is initiated by pulling chip select
low and inputting a clock signal. On the clock's first falling
edge after CS is brought low, DO output comes out of
high impedance mode. On the second and subsequent
clock falling edges, to a total of nine, the conversion
result is output on DO in MSB to LSB order . WM0831 only
provides output data in MSB first order.
For WM0832 conversion is also initiated by pulling the chip
select (CS) line low and inputting a clock signal but MUX
addressing information has also to be input on DI. The
start bit and the MUX assignment bits on DI are clocked
in on the first three rising edges of the clock input which
may be generated by the processor or run continuously.
WM0832 uses two MUX assignment bits.
When the logic “1” start bit is clocked into the start
conversion location of the multiplexer input register the
analogue MUX inputs are selected. After 1/2 a clock
period delay to allow for the selected MUX output to settle
the conversion commences using the successive
approximation technique.
When conversion begins the A/D conversion result from
the output of the SARS comparator appears at the DO
output on each falling edge of the clock (see Functional
Timing Diagrams).
With the successive approximation A/D conversion
routine the analogue input is compared with the output of
a digital to analogue converter (DAC) for each bit by the
SARS comparator and a decision made on whether the
analogue input is higher or lower than the DAC output.
Successive bits, MSB to LSB, are input to the DAC and
remain in its input if the analogue comparison decides
the analogue input is higher than the DAC output, if not
the bit is removed from the DAC input. There is no sample
and hold. The input needs to be stable during Tconv period
(see Functional T iming Diagrams).
The output from the SARS comparator forms the
resulting input to the DAC and the A/D conversion output
on DO, and is read by the processor as conversion takes
place in MSB to LSB order. After 8 clock periods the
conversion is complete.
Functional Description (continued)
For WM0832 the 8 bits of the conversion are stored in an
output shift register , after a conversion has completed and
MSB first data has been output WM0832 automatically
shifts out LSB first data on the DO output.
CS must be held low through an entire conversion, all
internal registers are cleared when CS is high. To initiate
another conversion CS must make a high to low transition
and for WM0832 MUX address assignments input to DI.
For WM0832 the DI input and DO output can be tied
together and controlled via a bidirectional processor I/O
bit line.
Reference Input
The analogue input voltage range, Vmax to Vmin for
differential inputs is defined by the voltage applied to the
reference input with respect to GND. WM0832 is fixed in a
ratiometric mode with VREF internally tied to Vcc, WM0832
has a separate VREF pin and can be used in either
ratiometric applications or those requiring absolute
accuracy.
A ratiometric reference input, typically the Vcc, is the same
supply used to power analogue input circuitry and
sensors. In such systems under a given input condition
the same code will be output with variations in supply
voltage because the same ratio change occurs in both the
analogue and reference input to the A/D. When used in
applications requiring absolute accuracy a suitable time
and temperature stable voltage reference source should
be used.
The voltage source used to drive the reference input should
be capable of driving the 2.4 kΩ typical of the SAR
resistor ladder. The maximum input voltage to the
reference input is the Vcc supply voltage. The minimum
for WM0832 can be at least as low as 1 V to allow for
direct conversion of sensor outputs with output voltage
ranges less than 5 V.