19-3886; Rev 1; 8/06
General Description
The MAX8809A/MAX8810A synchronous, 2-/3-/4-
phase, step-down, current-mode controllers with inte-
grated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel®VRD11/VRD10
and AMD K8 Rev F CPU core supplies. The flexible
design supplies load currents up to 150A for low-volt-
age CPU core power requirements.
A tri-state SEL input is available to configure the VID
logic for either the Intel VRD11/VRD10 or AMD K8 Rev F
applications. An enable input (EN) is available to dis-
able the IC. True-differential remote output-voltage
sensing enables precise regulation at the load by elimi-
nating the effects of trace impedance in the output and
return paths. A high-accuracy DAC combined with pre-
cision current-sense amplifiers and droop control
enable the MAX8809A/MAX8810A to meet the most
stringent tolerance requirements of new-generation
high-current CPUs. These ICs use either integral or volt-
age-positioning feedback control to achieve high out-
put-voltage accuracy.
The COMP input allows for either positive or negative
voltage offsets from the VID code voltage. A power-
good signal (VRREADY) is provided for startup
sequencing and fault annunciation. The SS/OVP pin
enables the programming of the soft-start period, and
provides an indication of an overvoltage condition. A
soft-stop feature prevents negative voltage spikes on
the output at turn-off, eliminating the need for an exter-
nal Schottky clamp diode.
The MAX8809A/MAX8810A incorporate a proprietary
“rapid active average” current-mode control scheme for
fast and accurate transient-response performance, as
well as precise load current sharing. Either the inductor
DCR or a resistive current-sensing element is used for
current sensing. When used with DCR sensing, rapid
active current averaging (RA2) eliminates the tolerance
effects of the inductance and associated current-sens-
ing components, providing superior phase current
matching, accurate current limit, and precise load-line.
The MAX8809A operates as a single-chip, 2-phase
solution with integrated drivers. It also provides a 3rd-
phase PWM output and easily supports 3-phase design
by adding the MAX8552 high-performance driver. The
MAX8810A enables up to 4-phase designs by adding
the MAX8523 high-performance dual driver for a com-
pact 2-chip solution.
Features
♦VRD11/VRD10 and K8 Rev F Compliant
♦±0.35% Initial Output Voltage Accuracy
♦Dual Integrated Drivers with Integrated Bootstrap
Diodes
♦Up to 26V Input Voltage
♦Adaptive Shoot-Through Protection
♦Soft-Start, Soft-Stop, VRREADY Output
♦Fast Load Transient Response
♦Individual Phase, Fully Temperature-
Compensated Cycle-by-Cycle Average Current
Limit
♦Current Foldback at Short Circuit
♦Voltage Positioning or Integral Feedback
♦Differential Remote Voltage Sensing
♦Programmable Positive and Negative Offset
Voltages
♦150kHz to 1.2MHz Switching Frequency per Phase
♦NTC-Based, Temperature-Independent Load Line
♦Precise Phase Current Sharing
♦Programmable Thermal-Monitoring Output
(VRHOT)
♦6A Peak MOSFET Drivers
♦0.3Ω/0.85ΩLow-Side, 0.8Ω/1.1ΩHigh-Side
Drivers (typ)
♦40-Pin and 48-Pin Thin QFN Packages
Applications
Desktop PCs
Servers, Workstations
Desknote and LCD PCs
Voltage-Regulator Modules
MAX8809A/MAX8810A
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
+Denotes lead-free package.
Note: All parts are specified in the -40°C to +85°C extended
temperature range.
EVALUATION KIT
AVAILABLE
PART PIN-
PACKAGE
PKG
CODE
FUNCTION
MAX8809AETL+
40 Thin QFN
5mm x 5mm T4055-1
2-/3-phase
MAX8810AETM+
48 Thin QFN
6mm x 6mm T4866-1
2-/3-/4-phase
Pin Configurations appear at end of data sheet.
Intel is a registered trademark of Intel Corp.
MAX8809A/MAX8810A
2 _______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩto GND, RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 118kΩto GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
REF, COMP, SS/OVP, OSC, NTC, VRTSET,
RS+, RS-, PWM_ to GND.......................-0.3V to (VCC + 0.3V)
CS_+, CS_-, VID_, BUF, EN, ILIM, SEL, VRREADY,
VRHOT, VCC to GND............................................-0.3V to +6V
BST_ to PGND_ ......................................................-0.3V to +35V
LX_ to PGND_............................................................-1V to +28V
BST_ to VL_ ...............................................................-1V to +30V
DH_ to PGND_.........................................-0.3V to (VBST_ + 0.3V)
DH_, BST_ to LX_ .....................................................-0.3V to +7V
VL_ to PGND_ ..........................................................-0.3V to +7V
DL_ to PGND_ ..........................................-0.3V to (VVL_ + 0.3V)
PGND_ to GND......................................................-0.3V to +0.3V
CS_+ to CS_-.........................................................-0.3V to +0.3V
DH_, DL_ Current ....................................................±200mARMS
VL_ to BST_ Diode Current...........................................50mARMS
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 5mm x 5mm
(derate 35.7mW/°C above +70°C)..........................2857.1mW
48-Pin Thin QFN 6mm x 6mm
(derate 37mW/°C above +70°C)................................2963mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
VCC Operating Range 4.5 5.5 V
Rising 4.0
4.25
4.5
VCC UVLO Trip Level Falling 3.7 4.0 4.3 V
VCC Shutdown Supply Current VCC < 3.75V
0.35
mA
VCC Standby Supply Current VEN = 0V 0.5 mA
VCC Operating Supply Current VRS+ - VRS- = 1.0V, no switching, VDAC = 1.0V (Note 1) 13 mA
Thermal Shutdown Temperature rising, hyster esi s = 25° C ( typ )
+160
°C
INTERNAL REFERENCE (REF)
Output Voltage IREF = -100µA
1.992 2.000 2.008
V
Output Regulation (Sourcing) VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA
-0.05 +0.05
%
Output Regulation (Sinking) VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA
-0.2 +0.2
%
Reference UVLO Trip Level Rising (100mV typ hysteresis)
1.84
V
BUF REFERENCE
BUF Regulation Voltage IBUF = 0A
0.99
1.0
1.01
V
BUF Output Regulation VCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IBUF = +500µA
-0.25 +0.25
%
SOFT-START
EN Startup Delay (TD1) From EN rising to VOUT rising 1.6 2.2 2.8 ms
Soft-Start Period Range (TD2) 12kΩ < RSS/OVP < 90.9kΩ0.5 6.5 ms
Soft-Start Tolerance RSS/OVP = 56kΩ
2.25 3.00 3.75
ms
Intel Boot-Level Duration (TD3) SEL = GND or SEL = VCC
175 250
350 µs
MAX8809A/MAX8810A
_______________________________________________________________________________________ 3
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩto GND, RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 118kΩto GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REGULATION
RS+ Input Bias Current VRS+ = 1V 0.1 1 µA
RS- Input Bias Current VRS- = 0.2V 0.1 1 µA
Output Voltage Initial Accuracy VDAC = 1V (Note 1)
-0.35 +0.35
%
TA = +25°C to +85°C
-3.5 +3.5
Droop Accuracy VDAC = 1V (Note 1),
RNTC = 10kΩTA = -5°C to +85°C
-5.5 +5.5
%
gMV Amplifier Transconductance
1.94 2.00 2.06
mS
gMV Gain Bandwidth Product 5
MHz
Comp Output Current VDAC - VRS+ = 200mV (Note 1)
385
µA
CURRENT LIMIT
Average Current-Limit Trip Level
Accuracy VILIM = 1.5V -6 +6 %
ILIM Input Bias Current
0.01
1µA
ILIM Default Program Level VILIM > VCC - 0.2V
1.197 1.330 1.463
V
ENABLE INPUT (EN)
Turn-On Threshold (Rising) VCC = 4.5V to 5.5V, 100mV typ hysteresis 0.8
0.85
0.9 V
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)
Input Low Level VCC = 4.5V to 5.5V 0.4 V
Input High Level VCC = 4.5V to 5.5V 0.8 V
Input Pulldown Resistance
100
270 kΩ
AMD (SEL = UNCONNECTED)
Input Low Level VCC = 4.5V to 5.5V 0.6 V
Input High Level VCC = 4.5V to 5.5V 1.4 V
Input Pulldown Resistance
100
270 kΩ
LOGIC INPUT (SEL)
Internal Bias Resistance 50
100
200 kΩ
Internal Bias Voltage VCC = 4.5V to 5.5V
VCC / 2
V
Input Low Level VCC = 4.5V to 5.5V 0.5 V
Input High Level VCC = 4.5V to 5.5V VCC -
0.5 V
VRREADY OUTPUT
Output Low Level IVRREADY = +4mA 0.4 V
Output High Leakage VVRREADY = 5.5V 1 µA
VRREADY Blanking Time Fr om E N r i si ng to V RRE AD Y r isi ng, RS S /OV P
= 12kΩ3.0 5.5 ms
MAX8809A/MAX8810A
4 _______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩto GND, RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 118kΩto GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
(VRS+ - VRS-) rising VDAC +
0.150
VDAC +
0.200
VRREADY Upper Threshold
(Note 1) (VRS+ - VRS-) falling VDAC +
0.075
VDAC +
0.125
V
(VRS+ - VRS-) falling VDAC -
0.250
VDAC -
0.200
VRREADY Lower Threshold
(Note 1)
(VRS+ - VRS-) rising VDAC -
0.175
VDAC -
0.125
V
OVERVOLTAGE PROTECTION
Intel (SEL = High or Low) (VRS+ - VRS-) rising (Note 1) VDAC +
0.150
VDAC +
0.175
VDAC +
0.200
V
AMD (SEL = Unconnected) (VRS+ - VRS-) rising
1.750 1.775 1.800
V
SS/OVP High Level ISS/OVP = -10mA VCC -
0.450
V
OSCILLATOR
Oscillator Frequency Accuracy
(per Phase) Frequency per phase = 300kHz -10
+10
%
Switching Frequency Range
(per Phase) 150
1200
kHz
CURRENT-SENSE AMPLIFIERS
Current-Sense Amplifier Gain (GCA)R
NTC = 10kΩ, TA = +25°C to +85°C
28.8 30.0 31.2
V/V
CS_+ Input Bias Current VCS_+ = VCS_- = 2V 0.3 3.0 µA
CS_- Input Bias Current VCS_+ = VCS_- = 2V 0.6 5.5 µA
CS to PWM_ Delay VCOMP falling 20 ns
GAIN TEMPERATURE COMPENSATION (NTC)
Compensation Accuracy RNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103) -6 +6 %
VRHOT TEMPERATURE MONITORING
VRHOT Output Low Voltage IVRHOT = +4mA 0.4 V
VRHOT Output High Leakage Current
VVRHOT = 5.5V 5 µA
VRTSET Temperature Range
+60 +125
°C
VRTSET Accuracy RN TC
tem p er atur e = + 60° C to + 125° C , 15° C
hyster esi s ( typ ) ( 10k N TC P anasoni c E RTJ1V R103) -5 +5 °C
MAX8809A/MAX8810A
_______________________________________________________________________________________ 5
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩto GND, RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 118kΩto GND, VCS_+ = VCS_- = 1V,
PWM_ = unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= 0°C
to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
PWM DRIVER
Output Low Level IPWM_ = +5mA 0.1 0.4 V
Output High Level IPWM_ = -5mA 4.5 4.9 V
Source Current VPWM_ = VCC - 2V 52 mA
Sink Current VPWM_ = 2V 65 mA
Rise/Fall Times 10 ns
PWM Disable Program Threshold 4V < VCC < 5.5V 3.0 VCC -
0.7 V
GATE-DRIVER SPECIFICATIONS
V L_, BS T_ to LX _ Inp ut V ol tag e Rang e 4.5 6.5 V
LX Operating Range 26 V
VL_ UVLO Threshold (VL12,
MAX8809A; VL1, MAX8810A) VVL_ rising, 250mV hysteresis (typ)
3.25 3.55 3.80
V
DH_ = BST_ 1 1.6
Driver Static Supply Current, IVL_
(per Channel) DH_ = LX_ 1.1 1.8 mA
Boost Static Supply Current, IBST_
(per Channel) DH_ = BST_ 0.6 1 mA
Sourcing current, VVL _ = 6.5V 1.1 2.0
DH Driver Resistance Sinking current, VVL _ = 6.5V 0.8 1.2 Ω
Sourcing current, VVL _ = 6.5V
0.85
1.7
DL Driver Resistance Sinking current, VVL _ = 6.5V 0.3 0.6 Ω
DH_ Rise Time (trDH)C
DH_ = 3000pF 14 ns
DH_ Fall Time (tfDH)C
DH_ = 3000pF 9 ns
DL_ Rise Time (trDL)C
DL_ = 3000pF 10 ns
DL_ Fall Time (tfDL)C
DL_ = 3000pF 7 ns
DH_ Propagation Delay (tpDHf) CS+ rising to DH falling 32 ns
Dead Time (tpDLr) LX_ falling to DL_ rising 18 ns
Dead Time (tDEAD) DL_ falling to DH_ rising 35 ns
INTERNAL BOOST-DIODE SPECIFICATIONS
On-Resistance IBST_ = 2mA 6 Ω
MAX8809A/MAX8810A
6 _______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
VCC Operating Range 4.5 5.5 V
Rising 4.0 4.5
VCC UVLO Trip Level Falling 3.7 4.3 V
INTERNAL REFERENCE (REF)
Output Voltage IREF = -100µA
1.99 2.01
V
Output Regulation (Sourcing) VCC = 4.5V at IREF = -500µA to VCC = 5.5V at
IREF = -100µA
-0.065 +0.065
%
Output Regulation (Sinking) VCC = 4.5V at IREF = +100µA to VCC = 5.5V at
IREF = +500µA
-0.2 +0.2
%
BUF REFERENCE
BUF Regulation Voltage IBUF = 0A
0.99 1.01
V
BUF Output Regulation VCC = 4.5V at IBUF = +100µA to VCC = 5.5V at
IREF = +500µA
-0.4 +0.4
%
SOFT-START
EN Startup Delay (TD1) From EN rising to VOUT rising 1.6 2.8 ms
Soft-Start Period Range (TD2) 12kΩ < RSS/OVP < 90.9kΩ0.5 6.5 ms
Soft-Start Tolerance RSS/OVP = 56kΩ
2.25 3.75
ms
Intel Boot Level Duration (TD3) SEL = GND or SEL = VCC
175 350
µs
VOLTAGE REGULATION
RS+ Input Bias Current VRS+ = 1.0V 1 µA
RS- Input Bias Current VRS- = 0.2V 1 µA
Output-Voltage Initial Accuracy VDAC_ = 1V (Note 1)
-0.35 +0.35
%
gMV Amplifier Transconductance
1.91 2.06
mS
CURRENT LIMIT
Average Current-Limit Trip-Level
Accuracy VILIM = 1.5V -11
+11
%
ILIM Input Bias Current 1µA
ILIM Default Program Level VILIM > VCC - 0.2V
1.197 1.463
V
ENABLE INPUT (EN)
Turn-On Threshold (Rising) VCC = 4.5V to 5.5V, 100mV typ hysteresis 0.8 0.9 V
LOGIC INPUTS (VID0–VID7)
INTEL (SEL = HIGH OR LOW)
Input Low Level VCC = 4.5V to 5.5V 0.4 V
Input High Level VCC = 4.5V to 5.5V 0.8 V
Input Pulldown Resistance
100 270
kΩ
ELECTRICAL CHARACTERISTICS
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩ= RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 50kΩto GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= -40°C to
+85°C.) (Note 2)
MAX8809A/MAX8810A
_______________________________________________________________________________________ 7
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
AMD (SEL = UNCONNECTED)
Input Low Level VCC = 4.5V to 5.5V 0.6 V
Input High Level VCC = 4.5V to 5.5V 1.4 V
Input Pulldown Resistance
100 270
kΩ
LOGIC INPUT (SEL)
Internal Bias Resistance 50
200
kΩ
Input Low Level VCC = 4.5V to 5.5V 0.5 V
Input High Level VCC = 4.5V to 5.5V VCC -
0.5 V
VRREADY OUTPUT
Output Low Level IVRREADY = +4mA 0.4 V
Output High Leakage VVRREADY = 5.5V 1 µA
VRREADY Blanking Time Fr om E N r i si ng to V RRE AD Y r i si ng , RS S / OV P
= 12kΩ3.0 5.5 ms
(VRS+ - VRS-) rising V
D AC
+
0.150
V
D AC
+
0.200
VRREADY Upper Threshold
(Note 1) (VRS+ - VRS-) falling V
D AC
+
0.075
V
D AC
+
0.125
V
(VRS+ - VRS-) falling VDAC -
0.250
VDAC -
0.200
VRREADY Lower Threshold
(Note 1) (VRS+ - VRS-) rising VDAC -
0.175
VDAC -
0.125
V
OVERVOLTAGE PROTECTION
Intel (SEL = High or Low) (VRS+ - VRS-) rising (Note 1) V
D AC
+
0.150
V
D AC
+
0.200
V
AMD (SEL = Unconnected) (VRS+ - VRS-) rising
1.75 1.80
V
SS/OVP High Level ISS/OVP = 10mA VCC -
0.450
V
OSCILLATOR
Oscillator Frequency Accuracy
(per Phase) Frequency per phase = 300kHz -20
+20
%
Switching Frequency Range
(per Phase)
150 1200
kHz
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩ= RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 50kΩto GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= -40°C to
+85°C.) (Note 2)
MAX8809A/MAX8810A
8 _______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
CURRENT-SENSE AMPLIFIERS
Current-Sense Amplifier Gain (GCA)R
NTC = 10kΩ27 33 V/V
CS_+ Input Bias Current VCS_+ = VCS_- = 2V 4.5 µA
CS_- Input Bias Current VCS_+ = VCS_- = 2V 7 µA
GAIN TEMPERATURE COMPENSATION (NTC)
Tem p er atur e C om p ensati on Accur acy RNTC temperature = 0°C to +125°C
(10k NTC Panasonic ERTJ1VR103)
-7.5 +7.5
%
VRHOT TEMPERATURE MONITORING
VRHOT Output Low Voltage 4mA sink current 0.4 V
VRHOT Output High Leakage Current
VVRHOT = 5.5V 5 µA
VRTSET Temperature Range
+60 +125
°C
VRTSET Accuracy RNTC temperature = +60°C to +125°C (10k NTC
Panasonic ERTJ1VR103) -5 +5 °C
PWM DRIVER
Output Low Level IPWM_ = +5mA 0.4 V
Output High Level IPWM_ = -5mA 4.5 V
PWM Disable Program Threshold 4V < VCC < 5.5V 3 V
GATE-DRIVER SPECIFICATIONS
VL_, BST_ to LX_ Input Voltage Range
4.5 6.5 V
LX_ Operating Range 26 V
VL_ UVLO Threshold (MAX8809A,
VL12; MAX8810A, VL1) VVL_ rising, 250mV hysteresis (typ)
3.25 3.80
V
DH_ = BST_ 1.6
Driver Static Supply Current,
IVL_ (per Channel) DH_ = LX_ 1.8 mA
Boost Static Supply Current,
IBST_ (per Channel) DH_ = BST_ 1 mA
Sourcing current, VVL _ = 6.5V 2.0
DH_ Driver Resistance Sinking current, VVL _ = 6.5V 1.2 Ω
Sourcing current, VVL _ = 6.5V 1.7
DL_ Driver Resistance Sinking current, VVL _ = 6.5V 0.6 Ω
ELECTRICAL CHARACTERISTICS (continued)
(VVL_ = VBST_ = 6.5V, VCC = VEN = 5V, VILIM = 1.5V, VID_ = SEL = REF = BUF = unconnected, VCOMP = VRS+ = 1.0V, RVRREADY =
5kΩpullup to 5V, RSS/OVP = 12kΩ= RNTC = 10kΩto GND, fSW = 300kHz, RVRTSET = 50kΩto GND, VCS_+ = VCS_- = 1V, PWM_ =
unconnected, RVRHOT = 249Ωpullup to 1.05V, VGND = VPGND_ = VLX_ = VRS- = 0V, DL_ = DH_ = unconnected, TA= -40°C to
+85°C.) (Note 2)
Note 1: VDAC refers to the internal voltage set by the VID code.
Note 2: Specifications to -40°C are guaranteed by design and characterization.
Typical Operating Characteristics
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO= 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
_______________________________________________________________________________________ 9
EFFICIENCY vs. LOAD CURRENT
ROSC = 130kΩ
LOAD CURRENT (A)
EFFICIENCY (%)
MAX8809A toc01
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
VIN = 12V
VIN = 20V
VIN = 7V
OUTPUT VOLTAGE vs. LOAD CURRENT
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
MAX8809A toc02
0 20 40 60 80 100 120
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
OUTPUT VOLTAGE
vs. INDUCTOR TEMPERATURE
MAX8809A toc03
INDUCTOR TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
100755025
1.20
1.25
1.30
1.35
1.40
1.15
0125
ILOAD = 50A
ILOAD = 0A
OUTPUT LOAD TRANSIENT
MAX8809A toc04
IOUT
VOUT 50mV/div
60A/div
20μs/div
ACTIVE CURRENT SHARING
vs. LOAD CURRENT
LOAD CURRENT (A)
VDC (mV)
MAX8809A toc05
0 50 100
0
5
10
15
20
25
MEASURED ACROSS
C19, C20, C26, C27
AVERAGE DCR IS 0.86mΩ (+25°C)
DYNAMIC VID RESPONSE
MAX8809A toc06
VRREADY
IOUT
VOUT
VRREADY
500mV/div
60A/div
1V/div
200μs/div
SOFT-START WAVEFORMS (INTEL)
MAX8809A toc07
EN
VOUT
IIN
VRREADY
500mA/div
1V/div
1V/div
1V/div
1ms/div
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO= 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
10 ______________________________________________________________________________________
SOFT-START WAVEFORMS (AMD)
MAX8809A toc08
IIN
VOUT
VEN
VRREADY
500mA/div
1V/div
1V/div
1V/div
1ms/div
SHUTDOWN WAVEFORMS AT NO LOAD
MAX8809A toc09
EN
VOUT
IIN
VRREADY
500mA/div
1V/div
1V/div
1V/div
400μs/div
SHUTDOWN WAVEFORMS AT FULL LOAD
MAX8809A toc10
EN
VOUT
IIN
VRREADY
500mV/div
2V/div
1V/div
5A/div
500μs/div
SHORT-CIRCUIT AND
RECOVERY WAVEFORMS
MAX8809A toc11
VRREADY
IOUT
IIN
VOUT 500mV/div
50A/div
5A/div
2V/div
40μs/div
CURRENT THRESHOLD
vs. INDUCTOR CASE TEMPERATURE
INDUCTOR TEMPERATURE (°C)
RMS CURRENT LIMIT (A)
MAX8809A toc12
908060 7010 20 30 40 500
20
40
60
80
100
120
140
160
ILIM = 155A
ILIM = 100A
180
0
-10 100
REFERENCE VOLTAGE
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX8809A toc13
-40-200 20406080
1.90
1.95
2.00
2.05
2.10
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO= 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
MAX8809A/MAX8810A
______________________________________________________________________________________ 11
BUF VOLTAGE
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
BUF VOLTAGE (V)
MAX8809A toc14
-40-200 20406080
0.90
0.95
1.00
1.05
1.10
PER-PHASE FREQUENCY vs. ROSC
ROSC (kΩ)
PER-PHASE FREQUENCY (kHz)
MAX8809A toc15
0 100 200
100
300
500
700
900
1100
1300
2/4 PHASE
3 PHASE
CLOCK FREQUENCY
vs. TEMPERATURE
TEMPERATURE (°C)
FREQUENCY (kHz)
MAX8809A toc16
-40 -15 10 35 60 85
500
550
600
650
700
750
800
850
900
950
1000
OUTPUT VOLTAGE OFFSET
vs. ROS
MAX8809A toc17
ROS (kΩ)
OUTPUT VOLTAGE (mV)
504030
5
15
10
20
25
30
35
0
20 60
SOFT-START DURATION
vs. RSS/OVP
RSS/OVP (kΩ)
SOFT-START DURATION (ms)
MAX8809A toc18
0 20406080100
0
1
2
3
4
5
6
VRHOT SETPOINT
vs. RVRTSET
RVRTSET (kΩ)
VRHOT SETPOINT (°C)
MAX8809A toc19
0 50 100 150 200 250 300
50
60
70
80
90
100
110
120
130
OUTPUT OVERVOLTAGE
PROTECTION WAVEFORM
MAX8809A toc20
VOUT
SS/OVP
VRREADY
500mV/div
1V/div
5V/div
2μs/div
VL_ POWER DISSIPATION
vs. PER-PHASE SWITCHING FREQUENCY
fS (kHz)
VL_ POWER DISSIPATION (mW)
MAX8809A toc21
0 200 400 600 800 1000
0
200
400
600
800
1000
CDL_ = CDH_ = 3300pF
1200
1400
1600
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO= 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
VL_ POWER DISSIPATION
vs. LOAD CAPACITANCE
DH_/DL_ LOAD CAPACITANCE (pF)
VL_ POWER DISSIPATION (mW)
MAX8809A toc22
1000 2000 3000 4000 5000 6000 7000
0
50
100
150
200
250
300
350
400
DL_ RISE/FALL TIME
vs. LOAD CAPACITANCE
LOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)
MAX8809A toc23
1000 3000 5000 7000
0
5
10
15
20
25
30
DL_ RISE
DL_ FALL
DH_ RISE/FALL TIME
vs. LOAD CAPACITANCE
LOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)
MAX8809A toc24
0 2000 4000 6000 8000
0
5
10
15
20
25
30
DH_ RISE
DH_ FALL
DH_/DL_ RISE/FALL TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
RISE/FALL TIME (ns)
MAX8809A toc25
-40 -20 0 20 40 60 80
0
5
10
15
20
25
DL_ RISE
DH_ RISE
DH_ FALL DL_ FALL
CDH_ = CDL_ = 3300pF
VL_ SUPPLY CURRENT
vs. PER-PHASE SWITCHING FREQENCY
fS (kHz)
VL_ SUPPLY CURRENT (mA)
MAX8809A toc26
0 200 400 600 800 1000
0
50
100
150
200
250
CDH_ = CDL_ = 3300pF
SWITCHING WAVEFORMS
MAX8809A t0c27
DL_
DH_
LX_
10V/div
10V/div
20V/div
200ns/div
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
MAX8809A/MAX8810A
______________________________________________________________________________________ 13
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
BST_ AND VL_ WAVEFORMS
VIN = 8V
MAX8809A toc28
VL_
LX_
BST_
500mV/div
(AC-COUPLED)
200mV/div
(AC-COUPLED)
5V/div
500ns/div
Typical Operating Characteristics (continued)
(Circuit of Figure 14, VIN = 12V, VOUT = 1.35V, IOUT_MAX = 115A, RO= 1mΩ, fSW = 200kHz, VCC = 5V, VVL_ = 6.5V, TA= +25°C,
unless otherwise noted.)
DH_ FALLING PROPAGATION DELAY
vs. TEMPERATURE
AMBIENT TEMPERATURE (°C)
PROPAGATION DELAY (ns)
MAX8809A toc29
-40-200 20406080
20
25
30
35
40
45
50
Pin Description
PIN
MAX8809A
MAX8810A
NAME FUNCTION
148
VRREADY
O p en- D r ai n, P ow er - O kay Ind i cator . V RRE AD Y i s an op en- d r ai n outp ut that g oes hi g h
i m p ed ance w hen the outp ut i s i n r eg ul ati on. V RRE AD Y p ul l s l ow w hen the outp ut i s out of
r eg ul ati on, the IC i s i n shutd ow n, or V
C C
i s b el ow the U V LO thr eshol d .
2 1 ILIM
Current-Limit Set Input. Connect to the center tap of an external resistor-divider from REF
to GND to set the cycle-by-cycle average current-limit threshold. Connect ILIM to VCC to
select the default current-limit threshold.
3 2 REF
Inter nal Refer ence O utp ut. RE F r eg ul ates to 2V . Byp ass RE F to G N D w i th a 0.1µF to 1µF
cer am i c cap aci tor . D o not use a cap aci tor g r eater than 1µF. RE F sour ces up to 500µA for
exter nal l oad s. RE F i s enab l ed w hen V
C C
i s ab ove U V LO r eg ar d l ess of the state of E N .
4 3 COMP
Error-Amplifier Output. Connect COMP to the compensation network to implement either
voltage positioning or integral feedback-control. Connect a resistor from COMP to GND
to set the offset voltage. See the Loop-Compensation Design section for details on
determining the compensation network.
5 5 GND Analog Ground. Connect GND to the analog ground plane.
66V
CC IC Supply Input. Connect VCC to a 4.5V to 5.5V power supply. Bypass VCC to GND with
a 1µF or larger ceramic capacitor.
7 8 RS-
Output-Voltage Remote-Sense Negative Input. Connect RS- to the VSS_SEN remote-
sense point at the load when using the remote sense. Otherwise, connect RS- to GND at
the load.
8 9 RS+
Output-Voltage Remote-Sense Positive Input. Connect RS+ to the VCC_SEN remote-
sense point at the load when using remote sense. Otherwise, connect RS+ to the output
at the load.
MAX8809A/MAX8810A
14 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809A
MAX8810A
NAME FUNCTION
9 11 OSC
Internal Clock Oscillator Frequency Set Input. Connect a resistor from OSC to GND to set
the internal oscillator frequency. See the Setting the Switching Frequency section for
determining the resistor value.
10 12
SS/OVP
S oft- S tar t P r og r am Inp ut and Over vol tag e- P r otecti on Faul t Fl ag . C onnect a r esi stor fr om
S S /OV P to GN D to set the soft- star t p er i od . S S /O V P p ul l s to V
C C
d ur i ng an O V P event to
si g nal the faul t cond i ti on. S ee the S oft- S tar t secti on for d eter m i ni ng the r esi stor val ue.
11 13
VRTSET
Temperature Comparator Program Input. Connect a resistor from VRTSET to GND to set
the VRHOT temperature threshold. Connect VRTSET to VCC to disable the VRHOT
monitoring feature. See the Temperature Monitoring (VRTSET, VRHOT) section for
resistor selection.
12 14 NTC
Temperature-Sensing Input. Connect a 10kΩ NTC thermistor between NTC and GND for
load-line independent temperature compensation. Connect NTC to VCC to disable the
temperature compensation and VRHOT monitoring features. See the Temperature
Monitoring (VRTSET, VRHOT) section for more details on selection of the NTC device.
13 — CS3- Phase 3 Current-Sense Negative Input. Connect to the load side of the output current-
sensing element.
14 17 CS3+
Phase 3 Current-Sense Positive Input. Connect CS3+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
15 18 CS2+
Phase 2 Current-Sense Positive Input. Connect CS2+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
16 19 CS12- Phases 1 and 2 Current-Sense Common Negative Input. Connect to the load side of the
output current-sensing elements.
17 20 CS1+
Phase 1 Current-Sense Positive Input. Connect CS1+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
18 21 EN
Enable Input. Drive EN high to enable the IC. Drive EN low to place the IC in shutdown
mode. If VCC is greater than the UVLO threshold, EN is internally pulled to VCC with a
100kΩ resistor. If VCC is less than the UVLO threshold, EN is internally pulled to GND
with a 2kΩ resistor.
19 23 PWM3 PWM Signal Output for phase 3. PWM3 is low during shutdown, UVLO, and OVP faults.
Connect PWM3 to VCC to enable 2-phase operation.
20 24
VRHOT
Temperature Fault Flag. VRHOT is an active-high, open-drain output that goes high
impedance when the temperature sensed by the thermistor at NTC exceeds the
temperature threshold programmed at VRTSET.
21 25 DH1 Phase 1 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for phase 1. DH1 is pulled low during shutdown, UVLO, and OVP faults.
22 26 LX1 Phase 1 Inductor Sense Point. Connect LX1 to the switched side of the inductor for
phase 1.
MAX8809A/MAX8810A
______________________________________________________________________________________ 15
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809A
MAX8810A
NAME FUNCTION
23 27 BST1
P hase 1 H i g h- S i d e M O S FE T Gate- D r i ve S up p l y. C onnect a 0.22µF or l ar g er cer am i c
cap aci tor fr om BS T1 to LX 1 to sup p l y g ate d r i ve for the hi g h- si d e M O S FE T. S ee the Boost
C ap aci tor S el ecti on secti on for d etai l s on cal cul ati ng the BS T1 cap aci tor val ue.
24 28 DL1
P hase 1 Low - S i d e M OS FE T Gate- D r i ve Outp ut. C onnect to the g ate of the l ow - si d e M O S FE T
for p hase 1. D L1 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an OV P
faul t. D L1 i s hi g h i n shutd ow n i f V
C C
i s g r eater than the U V LO thr eshol d .
25 29 PGND1
Power Ground for the Phase 1 Driver. Connect PGND1 to the source of the phase 1
low-side MOSFET. PGND1 must be connected to PGND2 and GND externally. See the
PC Board Layout Guidelines section for more details.
26 — VL12
Phase 1 and 2 Low-Side MOSFET Gate-Drive Supply. Connect VL12 to a 4.5V to 6.5V
supply. Bypass VL12 with a 2.2µF or larger ceramic capacitor to the power ground
plane.
27 32 PGND2
Power Ground for the Phase 2 Driver. Connect PGND2 to the source of the phase 2
low-side MOSFET. PGND2 must be connected to PGND1 and GND externally. See the
PC Board Layout Guidelines section for more details.
28 33 DL2
P hase 2 Low - S i d e M OS FE T Gate- D r i ve Outp ut. C onnect to the g ate of the l ow - si d e M OS FE T
for p hase 2. D L2 i s p ul l ed l ow d ur i ng und er vol tag e l ockout and p ul l ed hi g h d ur i ng an OV P
faul t. D L2 i s hi g h i n shutd ow n i f V
C C
i s g r eater than the U V LO thr eshol d .
29 34 BST2
P hase 2 H i g h- S i d e M O S FE T Gate- D r i ve S up p l y. C onnect a 0.22µF or l ar g er cer am i c
cap aci tor fr om BS T2 to LX 2 to sup p l y g ate d r i ve for the hi g h- si d e M O S FE T. S ee the Boost
C ap aci tor S el ecti on secti on for d etai l s on cal cul ati ng the BS T2 cap aci tor val ue.
30 35 LX2 Phase 2 Inductor Sense Point. Connect LX2 to the switched side of the inductor for
phase 2.
31 36 DH2 Phase 2 High-Side MOSFET Gate-Drive Output. Connect to the gate of the high-side
MOSFET for Phase 2. DH2 is pulled low during shutdown, UVLO, and OVP faults.
32 38 SEL
VID Table Selection Input. Connect SEL to GND to select the VRD10 VID code
(Table 5). Connect SEL to VCC to select the VRD11 8-bit VID code (Table 6). Leave SEL
unconnected to select the K8 Rev F VID code (Table 4).
33–40 39–46
VID7–VID0
Voltage Identification Code Inputs. Use VID_ to set the output voltage. SEL selects the
VRD10, VRD11, or K8 Rev F VID logic codes. Connect VID_ to the system VTT with a
680Ω resistor for logic-high for Intel VR solutions. Connect VID_ to the system VDDQ
with a 1kΩ resistor for logic-high for AMD VR solutions.
MAX8809A/MAX8810A
16 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Pin Description (continued)
PIN
MAX8809A
MAX8810A
NAME FUNCTION
— 4 BUF
1V Reference Output. Bypass BUF to GND with a 1µF or larger ceramic capacitor.
Connect a resistor from COMP to BUF to set the load-line. See the Loop-Compensation
Design section for more details.
—
7, 10, 37, 47
N.C. No Internal Connection
— 15 CS4+
Phase 4 Current-Sense Positive Input. Connect CS4+ to the positive side of the output
current-sense resistor, or the positive side of the filtering capacitor if inductor DCR
current sensing is used.
— 16 CS34- Phases 3 and 4 Current-Sense Common Negative Input. Connect to the load side of
the output current-sensing elements.
— 22 PWM4
PWM Signal Output for Phase 4. PWM4 is low during shutdown, UVLO, and OVP faults.
Connect PWM4 to VCC to enable 3-phase operation. Connect PWM3 and PWM4 to VCC
to enable 2-phase operation.
— 30 VL1
Phase 1 Low-Side MOSFET Gate-Drive Supply. Connect VL1 to a 4.5V to 6.5V supply.
VL1 must be connected to VL2 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.
— 31 VL2
Phase 2 Low-Side MOSFET Gate-Drive Supply. Connect VL2 to a 4.5V to 6.5V supply.
VL2 must be connected to VL1 externally. Bypass the VL1/VL2 connection with a 2.2µF
or larger ceramic capacitor to the power ground plane.
——EP
Exposed Paddle. Connect to the analog GND plane for enhanced thermal power
dissipation.
MAX8809A/MAX8810A
______________________________________________________________________________________ 17
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VL1
EN
VCC
MAX8809A
MAX8810A
1V
REF
gMB
TEMPERATURE
COMPENSATION
TEMPERATURE
COMPENSATION
NTC
THERMISTOR
LINEARIZATION
CIRCUIT
MAX8810A ONLY
OVP
COMPARATOR
S/R
S/R
S/R PWM3
BST1
DH1
LX1
DL1
PGND1
VL1
(MAX8810A)
VL12
(MAX8809A)
(MAX8809A)
BST2
DH2
LX2
DL2
PGND2
VL2
(MAX8810A)
PWM1
PWM2
VDAC
DHOUT
LX
SENSE
DLOUT
DL
SENSE
DHOUT
LX
SENSE
DLOUT
DL
SENSE
PWM4
(MAX8810A)
S/R
2-/3-/4-
PHASE
CONTROL
OSC
POWER-GOOD
CIRCUITRY
SOFT-START
SOFT-STOP
VID
DECODE
LOGIC
DRIVER
CONTROL
LOGIC
2V
REFERENCE
OVP
THRESHOLD
UVLO
BIAS
CLAMP
VRHOT NTCVRTSET
REF / 2
RSDA
CURRENT
FOLDBACK
+
-
CS1+
CS2+
CS3-
(MAX8809A)
CS3+
CS34-
(MAX8810A)
CS4+
(MAX8810A)
BUF
(MAX8810A)
COMP
SS/OVP
REF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
SEL
RS+
RS-
ILIM
VRREADY
CS12-
OSCILLATOR OPERATION
MODE DETECT
gMV
+
Figure 1. Block Diagram
MAX8809A/MAX8810A
18 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
trDL
tpDLr
tfDL
tDEAD
trDH tfDH
DL
LX
DH
Figure 2. Driver Timing Diagram
Detailed Description
The MAX8809A/MAX8810A synchronous, 2-/3-/4-
phase, step-down, current-mode controllers with inte-
grated dual-phase MOSFET drivers provide flexible
solutions that fully comply with Intel VRD11/VRD10 and
AMD K8 Rev F CPU core supplies. The flexible design
supplies load currents of up to 150A for low-voltage
CPU core power supplies.
The MAX8809A is suitable for 2- or 3-phase core sup-
ply applications. With an integrated dual-MOSFET dri-
ver, the MAX8809A offers a single-chip IC solution for
dual-phase core supplies. Together with the MAX8552,
a high-performance single-phase MOSFET driver, the
MAX8809A also supports 3-phase core supplies.
Similarly, the MAX8810A features a single IC solution
for dual-phase core supplies. It also features two-IC
solutions for 3- or 4-phase core supplies by adding a
single MOSFET driver (MAX8552) or a dual-MOSFET
driver (MAX8523).
Both the MAX8809A and MAX8810A fully comply with
Intel VRD11, Extended VRD10, and the AMD K8 Rev F
VID codes. The SEL input allows the user to select the
architecture specifications.
Clock Frequency (OSC)
An external resistor, ROSC, from OSC to GND sets the
internal clock frequency of the MAX8809A/MAX8810A.
A 1% resistor is recommended to maintain good fre-
quency accuracy. The internal clock frequency sets the
per-phase switching frequency. The selection of switch-
ing frequency per phase is influenced by factors such
as the switching speed of the MOSFETs, the inductor’s
core material, different types of input and output capac-
itors, and the available board space. Once the per-
phase switching frequency is selected, the internal
clock frequency is determined using the procedure in
the Setting the Switching Frequency section.
MAX8809A/MAX8810A
______________________________________________________________________________________ 19
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Voltage Reference (REF)
A precision 2V reference is provided by the MAX8809A/
MAX8810A at the REF output. REF is capable of sinking
and sourcing up to 500µA for external loads. Connect a
0.1µF to 1µF ceramic capacitor from REF to GND.
Internal REFOK circuitry monitors the reference voltage.
The reference voltage must be above the REFOK thresh-
old of 1.84V to activate the controller. The controller is
disabled if the reference voltage falls below 1.74V.
Output Current Sensing (CS_+, CS_-)
The output current of each phase is sensed differentially.
A low-offset-voltage, differential-current amplifier
(30V/V) at each phase allows low-resistance current-
sense resistors to be used to minimize power dissipa-
tion. Sensing the current at the output of each phase
offers advantages including less noise sensitivity, more
accurate current sharing between phases, and the flex-
ibility of using either a current-sense resistor or the DC
resistance of the output inductor.
Using the DC resistance, RDC, of the output inductor
(Figure 3) allows higher efficiency. In this configuration,
the initial tolerance and temperature coefficient of RDC
must be accounted for in the output-voltage droop-error
budget. The temperature coefficient can be compensat-
ed; see the Load-Line Independent Inductor DC
Resistance Temperature Compensation section for more
details. An RC-filtering network is needed to extract the
current information from the output inductor. The time
constant of the RC network is calculated as follows:
where L is the inductance of the output inductor. For
20A or higher current-per-phase applications, the DC
resistance of commercially available inductors is
approximately 1mΩ. To minimize current-sense error
due to the bias current at the current-sense inputs,
choose R1 less than 2kΩ. Determine the value for C1 as:
Select a 1% resistor for R1. For mainstream PCs 20%
tolerance is recommended for C1, and for performance
PCs 10% tolerance should be considered. If using an
inductor with RDC greater than 1mΩ, a resistor (R2)
may be necessary to divide down the voltage across
CS_+ and CS_-. The maximum average signal present
at the input of the current-sense amplifier should not
exceed 85mV.
When a current-sense resistor is used for more accu-
rate current sharing and load-line, a similar RC-filtering
circuit is recommended to cancel the equivalent series
inductance of the current-sense resistor, as shown in
Figure 4. Again, select R2 less than 2kΩ, and C2 is
determined by the following equation:
where ESL is the equivalent series inductance of the
current-sense resistor and RSis the value of the cur-
rent-sense resistor. For example, a 1mΩ, 2025 pack-
age sense resistor has an ESL of 1.6nH. If using an RS
greater than 1mΩ, a resistor (R2) may be necessary to
divide down the voltage across CS_+ and CS_-. The
maximum average signal present at the input of the
current-sense amplifier should not exceed 85mV.
Output Current Limit and Short-Circuit
Protection (ILIM)
The MAX8809A/MAX8810A feature a precise average
output current limit on a cycle-by-cycle basis using
Maxim’s proprietary RA2technology. The current-limit
scheme is insensitive to input-voltage variation, the
inductor tolerance, and the tolerance of the current-
sense capacitor, permitting the use of low-cost compo-
nents to reduce total BOM cost. Furthermore, the
current limit is fully temperature compensated resulting
CESL
RR
S
22
=×
()
CL
RR
DC
11
=×
()
RC L
RDC
11 ×=
RDC IOUT
R1
R2
OPTIONAL
VRDC = RDC x IOUT
RDC IS THE INDUCTOR DC RESISTANCE
L
C1
CS_+ CS_-
Figure 3. Inductor RDC Current Sense
RSIOUT
R2 VS = RS x IOUT
ESL IS THE PARASITIC INDUCTANCE OF THE CURRENT-SENSE RESISTOR
ESLL
C2
CS_+ CS_-
R2
OPTIONAL
Figure 4. Resistor Current Sense
MAX8809A/MAX8810A
20 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
in a constant output current limit over the entire opera-
tional temperature range. This eliminates the need to
oversize MOSFETs and inductors to compensate for
thermal effects. Connecting ILIM to VCC programs the
default current-limit threshold. To select a different cur-
rent-limit threshold, connect a resistor-divider from REF
to GND with ILIM connected to the center tap. The volt-
age at ILIM is proportional to the current-limit threshold.
See the Setting the Current-Limit section for more details.
The current-limit circuitry terminates the DH_ on-time
immediately when the current-sense voltage (VCS_+ -
VCS_-) exceeds the current-limit threshold, allowing the
output inductor current to ramp down. At the next
switching cycle, the PWM pulse is skipped if the output
inductor current is still above the current-limit threshold.
Otherwise, the new cycle initiates as normal.
The MAX8809A/MAX8810A offer foldback-current pro-
tection under soft-start and overload conditions. This
feature allows the VRM to safely operate under short-
circuit conditions and to automatically recover once the
short-circuit condition is removed. If the output voltage
falls below the VRREADY threshold during an overcur-
rent event, the foldback current-limit circuitry sets the
current-limit threshold to half the user-selected value.
Output Differential Sensing (RS+, RS-)
The MAX8809A/MAX8810A feature differential output-
voltage sensing to achieve the highest possible output
accuracy. This allows the controllers to sense the actu-
al voltage at the load, so the controller can compensate
for losses in the power output and ground lines. Traces
from the load point back to RS+ and RS- should be
routed close to each other and as far away as possible
from noise sources (such as inductors and high di/dt
traces). Use a ground plane to shield the remote-sense
traces from noise sources. To filter out common-mode
noise, RC filtering is recommended for these inputs as
shown in Figure 5. For VRD applications, a 100Ωresis-
tor with a 1nF capacitor should be used. For VRM
applications, additional 50Ωresistors should be con-
nected from these inputs to the local outputs of the
converter before the VRM connector. This avoids
excessive voltage at the CPU in case the remote-sense
connections get disconnected.
Programming the Output-Voltage Droop
Both the MAX8809A and MAX8810A employ peak-cur-
rent-mode control with finite gain to actively set the out-
put-voltage droop. Figure 6 shows the simplified control
block diagram. The relationship between the output
inductor current in an N-phase DC-DC converter and
the output voltage of the voltage-error amplifier is:
where GCA (30V/V typ) is the gain of the differential cur-
rent amplifier and N is the number of phases. IOUT is the
total output current. Therefore, when the output current
increases, VCincreases. On the other hand, VCis relat-
ed to the output voltage of the converter by the following
equation:
where gMV is the transconductance of the voltage-error
amplifier (2mS typ) and VDAC is the VID-generated voltage.
Vg R V V
C MV COMP DAC OUT
=× × −
()
VI
NRG
COUT SENSE CA
=× ×
MAX8809A/
MAX8810A
RS+
R1
50Ω
R2
50Ω
R3
100Ω
R4
100Ω
C2
1nF
C1
1nF
RS-
TO REMOTE SENSE
LOCATION
TO POSITIVE OUTPUT
OF VRM
TO POWER GROUND
OF VRM
Figure 5. Recommended Filtering for Output-Voltage Remote
Sensing
PWM
COMPARATOR
VOLTAGE-
ERROR AMPLIFIER RCOMP
VC
gMV
Vi
VDAC
VOUT
IL_PEAK
GCA
RSENSE
Figure 6. Simplified Peak Current-Mode Control IC with Active
Output-Voltage Positioning
MAX8809A/MAX8810A
______________________________________________________________________________________ 21
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
The DC gain of the voltage-error amplifier is equal to
gMV x RCOMP. From the previous equations it is clear
that the output-voltage droop can be accurately pro-
grammed if the DC gain of the voltage-error amplifier is
set to be a finite value. As the output current increases,
VCincreases and, consequently, VOUT decreases.
Define the output-droop resistance, RDROOP, as:
then RDROOP can be expressed as:
Since GCA and gMV are constants, RDROOP is solely
determined by RCOMP when RSENSE and N are chosen.
Peak current-mode control with finite gain is the sim-
plest way to achieve the output-voltage droop without
introducing a separate current loop, which is the case
for voltage-mode control. Therefore, the response time
of the output-voltage droop is the same as the voltage-
feedback loop, resulting in fast output-voltage-droop
transient response and less output capacitance than
solutions using voltage-mode control.
Other features offered by peak-current-mode control
are excellent line regulation and inherent current shar-
ing between phases. Standard peak-current-mode con-
trol does have one disadvantage in that current
matching between phases is impacted by the inductor
mismatch (tolerance) between phases. Because only
the current peak is controlled, any mismatch in the
inductor value between two phases creates an inductor
ripple current mismatch, which, in turn, creates a DC
current mismatch between those two phases.
Tolerance mismatch between the current-sense capac-
itors used in DCR current sensing creates the exact
same DC current mismatch as an inductor mismatch.
Maxim’s proprietary RA2technology addresses this
issue by averaging out the inductor ripple current indi-
vidually at each phase, as shown in Figure 7. The rapid
active average circuitry learns the peak-to-peak ripple
current of each phase in 5 to 10 switching cycles and
then biases the peak current signal down by half of the
peak-to-peak ripple current, consequently eliminating
the impact of both output inductance and DCR current-
sense capacitance variations. Since the rapid active
average circuitry is not part of the current-loop path, it
does not slow down the transient response.
Programming the Output Offset Voltage
According to the Intel VRD specifications, the output
voltage at no load cannot exceed the voltage specified
by the VID code, including the initial set tolerance, rip-
ple voltage, and other errors. Therefore, the actual out-
put voltage should be biased lower to compensate for
these errors. For the MAX8809A, the output-voltage off-
set is created through a resistor-divider that is connect-
ed between REF and GND, with the center tap
connected to COMP as shown in Figure 8. This resistor-
divider also sets the output load-line. The MAX8810A
contains a BUF output that makes the output-voltage
offset setting independent of the output load-line. To
program the output-voltage offset, connect a resistor
between COMP and GND. A resistor between BUF and
COMP sets the output load-line. See the Loop
Compensation Design section for details on setting the
output-voltage offset.
RRG
Ng R
DROOP SENSE CA
MV COMP
=×
××
RVV
I
DROOP DAC OUT
OUT
=−
()
1/S
PWM
COMPARATOR
VOLTAGE-
ERROR AMPLIFIER RCOMP
VC
VDAC
VOUT
gMA
GCA
RSENSE x (IOUT / N)
RSENSE x (IOUT / N)
RA2 ALGORITHM
VC
gMB
gMV
Figure 7. Implementation of the Rapid Active Averaging (RA2)
Algorithm
MAX8809A/MAX8810A
22 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Load-Line Independent Inductor DC
Resistance Temperature Compensation
Changes in inductor resistance due to temperature
cause a change in the output-droop characteristic. This
is compensated by changing the gain of the current-
sense amplifier as a function of temperature. In doing
so, the voltage at COMP is independent of temperature,
resulting in a temperature-independent load-line setting.
Additionally, the output short-circuit protection is also
temperature independent because current limit is imple-
mented by clamping the voltage at COMP. This technol-
ogy uses an NTC thermistor solely for temperature
compensation, freeing it from being one of the compo-
nents that determines the output load-line. Therefore,
only one NTC thermistor is needed to enable any output
load-line. The same NTC thermistor is used for tempera-
ture sense for the VRHOT output. The MAX8809A/
MAX8810A temperature-compensation scheme is opti-
mized for use with a Panasonic ERTJ1VR103 10kΩNTC
thermistor. Other thermistors may be used. Contact your
local Maxim representative for more details.
Loop Compensation
During a load transient, the output voltage instantly
changes due to the ESR of the output capacitors by an
amount equal to their ESR times the change in load cur-
rent (ΔVOUT = RESR x ΔILOAD). The output voltage then
deviates further based on the speed at which the loop
compensates for the load transient. The voltage-posi-
tioning method allows better utilization of the output reg-
ulation window, resulting in less required output
capacitors. The RA2architecture adjusts the output cur-
rent based on the instantaneous output voltage, result-
ing in fast voltage positioning. The voltage-error
amplifier consists of a high-bandwidth, high-accuracy
transconductance amplifier (gMV in Figure 7). The nega-
tive input of the transconductance amplifier is connected
to the output of the remote-voltage differential amplifier,
and the positive input is connected to the output of an
internal DAC controlled by the VID inputs. The DC gain
of the transconductance amplifier is set to a finite value
to achieve fast output-voltage positioning by connecting
an RC circuit (RCOMP and CCOMP) from COMP to GND.
See the Loop-Compensation Design section for details
on selecting the required components.
VR Ready Output (VRREADY)
VRREADY is an open-drain output that turns high
impedance when the output voltage reaches regula-
tion. VRREADY goes low if VOUT is less than (VDAC -
225mV) or greater than (VDAC + 175mV), signaling an
out-of-regulation fault. VRREADY is held low in shut-
down, if VCC is less than the UVLO threshold, or during
soft-start. For logic-level output voltages, connect an
external pullup resistor between VRREADY and the
logic power supply. A 100kΩresistor works well in most
applications.
Dynamic VID Change
The MAX8809A/MAX8810A provide the ability for the
CPU to dynamically change the VID inputs while the
controller is operating (on-the-fly or OTF). The output
voltage changes in 6.25mV steps (Intel) or
12.5mV/25mV steps (AMD) when a VID change is
detected.
The controller provides a 400ns logic-skew window to
prevent false code changes. The controller accepts
both step-by-step changes of VID inputs or all-at-once
VID input changes. For all-at-once VID input changes,
the output-voltage slew rate is the same, 1 LSB per
step and 2µs duration. VRREADY is blanked during
dynamic VID changes.
Multiphase Operation Selection
The MAX8809A operates in either a 2- or 3-phase config-
uration. Connect PWM3 to VCC for 2-phase operation.
The MAX8810A operates in 2-, 3- or 4-phase configura-
tion. Connect PWM4 to VCC for 3-phase operation.
Connect PWM4 and PWM3 to VCC for 2-phase operation.
All active PWM outputs are held low during shutdown.
UVLO and Output Enable
When the IC supply voltage (VCC) is less than the
UVLO threshold (4.25V typ), all active PWM outputs are
internally pulled low and most internal circuitry is shut
down to reduce the quiescent current. When EN is
released and VCC > UVLO, the internal 100kΩresistor
pulls EN to VCC and soft-start is initiated (after a typical
2.2ms delay).
ROS
RLL
REF
COMP
ROS
RLL
BUF
COMP
MAX8810AMAX8809A
Figure 8. Programming the Output Offset Voltage
MAX8809A/MAX8810A
______________________________________________________________________________________ 23
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
When the driver supply voltage (VVL_) is less than its
UVLO threshold (3.55V typ), DH_ and DL_ are held low.
If VVL_ is above the UVLO threshold and while EN is low,
DL_ is driven high and DH_ is held low. This prevents
the output of the converter from rising before a valid EN
high signal is present.
Soft-Start
The MAX8809A/MAX8810A soft-start with 6.25mV
steps, regardless of processor architecture. Connect a
resistor between SS/OVP and GND to program the soft-
start time. When the device is enabled, SS/OVP is dri-
ven to 2V and the current drawn by the set resistor is
measured. This current sets the internal delay time
between the DAC voltage steps. Select a resistor
between 12kΩand 90.9kΩfor a corresponding soft-
start time of 500µs to 6.5ms. For Intel designs, the
resistor value is calculated as:
where tSS is the desired soft-start time (in ms) to the
1.1V VBOOT level. Figure 9 shows the Intel startup
sequence, and Table 1 shows the values of the time
delays.
For AMD applications, the controllers soft-start up to the
voltage set by the VID inputs. The soft-start time is set
by the following equation:
where VDAC is the output voltage set by the VID inputs.
Figure 10 shows the AMD startup sequence, and Table 2
shows the values of the time delays.
Soft-Stop
When EN goes low, the output of the converter ramps
down to 0V in 6.25mV DAC steps in the time set by the
SS/OVP input. Once the output reaches 0V, DL is held
high and DH is held low to maintain the 0V output. This
Rk
tV
V
SS OVP ss
DAC
/() .
. .
Ω= −×
0 0183
0 0532
11
Rk
t
SS OVP ss
/() .
.
Ω= −0 0183
0 0532
VID
INPUT
READ
(SS TIME)
NO. OF STEPS x 2μs
TD5
TD4TD3TD2
TD1
SOFT-START RATE
SET BY RSS/OVP
SOFT-STOP
RATE SET BY RSS/OVP
VBOOT
6.25mV/STEP 6.25mV/STEP
OUT
VRREADY
EN
VID CODE
CHANGE
STEP TO
VID CODE
6.25mV/2μs
NORMAL
OPERATION
6.25mV/2μs
Figure 9. Intel VRD11/VRD10 Startup Sequence
Table 1. Intel Startup Sequence
Specifications
PARAMETER MIN MAX
TD1 1ms 5ms
TD2 50µs 5ms
TD3 50µs 3ms
TD4 — 2.5ms
TD5 50µs 3ms
approach prevents large negative voltages on the out-
put during shutdown and therefore eliminates the need
for a Schottky clamp diode on the output.
Output Overvoltage Protection (OVP)
When the output voltage exceeds the regulation voltage
by 200mV (Intel) or exceeds 1.8V (AMD), all active PWM
outputs are pulled low and the controller is latched off.
SS/OVP is internally pulled to VCC to signal an overvolt-
age fault. All DH_ outputs are held low and all DL_ out-
puts are held high to discharge the output. The latch
condition can only be cleared by cycling the input volt-
age (VCC).
Integrated Dual-MOSFET Driver
The MAX8809A/MAX8810A contain a dual-phase gate
driver capable of driving 3000pF capacitive loads with
only 32ns propagation delay and 11ns typical rise and fall
times, allowing operation up to 1.2MHz per phase.
Adaptive dead time controls low-side MOSFET turn-on
and high-side MOSFET turn-on. This maximizes converter
efficiency, while allowing operation with a variety of
MOSFETs. A UVLO circuit ensures proper power-on
sequencing.
Adaptive Shoot-Through Protection
Adaptive shoot-through protection is incorporated for
the switching transition after the high-side MOSFET is
turned off and before the low-side MOSFET is turned
on. The low-side driver is turned on only when the LX_
voltage falls below 2.5V typical. In addition, a fixed
35ns delay time between the low-side MOSFET turn-off
and high-side MOSFET turn-on adds further protection
from “shoot-through.” The 35ns time begins after DL_
has fallen through 1.5V typical.
MOSFET Driver UVLO
When VVL12 (MAX8809A) or VVL1 (MAX8810A) is below
the UVLO threshold (3.55 typ), DH_ and DL_ are held
MAX8809A/MAX8810A
24 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
SS TIME
TD2 TD3TD1
2ms TD4
1.1ms
SOFT-START RATE
SET BY RSS/OVP ABOVE 0.775V
25mV/4μs
SOFT-STOP
RATE SET BY RSS/OVP
VID CODE
LEVEL
6.25mV/STEP
6.25mV/STEP
BELOW 0.775V
12.5mV/2μs
OUT
VRREADY
EN
VID INPUT
CHANGE
Figure 10. K8 Rev F Startup Sequencing and Timing
Table 2. AMD Startup Sequence
Specifications
PARAMETER M IN IM U M T IM E
( µ s )
M A XIM U M T IM E
( m s )
TD1 1 —
TD2* 500 6.5
TD3 — 20
TD4 — 500
*User programmable.
MAX8809A/MAX8810A
______________________________________________________________________________________ 25
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
low. Once VVL_ is above the UVLO threshold and EN is
low, DL_ is kept high and DH_ is kept low. This pre-
vents the output from rising before a valid EN signal
is given.
Boost Circuit for High-Side MOSFET Driver
The gate-drive voltage for the high-side MOSFET dri-
vers is generated by a flying-capacitor boost circuit.
The capacitor between BST_ and LX_ is charged from
the VL_ supply through an internal switch while the low-
side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage on the capacitor is
stacked above LX_ to provide the necessary turn-on
voltage for the high-side MOSFET(s). No external boost
diode is needed. See the Boost Capacitor Selection
section for details on selecting the correct capacitor.
Thermal Protection
The MAX8809A/MAX8810A feature a thermal-fault-pro-
tection circuit. When the junction temperature rises
above +160°C typical, an internal thermal sensor acti-
vates the shutdown circuit to hold all MOSFET drivers
and active PWM outputs low to disable switching. The
thermal sensor reactivates the controller after the junc-
tion temperature cools by 25°C typical.
Temperature Monitoring (VRTSET, VRHOT)
The MAX8809A/MAX8810A contain temperature-moni-
toring circuitry that allows the user to program a tem-
perature trip point between +60°C and +125°C, and
monitor an active-high, open-drain VRHOT output.
Connect a resistor from VRTSET to GND to set the tem-
perature-monitoring threshold. The resistor is calculat-
ed as follows:
where KTis a temperature scale factor specifically for
the Panasonic ERTJ1VR103 NTC thermistor. Table 3
provides values of KTand the closest standard 1%
RVRTSET values needed to program the VRHOT thresh-
old over a +60°C to +125°C range. RVRTSET must be
greater than 20kΩ. Contact your local Maxim represen-
tative for information on using other thermistors.
Architecture Selection and Timing
AMD K8 Rev F
The AMD K8 Rev F processor uses a 6-bit VID code
that specifies a 0.375V to 1.55V output voltage range
(see Table 4). Leave SEL unconnected to select the
AMD K8 Rev F architecture. The startup sequencing
and timing specifications are shown in Figure 10. Note
that the VID input defines the AMD processor boot
level, and there is no internal default. The boot level is
not latched; therefore, if the codes change during soft-
start, the boot level also changes.
Extended Intel VRD10
The Intel VRD10 processor uses a 7-bit VID code that
specifies a 0.83125V to 1.6V output voltage range (see
Table 5). Connect SEL to GND to select the VRD10
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
Intel VRD11
The Intel VRD11 processor uses an 8-bit VID code that
specifies a 0.3125V to 1.6V output voltage range (see
Table 6). Connect SEL to VCC to select the VRD11
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
RKin k
VRTSET T
. =800
06 Ω
Table 3. Temperature Scale Factor
TEMPERATURE (°C)
KT
RVRTSET (kΩ)
+60 4.497 294
+65 5.453 243
+70 6.580 200
+75 7.903 169
+80 9.447 140
+85 11.244 118
+90 13.325 100
+95 15.725 84.5
+100 18.484 71.5
+105 21.643 61.9
+110 25.247 52.3
+115 29.345 45.3
+120 33.988 39.2
+125 39.231 34
MAX8809A/MAX8810A
26 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 4. AMD K8 Rev F VID Code, SEL = UNCONNECTED
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
111111
0.3750
111110
0.3875
111101
0.4000
111100
0.4125
111011
0.4250
111010
0.4375
111001
0.4500
111000
0.4625
110111
0.4750
110110
0.4875
110101
0.5000
110100
0.5125
110011
0.5250
110010
0.5375
110001
0.5500
110000
0.5625
101111
0.5750
101110
0.5875
101101
0.6000
101100
0.6125
101011
0.6250
101010
0.6375
101001
0.6500
101000
0.6625
100111
0.6750
100110
0.6875
100101
0.7000
100100
0.7125
100011
0.7250
100010
0.7375
100001
0.7500
100000
0.7625
VID5 VID4 VID3 VID2 VID1 VID0 VOUT (V)
0 1 1 1 1 1 0.7750
0 1 1 1 1 0 0.8000
0 1 1 1 0 1 0.8250
0 1 1 1 0 0 0.8500
0 1 1 0 1 1 0.8750
0 1 1 0 1 0 0.9000
0 1 1 0 0 1 0.9250
0 1 1 0 0 0 0.9500
0 1 0 1 1 1 0.9750
0 1 0 1 1 0 1.0000
0 1 0 1 0 1 1.0250
0 1 0 1 0 0 1.0500
0 1 0 0 1 1 1.0750
0 1 0 0 1 0 1.1000
0 1 0 0 0 1 1.1250
0 1 0 0 0 0 1.1500
0 0 1 1 1 1 1.1750
0 0 1 1 1 0 1.2000
0 0 1 1 0 1 1.2250
0 0 1 1 0 0 1.2500
0 0 1 0 1 1 1.2750
0 0 1 0 1 0 1.3000
0 0 1 0 0 1 1.3250
0 0 1 0 0 0 1.3500
0 0 0 1 1 1 1.3750
0 0 0 1 1 0 1.4000
0 0 0 1 0 1 1.4250
0 0 0 1 0 0 1.4500
0 0 0 0 1 1 1.4750
0 0 0 0 1 0 1.5000
0 0 0 0 0 1 1.5250
0 0 0 0 0 0 1.5500
Note: VID voltage increment is 12.5mV from 0.3875 to 0.775 and 25mV from 0.775 to 1.550.
MAX8809A/MAX8810A
______________________________________________________________________________________ 27
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 5. Extended Intel VRD10 VID Code, SEL = GND
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1101010
1.60000
0101010
1.59375
1001011
1.58750
0001011
1.58125
1101011
1.57500
0101011
1.56875
1001100
1.56250
0001100
1.55625
1101100
1.55000
0101100
1.54375
1001101
1.53750
0001101
1.53125
1101101
1.52500
0101101
1.51875
1001110
1.51250
0001110
1.50625
1101110
1.50000
0101110
1.49375
1001111
1.48750
0001111
1.48125
1101111
1.47500
0101111
1.46875
1010000
1.46250
0010000
1.45625
1110000
1.45000
0110000
1.44375
1010001
1.43750
0010001
1.43125
1110001
1.42500
0110001
1.41875
1010010
1.41250
0010010
1.40625
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOUT (V)
11100101.40000
01100101.39375
10100111.38750
00100111.38125
11100111.37500
01100111.36875
10101001.36250
00101001.35625
11101001.35000
01101001.34375
10101011.33750
00101011.33125
11101011.32500
01101011.31875
10101101.31250
00101101.30625
11101101.30000
01101101.29375
10101111.28750
00101111.28125
11101111.27500
01101111.26875
10110001.26250
00110001.25625
11110001.25000
01110001.24375
10110011.23750
00110011.23125
11110011.22500
01110011.21875
10110101.21250
00110101.20625
MAX8809A/MAX8810A
28 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT (V)
1111010
1.20000
0111010
1.19375
1011011
1.18750
0011011
1.18125
1111011
1.17500
0111011
1.16875
1011100
1.16250
0011100
1.15625
1111100
1.15000
0111100
1.14375
1011101
1.13750
0011101
1.13125
1111101
1.12500
0111101
1.11875
1011110
1.11250
0011110
1.10625
1111110
1.10000
0111110
1.09375
1011111 OFF
0011111 OFF
1111111 OFF
0111111 OFF
1000000
1.08750
0000000
1.08125
1100000
1.07500
0100000
1.06875
1000001
1.06250
0000001
1.05625
1100001
1.05000
0100001
1.04375
1000010
1.03750
0000010
1.03125
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOUT (V)
11000101.02500
01000101.01875
10000111.01250
00000111.00625
11000111.00000
01000110.99375
10001000.98750
00001000.98125
11001000.97500
01001000.96875
10001010.96250
00001010.95625
11001010.95000
01001010.94375
10001100.93750
00001100.93125
11001100.92500
01001100.91875
10001110.91250
00001110.90625
11001110.90000
01001110.89375
10010000.88750
00010000.88125
11010000.87500
01010000.86875
10010010.86250
00010010.85625
11010010.85000
01010010.84375
10010100.83750
00010100.83125
Table 5. Extended Intel VRD10 VID Code, SEL = GND (continued)
MAX8809A/MAX8810A
______________________________________________________________________________________ 29
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOUT (V)
00000000OFF
00000001OFF
0 0 0 0 0 0 1 0 1.60000
0 0 0 0 0 0 1 1 1.59375
0 0 0 0 0 1 0 0 1.58750
0 0 0 0 0 1 0 1 1.58125
0 0 0 0 0 1 1 0 1.57500
0 0 0 0 0 1 1 1 1.56875
0 0 0 0 1 0 0 0 1.56250
0 0 0 0 1 0 0 1 1.55625
0 0 0 0 1 0 1 0 1.55000
0 0 0 0 1 0 1 1 1.54375
0 0 0 0 1 1 0 0 1.53750
0 0 0 0 1 1 0 1 1.53125
0 0 0 0 1 1 1 0 1.52500
0 0 0 0 1 1 1 1 1.51875
0 0 0 1 0 0 0 0 1.51250
0 0 0 1 0 0 0 1 1.50625
0 0 0 1 0 0 1 0 1.50000
0 0 0 1 0 0 1 1 1.49375
0 0 0 1 0 1 0 0 1.48750
0 0 0 1 0 1 0 1 1.48125
0 0 0 1 0 1 1 0 1.47500
0 0 0 1 0 1 1 1 1.46875
0 0 0 1 1 0 0 0 1.46250
0 0 0 1 1 0 0 1 1.45625
0 0 0 1 1 0 1 0 1.45000
0 0 0 1 1 0 1 1 1.44375
0 0 0 1 1 1 0 0 1.43750
0 0 0 1 1 1 0 1 1.43125
0 0 0 1 1 1 1 0 1.42500
0 0 0 1 1 1 1 1 1.41875
0 0 1 0 0 0 0 0 1.41250
0 0 1 0 0 0 0 1 1.40625
0 0 1 0 0 0 1 0 1.40000
0 0 1 0 0 0 1 1 1.39375
0 0 1 0 0 1 0 0 1.38750
0 0 1 0 0 1 0 1 1.38125
0 0 1 0 0 1 1 0 1.37500
0 0 1 0 0 1 1 1 1.36875
MAX8809A/MAX8810A
30 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOUT (V)
0 0 1 0 1 0 0 0 1.36250
0 0 1 0 1 0 0 1 1.35625
0 0 1 0 1 0 1 0 1.35000
0 0 1 0 1 0 1 1 1.34375
0 0 1 0 1 1 0 0 1.33750
0 0 1 0 1 1 0 1 1.33125
0 0 1 0 1 1 1 0 1.32500
0 0 1 0 1 1 1 1 1.31875
0 0 1 1 0 0 0 0 1.31250
0 0 1 1 0 0 0 1 1.30625
0 0 1 1 0 0 1 0 1.30000
0 0 1 1 0 0 1 1 1.29375
0 0 1 1 0 1 0 0 1.28750
0 0 1 1 0 1 0 1 1.28125
0 0 1 1 0 1 1 0 1.27500
0 0 1 1 0 1 1 1 1.26875
0 0 1 1 1 0 0 0 1.26250
0 0 1 1 1 0 0 1 1.25625
0 0 1 1 1 0 1 0 1.25000
0 0 1 1 1 0 1 1 1.24375
0 0 1 1 1 1 0 0 1.23750
0 0 1 1 1 1 0 1 1.23125
0 0 1 1 1 1 1 0 1.22500
0 0 1 1 1 1 1 1 1.21875
0 1 0 0 0 0 0 0 1.21250
0 1 0 0 0 0 0 1 1.20625
0 1 0 0 0 0 1 0 1.20000
0 1 0 0 0 0 1 1 1.19375
0 1 0 0 0 1 0 0 1.18750
0 1 0 0 0 1 0 1 1.18125
0 1 0 0 0 1 1 0 1.17500
0 1 0 0 0 1 1 1 1.16875
0 1 0 0 1 0 0 0 1.16250
0 1 0 0 1 0 0 1 1.15625
0 1 0 0 1 0 1 0 1.15000
0 1 0 0 1 0 1 1 1.14375
0 1 0 0 1 1 0 0 1.13750
0 1 0 0 1 1 0 1 1.13125
0 1 0 0 1 1 1 0 1.12500
0 1 0 0 1 1 1 1 1.11875
MAX8809A/MAX8810A
______________________________________________________________________________________ 31
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOUT (V)
0 1 0 1 0 0 0 0 1.11250
0 1 0 1 0 0 0 1 1.10625
0 1 0 1 0 0 1 0 1.10000
0 1 0 1 0 0 1 1 1.09375
0 1 0 1 0 1 0 0 1.08750
0 1 0 1 0 1 0 1 1.08125
0 1 0 1 0 1 1 0 1.07500
0 1 0 1 0 1 1 1 1.06875
0 1 0 1 1 0 0 0 1.06250
0 1 0 1 1 0 0 1 1.05625
0 1 0 1 1 0 1 0 1.05000
0 1 0 1 1 0 1 1 1.04375
0 1 0 1 1 1 0 0 1.03750
0 1 0 1 1 1 0 1 1.03125
0 1 0 1 1 1 1 0 1.02500
0 1 0 1 1 1 1 1 1.01875
0 1 1 0 0 0 0 0 1.01250
0 1 1 0 0 0 0 1 1.00625
0 1 1 0 0 0 1 0 1.00000
0 1 1 0 0 0 1 1 0.99375
0 1 1 0 0 1 0 0 0.98750
0 1 1 0 0 1 0 1 0.98125
0 1 1 0 0 1 1 0 0.97500
0 1 1 0 0 1 1 1 0.96875
0 1 1 0 1 0 0 0 0.96250
0 1 1 0 1 0 0 1 0.95625
0 1 1 0 1 0 1 0 0.95000
0 1 1 0 1 0 1 1 0.94375
0 1 1 0 1 1 0 0 0.93750
011011010.93125
011011100.92500
011011110.91875
011100000.91250
011100010.90625
011100100.90000
011100110.89375
011101000.88750
011101010.88125
011101100.87500
011101110.86875
MAX8809A/MAX8810A
32 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOUT (V)
011110000.86250
011110010.85625
011110100.85000
011110110.84375
011111000.83750
011111010.83125
011111100.82500
011111110.81875
100000000.81250
100000010.80625
100000100.80000
100000110.79375
100001000.78750
100001010.78125
100001100.77500
100001110.76875
100010000.76250
100010010.75625
100010100.75000
100010110.74375
100011000.73750
100011010.73125
100011100.72500
100011110.71875
100100000.71250
100100010.70625
100100100.70000
100100110.69375
100101000.68750
100101010.68125
100101100.67500
100101110.66875
100110000.66250
100110010.65625
100110100.65000
100110110.64375
100111000.63750
100111010.63125
100111100.62500
100111110.61875
MAX8809A/MAX8810A
______________________________________________________________________________________ 33
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 6. Intel VRD11 VID Code, SEL = VCC (continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOUT (V)
1 0 1 0 0 0 0 0 0.61250
1 0 1 0 0 0 0 1 0.60625
1 0 1 0 0 0 1 0 0.60000
1 0 1 0 0 0 1 1 0.59375
1 0 1 0 0 1 0 0 0.58750
1 0 1 0 0 1 0 1 0.58125
1 0 1 0 0 1 1 0 0.57500
1 0 1 0 0 1 1 1 0.56875
1 0 1 0 1 0 0 0 0.56250
1 0 1 0 1 0 0 1 0.55625
1 0 1 0 1 0 1 0 0.55000
1 0 1 0 1 0 1 1 0.54375
1 0 1 0 1 1 0 0 0.53750
1 0 1 0 1 1 0 1 0.53125
1 0 1 0 1 1 1 0 0.52500
1 0 1 0 1 1 1 1 0.51875
1 0 1 1 0 0 0 0 0.51250
1 0 1 1 0 0 0 1 0.50625
1 0 1 1 0 0 1 0 0.50000
11111110OFF
11111111OFF
Design Procedure
The following sections detail the selection process for
the external components used with the MAX8809A/
MAX8810A. Contact your local Maxim representative to
obtain a spreadsheet-based tool to facilitate your
design.
Setting the Switching Frequency
The switching frequency influences the switching loss,
the size of the power MOSFETs, and the size of power
components such as output inductors and capacitors.
Higher switching frequencies result in smaller external
components and more compact designs. However,
power-MOSFET switching losses and magnetic core
losses in the output inductor increase with switching
frequency, reducing efficiency. Select a switching fre-
quency as a tradeoff between size and efficiency.
Once the per-phase switching frequency is selected,
the internal oscillator frequency (fOSC) must be set.
Determine the required oscillator frequency based on
the desired per-phase switching frequency (fSW) from
Table 7.
For 2- or 4-phase designs, the internal clock frequency
should be set at four times the desired per-phase
switching frequency. In 3-phase designs, the internal
clock frequency should be set at three times the
desired per-phase switching frequency. Set the internal
clock frequency with a resistor from OSC to GND
(ROSC). The value of ROSC for a given internal clock
frequency is approximated from the following equation:
Rf
OSC OSC
. .
=×
−
161 88 1 2074
Table 7. Required Clock Frequency for
Per-Phase Switching Frequency
NO. OF
PHASES
CONFIGURATION fOSC
2PWM3 = VCC (MAX8809A);
PWM3 = PWM4 = VCC (MAX8810A)
4 x fSW
3 PWM4 = VCC (MAX8810A)
3 x fSW
4 MAX8810A only
4 x fSW
MAX8809A/MAX8810A
34 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where fOSC is given in MHz and ROSC is in kΩ. Also
see the Per-Phase Frequency vs. ROSC graph in the
Typical Operating Characteristics for the relationship
between the clock frequency and the value of the fre-
quency-setting resistor.
Output Inductor Selection
The output inductor is selected based on the desired
amount of inductor ripple current. A larger inductance
value minimizes output ripple current and increases
efficiency but slows down the output-inductor-current
slew rate during a load transient. LIR is the ratio of rip-
ple current to the total current per phase. For the best
tradeoff of size, cost, and efficiency, an LIR of 30% to
60% is recommended (LIR = 0.3 to 0.6). Choose a
higher LIR when more phases are used to take advan-
tage of ripple-current cancellation. The inductor value
is determined from:
where fSW is the per-phase switching frequency,
IOUT_MAX is the maximum-rated output current, D is the
duty ratio, N is the number of phases, and VOUT is the
output voltage at a given VID code. The output-inductor
ripple current produces a ripple voltage across the out-
put-capacitor ESR that usually is the dominant compo-
nent of the output voltage ripple. For an N-phase buck
converter with a D x N factor of less than 1, the output
ripple voltage, VRIPPLE, can be calculated using:
This equation takes into account the voltage ripple can-
cellation from multiphase designs. Optimum voltage
positioning (droop) requires the effective output-capac-
itor ESR to match the load resistance, RO. For initial rip-
ple-voltage estimates, replace RESR_CO with RO. If the
output-ripple-voltage specification is not satisfied, a
larger value of output inductance should be chosen.
The selected inductor should have the lowest possible
DC resistance, and the saturation current should be
greater than the peak inductor current, IPEAK. IPEAK is
found from:
When the DC resistance (RDC) of the output inductor is
used for current sensing, the DC resistance should be
a minimum of 0.5mΩ.
It is also important that the peak-to-peak ripple voltage at
the input of the current-sense amplifier not exceed 23mV:
(VCS+ - VCS-) = IRIPPLE x RSENSE
where RSENSE is the sense resistance value at the
highest operating temperature. If this condition is not
met, then the LIR must be adjusted or the input signal
to the current-sense amplifier must be scaled down
with a resistor-divider.
Output Capacitor Selection
In most cases, selection of the output capacitor is dic-
tated by the target ESR requirement, RESR_CO = RO
(load resistance), to meet the core-supply transient
response. However, the minimum output capacitance,
CO(MIN) , required to meet load-dump requirements, is
estimated based on energy balance from:
where IINIT and IFIN are the initial and final values of the
inductor current during a load dump, VINIT is the volt-
age prior to the load dump, VFIN is the voltage after,
and VOV is the allowed overshoot above VFIN. The
above equation is an approximation, and the output-
capacitance value obtained serves as a good starting
point. The final value should be obtained from actual
measurements.
There is also an upper limit on the amount of output
capacitance to meet the OTF VID change requirement.
Too much output capacitance can prevent the output
voltage from reaching the new VID output voltage with-
in the OTF time window:
where tOTF is the time window to achieve ΔVOTF
(change in output voltage). If CO(MAX) is less than
CO(MIN), the system does not meet the VID OTF specifi-
cation. ILIM is usually set at 110% to 120% of IOUT_MAX.
RMS ripple current rating is an additional requirement
for the output capacitors. For a multiphase buck con-
verter, the RMS ripple current in the output capacitors
is given by:
for (N x D) ≤1, where D is the duty cycle and is com-
puted from the following equation:
DNV I R R
NV I R R
OUT OUT MAX DSON LS DC
IN OUT MAX DSON HS DS LO
=×+ × +
×− × −
__
___
()
()
IVND
Lf
CO RMS OUT
SW
_
()
=×−×
××
1
23
CII t
V
O MAX
LIM OUT MAX OTF
OTF
()
_
≤−
()
×
Δ
C
LI I
NV V V V
OMIN
INIT FIN
FIN INIT OV INIT
()
≥× ×−
⎛
⎝⎞
⎠
×−+
()
×
1
2
22
II
N
LIR
PEAK OUT MAX
_
=×+
⎛
⎝
⎜⎞
⎠
⎟
12
VVR DN
fL
RIPPLE OUT ESR CO
SW
=××−×
×
_(( ))1
LVDN
LIR f I
OUT
SW OUT MAX
≥×− ×
××
()
_
1
MAX8809A/MAX8810A
______________________________________________________________________________________ 35
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Use the maximum input voltage for calculating the duty
cycle to obtain the worst-case RMS ripple current.
RDSON_LS and RDSON_HS are the on-state resistances
of the low-side and high-side MOSFETs, respectively,
and RDC is the DC resistance of the output inductor.
Input Capacitor Selection
The input capacitor reduces the peak current drawn
from the power source and reduces the noise and volt-
age ripple on the input DC voltage bus caused by the
circuit’s switching. The input capacitors must meet the
ripple-current requirement (IRMS) imposed by the
switching currents as defined by the following equation:
for (D x N) ≤1
Use the minimum input voltage for calculating the duty
cycle to obtain the worst-case input-capacitor RMS rip-
ple current. Low-ESR aluminum electrolytic, polymer, or
ceramic capacitors should be used to avoid large volt-
age transients at the input during a large step load
change at the output. The ripple-current specifications
provided by the manufacturer should be carefully
reviewed for temperature derating. Additional small-
value, low-ESL ceramic capacitors (1µF to 10µF with
proper voltage rating) can be used in parallel to reduce
any high-frequency ringing.
Boost Capacitor Selection
The MAX8809A/MAX8810A use a bootstrap circuit to
generate the floating supply voltages for the high-side
drivers. The selected high-side MOSFET determines
the appropriate boost capacitance values according to
the following equation:
where MHS is the total number of high-side MOSFETs
handled by each BST_ capacitor, QGATE_HS is the total
gate charge of each high-side MOSFET, and ΔVBST is
the voltage variation allowed on the high-side MOSFET
drive. Choose ΔVBST = 0.1V to 0.2V when determining
the CBST_ value. Use low-ESR ceramic capacitors for
CBST_. Note that QGATE_HS is a function of gate-drive
voltage VVL_ and should be obtained from the MOSFET
data sheet VGS vs. QGATE curve.
VL_ Bypass Capacitor Selection
VL_provides the supply voltages for the low-side dri-
vers. The decoupling capacitor at VL_ also charges the
high-side driver’s BST capacitor during the time period
when the low-side MOSFET is turned on. Therefore, the
decoupling capacitor for VL_ should be large enough
to minimize the ripple voltage during switching transi-
tions. Choose CVL_ according to the following equation:
Power-MOSFET Selection
MOSFET power dissipation depends on the gate-drive
voltage (VD), the on-resistance (RDSON), the total gate
charge (QGATE), and the gate threshold voltage (VTH).
The supply voltage (VL_) range for the MOSFET drivers
is from 4.5V to 7V. With VGATE < 10V, logic-level
threshold MOSFETs are recommended.
Power dissipation in the high-side MOSFET consists of
two parts: the conduction loss and the switching loss.
The per phase conduction loss for the high side can be
calculated from:
where N is the number of phases and MHS is the num-
ber of MOSFETs in parallel for each phase. Total high-
side conduction loss equals the number of phases
times PCOND_HS.
Switching loss is the major contributor to the high-side
MOSFET power dissipation due to the hard switching
transition every time it turns on. The switching loss is
found from the following:
where VDis the gate-drive voltage and RGATE is the total
gate resistance including the driver’s on-resistance (see
the Electrical Characteristics table) and the MOSFET gate
resistance. For a logic-level power MOSFET, the gate
resistance is approximately 2Ω. QMILLER is the MOSFET
Miller charge found in the MOSFET data sheet.
Note that adding more MOSFETs in parallel on the high
side increases the switching loss. Smaller Miller gate
charge and lower gate resistance usually result in lower
switching loss.
The low-side MOSFET power dissipation is mostly
attributed to the conduction loss. Switching loss is neg-
ligible due to the zero-voltage switching at turn-on and
body-diode clamp at turn-off. Power dissipation in the
low-side MOSFETs of each phase can be calculated
from the following equation:
PD
I
N
LIR R
M
COND LS OUT MAX DSON LS
LS
___
() =− × × +
⎛
⎝
⎜⎞
⎠
⎟×11
12
2
2
2
PVI
N
RQ
VV fM
SW HS IN OUT MAX GATE MILLER
DTH SW HS_ _
=×× ××
−××
2
PD
I
N
LIR R
M
COND HS OUT MAX DSON HS
HS
___
()=× ×+ ×
2
2
2
112
CC
VL BST__
=×10
CQM
V
BST GATE HS HS
BST
_
=×
Δ
IDI ND
RMS OUT MAX
_
=× × ×−
11
MAX8809A/MAX8810A
36 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where MLS is the number of MOSFETs in parallel per
phase on the low side. Total power dissipation for the
low side equals the number of phases times the low-
side conduction loss of each phase.
Even though the switching loss is insignificant in the
low-side MOSFETs, RDSON is not the only parameter
that should be considered in selecting the low-side
MOSFETs. Large Miller capacitance (CRSS) could turn
on the low-side MOSFETs momentarily when the drain-
to-source voltage goes high at fast slew rates, if the dri-
ver cannot hold the gate low. The ratio of CRSS/CISS
should be less than 1/10th for the low-side MOSFETs to
avoid shoot-through current due to momentary turn-on
of the low-side switch. Adding a resistor between BST_
and CBST_ can slow the high-side MOSFET turn-on.
Similarly, adding a capacitor from the gate to the
source of the high-side MOSFET has the same effect.
However, both methods are at the expense of increas-
ing the high-side switching losses.
Loop-Compensation Design
Loop Compensation with Voltage Positioning
Processor power-supply specifications often require
the output voltage to “droop” from its no-load value at a
fixed slope with increasing load current. This slope is
termed the load-line resistance (RO). Once the current-
sense resistance (RSENSE), the required load-line resis-
tance, and the output offset voltage (VOS) are
determined, the values of RLL and ROS (see Figure 8)
are calculated from the following equations:
For the MAX8809A:
For the MAX8810A:
The 1V BUF output simplifies the ROS calculation con-
siderably. ROS and RLL are calculated as:
The pole due to the load (ROUT) and output capaci-
tance produces a -20dB/decade slope up to the output-
capacitor ESR zero frequency. To continue to roll off the
gain out to high frequencies at -20dB/decade, the com-
pensation places a pole at the ESR zero frequency. An
RC circuit, RCOMP and CCOMP, must be connected
from COMP to ground. Calculate RCOMP as the parallel
combination of RLL and ROS. The capacitor value can
be found from the following equation once the output
capacitor ESR is known:
where RESR_CO is the total equivalent series resistance
and COis the total capacitance of the output capacitors.
Loop Compensation with Integral Feedback
For applications that do not implement droop, it is nec-
essary to compensate the loop using integral feedback.
Looking at the transfer function from inductor current
iL(t) to output:
The DC gain is the output impedance ROUT:
ROUT = VOUT / IOUT_MAX
A pole and zero are present due to the output capaci-
tance (CO), output-capacitor ESR (RESR_CO), and the
load impedance (ROUT), as follows:
The transfer function from control voltage vC(t) to induc-
tor current iL(t) is:
where RSENSE is the resistance of the current-sense
element, and GCA is the current-sense amplifier gain.
The simplified control-to-output transfer function is then:
GgGN
CONTR OUTPUT PWM VI_ ωω
()
=×
()
×
git
vt RG
PWM L
CSENSE CA
=
()
()
=×
1
:
_
_
_
Ω= +
()
×
Ω= ×
()
+
()
×
POLE OUT ESR CO O
ZERO OUT ESR CO
OUT ESR CO O
RR C
and
RR
RR C
1
1
GR
VI OUT ZERO
POLE
ω
ω
ϖ
ω
ϖ
()
=×
+
+
1
1
CRC
R
COMP ESR CO O
COMP
=×
_
R
gV
RRR
RR
RRG
Ng R
OS
MV OS
LL OS COMP
OS COMP
COMP SENSE CA
MV O
=×
=×
−
=×
××
1
RgNR
RG
V
RgNR
RG
V
LL
MV O
SENSE CA OS
OS
MV O
SENSE CA OS
=
××
×−
⎛
⎝
⎜⎞
⎠
⎟
=
××
×+
⎛
⎝
⎜⎞
⎠
⎟−×
1
2
1
2
1
20 106
where:
MAX8809A/MAX8810A
______________________________________________________________________________________ 37
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
This simplified transfer function ignores a double pole
due to the current-mode sampling effect, which can be
approximately placed at 1/2 the per-phase switching
frequency.
As a rule-of-thumb, the loop should be designed to
close between 1/5th and 1/10th of the per-phase
switching frequency. At this point, a determination
should be made as to which of the following cases
applies to the desired crossover frequency:
• Case 1: ωPOLE < 2πx fCROSSOVER < ωZERO
This case is likely to exist in situations where the zero
frequency (ωZERO) is relatively high due to use of low-
value output capacitors with low ESR (e.g., 560µF/7mΩ
or all-ceramic designs).
Analysis of the control-to-output transfer function for
this case shows that 1) the slope is -1 at the crossover
frequency due to the low-frequency pole (ωPOLE), and
2) the compensation must provide gain boost at the
crossover frequency to bring the loop gain to zero at
crossover. Because of item 1), the compensator gain
must be flat at crossover so that the closed-loop gain
rolls off with -1 slope at crossover.
For this case, it is recommended to design the com-
pensator with type II compensation. The zero is placed
to ensure flat gain at crossover, and the 2nd pole pro-
vides phase shift above crossover. The compensator
consists of a series resistor (RCOMP) and capacitor
(CCOMP1) from COMP to GND, and a second capacitor
(CCOMP2) placed from COMP to GND, in parallel to
RCOMP and CCOMP1 (see Figure 11).
The first step in the compensator design is to choose
the desired phase margin at crossover and solve for
the error-amplifier phase shift:
φERROR_AMPLIFIER = φMARGIN - φCONTR_OUTPUT
where φMARGIN is the desired phase margin at cross-
over, and φCONTR_OUTPUT is the phase shift from control-
to-output (at crossover).
The next step is to determine the constant K value in the
equation below, which provides the desired error-ampli-
fier phase shift determined above. The value of K deter-
mines the locations of the error-amplifier zero and
high-frequency pole relative to the crossover frequency:
The simplified compensator transfer function can be
modeled at low frequencies as:
where gMV is the transconductance of the error amplifi-
er. At crossover, CCOMP1 is essentially a short and can
be ignored. The compensator must provide gain boost
to bring the loop gain to zero at crossover. Applying
these criteria and solving for RCOMP:
Solving for CCOMP1 and CCOMP2 is now relatively
straightforward:
• Case 2: ωZERO < 2πx fCROSSOVER < ωPOLE-CM
where ωPOLE-CM is the frequency of the double pole
created by the sampling effect. This case is likely to
exist in situations where high-capacitance, high-ESR
output capacitors (e.g., low-cost aluminum electrolytic
such as 2800µF/12mΩ) are used.
Analysis of the control-to-output transfer function for this
case shows that 1) the slope is zero at crossover so the
compensation must roll off with a -1 slope, and 2) the
compensation must provide gain boost at the
crossover frequency to bring the loop gain to zero at
crossover. Both of these conditions are satisfied with
the following relationship:
gfC
Gf
MV CROSSOVER COMP CONTR OUTPUT CROSSOVER
||
_
×××
=
()
1
2
1
π
CR
CR
COMP ZERO ERROR AMPLIFIER COMP
COMP POLE ERROR AMPLIFIER COMP
1
2
1
1
__
__
=×
=×
ω
ω
RgG f
COMP MV CONTR OUTPUT CROSSOVER
||
_
=×
()
1
gR C
MV COMP COMP
×+
×
⎛
⎝
⎜⎞
⎠
⎟
1
1
ω
φπ
ω
ω
ERROR AMPLIFIER
ZERO ERROR AMPLIFIER CROSSOVER
POLE ERROR AMPLIFIER CROSSOVER
KK
f
K
fK
_
__
__
arctan arctan
=
()
−⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜⎞
⎠
⎟×+
=π×
=π× ×
1 180 90
2
2
MAX8809A/
MAX8810A
COMP
RCOMP
CCOMP2
CCOMP1
Figure 11. Type II Compensation Scheme
MAX8809A/MAX8810A
38 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
where gMV is the transconductance of the error amplifi-
er and CCOMP is a capacitor placed from the output of
the error amplifier (COMP) to GND. Solving for CCOMP:
Multiload-Line Programming (MAX8810A)
In some applications, it may be desired to implement
multiple load-lines. This is easily accomplished by
switching resistors in parallel with RLL (Figure 12).
Paralleling resistors with RLL causes the load-line resis-
tance to increase. With this scheme implemented for
the MAX8810A, the offset voltage is not affected by the
new load-line setting. It is also not necessary to change
the temperature compensation based on the new load-
line setting. Switches S1 and S2 can be implemented
with small-signal n-channel MOSFETs.
RLL1 and ROS are designed using methods described
in the Loop-Compensation Design section. RO1, RO2,
and RO3 are the required load-line resistances. RLL2
and RLL3 are calculated as follows:
Setting the Current Limit
The current-limit threshold sets the maximum available
output DC current. The output current limit should be
selected to meet the OTF requirement as described in
the Output Capacitor Selection section. The voltage at
ILIM and the value of the current-sense resistor or the
DC resistance of the output inductor sets the current-
limit threshold:
where RSENSE is the resistance of the current-sensing
element. The value of RSENSE at room temperature
must be used because the MAX8809A and MAX8810A
provide temperature-compensated current limit. VILIM
is set by connecting ILIM to the center tap of a resistor-
divider from REF to GND. Select R1 and R3 (Figure 13)
so the current through the divider is at least 10µA:
R1 + R3 < 200kΩ
A typical value for R1 is 10kΩ; then solve for R3 using:
RR V
V
LIM
LIM
31
2
=×
−
VGR I
N
ILIM CA SENSE LIM
=× ×
RRR
RRR
RR
RR
RR
RRR
RR
RRR
RR
RR
R
COMP LL OS
LL COMP COMP
COMP COMP
COMP O
OCOMP
COMP LL OS
LL OS
LL COMP COMP
COMP COMP
COMP O
O
1
212
12
21
21
11
1
323
23
32
3
||
=
=×
−
=×
=×
+
=×
−
= ×RCOMP2
Cgx
Gf
f
COMP MV CONTR OUTPUT CROSSOVER
CROSSOVER
||
_
=
()
×2π
MAX8810A
COMP
BUF
RLL1
ROS
RLL2
RLL3
Figure 12. Load-Line Switching Circuit
where:
and:
where:
MAX8809A/MAX8810A
______________________________________________________________________________________ 39
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in
any switching DC-DC converter circuit. Mount the
MOSFETs, inductors, input/output capacitors, and cur-
rent-sense resistor on the top side of the PC board. A
single large ground plane is preferred; however it is
very important to partition the ‘analog’ portion of this
ground plane from the ‘power’ portion of the ground
plane. Ensure that all analog ground connections are
made to the ground plane away from any areas of
power ground switching currents. Do not connect the
analog returns at a single point to the ground plane;
use as many direct connections as possible. Connect
the GND of the IC to the thermal pad of the IC on the
top layer. Connect the thermal pad to the ground plane
through at least nine 10-mil drill size VIAs.
To help dissipate heat, place high-power components
(MOSFETs and inductors) on a large copper area, or
use a heat sink. Keep high-current traces short, wide,
and tightly coupled to reduce trace inductances and
resistances. Gate-drive traces should be at least 20
mils wide, kept as short as possible, and tightly cou-
pled to reduce EMI and ringing induced by high-fre-
quency gate currents. Adjacent DH_ and LX_ traces
should be tightly coupled. Connect the PGND_ pins to
the ground plane near the controller through two VIAs
(each).
A clean current-sense signal is critical to a successful
layout. Always place the current-sense traces on the
bottom layer. Make sure all adjacent traces (for exam-
ple CS1+, CS2+, and CS12-) are tightly coupled. Kelvin
connections to the current-sense element are essential.
For inductor DCR current-sensing, place all current-
sense components near the inductor, except for the fil-
tering capacitors, which should be placed next to the
controller IC. This ensures that noise generated by
large di/dt on the LX node is kept away from both cur-
rent-sense signals and the controller IC. To ensure the
integrity of the current-sense signal, the inner layer
above the bottom layer must be a solid ground plane.
Place the VL_ decoupling capacitor on the top layer
and near the VL_ pins. The negative terminal of the VL_
decoupling capacitor should be connected to PGND_
on the top layer. Also place the BST capacitors on the
top layer near the controller. When needed always use
double VIAs on the driver traces to reduce inductance.
Do not connect the PGND_ pins to the thermal pad on
the top layer.
The NTC thermistor should be placed near the “hottest”
inductor. Use two traces, tightly coupled, to return to
the controller. To ensure temperature compensation
accuracy, make sure that the GND trace of the NTC is
not “accidentally” connected to any other GND trace or
ground plane on the way back to the controller.
Place the BUF capacitor, REF capacitor, VCC capaci-
tor, the current-sense decoupling capacitors, and the
remote-sense decoupling capacitors as close to the
MAX8809A/MAX8810A as possible. All decoupling
capacitors must make a direct connection to the corre-
sponding pin. Making the connection using VIAs to
transition between layers creates parasitic inductance,
which negates the benefit of the decoupling capacitor.
If this cannot be avoided, use double VIAs to minimize
the parasitic inductance.
A sample layout is available in the evaluation kit to
speed designs.
Chip Information
PROCESS: BiCMOS
MAX8809A/MAX8810A
40 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
R5R4
C10
CS1+
VIN+
VOUT
VTT
VRHOT
VRREADY
VCC_SEN
VSS_SEN
OUTEN
REF
REF
SYSTEM 5V
C12
R7R6
C21
SYSTEM 5V
C26C25
R17
R13
R12
R16
R23
R24
VOUT
VIN+
N1
N3
N2
1
2
3
1
2
3
2
3
1
2
3
1
1
2
3
1
2
3
2
3
1
2
3
1
C5 C6 C7 C1 C2
L1
L2
C3 C4
C27 C28 C29 C30 C31 C32 C33
C17
C15
C11
C9
C8
6
32
20
1
18
3
10
4
12
11
5
26
8
7
C18 C19
C22 C23
C24
N4
VIN+
MAX8809A
C14
R11R10
C13
CS2+
R15
C16
N5
N7
N6
N8
R20R19
C20
CS3+
N9
N11
N10
1
1
2
9
3
3
1
2
3
2
3
1
2
3
1
10
1
4
BST
DH1
BST1
ILIM
ILIM
LX1
LX2
DL1
PGND1
DH2
DL2
BST2
PGND2
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CS3+
CS3-
CS2+
CS1+
CS12-
PWM3
OSC
DH
LX
CS3-
CS3+
CS2+
CS1+
CS12-
DL
5
6
7
VL
9
VCC
GND
PGND
VCC
SEL
VRHOT
VRREADY
EN
REF
SS/OVP
COMP
VRTSET
NTC
GND
VL12
VL
EP
RS+
RS-
VCC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DLY
PWM
MAX8552
EN
8
21
U1
2
23
22
24
25
31
29
30
28
27
33
34
35
36
37
38
39
40
13
14
15
17
16
19
2
3
L3
R21
R9
N12
VL
R14
R22
R1
R3
R2
R18
D1
U2
R25
CS12-
CS3-
Figure 13. Intel VRD11 Desktop Application Circuit Using the MAX8809A—3-Phase, 85A
MAX8809A/MAX8810A
______________________________________________________________________________________ 41
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
COMPONENTS DESCRIPTION PART NUMBER
C1–C4 1500µF, 16V aluminum electrolytic capacitors Rubycom 16VMBZ1500
C5, C6, C7 10µF, 16V X5R ceramic capacitors (1206) Taiyo Yuden EMK316BJ106ML
C8, C15, C21 2.2µF, 10V X5R ceramic capacitors (0603) Taiyo Yuden LMK107BJ225MA
C9, C11, C12, C16, C17 0.22µF, 16V X5R ceramic capacitors (0603) Taiyo Yuden EMK107BJ224KA
C10, C13, C20 2200pF, 50V X7R ceramic capacitors (0603) TDK C1608X7R1H222K
C14 68pF, 50V C0G ceramic capacitor (0603) Kemet C0603C101J5GACTU
C18, C22, C23 0.22µF, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A224K
C19, C24, C25, C26 1000pF, 50V X7R ceramic capacitors (0603) Kemet C0603C102J5RACTU
C27–C33 560µF, 4V, 7mΩ ESR OS-CON capacitors Sanyo 4R5SEP560M
D1 30V, 200mA Schottky diode (SOT23) Central Semiconductor CMPSH-3
L1, L2, L3 0.20µH, 30A toroid cores Falco T50069
N1, N2, N5, N6, N9, N10 30V, 12mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7821
N3, N4, N7, N8, N11, N12
30V, 4.5mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7843
R1 10kΩ ±1% resistor (0603) —
R2 10Ω ±5% resistor (0603) —
R15 5.62kΩ ±1% resistor (0603) —
R4, R9, R10, R19, R21 2.2Ω ±5% resistors (0603) —
R5, R11, R20 1.62kΩ ±1% resistors (0603) —
R6, R7 680Ω ±1% resistors (0603) —
R3, R12 8.06kΩ ±1% resistors (0603) —
R13 22kΩ ±5% resistor (0603) —
R14 0Ω ±5% resistor (0603) —
R16 10kΩ NTC thermistor Panasonic ERTJ1VR103
R17 61.9kΩ ±1% resistor (0603) —
R18 7.1kΩ ±1% resistor (0603) —
R22 Not installed
R23, R24 100Ω ±1% resistors (0603) —
R25 220kΩ ±1% resistor (0603) —
U1 VRD11, VRD10, and K8 Rev F 3-phase controller Maxim MAX8809A
U2 High-speed, single-phase MOSFET driver Maxim MAX8552
Table 8. Bill of Materials for Intel VRD11 3-Phase Desktop Application Circuit
(Figure 13)
MAX8809A/MAX8810A
42 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
R4
C11
VIN+
VOUT
VTT
VRHOT
VRREADY
VCC_SEN
VSS_SEN
OUTEN
REF
REF
SYSTEM 5V
C13
R7R6
C17
C25
C31C30
R12
NTC
R16
R22
R23
C14
R13
VOUT
VIN+
N1
N3
N2
C5
1
2
3
1
2
3
2
3
1
2
3
1
1
2
3
1
2
3
2
3
1
2
3
1
C6 C7 C8 C1 C2
L1
L2
C3 C4
C33 C34 C35 C36 C37 C38
C22
C18
C23
C19
C12
C10
C9
6
38
24
48
21
2
12
3
4
14
13
5
30
31
9
8
C20 C21
C26 C27
C28
C29
N4
VIN+
MAX8810A
R10
C15
C39 C40
N5
N7
N6
N8
R17
C24
VIN+
N9
N11
N10
1
1
2
2
11
3
3
1
2
3
2
3
1
2
3
1
1
16
15
14
12
1
4
13
BST1
DH1
BST1
ILIM
LX1
DL1
PGND1
DH2
BST2
LX2
DL2
PGND2
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CS34-
CS4+
CS3+
CS2+
CS1+
CS12-
PWM3
PWM4
OSC
DH1
LX1
CS34-
CS4+
CS3+
CS2+
CS1+
CS12-
PGND1
DL1
PGND2
BST2
DH2
LX2
DL2
7
8
9
10
2
PV1
PV2
VCC
SEL
VRHOT
VRREADY
EN
REF
SS/OVP
COMP
BUF
NTC
VRTSET
GND
VL1
VL
SYSTEM 5V
VL2
EP
RS+
RS-
VCC
N.C.
N.C.
VID5
VID4
VID3
VID2
VID1
VID0
VCC
DLY
PWM1
MAX8523
PWM2
3
25
U1
1
27
26
28
29
36
34
35
33
32
39
40
41
42
43
44
45
46
16
15
17
18
20
19
23
22
5
6
11
2
3
1
2
3
2
3
1
2
3
1
L3
L4
R19
R9
N12
VL
R25
R24
R21
R14
R15
R1
R3
R2
R20
D1
U2
R26
C32
CS4+
CS12-
CS34-
N13
N15
N14
N16
R27
R5
CS1+
R27
C41
R11
CS2+
R28
C42
R18
CS3+
R29
C43
R30
C44
Figure 14. Intel VRD11 Desktop Application Circuit Using the MAX8810A—4-Phase, 115A
MAX8809A/MAX8810A
______________________________________________________________________________________ 43
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 9. Bill of Materials for Intel VRD11 4-Phase Desktop Application Circuit
(Figure 14)
COMPONENTS DESCRIPTION PART NUMBER
C1–C4 1500µF, 16V aluminum electrolytic capacitors Rubycom 16VMBZ1500
C5–C8 10µF, 16V X5R ceramic capacitors (1206) Taiyo Yuden EMK316BJ106ML
C9, C17, C18, C25 2.2µF, 10V X5R ceramic capacitors (0603) Taiyo Yuden LMK107BJ225MA
C10, C12, C13, C22, C29 0.22µF, 16V X5R ceramic capacitors (0603) Taiyo Yuden EMK107BJ224KA
C11, C15, C24, C32 2200pF, 50V X7R ceramic capacitors (0603) TDK C1608X7R1H222K
C14 68pF, 50V C0G ceramic capacitor (0603) Kemet C0603C101J5GACTU
C19, C20, C26, C27 0.22µF, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A224K
C21, C28, C30, C31 1000pF, 50V X7R ceramic capacitors (0603) Murata C0603C102J5RACTU
C33–C40 560µF, 4V, 7mΩ ESR OS-CON capacitors Sanyo 4R5SEP560M
D1 30V, 200mA Schottky diode (SOT23) Central Semiconductor CMPSH-3A
L1–L4 0.20µH, 30A toroid cores Falco T50069
N 1, N 2, N 5, N 6, N 9, N 10, N 13, N 14
30V, 12mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7821
N 3, N 4, N 7, N 8, N 11, N 12, N 15, N 16
30V, 4.5mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7843
R1 10kΩ ±1% resistor (0603) —
R2, R15 10Ω ±5% resistors (0603) —
R3 7.15Ω ±1% resistor (0603) —
R4, R9, R10, R17, R19, R24 2.2Ω ±5% resistors (0603) —
R5, R11, R18, R25 1.62kΩ ±1% resistors (0603) —
R6, R7 680Ω ±1% resistors (0603) —
R12 22.0kΩ ±1% resistor (0603) —
R13 26.1kΩ ±1% resistor (0603) —
R14, R21 0Ω ±5% resistors (0603) —
R16 61.9kΩ, ±1% resistor (0603) —
R20 7.17Ω ±1% resistor (0603) —
R22, R23 100Ω ±1% resistors (0603) —
R26 160kΩ ±1% resistor (0603) —
R27 2.87kΩ ±1% resistor (0603) —
NTC 10kΩ NTC thermistor Panasonic ERTJ1VR103
U1
VRD11, VRD10, and K8 Rev F 4-phase controller
Maxim MAX8810A
U2 High-speed, dual-phase MOSFET driver Maxim MAX8523
MAX8809A/MAX8810A
44 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
R5R27
R4
C11
CS1+
C41
VIN+
VOUT
VTT
VRHOT
VRREADY
VCC_SEN
VSS_SEN
OUTEN
REF
REF
SYSTEM 5V
C13
R7R6
C17
C25
C31C30
R12
NTC
R16
R22
R23
C14
C16 R13
VOUT
VIN+
N1
N3
N2
C5
1
2
3
1
2
3
2
3
1
2
3
1
1
2
3
1
2
3
2
3
1
2
3
1
C6 C7 C8 C1 C2
L1
L2
C3 C4
C33 C34 C35 C36 C37 C38
C22
C18
C23
C19
C12
C10
C9
6
38
24
48
21
2
12
3
4
14
13
5
30
31
9
8
C20 C21
C26 C27
C28
C29
N4
VIN+
MAX8810A
R28
C42
R29
C43
R30
C44
R11
R10
C15
CS2+
C39 C40
N5
N7
N6
N8
R18
R17
C24
CS3+
VIN+
N9
N11
N10
1
1
2
2
11
3
3
1
2
3
2
3
1
2
3
1
1
16
15
14
12
1
4
13
BST1
DH1
BST1
ILIM
LX1
DL1
PGND1
DH2
BST2
LX2
DL2
PGND2
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CS34-
CS4+
CS3+
CS2+
CS1+
CS12-
PWM3
PWM4
OSC
DH1
LX1
DL1
CS34-
CS4+
CS3+
CS2+
CS1+
CS12-
PGND1
PGND2
BST2
DH2
LX2
DL2
7
8
9
10
2
PV1
PV2
VCC
SEL
VRHOT
VRREADY
EN
REF
SS/OVP
COMP
BUF
NTC
VRTSET
GND
VL1
VL
SYSTEM 5V
VL2
EP
RS+
RS-
VCC
N.C.
N.C.
VID5
VID4
VID3
VID2
VID1
VID0
VCC
DLY
PWM1
MAX8523
PWM2
3
25
U1
1
27
26
28
29
36
34
35
33
32
39
40
41
42
43
44
45
46
16
15
17
18
20
19
23
22
5
6
11
2
3
1
2
3
2
3
1
2
3
1
L3
L4
R19
R9
N12
VL
R25
R24
R21
R14
R15
R1
R3
R2
R20
D1
U2
R26
C32
CS4+
CS12-
CS34-
N13
N15
N14
N16
Figure 15. AMD K8 Rev F Desktop Application Circuit Using the MAX8810A—4-Phase, 115A
MAX8809A/MAX8810A
______________________________________________________________________________________ 45
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 10. Bill of Materials for AMD K8 Rev F Desktop Application Circuit (Figure 15)
COMPONENTS DESCRIPTION PART NUMBER
C1–C4 1500µF, 16V aluminum electrolytic capacitors Rubycom 16VMBZ1500
C5–C8 10µF, 16V X5R ceramic capacitors (1206) Taiyo Yuden EMK316BJ106ML
C9, C17, C18, C25 2.2µF, 10V X5R ceramic capacitors (0603) Taiyo Yuden LMK225BJ225ML
C10, C12, C13, C22, C29 0.22µF, 10V X5R ceramic capacitors (0603) Taiyo Yuden EMK107BJ224KA
C11, C15, C24, C32 2200pF, 50V X7R ceramic capacitors (0603) TDK C1608X7R1H222K
C14 Not installed (0603) —
C16 0.015µF, 50V C0G ceramic capacitor (0603) Murata GRM39X7R153K50
C19, C20, C23, C26, C27 0.22µF, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A224K
C21, C28, C30, C31 1000pF, 50V X7R ceramic capacitors (0603) Kemet C0603C102J5RACTU
C33–C40 2200µF, 6.3V, 12mΩ ESR aluminum electrolytic
capacitors Rubycon 6.3VMBZ2200
C41–C44 Not installed (0603) —
D1 30V, 200mA Schottky diode (SOT23) Central Semiconductor CMPSH-3A
L1–L4 0.28µH, 30A toroid cores Falco T50183
N 1, N 2, N 5, N 6, N 9, N 10, N 13, N 14
30V, 12mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7821
N 3, N 4, N 7, N 8, N 11, N 12, N 15, N 16
30V, 4.5mΩ n-channel logic MOSFETs (DPAK) International Rectifier IRLR7843
R1 10kΩ ±1% resistor (0603) —
R2, R15 10Ω ±5% resistors (0603) —
R3 7.15kΩ ±1% resistor (0603) —
R4, R9, R10, R17, R19, R24 2.2Ω ±5% resistors (0603) —
R5, R11, R18, R25 1.62kΩ ±1% resistors (0603) —
R6, R7 680Ω ±1% resistors (0603) —
R12 22.0kΩ ±1% resistor (0603) —
R13 4.32kΩ ±1% resistor (0603) —
R14, R21 0Ω ±5% resistors (0603) —
R16 61.9kΩ ±1% resistor (0603) —
R20 7.10kΩ ±1% resistor (0603) —
R22, R23 100Ω ±11% resistors (0603) —
R26 160kΩ ±1% resistor (0603) —
R27–R30 Not installed (0603) —
NTC 10kΩ NTC thermistor Panasonic ERTJ1VR103
U1 VRD11, VRD10, and K8 Rev F 4-phase Maxim MAX8810A
U2 High-speed, dual-phase MOSFET driver Maxim MAX8523
MAX8809A/MAX8810A
46 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Table 11. Suggested Component Suppliers
COMPONENT SUPPLIER PHONE FAX WEBSITE
BI Technologies 714-447-2300 714-388-0046 www.bitechnologies.com
Falco 305-662-7276 928-752-3256 www.falco.com
International Rectifier 310-252-7105 310-252-7903 www.irf.com
Kemet 864-963-6300 408-986-1442 www.kemet.com
Murata 770-436-1300 770-436-3030 www.murata.com
Pulse 215-781-6400 215-781-6403 www.pulseeng.com
Panasonic 800-344-2112 — www.panasonic.com
Sanyo 619-661-6835 619-661-1055 www.sanyo.com
Taiyo Yuden 81-3-3833-5441 81-3-3835-4754 www.t-yuden.com
TDK 408-437-9585 408-437-9591 www.component.tdk.com
Pin Configurations
TOP VIEW
MAX8810A
THIN QFN
13
14
15
16
17
18
19
20
21
22
23
24
VRTSET
NTC
CS4+
CS34-
CS3+
CS2+
CS12-
CS1+
EN
PWM4
PWM3
VRHOT
48
47
46
45
44
43
42
41
40
39
38
37
12345678910
11 12
VRREADY
N.C.
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
SEL
N.C.
SS/OVP
OSC
N.C.
RS+
RS-
N.C.
VCC
GND
BUF
COMP
REF
ILIM
36 35 34 33 32 31 30 29 28 27 26 25
DH1
LX1
BST1
DL1
PGND1
VL1
VL2
PGND2
DL2
BST2
LX2
DH2
MAX8809A
THIN QFN
TOP VIEW
35
36
34
33
12
11
13
ILIM
COMP
GND
VCC
RS-
14
VRREADY
PGND2
PGND1
DL1
DL2
BST2
LX2
BST1
LX1
12
VID6
4567
27282930 26 24 23 22
VID5
VID4
EN
CS1+
CS12-
CS2+
REF
VL12
3
25
37
VID3 CS3+
38
39
40
VID2
VID1
VID0 +
CS3-
NTC
VRTSET
VID7
32
15
PWM3
SEL
31
16
17
18
19
20 VRHOT
RS+
OSC
SS/OVP DH1
8910
21
DH2
+
MAX8809A/MAX8810A
______________________________________________________________________________________ 47
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX8809A/MAX8810A
48 ______________________________________________________________________________________
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8809A/MAX8810A
______________________________________________________________________________________ 49
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX8809A/MAX8810A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
50 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Cardenas - 80% Freed - 20%
Revision History
Pages changed at Rev 1: 1–6, 8, 13–16, 19, 20, 22,
30-37, 40, 43.
