SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
These dual positive-edge-triggered D-type
flip-flops are designed for 2-V to 5.5-V VCC
operation.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at the D input can be changed without affecting the
levels at the outputs.
The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV74A is characterized for operation from –40°C to 85°C.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54LV74A ...J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
SN54LV74A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
†
H
†
HH↑HHL
HH↑LLH
HHLXQ
0
Q
0
†
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol‡
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK 12
2D 13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
‡This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LV74A SN74LV74A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH
High level in
p
ut voltage
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7
V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
VIL
Low level in
p
ut voltage
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3
V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V –50 –50 µA
IOH
High level out
p
ut current
VCC = 2.3 V to 2.7 V –2 –2
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 3 V to 3.6 V –6 –6 mA
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
IOL
Low level out
p
ut current
VCC = 2.3 V to 2.7 V 2 2
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 3 V to 3.6 V 6 6 mA
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
∆t/∆vInput transition rise or fall rate VCC = 3 V to 3.6 V 0 100 0 100 ns/V
VCC = 4.5 V to 5.5 V 0 20 0 20
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LV74A SN74LV74A
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN TYP MAX
UNIT
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
VOH
IOH = –2 mA 2.3 V 2 2
V
V
OH IOH = –6 mA 3 V 2.48 2.48
V
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA2 V to 5.5 V 0.1 0.1
VOL
IOL = 2 mA 2.3 V 0.4 0.4
V
V
OL IOL = 6 mA 3 V 0.44 0.44
V
IOL = 12 mA 4.5 V 0.55 0.55
IIVI = VCC or GND 5.5 V ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 V 5 5 µA
Ci
VI=V
CC or GND
3.3 V 2.1 2.1 p
F
C
i
V
I =
V
CC
or
GND
5 V 2.1 2.1
pF
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
Pulse duration
PRE or CLR low 8 9 9
ns
t
w
P
u
lse
d
u
ration
CLK 8 9 9
ns
t
Setup time before CLK↑
Data 8 9 9
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
PRE or CLR inactive 7 7 7
ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
Pulse duration
PRE or CLR low 6 7 7
ns
t
w
P
u
lse
d
u
ration
CLK 6 7 7
ns
t
Setup time before CLK↑
Data 6 7 7
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
PRE or CLR inactive 5 5 5
ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
Pulse duration
PRE or CLR low 5 5 5
ns
t
w
P
u
lse
d
u
ration
CLK 5 5 5
ns
t
Setup time before CLK↑
Data 5 5 5
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
PRE or CLR inactive 3 3 3
ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
f
CL = 15 pF* 50 100 40 40
MHz
f
max CL = 50 pF 30 70 25 25
MH
z
td
*PRE or CLR
CL=15
p
F
9.8 14.8 1 17 1 17
ns
t
pd
*
CLK
or
C
L =
15
pF
11.1 16.4 1 19 1 19
ns
td
PRE or CLR
CL=50
p
F
13 17.4 1 20 1 20
ns
t
pd CLK
or
C
L =
50
pF
14.2 20 1 23 1 23
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
f
CL = 15 pF* 80 140 70 70
MHz
f
max CL = 50 pF 50 90 45 45
MH
z
td
*PRE or CLR
CL=15
p
F
6.9 12.3 1 14.5 1 14.5
ns
t
pd
*
CLK
or
C
L =
15
pF
7.9 11.9 1 14 1 14
ns
td
PRE or CLR
CL=50
p
F
9.2 15.8 1 18 1 18
ns
t
pd CLK
or
C
L =
50
pF
10.2 15.4 1 17.5 1 17.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV74A SN74LV74A
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
f
CL = 15 pF* 130 180 110 110
MHz
f
max CL = 50 pF 90 140 75 75
MH
z
td
*PRE or CLR
CL=15
p
F
57.7 1 9 1 9
ns
t
pd
*
CLK
or
C
L =
15
pF
5.6 7.3 1 8.5 1 8.5
ns
td
PRE or CLR
CL=50
p
F
6.6 9.7 1 11 1 11
ns
t
pd CLK
or
C
L =
50
pF
7.2 9.3 1 10.5 1 10.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
SN74LV74A
UNIT
PARAMETER
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.1 0.8 V
VOL(V) Quiet output, minimum dynamic VOL –0.04 –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3.2 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd
Power dissi
p
ation ca
p
acitance
CL=50
p
F
f=10MHz
3.3 V 21 p
F
C
p
d
Power
dissi ation
ca acitance
CL
=
50
F
,
f
=
10
MHz
5 V 23
F
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈ VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈ 0 V
VCC
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE W AVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kΩGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH – 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated