1
FEATURES
TERMINAL ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0/A0/CLK_SEL
VCC
CLK_IN0
CLK_IN1
SCLOCK
Y5
Y4
VCCOUT2
Y2
VCCOUT1
Y0
PWPackage
(TopView)
P0087-01
S1/A1
GND
VCC
GND
SDATA Y1
GND
Y3
GND
DESCRIPTION
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER
•High-Performance 3:6 PLL-Based ClockSynthesizer/Multiplier/Divider
•User-Programmable PLL Frequencies•EEPROM Programming Without the Need toApply High Programming Voltage•Easy In-Circuit Programming via SMBus DataInterface
•Wide PLL Divider Ratio Allows 0-ppm OutputClock Error•Clock Inputs Accept a Crystal, a Single-EndedLVCMOS, or a Differential Input Signal•Accepts Crystal Frequencies From 8 MHz to54 MHz•Accepts LVCMOS or Differential InputFrequencies up to 200 MHz•Two Programmable Control Inputs [S0/S1,
The CDCE706 is one of the smallest and mostA0/A1] for User-Defined Control Signals
powerful PLL synthesizer/multiplier/dividers available•Six LVCMOS Outputs With Output Frequencies
today. Despite its small physical outline, theup to 300 MHz
CDCE706 is very flexible. It has the capability toproduce an almost independent output frequency•LVCMOS Outputs Can Be Programmed for
from a given input frequency.Complementary Signals•Free Selectable Output Frequency via
The input frequency can be derived from anProgrammable Output Switching Matrix [6 × 6]
LVCMOS, differential input clock, or single crystal.The appropriate input waveform can be selected viaIncluding 7-Bit Post-Divider for Each Output
the SMBus data interface controller.•PLL Loop Filter Components Integrated
To achieve an independent output frequency, the•Low Period Jitter (Typically 60 ps)
reference divider M and the feedback divider N for•Features Spread-Spectrum Clocking (SSC) for
each PLL can be set to values from 1 to 511 for theLowering System EMI
M-divider and from 1 to 4095 for the N-divider. The•Programmable Output Slew-Rate Control
PLL-VCO (voltage controlled oscillator) frequency(SRC) for Lowering System EMI
then is routed from the programmable outputswitching matrix to any of the six outputs. The•3.3-V Device Power Supply
switching matrix includes an additional 7-bit•Industrial Temperature Range – 40 ° C to 85 ° C
post-divider (1 to 127) and an inverting logic for each•Development and Programming Kit for Easy
output.PLL Design and Programming (TI ClockPro
The deep M/N divider ratio allows the generation ofSoftware)
zero-ppm clocks from any reference input frequency•Packaged in 20-Pin TSSOP
(e.g., 27 MHz).
The CDCE706 includes three PLLs; of those, onesupports spread-spectrum clocking (SSC). PLL1,PLL2, and PLL3 are designed for frequencies up to300 MHz and optimized for zero-ppm applicationswith wide divider factors.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PLL2 also supports center- and down-spread-spectrum clocking (SSC). This is a common technique to reduceelectromagnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.
Based on the PLL frequency and the divider settings, the internal loop filter components are automaticallyadjusted to achieve the high stability and optimized jitter transfer characteristic of the PLL.
The device supports nonvolatile EEPROM programming for easily customized application. The device ispreprogrammed with a factory default configuration (see Figure 13 ) and can be reprogrammed to a differentapplication configuration before it goes onto the PCB or reprogrammed by in-system programming. A differentdevice setting is programmed via the serial SMBus interface.
Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logiccontrol settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).
The CDCE706 has three power-supply pins, V
CC
, V
CCOUT1
, and V
CCOUT2
. V
CC
is the power supply for the device.It operates from a single 3.3-V supply voltage. V
CCOUT1
and V
CCOUT2
are the power supply pins for the outputs.V
CCOUT1
supplies the outputs Y0 and Y1, and V
CCOUT2
supplies the outputs Y2, Y3, Y4, and Y5. Both outputsupplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.
The CDCE706 is characterized for operation from – 40 ° C to 85 ° C.
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PLL1
XO
or
2LVCMOS
or
Differential
Input
MUX
MUX
PLL3
PFD
Filter
VCO
PLL2
w/SSC
PFD
Filter
VCO
S0/A0/CLK_SEL
S1/A1
SCLOCK
OutputSwitchMatrix
LV
CMOS
LV
CMOS
EEPROM
LOGIC
SMBUS
LOGIC PFD
Filter
VCO
SDATA
Y0
Y1
VCO1Bypass
VCO2Bypass
VCO3Bypass
MUX
6Programmable7-BitDividers:P0,P1,P2,P3,P4,P5,andInversionLogic
5x6ProgrammableSwitch A
PLL Bypass
VCC GND VCCOUT1
GND VCCOUT2
Prg. 9-Bit
DividerM
Prg.12-Bit
DividerN
Prg.9-Bit
DividerM
Prg.12-Bit
DividerN
Prg.9-Bit
DividerM
Prg.12-Bit
DividerN
Crystalor
ClockInput
CLK_IN1
FactoryPrg.
CLK_IN0
6x6ProgrammableSwitchB
LV
CMOS
LV
CMOS
Y2
Y3
LV
CMOS
LV
CMOS
Y4
Y5
SSC
On/Off
B0334-01
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
FUNCTIONAL BLOCK DIAGRAM
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5x6-Switch A
InputCLK
(PLL Bypass)
PLL1
PLL3
6x6-SwitchB
7-BitDivider
Y0
Y1
Y2
Y3
Y4
Y5
P0
P1
P2
P3
P4
P5
Programming
PLL2
Non-SSC
PLL2
w/SSC
B0335-01
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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OUTPUT SWITCH MATRIX
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONTSSOP20NAME
NO.
Dependent on SMBus settings, CLK_IN0 is the crystal-oscillator input and can also be used as anCLK_IN0 5 I
LVCMOS input or as positive differential signal inputs.Depending on SMBus settings, CLK_IN1 serves as the crystal oscillator output or can be theCLK_IN1 6 I/O
second LVCMOS input or the negative differential signal input.GND 4, 8, 13, 17 Ground Ground
User-programmable control input S0 (PLL bypass or power-down mode) or A0 (address bit 0), orS0, A0,
1 I CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOSCLK_SEL
inputs; internal pullup 150 k Ω
User-programmable control input S1 (output enable/disable or all output low), A1 (address bit 1),S1, A1 2 I
dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 k Ω
SCLOCK 10 I Serial control clock input for SMBus controller; LVCMOS inputSDATA 9 I/O Serial control data input/output for SMBus controller; LVCMOS inputV
CC
3, 7 Power 3.3-V power supply for the deviceV
CCOUT1
14 Power Power supply for outputs Y0, Y1V
CCOUT2
18 Power Power supply for outputs Y2, Y3, Y4, Y511, 12, 15,Y0 to Y5 O LVCMOS outputs16, 19, 20
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ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL RESISTANCE
RECOMMENDED OPERATING CONDITIONS
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage range – 0.5 to 4.6 VV
I
Input voltage range
(2)
– 0.5 to V
CC
+ 0.5 VV
O
Output voltage range
(2)
– 0.5 to V
CC
+ 0.5 VI
I
Input current (V
I
< 0, V
I
> V
CC
) ± 20 mAI
O
Continuous output current ± 50 mAT
stg
Storage temperature range – 65 to 150 ° CT
J
Maximum junction temperature 125 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
for TSSOP20 (PW) Package
(1)
PARAMETER AIRFLOW (LFM) AIRFLOW (m/s) ° C/W
0 0 66.3150 0.762 59.3θ
JA
Thermal resistance, junction-to-ambient
250 1.27 56.3500 2.54 51.9θ
JC
Thermal resistance, junction-to-case 19.7
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Device supply voltage 3 3.3 3.6 VV
CCOUT1
(1)
Output Y0, Y1 supply voltage 2.3 3.6 VV
CCOUT2
(1)
Output Y2, Y3, Y4, Y5 supply voltage 2.3 3.6 VV
IL
Low-level input voltage, LVCMOS 0.3 V
CC
VV
IH
High-level input voltage, LVCMOS 0.7 V
CC
VV
Ithresh
Input voltage threshold, LVCMOS 0.5 V
CC
VV
I
Input voltage range, LVCMOS 0 3.6 V|V
ID
| Differential input voltage 0.1 VV
IC
Common-mode for differential input voltage 0.2 V
CC
– 0.6 VI
OH
/I
OL
Output current (3.3 V) ± 6 mAI
OH
/I
OL
Output current (2.5 V) ± 4 mAC
L
Output load, LVCMOS 25 pFT
A
Operating free-air temperature – 40 85 ° C
(1) The minimum output voltage can be down to 1.8 V. See the CDCx706/x906 Termination and Signal Integrity Guidelines applicationreport (SCAA080 ) for more information.
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RECOMMENDED CRYSTAL SPECIFICATIONS
EEPROM SPECIFICATION
TIMING REQUIREMENTS
DEVICE CHARACTERISTICS
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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MIN NOM MAX UNIT
f
Xtal
Crystal input frequency range (fundamental mode) 8 27 54 MHzESR Effective series resistance
(1) (2)
15 60 Ω
C
IN
Input capacitance CLK_IN0 and CLK_IN1 3 pF
(1) For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50 Ωto assure stable start-up condition.(2) For maximum power handling (drive level), see Figure 15 .
MIN TYP MAX UNIT
EEcyc Programming cycles of EEPROM 100 1000 CyclesEEret Data retention 10 Years
over recommended ranges of supply voltage, load, and operating-free air temperature
MIN NOM MAX UNIT
CLK_IN REQUIREMENTS
PLL mode 1 200f
CLK_IN
CLK_IN clock input frequency (LVCMOS or differential) MHzPLL bypass mode 0 200t
r
/t
f
Rise and fall time, CLK_IN signal (20% to 80%) 4 nsduty
REF
Duty cycle, CLK_IN at V
CC
/2 40% 60%
SMBus TIMING REQUIREMENTS (see Figure 11 )
f
SCLK
SCLK frequency 100 kHzt
h(START)
START hold time 4 µst
w(SCLL)
SCLK low-pulse duration 4.7 µst
w(SCLH)
SCLK high-pulse duration 4 50 µst
su(START)
START setup time 0.6 µst
h(SDATA)
SDATA hold time 0.3 µst
su(SDATA)
SDATA setup time 0.25 µst
r(SDATA)
/
SCLK/SDATA input rise time 1000 nst
r(SM)
t
f(SDATA)
/
SCLK/SDATA input fall time 300 nst
f(SM)
t
su(STOP)
STOP setup time 4 µst
(BUS)
Bus free time 4.7 µst
(POR)
Time in which the device must be operational after power-on reset 500 ms
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
OVERALL PARAMETER
All PLLs on, all outputs on,I
CC
Supply current
(2)
f
OUT
= 80 MHz, f
CLK_IN
= 27 MHz, 90 115 mAf
VCO
= 160 MHzEvery circuit powered down except SMBus,I
CCPD
Power-down current 50 µAf
IN
= 0 MHz, V
CC
= 3.6 VSupply voltage V
CC
threshold for power-upV
PUC
2.1 Vcontrol circuit
(1) All typical values are at nominal V
CC
.(2) For calculating total supply current, add the current from Figure 2 ,Figure 3 , and Figure 4 . Using the high-speed mode of the VCOreduces the current consumption. See Figure 3 .
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
DEVICE CHARACTERISTICS (continued)over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
All PLLs 80 200Normal speed-mode
(3)VCO frequency of internal PLL (any of threef
VCO
PLL2 with SSC 80 167 MHzPLLs)
High-speed mode
(3)
180 300V
CC
= 2.5 V 250LVCMOS output frequency range
(4)
, Seef
OUT
MHzFigure 4
V
CC
= 3.3 V 300
LVCMOS PARAMETER
V
IK
LVCMOS input voltage V
CC
= 3 V, I
I
= – 18 mA – 1.2 VLVCMOS input current (CLK_IN0 andI
I
V
I
= 0 V or V
CC
, V
CC
= 3.6 V ± 5 µACLK_IN1)
I
IH
LVCMOS input current (S1/S0) V
I
= V
CC
, V
CC
= 3.6 V 5 µAI
IL
LVCMOS input current (S1/S0) V
I
= 0 V, V
CC
= 3.6 V – 35 – 10 µAInput capacitance at CLK_IN0 andC
I
V
I
= 0 V or V
CC
3 pFCLK_IN1
LVCMOS PARAMETER FOR V
CCOUT
= 3.3-V Mode
V
CCOUT
= 3 V, I
OH
= – 0.1 mA 2.9V
OH
LVCMOS high-level output voltage V
CCOUT
= 3 V, I
OH
= – 4 mA 2.4 VV
CCOUT
= 3 V, I
OH
= – 6 mA 2.1V
CCOUT
= 3 V, I
OL
= 0.1 mA 0.1V
OL
LVCMOS low-level output voltage V
CCOUT
= 3 V, I
OL
= 4 mA 0.5 VV
CCOUT
= 3 V, I
OL
= 6 mA 0.85All PLL bypass 9t
PLH
,
Propagation delay nst
PHL
VCO bypass 11t
r0
/t
f0
Rise and fall time for output slew rate 0 V
CCOUT
= 3.3 V (20% – 80%) 1.7 3.3 4.8 nst
r1
/t
f1
Rise and fall time for output slew rate 1 V
CCOUT
= 3.3 V (20% – 80%) 1.5 2.5 3.2 nst
r2
/t
f2
Rise and fall time for output slew rate 2 V
CCOUT
= 3.3 V (20% – 80%) 1.2 1.6 2.1 nsRise and fall time for output slew rate 3t
r3
/t
f3
V
CCOUT
= 3.3 V (20% – 80%) 0.4 0.6 1 ns(default configuration)
f
OUT
= 50 MHz 55 901 PLL, 1 output
f
OUT
= 245.76 MHz 45 80t
jit(cc)
Cycle-to-cycle jitter
(5) (6)
psf
OUT
= 50 MHz 125 1553 PLLs, 3 outputs
f
OUT
= 245.76 MHz 60 95f
OUT
= 50 MHz 60 901 PLL, 1 output
f
OUT
= 245.76 MHz 55 80t
jit(per)
Peak-to-peak period jitter
(5) (6)
psf
OUT
= 50 MHz 145 1803 PLLs, 3 outputs
f
OUT
= 245.76 MHz 70 1051.6-ns rise/fall time at f
VCO
= 150 MHz,t
sk(o)
Output skew (see
(7)
and Table 5 ) 200 psPdiv = 3odc Output duty cycle
(8)
f
VCO
= 100 MHz, Pdiv = 1 45% 55%
(3) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in byte 6, bits [7:5]. The minimum f
VCOcan be lower, but impacts jitter performance.(4) Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).(5) 50,000 cycles(6) Jitter depends on configuration. Jitter data is normal t
r
/t
f
, input frequency = 3.84 MHz, f
VCO
= 245.76 MHz.(7) The t
sk(o)
specification is only valid for equal loading of all outputs.(8) odc depends on output rise and fall time (t
r
/t
f
). The data is for normal t
r
/t
f
and is valid for both SSC on and off.
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DEVICE CHARACTERISTICS (continued)over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVCMOS PARAMETER FOR V
CCOUT
= 2.5-V Mode
(9)
V
CCOUT
= 2.3 V, I
OH
= 0.1 mA 2.2V
OH
LVCMOS high-level output voltage V
CCOUT
= 2.3 V, I
OH
= – 3 mA 1.7 VV
CCOUT
= 2.3 V, I
OH
= – 4 mA 1.5V
CCOUT
= 2.3 V, I
OL
= 0.1 mA 0.1V
OL
LVCMOS low-level output voltage V
CCOUT
= 2.3 V, I
OL
= 3 mA 0.5 VV
CCOUT
= 2.3 V, I
OL
= 4 mA 0.85All PLL bypass 9t
PLH
,
Propagation delay nst
PHL
VCO bypass 11t
r0
/t
f0
Rise and fall time for output slew rate 0 V
CCOUT
= 2.5 V (20% – 80%) 2 3.9 5.6 nst
r1
/t
f1
Rise and fall time for output slew rate 1 V
CCOUT
= 2.5 V (20% – 80%) 1.8 2.9 4.4 nst
r2
/t
f2
Rise and fall time for output slew rate 2 V
CCOUT
= 2.5 V (20% – 80%) 1.3 2 3.2 nsRise and fall time for output slew rate 3t
r3
/t
f3
V
CCOUT
= 2.5 V (20% – 80%) 0.4 0.8 1.1 ns(default configuration)
f
OUT
= 50 MHz 60 1051 PLL, 1 output
f
OUT
= 245.76 MHz 50 85t
jit(cc)
Cycle-to-cycle jitter
(10) (11)
psf
OUT
= 50 MHz 130 1603 PLLs, 3 outputs
f
OUT
= 245.76 MHz 60 95f
OUT
= 50 MHz 65 1101 PLL, 1 output
f
OUT
= 245.76 MHz 60 90t
jit(per)
Peak-to-peak period jitter
(10) (11)
psf
OUT
= 50 MHz 145 1803 PLLs, 3 outputs
f
OUT
= 245.76 MHz 70 105t
sk(o)
Output skew (see
(12)
and Table 5 ) 2-ns rise/fall time at f
VCO
= 150 MHz, Pdiv = 3 250 psodc Output duty cycle
(13)
f
VCO
= 100 MHz, Pdiv = 1 45% 55%
SMBus PARAMETER
V
IK
SCLK and SDATA input clamp voltage V
CC
= 3 V, I
I
= – 18 mA – 1.2 VI
LK
SCLK and SDATA input current V
I
= 0 V or V
CC
, V
CC
= 3.6 V ± 5 µAV
IH
SCLK input, high voltage 2.1 VV
IL
SCLK input, low voltage 0.8 VV
OL
SDATA low-level output voltage I
OL
= 4 mA, V
CC
= 3 V 0.4 VInput capacitance at SCLK V
I
= 0 V or V
CC
3 10 pFC
I
Input capacitance at SDATA V
I
= 0 V or V
CC
3 10 pF
(9) There is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see the CDCx706/x906 Termination andSignal Integrity Guidelines application report, SCAA080 .(10) 50,000 cycles(11) Jitter depends on configuration. Jitter data is normal t
r
/t
f
, input frequency = 3.84 MHz, f
VCO
= 245.76 MHz.(12) The t
sk(o)
specification is only valid for equal loading of all outputs.(13) odc depends on output rise and fall time (t
r
/t
f
). The data is for normal t
r
/t
f
and is valid for both SSC on and off.
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PARAMETER MEASUREMENT INFORMATION
Yn
1kW
1kW10pF
LVCMOS
CDCE706
S0375-01
TYPICAL CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
110
120
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210
fVCO − VCO Frequency − MHz G001
ICC − Supply Current − mA
VCC = 3.3 V
M div = 1
N div = 2
P div = 1
VCO Normal-Speed Mode
PLL1 + PLL2 SSC + PLL3
PLL1 + PLL2 + PLL3
PLL1 + PLL2
PLL1
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Figure 1. Test Load
Figure 2. I
CC
vs Number of PLLs and VCO Frequency (VCO at Normal-Speed Mode, Byte 6 Bits [7:5])
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0
10
20
30
40
50
60
70
80
90
100
110
120
130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310
fVCO − VCO Frequency − MHz G002
ICC − Supply Current − mA
VCC = 3.3 V
M div = 1
N div = 2
P div = 1
VCO High-Speed Mode
PLL1 + PLL2 SSC + PLL3
PLL1 + PLL2 + PLL3
PLL1 + PLL2
PLL1
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
fVCO − VCO Frequency − MHz G003
VCC = 3.3 V
M div = 1
N div = 2
P div = 1
ICC − Supply Current − mA
6 Outputs
5 Outputs
4 Outputs
3 Outputs
2 Outputs
1 Output
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
Figure 3. I
CC
vs Number of PLLs and VCO Frequency (VCO at High-Speed Mode, Byte 6 Bits [7:5])
Figure 4. I
CCOUT
vs Number of Outputs and VCO Frequency
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0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420
fOUT − Output Frequency − MHz G004
VCC = 3.3 V
M div = 4
N div = 15
P div = 1
VOUT − Output Voltage − V
VOH at VCCOUT = 3.6 V
VOH at VCCOUT = 2.3 V
VOL at VCCOUT = 2.3 V VOL at VCCOUT = 3.6 V
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Figure 5. Output Swing vs Output Frequency
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APPLICATION INFORMATION
SMBus Data Interface
Data Protocol
Slave Receiver Address (7 bits)
CDCE706
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To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It followsthe SMBus specification Version 2.0, which is based on the principles of operation of I
2
C. More details of theSMBus specification can be found at http://www.smbus.org .
Through the SMBus, various device functions, such as individual clock output buffers, can be individuallyenabled or disabled. The registers associated with the SMBus data interface initialize to their default setting onpower up; therefore, using this interface is optional. The clock device register changes are normally made onsystem initialization, if any are required.
The clock-driver serial protocol accepts byte-write, byte-read, block-write, and block-read operations from thecontroller.
For block-write/read operations, the bytes must be accessed in sequential order from lowest to highest byte(most significant bit first) with the ability to stop after any complete byte has been transferred. For byte-write andbyte-read operations, the system controller can access individually addressed bytes.
Once a byte has been sent, it is written into the internal register and becomes effective immediately after therising edge of the ACK bit. This applies to each transferred byte, independently of whether this is a byte-write ora block-write sequence.
If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM.During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programmingsequence is completed. Data, however, can be read out during the programming sequence (byte read or blockread). The programming status can be monitored by EEPIP, byte 24 bit 7.
The offset of the indexed byte is encoded in the command code, as described in Table 1 .
The block-write and block-read protocol is outlined in Figure 9 and Figure 10 , whereas Figure 7 and Figure 8outline the corresponding byte-write and byte-read protocol.
A6 A5 A4 A3 A2 A1
(1)
A0
(1)
R/W11010010(1) Address bits A0 and A1 are programmable by the configuration inputs S0 and S1 (byte 10 bits [1:0] and bits [3:2]. This allowsaddressing up to four devices connected to the same SMBus.
Table 1. Command Code Definition
Bits Description
7 0 = Block-read or block-write operation1 = Byte-read or byte-write operation6 – 0 Byte offset for read and write operations
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M0053-01
171 1 81 1
S
S
Slave Address Wr A DataByte A P
StartCondition
Sr RepeatedStartCondition
Rd Read(BitValue=1)
Wr Write(BitValue=0)
AAcknowledge(ACK=0andNACK=1)
PStopCondition
PE PacketError
Master-to-Slave Transmission
Slave-to-Master Transmission
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Figure 6. Generic Programming Sequence
Byte-Write Programming Sequence
1 7 1 1 8 1 8 1 1S Slave Address Wr A CommandCode A Data Byte A P
Figure 7. Byte-Write Protocol
Byte-Read Programming Sequence
1 7 1 1 8 1 1 7 1 1S Slave Address Wr A CommandCode A S Slave Address Rd A
8 1 1
Data Byte A/NA PAcknowledge/Not Acknowledge
Figure 8. Byte-Read Protocol
Block-Write Programming Sequence
(1)
1 7 1 1 8 1 8 1
S Slave Address Wr A CommandCode A Byte Count N A
8 1 8 1 8 1 1
Data Byte 0 A Data Byte 1 A - - - - - Data Byte N – 1 A P
(1) Data Byte 0 is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it otherthan 0000 0001.
Figure 9. Block-Write Protocol
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SMBus Hardware Interface
9
10
SDATA
SCLK
SMBHost
CDCE706
CBUS CBUS
RPRP
S0376-01
CDCE706
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Block-Read Programming Sequence
1 7 1 1 8 1 1 7 1 1S Slave Address Wr A CommandCode A Sr Slave Address Rd A
8181 811
Byte Count N A Data Byte 0 A - - - - - Data Byte N – 1 NA P
Figure 10. Block-Read Protocol
Figure 11. Timing Diagram, Serial Control Interface
Figure 12 shows how the CDCE706 clock synthesizer is connected to the SMBus. Note that the current throughthe pullup resistors (R
p
) must meet the SMBus specifications (minimum 100 µA, maximum 350 µA). If theCDCE706 is not connected to the SMBus, the SDATA and SCLK inputs must be connected with 10-k Ωresistorsto V
CC
to avoid floating input conditions.
Figure 12. SMBus Hardware Interface
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Default Device Setting
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Table 2. Register Configuration Command Bitmap
Adr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Byte 0 Revision Code Vendor IdentificationByte 1 PLL1 Reference Divider M 9-Bit [7:0]Byte 2 PLL1 Feedback Divider N 12-Bit [7:0]Byte 3 PLL1 Mux PLL2 Mux PLL3 Mux PLL1 Feedback Divider N 12-Bit [11:8] PLL1 RefDiv M [8]Byte 4 PLL2 Reference Divider M 9-Bit [7:0]Byte 5 PLL2 Feedback Divider N 12-Bit [7:0]Byte 6 PLL1 f
VCO
PLL2 f
VCO
PLL3 f
VCO
PLL2 Feedback Divider N 12-Bit [11:8] PLL2 RefSelection Selection Selection Div M [8]Byte 7 PLL3 Reference Divider 9-Bit M [7:0]Byte 8 PLL3 Feedback Divider N [12-Bit 7:0]Byte 9 PLL Selection for P0 (Switch A) PLL3 Feedback Divider N 12-Bit [11:8] PLL3 RefDiv M [8]Byte 10 PLL Selection for P1 (Switch A) Inp. Clock Configuration Inputs S1 Configuration Inputs S0SelectionByte 11 Input Signal Source PLL Selection for P3 (Switch A) PLL Selection for P2 (Switch A)Byte 12 Reserved Power Down PLL Selection for P5 (Switch A) PLL Selection for P4 (Switch A)Byte 13 Reserved 7-Bit Divider P0 [6:0]Byte 14 Reserved 7-Bit Divider P1 [6:0]Byte 15 Reserved 7-Bit Divider P2 [6:0]Byte 16 Reserved 7-Bit Divider P3 [6:0]Byte 17 Reserved 7-Bit Divider P4 [6:0]Byte 18 Reserved 7-Bit Divider P5 [6:0]Byte 19 Reserved Y0 Inv. or Non-Inv Y0 Slew-Rate Control Y0 Enable or Y0 Divider Selection (Switch B)LowByte 20 Reserved Y1 Inv. or Non-Inv Y1 Slew-Rate Control Y1 Enable or Y1 Divider Selection (Switch B)LowByte 21 Reserved Y2 Inv. or Non-Inv Y2 Slew-Rate Control Y2 Enable or Y2 Divider Selection (Switch B)LowByte 22 Reserved Y3 Inv. or Non-Inv Y3 Slew-Rate Control Y3 Enable or Y3 Divider Selection (Switch B)LowByte 23 Reserved Y4 Inv. or Non-Inv Y4 Slew-Rate Control Y4 Enable or Y4 Divider Selection (Switch B)LowByte 24 EEPIP [read only] Y5 Inv or Non-Inv Y5 Slew-Rate Control Y5 Enable or Y5 Divider Selection (Switch B)LowByte 25 EELOCK SSC Modulation Selection Frequency Selection for SSCByte 26 EEWRITE 7-Bit Byte Count
The internal EEPROM of the CDCE706 is preprogrammed with a factory-default configuration as shown inFigure 13 . This puts the device in an operating mode without the need to program it first. The default settingappears after power is switched on or after a power-down/up sequence until it is reprogrammed by the user to adifferent application configuration. A new register setting is programmed via the serial SMBus Interface.
A different default setting can be programmed on customer request. Contact a Texas Instruments Sales andMarketing representative for more information.
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PLL1
XO
or
2LVCMOS
or
Differential
Input
MUX
MUX
PLL3
PFD
Filter
VCO
PLL2
w/SSC
PFD
Filter
VCO
S0/CLK_SEL
S1
SCLOCK
OutputSwitchMatrix
LV
CMOS
LV
CMOS
EEPROM
LOGIC
SMBUS
LOGIC PFD
Filter
VCO
SDATA
Y0
Y1
f =225.792MHz
VCO3
f =250MHz
VCO2
f =216MHz
VCO1
MUX
P0-Div
10
DividerN
8
DividerM
27
DividerN
250
DividerM
375
DividerN
3136
27-MHz
Crystal
CLK_IN1
CLK_IN0
LV
CMOS
LV
CMOS
Y2
Y3
LV
CMOS
LV
CMOS
Y4
Y5
SSC
Off
B0336-01
14pF
14pF
P1-Div
20
P3-Div
9
P4-Div
32
P5-Div
427MHz
27MHz
27MHz
27MHz
27MHz
27MHz
DividerM
1
P2-Div
8
in
out out
f N 27 MHz 8
f , i.e., f 27 MHz
M P (1 8)
´´
= = =
´ ´
(1)
CDCE706
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NOTE: All outputs are enabled and in noninverting mode. S0, S1, and SSC comply according the default setting described inbyte 10 and byte 25.
Figure 13. Default Device Setting
The output frequency can be calculated:
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Functional Description of the Logic
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All bytes are readable/writeable, unless otherwise expressly mentioned.Byte 0 (Read-Only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4]
(1)
Revision Code Vendor Identification
X X X X 0 0 0 1
(1) Byte 0 is only readable by the byte-read instruction (see Figure 8 ).
Bytes 1 to 9: Reference Divider M of PLL1, PLL2, PLL3
(1)
M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by Default
(2) (3)
0 0 0 0 0 0 0 0 0 Not allowed000000001 1000000010 2000000011 3•
•
•1 1 1 1 1 1 1 0 1 5091 1 1 1 1 1 1 1 0 5101 1 1 1 1 1 1 1 1 511
(1) By selecting the PLL divider factors, M ≤N and 80 MHz ≤f
VCO
≤300 MHz.(2) Unless customer-specific setting(3) Default setting of divider M for PLL1 = 1, for PLL2 = 27, and for PLL3 = 375.
Bytes 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3
(1)
N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 Div by Default
(2) (3)
0 0 0 0 0 0 0 0 0 0 0 0 Not allowed000000000001 1000000000010 2000000000011 3•
•
•1 1 1 1 1 1 1 1 1 1 0 1 40931 1 1 1 1 1 1 1 1 1 1 0 40941 1 1 1 1 1 1 1 1 1 1 1 4095
(1) By selecting the PLL divider factors, M ≤N and 80 MHz ≤f
VCO
≤300 MHz.(2) Unless customer-specific setting(3) Default setting of divider N for PLL1 = 8, for PLL2 = 250, and for PLL3 = 3136.
Byte 3 Bits [7:5]: PLL (VCO) Bypass Multiplexer
PLLxMUX PLL (VCO) MUX Output Default
(1)
0 PLLx Yes1 VCO bypass
(1) Unless customer-specific setting
Byte 6 Bits [7:5]: VCO Frequency Selection Mode for Each PLL
(1)
PLLxFVCO VCO Frequency Range Default
(2)
0 80 MHz – 200 MHz1 180 MHz – 300 MHz Yes
(1) This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2, or PLL3. At power up, thehigh-speed mode is selected, f
VCO
is 180 MHz – 300 MHz. In case of a higher f
VCO
, this bit must be set to 1.(2) Unless customer-specific setting
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Bytes 9 to 12: Output Switch Matrix (5 × 6 Switch A) PLL Selection for P-Divider P0 – P5
SWAPx2 SWAPx1 SWAPx0 Any Output Px Default
(1)
0 0 0 PLL bypass (input clock)0 0 1 PLL1 P2, P3, P4, P50 1 0 PLL2 non-SSC P00 1 1 PLL2 with SSC
(2)
1 0 0 PLL3 P11 0 1 Reserved1 1 0 Reserved1 1 1 Reserved
(1) Unless customer-specific setting(2) PLL2 has an SSC output and a non-SSC output. If SSC bypass is selected (see byte 25, bits [6:4]), the SSC circuitry of PLL2 ispowered down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.
Byte 10, Bits [1:0]: Configuration Settings of Input S0/A0/CLK_SEL
S01 S00 Function Default
(1)
If S0 is low, the PLLs and the clock-input stage go into power-down mode, outputs are in the Yes0 0 high-impedance state, all actual register settings are maintained, SMBus stays active. If S0 is high,then the device is powered on and outputs are active.
(2)
If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power down,all outputs are active (inv. or non-inv.), actual register settings are maintained, SMBus stays0 1
active; this mode is useful for production test. If S0 is high, then the device is powered on andoutputs are active.CLK_SEL (input clock selection — overwrites the CLK_SEL setting in byte 10, bit [4])
(3)
1 0 — CLK_SEL when set low selects CLK_IN_IN0.— CLK_SEL when set high selects CLK_IN_IN1.In this mode, the control input S0 is interpreted as address bit A0 of the slave receiver address1 1
byte
(4)
.
(1) Unless customer-specific setting(2) Power-down mode overwrites the high-impedance state or low state of the S1 setting in byte 10, bits [3:2].(3) If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (byte 11, bits [7:6]), then this setting is notrelevant.
(4) To use this pin as slave receiver address bit A0, an initialization pattern must be sent to the CDCE706. When S00/S01 is set to 1, theS0 input pin is interpreted in the next read or write cycle as address bit A0 of the slave receiver address byte. Note that right afterbyte 10 (S00/S01) has been written, A0 (via the S0-pin) is immediately active (also when byte 10 is sent within a block-write sequence).After the initialization, each CDCE706 has its own S0-dependent slave receiver address and can be addressed according to its newvalid address.
Byte 10, Bits [3:2]: Configuration Settings of Input S1/A1
S11 S10 Function Default
(1)
If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.). If S1 is high, then all Yes0 0
the outputs are active.If S1 is set low, all outputs are switched to a high-impedance state. If S1 is high, then all the outputs are0 1
active.1 0 Reserved1 1 In this mode, control input S1 is interpreted as address bit A1 of the slave receiver address byte.
(2)
(1) Unless customer-specific setting(2) To use this pin as slave-receiver address bit A1, an initialization pattern must be sent to the CDCE706. When S10/S11 is set to be 1,the S1 input pin is interpreted in the next read or write cycle as address bit A1 of the slave receiver address byte. Note that right afterbyte 10 (S10/S11) has been written, A1 (via the S1-pin) is immediately active (also when byte 10 is sent within a block-write sequence).After the initialization, each CDCE706 has its own S1-dependent slave receiver address and can be addressed according to its newvalid address.
Byte 10, Bit [4]: Input Clock Selection
(1)
CLKSEL Input Clock Default
(2)
0 CLK_IN0 Yes1 CLK_IN1
(1) This bit is not relevant if crystal input or differential clock input is selected, byte 11, bits [7:6].(2) Unless customer-specific setting
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Byte 11, Bits [7:6]: Input Signal Source
(1)
IS1 IS0 Function Default
(2)
0 0 CLK_IN0 is the crystal oscillator input, and CLK_IN1 serves as the crystal oscillator output. YesCLK_IN0 and CLK_IN1 are two LVCMOS inputs. CLK_IN0 or CLK_IN1 is selectable via the CLK_SEL0 1
control pin.1 0 CLK_IN0 and CLK_IN1 serve as differential signal inputs.1 1 Reserved
(1) In case the crystal input or differential clock input is selected, the input clock selection, byte 10, bit [4], is not relevant.(2) Unless customer-specific setting
Byte 12, Bit [6]: Power-Down Mode (Except SMBus)
PD Power-Down Mode Default
(1)
0 Normal device operation Yes1 Power down
(2)
(1) Unless customer-specific setting(2) In power down, all PLLs and the clock-input stage go into power-down mode, all outputs are in the high-impedance state, all actualregister settings are maintained, and the SMBus stays active. The power-down mode overwrites the high-impedance state or low stateof the S0 and S1 settings in byte 10.
Bytes 13 to 18, Bit [6:0]: Outputs Switch Matrix 6 × 7-Bit Divider P0 – P5
DIVYx6 DIVYx5 DIVYx4 DIVYx3 DIVYx2 DIVYx1 DIVYx0 Div by Default
(1) (2)
0 0 0 0 0 0 0 Not allowed0000001 10000010 2•
•
•1111101 1251111110 1261111111 127
(1) Unless customer-specific setting(2) Default settings of divider P0 = 10, P1 = 20, P2 = 8, P3 = 9, P4 = 32, and P5 = 4.
Bytes 19 to 24, Bits [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0 – Y5
SRCYx1 SRCYx0 Yx Default
(1)
0 0 Nominal +3 ns (t
r0
/t
f0
)0 1 Nominal +2 ns (t
r1
/t
f1
)1 0 Nominal +1 ns (t
r2
/t
f2
)1 1 Nominal (t
r3
/t
f3
) Yes
(1) Unless customer-specific setting
Bytes 19 to 24, Bits [2:0]: Outputs Switch Matrix (6 × 6 Switch B) Divider (P0 – P5) Selection for Outputs Y0 – Y5
SWBYx2 SWBYx1 SWBYx0 Any Output Yx Default
(1)
0 0 0 Divider P00 0 1 Divider P10 1 0 Divider P2 Y0, Y1, Y2, Y3, Y4, Y50 1 1 Divider P31 0 0 Divider P41 0 1 Divider P51 1 0 Reserved1 1 1 Reserved
(1) Unless customer-specific setting
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Bytes 19 to 24, Bit [3]: Output Y0 – Y5 Enable or Low-State
ENDISYx Output Yx Default
(1)
0 Disable to low1 Enable Yes
(1) Unless customer-specific setting
Bytes 19 to 24, Bit [6]: Output Y0 – Y5 Noninverting/Inverting
INVYx Output Yx Status Default
(1)
0 Noninverting Yes1 Inverting
(1) Unless customer-specific setting
Byte 24, Bit [7] (Read-Only): EEPROM Programming In Process Status
(1)
EEPIP Indicate EEPROM Write Process Default
0 No programming1 Programming in process
(1) This read-only bit indicates an EEPROM write process. It is set to high if programming starts and resets to low if programming iscompleted. Any data written to the EEPIP bit is ignored. During programming, no data are allowed to be sent to the device via theSMBus until the programming sequence is completed. Data, however, can be read out during the programming sequence (byte read orblock read).
Byte 25, Bits [3:0]: SSC Modulation Frequency Selection in the Range of 30 kHz to 60 kHz
(1)
f
vco
(MHz)ModulationFSSC3 FSSC2 FSSC1 FSSC0 Default
(2)Factor
100 110 120 130 140 150 160 167
0 0 0 0 5680 f
mod
17.6 19.4 21.1 22.9 24.6 26.4 28.2 29.4[kHz]0 0 0 1 5412 18.5 20.3 22.2 24.0 25.9 27.7 29.6 30.9
0 0 1 0 5144 19.4 21.4 23.3 25.3 27.2 29.2 31.1 32.5
0 0 1 1 4876 20.5 22.6 24.6 26.7 28.7 30.8 32.8 34.2
0 1 0 0 4608 21.7 23.9 26.0 28.2 30.4 32.6 34.7 36.2
0 1 0 1 4340 23.0 25.3 27.6 30.0 32.3 34.6 36.9 38.5
0 1 1 0 4072 24.6 27.0 29.5 31.9 34.4 36.8 39.3 41.0
0 1 1 1 3804 26.3 28.9 31.5 34.2 36.8 39.4 42.1 43.9
1 0 0 0 3536 28.3 31.1 33.9 36.8 39.6 42.4 45.2 47.2
1 0 0 1 3286 30.4 33.5 36.5 39.6 42.6 45.6 48.7 50.8 Yes
1 0 1 0 3000 33.3 36.7 40.0 43.3 46.7 50.0 53.3 55.7
1 0 1 1 2732 36.6 40.3 43.9 47.6 51.2 54.9 58.6 61.1
1 1 0 0 2464 40.6 44.6 48.7 52.8 56.8 60.9 64.9 67.8
1 1 0 1 2196 45.5 50.1 54.6 59.2 63.8 68.3 72.9 76.0
1 1 1 0 1928 51.9 57.1 62.2 67.4 72.6 77.8 83.0 86.6
1 1 1 1 1660 60.2 66.3 72.3 78.3 84.3 90.4 96.4 100.6
(1) The PLL must be bypassed (turned off) when changing the SSC Modulation Frequency Factor on-the-fly. This can be done by thefollowing programming sequence: bypass PLL2 (byte 3, bit 6 = 1); write new Modulation Factor (byte 25); re-activate PLL2 (byte 3,bit 6 = 0).(2) Unless customer-specific setting
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Byte 25, Bits [6:4]: SSC Modulation Amount
(1)
SSC2 SSC1 SSC0 Function Default
(2)
0 0 0 SSC modulation amount 0% = SSC bypass for PLL
(3)
Yes0 0 1 SSC modulation amount ± 0.1% (center spread)0 1 0 SSC modulation amount ± 0.25% (center spread)0 1 1 SSC modulation amount ± 0.4% (center spread)1 0 0 SSC modulation amount 1% (down spread)1 0 1 SSC modulation amount 1.5% (down spread)1 1 0 SSC modulation amount 2% (down spread)1 1 1 SSC modulation amount 3% (down spread)
(1) The PLL must be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by the followingprogramming sequence: bypass PLL2 (byte 3, bit 6 = 1); write new Modulation Amount (byte 25); re-activate PLL2 (byte 3, bit 6 = 0).(2) Unless customer-specific setting(3) If SSC bypass is selected, the SSC circuitry of PLL2 is powered down and the SSC output is reset to logic low. The non-SSC output ofPLL2 is not affected by this mode and can still be used.
Byte 25, Bit [7]: Permanently Lock EEPROM Data
EELOCK Permanently Lock EEPROM
(1)
Default
(2)
0 No Yes1 Yes
(1) If this bit is set, the actual data in the EEPROM is permanently locked. Note that the EEPROM lock becomes effective when this bit isset in the EEPROM and not in the internal volatile register. No further programming is possible, even if this bit is set low. Data, howevercan still be written via SMBUS to the internal register to change device function on the fly. But new data no longer can be stored into theEEPROM.
(2) Unless customer-specific setting
Byte 26, Bits [6:0]: Byte Count
(1)
BC6 BC5 BC4 BC3 BC2 BC1 BC0 No. of Bytes Default
(2)
0 0 0 0 0 0 0 Not allowed0000001 10000010 20000011 3•
•
•0 0 1 1 0 1 1 27 Yes•
•
•1111101 1251111110 1261111111 127
(1) Defines the number of bytes, which is sent from this device at the next block-read protocol.(2) Unless customer-specific setting
Byte 26, Bit [7]: Initiate EEPROM Write Cycle
(1)
EEWRITE Starts EEPROM Write Cycle Default
(2)
0 No Yes1 Yes
(1) The EEPROM WRITE cycle is initiated with the rising edge of the EEWRITE bit. The EEPROM WRITE bit must be sent last to ensurethat the content of all internal registers is stored in the EEPROM. Do not interrupt the EEPROM WRITE cycle; otherwise, random datacan be stored in the EEPROM. A static level-high does not trigger an EEPROM WRITE cycle. This bit stays high until the user resets itto low (it is not automatically reset after the programming has been completed). Therefore, to initiate an EEPROM WRITE cycle, it isrecommended to send a zero-one sequence to the EEWRITE bit in byte 26.During EEPROM programming, no data are allowed to be sent to the device via the SMBus until the programming sequence has beencompleted. Data, however, can be read out during the programming sequence (byte read or block read). The programming status canbe monitored by reading out EEPIP, byte 24, bit 7. If EELOCK is set, no EEPROM programming is possible.(2) Unless customer-specific setting
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FUNCTIONAL DESCRIPTION
Clock Inputs (CLK_IN0 and CLK_IN1)
XO
or
2LVCMOS
or
Differential
Input
CLK_IN0
CLK_IN1
InputSourceSelect
(FromEEPROM)
CX0
CX1
Crystal
Unit
CICB
CICB
S0377-01
CDCE706
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The CDCE706 features two clock inputs which can be used as:•Crystal oscillator input (default setting)•Two independent single-ended LVCMOS inputs•Differential signal input
The dedicated clock input can be selected by the input signal source bits [7:6] of byte 11.
Crystal Oscillator Inputs
The input frequency range in crystal mode is 8 MHz to 54 MHz. The CDCE706 uses Pierce-type oscillatorcircuitry with included feedback resistance for the inverting amplifier. The user, however, must add externalcapacitors (C
X0
, C
X1
) to match the input load capacitor from the crystal (see Figure 14 ). The required values canbe calculated:
C
X0
= C
X1
= 2 × C
L
– C
ICB
,
where C
L
is the crystal load capacitor as specified for the crystal unit and C
ICB
is the input capacitance of thedevice, including the board capacitance (stray capacitance of PCB).
For example, for a fundamental 27-MHz crystal with C
L
of 9 pF and C
ICB
of 4 pF,C
X0
= C
X1
= (2 × 9 pF) – 3 pF = 15 pF.
It is important to use a short PCB trace from the device to the crystal unit to keep the stray capacitance of theoscillator loop to a minimum.
Figure 14. Crystal Input Circuitry
In order to ensure stable oscillation, a certain drive power must be applied. The CDCE706 features an inputoscillator with adaptive gain control, which relieves the user of manually programming the gain. Additionally,adaptive gain control eliminates the use of external resistors to compensate the ESR of the crystal. The drivelevel is the amount of power dissipated by the oscillating crystal unit and is usually specified in terms of powerdissipated by the resonator (equivalent series resistance (ESR)). Figure 15 gives the resulting drive level vscrystal frequency and ESR.
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Product Folder Link(s): CDCE706
f − Frequency − MHz
0
10
20
30
40
50
60
70
80
90
100
5 10 15 20 25 30 35 40 45 50 55
P(Drive) − Drive Power − W
G005
CL = 18 pF
V(pk) = 300 mV
21 W
ESR = 60
ESR = 50
ESR = 40
ESR = 30
ESR = 25
ESR = 15
XO
or
2LVCMOS
or
Differential
Input
CLK_IN0
CLK_IN1
CLK_SEL(1)
InputSourceSelect
(FromEEPROM)
S0378-01
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Figure 15. Crystal Drive Power
For example, if a 27-MHz crystal with ESR of 50 Ωis used and 2 × C
L
is 18 pF, the drive power is 21 µW. Drivelevel should be held to a minimum to avoid overdriving the crystal. The maximum power dissipation is specifiedfor each type of crystal in the oscillator specifications, i.e., 100 µW for the example above.
Single-Ended LVCMOS Clock Inputs
When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock input pins and can bedriven up to 200 MHz. Both clock input circuits are equal in design and can be used independently of each other(see Figure 16 ). The internal clock select bit, byte 10, bit [4], selects one of the two input clocks. CLK_IN0 is thedefault selection. There is also the option to program the external control pin S0/A0/CLK_SEL as the clock-selectpin, byte 10, bits [1:0].
The two clock inputs can be used for redundancy switching, i.e., to switch between a primary clock andsecondary clock. Note that a phase difference between the clock inputs may require PLL correction. Also, in caseof different frequencies between the primary and secondary clock, the PLL must re-lock to the new frequency.
(1) CLK_SEL is optional and can be configured by EEPROM setting.
Figure 16. LVCMOS Clock Input Circuitry
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
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XO
or
2LVCMOS
or
Differential
Input
CLK_IN0
CLK_IN1
InputSourceSelect
(FromEEPROM)
S0379-01
PLL Configuration and Setting
B0337-01
MUX
PLLx
PFD
Filter
VCO
VCOBypass
9-BitDividerM
1...511
12-BitDividerN
1...4095
SSC
(PLL2Only)
PLL Output
SSCOutput
(PLL2Only)
Programming
InputClock
CDCE706
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Differential Clock Inputs
The CDCE706 supports differential signaling as well. In this mode, the CLK_IN0 and CLK_IN1 pins serve asdifferential signal inputs and can be driven up to 200 MHz.
The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode inputvoltage range of 200 mV to V
CC
– 0.6 V. If LVDS or LVPECL signal levels are applied, ac coupling and a biasingstructure are recommended to adjust the different physical layers (see Figure 17 ). The capacitor removes the dccomponent of the signal (common-mode voltage), whereas the ac component (voltage swing) is passed on. Aresistor pullup and/or pulldown network represents the biasing structure used to set the common-mode voltageon the receiver side of the ac-coupling capacitor. DC coupling is also possible.
Figure 17. Differential Clock Input Circuitry
The CDCE706 includes three PLLs which are equal in function and performance, except PLL2, which in additionsupports spread-spectrum clocking (SSC) generation. Figure 18 shows the block diagram of the PLL.
Figure 18. PLL Architecture
All three PLLs are designed for easiest configuration. The user must define only the input and output frequenciesor the divider (M, N, P) setting. All other parameters, such as charge-pump current, filter components, phasemargin, or loop bandwidth are controlled and set by the device itself. This assures optimized jitter attenuation andloop stability.
The PLLs supports normal-speed mode (80 MHz ≤f
VCO
≤200 MHz) and high-speed mode (180 MHz ≤f
VCO
≤300 MHz), which can be selected by PLLxFVCO (bits [7:5] of byte 6). The speed option assures stable operationand lowest jitter.
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Spread-Spectrum Clocking and EMI Reduction
CDCE706
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Divider M and divider N operate internally as a fractional divider for f
VCO
up to 250 MHz. This allows a fractionaldivider ratio for zero-ppm output clock error.
In the case of f
VCO
> 250 MHz, it is recommended that only integer factors of N/M are used.
For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider conceptrequires a PLL divider configuration, M ≤N (or N/M ≥1).
Additionally, each PLL supports two bypass options:•PLL bypass•VCO bypass
In PLL bypass mode, the PLL is completely bypassed, so that the input clock is switched directly to outputswitch A (SWAPxx of bytes 9 to 12). In the VCO bypass mode, only the VCO of the PLL is bypassed by settingPLLxMUX to 1 (bits [7:5] of byte 3). But divider M still is useable and expands the output divider by an additional9 bits. This gives a total divider range of M × P = 511 × 127 = 64,897. In VCO bypass mode, the PLL block ispowered down and minimizes current consumption.
Table 3. Example for Divide, Multiplication, and Bypass Operation
f
IN
f
OUT-desired
f
OUT-actual
DividerFunction Equation
(1)
f
VCO
[MHz][MHz] [MHz] [MHz]
M N P N/M
Fractional
(2)
f
OUT
= f
IN
× (N/M)/P 30.72 155.52 155.52 16 81 1 5.0625 155.52Integer factor
(3)
f
OUT
= f
IN
× (N/M)/P 27 270 270 1 10 1 10 270VCO bypass f
OUT
= f
IN
/(M × P) 30.72 0.06 0.06 8 — 64 — —
(1) P-divider of output-switch matrix is included in the calculation.(2) Fractional operation for f
VCO
≤250 MHz(3) Integer operation for f
VCO
> 250 MHz
In addition to the basic PLL function, PLL2 supports spread-spectrum clocking (SSC). Thus, PLL 2 features twooutputs, an SSC output and a non-SSC output. Both outputs can be used in parallel. The mean phase of thecenter-spread, SSC-modulated signal is equal to the phase of the nonmodulated input frequency. SSC isselected by output switch A (SWAPxx of bytes 9 to 12).
SSC also is bypassable (byte 25, bits [6:4]) by powering down the SSC output and setting it to the logic-lowstate. The non-SSC output of PLL2 is not affected by this mode and can still be used.
SSC is an effective method to reduce electromagnetic interference (EMI) noise in high-speed applications. Itreduces the RF energy peak of the clock signal by modulating the frequency and spreads the energy of thesignal to a broader frequency range. Because the energy of the clock signal remains constant, a varyingfrequency that broadens the overtones necessarily lowers their amplitudes. Figure 19 shows the effect of SSC ona 54-MHz clock signal for DSP.
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
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7dB
CenterSpread±0.4%
9th Harmonic,f =60
m
DownSpread3%
9th Harmonic,f =60
m
11.3dB
C001
SSC Modulation Amount
SSC Modulation Frequency
CDCE706
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Figure 19. Spread-Spectrum Clocking With Center Spread and Down Spread
The peak amplitude of the modulated clock is 11.3 dB lower than the nonmodulated carrier frequency for downspread and radiates less electromagnetic energy.
In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulationamount is the frequency deviation relative to the carrier (min/max frequency), whereas the modulation frequencydetermines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to167 MHz.
The CDCE706 supports center-spread modulation and down-spread modulation. In center spread, the clock issymmetrically shifted around the carrier frequency and can be ± 0.1%, ± 0.25%, or ± 0.4%. For down spread, theclock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, or 3%. The down spread ispreferred if a system cannot tolerate an operating frequency higher than the nominal frequency (overclockingproblem).
Example:
Minimum Center MaximumModulation Type
Frequency Frequency Frequency
A ± 0.25% center spread 53.865 MHz 54 MHz 54.135 MHzB 1% down spread 53.46 MHz — 54 MHzC 0.5% down spread
(1)
53.73 MHz 53.865 MHz 54 MHz
(1) A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of ± 0.25%.
The modulation frequency (sweep rate) can be selected between 30 kHz and 60 kHz. It is also based on theVCO frequency as shown in the SSC Modulation Amount as shown in the Byte 25, Bits [6:4] table. As shown inFigure 20 , the damping increases with higher modulation frequencies. It may be limited by the tracking skew of adownstream PLL. The CDCE706 uses a triangle modulation profile which is one of the common profiles for SSC.
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fModulation − Modulation Frequency − kHz
3
4
5
6
7
8
9
10
11
12
30 35 40 45 50 55 60
EMI Reduction − dB
G006
±0.4 Center Spread
±0.25 Center Spread
2% Down Spread
3% Down Spread
Further EMI Reduction
11.3dB 7dB
11.3dB11.3dB 7dB7dB
Nom – 1
Nom
Nom+2
–3dB
–2.5dB
6.4dB
5.6dB
Slew-RateforV =2.5V
CCOUT Slew-RateforV =3.3V
CCOUT
C002
Nom – 1
Nom
Nom+2
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Figure 20. EMI Reduction vs f
Modulation
and f
Amount
The optimum damping is a combination of modulation amount, modulation frequency, and the harmonics whichare considered. Note that higher-order harmonic frequencies result in stronger EMI reduction because of higherfrequency deviation.
As seen in Figure 21 and Figure 22 , a slower output slew rate and/or smaller output-signal amplitude helps toreduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDCE706allows slew rate control in four steps between 0.6 ns and 3.3 ns (bytes 19 – 24, bits [5:4]). The output amplitude isset by the two independent output supply voltage pins, V
CCOUT1
and V
CCOUT2
, and can vary from 2.3 V to 3.6 V.Even a lower output supply voltage down to 1.8 V works, but the maximum frequency must be considered.
Figure 21. EMI Reduction vs Slew-Rate and V
CCOUT
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VCCOUT − Supply Voltage − V
−1
0
1
2
3
4
5
EMI Reduction − dB (Relative to Norm)
G007
2.5 3 3.6
Multifunction Control Inputs S0 and S1
Output Switching Matrix
CDCE706
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Figure 22. EMI Reduction vs V
CCOUT
The CDCE706 features two user-definable input pins which can be used as external control pins or address pins.When programmed as control pins, they can function as the clock-select pin, enable/disable pin, or devicepower-down pin. If both pins are used as address bits, up to four devices can be connected to the same SMBus.The function is set in byte 10, bits [3:0]. Table 4 shows the possible settings for the different output conditions,clock select, and device addresses.
Table 4. Configuration Setting of Control InputsConfiguration Bits
External Control Pins Device FunctionByte 10, Byte 10,Bit [3:2] Bit [1:0]
S1 S0 PowerS11 S10 S01 S00 Yx Outputs Pin 2 Pin 1(Pin 2) (Pin 1) Down
0 X 0 X 1 1 Active No Output ctrl Output ctrl
0 0 0 X 0 1 Low/high
(1)
No Output ctrl Output ctrl
0 1 0 X 0 1 High impedance Outputs only Output ctrl Output ctrl
0 X 0 0 X 0 High impedance PLL, inputs, and Output ctrl Output ctrl and pdoutputs
0 X 0 1 0 0 S10 = 0: low/high
(1)
PLL only Output ctrl PLL and div. bypassS10 = 1: high impedance
0 X 0 1 1 0 Active PLL only Output ctrl PLL and div. bypass
0 X 1 0 0 0/1
(2)
S10 = 0: Low/High
(1)
No Output ctrl CLK_SELS10 = 1: high impedance
0 X 1 0 1 0/1
(2)
Active No Output ctrl CLK_SEL
1 1 1 1 X X Active No A1
(3)
A0
(3)
(1) A noninverting output is set to low, and an inverting output is set to high.(2) If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.(3) S0 and S1 are interpreted as address bits A0 and A1 of the slave receiver address byte.
As shown in Table 4 , there is a specific order of the different output conditions: power-down mode overwriteshigh-impedance state, high-impedance state overwrites low-state, and low-state overwrites active-state.
The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signalsources via a free-selectable post-divider to any of the six outputs.
As shown in Figure 23 , the CDCE706 is based on two banks of switches and six post-dividers. Switch Acomprises six five-input multiplexers which select one of the four PLL clock outputs or directly select the inputclock and feed it to one of the 7-bit post-dividers (P-divider). Switch B is made up of six six-input multiplexerswhich take any P-divider and feed it to one of the six outputs, Yx.
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5x6-Switch A
InputCLK
(PLL Bypass)
PLL1
PLL3
6x6-SwitchB
7-BitDivider
Y0
Y1
Y2
Y3
Y4
Y5
P0
(1...127)
P1
(1...127)
P2
(1...127)
P3
(1...127)
P4
(1...127)
P5
(1...127)
Programming
PLL2
Non-SSC
PLL2
w/SSC
B0335-02
InternalClockSources OutputSwitchMatrix Outputs
PLL/Input_Clk
Selection
P-Divider
Setting
P-Divider
Selection
OutputSelection:
Active/Low/3-State
Inverting/Non-Inverting
SlewRate/VCCOUT
LVCMOS Output Configuration
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Switch B was added to the output switch matrix to ensure that output frequencies derived from one P-divider are100% phase-aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cyclecorrected. Changing the divider value on the fly may cause a glitch on the output.
Figure 23. CDCE706 Output Switch Matrix
In addition, the outputs can be switched active, low, high-impedance state, and/or 180-degree phase-shifted.Also, the output slew rate and the output voltage are user-selectable.
The output stage of the CDCE706 supports all common output settings, such as enable, disable, low-state, andsignal inversion (180-degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variableoutput supply voltage (2.3 V to 3.6 V).
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Buffer
Sel
M
U
X
P-Div(0)Output
P-Div(1)Output
P-Div(2)Output
P-Div(3)Output
P-Div(4)Output
P-Div(5)Output
Yx
S1
P-DividerSelect
InversionSelect
Slew-RateControl
LowSelect
Enable/Disable
(Optional; All
OutputsLow
or3-State)
V /V
CCOUT1 CCOUT2
B0338-01
Divby3
Inverting
SlewRate
LowSelect
Enable/Disable
Clock
T0410-01
CDCE706
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Figure 24. Block Diagram of Output Architecture
Figure 25. Example for Output Waveforms
All output settings are programmable via SMBus:•Enable, disable, low-state via external control pins S0 and S1 →byte 10, bits[3:0]•Enable or disable-to-low →bytes 19 to 24, bit[3]•Inverting/noninverting →bytes 19 to 24, bit[6]•Slew-rate control →bytes 19 to 24, bits[5:4]•Output swing →external pins V
CCOUT1
(pin 14) and V
CCOUT2
(pin 18)
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Performance Data: Output Skew, Jitter, Cross-Coupling, Noise Rejection (Spur Suppression),
Output Skew
Jitter Performance
CDCE706
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and Phase Noise
Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputsthat are driven by the same input clock. Table 5 shows the output skew (t
sk(o)
) of the CDCE706 for high-to-lowand low-to-high transitions over the entire range of supply voltages, operating temperature and output voltageswing.
Table 5. Output Skew
PARAMETER CONDITION TYP MAX UNIT
V
CCOUT
= 2.5 V 130 250 pst
sk(o)
Output skew
V
CCOUT
= 3.3 V 130 200 ps
Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases andtiming budget decreases. The PLL and internal circuits of CDCE706 are designed for lowest jitter. Thepeak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation ofcycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.
Table 6. Jitter Performance of CDCE706
TYP
(1)
MAX
(1)
PARAMETER CONDITION UNITrms rmsPeak-Peak Peak-Peak(One Sigma) (One Sigma)
f
out
= 50 MHz 55 – 75 –t
jit(cc)
Cycle-to-cycle jitter f
out
= 133 MHz 50 – 85 – psf
out
= 245.76 MHz 45 – 60 –f
out
= 50 MHz 60 4 76 7t
jit(per)
Period jitter f
out
= 133 MHz 55 5 84 11 psf
out
= 245.76 MHz 55 5 72 8f
out
= 50 MHz 730 90 840 115t
jit(phase)
Phase jitter f
out
= 133 MHz 930 130 1310 175 psf
out
= 245.76 MHz 720 90 930 125
(1) All typical and maximum values are at V
CC
= 3.3 V, temperature = 25 ° C, V
CCOUT
= 3.3 V; one output is switching, data taken overseveral 10,000 cycles.
Figure 26 ,Figure 27 , and Figure 28 show the relationship between cycle-to-cycle jitter, period jitter, and phasejitter over 10,000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter andperiod jitter show the measured value, whereas the phase jitter is the accumulated period jitter.
Cycle-to-Cycle jitter (t
jit(cc)
) is the variation in cycle time of a clock signal between adjacent cycles, over a randomsample of adjacent cycle pairs. Cycle-to-cycle jitter is never greater than the period jitter. It is also known asadjacent-cycle jitter.
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Cycle
−40
−30
−20
−10
0
10
20
30
40
1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001
tjit(cc) − Cycle-to-Cycle Jitter T ime − ps
G008
Cycle
−25
−20
−15
−10
−5
0
5
10
15
20
25
1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001
tjit(per) − Period Jitter Time − ps
G009
CDCE706
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Figure 26. Snapshot of Cycle-to-Cycle Jitter
Period jitter (t
jit(per)
) is the deviation in cycle time of a clock signal with respect to the ideal period (1/f
O
) over arandom sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal thatwould ever occur on the PLL outputs. This is also referred to as short-term jitter.
Figure 27. Snapshot of Period Jitter
Phase jitter (t
jit(phase)
) is the long-term variation of the clock signal. It is the cumulative deviation in t( Θ) for acontrolled edge with respect to a t( Θ) mean in a random sample of cycles. Phase jitter, time-interval error (TIE),and wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander isdefined as phase variation at rates less than 10 Hz, whereas jitter is defined as phase variation greater than10 Hz. The measurement interval must be long enough to gain a meaningful result. Wander can be caused bytemperature drift, aging, supply-voltage drift, etc.
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Cycle
−300
−250
−200
−150
−100
−50
0
50
100
150
200
250
300
1 1001 2001 3001 4001 5001 6001 7001 8001 9001 10001
tjit(phase) − Phase Jitter Time − ps
G010
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360
fVCO − VCO Frequency − MHz Set Point G011
tjit(per)p-p − Peak-to-Peak Jitter Performance T ime − ps
TA = 25°C
VCC = 3.3 V
M div = 4
N div = 15
P div = 3
fVCO − Frequency Range
for Normal-Speed Mode fVCO − Frequency Range
for High-Speed Mode
High-Speed Mode > 180 MHz
Normal-Speed Mode < 200 MHz
CDCE706
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Figure 28. Snapshot of Phase Jitter
Jitter depends on the VCO frequency (f
VCO
) of the PLL. A higher f
VCO
results in better jitter performancecompared to a lower f
VCO
. The VCO frequency can be defined via the M- and N-dividers of the PLL.
As the CDCE706 supports a wide frequency range, the device offers VCO frequency-selection bits, bits [7:5] ofbyte 6. These bits define the jitter-optimized frequency range of each PLL. The user can select between thenormal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure 29 showsthe jitter performance over f
VCO
for the two frequency ranges.
Figure 29. Period Jitter vs f
VCO
for Normal-Speed Mode and High-Speed Mode
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Cross-Coupling, Spur Suppression, and Noise Rejection
Carrier
48MHz
2 Harmonic
nd
Spurat
27MHz
56dB
·Measured Y1:48MHz
· W
· W
· W
·
Y0is27MHz(XTAL Buffered,Loadedby50 )
Y2is56.448MHz(Loadedby50 )
Y3is33.33MHz(Loadedby50 )
Y4, Y5intheHigh-ImpedanceState
C003
56dB
·
·
·
Measured Y0:48MHz
Y1, Y2, Y3 Y4and Y5intheHigh-ImpedanceState
Inserted30mV,1MHzatV =3.3V
CC
Carrier
48MHz
Carrier
48MHz
Spursat
47MHzand49MHz
Spur47MHzand
Fundamentalat1MHz
C004
Phase Noise Characteristic
CDCE706
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The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.
Cross-coupling in ICs occurs through interactions between several parts of the chip such as between outputstages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive, and resistive (ohmic),induced by output switching, leakage current, ground bouncing, power supply transients, etc.
The CDCE706 is designed using RFSiGe process technology. This process gives excellent performance inlinearity, low power consumption, best-in-class noise performance, and very good isolation characteristicsbetween the on-chip components.
The good isolation is a major benefit of the RFSiGe process because it minimizes the coupling effect. Even if allthree PLLs are active and all outputs are on, the noise suppression is well above 50 dB. Figure 30 and Figure 31show an example of noise coupling, spur-suppression, and power-supply noise rejection of the CDCE706. Themeasurement conditions are shown in Figure 30 and Figure 31 .
Figure 30. Noise Coupling and Spur Suppression
Figure 31. Power-Supply Noise Rejection
In high-speed communication systems, the phase-noise characteristic of the PLL frequency synthesizer is of highinterest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitterspecification in the time domain.
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−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
foffset − Offset Frequency − Hz G012
Phase Noise − dBc/Hz
Phase Noise Comparison
fout = 135 MHz
27-MHz Crystal
Buffered Output
10 100 1k 10k 100k 1M 10M
fVCO = 270 MHz
fVCO = 135 MHz
PLL-Lock Time
CDCE706
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........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discretespurious components could be caused by known clock frequencies in the signal source, power line interference,and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be theresult of thermal noise, shot noise, and/or flicker noise in active and passive devices.
An important factor for the PLL synthesizer is the loop bandwidth ( – 3-dB cutoff frequency) — large loop bandwidth(LBW) results in fast transient response but less reference spur attenuation. The LBW of the CDCE706 is about100 kHz to 250 kHz, depending on the selected PLL parameter.
For the CDCE706, two phase-noise characteristics are of interest, the phase noise of the crystal-input stage andthe phase noise of the internal PLL (VCO). Figure 32 shows the respective phase noise characteristic.
Figure 32. Phase Noise Characteristic
Some applications use frequency switching, e.g., changing frequency in a TV application (switching betweenchannels) or changing the PCI-X frequency in computers. The time spent by the PLL in achieving the newfrequency is of main interest. The lock time is the time it takes to jump from one specified frequency to anotherspecified frequency within a given frequency tolerance (see Figure 33 ). It should be low, because a long locktime impacts the data rate of the system.
The PLL-lock time depends on the device configuration and can be changed by the VCO frequency, i.e., bychanging the M/N divider values. Table 7 gives the typical lock times of the CDCE706 and Figure 33 shows asnapshot of a frequency switch.
Table 7. CDCE706 PLL Lock-Times
Description Lock Time Unit
Frequency change via reprogramming of N/M counter 100 µsFrequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1) 100 µsPower-up lock time with system clock 50 µsPower-up lock time with 27-MHz crystal at CLK_IN0 and CLK_IN1 300
(1)
µs
(1) Is the result of crystal lock time (200 µs) and PLL lock time (100 µs).
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): CDCE706
Y0(PLL1), Y1–Y4inHigh-ImpedanceState
MeasuredChannel: Y0
StartCondition:(M=10,N=30)=81MHz
Byte-2Write:N=30(81MHz)>N=110(297MHz)
60 stoPLL Pull-In
·
·
·
·
· m
f
20 s/divm
81
297
StartCondition:
Acknowledgeof
N-DividerByte
f (MHz)
VCO
Frequency
Response
Curveof Y0
0 60 t( s)m
C005
Power-Supply Sequencing
Device Behavior During Supply-Voltage Drops
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ...........................................................................................................................................
www.ti.com
Figure 33. Snapshot of the PLL Lock-Time
The CDCE706 includes three power-supply pins, V
CC
, V
CCOUT1
, and V
CCOUT2
. There are no power-supplysequencing requirements, as the three power nodes are separated from each other. So, power can be suppliedin any order to the three nodes.
Also, the part has power-up circuitry which switches the device on if V
CC
exceeds 2.1 V (typ) and switches thedevice off at V
CC
< 1.7 V (typ). In power-down mode, all outputs and clock inputs are switched off.
The CDCE706 has a power-up circuit, which activates the device functionality at V
PUC_ON
(typical 2.1 V). At thesame time, the EEPROM information is loaded into the register. This mechanism ensures that there is apredefined default after power up and no need to reprogram the CDCE706 in the application.
In the event of a supply-voltage drop, the power-up circuit ensures that there is always a defined setup within theregister. Figure 34 shows possible voltage drops with different amplitudes.
36 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE706
V
t
Typ3.3V
Typ2.1V
Typ1.7V
A
B
C
D
VCC
VPUC_ON
VPUC_OFF
GND
T0411-01
EVM and Programming Software
CDCE706
www.ti.com
........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
Figure 34. Different Voltage Drops on V
CC
During Operation
The CDCE706 power-up circuit has built-in hysteresis. If the voltage stays above V
PUC_OFF
, which is typically at1.7 V, the register content stays unchanged. If the voltage drops below V
PUC_OFF
, the internal register is reloadedby the EEPROM after V
PUC_ON
is crossed again. V
PUC_ON
is typically 2.1 V. Table 8 shows the content of theEEPROM and the register after the voltage-drop scenarios shown in Figure 34 .
Table 8. EEPROM and Register Content After V
CC
Drop
Power Drop EEPROM Content Register Content
A Unchanged UnchangedB Unchanged UnchangedC Unchanged Reloaded from EEPROMD Unchanged Reloaded from EEPROM
The CDCE706 EVM is a development kit consisting of a performance evaluation module, the TI Pro Clocksoftware, and the User's Guide. Contact a Texas Instruments sales or marketing representative for moreinformation.
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): CDCE706
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDCE706PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCE706PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCE706PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCE706PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Feb-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCE706PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCE706PWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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