MAX15026BETD+T - Maxim

General Description

The MAX15026 synchronous step-down controller oper-

ates from a 4.5V to 28V input voltage range and gener-

ates an adjustable output voltage from 85% of the input

voltage down to 0.6V while supporting loads up to 25A.

The device allows monotonic startup into a prebiased

bus without discharging the output and features adap-

tive internal digital soft-start.

The MAX15026 offers the ability to adjust the switching

frequency from 200kHz to 2MHz with an external resis-

tor. The MAX15026’s adaptive synchronous rectification

eliminates the need for an external freewheeling

Schottky diode. The device also utilizes the external

low-side MOSFET’s on-resistance as a current-sense

element, eliminating the need for a current-sense resis-

tor. This protects the DC-DC components from damage

during output overloaded conditions or output short-

circuit faults without requiring a current-sense resistor.

Hiccup-mode current limit reduces power dissipation

during short-circuit conditions. The MAX15026 includes

a power-good output and an enable input with precise

turn-on/turn-off threshold, which can be used for input

supply monitoring and for power sequencing.

Additional protection features include sink-mode cur-

rent limit and thermal shutdown.

Sink-mode current limit prevents reverse inductor cur-

rent from reaching dangerous levels when the device is

sinking current from the output.

The MAX15026 is available in a space-saving and ther-

mally enhanced 3mm x 3mm, 14-pin TDFN-EP pack-

age. The MAX15026 operates over the extended -40°C

to +85°C and automotive -40°C to +125°C temperature

ranges.

The MAX15026C is designed to provide additional mar-

gin for break-before-make times.

The MAX15026B/MAX15026C provide a soft-stop

feature to ramp down the output voltage at turn-off. The

soft-stop function is disabled in the MAX15026D.

Applications

Set-Top Boxes

LCD TV Secondary Supplies

Switches/Routers

Power Modules

DSP Power Supplies

Points-of-Load Regulators

Features

o4.5V to 28V or 5V ±10% Input Supply Range

o0.6V to (0.85 x VIN) Adjustable Output

oAdjustable 200kHz to 2MHz Switching Frequency

oAbility to Start into a Prebiased Load

oLossless, Cycle-by-Cycle Valley Mode Current

Limit with Adjustable, Temperature-Compensated

Threshold

oSink-Mode Current-Limit Protection

oAdaptive Internal Digital Soft-Start

o±1% Accurate Voltage Reference

oInternal Boost Diode

oAdaptive Synchronous Rectification Eliminates

External Freewheeling Schottky Diode

oHiccup-Mode Short-Circuit Protection

oThermal Shutdown

oPower-Good Output and Enable Input for Power

Sequencing

o±5% Accurate Enable Input Threshold

oAEC-Q100 Qualified (MAX15026B)

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

________________________________________________________________

Maxim Integrated Products

*EP

DRV

VCC

LIM

MAX15026

1+14 DHIN

312

BSTPGOOD

GNDCOMP

RTFB

TDFN

(3mm x 3mm)

TOP VIEW

*EP = EXPOSED PAD.

Pin Configuration

Ordering Information

19-4108; Rev 4; 2/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-PACKAGE

MAX15026BETD+

-40°C to +85°C

14 TDFN-EP*

MAX15026BETD/V+T -40°C to +85°C

14 TDFN-EP*

MAX15026CETD+

-40°C to +85°C

14 TDFN-EP*

MAX15026BATD+

-40°C to +125°C

14 TDFN-EP*

MAX15026CATD+

-40°C to +125°C

14 TDFN-EP*

MAX15026DATD+

-40°C to +125°C

14 TDFN-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad. T = Tape and reel.

/V denotes an automotive qualified part.

MAX15026C recommended for new designs.

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA= -40°C to +85°C (MAX15026B/CETD+, MAX15026BETD/V+),

TA= TJ= -40°C to +125°C (MAX15026B/C/DATD+), unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: Dissipation wattage values are based on still air with no heatsink. Actual maximum power dissipation is a function of heat

extraction technique and may be substantially higher. Package thermal resistances were obtained using the method

described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal consid-

erations, refer to www.maxim-ic.com/thermal-tutorial.

IN to GND ...............................................................-0.3V to +30V

BST to GND ............................................................-0.3V to +36V

LX to GND .................................................................-1V to +30V

EN to GND................................................................-0.3V to +6V

PGOOD to GND .....................................................-0.3V to +30V

BST to LX..................................................................-0.3V to +6V

DH to LX ...............................................….-0.3V to (VBST + 0.3V)

DRV to GND .............................................................-0.3V to +6V

DL to GND ................................................-0.3V to (VDRV + 0.3V)

VCC to GND...............-0.3V to the lower of +6V and (VIN + 0.3V)

All Other Pins to GND.................................-0.3V to (VCC + 0.3V)

VCC Short Circuit to GND...........................................Continuous

DRV Input Current.............................................................600mA

PGOOD Sink Current ............................................................5mA

Continuous Power Dissipation (TA= +70°C) (Note 1)

14-Pin TDFN-EP, Multilayer Board

(derate 24.4mW/°C above +70°C)..............................1951mW

Operating Temperature Range

MAX15026B/CETD+, MAX15026BETD/V+.......-40°C to +85°C

MAX15026B/C/DATD+ ...................................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL

4.5 28

Input Voltage Range VIN VIN = VCC = VDRV 4.5 5.5 V

Quiescent Supply Current VFB = 0.9V, no switching 1.75 2.75 mA

Shutdown Supply Current IIN_SBY EN = GND 290 500 µA

Enable to Output Delay 480 µs

VCC High to Output Delay EN = VCC 375 µs

VCC REGULATOR

6V < VIN < 28V, ILOAD = 25mA

Output Voltage VCC VIN = 12V, 1mA < ILOAD < 70mA 5.0 5.25 5.5 V

VCC Regulator Dropout VIN = 4.5V, ILOAD = 70mA 0.28 V

VCC Short-Circuit Output Current VIN = 5V 100 200 300 mA

VCC Undervoltage Lockout VCC_UVLO VCC rising 3.8 4.0 4.2 V

VCC Undervoltage Lockout

Hysteresis 400 mV

ERROR AMPLIFIER (FB, COMP)

FB Input Voltage Set-Point VFB 585 591 597 mV

FB Input Bias Current IFB VFB = 0.6V -250 +250 nA

FB to COMP Transconductance gMICOMP = ±20µA 600 1200 1800 µS

Amplifier Open-Loop Gain 80 dB

Amplifier Unity-Gain Bandwidth Capacitor from COMP to GND = 50pF 4 MHz

VCOMP-RAMP Minimum Voltage 160 mV

COMP Source/Sink Current ICOMP VCOMP = 1.4V 50 80 110 µA

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

_______________________________________________________________________________________ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ENABLE (EN)

EN Input High VEN_H VEN rising 1.14 1.20 1.26 V

EN Input Low VEN_L VEN falling 0.997 1.05 1.103 V

EN Input Leakage Current ILEAK_EN VEN = 5.5V -1 +1 µA

OSCILLATOR

Switching Frequency fSW RRT = 27kΩ540 600 660 kHz

1MHz Switching Frequency RRT = 15.7kΩ0.9 1 1.1 MHz

2MHz Switching Frequency RRT = 7.2kΩ1.8 2.0 2.4 MHz

Switching Frequency Adjustment

Range (Note 3) 200 2000 kHz

RT Voltage VRT 1.19 1.205 1.22 V

PWM Ramp Peak-to-Peak

Amplitude VRAMP 1.8 V

PWM Ramp Valley VVALLEY 0.8 V

Minimum Controllable On-Time 65 100 ns

Maximum Duty Cycle fSW = 600kHz 85 88 %

Minimum Low-Side On-Time RRT = 15.7kΩ75 110 150 ns

OUTPUT DRIVERS/DRIVER SUPPLY (DRV)

DRV Undervoltage Lockout VDRV_UVLO VDRV rising 4.0 4.2 4.4 V

DRV Undervoltage Lockout

Hysteresis 400 mV

Low, sinking 100mA, VBST = 5V 1 3

DH On-Resistance High, sourcing 100mA, VBST = 5V 1.5 4.5 Ω

Low, sinking 100mA, VBST = 5.2V 1 3

DL On-Resistance High, sourcing 100mA, VBST = 5.2V 1.5 4.5 Ω

Sinking 4

DH Peak Current CLOAD = 10nF Sourcing 3 A

Sinking 4

DL Peak Current CLOAD = 10nF Sourcing 3 A

DH/DL Break-Before-Make Time DH at 1V (falling) to DL at 1V (rising) 10 (18, Note 5) ns

DL/DH Break-Before-Make Time DL at 1V (falling) to DH at 1V (rising) 10 (20, Note 6) ns

SOFT-START

Soft-Start Duration 2048 Switching

Cycles

Reference Voltage Steps 64 Steps

CURRENT LIMIT/HICCUP

Current-Limit Threshold

Adjustment Range

Cycle-by-cycle valley current-limit

threshold adjustment range

valley limit = VLIM/10

30 300 mV

ELECTRICAL CHARACTERISTICS (continued)

(VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA= -40°C to +85°C (MAX15026B/CETD+, MAX15026BETD/V+),

TA= TJ= -40°C to +125°C (MAX15026B/C/DATD+), unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

4 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LIM Reference Current ILIM VLIM = 0.3V to 3V (Note 4) 45 50 55 µA

LIM Reference Current Tempco VLIM = 0.3V to 3V 2300 ppm/°C

Number of Consecutive Current-

Limit Events to Hiccup 7 Events

Soft-Start Timeout 4096 Switching

Cycles

Soft-Start Restart Timeout 8192 Switching

Cycles

Hiccup Timeout Out of soft-start 4096 Switching

Cycles

Peak Low-Side Sink Current

Limit Sink limit = 1.5V, RLIM = 30kΩ (Note 4) 75 mV

BOOST

Boost Switch Resistance VIN = VCC = 5V, IBST = 10mA 3 8 Ω

POWER-GOOD OUTPUT

PGOOD Threshold Rising 90 94.5 97.5 % VFB

PGOOD Threshold Falling 88 92 94.5 %VFB

PGOOD Output Leakage ILEAK_PGD VIN = VPGOOD = 28V, VEN = 5V, VFB = 1V -1 +1 µA

PGOOD Output Low Voltage VPGOOD_L IPGOOD = 2mA, EN = GND 0.4 V

THERMAL SHUTDOWN

Thermal-Shutdown Threshold Temperature rising +150 °C

Thermal-Shutdown Hysteresis Temperature falling 20 °C

ELECTRICAL CHARACTERISTICS (continued)

(VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA= -40°C to +85°C (MAX15026B/CETD+, MAX15026BETD/V+),

TA= TJ= -40°C to +125°C (MAX15026B/C/DATD+), unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

Note 2: All devices are 100% tested at room temperature and guaranteed by design over the specified temperature range.

Note 3: Select RRT as: where fSW is in Hertz.

Note 4: TA= +25°C.

Note 5: 10ns for MAX15026B, 18ns for the MAX15026C/D.

Note 6: 10ns for MAX15026B, 20ns for the MAX15026C/D.

R17.3 10

f 1x10 )x(f

SW 7SW

=×

+−

()

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

_______________________________________________________________________________________ 5

EFFICIENCY vs. LOAD CURRENT

(MAX15026B/C)

MAX15026 toc01

LOAD CURRENT (A)

EFFICIENCY (%)

810

62 4

100

012

VOUT = 3.3V

VOUT = 1.2V

VOUT = 5V

VOUT = 1.8V

EFFICIENCY vs. LOAD CURRENT

(VIN = 12V, VCC = VDRV = 5V)

MAX15026 toc02

LOAD CURRENT (A)

EFFICIENCY (%)

2012

VOUT = 3.3V VOUT = 1.2V

VOUT = 5V

VOUT = 1.8V

100

VOUT vs. LOAD CURRENT

MAX15026 toc03

LOAD CURRENT (A)

% OUTPUT FROM NOMINAL

106842012

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

-1.0

VCC vs. LOAD CURRENT

MAX15026 toc04

LOAD CURRENT (mA)

VCC (V)

8020 40 60

5.230

5.235

5.240

5.245

5.250

5.255

5.260

5.265

5.225

0 100

VCC LINE REGULATION

MAX15026 toc05

VIN (V)

VCC (V)

252015105

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

4.3

030

5mA

50mA

VCC vs. TEMPERATURE

MAX15026 toc06

TEMPERATURE (°C)

VCC (V)

603510-15

5.238

5.240

5.242

5.244

5.246

5.248

5.236

-40 85

SWITCHING FREQUENCY

vs. RESISTANCE

MAX15026 toc07

RESISTANCE (kΩ)

SWITCHING FREQUENCY (kHz)

80604020

500

1000

1500

2000

2500

0 100

SWITCHING FREQUENCY

vs. TEMPERATURE

MAX15026 toc08

TEMPERATURE (°C)

SWITCHING FREQUENCY (kHz)

603510-15

500

1000

1500

2000

2500

-40 85

RRT = 7.2kΩ

RRT = 15.7kΩ

RRT = 27kΩ

RRT = 85kΩ

SUPPLY CURRENT

vs. SWITCHING FREQUENCY

MAX15026 toc09

SWITCHING FREQUENCY (kHz)

SUPPLY CURRENT (mA)

1000

100 10,000

Typical Operating Characteristics

(VIN = 12V, TA= +25°C. The following TOCs are for MAX15026B/C/D, unless otherwise noted.) (See the circuit of Figure 5.)

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VIN = 12V, TA= +25°C. The following TOCs are for MAX15026B/C/D, unless otherwise noted.) (See the circuit of Figure 5.)

LIM REFERENCE CURRENT

vs. TEMPERATURE

MAX15026 toc10

TEMPERATURE (°C)

LIM REFERENCE CURRENT (µA)

603510-15

-40 85

SINK AND SOURCE CURRENT-LIMIT

THRESHOLDS vs. RESISTANCE (RILIM)

MAX15026 toc11

RESISTANCE (kΩ)

CURRENT-LIMIT THRESHOLDS (V)

605040302010

-0.3

-0.2

-0.1

0.1

0.2

-0.4

070

SINK CURRENT-LIMIT

SOURCE CURRENT-LIMIT

LOAD TRANSIENT ON OUT

MAX15026 toc12

400µs/div

AC-COUPLED

VOUT

200mV/div

IOUT

10A

STARTUP AND DISABLE FROM EN

(RLOAD = 1.5Ω)

MAX15026 toc13

4ms/div

VOUT

1V/div

VIN

5V/div

PGOOD

5V/div

STARTUP RISE TIME

(MAX15026B)

MAX15026 toc14

1ms/div

VIN

5V/div

VOUT

1V/div

POWER-DOWN FALL TIME

MAX15026 toc15

4ms/div

VIN

5V/div

VOUT

1V/div

STARTUP RISE TIME

(MAX15026C/D)

MAX15026 toc16

1ms/div

VIN

5V/div

VOUT

1V/div

0V OUTPUT

SOFT-START WITH 0.5V

PREBIAS AT NO LOAD (MAX15026C/D)

MAX15026 toc17

1ms/div

VIN

5V/div

VOUT

1V/div

0.5V OUTPUT PREBIAS

OUTPUT SHORT-CIRCUIT BEHAVIOR MONITOR

OUTPUT VOLTAGE AND CURRENT

MAX15026 toc18

4ms/div

500mV/div

VOUT

IOUT

20A/div

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

_______________________________________________________________________________________ 7

Pin Description

PIN NAME FUNCTION

1IN

Regulator Input. Bypass IN to GND with a 1µF minimum ceramic capacitor. Connect IN to VCC when

operating in the 5V ±10% range.

5.25V Linear Regulator Output. Bypass VCC to GND with a minimum of 4.7µF low-ESR ceramic

capacitor to ensure stability up to the regulated rated current when VCC supplies the drive current at

DRV. Bypass VCC to GND when VCC supplies the device core quiescent current with a 2.2µF

minimum ceramic capacitor.

3 PGOOD Open-Drain Power-Good Output. Connect PGOOD with an external resistor to any supply voltage.

4EN

Active-High Enable Input. Pull EN to GND to disable the output. Connect EN to VCC for always-on

operation. EN can be used for power sequencing and as a UVLO adjustment input.

5 LIM Current-Limit Adjustment. Connect a resistor from LIM to GND to adjust current-limit threshold from

30mV (RLIM = 6kΩ) to 300mV (RLIM = 60kΩ). See the Setting the Valley Current Limit section.

6 COMP Compensation Input. Connect compensation network from COMP to FB or from COMP to GND. See

the Compensation section.

7FB

Feedback Input. Connect FB to a resistive divider between output and GND to adjust the output

voltage between 0.6V and (0.85 x Input Voltage). See the Setting the Output Voltage section.

8RT

Oscillator Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency

from 200kHz to 2MHz. See the Setting the Switching Frequency section.

9 GND Ground

10 DRV Drive Supply Voltage. DRV is internally connected to the anode terminal of the internal boost diode.

Bypass DRV to GND with a 2.2µF minimum ceramic capacitor (see the Typical Application Circuits).

11 DL Low-Side Gate-Driver Output. DL swings from DRV to GND. DL is low during UVLO.

12 BST Boost Flying Capacitor. Connect a ceramic capacitor with a minimum value of 100nF between BST

and LX.

13 LX

External Inductor Connection. Connect LX to the switching side of the inductor. LX serves as the

lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage

drop of the synchronous MOSFET.

14 DH High-Side Gate-Driver Output. DH swings from LX to BST. DH is low during UVLO.

—EP

Exposed Pad. Internally connected to GND. Connect EP to a large copper plane at GND potential to

improve thermal dissipation. Do not use EP as the only GND ground connection.

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

8 _______________________________________________________________________________________

Functional Diagram

OSCILLATOR

DC-DC

AND

OSCILLATOR

ENABLE

LOGIC

VREF

ENABLE

COMPARATOR

OSC_ENABLE

BANDGAP

GENERATOR

VCC

UVLO

DRV

UVLO

THERMAL

SHUTDOWN

AND ILIM

CURRENT

GEN

UVLO

BGAP_OK

EN_INT

VL_OK

VDRV_OK

SHUTDOWN

VIN_OK

VREF

VIN_OK

IBIAS

VBGAP

BGAP_OK

VDRV

VIN_OK

VBGAP

LIM

VCC

INTERNAL

VOLTAGE

REGULATOR

MAIN

BIAS

CURRENT

GENERATOR

VREF = 0.6V

VBGAP = 1.24V

BANDGAP

REFERENCE

ENABLE

SOFT-START/

SOFT-STOP

LOGIC AND

HICCUP LOGIC

VREF

HICCUP

ENABLE DH_DL_ENABLE

VREF

DH_DL_ENABLE

HICCUP

TIMEOUT

FB1

DAC_VREF

PWM

COMPARATOR

RAMP

GENERATOR

SINK

CURRENT-LIMIT

COMPARATOR

PGOOD

COMPARATOR

VALLEY

CURRENT-LIMIT

COMPARATOR

PWM

CONTROL

LOGIC

BOOST

DRIVER

HIGH-

SIDE

DRIVER

LOW-

SIDE

DRIVER

RAMP

GATEP

HICCUP TIMEOUT

HICCUP

LIM/20

LIM/10

COMP

BST

DRV

GND

PGOOD

GND

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

_______________________________________________________________________________________ 9

Detailed Description

The MAX15026 synchronous step-down controller oper-

ates from a 4.5V to 28V input voltage range and gener-

ates an adjustable output voltage from 85% of the input

voltage down to 0.6V while supporting loads up to 25A.

As long as the device supply voltage is within 5.0V to

5.5V, the input power bus (VIN) can be as low as 3.3V.

The MAX15026 offers adjustable switching frequency

from 200kHz to 2MHz with an external resistor. The

adjustable switching frequency provides design flexi-

bility in selecting passive components. The MAX15026

adopts an adaptive synchronous rectification to elimi-

nate an external freewheeling Schottky diode and

improve efficiency. The device utilizes the on-resis-

tance of the external low-side MOSFET as a current-

sense element. The current-limit threshold voltage is

resistor-adjustable from 30mV to 300mV and is temper-

ature-compensated, so that the effects of the MOSFET

RDS(ON) variation over temperature are reduced. This

current-sensing scheme protects the external compo-

nents from damage during output overloaded condi-

tions or output short-circuit faults without requiring a

current-sense resistor. Hiccup-mode current limit

reduces power dissipation during short-circuit condi-

tions. The MAX15026 includes a power-good output

and an enable input with precise turn-on/-off threshold

to be used for monitoring and for power sequencing.

The MAX15026 features internal digital soft-start that

allows prebias startup without discharging the output.

The digital soft-start function employs sink current limit-

ing to prevent the regulator from sinking excessive cur-

rent when the prebias voltage exceeds the

programmed steady-state regulation level. The digital

soft-start feature prevents the synchronous rectifier

MOSFET and the body diode of the high-side MOSFET

from experiencing dangerous levels of current while the

regulator is sinking current from the output. The

MAX15026 shuts down at a junction temperature of

+150°C to prevent damage to the device.

DC-DC PWM Controller

The MAX15026 step-down controller uses a PWM volt-

age-mode control scheme (see the

Functional Diagram

Control-loop compensation is external for providing max-

imum flexibility in choosing the operating frequency and

output LC filter components. An internal transconduc-

tance error amplifier produces an integrated error volt-

age at COMP that helps to provide higher DC accuracy.

The voltage at COMP sets the duty cycle using a PWM

comparator and a ramp generator. On the rising edge of

an internal clock, the high-side n-channel MOSFET turns

on and remains on until either the appropriate duty cycle

or the maximum duty cycle is reached. During the on-

time of the high-side MOSFET, the inductor current

ramps up. During the second-half of the switching cycle,

the high-side MOSFET turns off and the low-side n-chan-

nel MOSFET turns on. The inductor releases the stored

energy as the inductor current ramps down, providing

current to the output. Under overload conditions, when

the inductor current exceeds the selected valley current-

limit threshold (see the

Current-Limit Circuit (LIM)

sec-

tion), the high-side MOSFET does not turn on at the

subsequent clock rising edge and the low-side MOSFET

remains on to let the inductor current ramp down.

Internal 5.25V Linear Regulator

An internal linear regulator (VCC) provides a 5.25V nomi-

nal supply to power the internal functions and to drive

the low-side MOSFET. Connect IN and VCC together

when using an external 5V ±10% power supply. The

maximum regulator input voltage (VIN) is 28V. Bypass IN

to GND with a 1µF ceramic capacitor. Bypass the output

of the linear regulator (VCC) with a 4.7µF ceramic capac-

itor to GND. The VCC dropout voltage is typically 125mV.

When VIN is higher than 5.5V, VCC is typically 5.25V. The

MAX15026 also employs an undervoltage lockout circuit

that disables the internal linear regulator when VCC falls

below 3.6V (typ). The 400mV UVLO hysteresis prevents

chattering on power-up/power-down.

The internal VCC linear regulator can source up to

70mA to supply the IC, power the low-side gate driver,

recharge the external boost capacitor, and supply small

external loads. The current available for external loads

depends on the current consumed by the MOSFET

gate drivers.

For example, when switching at 600kHz, a MOSFET

with 18nC total gate charge (at VGS = 5V) requires

(18nC x 600kHz) = 11mA. The internal control functions

consume 5mA maximum. The current available for

external loads is:

(70 – (2 x 11) – 5)mA ≅43mA

MOSFET Gate Drivers (DH, DL)

DH and DL are optimized for driving large-size n-chan-

nel power MOSFETs. Under normal operating condi-

tions and after startup, the DL low-side drive waveform

is always the complement of the DH high-side drive

waveform, with controlled dead-time to prevent cross-

conduction or shoot-through. An adaptive dead-time

circuit monitors the DH and DL outputs and prevents

the opposite-side MOSFET from turning on until the

other MOSFET is fully off. Thus, the circuit allows the

high-side driver to turn on only when the DL gate driver

has turned off, preventing the low-side (DL) from turn-

ing on until the DH gate driver has turned off.

MAX15026

The adaptive driver dead-time allows operation without

shoot-through with a wide range of MOSFETs, minimiz-

ing delays and maintaining efficiency. There must be a

low-resistance, low-inductance path from DL and DH to

the MOSFET gates for the adaptive dead-time circuits

to function properly. The stray impedance in the gate

discharge path can cause the sense circuitry to inter-

pret the MOSFET gate as off while the VGS of the

MOSFET is still high. To minimize stray impedance, use

very short, wide traces.

Synchronous rectification reduces conduction losses in

the rectifier by replacing the normal low-side Schottky

catch diode with a low-resistance MOSFET switch. The

MAX15026 features a robust internal pulldown transis-

tor with a typical 1ΩRDS(ON) to drive DL low. This low

on-resistance prevents DL from being pulled up during

the fast rise time of the LX node, due to capacitive cou-

pling from the drain to the gate of the low-side synchro-

nous rectifier MOSFET.

High-Side Gate-Drive Supply (BST)

and Internal Boost Switch

An internal switch between BST and DH turns on to

boost the gate voltage above VIN providing the neces-

sary gate-to-source voltage to turn on the high-side

MOSFET. The boost capacitor connected between BST

and LX holds up the voltage across the gate driver dur-

ing the high-side MOSFET on-time.

The charge lost by the boost capacitor for delivering the

gate charge is replenished when the high-side MOSFET

turns off and LX node goes to ground. When LX is low,

an internal high-voltage switch connected between

VDRV and BST recharges the boost capacitor. See the

Boost Capacitor

section in the

Applications Information

to choose the right size of the boost capacitor.

Enable Input (EN), Soft-Start,

and Soft-Stop

Drive EN high to turn on the MAX15026. A soft-start

sequence starts to increase step-wise the reference

voltage of the error amplifier. The duration of the soft-

start ramp is 2048 switching cycles and the resolution

is 1/64th of the steady-state regulation voltage allowing

a smooth increase of the output voltage. A logic-low on

EN initiates a soft-stop sequence by stepping down the

reference voltage of the error amplifier. After the soft-

stop sequence is completed, the MOSFET drivers are

both turned off. See Figure 1. The soft-stop feature is

disabled in the MAX15026D.

Connect EN to VCC for always-on operation. Owing to

the accurate turn-on/-off thresholds, EN can be used as

UVLO adjustment input, and for power sequencing

together with the PGOOD output.

When the valley current limit is reached during soft-start

the MAX15026 regulates to the output impedance times

the limited inductor current and turns off after 4096

clock cycles. When starting up into a large capacitive

load (for example) the inrush current will not exceed the

current-limit value. If the soft-start is not completed

before 4096 clock cycles, the device will turn off. The

device remains off for 8192 clock cycles before trying

to soft-start again. This implementation allows the soft-

start time to be automatically adapted to the time nec-

essary to keep the inductor current below the limit while

charging the output capacitor.

Power-Good Output (PGOOD)

The MAX15026 includes a power-good comparator to

monitor the output voltage and detect the power-good

threshold, fixed at 94.5% of the nominal FB voltage. The

open-drain PGOOD output requires an external pullup

resistor. PGOOD sinks up to 2mA of current while low.

PGOOD goes high (high-impedance) when the regula-

tor output increases above 94.5% of the designed nom-

inal regulated voltage. PGOOD goes low when the

regulator output voltage drops to below 92% of the

nominal regulated voltage. PGOOD asserts low during

hiccup timeout period.

Startup into a Prebiased Output

When the MAX15026 starts into a prebiased output, DH

and DL are off so that the converter does not sink cur-

rent from the output. DH and DL do not start switching

until the PWM comparator commands the first PWM

pulse. The first PWM pulse occurs when the ramping

reference voltage increases above the FB voltage.

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

10 ______________________________________________________________________________________

Current-Limit Circuit (LIM)

The current-limit circuit employs a valley and sink cur-

rent-sensing algorithm that uses the on-resistance of

the low-side MOSFET as a current-sensing element, to

eliminate costly sense resistors. The current-limit circuit

is also temperature compensated to track the on-resis-

tance variation of the MOSFET over temperature. The

current limit is adjustable with an external resistor at

LIM, and accommodates MOSFETs with a wide range

of on-resistance characteristics (see the

Setting the

Valley Current Limit

section). The adjustment range is

from 30mV to 300mV for the valley current limit, corre-

sponding to resistor values of 6kΩto 60kΩ. The valley

current-limit threshold across the low-side MOSFET is

precisely 1/10th of the voltage at LIM, while the sink

current-limit threshold is 1/20th of the voltage at LIM.

Valley current limit acts when the inductor current flows

towards the load, and LX is more negative than GND

during the low-side MOSFET on-time. If the magnitude

of current-sense signal exceeds the valley current-limit

threshold at the end of the low-side MOSFET on-time,

the MAX15026 does not initiate a new PWM cycle and

lets the inductor current decay in the next cycle. The

controller also rolls back the internal reference voltage

so that the controller finds a regulation point deter-

mined by the current-limit value and the resistance of

the short. In this manner, the controller acts as a con-

stant current source. This method greatly reduces

inductor ripple current during the short event, which

reduces inductor sizing restrictions, and reduces the

possibility for audible noise. After a timeout, the device

goes into hiccup mode. Once the short is removed, the

internal reference voltage soft-starts back up to the nor-

mal reference voltage and regulation continues.

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 11

VCC

BCD E

2048 CLK

CYCLES

2048 CLK

CYCLES

FGHIA

UVLO

VOUT

DAC_VREF

UVLO Undervoltage threshold value is provided in

the Electrical Characteristics table.

Internal 5.25V linear regulator output.

Active-high enable input.

Regulator output voltage.

Regulator internal soft-start and soft-stop signal.

Regulator high-side gate-driver output.

Regulator low-side gate-driver output.

VCC rising while below the UVLO threshold.

EN is low.

VCC

VOUT

DAC_VREF

SYMBOL DEFINITION

BVCC is higher than the UVLO threshold. EN is low.

EN is pulled high. DH and DL start switching.

Normal operation.

VCC drops below UVLO.

VCC goes above the UVLO threshold. DH and DL

start switching. Normal operation.

EN is pulled low. VOUT enters soft-stop.

EN is pulled high. DH and DL start switching.

Normal operation.

VCC drops below UVLO.

SYMBOL DEFINITION

Figure 1. Power-On/-Off Sequencing for MAX15026B/C.

MAX15026

Sink current limit is implemented by monitoring the volt-

age drop across the low-side MOSFET when LX is more

positive than GND. When the voltage drop across the

low-side MOSFET exceeds 1/20th of the voltage at LIM

at any time during the low-side MOSFET on-time, the

low-side MOSFET turns off, and the inductor current

flows from the output through the body diode of the high-

side MOSFET. When the sink current limit activates, the

DH/DL switching sequence is no longer complementary.

Carefully observe the PCB layout guidelines to ensure

that noise and DC errors do not corrupt the current-

sense signals at LX and GND. Mount the MAX15026

close to the low-side MOSFET with short, direct traces

making a Kelvin-sense connection so that trace resis-

tance does not add to the intended sense resistance of

the low-side MOSFET.

Hiccup-Mode Overcurrent Protection

Hiccup-mode overcurrent protection reduces power dis-

sipation during prolonged short-circuit or deep overload

conditions. An internal three-bit counter counts up on

each switching cycle when the valley current-limit

threshold is reached. The counter counts down on each

switching cycle when the threshold is not reached, and

stops at zero (000). The counter reaches 111 (= 7

events) when the valley mode current-limit condition

persists. The MAX15026 stops both DL and DH drivers

and waits for 4096 switching cycles (hiccup timeout

delay) before attempting a new soft-start sequence. The

hiccup-mode protection remains active during the soft-

start time.

Undervoltage Lockout

The MAX15026 provides an internal undervoltage lockout

(UVLO) circuit to monitor the voltage on VCC. The UVLO

circuit prevents the MAX15026 from operating when VCC

is lower than VUVLO. The UVLO threshold is 4V, with

400mV hysteresis to prevent chattering on the rising/falling

edge of the supply voltage. DL and DH stay low to inhibit

switching when the device is in undervoltage lockout.

Thermal-Overload Protection

Thermal-overload protection limits total power dissipation

in the MAX15026. When the junction temperature of the

device exceeds +150°C, an on-chip thermal sensor shuts

down the device, forcing DL and DH low, allowing the

device to cool. The thermal sensor turns the device on

again after the junction temperature cools by 20°C. The

regulator shuts down and soft-start resets during thermal

shutdown. Power dissipation in the LDO regulator and

excessive driving losses at DH/DL trigger thermal-over-

load protection. Carefully evaluate the total power dissi-

pation (see the

Power Dissipation

section) to avoid

unwanted triggering of the thermal-overload protection in

normal operation.

Applications Information

Effective Input Voltage Range

The MAX15026 operates from input supplies up to 28V

and regulates down to 0.6V. The minimum voltage con-

version ratio (VOUT/VIN) is limited by the minimum con-

trollable on-time. For proper fixed-frequency PWM

operation, the voltage conversion ratio must obey the

following condition,

where tON(MIN) is 125ns and fSW is the switching fre-

quency in Hertz. Pulse-skipping occurs to decrease the

effective duty cycle when the desired voltage conver-

sion does not meet the above condition. Decrease the

switching frequency or lower VIN to avoid pulse skipping.

The maximum voltage conversion ratio is limited by the

maximum duty cycle (Dmax):

where VDROP1 is the sum of the parasitic voltage drops

in the inductor discharge path, including synchronous

rectifier, inductor, and PCB resistance. VDROP2 is the

sum of the resistance in the charging path, including

high-side switch, inductor, and PCB resistance. In

practice, provide adequate margin to the above condi-

tions for good load-transient response.

Setting the Output Voltage

Set the MAX15026 output voltage by connecting a

resistive divider from the output to FB to GND (Figure

2). Select R2from between 1kΩand 50kΩ. Calculate

R1with the following equation:

where VFB = 0.591V (see the

Electrical Characteristics

table) and VOUT can range from 0.591V to (0.85 x VIN).

Resistor R1also plays a role in the design of the Type III

compensation network. Review the values of R1and R2

when using a Type III compensation network (see the

Type III Compensation Network (See Figure 4)

section).

RR V

OUT

12 1=⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

−

VDDV (1D)V

OUT

IN max max DROP2 max DROP1

<×+ ×

−−

Vtf

OUT

NON(MIN) SW

>×

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

12 ______________________________________________________________________________________

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 13

Setting the Switching Frequency

An external resistor connecting RT to GND sets the

switching frequency (fSW). The relationship between

fSW and RRT is:

where fSW is in Hz and RRT is in Ω. For example, a

600kHz switching frequency is set with RRT = 27.2kΩ.

Higher frequencies allow designs with lower inductor

values and less output capacitance. Peak currents and

I2R losses are lower at higher switching frequencies,

but core losses, gate-charge currents, and switching

losses increase.

Inductor Selection

Three key inductor parameters must be specified for

operation with the MAX15026: inductance value (L),

inductor saturation current (ISAT), and DC resistance

(RDC). To determine the inductance value, select the

ratio of inductor peak-to-peak AC current to DC average

current (LIR) first. For LIR values which are too high, the

RMS currents are high, and therefore I2R losses are

high. Use high-valued inductors to achieve low LIR val-

ues. Typically, inductance is proportional to resistance

for a given package type, which again makes I2R losses

high for very low LIR values. A good compromise

between size and loss is a 30% peak-to-peak ripple cur-

rent to average-current ratio (LIR = 0.3). The switching

frequency, input voltage, output voltage, and selected

LIR determine the inductor value as follows,

where VIN, VOUT, and IOUT are typical values (so that

efficiency is optimum for typical conditions). The switch-

ing frequency is set by RRT (see the

Setting the

Switching Frequency

section). The exact inductor value

is not critical and can be adjusted to make trade-offs

among size, cost, and efficiency. Lower inductor values

minimize size and cost, but also improve transient

response and reduce efficiency due to higher peak cur-

rents. On the other hand, higher inductance increases

efficiency by reducing the RMS current.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. The satura-

tion current rating (ISAT) must be high enough to ensure

that saturation can occur only above the maximum cur-

rent-limit value (ICL(MAX)), given the tolerance of the on-

resistance of the low-side MOSFET and of the LIM

reference current (ILIM). Combining these conditions,

select an inductor with a saturation current (ISAT) of:

ISAT ≥1.35 x ICL(TYP)

where ICL(TYP) is the typical current-limit set-point. The

factor 1.35 includes RDS(ON) variation of 25% and 10%

for the LIM reference current error. A variety of inductors

from different manufacturers are available to meet this

requirement (for example, Coilcraft MSS1278-142ML

and other inductors from the same series).

Setting the Valley Current Limit

The minimum current-limit threshold must be high

enough to support the maximum expected load current

with the worst-case low-side MOSFET on-resistance

value as the RDS(ON) of the low-side MOSFET is used

as the current-sense element. The inductor’s valley cur-

rent occurs at ILOAD(MAX) minus one half of the ripple

current. The minimum value of the current-limit thresh-

old voltage (VITH) must be higher than the voltage on

the low-side MOSFET during the ripple-current valley:

where RDS(ON) is the on-resistance of the low-side

MOSFET in ohms. Use the maximum value for RDS(ON)

from the data sheet of the low-side MOSFET.

VR I LIR

ITH DS ON MAX LOAD MAX

>××

⎛

⎝

⎜⎞

⎠

⎟

−

(, ) ( ) 12

LVVV

Vf I LIR

OUT IN OUT

IN SW OUT

=−()

R17.3 10

f 1x10 )x(f

SW 7SW

=×

+−

()

OUT

MAX15026

Figure 2. Adjustable Output Voltage

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

14 ______________________________________________________________________________________

Connect an external resistor (RLIM) from LIM to GND to

adjust the current-limit threshold. The relationship

between the current-limit threshold (VITH) and RLIM is:

where RLIM is in kΩand VITH is in mV.

An RLIM resistance range of 6kΩto 60kΩcorresponds

to a current-limit threshold of 30mV to 300mV. Use 1%

tolerance resistors when adjusting the current limit to

minimize error in the current-limit threshold.

Input Capacitor

The input filter capacitor reduces peak currents drawn

from the power source and reduces noise and voltage

ripple on the input caused by the switching circuitry.

The input capacitor must meet the ripple current

requirement (IRMS) imposed by the switching currents

as defined by the following equation,

IRMS attains a maximum value when the input voltage

equals twice the output voltage (VIN = 2VOUT), so

IRMS(MAX) = ILOAD(MAX)/2. For most applications,

non-tantalum capacitors (ceramic, aluminum, poly-

mer, or OS-CON) are preferred at the inputs due to

the robustness of non-tantalum capacitors to accom-

modate high inrush currents of systems being pow-

ered from very low-impedance sources. Additionally,

two (or more) smaller-value low-ESR capacitors can

be connected in parallel for lower cost.

Output Capacitor

The key selection parameters for the output capacitor are

capacitance value, ESR, and voltage rating. These para-

meters affect the overall stability, output ripple voltage, and

transient response. The output ripple has two components:

variations in the charge stored in the output capacitor, and

the voltage drop across the capacitor’s ESR caused by

the current flowing into and out of the capacitor:

∆VRIPPLE ≅ ∆VESR + ∆VQ

The output voltage ripple as a consequence of the ESR

and the output capacitance is:

where IP-P is the peak-to-peak inductor current ripple

(see the

Inductor Selection

section). Use these equa-

tions for initial capacitor selection. Decide on the final

values by testing a prototype or an evaluation circuit.

Check the output capacitor against load-transient

response requirements. The allowable deviation of the

output voltage during fast load transients determines

the capacitor output capacitance, ESR, and equivalent

series inductance (ESL). The output capacitor supplies

the load current during a load step until the controller

responds with a higher duty cycle. The response time

(tRESPONSE) depends on the closed-loop bandwidth of

the converter (see the

Compensation

section). The

resistive drop across the ESR of the output capacitor,

the voltage drop across the ESL (∆VESL) of the capaci-

tor, and the capacitor discharge, cause a voltage

droop during the load step.

Use a combination of low-ESR tantalum/aluminum elec-

trolytic and ceramic capacitors for improved transient

load and voltage ripple performance. Nonleaded

capacitors and capacitors in parallel help reduce the

ESL. Keep the maximum output voltage deviation below

the tolerable limits of the load. Use the following equa-

tions to calculate the required ESR, ESL, and capaci-

tance value during a load step:

where ISTEP is the load step, tSTEP is the rise time of the

load step, tRESPONSE is the response time of the con-

troller and fOis the closed-loop crossover frequency.

Compensation

The MAX15026 provides an internal transconductance

amplifier with the inverting input and the output avail-

able for external frequency compensation. The flexibility

of external compensation offers a wide selection of out-

put filtering components, especially the output capaci-

tor. Use high-ESR aluminum electrolytic capacitors for

cost-sensitive applications. Use low-ESR tantalum or

ceramic capacitors at the output for size sensitive

applications. The high switching frequency of the

MAX15026 allows the use of ceramic capacitors at the

output. Choose all passive power components to meet

the output ripple, component size, and component cost

ESR V

CIt

ESL V

ESR

STEP

OUT STEP RESPONSE

=×

∆

∆EESL STEP

STEP

RESPONSE O

≅×

∆

V I ESR

IVV

ESR P P

QPP

OUT SW

PP IN O

=×

=××

−

UUT

OUT

V×

⎛

⎝

⎜⎞

⎠

⎟×⎛

⎝

⎜⎞

⎠

⎟

II VVV

RMS LOAD MAX OUT IN OUT

=−

()

LIM ITH

=×10

50µ

requirements. Choose the small-signal components for

the error amplifier to achieve the desired closed-loop

bandwidth and phase margin.

To choose the appropriate compensation network type,

the power-supply poles and zeros, the zero crossover

frequency, and the type of the output capacitor must be

determined.

In a buck converter, the LC filter in the output stage intro-

duces a pair of complex poles at the following frequency:

The output capacitor introduces a zero at:

where ESR is the equivalent series resistance of the

output capacitor.

The loop-gain crossover frequency (fO), where the loop

gain equals 1 (0dB) should be set below 1/10th of the

switching frequency:

Choosing a lower crossover frequency reduces the

effects of noise pick-up into the feedback loop, such as

jittery duty cycle.

To maintain a stable system, two stability criteria must

be met:

1) The phase shift at the crossover frequency fO, must

be less than 180°. In other words, the phase margin

of the loop must be greater than zero.

2) The gain at the frequency where the phase shift is

-180° (gain margin) must be less than 1.

Maintain a phase margin of around 60° to achieve a

robust loop stability and well-behaved transient

response.

When using an electrolytic or large-ESR tantalum output

capacitor the capacitor ESR zero fZO typically occurs

between the LC poles and the crossover frequency fO

(fPO < fZO < fO). Choose Type II (PI—proportional-inte-

gral) compensation network.

When using a ceramic or low-ESR tantalum output

capacitor, the capacitor ESR zero typically occurs

above the desired crossover frequency fO, that is fPO <

fO < fZO. Choose Type III (PID—proportional, integral,

and derivative) compensation network.

Type II Compensation Network

(Figure 3)

If fZO is lower than fOand close to fPO, the phase lead

of the capacitor ESR zero almost cancels the phase

loss of one of the complex poles of the LC filter around

the crossover frequency. Use a Type II compensation

network with a midband zero and a high-frequency

pole to stabilize the loop. In Figure 3, RFand CFintro-

duce a midband zero (fZ1). RFand CCF in the Type II

compensation network provide a high-frequency pole

(fP1), which mitigates the effects of the output high-fre-

quency ripple.

Follow the instructions below to calculate the component

values for the Type II compensation network in Figure 3:

1) Calculate the gain of the modulator (GAINMOD),

comprised of the regulator’s pulse-width modulator,

LC filter, feedback divider, and associated circuitry

at the crossover frequency:

where VIN is the input voltage of the regulator, VRAMP is

the amplitude of the ramp in the pulse-width modulator,

VFB is the FB input voltage set-point (0.591V typically,

see the

Electrical Characteristics

table), and VOUT is

the desired output voltage.

The gain of the error amplifier (GAINEA) in midband fre-

quencies is:

GAINEA = gMx RF

where gMis the transconductance of the error amplifier.

The total loop gain, which is the product of the modula-

tor gain and the error amplifier gain at fO, is 1.

So:

Solving for RF:

2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel

one of the LC poles):

fRC f

ZFF PO1

2075=×× =×

π.

RVfLV

V V g ESR

FRAMP O OUT OUT

FB IN M

=×××

()

×××

2π

ESR

VgR

RAMP O OUT

OUT MF

××× ×××=

()21

GAIN GAIN

MOD EA

×=1

GAIN V

ESR

MOD IN

RAMP O OUT

OUT

=×

××

()

2π

OSW

≤10

fESR C

ZO OUT

=××

2π

fLC

OUT OUT

=××

2π

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 15

MAX15026

Solving for CF:

3) Place a high-frequency pole at fP1 = 0.5 x fSW (to

attenuate the ripple at the switching frequency, fSW)

and calculate CCF using the following equation:

Type III Compensation Network

(See Figure 4)

When using a low-ESR tantalum or ceramic type, the

ESR-induced zero frequency is usually above the tar-

geted zero crossover frequency (fO). Use Type III com-

pensation. Type III compensation provides three poles

and two zeros at the following frequencies:

Two midband zeros (fZ1 and fZ2) cancel the pair of

complex poles introduced by the LC filter:

fP1 = 0

fP1 introduces a pole at zero frequency (integrator) for

nulling DC output voltage errors:

Depending on the location of the ESR zero (fZO), use

fP2 to cancel fZO, or to provide additional attenuation of

the high-frequency output ripple:

fP3 attenuates the high-frequency output ripple.

Place the zeros and poles so the phase margin peaks

around fO.

Ensure that RF>>2/gMand the parallel resistance of R1,

R2, and RIis greater than 1/gM. Otherwise, a 180°

phase shift is introduced to the response making the

loop unstable.

Use the following compensation procedure:

1) With RF≥10kΩ, place the first zero (fZ1) at 0.8 x fPO.

So:

2) The gain of the modulator (GAINMOD), comprises

the pulse-width modulator, LC filter, feedback

divider, and associated circuitry at the crossover

frequency is:

GN V

VfL C

RAMP OOUTOUT

AI MOD =×

()

××

GN V

RAMP

AI MOD =×

(

fRC f

ZFF PO1

208=×× =×

π.

RCC

FFCF

FCF

×× ×

fRC

PII

=××π

fRC

fCRR

ZFF

ZII

=××

=×× +

π()

Rf C

FSW F

×× −

CRf

FFPO

=×× ×

2075π.

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

16 ______________________________________________________________________________________

VREF

VOUT

R2gM

COMP

CFCCF

Figure 3. Type II Compensation Network

VREF

VOUT

COMP

CCF

RFCF

Figure 4. Type III Compensation Network

The gain of the error amplifier (GAINEA) in midband fre-

quencies is:

GAINEA = 2πx fOx C1x RF

The total loop gain as the product of the modulator gain

and the error amplifier gain at fOis 1.

So:

Solving for CI:

3) Use the second pole (fP2) to cancel fZO when fPO <

fO < fZO < fSW/2. The frequency response of the

loop gain does not flatten out soon after the 0dB

crossover, and maintains a -20dB/decade slope up

to 1/2 of the switching frequency. This is likely to

occur if the output capacitor is a low-ESR tantalum.

Set fP2 = fZO.

When using a ceramic capacitor, the capacitor ESR

zero fZO is likely to be located even above 1/2 the

switching frequency, fPO < fO < fSW/2 < fZO. In this

case, place the frequency of the second pole (fP2) high

enough to not significantly erode the phase margin at

the crossover frequency. For example, set fP2 at 5 x fO

so that the contribution to phase loss at the crossover

frequency fOis only about 11°:

fP2 = 5 x fPO

Once fP2 is known, calculate RI:

4) Place the second zero (fZ2) at 0.2 x fOor at fPO,

whichever is lower, and calculate R1using the fol-

lowing equation:

5) Place the third pole (fP3) at 1/2 the switching fre-

quency and calculate CCF:

6) Calculate R2as:

MOSFET Selection

The MAX15026 step-down controller drives two external

logic-level n-channel MOSFETs. The key selection

parameters to choose these MOSFETs include:

• On-Resistance (RDS(ON))

• Maximum Drain-to-Source Voltage (VDS(MAX))

• Minimum Threshold Voltage (VTH(MIN))

• Total Gate Charge (QG)

• Reverse Transfer Capacitance (CRSS)

• Power Dissipation

The two n-channel MOSFETs must be a logic-level type

with guaranteed on-resistance specifications at VGS =

4.5V. For maximum efficiency, choose a high-side

MOSFET that has conduction losses equal to the

switching losses at the typical input voltage. Ensure

that the conduction losses at minimum input voltage do

not exceed the MOSFET package thermal limits, or vio-

late the overall thermal budget. Also, ensure that the

conduction losses plus switching losses at the maxi-

mum input voltage do not exceed package ratings or

violate the overall thermal budget. Ensure that the DL

gate driver can drive the low-side MOSFET. In particu-

lar, check that the dv/dt caused by the high-side

MOSFET turning on does not pull up the low-side

MOSFET gate through the drain-to-gate capacitance

of the low-side MOSFET, which is the most frequent

cause of cross-conduction problems.

Check power dissipation when using the internal linear

regulator to power the gate drivers. Select MOSFETs

with low gate charge so that VCC can power both dri-

vers without overheating the device.

PDRIVE = VCC x QG_TOTAL x fSW

where QG_TOTAL is the sum of the gate charges of the

two external MOSFETs.

OUT FB

=×

−

fRC

CF F

SW F F

=×× ××

()

−205 1π.

RfC

I1 2

=××

−

RfC

IPI

=××

CVfLC

IRAMP O OUT OUT

IN F

=××× ×

()

2π

VfC L

RAMP OOUTOUT

××× ×

()π

GAIN GAIN

MOD EA

×=1

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 17

MAX15026

Boost Capacitor

The MAX15026 uses a bootstrap circuit to generate the

necessary gate-to-source voltage to turn on the high-

side MOSFET. The selected n-channel high-side

MOSFET determines the appropriate boost capaci-

tance value (CBST in the

Typical Application Circuits

)

according to the following equation:

where QGis the total gate charge of the high-side

MOSFET and ∆VBST is the voltage variation allowed on

the high-side MOSFET driver after turn-on. Choose

∆VBST so the available gate-drive voltage is not signifi-

cantly degraded (e.g. ∆VBST = 100mV to 300mV) when

determining CBST. Use a low-ESR ceramic capacitor as

the boost flying capacitor with a minimum value of

100nF.

Power Dissipation

The maximum power dissipation of the device depends

on the thermal resistance from the die to the ambient

environment and the ambient temperature. The thermal

resistance depends on the device package, PCB cop-

per area, other thermal mass, and airflow.

The power dissipated into the package (PT) depends

on the supply configuration (see the

Typical Application

Circuits

). Use the following equation to calculate power

dissipation:

PT= (VIN - VCC) x ILDO + VDRV x IDRV + VCC x IIN

where ILDO is the current supplied by the internal regu-

lator, IDRV is the supply current consumed by the dri-

vers at DRV, and IIN is the supply current of the

MAX15026 without the contribution of the IDRV, as given

in the

Typical Operating Characteristics

. For example, in

the application circuit of Figure 5, ILDO = IDRV + IIN and

VDRV = VCC so that PT= VIN x (IDRV + IIN).

Use the following equation to estimate the temperature

rise of the die:

TJ= TA+ (PTx θJA)

where θJA is the junction-to-ambient thermal imped-

ance of the package, PTis power dissipated in the

device, and TAis the ambient temperature. The θJA is

24.4°C/W for 14-pin TDFN package on multilayer

boards, with the conditions specified by the respective

JEDEC standards (JESD51-5, JESD51-7). An accurate

estimation of the junction temperature requires a direct

measurement of the case temperature (TC) when actual

operating conditions significantly deviate from those

described in the JEDEC standards. The junction tem-

perature is then:

TJ= TC+ (PTx θJC)

Use 8.7°C/W as θJC thermal impedance for the 14-pin

TDFN package. The case-to-ambient thermal imped-

ance (θCA) is dependent on how well the heat is trans-

ferred from the PCB to the ambient. Solder the exposed

pad of the TDFN package to a large copper area to

spread heat through the board surface, minimizing the

case-to-ambient thermal impedance. Use large copper

areas to keep the PCB temperature low.

PCB Layout Guidelines

Place all power components on the top side of the

board, and run the power stage currents using traces

or copper fills on the top side only. Make a star connec-

tion on the top side of traces to GND to minimize volt-

age drops in signal paths.

Keep the power traces and load connections short,

especially at the ground terminals. This practice is

essential for high efficiency and jitter-free operation. Use

thick copper PCBs (2oz or above) to enhance efficiency.

Place the MAX15026 adjacent to the synchronous recti-

fier MOSFET, preferably on the back side, to keep LX,

GND, DH, and DL traces short and wide. Use multiple

small vias to route these signals from the top to the bot-

tom side. Use an internal quiet copper plane to shield

the analog components on the bottom side from the

power components on the top side.

Make the MAX15026 ground connections as follows:

create a small analog ground plane near the device.

Connect this plane to GND and use this plane for the

ground connection for the VIN bypass capacitor, com-

pensation components, feedback dividers, VCC capaci-

tor, RT resistor, and LIM resistor.

Use Kelvin sense connections for LX and GND to the

synchronous rectifier MOSFET for current limiting to

guarantee the current-limit accuracy.

Route high-speed switching nodes (BST, LX, DH, and DL)

away from the sensitive analog areas (RT, COMP, LIM,

and FB). Group all GND-referred and feedback compo-

nents close to the device. Keep the FB and compensation

network as small as possible to prevent noise pickup.

BST

=∆

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

18 ______________________________________________________________________________________

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 19

Typical Application Circuits

10kΩ

4.02kΩ

11.8kΩ

1.4µH

BST

ENABLE

PGOOD

VIN

DRV

GND

VCC

PGOOD

LIM

COMP

4.02kΩ

15.4kΩ

27kΩ

R1*

*R1 IS A SMALL-VALUE RESISTOR TO DECOUPLE

SWITCHING TRANSIENTS CAUSED BY THE

MOSFET DRIVER (2.2Ω).

2.2µF

330µF

PANASONIC

EEEFCIE331P

4.5V TO 28V

C10

4.7µF

68pF

0.022µF

68pF

C11

1500pF

470µF

SANYO

4C54701

22µF

0.47µF

Q1 ( )

VOUT

COILCRAFT

MSS1278-142ML

MAX15026

ON-SEMICONDUCTOR

NTMFS4835NTIG

( )

ON-SEMICONDUCTOR

NTMFS4835NTIG

Single 4.5V to 28V Supply Operation

Figure 5 shows an application circuit for a single 4.5V to 28V power-supply operation.

Figure 5. VIN = 4.5V to 28V

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

20 ______________________________________________________________________________________

Typical Application Circuits (continued)

Single 4.5V to 5.5V Supply Operation

Figure 6 shows an application circuit for a single 4.5V to 5.5V power-supply operation.

Figure 6. VCC = VIN = VDRV = 4.5V to 5.5V

RLIM

BST

ENABLE

PGOOD

VIN

DRV

GND

VCC

PGOOD

LIM

COMP

4.5V TO 5.5V

CF1

CBST

VOUT

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

______________________________________________________________________________________ 21

Typical Application Circuits (continued)

RLIM

BST

ENABLE

VAUX

4.5V TO 5.5V

PGOOD

VIN

+12V

DRV

GND

VCC

PGOOD

LIM

COMP

CF1

CBST

VOUT

MAX15026

Auxiliary 5V Supply Operation

Figure 7 shows an application circuit for a +12V supply to drive the external MOSFETs and an auxiliary +5V supply

to power the device.

Figure 7. Operation with Auxiliary 5V Supply

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

22 ______________________________________________________________________________________

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maxim-ic.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE OUTLINE NO. LAND

PATTERN NO.

14 TDFN-EP T1433+2 21-0137 90-0063

MAX15026

Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in

the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/08 Initial release —

1 5/09

Revised General Description, Ordering Information, Absolute Maximum

Ratings, Electrical Characteristics, Power-Good Output (PGOOD) section,

and Typical Application Circuits

1–4, 10, 15, 19

2 9/10

Added MAX15026C; revised General Description, Ordering Information,

Electrical Characteristics, Typical Operating Characteristics, and Startup

into a Prebiased Output sections

1–6, 10

3 4/11 Added automotive part to Ordering Information, Absolute Maximum Ratings,

and Electrical Characteristics 1, 2, 3

4 2/12 Design modified to meet customer requirements and new OPN added to

Ordering Information 1–6, 10, 11