ACS8515REV2.1T - SEMTECH INTERNATIONAL

LL

Line CC

CC

Card PP

PP

Protection SS

SS

Switch

for SONET or SDH Network Elements

ACS8515 Rev2.1 LC/P

Description Description

Description Features Features

Features Features

Features

Block Diagram Block Diagram

Block Diagram

The ACS8515 is a highly integrated, single-chip

solution for ‘hit-less’ protection switching of SEC

clocks from Master and Slave SETS clockcards

in a SONET or SDH Network Element. The

ACS8515 has fast activity monitors on the in-

puts and will implement automatic system pro-

tection switching against master clock failure.

A further input is provided for an optional standby

SEC clock. The ACS8515 is fully compliant with

the required specifications and standards.

The ACS8515 can perform frequency translation

from a SEC input clock distributed along a back

plane to a different local line card clock, e.g.

8 kHz distributed on the back plane and

19.44 MHz generated on the line cards.

An SPI(1) compatible serial port is incorporated,

providing access to the configuration and status

registers for device setup.

The ACS8515 can utilise either a low cost XO

oscillator module, or a TCXO with full tempera-

ture calibration - as required by the application.

Rev2.1 adds choice of edge alignment for 8kHz

input, as well as a low jitter n x E1/DS1 output

mode. Other minor changes are made, with all

described in Appendix A.

ADVANCED COMMUNICATIONS FINAL

Revision 2.01/December 2005 Semtech Corp. www.semtech.com

•Suitable for Stratum 3, 4E and 4 SONET

or SDH Equipment Clock (SEC) applications

•Meets AT&T, ITU-T, ETSI and Telcordia

specifications

•Three SEC input clocks, from 2 kHz to

155.52 MHz

•Generates two SEC output clocks, up to

311.04 MHz

•Frequency translation of SEC input clock to a

different local line card clock

•Robust input clock source frequency and

activity monitoring on all inputs

•Supports Free-run, Locked and Holdover

modes of operation

•Automatic ‘hit-less’ source switchover on loss

of input

•External force fast switch between SEC inputs

•Phase build out for output clock phase

continuity during input switchover

•SPI(1) compatible serial microprocessor interface

•Programmable wander and jitter tracking

attenuation 0.1 Hz to 20 Hz

•Single +3.3 V operation. +5 V I/O compatible

•Operating temperature (ambient) -40°C to

+85°C

•Available in 64 pin LQFP package

•Lead (pb)-free version available (ACS8515

Rev2.1T) RoHS and WEEE compliant.

(1) SPI is a trademark of Motorola Corporation

Figure 1. Simple Block DiagramFigure 1. Simple Block Diagram

Figure 1. Simple Block Diagram

Monitors

Chip Clock

Generator

TCXO or XO

DPLL

Frequency Synthesis

3 x SEC Input

Master/Slave

+ Standby:

N x 8kHz

1.544/2.048MHz

6.48MHz

19.44MHz

38.88MHz

51.84MHz

77.76MHz

155.52MHz

MFrSync

APLL

Frequency

Dividers

Output

Ports

2xSEC

FrSync

MFrSync

Input

Ports

3xSEC

MFrSync

SPI Compatible Serial

Microprocessor Port

Priority

Table

Register

Set

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

T T

Table of Contable of Cont

able of Contable of Cont

able of Contentsents

entsents

ents

List of SectionsList of Sections

List of Sections

Description ................................................................................................................................................................................................ 1

Block Diagram........................................................................................................................................................................................... 1

Features ..................................................................................................................................................................................................... 1

T able of Contents ...................................................................................................................................................................................... 2

Pin Diagram............................................................................................................................................................................................... 4

Pin Descriptions........................................................................................................................................................................................ 5

Functional Description ............................................................................................................................................................................. 7

Local Oscillator Clock ..................................................................................................................................................................................... 7

Crystal Frequency Calibration........................................................................................................................................................ 7

Input Reference Clock Ports......................................................................................................................................................................... 8

Input Wander and Jitter Tolerance ............................................................................................................................................................ 10

Output Clock Ports ........................................................................................................................................................................................ 11

Low Speed Output Clock................................................................................................................................................................11

High Speed Output Clock ..............................................................................................................................................................12

Frame Sync and Multi-Frame Sync Clocks ................................................................................................................................12

Low Jitter Multiple E1/DS1 Outputs ...........................................................................................................................................12

Output Wander and Jitter............................................................................................................................................................................ 13

Phase Variation ............................................................................................................................................................................................. 14

Phase Build Out............................................................................................................................................................................................. 16

Microprocessor Interface ............................................................................................................................................................................. 16

Register Set .....................................................................................................................................................................................16

Configuration Registers .................................................................................................................................................................16

Status Registers ..............................................................................................................................................................................16

Register Access............................................................................................................................................................................... 17

Interrupt Enable and Clear ......................................................................................................................................................................... 17

Register Map .................................................................................................................................................................................................. 18

Register Map Description ........................................................................................................................................................................... 21

Selection of Input Reference Clock Source ............................................................................................................................................. 29

Automatic Control Selection ........................................................................................................................................................29

Ultra Fast Switching .......................................................................................................................................................................30

External Protection Switching .....................................................................................................................................................30

Activity Monitoring ....................................................................................................................................................................................... 30

Modes of Operation ...................................................................................................................................................................................... 32

Free-run Mode .................................................................................................................................................................................32

Pre-Locked Mode ............................................................................................................................................................................32

Locked Mode....................................................................................................................................................................................32

Lost-Phase Mode.............................................................................................................................................................................33

Holdover Mode ................................................................................................................................................................................33

Pre-Locked(2) Mode ........................................................................................................................................................................33

Power On Reset - PORB ............................................................................................................................................................................... 33

Electrical Specification..........................................................................................................................................................................35

Serial Microprocessor Interface Timing ...............................................................................................................................................44

Package Information ..............................................................................................................................................................................46

Thermal Conditions ....................................................................................................................................................................................... 47

Application Information..........................................................................................................................................................................48

Appendix A Rev2.1 Changes Described ...............................................................................................................................................49

Revision History .............................................................................................................. ........................................................................49

Ordering Information ..............................................................................................................................................................................50

Disclaimers ..................................................................................................................................................................................................... 50

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

List of FiguresList of Figures

List of Figures

Figure 1. Simple Block Diagram .............................................................................................................................................................. 1

Figure 2. ACS8515 Pin Diagram .................................................................................................. ........................................................... 4

Figure 3. Minimum Input Jitter T olerance (OC-3/STM-1)....................................................................................................................11

Figure 4. Minimum Input Jitter T olerance (DS1/E1) ...........................................................................................................................12

Figure 5. Wander and Jitter T ransfer Measured Characteristics ........................................................................................................14

Figure 6. Maximum Time Interval Error of TOUT0 Output Port ...........................................................................................................15

Figure 7 . Time Deviation of TOUT0 Output Port ...................................................................................................................................15

Figure 8. Phase Error Accumulation of TOUT0 Output Port in Holdover Mode.................................................................................15

Figure 9. Inactivity and Irregularity Monitoring....................................................................................................................................30

Figure 10. Automatic Mode Control State Diagram............................................................................................................................34

Figure 11. Recommended Line Termination for PECL Input/Output Ports .......................................................................................38

Figure 12. Recommended Line T ermination for LVDS Input/Output Ports .......................................................................................39

Figure 13. Input/Output Timing .............................................................................................................................................................43

Figure 14. Serial Interface Read Access Timing..................................................................................................................................44

Figure 15. Serial Interface Write Access Timing .................................................................................................................................45

Figure 16. LQFP Package.......................................................................................................................................................................46

Figure 1 7 . T ypical 64 Pin LQFP Footprint....................................................................................... ....................................................... 47

Figure 18. Simplified Application Schematic.......................................................................................................................................48

List of TList of T

List of Tablesables

ablesables

ables

T able 1. Power Pins.................................................................................................................................................................................... 5

T able 2. No Connections............................................................................................................................................................................ 5

T able 3. Other Pins..................................................................................................................................................................................... 6

T able 4. Input Reference Source Selection and Group Allocation ....................................................................................................... 9

T able 5. Input Reference Source Jitter Tolerance ................................................................................................................................10

T able 6. Amplitude and Frequency values for Jitter T olerance ............................................................................................................11

T able 7 . Amplitude and Frequency values for Jitter T olerance ............................................................................................................12

T able 8. Output Reference Source Selection Table .............................................................................................................................13

T able 9. Multiple E1/DS1 Output in Relation to Normal Outputs .................................................................. ...................................13

T able 10. Register Map ...........................................................................................................................................................................18

T able 11. Register Map Description ......................................................................................................................................................21

T able 12. Absolute Maximum Ratings ...................................................................................................................................................35

T able 13. Operating Conditions ..............................................................................................................................................................35

T able 14. DC Characteristics: TTL Input Pad.........................................................................................................................................35

T able 15. DC Characteristics: TTL Input Pad with Internal Pull-up .....................................................................................................36

T able 16. DC Characteristics: TTL Input Pad with Internal Pull-down ................................................................................................36

T able 1 7 . DC Characteristics: TTL Output Pad ......................................................................................................................................36

T able 18. DC Characteristics: PECL Input/Output Pad .......................................................................................................................37

T able 19. DC Characteristics: L VDS Input/Output Pad .......................................................................................................................38

T able 20. DC Characteristics: Output Jitter Generation (T est definition G.813)..............................................................................39

T able 21. DC Characteristics: Output Jitter Generation (T est definition G.8 12)..............................................................................40

T able 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) ..............................................................40

T able 23. DC Characteristics: Output Jitter Generation (T est definition GR-253-CORE)................................................................41

T able 24. DC Charact eristics: Output Jitter Generation (T est definition A T&T 624 11) ...................................................................41

T able 25. DC Characteristics: Output Jitter Generation (T est definition G.7 42) ..............................................................................42

T able 26. DC Characteristics: Output Jitter Generation (T est definition TR-NWT-000499) ...........................................................42

T able 27 . DC Characteristics: Output Jitter Generation (T est definition GR-1244-CORE)..............................................................42

T able 28. Serial Interface Read Access Timing....................................................................................................................................45

T able 29. Serial Interface Write Access Timing ...................................................................................................................................45

T able 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)...................................................................................... 47

T able 31. Revision Hist ory ......................................................................................................................................................................49

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

NC - Not Connected, IC - Internally Connected

Pin Diagram Pin Diagram

Pin Diagram

1 AGND

2IC

3 AGND

4 VA1+

5 INTREQ

6 REFCLK

7 DGND

8 VD+

9 VD+

10 DGND

11 DGND

12 VD+

13 SRCSW

14 VA2+

15 AGND

16 IC

17 FrSync

18 MFrSync

19 O1POS

20 O1NEG

21 GND_DIFF

22 VDD_DIFF

23 SEC1_POS

24 SEC1_NEG

25 SEC2_POS

26 SEC2_NEG

27 VDD5

28 Sync2k

29 SEC1

30 SEC2

31 DGND

32 VDD

64 SONSDHB

63 IC

62 IC

61 IC

60 IC

59 NC

58 DGND

57 VDD

56 O2

55 NC

54 VDD

53 DGND

52 SDO

51 IC

50 IC

49 IC

48 PORB

47 SCLK

46 VDD

45 VDD

44 CSB

43 SDI

42 CLKE

41 IC

40 DGND

39 VDD

38 VDD

37 IC

36 VDD

35 IC

34 SEC3

33 IC

ACS8515

LC/P

Rev 2.1

1

Figure 2. ACS8515 Pin DiagramFigure 2. ACS8515 Pin Diagram

Figure 2. ACS8515 Pin Diagram

Revision 2.01/December 2005 Semtech Corp. www.semtech.com5

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Pin Descriptions Pin Descriptions

Pin Descriptions

Table 1. Power PinsTable 1. Power Pins

Table 1. Power Pins

Table 2. No ConnectionsTable 2. No Connections

Table 2. No Connections

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

95,55CN-- detcennoCtoNdetcennoCtoN detcennoCtoN detcennoCtoNdetcennoCtoNtaolFotevaeL:

,33,61,2 ,16,06,53 36,26 CI-- detcennoCyllanretnIdetcennoCyllanretnI detcennoCyllanretnI detcennoCyllanretnIdetcennoCyllanretnItaolFotevaeL:

73CI-- :detcennocyllanretnI:detcennocyllanretnI :detcennocyllanretnI :detcennocyllanretnI:detcennocyllanretnIlortnocGATJrofdevreseR.taolFotevaeLnoisivertxennotupniteser

14CI-- :detcennocyllanretnI:detcennocyllanretnI :detcennocyllanretnI :detcennocyllanretnI:detcennocyllanretnIedomtsetGATJrofdevreseR.taolFotevaeL noisivertxennotupnitceles

94CI-- :detcennocyllanretnI:detcennocyllanretnI :detcennocyllanretnI :detcennocyllanretnI:detcennocyllanretnIGATJrofdevreseR.taolFotevaeL noisivertxennotupnikcolcnacsyradnuob

05CI-- :detcennocyllanretnI:detcennocyllanretnI :detcennocyllanretnI :detcennocyllanretnI:detcennocyllanretnItsetlairesGATJrofdevreseR.taolFotevaeL noisivertxennotuptuoatad

15CI-- :detcennocyllanretnI:detcennocyllanretnI :detcennocyllanretnI :detcennocyllanretnI:detcennocyllanretnItsetlairesGATJrofdevreseR.taolFotevaeLnoisivertxennotupniatad

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

21,9,8+DVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS,noitcesgolananisetagotylppuslatigiD

%01-/+.stloV3.3+

22FFID_DDVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS&91sniptuptuolaitnereffidrofylppuslatigiD %01-/+.stloV3.3+,02

725DDVP-

5DDV5DDV 5DDV 5DDV5DDVtcennoC.sniptupniotecnarelotstloV5+rofylppuslatigiD: rofDDVottcennoC.v5+otgnipmalcrof)%01-/+(stlov5+ot sniptupni,gnipmalconrofgnitaolfevaeL.v3.3+otgnipmalc .v5.5+otputnarelot

,83,63,23 ,64,54,93 75,45 DDVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS%01-/+.stloV3.3+,cigolotylppuslatigiD

4+1AVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS3.3+,LLPAgniypitlumkcolcotylppusgolanA

%01-/+.stloV

41+2AVP- egatlovylppuSegatlovylppuS egatlovylppuS egatlovylppuSegatlovylppuS%01-/+.stloV3.3+,LLPAtuptuootylppusgolanA:

,11,01,7 ,35,04,13 85 DNGDP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuScigolrofdnuorglatigiD:

12FFID_DNGP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuS&91sniptuptuolaitnereffidrofdnuorglatigiD:

02

51,3,1DNGAP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuSdnuorggolanA:

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Table 3. Other PinsTable 3. Other Pins

Table 3. Other Pins

Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

5QERTNIO- :tseuqertpurretnI:tseuqertpurretnI :tseuqertpurretnI :tseuqertpurretnI:tseuqertpurretnIelbanetpurretnIerawtfoS

6KLCFERILTT :kcolcecnerefeR:kcolcecnerefeR :kcolcecnerefeR :kcolcecnerefeR:kcolcecnerefeRlacoLdedaehnoitcesotrefer(zHM8.21

)kcolCrotallicsO

31WSCRSILTT

D

:gnihctiwsecruoS:gnihctiwsecruoS :gnihctiwsecruoS :gnihctiwsecruoS:gnihctiwsecruoS2CESdna1CESnognihctiwsecruostsafecroF

71cnySrFOLTT :ecnerefertuptuO:ecnerefertuptuO :ecnerefertuptuO :ecnerefertuptuO:ecnerefertuptuOoitarecaps/kram05:05,cnySemarFzHk8

tuptuo

81cnySrFMOLTT 2:ecnerefertuptuO2:ecnerefertuptuO 2:ecnerefertuptuO 2:ecnerefertuptuO2:ecnerefertuptuOecaps/kram05:05,cnySemarF-itluMzHk

tuptuooitar

9102 SOP1O GEN1O OSDVL/

LCEP :ecnerefertuptuO:ecnerefertuptuO :ecnerefertuptuO :ecnerefertuptuO:ecnerefertuptuOSDVLzHM88.83tluafed,elbammargorP

3242 SOP_1CES GEN_1CES ISDVL/

LCEP :ecnerefertupnI:ecnerefertupnI :ecnerefertupnI :ecnerefertupnI:ecnerefertupnISDVLzHM44.91tluafed,elbammargorP

5262 SOP_2CES GEN_2CES I/LCEP SDVL :ecnerefertupnI:ecnerefertupnI :ecnerefertupnI :ecnerefertupnI:ecnerefertupnILCEPzHM44.91tluafed,elbammargorP

82k2cnySILTT

D

:zHk2cnySemarF-itluM:zHk2cnySemarF-itluM :zHk2cnySemarF-itluM :zHk2cnySemarF-itluM:zHk2cnySemarF-itluMtupnicnySemarF-itluM

921CESILTT

D

:ecnerefertupnI:ecnerefertupnI :ecnerefertupnI :ecnerefertupnI:ecnerefertupnIzHk8tluafed,elbammargorP

032CESILTT

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:ecnerefertupnI:ecnerefertupnI :ecnerefertupnI :ecnerefertupnI:ecnerefertupnIzHk8tluafed,elbammargorP

433CESILTT

D

:ecnerefertupnI:ecnerefertupnI :ecnerefertupnI :ecnerefertupnI:ecnerefertupnI,ecruoskcolcecnereferybdnatslanretxE zHM44.91tluafed,elbammargorp

24EKLCILTT

D

:tcelesegdeKLCS:tcelesegdeKLCS :tcelesegdeKLCS :tcelesegdeKLCS:tcelesegdeKLCSstceles1=EKLC,tcelesegdeevitcaKLCS egdegnisirrof0=EKLC,evitcaebotKLCSfoegdegnillaf

34IDSILTT

D

:sserddaecafretnirossecorporciM:sserddaecafretnirossecorporciM :sserddaecafretnirossecorporciM :sserddaecafretnirossecorporciM:sserddaecafretnirossecorporciMtupniatadlaireS

44BSCILTT

U

:)wolevitca(tcelespihC:)wolevitca(tcelespihC :)wolevitca(tcelespihC :)wolevitca(tcelespihC:)wolevitca(tcelespihCehtybwoLdetressasinipsihT ecafretnirossecorporcimehtelbaneotrossecorporcim

74KLCSILTT

D

:elbanEhctaLsserddA:elbanEhctaLsserddA :elbanEhctaLsserddA :elbanEhctaLsserddA:elbanEhctaLsserddAnipsihtnehW.kcolcatadlaireStluafed dehctalerastupnisubsserddaeht,hgihotwolmorfsnoitisnart sretsigerlanretniehtotni

84BROPILTT

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:tesernorewoP:tesernorewoP :tesernorewoP :tesernorewoP:tesernorewoPlanretnilla,woLdecrofsiBROPfI.teserretsaM seulavtluafedotkcabtesererasetats

Revision 2.01/December 2005 Semtech Corp. www.semtech.com7

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

F F

F

unctional Descriptionunctional Description

unctional Description

The ACS8515 is a highly integrated, single-chip

solution for ‘hit-less’ protection switching of SEC

clocks from Master and Slave SETS clock cards

in a SONET or SDH Network Element. The

ACS8515 has fast activity monitors on the

inputs and will implement automatic system

protection switching for Master/Slave SEC clock

failure. The standby SEC clock will be selected

if both the Master and Slave input clocks fail.

The selection of the Master/Slave input can

also be forced by a Force Fast Switch pin.

The ACS8515 can perform frequency translation

from a SEC input clock distributed along a back

plane to a different local line card - e.g. 8 kHz

distributed on the back plane and 19.44 MHz

generated on the line cards.

The ACS8515 has three SEC clock inputs

(Master, Slave and Standby) and a single Multi-

Frame Sync input, for synchronising the frame

and multi-frame sync outputs.

The ACS8515 generates two SEC clock outputs

via PECL/LVDS and TTL ports, with spot

frequencies from 1.544/2.048 MHz up to

311.04 MHz. The ACS8515 also provides an

8 kHz Frame Sync and 2 kHz Multi-Frame Sync

output clock.

The ACS8515 has a high tolerance to input

jitter and wander. The jitter/wander transfer is

programmable (0.1 Hz up to 20 Hz cut-off

points).

The ACS8515 includes an SPI compatible serial

microprocessor port, providing access to the

configuration and status registers for device

setup.

Local Oscillator ClockLocal Oscillator Clock

Local Oscillator Clock

The Master system clock on the ACS8515

requires an external clock oscillator of frequency

12.80 MHz. The exact clock specification is

dependent on the quality of Holdover

performance required in the application.

In most Line Card protection switching

applications where there is a high chance that

at least one SEC reference input will be

available, the long term stability requirement

for Holdover is not appropriate and an

inexpensive crystal local oscillator can be used.

In other applications where there may be a

requirement for longer term Holdover stability

to meet the ITU standards for Stratum 3, a

higher quality oscillator can be used.

Please contact Semtech for information on

crystal oscillator suppliers.

Crystal Frequency CalibrationCrystal Frequency Calibration

Crystal Frequency Calibration

The absolute crystal frequency accuracy is less

important than the stability since any frequency

offset can be compensated by adjustment of

register values in the IC. This allows for

calibration and compensation of any crystal

frequency variation away from its nominal value.

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

25ODSOLTT

D

:sserddaecafretnirossecorporciM:sserddaecafretnirossecorporciM :sserddaecafretnirossecorporciM :sserddaecafretnirossecorporciM:sserddaecafretnirossecorporciMtuptuoatadlaireS

652OOLTT:ecnerefertuptuO:ecnerefertuptuO :ecnerefertuptuO :ecnerefertuptuO:ecnerefertuptuOdexifzHM44.91

46BHDSNOSILTT

D

:BHDSTENOS:BHDSTENOS :BHDSTENOS :BHDSTENOS:BHDSTENOSlaitiniehtstes:tcelesycneuqerfHDSroTENOS HDS/TENOSehtfo)BROParetfaetatsro(etatspu-rewop 5stib,83rddadna2tib,h43rdda,sretsigernoitcelesycneuqerf dna)ctezHM840.2(detceleserasetarHDSwolnehW.6dna ehT.)ctezHM445.1(detceleserasetarTENOShgihtesnehw .erawtfosybpurewopretfadegnahcebnacsetatsretsiger

Table 3 (continued).Table 3 (continued).

Table 3 (continued).

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

+/- 50 ppm adjustment would be sufficient to

cope with most crystals, in fact the range is an

order of magnitude larger due to the use of

two 8 bit register locations. The setting of the

conf_nominal_frequency register allows for this

adjustment. An increase in the register value

increases the output frequencies by 0.02 ppm

for each LSB step. The default value (in decimal)

is 39321. The minimum being 0 and the

maximum 65535, giving a -700 ppm to +500

ppm adjustment range of the output

frequencies.

For example, if the crystal was oscillating at

12.8 MHz + 5 ppm, then the calibration value

in the register to give a - 5 ppm adjustment in

output frequencies to compensate for the

crystal inaccuracy, would be :

39321 - (5 / 0.02) = 39071 (decimal)

The ACS8515 supports up to three individual input

reference clock sources via TTL/CMOS and PECL/

LVDS technologies. These interface technologies

support +3.3 V and +5 V operation.

Input Reference Clock PortsInput Reference Clock Ports

Input Reference Clock Ports

The input reference clock ports are arranged in

groups. Group one comprises a TTL port (SEC1)

and a PECL/LVDS port (SEC1POS and

SEC1NEG). Group two comprises a TTL port

(SEC2) and a PECL/LVDS port (SEC2POS and

SEC2NEG). Group three comprises a TTL port

(SEC3). For group one and group two, only one

of the two input ports types must be active at

any time, the other must not be driven by a

reference input. Unused PECL/LVDS differential

inputs should be fixed with one input high (VDD)

and the other low (GND), or set in LVDS mode

and left floating (in which case one input is

internally pulled high and the other low).

SDH and SONET networks use different default

frequencies; the network type is selectable

using the config_mode register 34 Hex, bit 2.

For SONET, config_mode register 34 Hex, bit 2

= 1, for SDH config_mode register 34 Hex, bit

2 = 0. On power-up or by reset, the default will

be set by the state of the SONSDHB pin (pin

64). Specific frequencies and priorities are set

by configuration.

The TTL ports (compatible also with CMOS

signals) support clock speeds up to 100 MHz,

with the highest spot frequency being 77.76

MHz. Clock speeds above 100 MHz should not

be applied to the TTL ports. The PECL/LVDS

ports support the full range of clock speeds,

up to 155.52 MHz.

The actual spot frequencies supported are:

•2 kHz

•4 kHz

•8 kHz (and N x 8 kHz),

•1.544 MHz (SONET)/2.048 MHz (SDH),

•6.48 MHz,

•19.44 MHz,

•25.92 MHz,

•38.88 MHz,

•51.84 MHz,

•77.76 MHz,

•155.52 MHz.

The frequency selection is programmed via the

cnfg_ref_source_frequency register. The

internal DPLL will normally lock to the selected

input at the frequency of the input, eg.

19.44 MHz will lock the DPLL phase

comparisons at 19.44 MHz. It is, however,

possible to utilise an internal pre-divider to the

DPLL to divide the input frequency before it is

used for phase comparisons in the DPLL. This

pre-divider can be used in one of 2 ways;

1. Any of the supported spot frequencies can be divided to

8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate

cnfg_ref_source_frequency register location. For good jitter

tolerance for all frequencies and for operation at

19.44 MHz and above, use lock8K. It is possible to choose

which edge of the 8kHz input to lock to, by setting the

appropriate bit of the cnfg_control1 register.

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

2. Any multiple of any supported frequency can be

supported by using the "DivN" feature (bit 7 of the

cnfg_ref_source_frequency register). Any reference input

can be set to lock at 8 kHz independently of the

frequencies and configurations of the other inputs.

Any reference input with the ‘DivN’ bit set in

the cnfg_ref_source_frequency register will

employ the internal pre-divider prior to the DPLL

locking. The cnfg_freq_divn register contains

the divider ratio N where the reference input

will get divided by (N+1) where 0<N<214-1. The

cnfg_ref_source_frequency register must be set

to the closest supported spot frequency to the

input frequency, but must be lower than the

input frequency. When using the ‘DivN’ feature

the post-divider frequency must be 8 kHz, which

is indicated by setting the ‘lock8k’ bit high (bit

6 in cnfg_ref_source_frequency register). Any

input set to DivN must have the frequency

monitors disabled (if the frequency monitors

are disabled, they are disabled for all inputs

regardless of the input configurations, in this

case only activity monitoring will take place).

Whilst any number of inputs can be set to use

the ‘DivN’ feature, only one N can be

programmed, hence all inputs using the ‘DivN’

feature must require the same division to get

to 8 kHz.

emaNtroPemaNtroP emaNtroP emaNtroPemaNtroP troPtupnItroPtupnI troPtupnI troPtupnItroPtupnI ygolonhceTygolonhceT ygolonhceT ygolonhceTygolonhceT detroppuSseicneuqerFdetroppuSseicneuqerF detroppuSseicneuqerF detroppuSseicneuqerFdetroppuSseicneuqerFpuorGecruoSCESpuorGecruoSCES puorGecruoSCES puorGecruoSCESpuorGecruoSCES tluafeDtluafeD tluafeD tluafeDtluafeD ytiroirPytiroirP ytiroirP ytiroirPytiroirP

)3etoN(

1CESSOMC/LTT zHM001otpU)1etoN(

TENOS(tluafeDHDS/zHk8:) 11)4(

2CESSOMC/LTT zHM001otpU)1etoN(

TENOS(tluafeDHDS/zHk8:) 2)5(3

1CES LCEP/SDVL SDVLtluafed zHM25.551otpU)2etoN(

TENOS(tluafeDHDS/zHM44.91:) 1)6(2

2CES SDVL/LCEP tluafedLCEP zHM25.551otpU)2etoN(

/TENOS(tluafeDHDSzHM44.91:) 2)7(4

3CESSOMC/LTT zHM001otpU)1etoN(

TENOS(tluafeDHDS/zHM44.91:) 3)01(5

1CNYSSOMC/LTTcnySemarFitluMzHk2--

Table 4. Input Reference Source Selection and Group AllocationTable 4. Input Reference Source Selection and Group Allocation

Table 4. Input Reference Source Selection and Group Allocation

Notes for Table 4.Notes for Table 4.

Notes for Table 4.

Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency

being 77.76 MHz. The actual spot frequencies are 2 kHz, 4 kHz, 8 kHz, N x 8 kHz, 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz.

Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output

clock frequencies available for SONET and SDH applications.

Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the

ACS8510.

On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by

configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

rettiJrettiJ rettiJ rettiJrettiJ ecnareloTecnareloT ecnareloT ecnareloTecnareloT rotinoMycneuqerFrotinoMycneuqerF rotinoMycneuqerF rotinoMycneuqerFrotinoMycneuqerF egnaRecnatpeccAegnaRecnatpeccA egnaRecnatpeccA egnaRecnatpeccAegnaRecnatpeccA

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF egnaRecnatpeccAegnaRecnatpeccA egnaRecnatpeccA egnaRecnatpeccAegnaRecnatpeccA )ni-lluP()ni-lluP( )ni-lluP( )ni-lluP()ni-lluP(

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF ecnatpeccAecnatpeccA ecnatpeccA ecnatpeccAecnatpeccA )ni-dloH(egnaR)ni-dloH(egnaR )ni-dloH(egnaR )ni-dloH(egnaR)ni-dloH(egnaR

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF egnaRecnatpeccAegnaRecnatpeccA egnaRecnatpeccA egnaRecnatpeccAegnaRecnatpeccA )tuo-lluP()tuo-lluP( )tuo-lluP( )tuo-lluP()tuo-lluP(

307.G

mpp6.61-/+

mpp6.4-/+ )1etoNees(

mpp2.9-/+ )2etoNees(

mpp6.4-/+ )1etoNees(

mpp2.9-/+ )2etoNees(

mpp6.4-/+ )1etoNees(

mpp2.9-/+ )2etoNees(

387.G

328.G

EROC-4421-RG

PECL and LVDS ports support the spot clock

frequencies listed above plus 155.52 MHz. The

choice of PECL or LVDS compatibility is

programmed via the cnfg_differential_inputs

register.

Unused PECL/LVDS differential inputs should

be fixed with one input high (VDD) and the other

input low (GND), or set in LVDS mode and left

floating, in which case one input is internally

pulled high and the other low.

Input Wander and Jitter ToleranceInput Wander and Jitter Tolerance

Input Wander and Jitter Tolerance

The ACS8515 is compliant to the requirements

of all relevant standards, principally ITU

Recommendation G.825, ANSI DS1.101-1994

and ETS 300 462-5 (1997).

All reference clock inputs have a tight frequency

tolerance but a generous jitter tolerance. Pull-

in, hold-in and pull-out ranges are specified for

each input port in Table 5. Minimum jitter

tolerance masks are specified in Figures 3 and

4, and Tables 6 and 7, respectively. The

ACS8515 will tolerate wander and jitter

components greater than those shown in Figure

3 and Figure 4, up to a limit determined by a

combination of the apparent long-term

frequency offset caused by wander and the

eye-closure caused by jitter (the input source

will be rejected if the offset pushes the

frequency outside the hold-in range for long

enough to be detected, whilst the signal will

also be rejected if the eye closes sufficiently to

affect the signal purity). The ‘8klocking’ mode

should be engaged for high jitter tolerance

according to these masks.

All reference clock ports are monitored for

quality, including frequency offset and general

activity. Single short-term interruptions in

selected reference clocks may not cause

rearrangements, whilst longer interruptions, or

multiple, short-term interruptions, will cause

rearrangements, as will frequency offsets which

are sufficiently large or sufficiently long to cause

loss-of-lock in the phase-locked loop. The failed

reference source will be removed from the

priority table and declared as unserviceable,

until its perceived quality has been restored to

an acceptable level.

Notes for Table 5.Notes for Table 5.

Notes for Table 5.

Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the

external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.

Note 2. The default acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency

of 12.8 MHz. This range is also programmable from 0 to 80 ppm in 0.08 ppm steps.

Table 5. Input Reference Source Jitter ToleranceTable 5. Input Reference Source Jitter Tolerance

Table 5. Input Reference Source Jitter Tolerance

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ADVANCED COMMUNICATIONS FINAL

f0 f1 f2 f3 f4 f5 f6

A3

A2

A1

A0

Jitt er and wander freque ncy (l

f8 f9

A4

f0 f1 f2 f3 f4 f5 f6

A3

A2

A1

A0

Jitt er and wander freque ncy (l

f8 f9

A4

MTSMTS MTS MTSMTS levellevel level levellevel

edutilpmakaepotkaePedutilpmakaepotkaeP edutilpmakaepotkaeP edutilpmakaepotkaePedutilpmakaepotkaeP )lavretnItinu()lavretnItinu( )lavretnItinu( )lavretnItinu()lavretnItinu( )zH(ycneuqerF)zH(ycneuqerF )zH(ycneuqerF )zH(ycneuqerF)zH(ycneuqerF

0A0A0A0A0A1A1A1A1A1A2A2A2A2A2A3A3A3A3A3A4A4A4A4A4A0F0F0F0F0F1F1F1F1F1F2F2F2F2F2F3F3F3F3F3F4F4F4F4F4F5F5F5F5F5F6F6F6F6F6F7F7F7F7F7F8F8F8F8F8F9F9F9F9F9F

1-MTS0082113935.151.0u21u871m6.1m6.51521.03.91005k5.6k56m3.1

The registers sts_curr_inc_offset (address 0C,

0D, 07) report the frequency of the DPLL with

respect to the external TCXO frequency. This is

a 19 bit signed number with one LSB

representing 0.0003 ppm (range of +/- 80

ppm). Reading this regularly can show how the

currently locked source is varying in value e.g.

due to wander on its input.

The ACS8515 performs automatic frequency

monitoring with an acceptable input frequency

offset range of +/- 16.6 ppm. The ACS8515

DPLL has a programmable frequency limit of

+/- 80 ppm. If the range is programmed to be

> 16.6 ppm, the frequency monitors should be

disabled so the input reference source is not

automatically rejected as out of frequency

range.

Output Clock PortsOutput Clock Ports

Output Clock Ports

The ACS8515 supports two SEC output clocks,

on TTL and PECL/LVDS ports, and a pair of

secondary output clocks, ‘Frame-Sync’ and

‘Multi-Frame-Sync’. The two output clocks are

individually controllable. The ‘Frame-Sync’ and

‘Multi-Frame-Sync’ are derived from the main

SEC clock. The frequencies of the output clock

are selectable from a range of pre-defined spot

frequencies, with a variety of output

technologies supported, as defined in Table 8.

Low Speed Output ClockLow Speed Output Clock

Low Speed Output Clock

The O2 SEC clock is supplied on a TTL port with

a fixed frequency of 19.44 MHz.

Table 6. Amplitude and Frequency values for Jitter ToleranceTable 6. Amplitude and Frequency values for Jitter Tolerance

Table 6. Amplitude and Frequency values for Jitter Tolerance

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)

(for inputs supporting G.783 compliant sources)

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ADVANCED COMMUNICATIONS FINAL

epyTepyT epyT epyTepyT.cepS.cepS .cepS .cepS.cepS edutilpmAedutilpmA edutilpmA edutilpmAedutilpmA )kp-kpIU()kp-kpIU( )kp-kpIU( )kp-kpIU()kp-kpIU( ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF )zH()zH( )zH( )zH()zH(

1A1A1A1A1A2A2A2A2A2A1F1F1F1F1F2F2F2F2F2F3F3F3F3F3F4F4F4F4F4F

1SD1SD 1SD 1SD1SDEROC-4421-RGEROC-4421-RG EROC-4421-RG EROC-4421-RGEROC-4421-RG51.001005k8k04

1E1E1E1E1E328.GUTI328.GUTI 328.GUTI 328.GUTI328.GUTI5.12.002k4.2k81k001

f1 f2 f3 f4

A2

A1

P eak-t o- peak jitter and wander amplit ude (lo g

scale)

Ji t t er an d wander f requen cy ( l og s

c

f1 f2 f3 f4

A2

A1

P eak-t o- peak jitter and wander amplit ude (lo g

scale)

Ji t t er an d wander f requen cy ( l og s

c

High Speed Output ClockHigh Speed Output Clock

High Speed Output Clock

The O1 SEC clock is supplied on a PECL/LVDS

port with spot frequencies of;

•19.44 MHz,

•38.88 MHz,

•155.52 MHz,

•311.04 MHz,

•Dig 1.

(where Dig 1 is 1.544 MHz (SONET)/2.048 MHz

(SDH), and multiples of 2, 4 and 8 depending

on SONET/SDH mode setting).

The actual frequency is selectable via the

cnfg_differential_outputs register. The O1 port

can also support 311.04 MHz, which is enabled

via the cnfg_T0_output_enable register. The O1

port can be made LVDS or PECL compatible via

the cnfg_differential_outputs register.

Frame Sync and Multi-Frame Sync ClocksFrame Sync and Multi-Frame Sync Clocks

Frame Sync and Multi-Frame Sync Clocks

Frame Sync (8 kHz) and Multi-Frame Sync (2

kHz) clocks will be provided on outputs FrSync

and MFrSync. The FrSync and MFrSync clocks

have a 50:50 mark/space ratio.

Low Jitter Multiple E1/DS1 OutputsLow Jitter Multiple E1/DS1 Outputs

Low Jitter Multiple E1/DS1 Outputs

This feature added to Rev2.1 is activated using

the cnfg_control1 register. This sends a fre-

quency of twice the Dig2 rate (see reg addr 39h,

bits 7:6) to the APLL instead of the normal

77.76MHz. For this feature to be used, the Dig2

rate must only be set to 12352kHz/16384kHz

using the cnfg_T0_output_frequencies register.

The normal OC3 rate outputs are then replaced

with E1/DS1 multiple rates. The E1(SONET)/

DS1(SDH) selection is made in the same way as

for Dig2 using the cnfg_T0_output_enable reg-

ister. Table 9 shows the relationship between

primary output frequencies and the correspond-

ing output in E1/DS1 mode, and which output

they are available from.

Figure 4. Minimum Input Jitter Tolerance (DS1/E1)Figure 4. Minimum Input Jitter Tolerance (DS1/E1)

Figure 4. Minimum Input Jitter Tolerance (DS1/E1)

Table 7. Amplitude and Frequency values for Jitter ToleranceTable 7. Amplitude and Frequency values for Jitter Tolerance

Table 7. Amplitude and Frequency values for Jitter Tolerance

(for inputs supporting G.783 compliant sources)

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Notes for Table 8.Notes for Table 8.

Notes for Table 8.

Dig 1 is shown as either 1.544 MHz or 2.048 MHz, where 1.544 MHz is SONET and 2.048 MHz is SDH. Pin SONSDHB controls

the default frequency output. When SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.

Output Wander and JitterOutput Wander and Jitter

Output Wander and Jitter

Wander and jitter present on the output clocks

are dependent on:

1. The magnitude of wander and jitter on the selected

input reference clock (in locked mode);

2. The internal wander and jitter transfer characteristic

(in Locked mode);

3. The jitter on the local oscillator clock;

4. The wander on the local oscillator clock (in Holdover

mode).

Wander and jitter are treated in different ways

to reflect their differing impacts on network

design. Jitter is always strongly attenuated,

whilst wander attenuation can be varied to suit

the application and operating state. Wander and

jitter attenuation is performed by using a digital

phase-locked loop (DPLL) with a programmable

bandwidth. This gives a transfer characteristic

of a low pass filter, with a programmable pole.

It is sometimes necessary to change the filter

dynamics to suit particular circumstances - one

example being when locking to a new source,

the filter can be opened up to reduce locking

time and can then be gradually tightened again

to remove wander. Since wander represents a

relatively long-term deviation from the nominal

operating frequency, it affects the rate of supply

of data to the network element. Strong wander

attenuation limits the rate of consumption of

data to within a smaller range, so a larger buffer

store is required to prevent data loss. But, since

Table 8. Output Reference Source Selection TableTable 8. Output Reference Source Selection Table

Table 8. Output Reference Source Selection Table

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1O LCEP/SDVL tluafedSDVL 1giD,zHM40.113,zHM25.551,)tluafed(zHM88.83,zHM44.91 8dna4,2foselpitlumdnazHM840.2/zHM445.1si1giD

2OSOMC/LTTdexifzHM44.91

cnySrFSOMC/LTToitarecaps/kram05:05.zHk8,cnySrF

cnySrFMSOMC/LTToitarecaps/kram05:05.zHk2,cnySrFM

Table 9. Multiple E1/DS1 Ouputs in relation to Standard OutputsTable 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs

Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs

edoMedoM edoM edoMedoMotqerFotqerF otqerF otqerFotqerF LLPALLPA LLPA LLPALLPA LLPALLPA LLPA LLPALLPA reilpitluMreilpitluM reilpitluM reilpitluMreilpitluM LLPALLPA LLPA LLPALLPA qerFqerF qerF qerFqerF tlif_klctlif_klc tlif_klc tlif_klctlif_klc_klc_klc _klc _klc_klc 2/tlif2/tlif 2/tlif 2/tlif2/tlif _klc_klc _klc _klc_klc 4/tlif4/tlif 4/tlif 4/tlif4/tlif _klc_klc _klc _klc_klc 6/tlif6/tlif 6/tlif 6/tlif6/tlif _klc_klc _klc _klc_klc 8/tlif8/tlif 8/tlif 8/tlif8/tlif _klc_klc _klc _klc_klc 21/tlif21/tlif 21/tlif 21/tlif21/tlif _klc_klc _klc _klc_klc 61/tlif61/tlif 61/tlif 61/tlif61/tlif _klc_klc _klc _klc_klc 84/tlif84/tlif 84/tlif 84/tlif84/tlif LLPDLLPD LLPD LLPDLLPD qerFqerF qerF qerFqerF

tluafeD67.774 40.11340.11325.55167.7748.1588.8329.5244.9184.667.77

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1Txn407.424618.89618.89804.94407.42407.42 407.42 407.42407.4233964.61253.21253.21 253.21 253.21253.21766432.8671.6671.6 671.6 671.6671.6766850.267.77

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

any buffer store potentially increases latency,

wander may often only need to be removed at

specific points within a network where buffer

stores are acceptable, such as at digital cross

connects. Otherwise, wander is sometimes not

required to be attenuated and can be passed

through transparently. The ACS8515 has

programmable wander transfer characteristics

in a range from 0.1 Hz to 20 Hz. The wander

and jitter transfer characteristic is shown in

Figure 5.

Wander on the local oscillator clock will not

have significant effect on the output clock whilst

in locked mode, so long as the DPLL bandwidth

is set high enough so that the DPLL can

compensate quickly enough for any frequency

changes in the crystal. In Free-run or Holdover

mode wander on the crystal is more significant.

Variation in crystal temperature or supply

voltage both cause drifts in operating frequency,

as does ageing. These effects must be limited

by careful selection of a suitable component

for the local oscillator, as specified in the section

‘Local Oscillator Clock’.

Phase VariationPhase Variation

Phase Variation

There will be a phase shift across the ACS8515

between the selected input reference source

and the output clock. This phase shift may vary

over time but will be constrained to lie within

specified limits. The phase shift is characterized

using two parameters, MTIE (Maximum Time

Interval Error), and TDEV (Time Deviation), which,

although being specified in all relevent

specifications, differ in acceptable limits in each

one. Typical measurements for the ACS8515

are shown in Figures 6 and 7, for locked mode

operation. Figure 8 shows a typical

measurement of Phase Error accumulation in

Holdover mode operation.

The required performance for phase variation

during Holdover is specified in several ways

depending upon the particular circumstances

pertaining:

1. ETSI 300 462-5, Section 9.1, requires that the short-

term phase error during switchover (i.e., Locked to Holdover

to Locked) be limited to an accumulation rate no greater

than 0.05 ppm during a 15 second interval.

5

0

-3

-5

-10

-15

-20

-25

-30

Gain (dB)

0.01 0.1 110 100 1000

Frequenc y (Hz)

0.1 Hz

0.3 Hz

0.5 Hz

1.0 Hz

2.0 Hz

4.0 Hz

8.0 Hz

17 Hz

Figure 5. Wander and Jitter Transfer Measured CharacteristicsFigure 5. Wander and Jitter Transfer Measured Characteristics

Figure 5. Wander and Jitter Transfer Measured Characteristics

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

10

1

0.1

0.01

Time

(ns)

0.01 0.1 110 100 1000 10000

Ob s e rv a tio n interv a l (s)

G .813 optio n 1 con stan t tem perature w ander lim it

TD EV m easurem e nt on 155 M H z output, 19.44 M Hz i/p (8kHz locking),

Vectron 6664 xtal

100

10

1

0.1

0.01

0.01 0.1 110 100 1000 10000

Observation interval

(

s

)

Time

(ns)

G.813 option 1, constant tem perature wander lim it

M TIE measurement on 155 M Hz output, 19.44 MHz i/p (8kH z locking),

Vectron 6664 xtal

10000000

1000000

100000

10000

1000

100 1000 10000 100000

Ob ti i t l( )

Phase Error (ns)

Permitted Phase Error Limit

Typical m easurem ent, 25°C constant tem perature

Figure 6. Maximum Time Interval Error of TFigure 6. Maximum Time Interval Error of T

Figure 6. Maximum Time Interval Error of TOUT0OUT0

OUT0OUT0

OUT0 Output Port Output Port

Output Port Output Port

Output Port

Figure 7. Time Deviation of TFigure 7. Time Deviation of T

Figure 7. Time Deviation of TOUT0OUT0

OUT0OUT0

OUT0 Output Port Output Port

Output Port Output Port

Output Port

Figure 8. Phase Error Accumulation of TFigure 8. Phase Error Accumulation of T

Figure 8. Phase Error Accumulation of TOUT0OUT0

OUT0OUT0

OUT0 Output Port in Holdover Mode Output Port in Holdover Mode

Output Port in Holdover Mode Output Port in Holdover Mode

Output Port in Holdover Mode

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

2. ETSI 300 462-5, Section 9.2, requires that the long-

term phase error in the Holdover mode should not exceed

{(a1+a2)S+0.5bS2+c}

where

a1 = 50 ns/s (allowance for initial frequency offset)

a2 = 2000 ns/s (allowance for temperature variation)

b = 1.16x10-4 ns/s2 (allowance for ageing)

c = 120 ns (allowance for entry into Holdover mode).

3. ANSI Tin1.101-1994, Section 8.2.2, requires that the

phase variation be limited so that no more than 255 slips

(of 125 µs each) occur during the first day of Holdover.

This requires a frequency accuracy better than:

((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm

Temperature variation is not restricted, except to within

the normal bounds of 0 to 50 Celsius.

4. Bellcore GR.1244.CORE, Section 5.2., Table 4, shows

that an initial frequency offset of 50 ppb is permitted on

entering Holdover, whilst a drift over temperature of 280

ppb is allowed; an allowance of 40 ppb is permitted for all

other effects.

5. ITU G.822, Section 2.6, requires that the slip rate during

category(b) operation (interpreted as being applicable to

Holdover mode operation) be limited to less than 30 slips

(of 125 µs each) per hour

((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm

Phase Build OutPhase Build Out

Phase Build Out

Phase Build Out (PBO) is the function to minimise

phase transients on the output SEC clock during

input reference switching or mode switching. If

the currently selected input reference clock

source is lost (due to a short interruption, out

of frequency detection, or complete loss of

reference), the second, next highest priority

reference source will be selected. During this

transition, the Lost_Phase mode is entered.

The typical phase disturbance on clock

reference source switching will be less than

10 ns on the ACS8515. For clock reference

switching caused by the main input failing or

being disconnected, then the phase disturbance

on the output will still be less than the 120 ns

allowed for in the G.813 spec. The actual

value is dependant on the frequency being

locked to.

The PBO requirement, as specified in Telcordia

GR1244-CORE, Section 5.7, in that a phase

transient of greater than 3.5 µs occuring in

less than 0.1 seconds should be absorbed, will

be implemented on a future version. ITU-T

G.813 states that the max allowable short term

phase transient response, resulting from a

switch from one clock source to another, with

Holdover mode entered in between, should be

a maximum of 1 µs over a 15 second interval.

The maximum phase transient or jump should

be less than 120 ns at a rate of change of less

than 7.5 ppm and the Holdover performance

should be better than 0.05 ppm.

On the ACS8515, PBO can be enabled, disabled

or frozen using the µP interface. By default, it

is enabled. When PBO is enabled, it can also

be frozen, which will disable the PBO operation

on the next input reference switch, but will

remain with the current offset. If PBO is

disabled while the device is in the Locked mode,

there will be a phase jump on the output SEC

clocks as the DPLL locks back to 0 degree

phase error.

Microprocessor InterfaceMicroprocessor Interface

Microprocessor Interface

The ACS8515 incorporates a serial

microprocessor interface that is compatible with

the Serial Peripheral Interface (SPI) for device

setup.

Register SetRegister Set

Register Set

All registers are 8-bits wide, organised with the

most-significant bit positioned in the left-most

bit, with bit-significance decreasing towards the

right-most bit. Some registers carry several

individual data fields of various sizes, from

single-bit values (e.g., flags) upwards. Several

data fields are spread across multiple registers;

their organisation is shown in the register map.

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Configuration RegistersConfiguration Registers

Configuration Registers

Each configuration register reverts to a default

value on power-up or following a reset. Most

default values are fixed, but some will be pin-

settable. All configuration registers can be read

out over the microprocessor port.

Status RegistersStatus Registers

Status Registers

The Status Registers contain readable registers.

They may all be read from outside the chip but

are not writable from outside the chip (except

for a clearing operation). All status registers

are read via shadow registers to avoid data

hits due to dynamic operation. Each individual

status register has a unique location.

Register AccessRegister Access

Register Access

Most registers are of one of two types,

configuration registers or status registers, the

exceptions being the chip_revision register.

Configuration registers may be written to or read

from at any time (the complete 8-bit register

must be written, even if only one bit is being

modified). All status registers may be read at

any time and, in some status registers (such as

the sts_interrupts register), any individual data

field may be cleared by writing a ‘1’ into each

bit of the field (writing a ‘0’ value into a bit will

not affect the value of the bit). Details of each

register are given in the Register Map and

Register Map Description sections.

Interrupt Enable and ClearInterrupt Enable and Clear

Interrupt Enable and Clear

Interrupt requests are flagged on pin INTREQ

(active High).

Bits in the interrupt status register are set (high)

by the following conditions;

1. Any reference source becoming valid or going invalid

2. A change in the operating state (eg. Locked, Holdover

etc.)

3. A brief loss of the currently selected reference source

All interrupt sources are maskable via the mask

register cnfg_interrupt_mask, each one being

enabled by writing a '1' to the appropriate bit.

Any unmasked bit set in the interrupt status

register will cause the interrupt request pin to

be asserted (high).

All interrupts are cleared by writing a '1' to the

bit(s) to be cleared in the status register.

When all pending unmasked interrupts are

cleared the interrupt pin will go inactive (low).

The loss of the currently selected reference

source will eventually cause the input to be

considered invalid, triggering an interrupt. The

time taken to raise this interrupt is dependent

on the leaky bucket configuration of the activity

monitors. The very fastest leaky bucket setting

will still take up to 128 ms to trigger the

interrupt. The interrupt caused by the brief

loss of the currently selected reference source

is provided to facilitate very fast source failure

detection if desired. It is triggered after missing

just a couple of cycles of the reference source.

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Shaded areas in the map are ‘don’t care’ and writing either 0 or 1 will not affect any function of

the device.

Bits labelled ‘Set to 0’ or ‘Set to 1’ must be set as stated during initialisation of the device,

either following power up, or after a power on reset (PORB). Failure to correctly set these bits

may result in the device operating in an unexpected way.

Some registers do not appear in this list, for example 07 and 08. These are either not used, or

have test functionality. Do not write to any undefined registers as this may cause the device to

operate in a test mode. If an undefined register has been inadvertently addressed, the device

should be reset to ensure the undefined registers are at default values.

Register MapRegister Map

Register Map

Table 10. Register MapTable 10. Register Map

Table 10. Register Map

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6

6655

5

5544

4

4433

3

3322

2

2211

1

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

20 noisiver_pihc )ylnodaer( )0:7(rebmunnoisiverpihC

30 1lortnoc_gfnc )etirw/daer( '0'otteS golanA cnysvid '0'otteS egdEk8 ytiraloP '0'otteS'0'otteS

40 2lortnoc_gfnc )etirw/daer( timilgalfssolesahP'0'otteS'1'otteS'0'otteS

50 stpurretni_sts )etirw/daer( FFID2CESFFID1CES2CES1CES

60 gnitarepO edom ferniaM deliaf 3CES

90 edom_gnitarepo_sts )ylnodaer( )0:2(edomgnitarepO

A0 elbat_ytiroirp_sts )ylnodaer( ecruosdilavytiroirptsehgiH ecruosecnereferdetcelesyltnerruC

B03

dr

ecruosdilavytiroirptsehgih2

dn

ecruosdilavytiroirptsehgih

C0 tesffo_cni_rruc_sts )ylnodaer( )0:7(tesffotnemercnitnerruC

D0 )8:51(tesffotnemercnitnerruC

70 )61:81(tesffotnemercnitnerruC

E0 dilav_secruos_sts )ylnodaer( FFID2CESFFID1CES2CES1CES

F0 3CES

11 secruos_ecnerefer_sts )etirw/daer( >2CES<sutats>1CES<sutats

21>FFID2CES<sutats >FFID1CES<sutats

41 >3CES<sutats

81 ytiroirp_noitceles_fer_gfnc )etirw/daer( '0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS

91 >2CES<ytiroirp_demmargorp >1CES<ytiroirp_demmargorp

A1 >FFID2CES<ytiroirp_demmargorp >FFID1CES<ytiroirp_demmargorp

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ADVANCED COMMUNICATIONS FINAL

Table 10. Register Map (continued).Table 10. Register Map (continued).

Table 10. Register Map (continued).

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6

6655

5

5544

4

4433

3

3322

2

2211

1

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

B1 ytiroirp_noitceles_fer_gfnc )etirw/daer( )deunitnoc(

'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS

C1'0'otteS'0'otteS'0'otteS'0'otteS>3CES<ytiroirp_demmargorp

D1'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS

E1'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS

22 ycneuqerf_ecruos_fer_gfnc )etirw/daer( nvidk8kcol)0:1(>1CES<di_tekcub )0:3(>1CES<ycneuqerf_ecruos_ecnerefer

32nvidk8kcol)0:1(>2CES<di_tekcub )0:3(>2CES<ycneuqerf_ecruos_ecnerefer

42nvidk8kcol di_tekcub )0:1(>FFID1CES< )0:3(>FFID1CES<ycneuqerf_ecruos_ecnerefer

52nvidk8kcol di_tekcub )0:1(>FFID2CES< )0:3(>FFID2CES<ycneuqerf_ecruos_ecnerefer

82nvidk8kcol)0:1(>3CES<di_tekcub )0:3(>3CES<ycneuqerf_ecruos_ecnerefer

23 edom_gnitarepo_gfnc )etirw/daer( edomgnitarepodecroF

33 noitceles_fer_gfnc )etirw/daer( ecruos_ecnerefer_tceles_ecrof

43

edom_gfnc )etirw/daer( otuA lanretxe elbanek2

esahP mrala tuoemit elbane

kcolC egde '0'otteS k2lanretxE elbanecnyS /TENOS P/IHDS evitreveR edom

53 3lortnoc_gfnc )etirw/daer( '1'otteS'0'otteS

63 stupni_laitnereffid_gfnc )etirw/daer( FFID2CES LCEP FFID1CES LCEP

83 elbane_tuptuo_gfnc )etirw/daer( 40.113 1OnozHM

TENOS=1 HDS=0 1giDrof '0'otteS'0'otteSelbane2O'0'otteS'0'otteS

93 seicneuqerf_tuptuo_1O_gfnc )etirw/daer( 1latigiD

A3 tuptuo_laitnereffid_gfnc )etirw/daer( noitcelesycneuqerf1O'0'otteS'0'otteS SDVL1O elbane LCEP1O elbane

B3 htdiwdnab_gfnc )etirw/daer( w/botuA hctiws kcol/qca htdiwdnabnoitisiuqcA'0'otteShtdiwdnabdekcol/lamroN

C3 ycneuqerf_lanimon_gfnc )etirw/daer( )0:7(ycneuqerflanimoN

D3 )8:51(ycneuqerflanimoN

04 tesffo_revodloh_gfnc )etirw/daer( '0'otteS

14 timil_qerf_gfnc )etirw/daer( )0:7(timiltesffoycneuqerFLLPD

24 tesffoycneuqerFLLPD )8:9(timil

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ADVANCED COMMUNICATIONS FINAL

Table 10. Register Map (continued).Table 10. Register Map (continued).

Table 10. Register Map (continued).

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6

6655

5

5544

4

4433

3

3322

2

2211

1

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

34 ksam_tpurretni_gfnc )etirw/daer( '0'otteS'0'otteS sutats FFID2CES sutats FFID1CES sutats 2CES sutats 1CES '0'otteS'0'otteS

44edom.repOferniaM'0'otteS'0'otteS'0'otteS'0'otteS'0'otteS sutats 3CES

54 '0'otteS'0'otteS'0'otteS'0'otteS'0'otteS

64 nvid_qerf_gfnc )etirw/daer( )0:7(oitarn-yb-tupni-ediviD

74 )8:31(oitarn-yb-tupni-ediviD

84

srotinom_gfnc )etirw/daer( tsaf-artlU gnihctiws

lanretxE ecruos hctiws elbane

ezeerF esahp tuodliub

esahP tuodliub elbane

srotinomycneuqerF )0:1(noitarugifnoc

05 0dlohserht_reppu_vitca_gfnc )etirw/daer( )0:7(dlohserhttesmralaytivitcA:0noitarugifnoC

15 0dlohserht_rewol_vitca_gfnc )etirw/daer( )0:7(dlohserhttesermralaytivitcA:0noitarugifnoC

25 0ezis_tekcub_gfnc )etirw/daer( )0:7(ezistekcubmralaytivitcA:0noitarugifnoC

35 0etar_yaced_gfnc )etirw/daer( :0noitarugifnoC )0:1(etar_yaced

45 1dlohserht_reppu_vitca_gfnc )etirw/daer( )0:7(dlohserhttesmralaytivitcA:1noitarugifnoC

55 1dlohserht_rewol_vitca_gfnc )etirw/daer( )0:7(dlohserhttesermralaytivitcA:1noitarugifnoC

65 1ezis_tekcub_gfnc )etirw/daer( )0:7(ezistekcubmralaytivitcA:1noitarugifnoC

75 1etar_yaced_gfnc )etirw/daer( :1noitarugifnoC )0:1(etar_yaced

85 2dlohserht_reppu_vitca_gfnc )etirw/daer( )0:7(dlohserhttesmralaytivitcA:2noitarugifnoC

95 2dlohserht_rewol_vitca_gfnc )etirw/daer( )0:7(dlohserhttesermralaytivitcA:2noitarugifnoC

A5 2ezis_tekcub_gfnc )etirw/daer( )0:7(ezistekcubmralaytivitcA:2noitarugifnoC

B5 2etar_yaced_gfnc )etirw/daer( :2noitarugifnoC )0:1(etar_yaced

C5 3dlohserht_reppu_vitca_gfnc )etirw/daer( )0:7(dlohserhttesmralaytivitcA:3noitarugifnoC

D5 3dlohserht_rewol_vitca_gfnc )etirw/daer( )0:7(dlohserhttesermralaytivitcA:3noitarugifnoC

E5 3ezis_tekcub_gfnc )etirw/daer( )0:7(ezistekcubmralaytivitcA:3noitarugifnoC

F5 3etar_yaced_gfnc )etirw/daer( :3noitarugifnoC )0:1(etar_yaced

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ADVANCED COMMUNICATIONS FINAL

Table 11. Register Map DescriptionTable 11. Register Map Description

Table 11. Register Map Description

Register Map DescriptionRegister Map Description

Register Map Description

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

20noisiver_pihc rebmunnoisiverpihcehtsniatnocretsigerylno-daersihT 1=noisiversihT 0=)selpmasgnireenigne(noisivertsaL

10000000

30

1lortnoc_gfncdesunU)6:7(stiB

5tiB .zhM67.77lamronehtfodaetsniLLPAehtotycneuqerf2giDx2sdeeF:LLPAotzHM42/231= stibtes2giD:etoN.setar1T/1Eelpitlumhtiwdecalpererastuptuo1MTS/3COlamronehtsuhT .edomsihtrof11ottesebtsum))6:7(stiBh93.geR( LLPAotzHM67.770=

4tiB noitcesLLPDehtnisredividehtotnoitcesLLPAtuptuoehtnisredividehtsezinorhcnyS1= stupnineewtebtnemngilaesahpevahotredroniyrassecensisihT.ngilasesahpriehttahthcus ebyamhgihtibsihtgnipeeK.)zHM67.77otzHM84.6(setardevired3COtaskcolctuptuodna ycneuqerfnisegnahckciuqnehwnoitazinorhcnysfotuognittegsredividehtdiovaotyrassecen .nuR-eerFotniecrofasahcusrucco ehtedomsihtnitub,ycneuqerfnisegnahcpetsgniwollofesahpfotuotegyamsredividehT0= ehT.doirepnoitazinorhcnysynanihtiwdeetneraugsisegdeycneuqerfhgihforebmuntcerroc .)tluafed(kcolycneuqerflliwtuptuo tluafedehterofeb,teseramorfsdnoces2noitazinorhcnysniniamersyawlalliwecivedehT .seilppagnittes

'0'ottesro,degnahcnuevael-lortnoctseT3stiB

2tiB .egdekcolctupnignisirehtotkcollliwmetsysehtedomgnikcolk8ninehW1= .egdekcolctupnignillafehtotkcollliwmetsysehtedomgnikcolk8ninehW0=

'00'ottesro,degnahcnuevael-slortnoctseT)0:1(stiB

000000XX

402lortnoc_gfnc.desunU)6:7(stiB

otsdnopserrochcihw)001(4ottestluafedyB.timilgalfssolesahpehtenifed)3:5(stiB timilgalfehT.timilesahprewolgnidnopserrocasteseulavrewolA.°041yletamixorppa esahpa,rettijtupnifotluserasatsolesahpsetacidniLLPDehthcihwtaeulavehtsenimreted .tupniehtnopmujycneuqerfaro,pmuj

.'010'ottesrodegnahcnuevael-slortnoctseT)0:2(stiB

010001XX

stpurretni_sts ehtecnereferfossolrofeno,dilav_secruos_stsfotibhcaeroftibenosniatnocretsigersihT .hgihevitcaerastibllA.edomgnitarepoehtrofrehtonadna,otdekcolsawecived

tnevelerehtfoetatsehtni'egnahc'anotesera)41tib(tib'deliafferniam'ehttpecxestibllA ehtfI.tpurretninareggirtlliwtidilavniseogro,dilavsemocebecruosafi.e.i,tibsutats .detarenegeblliwtpurretniehtetatssegnahc)9retsiger(edoMgnitarepO

ecnereferehtnoytivitcanigalfotdesusiretsigersutatstpurretniehtfo)deliafferniam(41tiB fo6tibfI.troppusnacsrotinomytivitcaehtnahtylkciuqeromhcumotdekcolsiecivedehttaht sitibsihtfoetatsehtneht,tessi)ODTnossolfergalf()84retsiger(retsigersrotinom_gfnceht .ecivedehtfonipODTehtotnonevird

deraelcebyamtibhcaE.retsigerksam_tpurretni_gfncehtnistibehtybelbaksamerastibllA ebnacstibforebmunynA.tpurretniehtgnittesersuht,tibtahtot'1'agnitirwybyllaudividni .tceffeonevahlliws'0'gnitirW.noitarepoetirwelgnisahtiwderaelc

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

50stpurretni_sts )deunitnoc( desunU)6:7(stiB

)5tibstpurretni_sts(FFID2CES5tiB

)4tibstpurretni_sts(FFID1CES4tiB

)3tibstpurretni_sts(2CES3tiB

)2tibstpurretni_sts(1CES2tiB

desunU)0:1(stiB

XX0000XX

60 )51tibstpurretni_sts(edomgnitarepO7stiB

)41tibstpurretni_sts(deliafferniaM6tiB

desunU)1:5(stiB

)8tibstpurretni_sts(3CES0tiB

0XXXXX00

90edom_gnitarepo_sts 01erugiF.enihcametatsniamehtfoetatsgnitarepotnerrucehtsdlohretsigerylno-daersihT .setatslaudividniehthtiwhctamelbairav'etatsgnitarepo'ehtfoseulavehtwohwohs

desunU)3:7(stiB

etatS)0:2(stiB )tluafed(nureerF100 revodloH010 dekcoL001 dekcol-erP011 2dekcol-erP101 tsolesahP111

100XXXXX

elbat_ytiroirp_sts.retsigerylno-daertib-61asisihT

ecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgih-drihT)21:51(stiB .ecruosdilavytiroirp-tsehgih-dnocesehtotytiroirptsehgih-txenehtsahdnadilavsihcihwecruos

ecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgih-dnoceS)8:11(stiB .ecruosdilavytiroirp-tsehgihehtotytiroirptsehgih-txenehtsahdnadilavsihcihwecruos

ecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirp-tsehgiH)4:7(stiB detceles-yltnerrucehtsaemasehtebtonyamti;ytiroirptsehgihehtsahdnadilavsihcihw .)ytiroirpdemmargorpnisegnahcroyrotsiheruliafoteud(ecruosecnerefer

ecnerefertupniehtforebmunlennahcehtsisiht:ecruosecnereferdetceles-yltnerruC)0:3(stiB .LLPDehtottupniyltnerrucsihcihwecruos

ehtfostnetnocehtotesnopsernienihcametatsehtybdetadpuerasretsigeresehttahtetoN lennahc;slennahclaudividnifosutatsgniognoehtdnaretsigerytiroirp_noitceles_fer_gfnc tahtrofelbaliavasilennahcontahtsetacidni,sretsigeresehtfoynanigniraeppa,'0000'rebmun .ytiroirp

A0 ))4:7(stibelbat_ytiroirp_sts(ecruosdilavytiroirp-tsehgiH)4:7(stiB ))0:3(stibelbat_ytiroirp_sts(ecruosecnereferdetcelesyltnerruC)0:3(stiB 00000000

B0 3)4:7(stiB

dr

))21:51(stibelbat_ytiroirp_sts(ecruosdilavytiroirp-tsehgih-

2)0:3(stiB

dn

))8:11(stibelbat_ytiroirp_sts(ecruosdilavytiroirp-tsehgih- 00000000

tesffo_cni_rruc_sts ehtfostibtnacifingis91ehtgnitneserpereulavregetni-dengisasniatnocretsigerylno-daersihT apudliubotyllacidoirepdaerebyamretsigerehT.LLPlatigidehtfotesffotnemercnitnerruc nafiyrassecenebylnodluowsiht(sdoireprevodlohgnirudesuretalrofesabatadlacirotsih kcolCrotallicsOlacoLnidebircsedairetircytilibatsehtteemtondidhcihwrotallicsolanretxe .teserretfayletaidemmi00000000daerlliwretsigerehT.)desusinoitces

C0 )0:7(stibtesffo_cni_rruc_sts)0:7(stiB 00000000

D0 )8:51(stibtesffo_cni_rruc_sts)0:7(stiB 00000000

70desunU)3:7(stiB

)61:81(stibtesffo_cni_rruc_sts)0:2(stiB 000XXXXX

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com23

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

dilav_secruos_sts .ecruosecnereferyreverofytidilavwohsottibasniatnocretsigersihT ecruosdilaV1= )tluafed(ecruosdilavnI0=

E0

desunU)6:7(stiB

FFID2CES5tiB

FFID1CES4tiB

2CES3tiB

1CES2tiB

desunU)0:1(stiB

XX0000XX

F0 desunU)1:7(stiB

3CES0tiB 0XXXXXXX

secruos_ecnerefer_sts ecnereferhcaefosutatsehT.secruosecnerefertupniehtfohcaefosutatsehtsdlohretsigersihT hcaefoypoca,gnikcehcsutatsdiaoT.hgihevitcasitibhcaE.dleiftib-4aninwohssiecruos hcaE(:swollofsadetropersisutatsehT.retsigerdilav_secruos_stsehtnidedivorpsi3tibsutats )yllaudividnideraelcebyamtib

)0tluafed()2-0stibfonoitanibmocsi3tib()smralaon(dilavecruoS=3tibsutatS )1tluafed(mraladnab-fo-tuO=2tibsutatS )1tluafed(mralaytivitcaoN=1tibsutatS )0tluafed(mralakcolesahP=0tibsutatS

11 2CESecruosecnerefertupnifosutatS)4:7(stiB

1CESecruosecnerefertupnifosutatS)0:3(stiB 01100110

21 FFID2CESecruosecnerefertupnifosutatS)4:7(stiB

FFID1CESecruosecnerefertupnifosutatS)0:3(stiB 01100110

41 desunU)4:7(stiB

3CESecruosecnerefertupnifosutatS)0:3(stiB 0110XXXX

ytiroirp_noitceles_fer_gfnc llaeraseulavytiroirpehT.secruosecnerefertupniehtfohcaefoytiroirpehtsdlohretsigersihT ot1seulavehtylnO.seitiroirprehgihgnikatsrebmundeulav-rewolhtiw,rehtohcaeotevitaler anevigebtsumecruosecnereferhcaE.ecruosecnereferehtselbasid'0'-dilavera)ced(51 nitsrifanodengissaeblliwrebmunytiroirpemasehtnevigsecruosowtrevewoh,ytiroirpeuqinu .sisabtuotsrif

noitcelesecnerefergnicrofnehwdesusisihtsa'1'eulavytiroirpehtevreserotdednemmocersitI noitceles_fer_gfncehtesuotdnetnitonseodresuehtfI.retsigernoitceles_fer_gfncehtaiv .devreserebtondeen'1'eulavytiroirpnehtretsiger

81 noitasilaitinignirud'00000000'ottesebtsuM)0:7(stiB 01001100

91 2CESecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

1CESecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB 00101010

A1 FFID2CESecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

FFID1CESecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB 01101110

B1 noitasilaitinignirud'00000000'ottesebtsuM)0:7(stiB 00011001

C1 noitasilaitinignirud'0000'ottesebtsuM)4:7(stiB

3CESecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB 01011101

D1 noitasilaitinignirud'00000000'ottesebtsuM)0:7(stiB 10001011

E1 noitasilaitinignirud'00000000'ottesebtsuM)0:7(stiB 01111111

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com24

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

ycneuqerf_ecruos_fer_gfnc .secruosecnerefertupniehtfohcaeputesotdesusiretsigersihT

ecnadroccani,ycneuqerftupniehtnonekatrednunoitarepoehtenifedetybhcaefo)6:7(stiB :yekgniwollofehthtiw

.)tluafed(LLPDehtotniyltceriddefsiycneuqerftupniehT00 ehtotnidefgnieberofeb,zHk8otnwoddedividyllanretnisiycneuqerftupniehT10 .)ecnarelotrettijhgihroF(.LLPD esutonod-noitarugifnocdetroppusnU01 edividot)nvid_qerf_gfnc(74&64sretsigerniderotstneiciffeocnoisividehtsesU11 srotinomycneuqerfehT.LLPDehtotnidefgniebotroirpeulavsihtybtupnieht ycneuqerfehT.zHk8lauqedluohsycneuqerfnwoddedividehT.delbasidebtsum tupnilautcaehtwolebtsujycneuqerftopstseraenehtottesebdluohs)0:3( dnazHM445.1neewtebseicneuqerftupnirofskrowerutaefNviDehT.ycneuqerf .zHM001

05sretsigernidenifedsa,desuera)3-0(sgnittestekcubykaelhcihwenifedrehtegot)4:5(stiB .)00tluafed(.F5ot

:yekgniwollofehthtiwecnadroccaniecruosecnereferehtfoycneuqerfehtenifed)0:3(stiB

)2CES,1CEStluafed(zHk80000 )2tib,43retsigeRybdenifedsA()HDS(zHk8402/)TENOS(zHk44511000 zHM84.60100 )3CES,FFID2CES,FFID1CEStluafed(zHM44.911100 zHM29.520010 zHM88.831010 zHM48.150110 zHM67.771110 zHM25.5510001 zHk21001 zHk40101

221CESecruosecnereferfoycneuqerF 00000000

322CESecruosecnereferfoycneuqerF 00000000

42 FFID1CESecruosecnereferfoycneuqerF 11000000

52 FFID2CESecruosecnereferfoycneuqerF 11000000

823CESecruosecnereferfoycneuqerF 11000000

23

edom_gnitarepo_gfnc yranibehtybdetneserper,etatsgnitarepoderisedaotniecivedehtecrofotdesusiretsigersihT etarepootenihcametatslortnocehtswolla)xeh(0eulaV.01erugiFninwohsseulav .yllacitamotua

desunU)3:7(stiB

)01erugiFrepsa(etatsgnitarepoderiseD)0:2(stiB

000XXXXX

33

noitceles_fer_gfnc evitcepserri,ecruosecnerefertupniralucitrapatcelesotecivedehtecrofotdesusiretsigersihT dedivorP.'1'ytiroirpottupnidetcelesehtsesiaryliraropmetretsigersihtotgnitirW.ytiroirpstifo lliwecruossiht,nosiedomevitreverdna,'1'ytiroirphtiwdemmargorpydaerlasitupnirehtoon .detceleseb

desunU)4:7(stiB

)0:3(stiB noitcelescitamotuA0000 1CES1100 2CES0010 FFID1CES1010 FFID2CES0110 3CES1001 )tluafed(noitcelescitamotuA1111 .desuebtondluohsseulavrehtO

1111XXXX

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com25

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

43

edom_gfnc :wolebdeliatedsa,sdleifnoitarugifnoclaudividnilarevessniatnocretsigersihT

7tiB dekcolsiecruosehtnehwylnodelbaneeblliwcnySzHk2lanretxE:elbanEcnySzHk2otuA1= .)tluafed(.delbasideblliwtiesiwrehtO.zHM84.6ot sa,retsigersihtfo3tibgnisunoitcnufsihtslortnocresuehT:elbasiDcnySzHk2otuA0= .wolebdebircsed

6tiB .)tluafed(.sdnoces001retfatuoemitlliwmralaesahpehT:elbanetuoemiTmralAesahP1= ybteserebtsumdnatuoemittonlliwmralaesahpehT:elbasidtuoemiTmralAesahP0= .erawtfos

5tiB lanretxeehtfoegdegnisirehtotecnereferlliwecivedehT:detcelesegdEkcolCgnisiR1= .langisrotallicso lanretxeehtfoegdegnillafehtotecnereferlliwecivedehT:detcelesegdEkcolCgnillaF0= .)tluafed(langisrotallicso

.noitasilaitinignirud'0'ottesebtsuM.desunU4tiB

3tiB detarenegyllanretnistifoesahpehtngilalliwecivedehT:elbanEcnySzHk2lanretxE1= deilppuslangisehtfotahthtiw)zHk2(langiscnySemarF-itluMdna)zHk8(langiscnySemarF .0158SCAnafocnySemarF-itluMzHk2ehtmorfebdluohstupnisihT.nipk2cnySehtot .)tluafed(nipk2cnySehterongilliwecivedehT:elbasiDcnySzHk2lanretxE0=

2tiB eulavehtneviglennahctupniynafoycneuqerftupniehtstcepxeecivedehT:edomTENOS1= .zHk4451ebotretsigerycneuqerf_ecruos_fer_gfncehtni'1000' eulavehtneviglennahctupniynafoycneuqerftupniehtstcepxeecivedehT:edomHDS0= .zHk8402ebotretsigerycneuqerf_ecruos_fer_gfncehtni'1000' gnittessihT.BHDSNOSnipfognittesehtotdetluafedeblliweulavtibehtteserroputratstA .eulavtibsihtgnignahcybderetlaebyltneuqesbusnac

desunU1tiB

0tiB ninwohsecruosytiroirptsehgihehtothctiwslliwecivedehT:edoMevitreveR1= .)4:7(stib,retsigerelbat_ytiroirp_sts .)tluafed(ecruosdetcelesyltneserpehtniaterlliwecivedehT:edoMevitrever-noN0=

0X00X011 )0=BHDSNOS( 0X10X011 )1=BHDSNOS(

53

3lortnoc_gfncdesunU)6:7(stiB

.noitasilaitinignirud'01'ottesebtsuM)4:5(stiB

desunU)0:3(stiB

XXXX00XX

63

stupni_laitnereffid_gfnc sdleifnoitarugifnoclaudividniowtsniatnocretsigersihT

desunU)2:7(stiB

1tiB )tluafed(elbitapmocLCEPsiFFID2CEStupnI1= elbitapmocSDVLsiFFID2CEStupnI0=

0tiB elbitapmocLCEPsiFFID1CEStupnI1= )tluafed(elbitapmocSDVLsiFFID1CEStupnI0=

01XXXXXX

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com26

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

83elbane_tuptuo_gfnc :swollofsa,sdleifnoitarugifnoclaudividnilarevessniatnocretsigersihT

7tiB zHM40.113ottesycneuqerftuptuo1O1= )tluafed()4:5(A3sserddAybtesycneuqerftuptuo1O0=

.noitasilaitinignirud'0'ottesebtsuM.desunU6tiB

5tiB 1giDrofdetcelesedomTENOS1= )tluafed(1giDrofdetcelesedomHDS0= seicneuqerf_tuptuo_1O_gfncretsigerees-

.noitasilaitinignirud'0'ottesebtsuM.desunU)3:4(stiB

2tiB )tluafed()zHM44.91(delbane2OtroptuptuO1= delbasid2OtroptuptuO0=

.noitasilaitinignirud'0'ottesebtsuM.desunU)0:1(stiB

.)detats-irTtonsitropeht(eulavcigolcitatsasdlohtroptuptuoehtsnaem"delbasiD":etoN

XX1XX0X0

93seicneuqerf_tuptuo_1O_gfnc .wolebdeliatedsa,troptuptuohcaerofsnoitcelesycneuqerfehtsdlohretsigersihT

1giD)4:5(stiBdesunU)6:7(stiB )tluafed(zHk8402/zHk445100 zHk6904/zHk880310 zHk2918/zHk671601 zHk48361/zHk2532111

desunU)0:1(stiBdesunU)2:3(stiB

HDS/TENOSehtaivdetceleserayehT.HDS/TENOSrofnwohseraseulavycneuqerfeht1giDroF .elbane_tuptuo_gfncretsigernistib

XXXX00XX

A3tuptuo_laitnereffid_gfnc laitnereffidehtrofepytygolonhcet-tropehtdnasnoitcelesycneuqerfehtsdlohretsigersihT .wolebdeliatedsa,1Otuptuo

desunU)2:3(stiBdesunU)6:7(stiB

1O)0:1(stiB1O)4:5(stiB delbasidtroP00)tluafed(zHM88.8300 elbitapmoc-LCEP10zHM44.9110 )tluafed(elbitapmoc-SDVL01zHM25.55101 desunU111giD11

01XX00XX

B3htdiwdnab_gfnc nehW.LLPlatigidehtfonoitarepoehtlortnocotdesunoitamrofnisniatnocretsigersihT gnitteshtdiwdnabnoitisiuqcaehtesulliwLLPDeht,citamotuaottessinoitceleshtdiwdnab ,launamottesnehW.kcolninehwgnitteshtdiwdnabdekcol/lamronehtdna,kcolfotuonehw .gnitteshtdiwdnabdekcol/lamronehtesuyawlalliwLLPDeht

7tiB noitarepocitamotuA1= )tluafed(noitarepolaunaM0=

htdiwdnabpooL)0:2(tiBhtdiwdnabnoitisiuqcA)4:6(stiB zH1.0000zH1.0000 zH3.0100zH3.0100 zH5.0010zH5.0010 zH0.1110zH0.1110 zH0.2001zH0.2001 )tluafed(zH0.4101zH0.4101 zH0.8011zH0.8011 zH71111)tluafed(zH71111

desunU3tiB

101X1110

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com27

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

ycneuqerf_lanimon_gfnc latsyrcehtfotesfforofnoitasnepmocgniwollaregetnidengisnutib61asdlohretsigersihT tluafeD.noitarbilaCycneuqerFlatsyrCnoitceseeS.zHM8.21lanimonehtmorfrotallicso .tnemtsujdampp0nistluser

C3 )0:7(stibycneuqerf_lanimon_gfnc)0:7(stiB 10011001

D3 )8:51(stibycneuqerf_lanimon_gfnc)0:7(stiB 10011001

tesffo_revodloh_gfnc .noitazilaitinignirud'0'ottesebtsumhcihwtib1sdlohretsigersihT

04 noitazilaitinignirud'0'ottesebtsuM7tiB

desunU)0:6(stiB XXXXXXX1

timil_qerf_gfnc tI.LLPDehtfoegnarni-llupehtgnitneserperregetnidengisnutib01asdlohretsigersihT ehtgnisu,noitacilppaehtnidetnemelpmilatsyrcfoycaruccaehtotgnidroccatesebdluohs ;alumrofgniwollof

ro74610.0+)5870.0xtimil_qerf_gfnc(=)mpp(-/+egnarycneuqerF 5870.0/)74610.0-)mpp(-/+egnarycneuqerF(=timil_qerf_gfnc

nehweulavtluafeD.mpp3.9±siwoldeitrodetcennocnutfelsiWSCRSnehweulavtluafeD .mpp08±dnuorafoegnarllufehtsihgihsiWSCRS

14)0:7(stibtimil_qerf_gfnc)0:7(stiB

01101110 )wolWSCRS( 11111111 )hgihWSCRS(

24 desunU)2:7(stiB

)8:9(stibstimil_qerf_gfnc)0:1(stiB

00XXXXXX )wolWSCRS( 11XXXXXX )hgihWSCRS(

ksam_tpurretni_gfnc .retsigersutatstpurretniehtniecruostpurretnietairporppaehtelbasidlliw'0'tesfi,tibhcaE

34

noitasilaitinignirud'00'ottesebtsuM)6:7(tiB

FFID2CESsutatS5tiB

FFID1CESsutatS4tiB

2CESsutatS3tiB

1CESsutatS2tiB

noitasilaitinignirud'00'ottesebtsuM)0:1(tiB

11111111

44

edom.repO7tiB

ferniaM6tiB

noitasilaitinignirud'00000'ottesebtsuM)1:5(tiB

ecruostpurretnI0tiB

11111111

54 desunU)5:7(tiB

noitasilaitinignirud'00000'ottesebtsuM)0:4(tiB 11111XXX

nvid_qerf_gfnc ycneuqerfgnikcolesahpehttegottupniynarofrosividehtsadesusiregetnitib41sihT ycneuqerftupniehtesuaclliwsihT.’1‘ottestibNviDehthtiwstupnirofevitcaylnO.derised :otNmargorp.g.e,nosirapmocesahpotroirp)1+n(ybdedividebot

1-)zHk8/)qerftupni((

ehtotycneuqerftopstsesolcehttcelferottesebdluohsstibycneuqerf_ecruos_ecnereferehT .ycneuqerftupniehtnahtrewolebtsumtub,ycneuqerftupni

64)0:7(stibnvid_qerf_gfnc)0:7(stiB 00000000

74 desunU)6:7(stiB

)8:31(stibnvid_qerf_gfnc)0:5(stiB 000000XX

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

Revision 2.01/December 2005 Semtech Corp. www.semtech.com28

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Table 11. Register Map Description (continued).Table 11. Register Map Description (continued).

Table 11. Register Map Description (continued).

.rddA.rddA .rddA .rddA.rddA )xeH()xeH( )xeH( )xeH()xeH( emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPnoitpircseDnoitpircseD noitpircseD noitpircseDnoitpircseDtluafeDtluafeD tluafeD tluafeDtluafeD )nib(eulaV)nib(eulaV )nib(eulaV )nib(eulaV)nib(eulaV

84

srotinom_gfnc .tuodliubesahpfolortnocdnasrotinomfonoitarugifnoclabolgswollaretsigersihT

desunU7tiB

desunU6tiB

5tiB yltnerrucehtnomralaytivitcanaesiarotLLPDehtswollA:gnihctiwstsafartluselbanE1= .gnihctiwStsaFartlUnonoitceseeS.selcycwefaylnognissimretfaecruosdetceles )tluafed(noitarepolamroN0=

4tiB wolWSCRSnipfi)03nip(2CESro,hgihWSCRSnipfi)92nip(1CESotgnikcolsecroF1= delbanelortnoccitamotuadna,derongiWSCRSniP0=

3tiB tesffoesahptuptuoottupnitnerrucehthtiwpihsnoitaleresahptuptuoehtezeerflliW1= )edomtuodliubesahplamroN(ecalpekatottesffoesahptuptuoottupninisegnahcswollA0= )tluafed(

2tiB )tluafed(tuodtliubesahpselbanE1= °0otkcolswollalliwLLPD0=

rofdevresererasrehto,mpp51=10,ffo=00-srotinomycneuqerfgnirugifnocrofera)0:1(stiB .esuerutuf

1010000X )wolWSCRS( 1010100X )hgihWSCRS(

05 0dlohserht_reppu_vitca_gfnc .desiarebotmralaytivitcaehtsesuactahttekcubykaelehtnieulavehttes)0:7(stiB 01100000

15 0dlohserht_rewol_vitca_gfnc .deraelcebotmralaytivitcaehtsesuactahttekcubykaelehtnieulavehttes)0:7(stiB 00100000

25 0ezis_tekcub_gfnc .tupnievitcaninanevighcaernactekcubykaelehttahteulavmumixamehttes)0:7(stiB 00010000

35

0etar_yaced_gfncdesunU)2:7(stiB

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65 1ezis_tekcub_gfnc .1tekcubroftub25retsigerrofsA 00010000

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85 2dlohserht_reppu_vitca_gfnc .2tekcubroftub05retsigerrofsA 01100000

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B5 2etar_yaced_gfnc .2tekcubroftub35retsigerrofsA 10XXXXXX

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E5 3ezis_tekcub_gfnc .3tekcubroftub25retsigerrofsA 00010000

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Revision 2.01/December 2005 Semtech Corp. www.semtech.com29

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

to do so by the software; by briefly setting the

Revertive mode bit. When there is a reference

available with higher priority than the selected

reference, there will be NO change of reference

source as long as the Non-Revertive mode

remains on AND the device will remain indicating

a locked state on the failed reference. This is

the case even if there are lower priority

references available or the currently selected

reference fails. When the ONLY valid reference

sources that are available have a lower priority

than the selected reference, a failure of the

selected reference will always trigger a switch-

over, regardless of whether Revertive or Non-

Revertive mode has been chosen.

Automatic Control SelectionAutomatic Control Selection

Automatic Control Selection

When automatic selection is required, the

cnfg_ref_selection registers must be set to all-

zero or all-one. The configuration registers,

cnfg_ref_selection_priority, held in the µP port

are organised as 5, 4-bit registers with each

representing an input reference port. Unused

ports should be given the value '0000' in the

relevant register to indicate they are not to be

included in the priority table. On power-up, or

following a reset, the whole of the configuration

file will be defaulted to the values defined by

Table 4. The selection priority values are all

relative to each other, with lower-valued

numbers taking higher priorities. Each reference

source should be given a unique number, the

valid values are 1 to 15 (dec). A value of 0

disables the reference source. However if two

or more inputs are given the same priority

number those inputs will be selected on a first

in, first out basis. If the first of two same priority

number sources goes invalid the second will be

switched in. If the first then becomes valid

again, it becomes the second source on the

first in, first out basis, and there will not be a

switch. If a third source with the same priority

number as the other two becomes valid, it joins

the priority list on the same first in, first out

basis. There is no implied priority based on the

channel numbers.

Selection of Input Reference ClockSelection of Input Reference Clock

Selection of Input Reference Clock

SourceSource

Source

Under normal operation, the input reference

sources are selected automatically by an order

of priority, where SEC1 is the highest priority,

SEC2 is the second highest priority and SEC3

is the lowest priority. The priorities can be

re-assigned with external software. The SEC1

reference source has inputs via either a low

speed TTL input port or a high speed PECL/

LVDS input port. Similarly, the SEC2 reference

source has both a low speed TTL or a high

speed PECL/LVDS input port. The SEC3

(standby) reference source only has provision

via a low speed TTL input port. There is provision

for one sync clock input via a TTL port. Whilst

SEC1, SEC2 and SEC3 reference source inputs

can all be active at the same time, only one of

the TTL or PECL/LVDS input ports for the SEC1

and SEC2 reference sources may be used at

any time, the inactive port is ignored, by setting

the priority of that port to zero.

Restoration of repaired reference sources is

handled carefully to avoid inadvertent

disturbance of the output clock. The ACS8510

has two modes of operation; Revertive and

Non-Revertive. In Revertive mode, if a re-

validated (or newly validated) source has a

higher priority than the reference source which

is currently selected, a switch over will take

place. Many applications prefer to minimise the

clock switching events and choose Non-

Revertive mode. In Non-Revertive mode , when

a re-validated (or newly validated) source has a

higher priority then the selected source will be

maintained. The re-validation of the reference

source will be flagged in the sts_sources_valid

register and, if not masked, will generate an

interrupt. Selection of the re-validated source

can only take place under software control -

the software should briefly enable Revertive

mode to affect a switch-over to the higher

priority source. If the selected source fails under

these conditions the device will indicate that it

is still locked to the failed reference. It will not

select the higher priority source until instructed

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Any of these registers can be subsequently set

by external s/w if required.

When external protection switching is enabled,

the device will operate as a simple switch. All

clock monitoring is disabled and the DPLL will

simply be forced to try to lock on to the

indicated reference source. The operating state

(sts_operating_mode register) will always

indicate ‘locked’ in the mode.

Activity MonitoringActivity Monitoring

Activity Monitoring

The ACS8515 has a combined inactivity and

irregularity monitor. The ACS8515 uses a ‘leaky

bucket’ accumulator, which is a digital circuit

which mimics the operation of an analog

integrator, in which input pulses increase the

output amplitude but die away over time. Such

integrators are used when alarms have to be

triggered either by fairly regular defect events,

which occur sufficiently close together, or by

defect events which occur in bursts. Events

which are sufficiently spread out should not

trigger the alarm. By controlling the alarm-

setting threshold, the point at which the alarm

is triggered can be controlled. The point at which

Ultra Fast SwitchingUltra Fast Switching

Ultra Fast Switching

A reference source is normally disqualified after

the leaky bucket monitor thresholds have been

crossed. An option for a faster disqualification

has been implemented, whereby if register 48H,

bit 5 (Ultra Fast Switching), is set then a loss of

activity of just a few reference clock cycles will

set the ‘no activity alarm’ and cause a

reference switch. This can be chosen to cause

an interrupt to occur instead of, or as well as,

causing the reference switch.

External Protection SwitchingExternal Protection Switching

External Protection Switching

Fast external switching between inputs SEC1

and SEC2 can also be triggered directly from a

dedicated pin (SRCSW). This mode can be

activated either by holding this pin high during

reset, or by writing to bit 4 of register address

48Hex.

Once external protection switching is enabled,

then the value of this pin directly selects either

SEC1 (SRCSW high) or SEC2 (SRCSW low). If

this mode is activated at reset by pulling the

SRCSW pin high, then it configures the default

frequency tolerance of SEC1 and SEC2 to +/-

80 ppm (register address 41Hex and 42Hex).

reference

leaky bucket

source

response

alarm

bucket_size

upper_threshold

lower_threshold

(all programmable)programmable fall slopes

inactivities/irregularities

Figure 9. Inactivity and Irregularity MonitoringFigure 9. Inactivity and Irregularity Monitoring

Figure 9. Inactivity and Irregularity Monitoring

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ADVANCED COMMUNICATIONS FINAL

The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky

bucket empty) will be:

(cnfg_activ_upper_threshold N)

8

where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then

this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is

0.75 s.

The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated

as:

2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_threshold N))

8

where N is the number of the relevent leaky bucket configuration in each case. The default settings are shown

in the following:

2 x (8-4) = 1.0 s

8

secs

(cnfg_decay_rate N)

Leaky bucket timing Leaky bucket timing

Leaky bucket timing

1

the alarm is cleared depends upon the decay

rate and the alarm-clearing threshold. On the

alarm-setting side, if several events occur close

together, each event adds to the amplitude

and the alarm will be triggered quickly; if events

occur a little more spread out, but still

sufficiently close together to overcome the

decay, the alarm will be triggered eventually. If

events occur at a rate which is not sufficient to

overcome the decay, the alarm will not be

triggered. On the alarm-clearing side, if no defect

events occur for a sufficient time, the amplitude

will decay gradually and the alarm will be cleared

when the amplitude falls below the alarm-

clearing threshold. The ability to decay the

amplitude over time allows the importance of

defect events to be reduced as time passes

by. This means that, in the case of isolated

events, the alarm will not be set, whereas, once

the alarm becomes set, it will be held on until

normal operation has persisted for a suitable

time (but if the operation is still erratic, the

alarm will remain set). See Figure 9.

The ‘leaky bucket’ accumulators are

programmable for size, alarm set & reset

thresholds and decay rate. Each source is

monitored over a 128 ms period. If, within a

128 ms period, an irregularity occurs that is

not deemed to be due to allowable jitter/wander,

then the accumulator is incremented. The

accumulator will continue to increment up to

the point that it reaches the programmed

bucket size. The ‘fill rate’ of the leaky bucket

is, therefore, 8 units/second. The "leak rate"

of the leaky bucket is programmable to be in

multiples of the fill rate (x1, x0.5, x0.25 and

x0.125) to give a programmable leak rate from

8 units/sec down to 1 unit/sec. A conflict

between trying to ‘leak’ at the same time as a

‘fill’ is avoided by preventing a ‘leak’ when a

‘fill’ event occurs.

Disqualification of a non-selected reference

source is based on inactivity, or on an out of

band result from the frequency monitors. The

currently selected reference source can be

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

the Free-run mode, the timing and

synchronization signals generated from the

ACS8515 are based on the Master clock

frequency provided from the external oscillator

and are not synchronized to an input reference

source. The frequency of the output clock is a

fixed multiple of the frequency of the external

oscillator, and the accuracy of the output clock

is equal to the accuracy of the Master clock.

The transition from Free-run to Pre-locked

occurs when the ACS8515 selects a reference

source.

Pre-Locked ModePre-Locked Mode

Pre-Locked Mode

The ACS8515 will enter the Locked state in a

maximum of 100 seconds, as defined by GR-

1244-CORE specification, if the selected

reference source is of good quality. If the device

cannot achieve lock within 100 seconds, it

reverts to Free-run mode and another reference

source is selected.

Locked ModeLocked Mode

Locked Mode

The Locked mode is used when an input

reference source has been selected and the

PLL has had time to lock. When the Locked

mode is achieved, the output signal is in phase

and locked to the selected input reference

source. The selected input reference source is

determined by the priority table. When the

ACS8515 is in Locked mode, the output

frequency and phase follows that of the

selected input reference source. Variations of

the external crystal frequency have a minimal

effect on the output frequency. Only the

minimum to maximum frequency range is

affected. Note that the term, 'in phase', is not

applied in the conventional sense when the

ACS8515 is used as a frequency translator (e.g.,

when the input frequency is 2.048 MHz and

the output frequency is 19.44 MHz) as the input

and output cycles will be constantly moving past

each other; however, this variation will itself be

cyclical over time unless the input and output

are not locked.

disqualified for phase, frequency, inactivity or if

the source is outside the DPLL lock range. If

the currently selected reference source is

disqualified, the next highest priority, active

reference source is selected.

Restoration of repaired reference sources is

handled carefully to avoid inadvertant disruption

of the output clock. The ACS8515 operates in

a Non-Revertive mode by default. In this mode,

if the restored reference source has a higher

priority than the reference source which is

currently selected, a switch-over to the restored

source will not tale place automatically. A

restored reference source will assume its

correct place in the priority table but a switch-

over will only take place automatically upon

failure of the currently selected source. It is

possible to invoke a switch-over by external

control or by enabling Revertive mode.

Modes of OperationModes of Operation

Modes of Operation

The ACS8515 has three primary modes of

operation (Free-run, Locked and Holdover)

supported by three secondary, temporary

modes (Pre-Locked, Lost_Phase and Pre-

Locked2). These are shown in the State

Transition Diagram, Figure 10.

The ACS8515 can operate in Forced or

Automatic control. On reset, the ACS8515

reverts to Automatic Control, where transitions

between states are controlled completely

automatically. Forced Control can be invoked

by configuration, allowing transitions to be

performed under external control. This is not

the normal mode of operation, but is provided

for special occasions such as testing, or where

a high degree of hands-on control is required.

Free-run ModeFree-run Mode

Free-run Mode

The Free-run mode is typically used following a

power-on-reset or a device reset before

network synchronization has been achieved. In

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Lost-Phase ModeLost-Phase Mode

Lost-Phase Mode

Lost-phase mode is entered when the current

phase error, as measured within the DPLL, is

larger than a preset limit (see register 04, bits

5:3), as a result of a frequency or phase tran-

sient on the selected reference source. This

mode is similar in behavior to the Pre-locked or

Pre-locked(2) modes, although in this mode the

DPLL is attempting to regain lock to the same

reference rather than attempt lock to a new ref-

erence. If the DPLL cannot regain lock within 100

s, the source is disqualified, and one of the fol-

lowing transitions takes place:

1. Go to Pre-Locked(2);

- If a known-good standby source is available.

2. Go to Holdover;

- If no standby sources are available.

Holdover ModeHoldover Mode

Holdover Mode

The Holdover mode is used when the circuit

was in Locked mode but the selected reference

source has become unavailable and a

replacement has not yet been selected.

Holdover freezes the DPLL at the current

frequency (as reported by the

sts_curr_inc_offset register). The proportional

DPLL path is ignored so that recent signal

disturbances do not affect the Holdover

frequency value.

Pre-Locked(2) ModePre-Locked(2) Mode

Pre-Locked(2) Mode

This state is very similar to the Pre-Locked state.

It is entered from the Holdover state when a

reference source has been selected and applied

to the phase locked loop. It is also entered if

the device is operating in Revertive mode and

a higher-priority reference source is restored.

Power On Reset - PORBPower On Reset - PORB

Power On Reset - PORB

The Power On Reset (PORB) pin resets the

device if forced Low for a power-on-reset to be

initiated. The reset is asynchronous, the

minimum low pulse width is 5 ns. Reset is

needed to initialize all of the register values to

their defaults. Asserting Reset (POR) is required

at power on, and may be re-asserted at any

time to restore defaults. This is implemented

most simplistically by an external capacitor to

GND along with the internal pull-up resistor.

The ACS8515 is held in a reset state for 250

ms after the PORB pin has been pulled High. In

normal operation PORB should be held High.

Revision 2.01/December 2005 Semtech Corp. www.semtech.com34

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

pre-locked

wait for up to 100s

(state 110)

locked

keep ref

(state 100)

holdover

select ref

(state 010)

(2) all refs evaluated

&

at least one ref valid

(5) se lected re f

phase lock ed

(3) no valid standby ref

&

(main ref in v alid

or out of lock >100s)

(14) all refs evaluated

&

at least one ref valid

pre-locked2

wait for up to 100s

(state 101)

(10) selected source phase

locked

(6) no valid standby ref

&

ma in ref in v alid

free-run

select ref

(state 001)

(1)Reset

Referenc e sources are flagged as 'va

l

active, 'in- band' and have no phase al

a

A

ll sources are continuously checke

d

activi ty and frequency.

Only the main source is checked for

p

A

phase lock alarm is only raised on

a

ref erence when t hat reference has los

whilst being used as the main referen

c

micro-processor ca n reset the phase

alarm.

A

source is considered to have phase

when it has been continuously in pha

s

for between 1 and 2 seconds

Lost phase

wait for up to 100s

(state 111)

(7) phase lost

on main ref

(8) phase

re gained with in

100s

(12) valid standby ref

&

(main ref invalid

or out of lock >100s)

(13) no valid standby ref

&

(main re f inv al id

or out of lock >100s)

(11) no valid standby ref

&

(main re f inv al id

or out of lock >100s)

(9) valid standby ref

&

[ main ref inva lid or

(hig her-prio rity ref valid

& in re v e rtive mo de ) ]

(15) valid standby ref

&

[ main ref invalid or

(higher-priority ref valid

& in revertive mode) or

out of lock >100s]

(4) valid standby ref

&

[ main ref inva lid or

(hig her-prio rity ref valid

& in revertive mode) or

out of lock >100s]

Figure 10. Automatic Mode Control State DiagramFigure 10. Automatic Mode Control State Diagram

Figure 10. Automatic Mode Control State Diagram

Revision 2.01/December 2005 Semtech Corp. www.semtech.com35

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Electrical Specification Electrical Specification

Electrical Specification

Important NoteImportant Note

Important Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation

of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of

this specification are not implied. Exposure to the absolute maximum ratings for an extended

period may reduce the reliability or useful lifetime of the product.

PP

P

PPRETEMARARETEMARA RETEMARA RETEMARARETEMARA SS

S

SSLOBMYLOBMY LOBMY LOBMYLOBMY MM

M

MMNININININI MM

M

MMXAXAXAXAXA UU

U

UUSTINSTIN STIN STINSTIN

ppuSegatloVyl

V

DD

V,

D

V,+

A

,+1V

A

+2 V

DD

5.0-6.3V

egatloVtupnI )snipylppus-non( niV- 5.5V

egatloVtuptuO )snipylppus-non( tuoV-5.5V

erutarepmeTgnitarepOtneibmA egnaR T

A

04-58°C

erutarepmeTegarotST

rots

05-051°C

Across all operating conditions, unless otherwise stated

PP

P

PPRETEMARARETEMARA RETEMARA RETEMARARETEMARA SS

S

SSLOBMYLOBMY LOBMY LOBMYLOBMY NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

)egatlovcd(ylppuSrewoP

VDD+2AV,+1AV,+DV,FFID_DDV, DDV0.33.36.3V

)egatlovcd(ylppuSrewoP 5DDV 5DDV0.30.5/3.35.5V

egnaRerutarepmeTtneibmAT

A

04--58°C

tnerruCylppuS

tuptuozHM91eno-lacipyT w/serofebAm091-mumixaM noitasilaitniw/sretfaAm051,noitasilaitini

DDI-011051/091Am

noitapissidrewoplatoTP

TOT

-063586Wm

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

V

ni

hgiHV

hi

0.2--V

V

ni

woLV

li

-- 8.0V

tnerruCtupnII

ni

--01Aµ

Table 12. Absolute Maximum RatingsTable 12. Absolute Maximum Ratings

Table 12. Absolute Maximum Ratings

Table 13. Operating ConditionsTable 13. Operating Conditions

Table 13. Operating Conditions

Table 14. DC Characteristics: TTL Input PadTable 14. DC Characteristics: TTL Input Pad

Table 14. DC Characteristics: TTL Input Pad

Revision 2.01/December 2005 Semtech Corp. www.semtech.com36

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Across all operating conditions, unless otherwise stated

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

V

ni

hgiHV

hi

0.2--V

V

ni

woLV

li

-- 8.0V

rotsiseRpu-lluPUP03-08k!

tnerruCtupnII

ni

-- 021Aµ

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

V

ni

hgiHV

hi

0.2--V

V

ni

woLV

li

-- 8.0V

rotsiseRnwod-lluPDP03-08k!

tnerruCtupnII

ni

-- 021Aµ

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

woLtuoV Am4=loI loV0- 4.0V

hgiHtuoV Am4=hoI hoV4.2- V

tnerruCevirDDI--4Am

Table 15. DC Characteristics: TTL Input Pad with Internal Pull-upTable 15. DC Characteristics: TTL Input Pad with Internal Pull-up

Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up

Table 16. DC Characteristics: TTL Input Pad with Internal Pull-downTable 16. DC Characteristics: TTL Input Pad with Internal Pull-down

Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down

Table 17. DC Characteristics: TTL Output PadTable 17. DC Characteristics: TTL Output Pad

Table 17. DC Characteristics: TTL Output Pad

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ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Notes for Table 18Notes for Table 18

Notes for Table 18

Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to

VDD and GND respectively.

Note 1. Assuming a differential input voltage of at least 100 mV.

Note 2. Unused differential input terminated to VDD-1.4 V.

Note 3. With 50 ! load on each pin to VDD-2 V . i.e. 82 ! to GND and 130 ! to VDD.

Across operating conditions, unless otherwise stated

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

egatlovwoLtupnILCEP

stupnilaitnereffiD)1etoN(

V

LCEPLI

-DDV5.2- 5.0-DDVV

egatlovhgiHtupnILCEP

stupnilaitnereffiD)1etoN(

V

LCEPHI

-DDV4.2- 4.0-DDVV

egatlovlaitnereffiDtupnIV

LCEPDI

1.0-4.1V

egatlovwoLtupnILCEP

tupnidedneelgniS)2etoN(

V

S_LCEPLI

-DDV4.2- 5.1-DDVV

egatlovhgiHtupnILCEP

tupnidedneelgniS)2etoN(

V

S_LCEPHI

1-DDV3.- 5.0-DDVV

tnerruchgiHtupnI

egatlovlaitnereffidtupnIV

DI

v4.1=

I

LCEPHI

01--01+Aµ

tnerrucwoLtupnI

egatlovlaitnereffidtupnIV

DI

v4.1=

I

LCEPLI

01--01+Aµ

egatlovwoLtuptuOLCEP

)3etoN(

V

LCEPLO

-DDV01.2- 26.1-DDVV

egatlovhgiHtuptuOLCEP

)3etoN(

V

LCEPHO

52.1-DDV-88.0-DDVV

egatlovlaitnereffiDtuptuOLCEP

)1etoN(

V

LCEPDO

085-009Vm

Table 18. DC Characteristics: PECL Input/Output PadTable 18. DC Characteristics: PECL Input/Output Pad

Table 18. DC Characteristics: PECL Input/Output Pad

Revision 2.01/December 2005 Semtech Corp. www.semtech.com38

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

130R

SEC2_POS

SEC2_NEG

SEC1_NEG

SEC1_POS

O1POS

O1NEG

ZO=50Ω

82R

DD

V

82R

130R

ZO=50Ω

130R

82R

130R

DD

V

130R

82R

130R

DD

V

GND

8kHz, 1.544/2.048,

6.48, 19 .44, 38.88,

51.8 4, 77.76 or

155.5 2 M H z

51.8 4, 77.76 or

155.5 2 M H z

8kHz, 1.544/2.048,

6.48, 19 .44, 38.88,

19.44, 38 .88, 155.52,

311.04 MHz & DIG1

VDD = +3.3 V

Across all operating conditions, unless otherwise stated

Note 1. With 100 ! load between the differential outputs.

Table 19. DC Characteristics: LVDS Input/Output PadTable 19. DC Characteristics: LVDS Input/Output Pad

Table 19. DC Characteristics: LVDS Input/Output Pad

Figure 11. Recommended Line Termination for PECL Input/Output PortsFigure 11. Recommended Line Termination for PECL Input/Output Ports

Figure 11. Recommended Line Termination for PECL Input/Output Ports

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

LSDVegnaregatlovtupnI

Vm001=egatlovtupnilaitnereffiD

V

SDVLRV

0- 04.2V

dlohserhttupnilaitnereffiDSDVLV

HTID

001--001+mV

egatlovlaitnereffiDtupnISDVLV

SDVLDI

1.0-4.1V

ecnatsisernoitanimrettupnISDVL

ehtssorcayllanretxedecalpebtsuM .5158SCAfosniptupni-/+SDVL %5htiwmho001ebdluohsrotsiseR ecnarelot

R

MRET

59001501 W

egatlovhgihtuptuOSDVL

)1etoN(

V

SDVLHO

-- 585.1V

egatlovwoltuptuOSDVL

)1etoN(

V

SDVLLO

588.0--V

egatlovtuptuolaitnereffiDSDVL

)1etoN(

V

SDVLDO

052-054Vm

LSDVfoedutingamniegrahC rofegatlovtuptuolaitnereffid setatsyratnemilpmoc

)1etoN(

V

SDVLSOD

--52Vm

LSDVegatlovtesffotuptuo

C°52=erutarepmeT )1etoN(

V

SDVLSO

521.1-572.1V

Revision 2.01/December 2005 Semtech Corp. www.semtech.com39

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813)Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813)

Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813)

Across all operating conditions, unless otherwise stated

Figure 12. Recommended Line Termination for LVDS Input/Output PortsFigure 12. Recommended Line Termination for LVDS Input/Output Ports

Figure 12. Recommended Line Termination for LVDS Input/Output Ports

SEC2_POS

SEC2_NEG

SEC1_NEG

SEC1_POS

O1POS

O1NEG

ZO=50Ω

100R

ZO=50Ω

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

51.84, 77.76 or

155.52 MHz

51.84, 77.76 or

155.52 MHz

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

19.44,

311.0

4

100R

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

1noitpozHM25.551rof318.GzHM3.1otzH005IU

pp

5.0=)2etoN(850.0

1noitpozHM25.551rof318.GzHM3.1otzHk56IU

pp

1.0= )3etoN(840.0 )2etoN(840.0

2noitpozHM25.551rof318.GzHM3.1otzHk21IU

pp

1.0=

)4etoN(350.0 )5etoN(350.0

)6etoN(850.0 )7etoN(350.0

)2etoN(350.0 )3etoN(850.0

)8etoN(750.0 )9etoN(550.0

)01etoN(750.0 )11etoN(750.0

)21etoN(750.0 )31etoN(350.0

zHM840.2rof218.G&318.G 1noitpo zHk001otzH02IU

pp

50.0=)41etoN(640.0

Revision 2.01/December 2005 Semtech Corp. www.semtech.com40

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

zHM840.2rof3-264-003-STE CES zHk001otzH02IU

pp

5.0=)41etoN(640.0

zHM840.2rof3-264-003-STE CES )zHk001otzH94cepsretliF( zHk001otzH02IU

pp

2.0=)41etoN(640.0

zHM840.2rof3-264-003-STE USS zHk001otzH02IU

pp

50.0=)41etoN(640.0

zHM25.551rof3-264-003-STEzHM3.1otzH005IU

pp

5.0=)3etoN(850.0

zHM25.551rof3-264-003-STEzHM3.1otzHk56IU

pp

1.0=)3etoN(840.0

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812)Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812)

Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3)Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3)

Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3)

Across all operating conditions, unless otherwise stated

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

zHM445.1rof218.GzHk04otzH01IU

pp

50.0=)41etoN(630.0

lacirtcelezHM25.551rof218.GzHM3.1otzH005IU

pp

5.0=)3etoN(850.0

lacirtcelezHM840.2rof218.GzHM3.1otzHk56 IU

pp

=

570.0 )3etoN(840.0

Revision 2.01/December 2005 Semtech Corp. www.semtech.com41

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

48.15,f/itenEROC-352-RG zHM zHk004otzH001IU

pp

5.1=)3etoN(220.0

48.15,f/itenEROC-352-RG zHM )zHk004otzHk02cepsretliF( zHk004otzHk81IU

pp

51.0=)3etoN(910.0

25.551,f/itenEROC-352-RG zHM zHM3.1otzH005IU

pp

5.1=)3etoN(850.0

25.551,f/itenEROC-352-RG zHM zHM3.1otzHk56IU

pp

51.0=)3etoN(840.0

,f/itceleIItacEROC-352-RG zHM25.551 zHM3.1otzHk21 IU

pp

1.0=)3etoN(850.0

IU

smr

10.0=)3etoN(600.0

,f/itceleIItacEROC-352-RG zHM48.15 zHk004otzHk21 IU

pp

1.0=)3etoN(710.0

IU

smr

10.0=)3etoN(300.0

445.1,f/i1SDEROC-352-RG zHM zHk04otzH01 IU

pp

1.0=)41etoN(630.0

IU

smr

10.0=)41etoN(5500.0

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

zHM445.1rof11426T&TA )zHk8otzH01cepsretliF( zHk04otzH01IU

smr

20.0=)41etoN(5500.0

zHM445.1rof11426T&TAzHk04otzH01 IU

smr

=

520.0 )41etoN(5500.0

zHM445.1rof11426T&TAzHk04otzH01 IU

smr

=

520.0 )41etoN(5500.0

zHM445.1rof11426T&TAdnabdaorBIU

smr

50.0=)41etoN(5500.0

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE)Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE)

Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411)Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411)

Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411)

Across all operating conditions, unless otherwise stated

Revision 2.01/December 2005 Semtech Corp. www.semtech.com42

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

zHM445.1rofEROC-4421-RGzH01>IU

pp

50.0=)41etoN(630.0

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742)Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742)

Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499)Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499)

Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE)Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE)

Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE)

Across all operating conditions, unless otherwise stated

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

zHM840.2rof247.GzHk001otCDIU

pp

52.0=)41etoN(740.0

zHM840.2rof247.G )zHk001otzHk81cepsretliF( zHk001otzH02IU

pp

50.0=)41etoN(640.0

zHM840.2rof247.GzHk001otzH02IU

pp

50.0=)41etoN(640.0

NOITINIFEDTSETNOITINIFEDTSET NOITINIFEDTSET NOITINIFEDTSETNOITINIFEDTSETDESURETLIFDESURETLIF DESURETLIF DESURETLIFDESURETLIFCEPSIUCEPSIU CEPSIU CEPSIUCEPSIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU 5158SCANOTNEMERUSAEMIU5158SCANOTNEMERUSAEMIU 2VER2VER 2VER 2VER2VER

rof428.G&994000-TWN-RT zHM445.1 zHk04otzH01IU

pp

0.5=)41etoN(630.0

rof428.G&994000-TWN-RT zHM445.1 )zHk04otzHk8cepsretliF( zHk04otzH01IU

pp

1.0=)41etoN(630.0

Revision 2.01/December 2005 Semtech Corp. www.semtech.com43

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

(Multiples have the

E1

< ± 0.5 ns311.04 MHz

< ± 1 ns

+2.0 to +4. 0 ns

+6.0 to +8. 0 ns

+3.0 to +4. 5 ns

+3.0 to +5.0 ns

+2.5 to +4. 5 ns

+3.0 to +5. 0 ns

155.52 MHz

77.76 MHz

51.84 MHz

38.88 MHz

19.44 MHz

25.92 MHz

6.48 MHz

for this outpu t)

(Additional delay

same offset)

+3.5 to +5. 5 ns

< ±1 n s

Alignment

Phase

T1

8 kHz

2 kHz

Output

same offset)

(Multiples have the

8 kHz input

8 kHz outp ut

6.48 MHz input

6.48 MHz output

19.44 MHz input

19.44 MHz output

25.92 MHz input

25.92 MHz output

38.88 MHz input

38.88 MHz output

51.84 MHz input

51.84 MHz output

77.76 MHz input

77.76 MHz output

Input/Output Delay

± 1.5 ns

+6.5 to +8.5 ns

+5.5 to +7.5 ns

+6.5 to +8.5 ns

+4.0 to +6.0 ns

+6.0 to +8.0 ns

+5.5 to +7.5 ns

Typical

Figure 13. Input/Output TimingFigure 13. Input/Output Timing

Figure 13. Input/Output Timing

Notes for tables 20 - 227Notes for tables 20 - 227

Notes for tables 20 - 227

Note 1. Filter used is that defined by test definition unless otherwise stated

Note 2. 5 Hz bandwidth, 19.44 MHz input, direct lock

Note 3. 5 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 4. 20 Hz bandwidth, 19.44 MHz input, direct lock

Note 5. 20 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 6. 10 Hz bandwidth, 19.44 MHz input, direct lock

Note 7. 10 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 8. 2.5 Hz bandwidth, 19.44 MHz input, direct lock

Note 9. 2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 10. 1.2 Hz bandwidth, 19.44 MHz input, direct lock

Note 11. 1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 12. 0.6 Hz bandwidth, 19.44 MHz input, direct lock

Note 13. 0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock

Note 14. 5 Hz bandwidth, 2.048 MHz input, 8 kHz lock

Revision 2.01/December 2005 Semtech Corp. www.semtech.com44

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

The device has a Serial microprocessor interface. The combined minimum High and Low times for SCLK define

the maximum clock rate.

For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is

affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us).

This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read

mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final

address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With

CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock

out the SDO.

A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking

it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has

a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz.

SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing

diagrams for Write and Read access for this mode.

Microprocessor Interface Timing Microprocessor Interface Timing

Microprocessor Interface Timing

Figure 14. Read Access TimingFigure 14. Read Access Timing

Figure 14. Read Access Timing

F8525D_013ReadAccSerial_01

SCLK

CSB

CLKE = 0; SDO data is clocked out on the rising edge of SCLK

CLKE = 1; SDO data is clocked out on the falling edge of SCLK

R/W

Output not driven, pulled low by internal resistor

SDI

SDO

t

su2

t

su1

t

h1

t

pw1

t

pw2

_

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

t

h2

t

d2

t

d1

SCLK

CSB

R/W

Output not driven, pulled low by internal resistor

SDI

SDO

_

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

t

h2

t

d2

t

d1

Revision 2.01/December 2005 Semtech Corp. www.semtech.com45

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

t

1us

KLCSotdilavIDSputeS

egdegnisir

0sn- -

t

2us

BSCputeS

egdegnillaf

KLCSot

egdegnisir

sn061--

t

1wp

emitwolKLCS sn081--

t

2wp

emithgihKLCS sn081--

t

1h

KLCSretfadilavIDSdloH

egdegnisir

sn071--

t

2h

KLCSretfawolBSCdloH

egdegnisir

sn5--

t

p

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn061--

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

t

1us

KLCSotdilavIDSputeS

egdegnisir

0sn- -

t

2us

BSCputeS

egdegnillaf

KLCSot

egdegnisir

sn061--

t

1d

KLCSyaleD

egdegnisir

KLCS(

egdegnillaf

dilavODSot)1=EKLCrof--sn71

t

2d

BSCyaleD

egdegnisir

Z-hgihODSot--sn01

t

1wp

emitwolKLCS 0=EKLC 1=EKLC sn052 sn005 --

t

2wp

emithgihKLCS 0=EKLC 1=EKLC sn052 sn005 --

t

1h

KLCSretfadilavIDSdloH

egdegnisir

sn071--

t

2h

KLCSretfawolBSCdloH

egdegnisir

0=EKLCrof,

KLCSretfawolBSCdloH

egdegnillaf

1=EKLCrof, sn5--

t

p

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn061--

Figure 15. Write Access TimingFigure 15. Write Access Timing

Figure 15. Write Access Timing

Table 29. Write Access TimingTable 29. Write Access Timing

Table 29. Write Access Timing

Table 28. Read Access TimingTable 28. Read Access Timing

Table 28. Read Access Timing

SCLK

CSB

R/W

Output not driven, pulled low by internal resistor

SDI

SDO

tsu2

tsu1 th1 tpw1

tpw2

_A0 A1 A2 A3 A4 A5 A6

th2

D0 D1 D2 D3 D4 D5 D6 D7

F8525D_014WriteAccSerial_01

Revision 2.01/December 2005 Semtech Corp. www.semtech.com46

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Package Information Package Information

Package Information

E

D

AA2

A1 b

e

b1

b

c

L

L1

AN2

S

AN1

AA

Seating plane

1

2

3

4

5

6

D1

E1

1

2

3

7

Notes

1

2

3

4

5

6

7

8

R1

B

The top package body may be smaller than the bottom package body by as much as 0.15 mm.

To be determined at seating plane.

Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.

D1 and E1 are maximum plastic body size dimensions including mold mismatch.

Details of pin 1 identifier are optional but will be located within the zone indicated.

Exact shape of corners can vary.

A1 is defined as the distance from the seating plane to the lo west point of the packa ge body.

These dimensions appl

y

to the flat sec tion of the lead between 0.10 mm and 0. 25 mm from the lead

Shows plating.

123

Figure 16. LQFP PackageFigure 16. LQFP Package

Figure 16. LQFP Package

Revision 2.01/December 2005 Semtech Corp. www.semtech.com47

ACS8515 Rev2.1 LC/P

ADVANCED COMMUNICATIONS FINAL

Thermal ConditionsThermal Conditions

Thermal Conditions

The device is rated for full temperature range when this package is used with a 4 layer or more

PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum

operating temperature must be reduced when the device is used with a PCB with less than these

requirements.

PFQL46PFQL46 PFQL46 PFQL46PFQL46 egakcaPegakcaP egakcaP egakcaPegakcaP

snoisnemiDsnoisnemiD snoisnemiD snoisnemiDsnoisnemiD mmnimmni mmni mmnimmni

E/DE/D E/D E/DE/D1E/1D1E/1D 1E/1D 1E/1D1E/1DAA

A

AA1A1A1A1A1A2A2A2A2A2Aee

e

ee1NA1NA 1NA 1NA1NA2NA2NA 2NA 2NA2NA3NA3NA 3NA 3NA3NA4NA4NA 4NA 4NA4NA1R1R1R1R1R2R2R2R2R2RLL

L

LL1L1L1L1L1LSS

S

SSbb

b

bb1b1b1b1b1bcc

c

cc1c1c1c1c1c

niM04.150.053.1°11°11°0°080.080.054.002.071.071.090.090.0

moN00.2100.0105.101.004.105.0°21°21- °5.3--06.0 00.1 )fer( -22.002.0--

xaM06.151.054.1°31°31-°7- 02.057.0-72.032.002.061.0

Figure 17. Typical 64 Pin LQFP FootprintFigure 17. Typical 64 Pin LQFP Footprint

Figure 17. Typical 64 Pin LQFP Footprint

10.6 mm

13.0 mm (1)

14.3 mm

Pitch 0.5 mm

Width 0.3 mm

1.85 mm

Notes

(1) Solderable to this limit.

Square package - dimensions apply in both X and Y directions.

Typical example - the user is responsible for ensuring compatibility with PCB manufacturing process, etc.

Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)

Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)

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Application Information Application Information

Application Information

Figure 18. Simplified Application SchematicFigure 18. Simplified Application Schematic

Figure 18. Simplified Application Schematic

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Appendix A Rev2.1 Changes Described Appendix A Rev2.1 Changes Described

Appendix A Rev2.1 Changes Described

SummarySummary

Summary

This section summarizes the minor changes and improvements made to the ACS8515 from Rev2.0 to Rev2.1.

The bulk of these changes are designed to remove the need for software work arounds associated with Phase

Build Out.

Two new features have been added, necessitating changes to the control software. These are described in detail

below.

Input Edge Alignment for 8k locking modeInput Edge Alignment for 8k locking mode

Input Edge Alignment for 8k locking mode

An additional bit in the register cnfg_control1 (Bit 2) has been allocated to select which edge of the input

reference to lock to when the device is configured in 8k locking mode.

This bit, when set to one ensures that the rising edge of the output clock phase locks to the rising edge of the

input clock, when 8k locking mode is used on the input.

Low Jitter n x E1/DS1 ModeLow Jitter n x E1/DS1 Mode

Low Jitter n x E1/DS1 Mode

A second bit of the cnfg_control1 register has been allocated to controlling what frequency is fed into the APLL.

This allows the user to switch from the normal 77.76MHz to twice the dig2 output frequency.

This has the effect of replacing the normal OC/STM outputs with multiples of the E1 or DS1 rate. The E1/DS1

choice is controlled by the SONET/SDH bit in the cnfg_mode register.

Revision History Revision History

Revision History

Table 31. Table 31.

Table 31. Changes from Revision 1.05 to 2.00 September 2003.

Item Section Page Description

1Non-Revertive

Mode 29 Updated N on-Revertive mode description

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Ordering Information Ordering Information

Ordering Information

DisclaimersDisclaimers

Disclaimers

Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or

other critical applications. This product is not authorized or warranted by Semtech Corporation for such use.

Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product.

Customers are advised to obtain the latest version of the relevant information before placing orders.

Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design

practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards.

REBMUNTRAPREBMUNTRAP REBMUNTRAP REBMUNTRAPREBMUNTRAP NOITPIRCSEDNOITPIRCSED NOITPIRCSED NOITPIRCSEDNOITPIRCSED

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T1.2veR5158SCA 1.2ver5158SCAfonoisrevegakcapeerf-)bP(daeL

ISO9001

CERTIFIED

For additional information, contact the following:

Semtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications Products

Semtech Corporation Advanced Communications Products

E-Mail: sales@semtech.com acsupport@semtech.com

Internet: http://www.semtech.com

USA: 20 0 F lynn Road, Camarillo, CA 93012-8790

Tel: +1 805 498 2111, Fax: +1 805 498 3804

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