ACS8515 Rev2.1 LC/P ADVANCED COMMUNICATIONS Line Card Protection Switch for SONET or SDH Network Elements FINAL Description Features The ACS8515 is a highly integrated, single-chip solution for `hit-less' protection switching of SEC clocks from Master and Slave SETS clockcards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching against master clock failure. A further input is provided for an optional standby SEC clock. The ACS8515 is fully compliant with the required specifications and standards. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card clock, e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. An SPI(1) compatible serial port is incorporated, providing access to the configuration and status registers for device setup. The ACS8515 can utilise either a low cost XO oscillator module, or a TCXO with full temperature calibration - as required by the application. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. Block Diagram Figure 1. Simple Block Diagram 3 x SEC Input Master/Slave + Standby: N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz MFrSync *Suitable for Stratum 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications *Meets AT&T, ITU-T, ETSI and Telcordia specifications *Three SEC input clocks, from 2 kHz to 155.52 MHz *Generates two SEC output clocks, up to 311.04 MHz *Frequency translation of SEC input clock to a different local line card clock *Robust input clock source frequency and activity monitoring on all inputs *Supports Free-run, Locked and Holdover modes of operation *Automatic `hit-less' source switchover on loss of input *External force fast switch between SEC inputs *Phase build out for output clock phase continuity during input switchover *SPI(1) compatible serial microprocessor interface *Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz *Single +3.3 V operation. +5 V I/O compatible *Operating temperature (ambient) -40C to +85C *Available in 64 pin LQFP package *Lead (pb)-free version available (ACS8515 Rev2.1T) RoHS and WEEE compliant. (1) SPI is a trademark of Motorola Corporation 3xSEC Input Ports 2xSEC APLL Monitors DPLL Frequency Synthesis Frequency Dividers MFrSync Chip Clock Generator Priority Table Register Set Output Ports FrSync MFrSync SPI Compatible Serial Microprocessor Port TCXO or XO Revision 2.01/December 2005 Semtech Corp. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS TTable able of Cont ents Contents List of Sections Description ................................................................................................................................................................................................ 1 Block Diagram ........................................................................................................................................................................................... 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 4 Pin Descriptions ........................................................................................................................................................................................ 5 Functional Description ............................................................................................................................................................................. 7 Local Oscillator Clock ..................................................................................................................................................................................... 7 Crystal Frequency Calibration ........................................................................................................................................................ 7 Input Reference Clock Ports ......................................................................................................................................................................... 8 Input Wander and Jitter Tolerance ............................................................................................................................................................ 10 Output Clock Ports ........................................................................................................................................................................................ 11 Low Speed Output Clock ................................................................................................................................................................ 11 High Speed Output Clock .............................................................................................................................................................. 12 Frame Sync and Multi-Frame Sync Clocks ................................................................................................................................ 12 Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 12 Output Wander and Jitter ............................................................................................................................................................................ 13 Phase Variation ............................................................................................................................................................................................. 14 Phase Build Out ............................................................................................................................................................................................. 16 Microprocessor Interface ............................................................................................................................................................................. 16 Register Set ..................................................................................................................................................................................... 16 Configuration Registers ................................................................................................................................................................. 16 Status Registers .............................................................................................................................................................................. 16 Register Access ............................................................................................................................................................................... 17 Interrupt Enable and Clear ......................................................................................................................................................................... 17 Register Map .................................................................................................................................................................................................. 18 Register Map Description ........................................................................................................................................................................... 21 Selection of Input Reference Clock Source ............................................................................................................................................. 29 Automatic Control Selection ........................................................................................................................................................ 29 Ultra Fast Switching ....................................................................................................................................................................... 30 External Protection Switching ..................................................................................................................................................... 30 Activity Monitoring ....................................................................................................................................................................................... 30 Modes of Operation ...................................................................................................................................................................................... 32 Free-run Mode ................................................................................................................................................................................. 32 Pre-Locked Mode ............................................................................................................................................................................ 32 Locked Mode .................................................................................................................................................................................... 32 Lost-Phase Mode ............................................................................................................................................................................. 33 Holdover Mode ................................................................................................................................................................................ 33 Pre-Locked(2) Mode ........................................................................................................................................................................ 33 Power On Reset - PORB ............................................................................................................................................................................... 33 Electrical Specification .......................................................................................................................................................................... 35 Serial Microprocessor Interface Timing ............................................................................................................................................... 44 Package Information .............................................................................................................................................................................. 46 Thermal Conditions ....................................................................................................................................................................................... 47 Application Information .......................................................................................................................................................................... 48 Appendix A Rev2.1 Changes Described ............................................................................................................................................... 49 Revision History ...................................................................................................................................................................................... 49 Ordering Information .............................................................................................................................................................................. 50 Disclaimers ..................................................................................................................................................................................................... 50 Revision 2.01/December 2005 Semtech Corp. 2 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS List of Figures Figure 1. Simple Block Diagram .............................................................................................................................................................. 1 Figure 2. ACS8515 Pin Diagram ............................................................................................................................................................. 4 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) .................................................................................................................... 11 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) ........................................................................................................................... 12 Figure 5. Wander and Jitter Transfer Measured Characteristics ........................................................................................................ 14 Figure 6. Maximum Time Interval Error of TOUT0 Output Port ........................................................................................................... 15 Figure 7. Time Deviation of TOUT0 Output Port ................................................................................................................................... 15 Figure 8. Phase Error Accumulation of TOUT0 Output Port in Holdover Mode ................................................................................. 15 Figure 9. Inactivity and Irregularity Monitoring .................................................................................................................................... 30 Figure 10. Automatic Mode Control State Diagram ............................................................................................................................ 34 Figure 11. Recommended Line Termination for PECL Input/Output Ports ....................................................................................... 38 Figure 12. Recommended Line Termination for LVDS Input/Output Ports ....................................................................................... 39 Figure 13. Input/Output Timing ............................................................................................................................................................. 43 Figure 14. Serial Interface Read Access Timing .................................................................................................................................. 44 Figure 15. Serial Interface Write Access Timing ................................................................................................................................. 45 Figure 16. LQFP Package ....................................................................................................................................................................... 46 Figure 17. Typical 64 Pin LQFP Footprint .............................................................................................................................................. 47 Figure 18. Simplified Application Schematic ....................................................................................................................................... 48 List of TTables ables Table 1. Power Pins .................................................................................................................................................................................... 5 Table 2. No Connections ............................................................................................................................................................................ 5 Table 3. Other Pins ..................................................................................................................................................................................... 6 Table 4. Input Reference Source Selection and Group Allocation ....................................................................................................... 9 Table 5. Input Reference Source Jitter Tolerance ................................................................................................................................ 10 Table 6. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 11 Table 7. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 12 Table 8. Output Reference Source Selection Table ............................................................................................................................. 13 Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 13 Table 10. Register Map ........................................................................................................................................................................... 18 Table 11. Register Map Description ...................................................................................................................................................... 21 Table 12. Absolute Maximum Ratings ................................................................................................................................................... 35 Table 13. Operating Conditions .............................................................................................................................................................. 35 Table 14. DC Characteristics: TTL Input Pad ......................................................................................................................................... 35 Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up ..................................................................................................... 36 Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down ................................................................................................ 36 Table 17. DC Characteristics: TTL Output Pad ...................................................................................................................................... 36 Table 18. DC Characteristics: PECL Input/Output Pad ....................................................................................................................... 37 Table 19. DC Characteristics: LVDS Input/Output Pad ....................................................................................................................... 38 Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813) .............................................................................. 39 Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) .............................................................................. 40 Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) .............................................................. 40 Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) ................................................................ 41 Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411) ................................................................... 41 Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) .............................................................................. 42 Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499) ........................................................... 42 Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE) .............................................................. 42 Table 28. Serial Interface Read Access Timing .................................................................................................................................... 45 Table 29. Serial Interface Write Access Timing ................................................................................................................................... 45 Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) ...................................................................................... 47 Table 31. Revision History ...................................................................................................................................................................... 49 Revision 2.01/December 2005 Semtech Corp. 3 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Pin Diagram Figure 2. ACS8515 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND IC AGND VA1+ INTREQ REFCLK DGND VD+ VD+ DGND DGND VD+ SRCSW VA2+ AGND IC FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF SEC1_POS SEC1_NEG SEC2_POS SEC2_NEG VDD5 Sync2k SEC1 SEC2 DGND VDD 1 ACS8515 LC/P Rev 2.1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SONSDHB IC IC IC IC NC DGND VDD O2 NC VDD DGND SDO IC IC IC PORB SCLK VDD VDD CSB SDI CLKE IC DGND VDD VDD IC VDD IC SEC3 IC NC - Not Connected, IC - Internally Connected Revision 2.01/December 2005 Semtech Corp. 4 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Pin Descriptions Table 1. Power Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 8, 9, 12 VD+ P - S u p p l y v o l t a g e : Digital supply to gates in analog section, +3.3 Volts. +/- 10% 22 VDD_DIFF P - S u p p l y v o l t a g e : Digital supply for differential output pins 19 & 20, +3.3 Volts. +/- 10% 27 VDD5 P - V D D 5 : Digital supply for +5 Volts tolerance to input pins. Connect to +5 volts (+/- 10%) for clamping to +5 v. Connect to VDD for clamping to +3.3 v. Leave floating for no clamping, input pins tolerant up to +5.5 v. 32, 36, 38, 39, 45, 46, 54, 57 VDD P - S u p p l y v o l t a g e : Digital supply to logic, +3.3 Volts. +/- 10% 4 VA1+ P - S u p p l y v o l t a g e : Analog supply to clock multipying APLL, +3.3 Volts. +/- 10% 14 VA2+ P - S u p p l y v o l t a g e : Analog supply to output APLL, +3.3 Volts. +/- 10% 7, 10, 11, 31, 40, 53, 58 DGN D P - S u p p l y G r o u n d : Digital ground for logic 21 GN D_DIFF P - S u p p l y G r o u n d : Digital ground for differential output pins 19 & 20 1, 3, 15 AGN D P - S u p p l y G r o u n d : Analog ground Table 2. No Connections PIN SYMB OL IO IO T YPE 55, 59 NC - - N o t C o n n e c t e d : Leave to Float 2, 16, 33, 35, 60, 61, 62, 63 IC - - I n t e r n a l l y C o n n e c t e d : Leave to Float 37 IC - - I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG control reset inp ut on next revision 41 IC - - I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG test mode select inp ut on next revision 49 IC - - I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG boundary scan clock inp ut on next revision 50 IC - - I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG serial test data outp ut on next revision 51 IC - - I n t e r n a l l y c o n n e c t e d : Leave to Float. Reserved for JTAG serial test data inp ut on next revision Revision 2.01/December 2005 Semtech Corp. N A M E /DE S CR I P T I O N 5 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 5 IN T R E Q O - 6 REFCLK I TTL R e f e r e n c e c l o c k : 12.8 MHz (refer to section headed Local Oscillator Clock) 13 SRCSW I T T LD S o u r c e s w i t c h i n g : Force fast source switching on SEC1 and SEC2 17 FrSync O TTL O u t p u t r e f e r e n c e : 8 kHz Frame Sync, 50:50 mark/space ratio output 18 MFrSync O TTL O u t p u t r e f e r e n c e : 2 kHz Multi-Frame Sync, 50:50 mark/space ratio output 19 20 O1POS O1N EG O LVDS/ PECL O u t p u t r e f e r e n c e : Programmable, default 38.88 MHz LVDS 23 24 SEC1_POS SEC1_N EG I LVDS/ PECL I n p u t r e f e r e n c e : Programmable, default 19.44 MHz LVDS 25 26 SEC2_POS SEC2_N EG I PECL/ LVDS I n p u t r e f e r e n c e : Programmable, default 19.44 MHz PECL 28 Sync2k I T T LD M u l t i - Fr a m e S y n c 2 k H z : Multi-Frame Sync input 29 SEC1 I T T LD I n p u t r e f e r e n c e : Programmable, default 8 kHz 30 SEC2 I T T LD I n p u t r e f e r e n c e : Programmable, default 8 kHz 34 SEC3 I T T LD I n p u t r e f e r e n c e : External standby reference clock source, programmable, default 19.44 MHz 42 CLKE I T T LD S C L K e d g e s e l e c t : SCLK active edge select, CLKE=1 selects falling edge of SCLK to be active, CLKE = 0 for rising edge 43 SDI I T T LD M i c r o p r o c e s s o r i n t e r f a c e a d d r e s s : Serial data input 44 CSB I T T LU C h i p s e l e c t ( a c t i v e l o w ) : This pin is asser ted Low by the microprocessor to enable the microprocessor inter face 47 SCLK I T T LD A d d r e s s L a t c h E n a b l e : default Serial data clock. When this pin transitions from low to high, the address bus inputs are latched into the internal registers 48 PORB I T T LU P o w e r o n r e s e t : Master reset. If PORB is forced Low, all internal states are reset back to default values I n t e r r u p t r e q u e s t : Software Interrupt enable Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor Revision 2.01/December 2005 Semtech Corp. 6 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 3 (continued). PIN SYMB OL IO IO T YPE 52 SDO O T T LD M i c r o p r o c e s s o r i n t e r f a c e a d d r e s s : Serial data outp ut 56 O2 O TTL O u t p u t r e f e r e n c e : 19.44 MHz fixed T T LD S O N E T S D H B : SON ET or SDH frequency select: sets the initial p ower-up state (or state after a PORB) of the SON ET/SDH frequency selection registers, addr 34h, bit 2 and addr 38, bits 5 and 6. When low SDH rates are selected (2.048 MHz etc) and when set high SON ET rates are selected (1.544 MHz etc). The register states can be changed after p ower up by software. 64 SON SDHB I N A M E /DE S CR I P T I O N FFunctional unctional Description The ACS8515 is a highly integrated, single-chip solution for `hit-less' protection switching of SEC clocks from Master and Slave SETS clock cards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching for Master/Slave SEC clock failure. The standby SEC clock will be selected if both the Master and Slave input clocks fail. The selection of the Master/Slave input can also be forced by a Force Fast Switch pin. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card - e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. The ACS8515 has three SEC clock inputs (Master, Slave and Standby) and a single MultiFrame Sync input, for synchronising the frame and multi-frame sync outputs. The ACS8515 generates two SEC clock outputs via PECL/LVDS and TTL ports, with spot frequencies from 1.544/2.048 MHz up to 311.04 MHz. The ACS8515 also provides an 8 kHz Frame Sync and 2 kHz Multi-Frame Sync output clock. The ACS8515 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). Revision 2.01/December 2005 Semtech Corp. 7 The ACS8515 includes an SPI compatible serial microprocessor port, providing access to the configuration and status registers for device setup. Local Oscillator Clock The Master system clock on the ACS8515 requires an external clock oscillator of frequency 12.80 MHz. The exact clock specification is dependent on the quality of Holdover performance required in the application. In most Line Card protection switching applications where there is a high chance that at least one SEC reference input will be available, the long term stability requirement for Holdover is not appropriate and an inexpensive crystal local oscillator can be used. In other applications where there may be a requirement for longer term Holdover stability to meet the ITU standards for Stratum 3, a higher quality oscillator can be used. Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, giving a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a - 5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) The TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. Clock speeds above 100 MHz should not be applied to the TTL ports. The PECL/LVDS ports support the full range of clock speeds, up to 155.52 MHz. The actual spot frequencies supported are: *2 kHz *4 kHz *8 kHz (and N x 8 kHz), *1.544 MHz (SONET)/2.048 MHz (SDH), *6.48 MHz, The ACS8515 supports up to three individual input reference clock sources via TTL/CMOS and PECL/ LVDS technologies. These interface technologies support +3.3 V and +5 V operation. *19.44 MHz, *25.92 MHz, *38.88 MHz, *51.84 MHz, Input Reference Clock Ports The input reference clock ports are arranged in groups. Group one comprises a TTL port (SEC1) and a PECL/LVDS port (SEC1POS and SEC1NEG). Group two comprises a TTL port (SEC2) and a PECL/LVDS port (SEC2POS and SEC2NEG). Group three comprises a TTL port (SEC3). For group one and group two, only one of the two input ports types must be active at any time, the other must not be driven by a reference input. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other low (GND), or set in LVDS mode and left floating (in which case one input is internally pulled high and the other low). SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit Revision 2.01/December 2005 Semtech Corp. 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 64). Specific frequencies and priorities are set by configuration. 8 *77.76 MHz, *155.52 MHz. The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways; 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the `lock8K' bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 4. Input Reference Source Selection and Group Allocation P or t N am e I n p u t P or t Te c h n o l o g y Fr e q u e n c i e s S u p p o r t e d S E C S ou r ce Gr ou p Def au l t P ri ori t y (N ote 3) SEC1 TTL/CMOS Up to 100MHz (N ote 1) Default (SON ET/SDH): 8kHz SEC2 TTL/CMOS Up to 100MHz (N ote 1) Default (SON ET/SDH): 8kHz SEC1 LVDS/PECL LVDS default SEC2 PECL/LVDS PECL default SEC3 SYN C1 1 1 (4) 2 3 (5) Up to 155.52MHz (N ote 2) Default (SON ET/SDH): 19.44MHz 1 2 (6) Up to 155.52MHz (N ote 2) Default (SON ET/SDH): 19.44MHz 2 4 (7) TTL/CMOS Up to 100MHz (N ote 1) Default (SON ET/SDH): 3 5 (10) TTL/CMOS 2kHz Multi Frame Sync - - 19.44MHz Notes for Table 4. Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are 2 kHz, 4 kHz, 8 kHz, N x 8 kHz, 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz. Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output clock frequencies available for SONET and SDH applications. Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the ACS8510. On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0. 2. Any multiple of any supported frequency can be supported by using the "DivN" feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to lock at 8 kHz independently of the frequencies and configurations of the other inputs. Any reference input with the `DivN' bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<214-1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the Revision 2.01/December 2005 Semtech Corp. 9 input frequency. When using the `DivN' feature the post-divider frequency must be 8 kHz, which is indicated by setting the `lock8k' bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (if the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the `DivN' feature, only one N can be programmed, hence all inputs using the `DivN' feature must require the same division to get to 8 kHz. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other input low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled high and the other low. Input Wander and Jitter Tolerance The ACS8515 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI DS1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for each input port in Table 5. Minimum jitter tolerance masks are specified in Figures 3 and 4, and Tables 6 and 7, respectively. The ACS8515 will tolerate wander and jitter components greater than those shown in Figure 3 and Figure 4, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). The `8klocking' mode should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. Table 5. Input Reference Source Jitter Tolerance J i t t er To l e r a n c e Fr e q u e n c y M o n i t o r A ccep t an ce R an g e G.703 G.783 G.823 Fr e q u e n c y A ccep t an ce R an g e ( Pu l l -i n ) Fr e q u e n c y A ccep t an ce R an g e ( H ol d - i n ) Fr e q u e n c y A ccep t an ce R an g e ( P u l l - ou t ) +/- 4.6 ppm (see N ote 1) +/- 4.6 ppm (see N ote 1) +/- 4.6 ppm (see N ote 1) +/- 9.2 ppm (see N ote 2) +/- 9.2 ppm (see N ote 2) +/- 9.2 ppm (see N ote 2) +/- 16.6 ppm GR-1244-CORE Notes for Table 5. Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm. Note 2. The default acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Revision 2.01/December 2005 Semtech Corp. 10 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Output Clock Ports The registers sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This is a 19 bit signed number with one LSB representing 0.0003 ppm (range of +/- 80 ppm). Reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. The ACS8515 supports two SEC output clocks, on TTL and PECL/LVDS ports, and a pair of secondary output clocks, `Frame-Sync' and `Multi-Frame-Sync'. The two output clocks are individually controllable. The `Frame-Sync' and `Multi-Frame-Sync' are derived from the main SEC clock. The frequencies of the output clock are selectable from a range of pre-defined spot frequencies, with a variety of output technologies supported, as defined in Table 8. The ACS8515 performs automatic frequency monitoring with an acceptable input frequency offset range of +/- 16.6 ppm. The ACS8515 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. Low Speed Output Clock The O2 SEC clock is supplied on a TTL port with a fixed frequency of 19.44 MHz. Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) (for inputs supporting G.783 compliant sources) A0 A1 A2 A3 A4 Jitter and wander frequency (l f0 f1 f2 f3 f4 f5 f6 f8 f9 Table 6. Amplitude and Frequency values for Jitter Tolerance (for inputs supporting G.783 compliant sources) P eak t o p eak am p l i t u d e ( u n i t I n t er v al ) ST M l evel STM-1 Fr e q u e n c y ( H z ) A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 F0 F0 F1 F1 F2 F2 F3 F3 F4 F4 F5 F5 F6 F6 F7 F7 F8 F8 F9 F9 2800 311 39 1.5 0.15 12u 178u 1.6m 15.6m 0.125 19.3 500 6.5k 65k 1.3m Revision 2.01/December 2005 Semtech Corp. 11 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 4. Minimum Input Jitter Tolerance (DS1/E1) (for inputs supporting G.783 compliant sources) Peak-to-peak jitter and wander amplitude (log scale) A1 A2 Jitter and wander frequency (log sc f1 f2 f3 f4 Table 7. Amplitude and Frequency values for Jitter Tolerance (for inputs supporting G.783 compliant sources) Ty p e S p ec. A mp l i tu d e ( U I p k-p k) Fr e q u e n c y ( Hz ) A1 A1 A2 A2 F1 F1 F2 F2 F3 F3 F4 F4 DS 1 G R - 1 24 4 - C O R E 5 0.1 10 500 8k 40k E1 E1 I T U G. 823 1.5 0.2 20 2.4k 18k 100k High Speed Output Clock Frame Sync and Multi-Frame Sync Clocks The O1 SEC clock is supplied on a PECL/LVDS port with spot frequencies of; Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks will be provided on outputs FrSync and MFrSync. The FrSync and MFrSync clocks have a 50:50 mark/space ratio. *19.44 MHz, *38.88 MHz, Low Jitter Multiple E1/DS1 Outputs *155.52 MHz, *311.04 MHz, *Dig 1. (where Dig 1 is 1.544 MHz (SONET)/2.048 MHz (SDH), and multiples of 2, 4 and 8 depending on SONET/SDH mode setting). The actual frequency is selectable via the cnfg_differential_outputs register. The O1 port can also support 311.04 MHz, which is enabled via the cnfg_T0_output_enable register. The O1 port can be made LVDS or PECL compatible via the cnfg_differential_outputs register. Revision 2.01/December 2005 Semtech Corp. 12 This feature added to Rev2.1 is activated using the cnfg_control1 register. This sends a frequency of twice the Dig2 rate (see reg addr 39h, bits 7:6) to the APLL instead of the normal 77.76MHz. For this feature to be used, the Dig2 rate must only be set to 12352kHz/16384kHz using the cnfg_T0_output_frequencies register. The normal OC3 rate outputs are then replaced with E1/DS1 multiple rates. The E1(SONET)/ DS1(SDH) selection is made in the same way as for Dig2 using the cnfg_T0_output_enable register. Table 9 shows the relationship between primary output frequencies and the corresponding output in E1/DS1 mode, and which output they are available from. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Output Wander and Jitter the application and operating state. Wander and jitter attenuation is performed by using a digital phase-locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. Since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. Strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. But, since Wander and jitter present on the output clocks are dependent on: 1. The magnitude of wander and jitter on the selected input reference clock (in locked mode); 2. The internal wander and jitter transfer characteristic (in Locked mode); 3. The jitter on the local oscillator clock; 4. The wander on the local oscillator clock (in Holdover mode). Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit Table 8. Output Reference Source Selection Table P or t N am e O u t p u t P or t Te c h n o l o g y O1 LVDS/PECL LVDS default O2 TTL/CMOS 19.44 MHz fixed FrSync TTL/CMOS FrSync, 8 kHz. 50:50 mark/space ratio MFrSync TTL/CMOS MFrSync, 2 kHz. 50:50 mark/space ratio Fr e q u e n c i e s S u p p o r t e d 19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz, Dig1 Dig1 is 1.544 MHz/2.048 MHz and multiples of 2, 4 and 8 Notes for Table 8. Dig 1 is shown as either 1.544 MHz or 2.048 MHz, where 1.544 MHz is SONET and 2.048 MHz is SDH. Pin SONSDHB controls the default frequency output. When SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default. Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs M od e Default Fr e q t o A PLL A P L L M u l t i p l i er 77.76 4 A PLL Fr e q cl k _ f i l t cl k _ f i l t /2 cl k _ f i l t /4 cl k _ f i l t /6 cl k _ f i l t /8 cl k _ f i l t /12 cl k _ f i l t / 16 cl k _ f i l t /48 DP L L Fr e q 311.04 311.04 155.52 77.76 51.84 38.88 25.92 19.44 6.48 77.76 n value 16 16 8 4 n x E1 32.768 4 131.072 131.072 65.536 3 2 . 76 8 21.84533 16 . 3 8 4 10.92267 8 .1 9 2 2.730667 77.76 n x T1 24.704 4 98.816 6 .176 2.058667 77.76 98.816 49.408 24 . 7 0 4 16.46933 1 2 . 3 5 2 8.234667 Frequencies Available by Output O1 O1 O1 O2 Revision 2.01/December 2005 Semtech Corp. 13 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 5. Wander and Jitter Transfer Measured Characteristics 5 0 -3 Gain (dB) -5 -10 0.1 Hz 0.3 Hz -15 0.5 Hz 1.0 Hz -20 2.0 Hz 4.0 Hz 8.0 Hz -25 -30 17 Hz 0.01 0.1 10 1 100 1000 Frequency (Hz) any buffer store potentially increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8515 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 5. Wander on the local oscillator clock will not have significant effect on the output clock whilst in locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section `Local Oscillator Clock'. Revision 2.01/December 2005 Semtech Corp. 14 Phase Variation There will be a phase shift across the ACS8515 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterized using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevent specifications, differ in acceptable limits in each one. Typical measurements for the ACS8515 are shown in Figures 6 and 7, for locked mode operation. Figure 8 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances pertaining: 1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 6. Maximum Time Interval Error of T OUT0 Output Port 1 00 G .8 1 3 o p tion 1 , co n sta n t te m p e rature w an de r lim it T im e (n s) 10 1 M T IE m e a su re m e n t o n 1 5 5 M H z o u tp u t, 1 9.44 M H z i/p (8 kH z lo ckin g), V e c tro n 6 6 6 4 x tal 0 .1 0 .0 1 0 .01 1 0.1 10 100 1000 10000 O b s erv a tio n in terva l (s) Figure 7. Time Deviation of T OUT0 Output Port 10 G .813 op tio n 1 con stan t tem perature w ander lim it T im e (ns ) 1 0.1 T D E V m ea su rem e nt on 1 55 M H z output, 1 9.4 4 M H z i/p (8kH z lock ing), V ectron 6 664 xtal 0 .01 0.01 0 .1 1 10 100 10 00 10 000 O b s erv ation in terv al (s) Figure 8. Phase Error Accumulation of T OUT0 Output Port in Holdover Mode 10000000 Phase Error (ns) 1000000 P e rm itte d P h a s e E rro r L im it 100000 10000 1000 100 T y p ic a l m e a s u re m e n t, 2 5 C c o n s ta n t te m p e ra tu re 10000 1000 Ob Revision 2.01/December 2005 Semtech Corp. 15 ti i t 100000 l( ) www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS 2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not exceed {(a1+a2)S+0.5bS2+c} where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16x10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). 3. ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of Holdover. This requires a frequency accuracy better than: ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm Temperature variation is not restricted, except to within the normal bounds of 0 to 50 Celsius. 4. Bellcore GR.1244.CORE, Section 5.2., Table 4, shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. ITU G.822, Section 2.6, requires that the slip rate during category(b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour ((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm on the output will still be less than the 120 ns allowed for in the G.813 spec. The actual value is dependant on the frequency being locked to. The PBO requirement, as specified in Telcordia GR1244-CORE, Section 5.7, in that a phase transient of greater than 3.5 s occuring in less than 0.1 seconds should be absorbed, will be implemented on a future version. ITU-T G.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. On the ACS8515, PBO can be enabled, disabled or frozen using the P interface. By default, it is enabled. When PBO is enabled, it can also be frozen, which will disable the PBO operation on the next input reference switch, but will remain with the current offset. If PBO is disabled while the device is in the Locked mode, there will be a phase jump on the output SEC clocks as the DPLL locks back to 0 degree phase error. Phase Build Out Microprocessor Interface Phase Build Out (PBO) is the function to minimise phase transients on the output SEC clock during input reference switching or mode switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. During this transition, the Lost_Phase mode is entered. The ACS8515 incorporates a serial microprocessor interface that is compatible with the Serial Peripheral Interface (SPI) for device setup. The typical phase disturbance on clock reference source switching will be less than 10 ns on the ACS8515. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance Revision 2.01/December 2005 Semtech Corp. 16 Register Set All registers are 8-bits wide, organised with the most-significant bit positioned in the left-most bit, with bit-significance decreasing towards the right-most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g., flags) upwards. Several data fields are spread across multiple registers; their organisation is shown in the register map. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Configuration Registers Interrupt Enable and Clear Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pinsettable. All configuration registers can be read out over the microprocessor port. Interrupt requests are flagged on pin INTREQ (active High). Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. Register Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_revision register. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a `1' into each bit of the field (writing a `0' value into a bit will not affect the value of the bit). Details of each register are given in the Register Map and Register Map Description sections. Revision 2.01/December 2005 Semtech Corp. 17 Bits in the interrupt status register are set (high) by the following conditions; 1. Any reference source becoming valid or going invalid 2. A change in the operating state (eg. Locked, Holdover etc.) 3. A brief loss of the currently selected reference source All interrupt sources are maskable via the mask register cnfg_interrupt_mask, each one being enabled by writing a '1' to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependent on the leaky bucket configuration of the activity monitors. The very fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Register Map Shaded areas in the map are `don't care' and writing either 0 or 1 will not affect any function of the device. Bits labelled `Set to 0' or `Set to 1' must be set as stated during initialisation of the device, either following power up, or after a power on reset (PORB). Failure to correctly set these bits may result in the device operating in an unexpected way. Some registers do not appear in this list, for example 07 and 08. These are either not used, or have test functionality. Do not write to any undefined registers as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. Table 10. Register Map A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 02 chip _revision (read only) 03 cnfg_control1 (read/write) 04 cnfg_control2 (read/write) 05 sts_interrup ts (read/write) 09 0A 4 Analog div sync Set to '0' 3 Set to '0' Phase loss flag limit SEC2DIFF 1 0 ( l sb ) 8k Edge Polarity Set to '0' Set to '0' Set to '0' Set to '1' Set to '0' SEC1DIFF SEC2 SEC1 Main ref failed SEC3 Op erating mode (2:0) sts_p riority_table (read only) Highest p riority valid source Currently selected reference source 3rd highest p riority valid source 2nd highest p riority valid source sts_curr_inc_offset (read only) Current increment offset (7:0) 0D Current increment offset (15:8) Current increment offset (18:16) 07 0E 2 sts_op erating_mode (read only) 0B 0C 5 Chip revision number (7:0) Op erating mode 06 6 sts_sources_valid (read only) SEC2DIFF SEC1DIFF SEC2 SEC1 0F 11 SEC3 sts_reference_sources (read/write) 12 status <SEC2> status <SEC1> status <SEC2DIFF> status <SEC1 DIFF> status <SEC3> 14 18 cnfg_ref_selection_p riority (read/write) Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' 19 p rogrammed _p riority <SEC2> p rogrammed _p riority <SEC1> 1A p rogrammed _p riority <SEC2DIFF> p rogrammed _p riority <SEC1DIFF> Revision 2.01/December 2005 Semtech Corp. 18 Set to '0' www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 10. Register Map (continued). A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 6 5 4 3 2 1 0 ( l sb ) Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' 1D Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' 1E Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' divn lock8k bucket_id <SEC1> (1:0) reference_source_frequency <SEC1> (3:0) 23 divn lock8k bucket_id <SEC2> (1:0) reference_source_frequency <SEC2> (3:0) 24 divn lock8k bucket_id <SEC1DIFF> (1:0) reference_source_frequency <SEC1DIFF> (3:0) 25 divn lock8k bucket_id <SEC2DIFF> (1:0) reference_source_frequency <SEC2DIFF> (3:0) 28 divn lock8k bucket_id <SEC3> (1:0) reference_source_frequency <SEC3> (3:0) 1B 1C 22 cnfg_ref_selection_p riority (read/write) (continued) cnfg_ref_source_frequency (read/write) 32 cnfg_op erating_mode (read/write) 33 cnfg_ref_selection (read/write) 34 cnfg_mode (read/write) 35 cnfg_control3 (read/write) 36 cnfg_differential_inp uts (read/write) 38 cnfg_outp ut_enable (read/write) 39 cnfg_O1_outp ut_frequencies (read/write) 3A cnfg_differential_outp ut (read/write) 3B 3C cnfg_bandwidth (read/write) Forced op erating mode force_select_reference_source A u to external 2k enable 311.04 MHz on O1 Phase alarm timeout enable Clock edge Set to '0' Set to '1' Set to '0' 1=SON ET 0=SDH for Dig1 41 Set to '0' External 2k Sync enable Rever tive mode SON ET/ SDH I/P SEC2DIFF PECL SEC1DIFF PECL Set to '0' O2 enable Set to '0' Set to '0' Set to '0' Set to '0' O1 LVDS enable O1 PECL enable Digital 1 O1 frequency selection Auto b/w switch acq/lock Acquisition bandwidth cnfg_nominal_frequency (read/write) Set to '0' N ormal/locked bandwidth N ominal frequency (7:0) 3D 40 p rogrammed _p riority <SEC3> N ominal frequency (15:8) cnfg_holdover_offset (read/write) Set to '0' cnfg_freq_limit (read/write) DPLL Frequency offset limit (7:0) DPLL Frequency offset limit (9:8) 42 Revision 2.01/December 2005 Semtech Corp. 19 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 10. Register Map (continued). A d d r. P a r a m e t e r N a m e ( Hex ) 43 cnfg_interrupt_mask (read/write) 44 Dat a B i t 7 ( m sb ) 6 5 4 3 2 1 0 ( l sb ) Set to '0' Set to '0' status SEC2DIFF status SEC1DIFF status SEC2 status SEC1 Set to '0' Set to '0' Oper. mode Main ref Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' status SEC3 Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' 45 46 cnfg_freq_divn (read/write) Divide-input-by-n ratio (7:0) Divide-input-by-n ratio (13:8) 47 48 cnfg_monitors (read/write) Ultra-fast switching External source switch enable Freeze phase buildout Phase buildout enable 50 cnfg_activ_upper_threshold 0 (read/write) Configuration 0: Activity alarm set threshold (7:0) 51 cnfg_activ_lower_threshold 0 (read/write) Configuration 0: Activity alarm reset threshold (7:0) 52 cnfg_bucket_size 0 (read/write) 53 cnfg_decay_rate 0 (read/write) 54 cnfg_activ_upper_threshold 1 (read/write) Configuration 1: Activity alarm set threshold (7:0) 55 cnfg_activ_lower_threshold 1 (read/write) Configuration 1: Activity alarm reset threshold (7:0) 56 cnfg_bucket_size 1 (read/write) 57 cnfg_decay_rate 1 (read/write) 58 cnfg_activ_upper_threshold 2 (read/write) Configuration 2: Activity alarm set threshold (7:0) 59 cnfg_activ_lower_threshold 2 (read/write) Configuration 2: Activity alarm reset threshold (7:0) 5A cnfg_bucket_size 2 (read/write) 5B cnfg_decay_rate 2 (read/write) 5C cnfg_activ_upper_threshold 3 (read/write) Configuration 3: Activity alarm set threshold (7:0) 5D cnfg_activ_lower_threshold 3 (read/write) Configuration 3: Activity alarm reset threshold (7:0) 5E cnfg_bucket_size 3 (read/write) 5F cnfg_decay_rate 3 (read/write) Revision 2.01/December 2005 Semtech Corp. Frequency monitors configuration (1:0) Configuration 0: Activity alarm bucket size (7:0) Configuration 0: decay_rate (1:0) Configuration 1: Activity alarm bucket size (7:0) Configuration 1: decay_rate (1:0) Configuration 2: Activity alarm bucket size (7:0) Configuration 2: decay_rate (1:0) Configuration 3: Activity alarm bucket size (7:0) Configuration 3: decay_rate (1:0) 20 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Register Map Description Table 11. Register Map Description A d d r. P a r a m e t e r N a m e ( Hex ) 02 Descr i p t i on chip _revision This read-only register contains the chip revision number This revision = 1 Last revision (engineering samp les) = 0 cnfg_control1 Bits (7:6) Def au l t Va l u e ( b i n ) 00000001 Unused Bi t 5 =1 32/24MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76Mhz. Thus the normal OC3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits (Reg. 39h Bits (7:6)) must be set to 11 for this mode. =0 77.76MHz to APLL Bi t 4 =1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section such that their phases align. This is necessary in order to have phase alignment between inputs and output clocks at OC3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be necessary to avoid the dividers getting out of synchronization when quick changes in frequency occur such as a force into Free-Run. =0 The dividers may get out of phase following step changes in frequency, but in this mode the correct number of high frequency edges is guarenteed within any synchronization period. The output will frequency lock (default). The device will always remain in synchronization 2 seconds from a reset, before the default setting applies. 03 Bits 3 X X 000000 Test control - leave unchanged, or set to '0' Bi t 2 =1 When in 8k locking mode the system will lock to the rising input clock edge. =0 When in 8k locking mode the system will lock to the falling input clock edge. 04 cnfg_control2 Bits (1:0) Test controls - leave unchanged, or set to '00' Bits (7:6) Unused. XX100010 Bits (5:3) define the p hase loss flag limit. By default set to 4 (100) which corresp onds to ap p roximately 140. A lower value sets a corresp onding lower p hase limit. The flag limit determines the value at which the DPLL indicates p hase lost as a result of inp ut jitter, a p hase jump , or a frequency jump on the inp ut. Bits (2:0) sts_interrup ts Test controls - leave unchanged or set to '010'. This register contains one bit for each bit of sts_sources_valid, one for loss of reference the device was locked to, and another for the op erating mode. All bits are active high. All bits excep t the 'main ref failed' bit (bit 14) are set on a 'change' in the state of the relevent status bit, i.e. if a source becomes valid, or goes invalid it will trigger an interrup t. If the Op erating Mode (register 9) changes state the interrup t will be generated. Bit 14 (main ref failed) of the interrup t status register is used to flag inactivity on the reference that the device is locked to much more quickly than the activity monitors can sup p or t. If bit 6 of the cnfg_monitors register (register 48) (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO p in of the device. All bits are maskable by the bits in the cnfg_interrup t_mask register. Each bit may be cleared individually by writing a '1' to that bit, thus resetting the interrup t. Any number of bits can be cleared with a single write op eration. Writing '0's will have no effect. Revision 2.01/December 2005 Semtech Corp. 21 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) 05 sts_interrupts (continued) Descr i p t i on Bits (7:6) Unused Bit 5 SEC2DIFF (sts_interrupts bit 5) Bit 4 SEC1DIFF (sts_interrupts bit 4) Bit 3 SEC2 (sts_interrupts bit 3) Bit 2 SEC1 (sts_interrupts bit 2) Bits (1:0) Unused B i ts 7 Operating mode (sts_interrupts bit 15) Bit 6 Main ref failed (sts_interrupts bit 14) Bits (5:1) Unused Bit 0 SEC 3 (sts_interrupts bit 8) Def au l t Va l u e ( b i n ) XX0000XX 06 00XXXXX0 09 sts_operating_mode sts_priority_table This read-only register holds the current operating state of the main state machine. Figure 10 show how the values of the 'operating state' variable match with the individual states. Bits (7:3) Unused Bits (2:0) 001 010 100 110 101 111 State Freerun (default) Holdover Locked Pre-locked Pre-locked2 Phase lost XXXXX001 This is a 16-bit read-only register. Bits (15:12) Third-highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the second-highest-priority valid source. Bits (11:8) Second-highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the highest-priority valid source. Bits (7:4) Highest-priority valid source: this is the channel number of the input reference source which is valid and has the highest priority; it may not be the same as the currently-selected reference source (due to failure history or changes in programmed priority). Bits (3:0) Currently-selected reference source: this is the channel number of the input reference source which is currently input to the DPLL. N ote that these registers are updated by the state machine in response to the contents of the cnfg_ref_selection_priority register and the ongoing status of individual channels; channel number '0000', appearing in any of these registers, indicates that no channel is available for that priority. 0A Bits (7:4) Bits (3:0) Highest-priority valid source (sts_priority_table bits (7:4)) Currently selected reference source (sts_priority_table bits (3:0)) 00000000 0B Bits (7:4) Bits (3:0) 3rd-highest-priority valid source (sts_priority_table bits (15:12)) 2nd-highest-priority valid source (sts_priority_table bits (11:8)) 00000000 sts_curr_inc_offset This read-only register contains a signed-integer value representing the 19 significant bits of the current increment offset of the digital PLL. The register may be read periodically to build up a historical database for later use during holdover periods (this would only be necessary if an external oscillator which did not meet the stability criteria described in Local Oscillator Clock section is used). The register will read 00000000 immediately after reset. 0C Bits (7:0) sts_curr_inc_offset bits (7:0) 00000000 0D Bits (7:0) sts_curr_inc_offset bits (15:8) 00000000 07 Bits (7:3) Unused Bits (2:0) sts_curr_inc_offset bits (18:16) XXXXX000 Revision 2.01/December 2005 Semtech Corp. 22 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) sts_sources_valid Descr i p t i on Def au l t Va l u e ( b i n ) This register contains a bit to show validity for every reference source. =1 Valid source =0 Invalid source (default) Bits (7:6) Unused Bit 5 SEC2DIFF Bit 4 SEC1DIFF Bit 3 SEC2 Bit 2 SEC1 Bits (1:0) Unused Bits (7:1) Unused Bit 0 SEC3 0E XX0000XX 0F XXXXXXX0 sts_reference_sources This register holds the status of each of the input reference sources. The status of each reference source is shown in a 4-bit field. Each bit is active high. To aid status checking, a copy of each status bit 3 is provided in the sts_sources_valid register. The status is repor ted as follows: (Each bit may be cleared individually) Status bit Status bit Status bit Status bit 3 = Source valid (no alarms) (bit 3 is combination of bits 0-2) (default 0) 2 = Out-of-band alarm (default 1) 1 = N o activity alarm (default 1) 0 = Phase lock alarm (default 0) Bits (7:4) Status of input reference source SEC2 Bits (3:0) Status of input reference source SEC1 Bits (7:4) Status of input reference source SEC2DIFF Bits (3:0) Status of input reference source SEC1DIFF Bits (7:4) Unused Bits (3:0) Status of input reference source SEC3 01100110 11 12 01100110 XXXX0110 14 cnfg_ref_selection_priority This register holds the priority of each of the input reference sources. The priority values are all relative to each other, with lower-valued numbers taking higher priorities. Only the values 1 to 15 (dec) are valid - '0' disables the reference source. Each reference source must be given a unique priority, however two sources given the same priority number will be assigned on a first in first out basis. It is recommended to reserve the priority value '1' as this is used when forcing reference selection via the cnfg_ref_selection register. If the user does not intend to use the cnfg_ref_selection register then priority value '1' need not be reserved. 18 Bits (7:0) Must be set to '00000000' during initialisation Bits (7:4) Programmed priority of input reference source SEC2 Bits (3:0) Programmed priority of input reference source SEC1 Bits (7:4) Programmed priority of input reference source SEC2DIFF Bits (3:0) Programmed priority of input reference source SEC1DIFF Bits (7:0) Must be set to '00000000' during initialisation Bits (7:4) Must be set to '0000' during initialisation Bits (3:0) Programmed priority of input reference source SEC3 1D Bits (7:0) Must be set to '00000000' during initialisation 11010001 1E Bits (7:0) Must be set to '00000000' during initialisation 11111110 01010100 19 1A 1B 00110010 01110110 1C 10011000 10111010 Revision 2.01/December 2005 Semtech Corp. 23 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) cnfg_ref_source_frequency Descr i p t i on Def au l t Va l u e ( b i n ) This register is used to set up each of the input reference sources. Bits (7:6) of each byte define the operation under taken on the input frequency, in accordance with the following key: 00 01 10 11 The input frequency is fed directly into the DPLL (default). The input frequency is internally divided down to 8 kHz, before being fed into the DPLL. (For high jitter tolerance). Unsuppor ted configuration - do not use Uses the division coefficient stored in registers 46 & 47 (cnfg_freq_divn) to divide the input by this value prior to being fed into the DPLL. The frequency monitors must be disabled. The divided down frequency should equal 8 kHz. The frequency (3:0) should be set to the nearest spot frequency just below the actual input frequency. The DivN feature works for input frequencies between 1.544 MHz and 100 MHz. Bits (5:4) together define which leaky bucket settings (0-3) are used, as defined in registers 50 to 5F. (default 00). Bits (3:0) define the frequency of the reference source in accordance with the following key: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 8 kHz (default SEC1, SEC2) 1544 kHz(SON ET)/2048 kHz(SDH) (As defined by Register 34, bit 2) 6.48 MHz 19.44 MHz (default SEC1DIFF, SEC2DIFF, SEC3) 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 2 kHz 4 kHz 22 Frequency of reference source SEC1 00000000 23 Frequency of reference source SEC2 00000000 24 Frequency of reference source SEC1DIFF 00000011 25 Frequency of reference source SEC2DIFF 00000011 28 Frequency of reference source SEC3 00000011 cnfg_operating_mode This register is used to force the device into a desired operating state, represented by the binary values shown in Figure 10. Value 0 (hex) allows the control state machine to operate automatically. 32 XXXXX000 cnfg_ref_selection Bits (7:3) Unused Bits (2:0) Desired operating state (as per Figure 10) This register is used to force the device to select a par ticular input reference source, irrespective of its priority. Writing to this register temporarily raises the selected input to priority '1'. Provided no other input is already programmed with priority '1', and rever tive mode is on, this source will be selected. Bits (7:4) 33 Unused Bits (3:0) 0000 Automatic selection 0011 SEC1 0100 SEC2 0101 SEC1DIFF 0110 SEC2DIFF 1001 SEC3 1111 Automatic selection (default) Other values should not be used. Revision 2.01/December 2005 Semtech Corp. 24 XXXX1111 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) cnfg_mode Descr i p t i on Def au l t Va l u e ( b i n ) This register contains several individual configuration fields, as detailed below: Bit 7 =1 Auto 2 kHz Sync Enable: External 2 kHz Sync will be enabled only when the source is locked to 6.48 MHz. Otherwise it will be disabled. (default). =0 Auto 2 kHz Sync Disable: The user controls this function using bit 3 of this register, as described below. Bit 6 =1 Phase Alarm Timeout enable: The p hase alarm will timeout after 100 seconds. (default). =0 Phase Alarm Timeout disable: The p hase alarm will not timeout and must be reset by software. Bit 5 =1 Rising Clock Edge selected: The device will reference to the rising edge of the external oscillator signal. =0 Falling Clock Edge selected: The device will reference to the falling edge of the external oscillator signal (default). Bit 4 Unused. Must be set to '0' during initialisation. 34 Bit 3 =1 External 2 kHz Sync Enable: The device will align the p hase of its internally generated Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of the signal sup p lied to the Sync2k p in. This inp ut should be from the 2 kHz Multi-Frame Sync of an ACS8510. =0 External 2 kHz Sync Disable: The device will ignore the Sync2k p in (default). 110X00X0 (SON SDHB=0) 110X01X0 (SON SDHB=1) Bit 2 =1 SON ET mode: The device exp ects the inp ut frequency of any inp ut channel given the value '0001' in the cnfg_ref_source_frequency register to be 1544 kHz. =0 SDH mode: The device exp ects the inp ut frequency of any inp ut channel given the value '0001' in the cnfg_ref_source_frequency register to be 2048 kHz. At star t up or reset the bit value will be defaulted to the setting of p in SON SDHB. This setting can subsequently be altered by changing this bit value. Bit 1 Unused Bit 0 = 1 Rever tive Mode: The device will switch to the highest p riority source shown in sts_p riority_table register, bits (7:4). = 0 N on-rever tive Mode: The device will retain the p resently selected source (default). cnfg_control3 35 cnfg_differential_inp uts 36 Bits (7:6) Unused Bits (5:4) Must be set to '10' during initialisation. Bits (3:0) Unused XX00XXXX This register contains two individual configuration fields Bits (7:2) Unused Bit 1 =1 =0 Inp ut SEC2DIFF is PECL comp atible (default) Inp ut SEC2DIFF is LVDS comp atible Bit 0 =1 =0 Inp ut SEC1DIFF is PECL comp atible Inp ut SEC1DIFF is LVDS comp atible (default) Revision 2.01/December 2005 Semtech Corp. 25 XXXXXX10 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) 38 cnfg_outp ut_enable Descr i p t i on Def au l t Va l u e ( b i n ) This register contains several individual configuration fields, as follows: Bit 7 =1 =0 O1 outp ut frequency set to 311.04 MHz O1 outp ut frequency set by Address 3A (5:4) (default) Bit 6 Unused. Must be set to '0' during initialisation. Bit 5 =1 =0 0X0XX1XX SON ET mode selected for Dig1 SDH mode selected for Dig1 (default) - see register cnfg_O1_outp ut_frequencies Bits (4:3) Unused. Must be set to '0' during initialisation. Bit 2 =1 =0 Outp ut p or t O2 enabled (19.44 MHz) (default) Outp ut p or t O2 disabled Bits (1:0) Unused. Must be set to '0' during initialisation. N ote: "Disabled" means the outp ut p or t holds a static logic value (the p or t is not Tri-stated). 39 cnfg_O1_outp ut_frequencies This register holds the frequency selections for each outp ut p or t, as detailed below. Bits (7:6) Unused Bits (5:4) 00 01 10 11 Dig1 1544 kHz/2048 kHz (default) 3088 kHz/4096 kHz 6176 kHz/8192 kHz 12352 kHz/16384 kHz Bits (3:2) Unused Bits (1:0) Unused XX00XXXX For Dig1 the frequency values are shown for SON ET/SDH. They are selected via the SON ET/SDH bits in register cnfg_outp ut_enable. 3A 3B cnfg_differential_outp ut cnfg_bandwidth This register holds the frequency selections and the p or t-technology typ e for the differential outp ut O1, as detailed below. Bits (7:6) Unused Bits (3:2) Unused Bits (5:4) 00 01 10 11 O1 38.88 MHz (default) 19.44 MHz 155.52 MHz Dig1 Bits (1:0) 00 01 10 11 O1 Por t disabled PECL-comp atible LVDS-comp atible (default) Unused XX00XX10 This register contains information used to control the op eration of the digital PLL. When bandwidth selection is set to automatic, the DPLL will use the acquisition bandwidth setting when out of lock, and the normal/locked bandwidth setting when in lock. When set to manual, the DPLL will alway use the normal/locked bandwidth setting. Bit 7 =1 =0 Automatic op eration Manual op eration (default) Bits (6:4) 000 001 010 011 100 101 110 111 Acquisition bandwidth 0.1 Hz 0.3 Hz 0.5Hz 1.0 Hz 2.0 Hz 4.0 Hz 8.0 Hz 17 Hz (default) Bit 3 Unused Revision 2.01/December 2005 Semtech Corp. 26 Bit (2:0) 000 001 010 011 100 101 110 111 0111X101 Loop bandwidth 0.1 Hz 0.3 Hz 0.5 Hz 1.0 Hz 2.0 Hz 4.0 Hz (default) 8.0 Hz 17 Hz www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) cnfg_nominal_frequency Descr i p t i on Def au l t Va l u e ( b i n ) This register holds a 16 bit unsigned integer allowing compensation for offset of the crystal oscillator from the nominal 12.8 MHz. See section Crystal Frequency Calibration. Default results in 0 ppm adjustment. 3C Bits (7:0) cnfg_nominal_frequency bits (7:0) 10011001 3D Bits (7:0) cnfg_nominal_frequency bits (15:8) 10011001 cnfg_holdover_offset This register holds 1 bit which must be set to '0' during initialization. Bit 7 Must be set to '0' during initialization 40 1XXXXXXX Bits (6:0) cnfg_freq_limit Unused This register holds a 10 bit unsigned integer rep resenting the p ull-in range of the DPLL. It should be set according to the accuracy of crystal imp lemented in the ap p lication, using the following formula; Frequency range +/- (p p m) = (cnfg_freq_limit x 0.0785)+0.01647 or cnfg_freq_limit = (Frequency range +/- (p p m) - 0.01647) / 0.0785 Default value when SRCSW is left unconnected or tied low is 9.3 p p m. Default value when SRCSW is high is the full range of around 80 p p m. 41 Bits (7:0) cnfg_freq_limit bits (7:0) Bits (7:2) Unused Bits (1:0) cnfg_freq_limits bits (9:8) 01110110 (SRCSW low) 11111111 (SRCSW high) XXXXXX00 (SRCSW low) XXXXXX11 (SRCSW high) 42 cnfg_interrup t_mask Each bit, if set '0' will disable the ap p rop riate interrup t source in the interrup t status register. Bit (7:6) Must be set to '00' during initialisation Bit 5 Status SEC2DIFF Bit 4 Status SEC1DIFF Bit 3 Status SEC2 Bit 2 Status SEC1 11111111 43 Bit (1:0) Must be set to '00' during initialisation Bit 7 Op er. mode Bit 6 Main ref 44 11111111 Bit (5:1) Must be set to '00000' during initialisation Bit 0 Interrup t source Bit (7:5) Unused 45 XXX11111 Bit (4:0) Must be set to '00000' during initialisation cnfg_freq_divn This 14 bit integer is used as the divisor for any inp ut to get the p hase locking frequency desired. Only active for inp uts with the DivN bit set to `1'. This will cause the inp ut frequency to be divided by (n+1) p rior to p hase comp arison, e.g. p rogram N to: ((inp ut freq)/8kHz)-1 The reference_source_frequency bits should be set to reflect the closest sp ot frequency to the inp ut frequency, but must be lower than the inp ut frequency. 46 Bits (7:0) cnfg_freq_divn bits (7:0) Bits (7:6) Unused Bits (5:0) cnfg_freq_divn bits (13:8) 47 00000000 XX000000 Revision 2.01/December 2005 Semtech Corp. 27 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). A d d r. P a r a m e t e r N a m e ( Hex ) cnfg_monitors Descr i p t i on Def au l t Va l u e ( b i n ) This register allows global configuration of monitors and control of p hase build out. Bit 7 Unused Bit 6 Unused Bit 5 =1 Enables ultra fast switching: Allows the DPLL to raise an activity alarm on the currently selected source after missing only a few cycles. See section on Ultra Fast Switching. =0 N ormal op eration (default) Bit 4 =1 Forces locking to SEC1 (p in 29) if p in SRCSW high, or SEC2 (p in 30) if p in SRCSW low =0 Pin SRCSW ignored, and automatic control enabled 48 X0000101 (SRCSW low) X0010101 (SRCSW high) Bit 3 =1 Will freeze the outp ut p hase relationship with the current inp ut to outp ut p hase offset =0 Allows changes in inp ut to outp ut p hase offset to take p lace (N ormal p hase build out mode) (default) Bit 2 =1 Enables p hase builtd out (default) =0 DPLL will allows lock to 0 Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15p p m, others are reserved for future use. 50 cnfg_activ_up p er_threshold 0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be raised. 00000110 51 cnfg_activ_lower_threshold 0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be cleared. 00000100 52 cnfg_bucket_size 0 Bits (7:0) set the maximum value that the leaky bucket can reach given an inactive inp ut. 00001000 cnfg_decay_rate 0 Bits (7:2) Unused Bits (1:0) control the leak rate of the leaky bucket. The fill-rate of the bucket is +1 for every 128 ms interval that has exp erienced some level of inactivity. The decay rate is p rogrammable in ratios of the fill rate. The ratio can be set to 1:1, 2:1, 4:1, 8:1 by using values of 00, 01, 10, 11 resp ectively. However, these buckets are not `true' leaky buckets in nature. The bucket stop s `leaking' when it is being filled. This means that the fill and decay rates can be the same (00 = 1:1) with the net effect that an active inp ut can be recognised at the same rate as an inactive one. 53 XXXXXX01 54 cnfg_activ_up p er_threshold 1 As for register 50 but for bucket 1. 00000110 55 cnfg_activ_lower_threshold 1 As for register 51 but for bucket 1. 00000100 56 cnfg_bucket_size 1 As for register 52 but for bucket 1. 00001000 57 cnfg_decay_rate 1 As for register 53 but for bucket 1. XXXXXX01 58 cnfg_activ_up p er_threshold 2 As for register 50 but for bucket 2. 00000110 59 cnfg_activ_lower_threshold 2 As for register 51 but for bucket 2. 00000100 5A cnfg_bucket_size 2 As for register 52 but for bucket 2. 00001000 5B cnfg_decay_rate 2 As for register 53 but for bucket 2. XXXXXX01 5C cnfg_activ_up p er_threshold 3 As for register 50 but for bucket 3. 00000110 5D cnfg_activ_lower_threshold 3 As for register 51 but for bucket 3. 00000100 5E cnfg_bucket_size 3 As for register 52 but for bucket 3. 00001000 5F cnfg_decay_rate 3 As for register 53 but for bucket 3. XXXXXX01 Revision 2.01/December 2005 Semtech Corp. 28 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority, where SEC1 is the highest priority, SEC2 is the second highest priority and SEC3 is the lowest priority. The priorities can be re-assigned with external software. The SEC1 reference source has inputs via either a low speed TTL input port or a high speed PECL/ LVDS input port. Similarly, the SEC2 reference source has both a low speed TTL or a high speed PECL/LVDS input port. The SEC3 (standby) reference source only has provision via a low speed TTL input port. There is provision for one sync clock input via a TTL port. Whilst SEC1, SEC2 and SEC3 reference source inputs can all be active at the same time, only one of the TTL or PECL/LVDS input ports for the SEC1 and SEC2 reference sources may be used at any time, the inactive port is ignored, by setting the priority of that port to zero. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. The ACS8510 has two modes of operation; Revertive and Non-Revertive. In Revertive mode, if a revalidated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. Many applications prefer to minimise the clock switching events and choose NonRevertive mode. In Non-Revertive mode , when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Selection of the re-validated source can only take place under software control the software should briefly enable Revertive mode to affect a switch-over to the higher priority source. If the selected source fails under these conditions the device will indicate that it is still locked to the failed reference. It will not select the higher priority source until instructed Revision 2.01/December 2005 Semtech Corp. 29 to do so by the software; by briefly setting the Revertive mode bit. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-Revertive mode remains on AND the device will remain indicating a locked state on the failed reference. This is the case even if there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switchover, regardless of whether Revertive or NonRevertive mode has been chosen. Automatic Control Selection When automatic selection is required, the cnfg_ref_selection registers must be set to allzero or all-one. The configuration registers, cnfg_ref_selection_priority, held in the P port are organised as 5, 4-bit registers with each representing an input reference port. Unused ports should be given the value '0000' in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 4. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the `no activity alarm' and cause a reference switch. This can be chosen to cause an interrupt to occur instead of, or as well as, causing the reference switch. Any of these registers can be subsequently set by external s/w if required. When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. The operating state (sts_operating_mode register) will always indicate `locked' in the mode. External Protection Switching Activity Monitoring Fast external switching between inputs SEC1 and SEC2 can also be triggered directly from a dedicated pin (SRCSW). This mode can be activated either by holding this pin high during reset, or by writing to bit 4 of register address 48Hex. The ACS8515 has a combined inactivity and irregularity monitor. The ACS8515 uses a `leaky bucket' accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By controlling the alarmsetting threshold, the point at which the alarm is triggered can be controlled. The point at which Once external protection switching is enabled, then the value of this pin directly selects either SEC1 (SRCSW high) or SEC2 (SRCSW low). If this mode is activated at reset by pulling the SRCSW pin high, then it configures the default frequency tolerance of SEC1 and SEC2 to +/80 ppm (register address 41Hex and 42Hex). Figure 9. Inactivity and Irregularity Monitoring inactivities/irregularities reference source bucket_size leaky bucket response upper_threshold lower_threshold programmable fall slopes (all programmable) alarm Revision 2.01/December 2005 Semtech Corp. 30 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS the alarm is cleared depends upon the decay rate and the alarm-clearing threshold. On the alarm-setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm-clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarmclearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 9. The `leaky bucket' accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The `fill rate' of the leaky bucket is, therefore, 8 units/second. The "leak rate" of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to `leak' at the same time as a `fill' is avoided by preventing a `leak' when a `fill' event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be Leaky bucket timing The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky bucket empty) will be: (cnfg_activ_upper_threshold N) secs 8 where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is 0.75 s. The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated as: (cnfg_decay_rate N) 2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_threshold N)) secs 8 where N is the number of the relevent leaky bucket configuration in each case. The default settings are shown in the following: 1 2 x (8-4) = 1.0 s 8 Revision 2.01/December 2005 Semtech Corp. 31 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Restoration of repaired reference sources is handled carefully to avoid inadvertant disruption of the output clock. The ACS8515 operates in a Non-Revertive mode by default. In this mode, if the restored reference source has a higher priority than the reference source which is currently selected, a switch-over to the restored source will not tale place automatically. A restored reference source will assume its correct place in the priority table but a switchover will only take place automatically upon failure of the currently selected source. It is possible to invoke a switch-over by external control or by enabling Revertive mode. Modes of Operation The transition from Free-run to Pre-locked occurs when the ACS8515 selects a reference source. Pre-Locked Mode The ACS8515 will enter the Locked state in a maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Locked Mode The ACS8515 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State Transition Diagram, Figure 10. The ACS8515 can operate in Forced or Automatic control. On reset, the ACS8515 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run Mode The Free-run mode is typically used following a power-on-reset or a device reset before network synchronization has been achieved. In Revision 2.01/December 2005 Semtech Corp. the Free-run mode, the timing and synchronization signals generated from the ACS8515 are based on the Master clock frequency provided from the external oscillator and are not synchronized to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. 32 The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8515 is in Locked mode, the output frequency and phase follows that of the selected input reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, 'in phase', is not applied in the conventional sense when the ACS8515 is used as a frequency translator (e.g., when the input frequency is 2.048 MHz and the output frequency is 19.44 MHz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Lost-Phase Mode Pre-Locked(2) Mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. This mode is similar in behavior to the Pre-locked or Pre-locked(2) modes, although in this mode the DPLL is attempting to regain lock to the same reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. 1. Go to Pre-Locked(2); - If a known-good standby source is available. 2. Go to Holdover; - If no standby sources are available. Holdover Mode The Holdover mode is used when the circuit was in Locked mode but the selected reference source has become unavailable and a replacement has not yet been selected. Power On Reset - PORB The Power On Reset (PORB) pin resets the device if forced Low for a power-on-reset to be initiated. The reset is asynchronous, the minimum low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset (POR) is required at power on, and may be re-asserted at any time to restore defaults. This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8515 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. Holdover freezes the DPLL at the current frequency (as reported by the sts_curr_inc_offset register). The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. Revision 2.01/December 2005 Semtech Corp. 33 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 10. Automatic Mode Control State Diagram (1)Reset free-run select ref (state 001) (2) all refs evaluated & at least one ref valid (3) no valid standby ref & (main ref invalid or out of lock >100s) Reference sources are flagged as 'val active, 'in-band' and have no phase ala (4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] pre-locked w ait for up to 100s (state 110) (5) selected ref phase locked All sources are continuously checked activity and frequency. Only the main source is checked for p A phase lock alarm is only raised on a reference when that reference has los whilst being used as the main referenc micro-processor can reset the phase alarm. A source is considered to have phase when it has been continuously in phas for between 1 and 2 seconds locked keep ref (state 100) (10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] pre-locked2 w ait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) (15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] Revision 2.01/December 2005 Semtech Corp. (8) phase regained within 100s (6) no valid standby ref & main ref invalid (7) phase lost on main ref Lost phase w ait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) holdover select ref (state 010) (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid 34 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Electrical Specification Important Note: Note The `Absolute Maximum Ratings' are stress ratings only, and functional operation of the device at conditions other than those indicated in the `Operating Conditions' sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 12. Absolute Maximum Ratings PA RA METER SYMB OL M IN IN M AX AX U N ITS Sup p ly Voltage VDD, VD+, VA1+,VA2+ VDD -0.5 3.6 V Inp ut Voltage (non-sup p ly p ins) Vin - 5.5 V Outp ut Voltage (non-sup p ly p ins) Vout - 5.5 V TA -40 85 C Tstor -50 150 C Ambient Op erating Temp erature Range Storage Temp erature Table 13. Operating Conditions PA RA METER SYMB OL MIN T YP MA X U N ITS Power Sup p ly (dc voltage) VDD, VD+,VA1+, VA2+, VDD_DIFF VDD 3.0 3.3 3.6 V Power Sup p ly (dc voltage) VDD5 VDD5 3.0 3.3/5.0 5.5 V TA -40 - 85 C Typ ical - one 19 MHz outp ut Maximum - 190 mA before s/w initialisation, 150 mA after s/w intialisation IDD - 110 190/150 mA Total p ower dissip ation PTOT - 360 685 mW Ambient Temp erature Range Sup p ly Current Table 14. DC Characteristics: TTL Input Pad Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Inp ut Current Ii n - - 10 A Revision 2.01/December 2005 Semtech Corp. 35 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-up Resistor PU 30 - 80 k! Inp ut Current Ii n - - 120 A Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-down Resistor PD 30 - 80 k! Inp ut Current Ii n - - 120 A Table 17. DC Characteristics: TTL Output Pad Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vout Low Iol = 4mA Vol 0 - 0.4 V Vout High Ioh = 4mA Voh 2.4 - Drive Current ID - - Revision 2.01/December 2005 Semtech Corp. 36 V 4 mA www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 18. DC Characteristics: PECL Input/Output Pad Across operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VILPECL VDD-2.5 - VDD-0.5 V Differential inp uts (N ote 1) VIHPECL VDD-2.4 - VDD-0.4 V Inp ut Differential voltage VIDPECL 0.1 - 1.4 V VILPECL_S VDD-2.4 - VDD-1.5 V VIHPECL_S VDD-1.3 - VDD-0.5 V IIHPECL -10 - +10 A IILPECL -10 - +10 A VOLPECL VDD-2.10 - VDD-1.62 V VOHPECL VDD-1.25 - VDD-0.88 V VODPECL 580 - 900 mV PECL Inp ut Low voltage Differential inp uts (N ote 1) PECL Inp ut High voltage PECL Inp ut Low voltage Single ended inp ut (N ote 2) PECL Inp ut High voltage Single ended inp ut (N ote 2) Inp ut High current Inp ut differential voltage VID = 1.4v Inp ut Low current Inp ut differential voltage VID = 1.4v PECL Outp ut Low voltage (N ote 3) PECL Outp ut High voltage (N ote 3) PECL Outp ut Differential voltage (N ote 1) Notes for Table 18 Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 ! load on each pin to VDD-2 V . i.e. 82 ! to GND and 130 ! to VDD. Revision 2.01/December 2005 Semtech Corp. 37 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 11. Recommended Line Termination for PECL Input/Output Ports V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 130R SEC1_POS 130R 82R ZO=50 V DD SEC1_NEG 82R ZO=50 130R O1POS GND ZO=50 130R 82R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 O1NEG V DD 82R 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 130R SEC2_POS ZO=50 GND 130R 82R SEC2_NEG VDD = +3.3 V 82R GND Table 19. DC Characteristics: LVDS Input/Output Pad Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VVRLVDS 0 - 2.40 V VDITH -100 - +100 mV VIDLVDS 0.1 - 1.4 V R TERM 95 100 105 W VOHLVDS - - 1.585 V VOLLVDS 0.885 - - V (N ote 1) VODLVDS 250 - 450 mV LVDS Charge in magnitude of differential outp ut voltage for comp limentary states VDOSLVDS - - 25 mV VOSLVDS 1.125 - 1.275 V LVDS Inp ut voltage range Differential inp ut voltage = 100 mV LVDS Differential inp ut threshold LVDS Inp ut Differential voltage LVDS Inp ut termination resistance Must be p laced externally across the LVDS+/- inp ut p ins of ACS8515. Resistor should be 100 ohm with 5% tolerance LVDS Outp ut high voltage (N ote 1) LVDS Outp ut low voltage (N ote 1) LVDS Differential outp ut voltage (N ote 1) LVDS outp ut offset voltage Temp erature = 25C (N ote 1) Note 1. With 100 ! load between the differential outputs. Revision 2.01/December 2005 Semtech Corp. 38 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Figure 12. Recommended Line Termination for LVDS Input/Output Ports 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 SEC1_POS ZO=50 100R SEC1_NEG ZO=50 O1POS ZO=50 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz 100R 19.44, 311.04 O1NEG ZO=50 SEC2_POS ZO=50 100R SEC2_NEG Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 TE S T D E F I N I T I O N FIL T E R U SE D G.813 for 155.52 MHz op tion 1 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 2) G.813 for 155.52 MHz op tion 1 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) G.813 for 155.52 MHz op tion 2 12 kHz to 1.3 MHz UIpp = 0.1 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G.813 & G.812 for 2.048 MHz op tion 1 UIpp = 0.05 20 Hz to 100 kHz Revision 2.01/December 2005 Semtech Corp. 39 0.046 (N ote 14) www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 G.812 for 1.544 MHz 10 Hz to 40 kHz UIpp = 0.05 0.036 (N ote 14) G.812 for 155.52 MHz electrical 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 3) G.812 for 2.048 MHz electrical 65 kHz to 1.3 MHz U Ip p = 0.075 0.048 (N ote 3) Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 ETS-300-462-3 for 2.048 MHz SEC 20 Hz to 100 kHz UIpp = 0.5 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.2 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SSU 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) ETS-300-462-3 for 155.52 MHz 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 3) ETS-300-462-3 for 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 3) Revision 2.01/December 2005 Semtech Corp. 40 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 GR-253-CORE net i/f, 51.84 MHz 100 Hz to 400 kHz UIpp = 1.5 0.022 (N ote 3) GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) 18 kHz to 400 kHz UIpp = 0.15 0.019 (N ote 3) GR-253-CORE net i/f, 155.52 MHz 500 Hz to 1.3 MHz UIpp = 1.5 0.058 (N ote 3) GR-253-CORE net i/f, 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.15 0.048 (N ote 3) UIpp = 0.1 0.058 (N ote 3) UIrms = 0.01 0.006 (N ote 3) UIpp = 0.1 0.017 (N ote 3) UIrms = 0.01 0.003 (N ote 3) UIpp = 0.1 0.036 (N ote 14) UIrms = 0.01 0.0055 (N ote 14) GR-253-CORE cat II elect i/f, 155.52 MHz 12 kHz to 1.3 MHz GR-253-CORE cat II elect i/f, 51.84 MHz 12 kHz to 400 kHz GR-253-CORE DS1 i/f, 1.544 MHz 10 Hz to 40 kHz Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) 10 Hz to 40 kHz UIrms = 0.02 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz Broadband UIrms = 0.05 0.0055 (N ote 14) Revision 2.01/December 2005 Semtech Corp. 41 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 G.742 for 2.048 MHz DC to 100 kHz UIpp = 0.25 0.047 (N ote 14) G.742 for 2.048 MHz (Filter spec 18 kHz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) G.742 for 2.048 MHz 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N FIL T E R U SE D U I SPE C U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 TR-N WT-000499 & G.824 for 1.544 MHz 10 Hz to 40 kHz UIpp = 5.0 0.036 (N ote 14) TR-N WT-000499 & G.824 for 1.544 MHz (Filter spec 8 kHz to 40 kHz) 10 Hz to 40 kHz UIpp = 0.1 0.036 (N ote 14) Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. TE S T D E F I N I T I O N GR-1244-CORE for 1.544 MHz FIL T E R U SE D U I SPE C >10 Hz Revision 2.01/December 2005 Semtech Corp. UIpp = 0.05 42 U I M E A S U R E M E N T O N A C S 8 51 5 REV 2 0.036 (N ote 14) www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Notes for tables 20 - 227 Note 1. Filter used is that defined by test definition unless otherwise stated Note 2. 5 Hz bandwidth, 19.44 MHz input, direct lock Note 3. 5 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 4. 20 Hz bandwidth, 19.44 MHz input, direct lock Note 5. 20 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 6. 10 Hz bandwidth, 19.44 MHz input, direct lock Note 7. 10 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 8. 2.5 Hz bandwidth, 19.44 MHz input, direct lock Note 9. 2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 10. 1.2 Hz bandwidth, 19.44 MHz input, direct lock Note 11. 1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 12. 0.6 Hz bandwidth, 19.44 MHz input, direct lock Note 13. 0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock Note 14. 5 Hz bandwidth, 2.048 MHz input, 8 kHz lock Figure 13. Input/Output Timing Input/Output Typical Delay 8 kHz input Output 1.5 ns Typical Phase Alignment 8 kHz output 8 kHz 6.48 MHz input 2 kHz < 1 ns +6.5 to +8.5 ns 6.48 MHz output 19.44 MHz input +5.5 to +7.5 ns T1 +3.5 to +5.5 ns (Multiples have the same offset) E1 +3.5 to +5.5 ns (Multiples have the same offset) 19.44 MHz output 25.92 MHz input 6.48 MHz +3.0 to +5.0 ns 19.44 MHz +2.5 to +4.5 ns 25.92 MHz +3.0 to +5.0 ns 38.88 MHz +3.0 to +4.5 ns 51.84 MHz +6.0 to +8.0 ns (Additional delay for this output) 77.76 MHz +2.0 to +4.0 ns +6.5 to +8.5 ns 25.92 MHz output 38.88 MHz input +4.0 to +6.0 ns 38.88 MHz output 51.84 MHz input +6.0 to +8.0 ns 51.84 MHz output 77.76 MHz input +5.5 to +7.5 ns 155.52 MHz < 1 ns 311.04 MHz < 0.5 ns 77.76 MHz output Revision 2.01/December 2005 Semtech Corp. 43 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Microprocessor Interface Timing The device has a Serial microprocessor interface. The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. Figure 14. Read Access Timing CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 tpw2 th2 SCLK th1 tsu1 _ SDI R/W tpw1 A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK _ SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 F8525D_013ReadAccSerial_01 Revision 2.01/December 2005 Semtech Corp. 44 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 28. Read Access Timing S y m b ol P ar am et er MIN T YP MA X 0 ns - - 160 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge td 1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1)to SDO valid - - 17 ns td 2 Delay CSBrising edge to SDO high-Z - - 10 ns tp w 1 SCLK low time CLKE = 0 CLKE = 1 250 ns 500 ns - - tp w 2 SCLK high time CLKE = 0 CLKE = 1 250 ns 500 ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time b etween consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Figure 15. Write Access Timing CSB tsu2 tpw2 th2 SCLK th1 tsu1 _ SDI SDO R/W tpw1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Output not driven, pulled low by internal resistor F8525D_014WriteAccSerial_01 Table 29. Write Access Timing S y m b ol P ar am et er MIN T YP MA X 0 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - tp w 1 SCLK low time 180 ns - - tp w 2 SCLK high time 180 ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Revision 2.01/December 2005 Semtech Corp. 45 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Package Information Figure 16. LQFP Package D 2 D1 1 3 AN2 1 R1 S E 2 AN1 E1 1 A A B 3 L 4 L1 5 1 2 3 b 7 e A A2 c 7 Seating plane A1 6 b1 7 b Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm. 2 To be determined at seating plane. 3 Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4 Details of pin 1 identifier are optional but will be located within the zone indicated. 5 Exact shape of corners can vary. 6 A1 is defined as the distance from the seating plane to the lowest point of the package body. 7 These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead 8 Shows plating. Revision 2.01/December 2005 Semtech Corp. 46 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) 64 L Q F P P ack ag e Di m en si on s i n mm D/E D1/E 1 Mi n N om Max 12.00 10.00 A A1 A1 A2 A2 1.40 0.05 1.35 1.50 0.10 1.40 1.60 0.15 1.45 e 0.50 AN1 AN2 AN3 AN4 R1 R1 R2 R2 L 11 11 0 0 0.08 0.08 0.45 12 12 - 3.5 - - 0.60 13 13 - 7 - 0.20 0.75 L1 L1 1.00 (ref) S b b1 b1 c c1 c1 0.20 0.17 0.17 0.09 0.09 - 0.22 0.20 - - - 0.27 0.23 0.20 0.16 Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 17. Typical 64 Pin LQFP Footprint 14.3 mm 13.0 mm (1) 10.6 mm 1.85 mm Pitch 0.5 mm Width 0.3 mm Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example - the user is responsible for ensuring compatibility with PCB manufacturing process, etc. Revision 2.01/December 2005 Semtech Corp. 47 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Application Information Figure 18. Simplified Application Schematic Revision 2.01/December 2005 Semtech Corp. 48 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Appendix A Rev2.1 Changes Described Summary This section summarizes the minor changes and improvements made to the ACS8515 from Rev2.0 to Rev2.1. The bulk of these changes are designed to remove the need for software work arounds associated with Phase Build Out. Two new features have been added, necessitating changes to the control software. These are described in detail below. Input Edge Alignment for 8k locking mode An additional bit in the register cnfg_control1 (Bit 2) has been allocated to select which edge of the input reference to lock to when the device is configured in 8k locking mode. This bit, when set to one ensures that the rising edge of the output clock phase locks to the rising edge of the input clock, when 8k locking mode is used on the input. Low Jitter n x E1/DS1 Mode A second bit of the cnfg_control1 register has been allocated to controlling what frequency is fed into the APLL. This allows the user to switch from the normal 77.76MHz to twice the dig2 output frequency. This has the effect of replacing the normal OC/STM outputs with multiples of the E1 or DS1 rate. The E1/DS1 choice is controlled by the SONET/SDH bit in the cnfg_mode register. Revision History Table 31. Changes from Revision 1.05 to 2.00 September 2003. Item 1 Section Non-Revertive Mode Page 29 Description Updated Non-Revertive mode description Revision 2.01/December 2005 Semtech Corp. 49 www.semtech.com ACS8515 Rev2.1 LC/P FINAL ADVANCED COMMUNICATIONS Ordering Information PA R T N U M B E R DE S CR I P T I O N A CS8515 Rev2.1 SON ET/SDH Li n e Card Protecti on , 64 p i n LQFP A CS8515 Rev2.1T Lead (Pb ) - free p ackage versi on of A CS8515 rev 2.1 Disclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user's implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards. For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com USA: 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 ISO9001 CERTIFIED Revision 2.01/December 2005 Semtech Corp. 50 www.semtech.com