Features * Processor Bus Frequency up to 100 MHz * 64-bit or 32 bits Data Bus and 32-bit Address Bus * Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible IEEE 1149.1 Compliant, JTAG Boundary-scan Interface PD Max = 1W (66 MHz), Full Operating Conditions Nap, Doze and Sleep Modes for Power Savings Two-channel Integrated DMA Controller Message Unit - Intelligent Input/Output (Two-wire Interface) Message Controller - Two Door Bell Registers - Inbound and Outbound Messaging Registers * Inter-Integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support * Embedded Programmable Interrupt Controller (EPIC) - Five Hardware Interrupts (IRQs) or 16 Serial Interrupts - Four Programmable Timers * * * * * * * Description The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between the Peripheral Component Interconnect, (PCI) bus and PowerPC 603eTM, PowerPC 740TM, PowerPC 750TM or PC7400 microprocessors. PCI support allows system designers to design systems quickly using peripherals already designed for PCI and other standard interfaces available in the personal computer hardware environment. The PC107A provides many other necessities for embedded applications including a high-performance memory controller and dual processor support, 2-channel flexible DMA controller, an interrupt controller, an I2O-ready message unit, an inter-integrated circuit controller (Two-wire Interface), and low skew clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller (EPIC) featuring five hardware interrupts (IRQ's) as well as sixteen serial interrupts along with four timers. The PC107A uses an advanced, 2.5V HiP3 process technology and is fully compatible with TTL devices. PCI Bridge Memory Controller PC107A Preliminary Specification alpha Site ZF PBGA 503 Flip-chip Plastic Ball Grid Array Screening This product is manufactured in full compliance with : * PBGA upscreenings based upon Atmel standards * Full military temperature range (Tj = -55C,+125C) * Industrial temperature range (Tj = -40C,+110C) Rev. 2137A-HIREL-06/02 1 General Description Simplified Block Diagram The PC107A integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers, a message unit with an Intelligent Input/Output (I2O) message controller, and an Inter-integrated Circuit (two-wire interface) controller. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. Figure 1 shows the major functional units within the PC107A. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented. Figure 1. PC107A Block Diagram Additional features: * Programmable I/O * with Watchpoint * JTAG/COP Interface * Power Management MPC107 60x Bus Interface (64- or 32-Bit Data Bus) Peripheral Logic Block Message Unit (with I2O) DMA Controller Address (32-Bit) Data (64-Bit) Data Path ECC Controller Data Bus (64- or 32-bit) with 8-bit Parity or ECC Memory Controller Memory/ROM/ Port X Control/ Address Central Control Unit Configuration Registers I2C 5 IRQs/ 16 Serial Interrupts I2C Controller EPIC Interrupt Controller /Timers PCI Bus Interface Unit Address Translator 32-Bit PCI Interface 2 PCI Arbiter Five Request/Grant Pairs SDRAM_SYNC_IN DLL SDRAM Clocks CPU Clocks PLL PCI_SYNC_IN Fanout Buffers PCI Bus Clocks OSC_IN PC107A 2137A-HIREL-06/02 PC107A General Parameters The following list provides a summary of the general parameters of the PC107A: Parameter Features Technology 0.29 m CMOS, five-layer metal Die size 50 mm2 Transistor count 0.96 million Logic design Fully-static Package Surface mount 503 Plastic Ball Grid Array (C4/PBGA) Core power supply 2.5V 5% V DC (nominal; see Table 3 on page 12 for recommended operating conditions) I/O power supply 3.0V to 3.6V DC The PC107A provides an integrated high-bandwidth, high-performance interface between up to two 60x processors, the PCI bus, and main memory. This section summarizes the features of the PC107A. Major features of the PC107A are as follows: * * Memory Interface - 64-/32-bit 100 MHz bus - Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM - High-bandwidth bus (32-/64-bit data bus) to DRAM - Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to four banks of 256-Mbit SDRAM devices - Supports 1-Mbyte to 1-Gbyte DRAM memory - 144 Mbytes of ROM space - 8-, 32-, or 64-bit ROM - Write buffering for PCI and processor accesses - Supports normal parity, read-modify-write (RMW), or ECC - Data-path buffering between memory interface and processor - Low-voltage TTL logic (LVTTL) interfaces - Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing 32-bit PCI Interface Operating up to 66 MHz - PCI 2.1-compliant - PCI 5.0V tolerance - Support for PCI locked accesses to memory - Support for accesses to PCI memory, I/O, and configuration spaces - Selectable big- or little-endian operation - Store gathering of processor-to-PCI write and PCI-to-memory write accesses - Memory prefetching of PCI read accesses - Selectable hardware-enforced coherency - PCI bus arbitration unit (five request/grant pairs) - PCI agent mode capability - Address translation unit - Some internal configuration registers accessible from PCI 3 2137A-HIREL-06/02 * * - Supports direct mode or chaining mode (automatic linking of DMA transfers) - Supports scatter gathering-read or write discontinuous memory - Interrupt on completed segment, chain, and error - Local-to-local memory - PCI-to-PCI memory - PCI-to-local memory - PCI memory-to-local memory Message Unit - Two doorbell registers - An extended doorbell register mechanism that facilitates interprocessor communication through interrupts in a dual-local-processor system - Two inbound and two outbound messaging registers - I2O message controller * Two-wire Interface Controller with Full Master/Slave Support (Except Broadcast All) * Embedded Programmable Interrupt Controller (EPIC) - Five hardware interrupts (IRQs) or 16 serial interrupts - Four programmable timers * Integrated PCI Bus, CPU, and SDRAM Clock Generation * Programmable PCI Bus, 60x, and Memory Interface Output Drivers * Dynamic Power Management - Supports 60x Nap, Doze, and Sleep Modes * Programmable Input and Output Signals with Watchpoint Capability * Built-in PCI Bus Performance Monitor Facility * Debug Features * 4 Two-channel Integrated DMA Controller (Writes to ROM/Port X Not Supported) - Error injection/capture on data path - IEEE 1149.1 (JTAG)/test interface Processor Interface - Supports up to two PowerPCTM microprocessors with 60x bus interface - Supports various operating frequencies and bus divider ratios - 32-bit address bus, 64/32-bit data bus supported at 100 MHz - Supports full memory coherency - Supports optional local bus slave - Decoupled address and data buses for pipelining of 60x accesses - Store gathering on 60x-to-PCI writes - Concurrent transactions on 60x and PCI buses supported PC107A 2137A-HIREL-06/02 PC107A Pin Assignments Pinout Listings Table 1 provides the pinout listing for the PC107A, 503 PBGA package. Table 1. PC107A Pinout Listing Signal Name Package Pin Number Supply Voltage Output Driver Type Notes I/O BVDD DRV_CPU (4) Output BVDD DRV_CPU I/O BVDD DRV_CPU Pin Type 60x Processor Interface Signals A[0-31] AE22, AE16, AA14, AE17, AD21, AD14, AD20, AB16, AB20, AB15, AA20, AD13, Y15, AE12, AD15, AB9, AB14, AA8, AC13, Y12, Y11, AE15, AE13, AA16, Y13, AB8, AD12, AE10, AB13, Y9, Y8, AD9 AACK AC7 ARTRY Y7 BG0 AE11 Output BVDD DRV_CPU BG1 AD11 Output BVDD DRV_CPU BR0 AB17 Input BVDD - BR1 Y14 Input BVDD - CI AD16 I/O BVDD DRV_CPU DBG0 AC10 Output BVDD DRV_MEM_ADDR DBG1 AD10 Output BVDD DRV_MEM_ADDR DBGLB AB10 Output BVDD DRV_MEM_ADDR DH[0-31] P1, R1, P2, T4, T1, T3, R4, P6, U6, V5, V2, T5, U1, R6, W1, V4, W2, U4, T2, V6, W3, W5, Y1, Y2, Y4, Y5, AA1, AA2, AA4, AB1, AB3, AB4 I/O BVDD DRV_CPU (4) DL[0-31] AA7, W6, AB6, AA6, AB5, AC4, AD3, AB7, AE1, W4, N6, M1, N3, N4, N5, N1, M2, R2, V1, P5, P4, N2, U2, AE4, AE6, AE2, AE3, AE7, AD5, AB2, AC2, AC1 I/O BVDD DRV_CPU (4) DP[0-7] AE9, AD6, AD8, AD1, AE8, AD7, AD4, AE5 I/O BVDD DRV_CPU (4) GBL AD17 I/O BVDD DRV_CPU LBCLAIM Y17 Input BVDD TA AE14 I/O BVDD DRV_CPU TBST AE21 I/O BVDD DRV_CPU TEA AB11 Output BVDD DRV_CPU TS AA10 I/O BVDD DRV_CPU (15) TSIZ[0-2] AE19, AD18, AB18 I/O BVDD DRV_CPU (4) TT[0-4] AD19, AC19, AB19, AA19, AA18 I/O BVDD DRV_CPU (4) (15) (10) (15) 5 2137A-HIREL-06/02 Table 1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number WT AC16 Pin Type Supply Voltage Output Driver Type I/O BVDD DRV_CPU Notes PCI Interface Signals AD[31-0] N23, N21, M20, M21, M22, M24, M25, L20, L22, K25, K24, K23, K21, J20, J24, J25, H20, F24, E25, F21, E24, E22, D25, A25, B25, A23, B23, B22, C22, C25, D23, D21 I/O OVDD DRV_PCI (4)(11) C/BE[0-3] L24, J22, G22, A24, I/O OVDD DRV_PCI (4)(11) DEVSEL G23 I/O OVDD DRV_PCI (6)(11) FRAME G20 I/O OVDD DRV_PCI (6)(11) GNT[4-0] T24, P22, P21, R22, N20 Output OVDD DRV_PCI (4)(11) IDSEL L25 Input OVDD - INTA V21 Output OVDD DRV_PCI (6)(11)(12) IRDY H24 I/O OVDD DRV_PCI (6)(11) LOCK G21 Input OVDD - (6) PAR G24 I/O OVDD DRV_PCI (11) PERR G25 I/O OVDD DRV_PCI (6)(11)(13) REQ[4-0] W25, V25, U25, T25, T23 Input OVDD - (10) SERR F25 I/O OVDD DRV_PCI (6)(11)(12) STOP H21 I/O OVDD DRV_PCI (6)(11) TRDY H25 I/O OVDD DRV_PCI (6)(11) Memory Interface Signals AS A4 Output GVDD DRV_MEM_ADDR CAS/DQM[0-7] A2, B1, A11, A10, B3, C2, F12, D11 Output GVDD DRV_MEM_ADDR (4) CKE A12 Output GVDD DRV_MEM_ADDR (1) FOE A13 I/O GVDD DRV_MEM_ADDR (1)(2) MDH[0-31] M6, L4, L6, K2, K4, K5, J4, J6, H4, H5, G3, G5, G6, F5, F1, E1, B14, D15, B15, E16, D16, C16, D18, D17, B17, F18, E19, E20, B19, B20, B21, A22 I/O GVDD DRV_MEM_DATA (4) MDL[0-31] M5, L1, L2, K1, K3, J1, J2, H1, H2, H6, G2, G4, F4, G1, F2, E2, F14, F15, A16, F17, B16, A17, A18, A19, B18, E18, D19, F19, A20, C19, D20, A21 I/O GVDD DRV_MEM_DATA (3)(4) PAR/AR[0-7] D2, C1, A15, A14, D1, D3, F13, C13 I/O GVDD DRV_MEM_DATA (4) RAS/CS[0-7] E6, C4, D5, E4, C10, F11, B10, B11 Output GVDD DRV_MEM_ADDR (4) RCS0 D10 I/O GVDD DRV_MEM_ADDR (1)(2) RCS1 B9 Output GVDD DRV_MEM_DATA RCS2 B5 Output GVDD DRV_MEM_ADDR 6 PC107A 2137A-HIREL-06/02 PC107A Table 1. PC107A Pinout Listing (Continued) Pin Type Supply Voltage Output Driver Type D7 Output GVDD DRV_MEM_ADDR SDBA0 A9 Output GVDD DRV_MEM_ADDR SDBA1 A8 Output GVDD DRV_MEM_ADDR SDCAS D4 Output GVDD DRV_MEM_ADDR (1) SDMA[13-0] E10, F9, D9, F8, E8, D8, B8, E7, C7, B7, A7, B6, A6, A5 Output GVDD DRV_MEM_ADDR (4)(5) SDRAS B4 Output GVDD DRV_MEM_ADDR (1) WE A3 Output GVDD DRV_MEM_ADDR Signal Name Package Pin Number RCS3 Notes (1)(2) EPIC Control Signals INT Y22 Output OVDD DRV_CPU IRQ_0 / S_INT U24 Input OVDD - IRQ_1 / S_CLK C24 I/O OVDD DRV_PCI IRQ_2 / S_RST T21 I/O OVDD DRV_PCI IRQ_3 / S_FRAME U20 I/O OVDD DRV_PCI IRQ_4/ L_INT V22 I/O OVDD DRV_PCI (16) Two-wire Interface Control Signals SCL AB25 I/O OVDD DRV_CPU (8)(12) SDA AB24 I/O OVDD DRV_CPU (8)(12) Clock Signals CKO V20 Output OVDD DRV_PCI CPUCLK[0-2] AA12, AA13, AB12 Output BVDD DRV_MEM_ADDR OSC_IN U22 Input OVDD - PCI_CLK[0-4] R25, P24, R24, N24, N25 Output OVDD DRV_MEM_ADDR PCI_SYNC_IN P20 Input OVDD - PCI_SYNC_OUT P25 Output OVDD DRV_MEM_ADDR SDRAM_CLK[0-3] D14, D13, E12, E14 Output GVDD DRV_MEM_ADDR SDRAM_SYNC_IN E13 Input GVDD - SDRAM_SYNC_OUT D12 Output GVDD DRV_MEM_ADDR (4) (4) (4) Miscellaneous Signals HRESET AA23 Input OVDD - HRESET_CPU AB21 Output BVDD DRV_CPU (10)(12) MCP AE20 Output OVDD DRV_CPU (12)(16) NMI AC25 Input OVDD - QACK AE18 Output BVDD DRV_CPU QREQ M4 Input BVDD - SRESET Y18 Output BVDD DRV_CPU (10) (10) 7 2137A-HIREL-06/02 Table 1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number Pin Type Supply Voltage Output Driver Type Notes Test/Configuration Signals PLL_CFG[0-3] AC22, AD23, AD22, AE23 Input OVDD - (2)(4) TCK W24 Input OVDD - (7)(10) TDI Y25 Input OVDD - (7)(10) TDO W23 Output OVDD DRV_PCI TEST AA25 Input OVDD - (7)(10) TEST1 V24 Input OVDD - (8) TEST2 D6 Input GVDD - (9) TMS Y24 Input OVDD - (7)(10) TRIG_IN W22 Input OVDD - TRIG_OUT W21 Output OVDD DRV_CPU (10) TRST AA24 Input OVDD - (7)(10)(14) Power and Ground Signals AVDD AE24 Input - - GND AA21, AB22, AC11, AC14, AC17, AC20, AC23, AC3, AC5, AC8, AD24, AE25, C12, C15, C18, C21, C23, C3, C6, C9, E3, F10, F16, F20, F23, F6, G11, G13, G15, G18, G8, H19, H3, H7, J23, K20, K6, L19, L3, L7, M23, N19, N7, P3, R19, R23, R7, T20, T6, U3, V19, V23, V7, W11, W13, W15, W18, W8, Y10, Y16, Y19, Y20, Y3, Y6 Input - - GVDD B2, C5, C8, C11, C14, C17, C20, E5, E9, E11, E15, E17, F3, G7, G9, G12, G14, G17, G19, J3, J5, J7, L5, M3, M7 Input - - LAVDD F7 Input - - LVDD D22, F22, H22, K22, N22, T22 Input - - OVDD B24, E21, E23, H23, J19, J21, L21, L23, M19, P19, P23, R21, U19, U21, U23, Y23 Input - - BVDD P7, R3, R5, U5, U7, V3, W7, W9, W12, W14, W17, AA3, AA5, AA9, AA11, AA15, AA17, AC6, AC9, AC12, AC15, AC18, AC21, AD2 Input - - VDD K19, W16, T19, G10, G16, K7, T7, W10, W19, W20, Y21, AA22, AB23, AC24, AD25 Input - - Manufacturing Pins FTP[2-3] R20, D24 I/O OVDD DRV_PCI (4)(8) MTP[1-2] B12, B13 I/O GVDD DRV_MEM_ADDR (4)(9) 8 PC107A 2137A-HIREL-06/02 PC107A Notes: 1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset. 2. This pin is a reset configuration pin. 3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into configuration bits during reset. 4. Multi-pin signals such as AD[0-31] or DL[0-31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23. 5. SDMA[10-1] are reset configuration pins and have internal pull-up resistors which are enabled only when the MPC107 is in the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s are read into the configuration bits during reset. 6. Recommend a weak pull-up resistor (2 k- 10 k) be placed on this PCI control pin to LVDD. 7. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 6, "DC Electrical Specifications." 8. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to OVDD. 9. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to GVDD. 10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 11. This pin is affected by programmable PCI_HOLD_DEL parameter, see "PCI Signal Output Hold Timing" on page 26." 12. This pin is an open drain signal. 13. This pin is a sustained tri-state pin as defined by the PCI Local Bus Specification. 14. See "Connection Recommendations" on page 39 for additional information on this pin. 15. A weak pull-up resistor is recommend (2 k - 10 k) to be placed on this pin to BVDD. 16. If BVDD = 2.5V 5%, this microprocessor interface pin needs to be DC voltage level shifted from OVDD (3.3V 0.3V) to 2.5V 5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal. 9 2137A-HIREL-06/02 Signal Description Figure 2. PC107A Microprocessor Signal Groups AS CAS/DQM[0-7] 32 8 1 CKE 1 1 FOE 1 1 32 1 MDH[0-31] MDL[0-31] 1 1 CI RCS0 1 1 DBG0 RCS1 1 1 DBG1 1 1 DBGLB RCS2 1 32 RTC 1 32 SDBA0 1 8 SDBA1 1 1 1 1 14 1 SDMA[13-0] SDRAS WE 1 1 1 1 1 INT IRQ_0/S_INT IRQ_1/S_CLK IRQ2_2/S_RST IRQ_3/S_FRAME IRQ_4/L_INT SCL SDA 1 3 1 5 1 1 CPUCLK[0-2] OSC_IN PCI_CLK[0-4] PCI_SYNC_IN PCI_SYNC_OUT SDRAM_CLK[0-3] SDRAM_SYNC_IN QACK QREQ SRESET GND Power and Ground Signals 10 TEA TS TSIZ[0-2] TT[0-4] WT AD[0-31] 1 DEVSEL 1 1 1 5 1 1 3 1 1 1 5 1 1 1 1 6 4 1 FRAME GNT[0-4] IDSEL INTA IRDY PCI Interface Signals LOCK PAR PERR REQ[0-4] SERR STOP TRDY 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 64 1 25 1 LAVdd 1 1 LVdd 6 OVdd 16 GVdd TA TBST C/BE[0-3] 1 AVdd GBL LBCLAIM 4 1 NMI 60x Processor Interface S DL[0-7] 32 1 MCP DL[0-31] 1 SDRAM_SYNC_OUT 1 HRESET DLL[0-31] 1 1 HRESET_CPU BR1 1 1 CKO Miscellaneous Signals BG1 BR0 8 SDcAS Clock Signals BG0 1 RCS3 Two-wire Interface Control Signals AACK ARTRY 8 RAS/CS[0-7] EPIC Control Signals A[0-31] 32 PAR/AR[0-7] Memory Interface Signals 1 BVdd 24 Vdd 15 PLL_CFG[0-3] TCK TDI TDO TEST TEST1 TEST2 Test/Configuration Sig TMS TRIG_IN TRIG_OUT TRST 2 FTP[2-3] 2 MTP[1-2] Manufacturing Pins PC107A 2137A-HIREL-06/02 PC107A Detailed Specification Scope This drawing describes the specific requirements for the PC107A, in compliance with Atmel standard screening. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics. 2. SQ32S0100.0: Quality levels for supplied components. Requirements General The microcircuits are in accordance with the applicable documents and as specified herein. Design and Construction Terminal Connections The terminal connections are shown in Table 1, "PC107A Pinout Listing," on page 5. Absolute Maximum Ratings The tables in this section describe the PC107A DC electrical characteristics. Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings Symbol Characteristic(1) VDD Value Unit Supply Voltage - Core -0.3 to 2.75 V VDD GVDD Supply Voltage - Memory Bus Drivers -0.3 to 3.6 V GVDD BVDD Supply Voltage - Processor Bus Drivers -0.3 to 3.6 V BVDD OVDD Supply Voltage - PCI and Standard I/O Buffers -0.3 to 3.6 V OVDD AVDD/LAVDD Supply Voltage - PLLs and DLL -0.3 to 2.75 V AVDD/LAVDD LVDD Supply Voltage - PCI Reference -0.3 to 5.4 V LVDD VIN Input Voltage(2) -0.3 to 3.6 V VIN TJ Operational Die-Junction Temperature Range -55 to 125 C TJ TSTG Storage Temperature Range -55 to 150 C TSTG Notes: Symbol 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. PCI inputs with LVDD = 5V 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5 V DC. 11 2137A-HIREL-06/02 Recommended Operating Conditions Table 3 provides the recommended operating conditions for the PC107A. Table 3. Recommended Operating Conditions Symbol Characteristic Recommended Value Unit Notes VDD Supply Voltage 2.5 5% V (4) GVDD Supply Voltages for Memory Bus Drivers 3.3 5% V (6) BVDD Supply Voltages for Processor Bus Drivers 3.3 5% V (6) 2.5 5% OVDD I/O Buffer supply for PCI and Standard 3.3 0.3 V (4) AVDD PLL Supply Voltage 2.5 5% V (5) LAVDD DLL Supply Voltage 2.5 5% V (5) LVDD PCI Reference 5.0 5% V (7)(8) 3.3 0.3 V (7)(8) 0 to 3.6 or 5.75 V (1)(2) 0 to 3.6 V (3) -55C to 125C C VIN Input Voltage PCI Inputs All Other Inputs TJ Notes: 12 Die-Junction Temperature 1. PCI pins are designed to withstand LVDD + 0.5V dc when LVDD is connected to a 5.0V DC power supply. 2. PCI pins are designed to withstand LVDD + 0.5V dc when LVDD is connected to a 3.3V DC power supply. 3. Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/LAVDD) by more than 2.5V at all times including during power-on reset. 4. OVDD must not exceed VDD/AVDD/LAVDD by more than 1.8V at any time including during power-on reset. 5. VDD/AVDD/LAVDD must not exceed OVDD by more than 0.6V at any time including during power-on reset. 6. BVDD/GVDD must not exceed VDD/AVDD/LAVDD by more than 1.8V at any time including during power-on reset. 7. LVDD must not exceed VDD/AVDD/LAVDD by more than 5.4V at any time including during power-on reset. 8. LVDD must not exceed OVDD by more than 3.6V at any time including during power-on reset. PC107A 2137A-HIREL-06/02 PC107A Figure 3 shows the supply voltage sequencing and separation cautions. DC Power Supply Voltage Figure 3. Supply Voltage Sequencing and Separation Cautions LVDD at 5V 5V 8 9 9 3.3V OVDD/BVDD/GVDD(LVDD at 3.3V ----) 8 2.5V See Note 1 below. 6 5.7 VDD/AVDD/LAVDD Vdd Stable 100 s PLL Relock Time (3) 0 Voltage Regulator Delay (2) Power Supply Ramp Up (2) Time HRESET asserted 255 external memory Clock cycles (3) Reset Configuration Pins 9 external memory clock cycles setup time (4) VM = 1.4 V HRESET Maximum rise time must be less than one external memory clock cycle (5) 6 VM = 1.4 V HRESET_CPU Notes: 1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, "Recommended Operating Conditions," on page 12. 2. Refer to "Power Supply Voltage Sequencing" on page 38 for additional information. 3. Refer to Table 9 on page 23 for additional information on PLL Relock and reset signal assertion timing requirements. 4. Refer to Table 10 on page 23 for additional information on reset configuration pin setup timing requirements. 5. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the non-reset state. 6. HRESET_CPU negates 217 memory clock cycles after HRESET negates. 13 2137A-HIREL-06/02 Figure 4 shows the undershoot and overshoot voltage of the memory interface of the PC107A. Figure 4. Overshoot/Undershoot Voltage 4V VIH VIL GVdd +5% GVdd Gnd Gnd - 0.3V Gnd - 1.0V Not to exceed 10% of tSDRAM_CLK Thermal Information Package Characteristics Table 4 provides the package thermal characteristics for the PC107A. Table 4. PBGA Package Thermal Characteristics Symbol Characteristic(1) Value Unit JC Die Junction-to-Case Thermal Resistance < 0.1 C/W JB Die Junction-to-Board Thermal Resistance 5.2 C/W JA Notes: 14 Package Junction-to-Ambient Thermal Resistance (2) See Figure 5 1. Refer to "System Design Information" on page 38 for more details about thermal management. 2. TJ = TA + PD x JA TJ = Die junction temperature. TA = System air ambient temperature near the package. PD = Average power consumed by IC in Watts. JA = Thermal resistance from die junction to ambient air in C/W PC107A 2137A-HIREL-06/02 PC107A Thermal Management Information This section provides thermal management information for the plastic ball grid array (PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design -- the heat sink, airflow and thermal interface material. Figure 5 depicts the die junction-to-ambient thermal resistance for two typical cases: 1. A heat sink is not attached to the PBGA package and there exists high boardlevel thermal loading of adjacent components. See "Typical Upper Limit" curve in Figure 5. 2. A heat sink is not attached to the PBGA package and there exists low boardlevel thermal loading of adjacent components. See "Typical Lower Limit" curve in Figure 5. Figure 5 shows the die junction-to-ambient resistance. Figure 5. Die Junction-to-Ambient Thermal Resistance Die Junction- to- Ambient Thermal Resistance (C/ W) 50 45 Typical Upper Limit Typical LowerLimit 40 35 30 25 20 15 0 0.5 1 1.5 2 2.5 Airflow Velocity (m/s) 15 2137A-HIREL-06/02 Internal Package Conduction Resistance For the PBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows: * The die junction-to-case thermal resistance, * The die junction-to-ball thermal resistance. Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 6. C4 Package with Heat Sink Mounted to a Printed-Circuit Board External Re sistance Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Internal Resistance Printed-Circuit Board External Resistance Note: Radiation Convection The internal versus external package resistance For this PBGA package, heat is dissipated from the component via several concurrent paths. Heat is conducted through the silicon and may be removed to the ambient air by convection and/or radiation. In addition, a second, parallel heat flow path exists by conduction in parallel through the C4 bumps and the epoxy under-fill, to the plastic substrate for further convection cooling off the edges. Then from the plastic substrate, heat is conducted via the leads/balls to the next-level interconnect (printed-circuit board) whereupon the primary mode of heat transfer is by convection and/or radiation. 16 PC107A 2137A-HIREL-06/02 PC107A Power Consideration Power Dissipation Table 5 provides the preliminary power consumption estimates for the PC107A. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V 5% and LVDD = 3.3V 5% Table 5. Power Consumption PCI_SYNC_IN/Core Frequency (MHz) 25/50 33/33 33/66 66/100 Mode VDD Pwr I/O Pwr VDD Pwr I/O Pwr VDD Pwr I/O Pwr VDD Pwr I/O Pwr Unit Maximum 477 1341 334 1105 636 1655 954 1635 mW Typical 400 1125 300 925 550 1325 800 1375 mW (1)(2) Doze 375 850 250 775 500 975 750 1125 mW (1)(2) Nap 375 875 250 825 500 1025 750 1150 mW (1)(2) Sleep 175 875 125 825 225 1025 325 1150 mW (1)(2) Sleep 125 725 100 650 175 875 275 1025 mW (1)(2)(3) Sleep 125 575 100 500 175 650 250 675 mW (1)(3)(4) Sleep 10 400 10 425 10 425 25 500 mW (1)(3)(4)(5) Reset 550 850 350 675 700 975 1050 950 mW (1)(2) Notes: 1. 2. 3. 4. 5. Notes Power is measured with VDD = 2.625V, GVDD = OVDD = BVDD = 3.45V at 0C and one DIMM populated in test system. All clock drivers enabled. Memory refresh off. One PCI_CLK, one CPU_CLK, and one SDRAM_CLK enabled. PLL off. 17 2137A-HIREL-06/02 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PC107A. Static Characteristics DC Electrical Specification Table 6 provides the DC electrical characteristics for the PC107A. At recommended operating conditions (see Table 3 on page 12) Table 6. DC Electrical Specifications Value Characteristics Conditions Input High Voltage(2) Input Low Voltage (1) Symbol Min Max Unit PCI only VIH 0.65*OVDD(3) LVDD V PCI only VIL - 0.3*OVDD V Input High Voltage (2) All other pins (GVDD = 3.3V) VIH 2.0 - V Input High Voltage (2) All other pins (BVDD = 2.5V) VIH 1.7 - V All inputs except PCI_SYNC_IN VIL GND 0.8 V PCI_SYNC_IN Input High Voltage CVIH 2.4 - V PCI_SYNC_IN Input Low Voltage CVIL GND 0.4 V IL - 70 A IL - 10 A Input Low Voltage Input Leakage Current for pins using DRV_PCI driver(4) 0.5V VIN 2.7V at LVDD = 4.75 Input Leakage Current all others(4) LVDD = 3.6V (GVDD 3.465) Output High Voltage (5) (GVDD = 3.3V) VOH 2.4 - V (5) IOH = Driver Dependent Output Low Voltage IOL = Driver Dependent (GVDD = 3.3V) VOL - 0.4 V Output High Voltage IOH = Driver Dependent(5) (BVDD = 2.5V) All outputs except CPUCLKS[0-2] VOH 1.85 - V IOH = Driver Dependent(5) (BVDD = 2.5V) CPUCLKS[0-2] Only VOH 2.0 - V Notes: 18 1. These specifications are for the default driver strengths indicated in Table 7 on page 19. 2. See Figure 20 on page 32 for pins with internal pull-up resistors. 3. The minimum Input high voltage is not compliant with the PCI Local Bus Specification (Rev 2.1) which specifies 0.5*OVDD for minimum input high voltage. 4. Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is measured for nominal OVDD/LVDD and VDD or both OvDD/LVDD and VDD must vary in the same direction. 5. See Table 7 on page 19 for the typical drive capability of a specific signal pin based upon the type of output driver associated with that pin as listed in Table 1 on page 5. 6. Capacitance is periodically sampled rather than 100% tested. PC107A 2137A-HIREL-06/02 PC107A Output Driver Characteristics Table 7 provides information on the characteristics of the output drivers referenced in Table 1 on page 5. The values are from the PC107A IBIS model (v1.1) and are not tested, for additional detailed information see the complete IBIS model listing at http://www.motorola.com/semiconductor. Table 7. Drive Capability of PC107A Output Pins Driver Type Programmable Output Impedance (Ohms) Supply Voltage IOH IOL Unit Notes DRV_CPU 20 BVDD = 3.3V 36.6 18.1 mA (2)(5) BVDD = 2.5V 21.4 15.6 mA (3)(6)(7) BVDD = 3.3V 18.6 9.2 mA (2)(5) BVDD = 2.5V 10.8 7.9 mA (3)(6)(7) 25 OVDD = 3.3V 12.0 12.4 mA (1)(4) 50 (default) OVDD = 3.3V 6.1 6.3 mA (1)(4) 8 (default) GVDD = 3.3V 89.0 42.3 mA (2)(5) 13.3 GVDD = 3.3V 55.8 26.4 mA (2)(5) 20 GVDD = 3.3V 36.6 18.1 mA (2)(5) 40 GVDD = 3.3V 18.6 9.2 mA (2)(5) 20 (default) GVDD = 3.3V 36.6 18.1 mA (2)(5) 40 (default) DRV_PCI DRV_MEM_ADDR DRV_PCI_CLK DRV_MEM_DATA Notes: 1. 2. 3. 4. 5. 6. 7. (2)(5) 40 GVDD = 3.3V 18.6 9.2 mA For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the 0.3V and 0.4V table entries' current values which corresponds to the PCI VOH = 2.97 = 0.9*OVDD (OVDD = 3.3V) where Table Entry Voltage = OVDD - PCI VOH. For all others with GVDD or BVDD = 3.3V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.9V table entry which corresponds to the VOH = 2.4V where Table Entry Voltage = G/BVDD - VOH. For all others with BVDD = 2.5V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.65V table entry by interpolating between the 0.6V and 0.7V table entries' current values which corresponds to the VOH = 1.85V where Table Entry Voltage = BVDD - VOH. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33V = PCI VOL = 0.1*OVDD (OVDD = 3.3V) by interpolating between the 0.3V and 0.4V table entries. For all others with GVDD or BVDD = 3.3V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table entry. For all others with BVDD = 2.5V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table entry. For BVDD = 2.5V, the IOH and IOL values are estimated from the io_mem_data_XX_2.5 and io_mem_addr_XX_2.5 sections of the IBIS model where XX = driver output impedance (20 or 40). Dynamic Electrical Characteristics Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Section. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V 5% and LVDD = 3.3V 0.3V 19 2137A-HIREL-06/02 Table 8. Clock AC Timing Specifications Characteristics and Conditions (1) Min Max Unit Notes 1a Frequency of Operation (PCI_SYNC_IN) 12.5 66 MHz (8) 1b PCI_SYNC_IN Cycle Time 80 15 ns (8) 2, 3 PCI_SYNC_IN Rise and Fall Times - 2.0 ns (2) 4 PCI_SYNC_IN Duty Cycle Measured at 1.4V 40 60 % 5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 6 9 ns (3) 5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V 6 9 ns (3) 7 PCI_SYNC_IN Jitter - < 150 ps 9a PCI_CLK[0-4] Skew (Pin to Pin) - 500 ps 9b SDRAM_CLK[0-3] Skew (Pin to Pin) - 350 ps 9c CPU_CLK[0-2] Skew (Pin to Pin) - 350 ps 9d SDRAM_CLK[0-3]/CPU_CLK[0-2] Jitter - 150 ps 10 Internal PLL Relock Time - 100 s (3)(4)(6) 15 DLL Lock Range with DLL_EXTEND = 0 disabled 0 (NTclk - tloop - tfix0) 7 ns (7) 16 DLL Lock Range with DLL_EXTEND = 1 enabled (default) 0 (NTclk - Tclk/2 - tloop - tfix0) 7 ns (7) 17 Frequency of Operation (OSC_IN) 18 Num 12.5 66 MHz (8) OSC_IN Cycle Time 80 15 ns (8) 19 OSC_IN Rise and Fall Times - 5 ns (5) 20 OSC_IN Duty Cycle Measured at 1.4V 40 60 % 21 OSC_IN Frequency Stability - 100 ppm Notes: 20 1. 2. 3. 4. 5. These specifications are for the default driver strengths indicated in Table 7 on page 19. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4V to 2.4V. Specification value at maximum frequency of operation. Relock time is guaranteed by design and characterization. Relock time is not tested. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not tested. 6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence. 7. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). Tclk is the period of one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. tfix0 is a fixed delay inherent in the design when the DLL is at tap point 0 and the DLL is contributing no delay; tfix0 equals approximately 3 ns. See Figure 9 on page 22 for DLL locking ranges. 8. See Table 19 on page 37 for PCI_SYNC_IN input frequency range for specific PLL_CFG[0-3] settings. PC107A 2137A-HIREL-06/02 PC107A Figure 7 shows the PCI_SYNC_IN Input Clock Timing Diagram, Figure 8 illustrates how Table 8 clock specifications relate to the PC107A Clocking diagram, and Figure 9 shows the DLL Locking Range Loop Delay vs. Frequency of Operation. Figure 7. PCI_SYNC-IN Input Clock Timing Diagram 1 5a 5b 2 3 CVIH PCI_SYNC_IN VM VM VM CVIL VM = Midpoint Voltage (1.4V) Figure 8. Clock Subsystem Block Diagram MPC107 CPU_CLK[0:2] Specs. 15,16 DLL Spec. 10 PLL Specs. 9c,9d SDRAM_CLK[0:3] Specs. 9b,9d SDRAM_SYNC_OUT SDRAM_SYNC_IN sys_logic_clk PCI_SYNC_IN Specs. 1 - 7 PCI_SYNC_OUT OSC_IN Specs. 17 23 Note: Spec. 9a Core Logic PCI_CLK[0:4] Specification numbers are from Table 8. 21 2137A-HIREL-06/02 Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation DLL will lock Tclk SDRAM_ SYNC_ OUT Period and Frequency DLL not guaranteed to lock 25 MHz 40 ns N=1 DLL_EXTEND = 1 33 MHz 30 ns N=1 DLL_EXTEND = 0 50 MHz 20 ns N=2 DLL_EXTEND = 1 N=2 DLL_EXTEND = 0 100 MHz 10 ns 0 ns 5 ns 10 ns 15 ns Tloop Propagation Delay Time in Nanoseconds 22 PC107A 2137A-HIREL-06/02 PC107A Operating Frequency This section provides the AC electrical characteristics for the PC107A. After fabrication, functional parts are sorted by maximum core frequency as shown in Figure 9 and "Clock AC Specifications" on page 19 and tested for conformance to the AC specifications for that frequency. The core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency; see "Ordering Information" on page 42. Table 9 provides the operating frequency information for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 0.3V. Table 9. Operating Frequency 66 MHz Characteristic(1) Core (memory bus/processor bus) Frequency Min Max Min Max Unit 25 66 25 100 MHz PCI Input Frequency (PCI_SYNC_IN) Note: Input AC Timing Specifications 100 MHz 12.5 - 66 MHz 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0-3] settings must be chosen such that the resulting peripheral logic/memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in "Clock Relationships Choice" on page 37 for valid PLL_CFG[0-3] settings and PCI_SYNC_IN frequencies. Table 10 provides the input AC timing specifications. See Figure 10 on page 24 and Figure 11 on page 24. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V 5% and LVDD = 3.3V 0.3V Table 10. Input AC Timing Specifications Num Characteristics Min Max Unit Notes 10a PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) 3.0 - ns (2)(3) 10b Memory Interface Signals Valid to SDRAM_SYNC_IN (Input Setup) 2.0 - ns (1)(3) 10c Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 2.0 - ns (1)(3) 10d Two-wire interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 2.0 - ns (1)(3) 10e Mode select Inputs Valid to HRESET (Input Setup) 9*tCLK - ns (1)(3)(5) 10f 60x Processor Interface Signals Valid to SDRAM_SYNC_IN (Input Setup) 2.0 - ns (1)(3) PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold) 1.0 - ns (2)(3) 11a1 23 2137A-HIREL-06/02 Table 10. Input AC Timing Specifications (Continued) Num Characteristics Min Max Unit Notes 11a2 Memory Interface Signals SDRAM_SYNC_IN to Inputs Invalid (Input Hold) 0.5 - ns (1)(3) 11a3 60x Processor Interface Signals SDRAM_SYNC_IN to Inputs Invalid (Input Hold) 0 - ns (1)(3) 11b HRESET to Mode select Inputs Invalid (Input Hold) 0 - ns (1)(3)(5) Notes: 1. All memory, processor and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 10. 2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4*OVDD of the signal in question for 3.3V PCI signaling levels. See Figure 11. 3. Input timings are measured at the pin. 4. tCLK is the time of one SDRAM_SYNC_IN clock cycle. 5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the HRESET signal. See Figure 12 on page 25. Figure 10. Input - Output Timing Diagram Referenced to SDRAM_SYNC_IN PCI_SYNC_IN SDRAM_SYNC_IN shown in 2:1 mode VM VM VM 10b-d 12b-d 11a 2.0V 2.0V 0.8V 0.8V 13b 14b MEMORY INPUTS/OUTPUTS Output Timing Input Timing VM = Midpoint Voltage (1.4V) Figure 11. Input - Output Timing Diagram Referenced to PCI_SYNC_IN OVdd/2 OVdd/2 PCI_SYNC_IN OVdd/2 10a 11a PCI INPUTS/OUTPUTS 13a 14a 0.615*OVdd 0.4*OVdd Input Timing 24 12a 0.285*OVdd Output Timing PC107A 2137A-HIREL-06/02 PC107A Figure 12. Input Timing Diagram for Mode Select Signals VM HRESET 10e 11b 2.0 V MODE PINS 0.8 V VM = Midpoint Voltage (1.4V) Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the PC107A. See Figure 10 on page 24 and Figure 11 on page 24. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 0.3V Table 11. Output AC Timing Specifications Num Characteristics(3)(6) 12a Min Max Unit Notes PCI_SYNC_IN to Output Valid, 66 MHz PCI, with SDMA4 pulleddown to logic 0 state. See Figure 14. - 6.0 ns (2)(4) PCI_SYNC_IN to Output Valid, 33 MHz PCI, with SDMA4 in the default logic 1 state. See Figure 14. - 11.0 ns (2)(4) 12b Memory Interface Signals, SDRAM_SYNC_IN to Output Valid - 5.5 ns (1) 12b1 Memory Interface Signal: CKE (100 MHz Device), SDRAM_SYNC_IN to Output Valid - 5.5 ns (1) 12b2 Memory Interface Signal: CKE (66 MHz Device), SDRAM_SYNC_IN to Output Valid - 6.0 ns (1) 12c Epic, Misc. Debug Signals, SDRAM_SYNC_IN to Output Valid - 9.0 ns (1) 12d Two-wire interface, SDRAM_SYNC_IN to Output Valid - 5.0 ns (1) 12e 60x Processor Interface Signals, SDRAM_SYNC_IN to Output Valid - 5.5 ns (1) 13a Output Hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled-down to logic 0 states. See Table 12. 1.0 - ns (2)(4)(5) Output Hold, 33 MHz PCI, with SDMA4 in the default logic 1 state and SDMA3 pulled-down to logic 0 state. See Table 12. 2.0 - ns (2)(4)(5) ns (1) 13b Output Hold (For All Others) 1 14a PCI_SYNC_IN to Output High Impedance (Toff for PCI) - 14.0 ns (2)(4) 14b SDRAM_SYNC_IN to Output High Impedance (For All Others) - 4.0 ns (1) Notes: 1. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 24. 2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285*OVDD or 0.615*OVDD of the signal in question for 3.3V PCI signaling levels. See Figure 11 on page 24. 3. All output timings assume a purely resistive 50 load (See Figure 13 on page 26). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 25 2137A-HIREL-06/02 4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0-3], PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD[0-31], REQ[4-0], GNT[4-0], IDSEL, INTA. 5. PCI hold times can be varied, see "PCI Signal Output Hold Timing" on page 26 for information on programmable PCI output hold times. The values shown for item 13a are for PCI compliance. 6. These specifications are for the default driver strengths indicated in Table 7 on page 19. Figure 13. AC Test Load for the PC107A Output measurements are made at the device pin. OUTPUT PIN OVdd/2 Z0 = 50 RL = 50 PCI Signal Output Hold Timing In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the PC107A has a programmable output hold delay for PCI signals. The initial value of the output hold delay is determined by the values on the SDMA4 and SDMA3 reset configuration signals. Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register. Table 12 describes the bit values for the PCI_HOLD_DEL values in PMCR2. Table 12. Power Management Configuration Register 2-0x72 Bit Name Reset value Description 6-4 PCI_HOLD_DEL xx0 PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5 are determined by the reset configuration pins SDMA4 and SDMA3, respectively. As these two pins have internal pull-up resistors, the default value after reset is 0b110. While the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or decrementing the value in these bit fields of this register via software or hardware configuration. The increment is in approximately 400 picosecond steps. Lowering the value in the three bit field decreases the amount of output hold available. 000 66 MHz PCI. Pull-down SDMA4 configuration pin with a 2 k or less value resistor. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 11 are met for a 66 MHz PCI system. See Figure 14 on page 27. 001 010 011 100 33 MHz PCI. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 11 are met for a 33 MHz PCI system. See Figure 14 on page 27. 101 110 (Default if reset configuration pins left unconnected) 111 26 PC107A 2137A-HIREL-06/02 PC107A Figure 14. PCI_HOLD_DEL Effect on Output Valid and Hold Time PCI_SYNC_IN 12a, 8 ns for 33 MHz PCI PCI_HOLD_DEL = 100 OVdd/2 OVdd/2 13a, 2 ns for 33 MHz PCI PCI_HOLD_DEL = 100 PCI INPUTS/OUTPUTS 33 MHz PCI 12a, 6 ns for 66 MHz PCI PCI_HOLD_DEL = 000 13a, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 000 PCI INPUTS/OUTPUTS 66 MHz PCI As PCI_HOLD_DEL values decrease PCI INPUTS and OUTPUTS As PCI_HOLD_DEL values increase Diagram Not to Scale OUTPUT VALID OUTPUT HOLD 27 2137A-HIREL-06/02 Two-wire Interface AC Timing Specifications Table 13 provides the two-wire interface input AC timing specifications for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 0.3V Table 13. Two-wire Interface Input AC Timing Specifications Num Characteristics Min Max Unit Notes 1 Start condition hold time 4.0 - CLKs (1)(2) 2 Clock low period (The time before the PC107A will drive SCL low as a transmitting slave after detecting SCL low as driven by an external master) 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) - CLKs (1)(2)(4)(5) 3 SCL/SDA rise time (from 0.5V to 2.4V) - 1 ms 4 Data hold time 0 - ns 5 SCL/SDA fall time (from 2.4V to 0.5V) - 1 mS 6 Clock high period (Time needed to either receive a data bit or generate a START or STOP) 5.0 - CLKs (1)(2)(5) 7 Data setup time 3.0 - ns (3) 8 Start condition setup time (for repeated start condition only) 4.0 - CLKs (1)(2) 9 Stop condition setup time 4.0 - CLKs (1)(2) Notes: 28 (2) 1. Units for these specifications are in SDRAM_CLK/CPU_CLK units. 2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider Register two-wire interface FDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 16 on page 31. 3. Timing is relative to the Sampling Clock (not SCL). 4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. 5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine the maximum two-wire interface input frequency. See Figure 16 on page 31. PC107A 2137A-HIREL-06/02 PC107A Table 14 provides the two-wire interface Frequency Divider Register (I2CFDR) information for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 5% Table 14. PC8240 Maximum Two-wire Interface Input Frequency Max Two-wire Interface Input Frequency(1) FDR Hex(2) Divider (Dec)(2) SDRAM_CLK/ CPU_CLK at 25 MHz 20, 21 160, 192 862 1.13 MHz 1.72 MHz 3.44 MHz 22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 MHz 2.22 MHz 0, 1 288, 320 409 540 819 1.63 MHz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 324 428 649 1.29 MHz 4, 5 576, 640 229 302 458 917 6, 7, 2A, 2B, 2C, 2D 768, 896, 960, 1024, 1280, 1536 177 234 354 709 8, 9 1152, 1280 121 160 243 487 A, B, 2E, 2F, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 92 122 185 371 C, D 2304, 2560 62 83 125 251 E, F, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 47 62 95 190 10, 11 4608, 5120 32 42 64 128 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 24 31 48 96 14, 15 9216, 10240 16 21 32 64 16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384, 20480, 24576 12 16 24 48 18, 19 18432, 20480 8 10 16 32 1A, 1B, 3E, 3F 24576, 28672, 30720, 32768 6 8 12 24 1C, 1D 36864, 40960 4 5 8 16 1E, 1F 49152, 61440 3 4 6 12 Notes: SDRAM_CLK/ CPU_CLK at 33 MHz SDRAM_CLK/ CPU_CLK at 50 MHz SDRAM_CLK/ CPU_CLK at 100 MHz 1. Values are in kHz unless otherwise specified. 2. FDR Hex and Divider (Dec) values are listed in corresponding order. 3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique output frequency as shown in Table 15 on page 30. 29 2137A-HIREL-06/02 Table 15 provides the two-wire interface output AC timing specifications for the PC107A. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V 5% and LVDD = 3.3V 0.3V Table 15. Two-wire Interface Output AC Timing Specifications Num Characteristics Min Max Unit Notes (FDR[5] == 0) x (DFDR/16) / 2N + (FDR[5] == 1) x (DFDR/16) / 2M - CLKs (1)(2)(5) DFDR / 2 - CLKs (1)(2)(5) - - mS (3) 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) - CLKs (1)(2)(5) - <5 ns (4) DFDR / 2 - CLKs (1)(2)(5) 1 Start condition hold time 2 Clock low period 3 SCL/SDA rise time (from 0.5V to 2.4V) 4 Data hold time 5 SCL/SDA fall time (from 2.4V to 0.5V) 6 Clock high time 7 Data setup time (PC107A as a master only) (DFDR / 2) - (Output data hold time) - CLKs (1)(5) 8 Start condition setup time (for repeated start condition only) DFDR + (Output start condition hold time) - CLKs (1)(2)(5) 9 Stop condition setup time 4.0 - CLKs (1)(2) Notes: 1. Units for these specifications are in SDRAM_CLK/CPU_CLK units. 2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 16 on page 31. 3. Since SCL and SDA are open-drain type outputs, which the PC107A can only drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 4. Specified at a nominal 50 pF load. 5. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to the two-wire Interface chapter's Serial Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 9. Figure 15. Two-wire Interface Timing Diagram I 2 SCL VM VM 6 1 4 SDA 30 PC107A 2137A-HIREL-06/02 PC107A Figure 16. Two-wire Interface Timing Diagram II 5 SCL 3 VH VM VL 8 9 SDA Figure 17. Two-wire Interface Timing Diagram III DFFSR FILTER CLK (1) 7 SDA Note: INPUT DATA VALID DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value. Figure 18. Two-wire Interface Timing Diagram IV (Qualified signal) SCL/SDArealtime VM Delay (1) SCL/SDAqualified Note: VM The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock. 31 2137A-HIREL-06/02 EPIC Serial Interrupt Mode AC Timing Specifications Table 16 provides the EPIC serial interrupt mode AC timing specifications for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 0.3V Table 16. EPIC Serial Interrupt Mode AC Timing Specifications Num Characteristics Min Max Unit Notes (1) 1 S_CLK Frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz 2 S_CLK Duty Cycle 40 60 % 3 S_CLK Output Valid Time - 6 nS 4 Output Hold Time 0 - nS 5 S_FRAME, S_RST Output Valid Time - 1 sys_logic_clk period + 6 nS (2) 6 S_INT Input Setup Time to S_CLK 1 sys_logic_clk period + 2 - nS (2) 7 S_INT Inputs Invalid (Hold Time) to S_CLK - 0 nS (2) Notes: 1. See the PC107A User's Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency programming. 2. S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the PC107A User's Manual for a complete description of the functional relationships between these signals. 3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See the PC107A User's Manual for a complete clocking description. Figure 19. EPIC Serial Interrupt Mode Output Timing Diagram sys_logic_clk3 VM VM VM 3 S_CLK 4 VM VM 5 4 S_FRAME VM VM S_RST Figure 20. EPIC Serial Interrupt Mode Input Timing Diagram VM S_CLK 7 6 S_INT 32 PC107A 2137A-HIREL-06/02 PC107A IEEE 1149.1 (JTAG) AC Timing Specifications Table 17 provides the JTAG AC timing specifications for the PC107A while in the JTAG operating mode. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V 0.3V Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN) Characteristics(4) Num Min Max Unit TCK Frequency of Operation 0 25 MHz 1 TCK Cycle Time 40 - ns 2 TCK Clock Pulse Width Measured at 1.5V 20 - ns 3 TCK Rise and Fall Times 0 3 ns 4 TRST_ Setup Time to TCK Falling Edge 10 - ns 5 TRST_ Assert Time 10 - ns 6 Boundary Scan Input Data Setup Time 5 - ns (2) 7 Boundary Scan Input Data Hold Time 15 - ns (2) 8 TCK to Output Data Valid 0 30 ns (3) 9 TCK to Output High Impedance 0 30 ns (3) 10 TMS, TDI Data Setup Time 5 - ns 11 TMS, TDI Data Hold Time 15 - ns 12 TCK to TDO Data Valid 0 15 ns 13 TCK to TDO High Impedance 0 15 ns Notes: 1. 2. 3. 4. Notes (1) TRST is an asynchronous signal. The setup time is for test purposes only. Non-test (other than TDI and TMS) signal input timing with respect to TCK. Non-test (other than TDO) signal output timing with respect to TCK. Timings are independent of the system clock (PCI_SYNC_IN). Figure 21. JTAG Clock Input Timing Diagram 1 2 2 VM TCK 3 3 VM VM VM = Midpoint Voltage Figure 22. JTAG TRST Timing Diagram TCK 4 TRST 5 33 2137A-HIREL-06/02 Figure 23. JTAG Boundary Scan Timing Diagram TCK 6 DATA INPUTS 7 INPUT DATA VALID 8 DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS Figure 24. Test Access Port Timing Diagram TCK 10 TDI, TMS 11 INPUT DATA VALID 12 TDO OUTPUT DATA VALID 13 TDO 34 PC107A 2137A-HIREL-06/02 PC107A Preparation for Delivery Packaging Microcircuits are prepared for delivery in accordance with internal standards. Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with internal specifications and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: * Devices should be handled on benches with conductive and grounded surfaces. * Ground test equipment, tools and operator. * Do not handle devices by the leads. * Store devices in conductive foam or carriers. * Avoid use of plastic, rubber or silk in MOS areas. * Maintain relative humidity above 50% if practical. Package Mechanical Data Package Parameters The PC107A uses a 33 mm x 33 mm, 503 pin Plastic Ball Grid Array (PBGA) package. The plastic package parameters are as provided in the following list. Table 18. Package Parameters Parameter Package Outline 33 mm x 33 mm Interconnects 503 Pitch 1.27 mm Solder Attach 62 Sn/36 Pb/2 Ag Solder Balls 62 Sn/36 Pb/2 Ag Solder Balls Diameter 0.60 mm - 0.90 mm Maximum Module Height 2.75 mm Co-planarity Specification 0.20 mm Maximum Force 6.0 lbs. total, uniformly distributed over package (5.4 grams/ball) 35 2137A-HIREL-06/02 Mechanical Dimensions Figure 25 shows the top surface, side profile, and pinout of the PC107A, 503 PBGA package. Figure 25. PC107A Package Dimensions and Pinout Assignments 2X D A1 CORNER C 0.2 A 0.2 C D4 // 0.25 A Capacitor places // 0.35 A E2 E4 E Millimeters DIM M A 2X D3 2X A1 A2 0.2 0.70 1.20 0.80 0.82 0.90 0.60 0.90 33 GSC D1 30.48 BSC D2 D3 3.43 AC D4 e 5.00 1.27 BSC AA E 33 GSC W E1 30.48 BSC U E2 E3 3.43 E4 9.00 Top View A3 2X E3 A2 A4 D1 24Xe C V 0.50 1.00 A4 b C B AB Max 2.75 A3 D2 AD Min 24Xe A1 A Side View AE T R P N M L K J H G F E D C B A 12.50 14.50 E1 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 0.3 503 x b A B C 0.15 A Bottom View Notes: 1. 2. 3. 4. Dimensioning and tolerancing per A. Dimensions in millimeters. Dimension b is the maximum solder ball diameter measured parallel to datum A. D2 and E2 define the area occupied on the die and underfill actual size of this area may be smaller than shown. D3 and E3 are the minimum clearance from the package edge to the chip capacitors. 5. Capacitors may not be present on all devices. 6. Caution must be taken not to short expose metal capacitor pads on package top. 36 PC107A 2137A-HIREL-06/02 PC107A Clock Relationships Choice The PC107A's internal PLL is configured by the PLL_CFG[0-3] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set the Core/Memory/Processor PLL (VCO) frequency of operation for the PCI-toCore/Memory/Processor frequency multiplying, if any. All valid PLL configurations for the PC107A are shown in Table 19. Table 19. PC107A Microprocessor PLL Configuration 66 MHz Part Ref PLL_CFG [0-3](2) 1 0001 2 0010 3 0011 5 0101 PCI_SYNC_IN Range (MHz) 25 (5) - 50 100 MHz Part Core/Mem/CPU Range (MHz) (4) 12.5(5) - 25(4) 25 - 50 25 - 5 PCI_SYNC_IN Range (MHz) 25 (5) 25 (5) - 33 PCI: Core Ratio VCO Multiplier 25 - 50 1 4 25 - 5 2 4 Bypass Bypass (4) - 50 12.5(5) - 25(4) Bypass (5) Core/Mem/CPU Range (MHz) Bypass 50 - 66 25 (5) - 50 50 - 100 2 2 (5) 8 1000 16 - 22 50 - 66 16 - 33 50 - 100 3 2 9 1001 33(5) - 44 50 - 66 33(5) - 66 50 - 100 1.5 2 C 1100 20(5) - 26 50 - 66 20(5) - 40 50 - 100 2.5 2 50 - 66 1 2 Not Usable Off Off D F Notes: 1101 1111 50 (5) - 66 Clock off (3) 50 - 66 Not Usable 50 (5) - 66 Clock off (3) 1. PLL_CFG[0-3] settings not listed (00000100, 0110, 0111, 1010, 1011, and 1110) are reserved. 2. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal core directly, the PLL is disabled, and the PCI: core mode is set for 1:1 mode operation. The AC timing specifications given in this document do not apply in PLL Bypass mode. 3. In Clock Off mode, no clocking occurs inside the PC107A regardless of the PCI_SYNC_IN input. 4. Limited due to maximum memory VCO = 200 MHz. 5. Limited due to minimum VCO = 100 MHz. 6. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 37 2137A-HIREL-06/02 System Design Information PLL Power Supply Filtering The AVDD and LAVDD power signals are provided on the PC107A to provide power to the peripheral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal clocks, the power supplied to the AVDD and LAVDD input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. A separate circuit similar to the one shown in Figure 26 using surface mount capacitors with minimum effective series inductance (ESL) is recommended for each of the AVDD and LAVDD power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. The circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important but proportionately less critical for the LAVDD pin. Figure 26. PLL Power Supply Filter Circuit 10 Vdd AVdd or LAVdd 2.2 F 2.2 F Low ESL surface mount capacitors GND Power Supply Voltage Sequencing The notes in Table 3 on page 12 contain cautions illustrated in Figure 3 on page 13 about the sequencing of the external bus voltages and internal voltages of the PC107A. These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward biased and excessive current can flow through these diodes. Figure 3 shows a typical ramping voltage sequence where the DC power sources (voltage regulators and/or power supplies) are connected as shown in Figure 27. The voltage regulator delay shown in Figure 3 can be zero if the various DC voltage levels are all applied to the target board at the same time. The ramping voltage sequence shows a scenario in which the VDD/AVDD/LAVDD power plane is not loaded as much as the OVDD/GVDD power plane and thus VDD/AVDD/LAVDD ramps at a faster rate than OVDD/GVDD. If the system power supply design does not control the voltage sequencing, the circuit of Figure 27 can be added to meet these requirements. The MUR420 diodes of Figure 27 control the maximum potential difference between the 3.3 bus and internal voltages on power-up and the 1N5820 Schottky diodes regulate the maximum potential difference on power-down. 38 PC107A 2137A-HIREL-06/02 PC107A Figure 27. Example Voltage Sequencing Circuits + 5V Source 5V + 3.3V Source 3.3V + 2.5V Source 2.5V 3.3V 2.5V MUR420 MUR420 IN5820 IN5820 Decoupling Recommendations Due to the PC107A's dynamic power management feature, large address and data buses, and high operating frequencies, the PC107A can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC107A system, and the PC107A itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each V DD , OV DD , GV DD , and LV DD pin of the PC107A. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, BVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors-100 - 330 F (AVX TPS tantalum or Sanyo OSCON). Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD, BVDD, and GND pins of the PC107A. The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of the PC107A. The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the SDRAM_SYNC_IN input of the PC107A. The trace length may be used to skew or adjust the timing window as needed. See Motorola application note "AN1794/D" for more information on this topic. The TRST signal must be asserted during reset to ensure proper initialization and operation of the PC107A. It is recommended that the TRST signal be connected to the system HRESET signal or pulled down with a 100 - 1 k resistor. 39 2137A-HIREL-06/02 Pull-up/Pull-down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The processor data bus signals are: DH[0-31], DL[0-31], and PAR[0-7]. The memory data bus signals are: MDH[0-31], MDL[0-31], and PAR/AR[0-7]. If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0-31], DP[4-7], MDL[0-31], and PAR[4-7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. It is recommended that ARTRY, TA, and TS have weak pull-up resistors (2 k - 10 k) connected to BVDD. It is recommended that MTP[1-2] and TEST2 have weak pull-up resistor (2 k - 10 k) connected to GVDD. It is recommended that the following signals be pulled up to OVDD with weak pull-up resistors (2 k - 10 k): SDA, SCL, TEST1, and FTP[3-3]. It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors (2 k - 10 k): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, TRDY and INTA. The resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. The following pins have internal pull-up resistors enabled at all times: REQ[06-4], TCK, TDI, TMS, and TRST, BR1, HRESET_CPU, MCP, QACK, SRESET, TEST and TRIG_OUT. See Table 1, "PC107A Pinout Listing," on page 5 for more information. The following pins have internal pull-up resistors enabled only while device is in the reset state: MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, SDBAO, and SDMA[10-1]. See Table 1, "PC107A Pinout Listing," on page 5 for more information. The following pins are reset configuration pins: MDL0, FOE, RCS0, SDBAO, SDMA[10- 1], and PLL_CFG[0-3]. These pins are sampled during reset to configure the device. Any other unused active low input pins should be tied to a logic one level via weak pullup resistors (2 k - 10 k) to the appropriate power supply listed in Table 3 on page 12. Unused active high input pins should be tied to GND via weak pull-down resistors (2 k- 10 k). 40 PC107A 2137A-HIREL-06/02 PC107A Definitions Datasheet Status Description Table 20. Datasheet Status Datasheet Status Validity Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. Before design phase Target specification This datasheet contains target or goal specifications for product development. Valid during the design phase Preliminary specification -site This datasheet contains preliminary data. Additional data may be published later; could include simulation results. Valid before characterization phase Preliminary specification -site This datasheet contains also characterization results. Valid before the industrialization phase Product specification This datasheet contains final product specification. Valid for production purposes Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 41 2137A-HIREL-06/02 Differences with Commercial Part Table 21. Differences with Commercial Part Temperature range Commercial Part Military Part Tj = 0 to 105C Tj = -55 to 125C Ordering Information PC107A M ZF U 100 L (C) Revision Level(1) B C Type (PCX107A if prototype) Bus divider (to be confirmed) L: Any valid PLL configuration Temperature Range: Tj M: -55C, +125C V: -40C, +110C Package ZF: FC-PBGA(2) Operating Frequency 100: 100 MHz Screening Level(1) U: Upscreening Test Notes: 42 1. For availability of the different versions, contact your ATMEL sale office. 2. FC-PBGA = PBGA with Flip Chip Assembly process. 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